aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mn10300/include/asm/reset-regs.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mn10300/include/asm/reset-regs.h')
-rw-r--r--arch/mn10300/include/asm/reset-regs.h64
1 files changed, 64 insertions, 0 deletions
diff --git a/arch/mn10300/include/asm/reset-regs.h b/arch/mn10300/include/asm/reset-regs.h
new file mode 100644
index 000000000000..174523d50132
--- /dev/null
+++ b/arch/mn10300/include/asm/reset-regs.h
@@ -0,0 +1,64 @@
1/* MN10300 Reset controller and watchdog timer definitions
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11
12#ifndef _ASM_RESET_REGS_H
13#define _ASM_RESET_REGS_H
14
15#include <asm/cpu-regs.h>
16#include <asm/exceptions.h>
17
18#ifdef __KERNEL__
19
20#ifdef CONFIG_MN10300_WD_TIMER
21#define ARCH_HAS_NMI_WATCHDOG /* See include/linux/nmi.h */
22#endif
23
24/*
25 * watchdog timer registers
26 */
27#define WDBC __SYSREGC(0xc0001000, u8) /* watchdog binary counter reg */
28
29#define WDCTR __SYSREG(0xc0001002, u8) /* watchdog timer control reg */
30#define WDCTR_WDCK 0x07 /* clock source selection */
31#define WDCTR_WDCK_256th 0x00 /* - OSCI/256 */
32#define WDCTR_WDCK_1024th 0x01 /* - OSCI/1024 */
33#define WDCTR_WDCK_2048th 0x02 /* - OSCI/2048 */
34#define WDCTR_WDCK_16384th 0x03 /* - OSCI/16384 */
35#define WDCTR_WDCK_65536th 0x04 /* - OSCI/65536 */
36#define WDCTR_WDRST 0x40 /* binary counter reset */
37#define WDCTR_WDCNE 0x80 /* watchdog timer enable */
38
39#define RSTCTR __SYSREG(0xc0001004, u8) /* reset control reg */
40#define RSTCTR_CHIPRST 0x01 /* chip reset */
41#define RSTCTR_DBFRST 0x02 /* double fault reset flag */
42#define RSTCTR_WDTRST 0x04 /* watchdog timer reset flag */
43#define RSTCTR_WDREN 0x08 /* watchdog timer reset enable */
44
45#ifndef __ASSEMBLY__
46
47static inline void mn10300_proc_hard_reset(void)
48{
49 RSTCTR &= ~RSTCTR_CHIPRST;
50 RSTCTR |= RSTCTR_CHIPRST;
51}
52
53extern unsigned int watchdog_alert_counter;
54
55extern void watchdog_go(void);
56extern asmlinkage void watchdog_handler(void);
57extern asmlinkage
58void watchdog_interrupt(struct pt_regs *, enum exception_code);
59
60#endif
61
62#endif /* __KERNEL__ */
63
64#endif /* _ASM_RESET_REGS_H */