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Diffstat (limited to 'arch/mn10300/include/asm/cache.h')
-rw-r--r-- | arch/mn10300/include/asm/cache.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/mn10300/include/asm/cache.h b/arch/mn10300/include/asm/cache.h new file mode 100644 index 000000000000..e03cfa2e997e --- /dev/null +++ b/arch/mn10300/include/asm/cache.h | |||
@@ -0,0 +1,54 @@ | |||
1 | /* MN10300 cache management registers | ||
2 | * | ||
3 | * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. | ||
4 | * Written by David Howells (dhowells@redhat.com) | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public Licence | ||
8 | * as published by the Free Software Foundation; either version | ||
9 | * 2 of the Licence, or (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | #ifndef _ASM_CACHE_H | ||
13 | #define _ASM_CACHE_H | ||
14 | |||
15 | #include <asm/cpu-regs.h> | ||
16 | #include <proc/cache.h> | ||
17 | |||
18 | #ifndef __ASSEMBLY__ | ||
19 | #define L1_CACHE_DISPARITY (L1_CACHE_NENTRIES * L1_CACHE_BYTES) | ||
20 | #else | ||
21 | #define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES | ||
22 | #endif | ||
23 | |||
24 | /* data cache purge registers | ||
25 | * - read from the register to unconditionally purge that cache line | ||
26 | * - write address & 0xffffff00 to conditionally purge that cache line | ||
27 | * - clear LSB to request invalidation as well | ||
28 | */ | ||
29 | #define DCACHE_PURGE(WAY, ENTRY) \ | ||
30 | __SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \ | ||
31 | (ENTRY) * L1_CACHE_BYTES, u32) | ||
32 | |||
33 | #define DCACHE_PURGE_WAY0(ENTRY) \ | ||
34 | __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) | ||
35 | #define DCACHE_PURGE_WAY1(ENTRY) \ | ||
36 | __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) | ||
37 | #define DCACHE_PURGE_WAY2(ENTRY) \ | ||
38 | __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) | ||
39 | #define DCACHE_PURGE_WAY3(ENTRY) \ | ||
40 | __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) | ||
41 | |||
42 | /* instruction cache access registers */ | ||
43 | #define ICACHE_DATA(WAY, ENTRY, OFF) \ | ||
44 | __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32) | ||
45 | #define ICACHE_TAG(WAY, ENTRY) \ | ||
46 | __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32) | ||
47 | |||
48 | /* instruction cache access registers */ | ||
49 | #define DCACHE_DATA(WAY, ENTRY, OFF) \ | ||
50 | __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32) | ||
51 | #define DCACHE_TAG(WAY, ENTRY) \ | ||
52 | __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32) | ||
53 | |||
54 | #endif /* _ASM_CACHE_H */ | ||