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-rw-r--r--arch/mips/Kconfig9
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c5
-rw-r--r--arch/mips/bcm63xx/nvram.c7
-rw-r--r--arch/mips/bcm63xx/setup.c2
-rw-r--r--arch/mips/cavium-octeon/setup.c5
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h4
-rw-r--r--arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h4
-rw-r--r--arch/mips/include/asm/mipsregs.h209
-rw-r--r--arch/mips/include/asm/page.h2
-rw-r--r--arch/mips/include/asm/signal.h2
-rw-r--r--arch/mips/include/uapi/asm/signal.h8
-rw-r--r--arch/mips/kernel/Makefile25
-rw-r--r--arch/mips/kernel/cpu-probe.c13
-rw-r--r--arch/mips/kernel/linux32.c2
-rw-r--r--arch/mips/kernel/mcount.S11
-rw-r--r--arch/mips/kernel/proc.c2
-rw-r--r--arch/mips/kernel/traps.c2
-rw-r--r--arch/mips/lib/bitops.c16
-rw-r--r--arch/mips/lib/csum_partial.S4
-rw-r--r--arch/mips/mm/c-r4k.c6
-rw-r--r--arch/mips/mm/sc-mips.c6
-rw-r--r--arch/mips/pci/pci-alchemy.c4
22 files changed, 250 insertions, 98 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ae9c716c46bb..51244bf97271 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -18,7 +18,7 @@ config MIPS
18 select HAVE_KRETPROBES 18 select HAVE_KRETPROBES
19 select HAVE_DEBUG_KMEMLEAK 19 select HAVE_DEBUG_KMEMLEAK
20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE 20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
21 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 21 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
22 select RTC_LIB if !MACH_LOONGSON 22 select RTC_LIB if !MACH_LOONGSON
23 select GENERIC_ATOMIC64 if !64BIT 23 select GENERIC_ATOMIC64 if !64BIT
24 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 24 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
@@ -38,7 +38,7 @@ config MIPS
38 select GENERIC_CLOCKEVENTS 38 select GENERIC_CLOCKEVENTS
39 select GENERIC_CMOS_UPDATE 39 select GENERIC_CMOS_UPDATE
40 select HAVE_MOD_ARCH_SPECIFIC 40 select HAVE_MOD_ARCH_SPECIFIC
41 select HAVE_VIRT_TO_BUS 41 select VIRT_TO_BUS
42 select MODULES_USE_ELF_REL if MODULES 42 select MODULES_USE_ELF_REL if MODULES
43 select MODULES_USE_ELF_RELA if MODULES && 64BIT 43 select MODULES_USE_ELF_RELA if MODULES && 64BIT
44 select CLONE_BACKWARDS 44 select CLONE_BACKWARDS
@@ -657,7 +657,7 @@ config SNI_RM
657 bool "SNI RM200/300/400" 657 bool "SNI RM200/300/400"
658 select FW_ARC if CPU_LITTLE_ENDIAN 658 select FW_ARC if CPU_LITTLE_ENDIAN
659 select FW_ARC32 if CPU_LITTLE_ENDIAN 659 select FW_ARC32 if CPU_LITTLE_ENDIAN
660 select SNIPROM if CPU_BIG_ENDIAN 660 select FW_SNIPROM if CPU_BIG_ENDIAN
661 select ARCH_MAY_HAVE_PC_FDC 661 select ARCH_MAY_HAVE_PC_FDC
662 select BOOT_ELF32 662 select BOOT_ELF32
663 select CEVT_R4K 663 select CEVT_R4K
@@ -1144,7 +1144,7 @@ config DEFAULT_SGI_PARTITION
1144config FW_ARC32 1144config FW_ARC32
1145 bool 1145 bool
1146 1146
1147config SNIPROM 1147config FW_SNIPROM
1148 bool 1148 bool
1149 1149
1150config BOOT_ELF32 1150config BOOT_ELF32
@@ -1493,7 +1493,6 @@ config CPU_XLP
1493 select CPU_SUPPORTS_32BIT_KERNEL 1493 select CPU_SUPPORTS_32BIT_KERNEL
1494 select CPU_SUPPORTS_64BIT_KERNEL 1494 select CPU_SUPPORTS_64BIT_KERNEL
1495 select CPU_SUPPORTS_HIGHMEM 1495 select CPU_SUPPORTS_HIGHMEM
1496 select CPU_HAS_LLSC
1497 select WEAK_ORDERING 1496 select WEAK_ORDERING
1498 select WEAK_REORDERING_BEYOND_LLSC 1497 select WEAK_REORDERING_BEYOND_LLSC
1499 select CPU_HAS_PREFETCH 1498 select CPU_HAS_PREFETCH
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index ed1949c29508..9aa7d44898ed 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -745,10 +745,7 @@ void __init board_prom_init(void)
745 strcpy(cfe_version, "unknown"); 745 strcpy(cfe_version, "unknown");
746 printk(KERN_INFO PFX "CFE version: %s\n", cfe_version); 746 printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
747 747
748 if (bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET)) { 748 bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
749 printk(KERN_ERR PFX "invalid nvram checksum\n");
750 return;
751 }
752 749
753 board_name = bcm63xx_nvram_get_name(); 750 board_name = bcm63xx_nvram_get_name();
754 /* find board by name */ 751 /* find board by name */
diff --git a/arch/mips/bcm63xx/nvram.c b/arch/mips/bcm63xx/nvram.c
index 620611680839..a4b8864f9307 100644
--- a/arch/mips/bcm63xx/nvram.c
+++ b/arch/mips/bcm63xx/nvram.c
@@ -38,7 +38,7 @@ struct bcm963xx_nvram {
38static struct bcm963xx_nvram nvram; 38static struct bcm963xx_nvram nvram;
39static int mac_addr_used; 39static int mac_addr_used;
40 40
41int __init bcm63xx_nvram_init(void *addr) 41void __init bcm63xx_nvram_init(void *addr)
42{ 42{
43 unsigned int check_len; 43 unsigned int check_len;
44 u32 crc, expected_crc; 44 u32 crc, expected_crc;
@@ -60,9 +60,8 @@ int __init bcm63xx_nvram_init(void *addr)
60 crc = crc32_le(~0, (u8 *)&nvram, check_len); 60 crc = crc32_le(~0, (u8 *)&nvram, check_len);
61 61
62 if (crc != expected_crc) 62 if (crc != expected_crc)
63 return -EINVAL; 63 pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n",
64 64 expected_crc, crc);
65 return 0;
66} 65}
67 66
68u8 *bcm63xx_nvram_get_name(void) 67u8 *bcm63xx_nvram_get_name(void)
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 314231be788c..35e18e98beb9 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -157,4 +157,4 @@ int __init bcm63xx_register_devices(void)
157 return board_register_devices(); 157 return board_register_devices();
158} 158}
159 159
160device_initcall(bcm63xx_register_devices); 160arch_initcall(bcm63xx_register_devices);
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index c594a3d4f743..b0baa299f899 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -174,7 +174,10 @@ static int octeon_kexec_prepare(struct kimage *image)
174 174
175static void octeon_generic_shutdown(void) 175static void octeon_generic_shutdown(void)
176{ 176{
177 int cpu, i; 177 int i;
178#ifdef CONFIG_SMP
179 int cpu;
180#endif
178 struct cvmx_bootmem_desc *bootmem_desc; 181 struct cvmx_bootmem_desc *bootmem_desc;
179 void *named_block_array_ptr; 182 void *named_block_array_ptr;
180 183
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
index 62d6a3b4d3b7..4e0b6bc1165e 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
@@ -9,10 +9,8 @@
9 * 9 *
10 * Initialized the local nvram copy from the target address and checks 10 * Initialized the local nvram copy from the target address and checks
11 * its checksum. 11 * its checksum.
12 *
13 * Returns 0 on success.
14 */ 12 */
15int __init bcm63xx_nvram_init(void *nvram); 13void bcm63xx_nvram_init(void *nvram);
16 14
17/** 15/**
18 * bcm63xx_nvram_get_name() - returns the board name according to nvram 16 * bcm63xx_nvram_get_name() - returns the board name according to nvram
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
index d9c828419037..193c0912d38e 100644
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
@@ -28,11 +28,7 @@
28/* #define cpu_has_prefetch ? */ 28/* #define cpu_has_prefetch ? */
29#define cpu_has_mcheck 1 29#define cpu_has_mcheck 1
30/* #define cpu_has_ejtag ? */ 30/* #define cpu_has_ejtag ? */
31#ifdef CONFIG_CPU_HAS_LLSC
32#define cpu_has_llsc 1 31#define cpu_has_llsc 1
33#else
34#define cpu_has_llsc 0
35#endif
36/* #define cpu_has_vtag_icache ? */ 32/* #define cpu_has_vtag_icache ? */
37/* #define cpu_has_dc_aliases ? */ 33/* #define cpu_has_dc_aliases ? */
38/* #define cpu_has_ic_fills_f_dc ? */ 34/* #define cpu_has_ic_fills_f_dc ? */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 12b70c25906a..0da44d422f5b 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1166,7 +1166,10 @@ do { \
1166 unsigned int __dspctl; \ 1166 unsigned int __dspctl; \
1167 \ 1167 \
1168 __asm__ __volatile__( \ 1168 __asm__ __volatile__( \
1169 " .set push \n" \
1170 " .set dsp \n" \
1169 " rddsp %0, %x1 \n" \ 1171 " rddsp %0, %x1 \n" \
1172 " .set pop \n" \
1170 : "=r" (__dspctl) \ 1173 : "=r" (__dspctl) \
1171 : "i" (mask)); \ 1174 : "i" (mask)); \
1172 __dspctl; \ 1175 __dspctl; \
@@ -1175,30 +1178,198 @@ do { \
1175#define wrdsp(val, mask) \ 1178#define wrdsp(val, mask) \
1176do { \ 1179do { \
1177 __asm__ __volatile__( \ 1180 __asm__ __volatile__( \
1181 " .set push \n" \
1182 " .set dsp \n" \
1178 " wrdsp %0, %x1 \n" \ 1183 " wrdsp %0, %x1 \n" \
1184 " .set pop \n" \
1179 : \ 1185 : \
1180 : "r" (val), "i" (mask)); \ 1186 : "r" (val), "i" (mask)); \
1181} while (0) 1187} while (0)
1182 1188
1183#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) 1189#define mflo0() \
1184#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) 1190({ \
1185#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) 1191 long mflo0; \
1186#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) 1192 __asm__( \
1187 1193 " .set push \n" \
1188#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) 1194 " .set dsp \n" \
1189#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) 1195 " mflo %0, $ac0 \n" \
1190#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) 1196 " .set pop \n" \
1191#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) 1197 : "=r" (mflo0)); \
1192 1198 mflo0; \
1193#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) 1199})
1194#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) 1200
1195#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) 1201#define mflo1() \
1196#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) 1202({ \
1197 1203 long mflo1; \
1198#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) 1204 __asm__( \
1199#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) 1205 " .set push \n" \
1200#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) 1206 " .set dsp \n" \
1201#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) 1207 " mflo %0, $ac1 \n" \
1208 " .set pop \n" \
1209 : "=r" (mflo1)); \
1210 mflo1; \
1211})
1212
1213#define mflo2() \
1214({ \
1215 long mflo2; \
1216 __asm__( \
1217 " .set push \n" \
1218 " .set dsp \n" \
1219 " mflo %0, $ac2 \n" \
1220 " .set pop \n" \
1221 : "=r" (mflo2)); \
1222 mflo2; \
1223})
1224
1225#define mflo3() \
1226({ \
1227 long mflo3; \
1228 __asm__( \
1229 " .set push \n" \
1230 " .set dsp \n" \
1231 " mflo %0, $ac3 \n" \
1232 " .set pop \n" \
1233 : "=r" (mflo3)); \
1234 mflo3; \
1235})
1236
1237#define mfhi0() \
1238({ \
1239 long mfhi0; \
1240 __asm__( \
1241 " .set push \n" \
1242 " .set dsp \n" \
1243 " mfhi %0, $ac0 \n" \
1244 " .set pop \n" \
1245 : "=r" (mfhi0)); \
1246 mfhi0; \
1247})
1248
1249#define mfhi1() \
1250({ \
1251 long mfhi1; \
1252 __asm__( \
1253 " .set push \n" \
1254 " .set dsp \n" \
1255 " mfhi %0, $ac1 \n" \
1256 " .set pop \n" \
1257 : "=r" (mfhi1)); \
1258 mfhi1; \
1259})
1260
1261#define mfhi2() \
1262({ \
1263 long mfhi2; \
1264 __asm__( \
1265 " .set push \n" \
1266 " .set dsp \n" \
1267 " mfhi %0, $ac2 \n" \
1268 " .set pop \n" \
1269 : "=r" (mfhi2)); \
1270 mfhi2; \
1271})
1272
1273#define mfhi3() \
1274({ \
1275 long mfhi3; \
1276 __asm__( \
1277 " .set push \n" \
1278 " .set dsp \n" \
1279 " mfhi %0, $ac3 \n" \
1280 " .set pop \n" \
1281 : "=r" (mfhi3)); \
1282 mfhi3; \
1283})
1284
1285
1286#define mtlo0(x) \
1287({ \
1288 __asm__( \
1289 " .set push \n" \
1290 " .set dsp \n" \
1291 " mtlo %0, $ac0 \n" \
1292 " .set pop \n" \
1293 : \
1294 : "r" (x)); \
1295})
1296
1297#define mtlo1(x) \
1298({ \
1299 __asm__( \
1300 " .set push \n" \
1301 " .set dsp \n" \
1302 " mtlo %0, $ac1 \n" \
1303 " .set pop \n" \
1304 : \
1305 : "r" (x)); \
1306})
1307
1308#define mtlo2(x) \
1309({ \
1310 __asm__( \
1311 " .set push \n" \
1312 " .set dsp \n" \
1313 " mtlo %0, $ac2 \n" \
1314 " .set pop \n" \
1315 : \
1316 : "r" (x)); \
1317})
1318
1319#define mtlo3(x) \
1320({ \
1321 __asm__( \
1322 " .set push \n" \
1323 " .set dsp \n" \
1324 " mtlo %0, $ac3 \n" \
1325 " .set pop \n" \
1326 : \
1327 : "r" (x)); \
1328})
1329
1330#define mthi0(x) \
1331({ \
1332 __asm__( \
1333 " .set push \n" \
1334 " .set dsp \n" \
1335 " mthi %0, $ac0 \n" \
1336 " .set pop \n" \
1337 : \
1338 : "r" (x)); \
1339})
1340
1341#define mthi1(x) \
1342({ \
1343 __asm__( \
1344 " .set push \n" \
1345 " .set dsp \n" \
1346 " mthi %0, $ac1 \n" \
1347 " .set pop \n" \
1348 : \
1349 : "r" (x)); \
1350})
1351
1352#define mthi2(x) \
1353({ \
1354 __asm__( \
1355 " .set push \n" \
1356 " .set dsp \n" \
1357 " mthi %0, $ac2 \n" \
1358 " .set pop \n" \
1359 : \
1360 : "r" (x)); \
1361})
1362
1363#define mthi3(x) \
1364({ \
1365 __asm__( \
1366 " .set push \n" \
1367 " .set dsp \n" \
1368 " mthi %0, $ac3 \n" \
1369 " .set pop \n" \
1370 : \
1371 : "r" (x)); \
1372})
1202 1373
1203#else 1374#else
1204 1375
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 99fc547af9d3..eab99e536b5c 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -31,7 +31,7 @@
31#define PAGE_SHIFT 16 31#define PAGE_SHIFT 16
32#endif 32#endif
33#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) 33#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
34#define PAGE_MASK (~(PAGE_SIZE - 1)) 34#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
35 35
36#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 36#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
37#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3) 37#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
diff --git a/arch/mips/include/asm/signal.h b/arch/mips/include/asm/signal.h
index 197f6367c201..8efe5a9e2c3e 100644
--- a/arch/mips/include/asm/signal.h
+++ b/arch/mips/include/asm/signal.h
@@ -21,6 +21,6 @@
21#include <asm/sigcontext.h> 21#include <asm/sigcontext.h>
22#include <asm/siginfo.h> 22#include <asm/siginfo.h>
23 23
24#define __ARCH_HAS_ODD_SIGACTION 24#define __ARCH_HAS_IRIX_SIGACTION
25 25
26#endif /* _ASM_SIGNAL_H */ 26#endif /* _ASM_SIGNAL_H */
diff --git a/arch/mips/include/uapi/asm/signal.h b/arch/mips/include/uapi/asm/signal.h
index d6b18b4d0f3a..addb9f556b71 100644
--- a/arch/mips/include/uapi/asm/signal.h
+++ b/arch/mips/include/uapi/asm/signal.h
@@ -72,6 +72,12 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */
72 * 72 *
73 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single 73 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
74 * Unix names RESETHAND and NODEFER respectively. 74 * Unix names RESETHAND and NODEFER respectively.
75 *
76 * SA_RESTORER used to be defined as 0x04000000 but only the O32 ABI ever
77 * supported its use and no libc was using it, so the entire sa-restorer
78 * functionality was removed with lmo commit 39bffc12c3580ab for 2.5.48
79 * retaining only the SA_RESTORER definition as a reminder to avoid
80 * accidental reuse of the mask bit.
75 */ 81 */
76#define SA_ONSTACK 0x08000000 82#define SA_ONSTACK 0x08000000
77#define SA_RESETHAND 0x80000000 83#define SA_RESETHAND 0x80000000
@@ -84,8 +90,6 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */
84#define SA_NOMASK SA_NODEFER 90#define SA_NOMASK SA_NODEFER
85#define SA_ONESHOT SA_RESETHAND 91#define SA_ONESHOT SA_RESETHAND
86 92
87#define SA_RESTORER 0x04000000 /* Only for o32 */
88
89#define MINSIGSTKSZ 2048 93#define MINSIGSTKSZ 2048
90#define SIGSTKSZ 8192 94#define SIGSTKSZ 8192
91 95
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index f81d98f6184c..de75fb50562b 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -100,29 +100,16 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
100obj-$(CONFIG_JUMP_LABEL) += jump_label.o 100obj-$(CONFIG_JUMP_LABEL) += jump_label.o
101 101
102# 102#
103# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe 103# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
104# to enable DSP assembler support here even if the MIPS Release 2 CPU we 104# safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches
105# are targetting does not support DSP because all code-paths making use of 105# here because the compiler may use DSP ASE instructions (such as lwx) in
106# it properly check that the running CPU *actually does* support these 106# code paths where we cannot check that the CPU we are running on supports it.
107# instructions. 107# Proper abstraction using HAVE_AS_DSP and macros is done in
108# arch/mips/include/asm/mipsregs.h.
108# 109#
109ifeq ($(CONFIG_CPU_MIPSR2), y) 110ifeq ($(CONFIG_CPU_MIPSR2), y)
110CFLAGS_DSP = -DHAVE_AS_DSP 111CFLAGS_DSP = -DHAVE_AS_DSP
111 112
112#
113# Check if assembler supports DSP ASE
114#
115ifeq ($(call cc-option-yn,-mdsp), y)
116CFLAGS_DSP += -mdsp
117endif
118
119#
120# Check if assembler supports DSP ASE Rev2
121#
122ifeq ($(call cc-option-yn,-mdspr2), y)
123CFLAGS_DSP += -mdspr2
124endif
125
126CFLAGS_signal.o = $(CFLAGS_DSP) 113CFLAGS_signal.o = $(CFLAGS_DSP)
127CFLAGS_signal32.o = $(CFLAGS_DSP) 114CFLAGS_signal32.o = $(CFLAGS_DSP)
128CFLAGS_process.o = $(CFLAGS_DSP) 115CFLAGS_process.o = $(CFLAGS_DSP)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 6bfccc227a95..5fe66a0c3224 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -580,6 +580,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
580 c->tlbsize = 48; 580 c->tlbsize = 48;
581 break; 581 break;
582 case PRID_IMP_VR41XX: 582 case PRID_IMP_VR41XX:
583 set_isa(c, MIPS_CPU_ISA_III);
584 c->options = R4K_OPTS;
585 c->tlbsize = 32;
583 switch (c->processor_id & 0xf0) { 586 switch (c->processor_id & 0xf0) {
584 case PRID_REV_VR4111: 587 case PRID_REV_VR4111:
585 c->cputype = CPU_VR4111; 588 c->cputype = CPU_VR4111;
@@ -604,6 +607,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
604 __cpu_name[cpu] = "NEC VR4131"; 607 __cpu_name[cpu] = "NEC VR4131";
605 } else { 608 } else {
606 c->cputype = CPU_VR4133; 609 c->cputype = CPU_VR4133;
610 c->options |= MIPS_CPU_LLSC;
607 __cpu_name[cpu] = "NEC VR4133"; 611 __cpu_name[cpu] = "NEC VR4133";
608 } 612 }
609 break; 613 break;
@@ -613,9 +617,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
613 __cpu_name[cpu] = "NEC Vr41xx"; 617 __cpu_name[cpu] = "NEC Vr41xx";
614 break; 618 break;
615 } 619 }
616 set_isa(c, MIPS_CPU_ISA_III);
617 c->options = R4K_OPTS;
618 c->tlbsize = 32;
619 break; 620 break;
620 case PRID_IMP_R4300: 621 case PRID_IMP_R4300:
621 c->cputype = CPU_R4300; 622 c->cputype = CPU_R4300;
@@ -1226,10 +1227,8 @@ __cpuinit void cpu_probe(void)
1226 if (c->options & MIPS_CPU_FPU) { 1227 if (c->options & MIPS_CPU_FPU) {
1227 c->fpu_id = cpu_get_fpu_id(); 1228 c->fpu_id = cpu_get_fpu_id();
1228 1229
1229 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1230 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1230 c->isa_level == MIPS_CPU_ISA_M32R2 || 1231 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1231 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1232 c->isa_level == MIPS_CPU_ISA_M64R2) {
1233 if (c->fpu_id & MIPS_FPIR_3D) 1232 if (c->fpu_id & MIPS_FPIR_3D)
1234 c->ases |= MIPS_ASE_MIPS3D; 1233 c->ases |= MIPS_ASE_MIPS3D;
1235 } 1234 }
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 8eeee1c860c0..db9655f08892 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -171,7 +171,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
171 err = compat_sys_shmctl(first, second, compat_ptr(ptr)); 171 err = compat_sys_shmctl(first, second, compat_ptr(ptr));
172 break; 172 break;
173 default: 173 default:
174 err = -EINVAL; 174 err = -ENOSYS;
175 break; 175 break;
176 } 176 }
177 177
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index 165867673357..33d067148e61 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -46,10 +46,9 @@
46 PTR_L a5, PT_R9(sp) 46 PTR_L a5, PT_R9(sp)
47 PTR_L a6, PT_R10(sp) 47 PTR_L a6, PT_R10(sp)
48 PTR_L a7, PT_R11(sp) 48 PTR_L a7, PT_R11(sp)
49#else
50 PTR_ADDIU sp, PT_SIZE
51#endif 49#endif
52.endm 50 PTR_ADDIU sp, PT_SIZE
51 .endm
53 52
54 .macro RETURN_BACK 53 .macro RETURN_BACK
55 jr ra 54 jr ra
@@ -68,7 +67,11 @@ NESTED(ftrace_caller, PT_SIZE, ra)
68 .globl _mcount 67 .globl _mcount
69_mcount: 68_mcount:
70 b ftrace_stub 69 b ftrace_stub
71 addiu sp,sp,8 70#ifdef CONFIG_32BIT
71 addiu sp,sp,8
72#else
73 nop
74#endif
72 75
73 /* When tracing is activated, it calls ftrace_caller+8 (aka here) */ 76 /* When tracing is activated, it calls ftrace_caller+8 (aka here) */
74 lw t1, function_trace_stop 77 lw t1, function_trace_stop
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 135c4aadccbe..7a54f74b7818 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -67,7 +67,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
67 if (cpu_has_mips_r) { 67 if (cpu_has_mips_r) {
68 seq_printf(m, "isa\t\t\t:"); 68 seq_printf(m, "isa\t\t\t:");
69 if (cpu_has_mips_1) 69 if (cpu_has_mips_1)
70 seq_printf(m, "%s", "mips1"); 70 seq_printf(m, "%s", " mips1");
71 if (cpu_has_mips_2) 71 if (cpu_has_mips_2)
72 seq_printf(m, "%s", " mips2"); 72 seq_printf(m, "%s", " mips2");
73 if (cpu_has_mips_3) 73 if (cpu_has_mips_3)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index a200b5bdbb87..c3abb88170fc 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1571,7 +1571,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
1571#ifdef CONFIG_64BIT 1571#ifdef CONFIG_64BIT
1572 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 1572 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1573#endif 1573#endif
1574 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 1574 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
1575 status_set |= ST0_XX; 1575 status_set |= ST0_XX;
1576 if (cpu_has_dsp) 1576 if (cpu_has_dsp)
1577 status_set |= ST0_MX; 1577 status_set |= ST0_MX;
diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c
index 81f1dcfdcab8..a64daee740ee 100644
--- a/arch/mips/lib/bitops.c
+++ b/arch/mips/lib/bitops.c
@@ -90,12 +90,12 @@ int __mips_test_and_set_bit(unsigned long nr,
90 unsigned bit = nr & SZLONG_MASK; 90 unsigned bit = nr & SZLONG_MASK;
91 unsigned long mask; 91 unsigned long mask;
92 unsigned long flags; 92 unsigned long flags;
93 unsigned long res; 93 int res;
94 94
95 a += nr >> SZLONG_LOG; 95 a += nr >> SZLONG_LOG;
96 mask = 1UL << bit; 96 mask = 1UL << bit;
97 raw_local_irq_save(flags); 97 raw_local_irq_save(flags);
98 res = (mask & *a); 98 res = (mask & *a) != 0;
99 *a |= mask; 99 *a |= mask;
100 raw_local_irq_restore(flags); 100 raw_local_irq_restore(flags);
101 return res; 101 return res;
@@ -116,12 +116,12 @@ int __mips_test_and_set_bit_lock(unsigned long nr,
116 unsigned bit = nr & SZLONG_MASK; 116 unsigned bit = nr & SZLONG_MASK;
117 unsigned long mask; 117 unsigned long mask;
118 unsigned long flags; 118 unsigned long flags;
119 unsigned long res; 119 int res;
120 120
121 a += nr >> SZLONG_LOG; 121 a += nr >> SZLONG_LOG;
122 mask = 1UL << bit; 122 mask = 1UL << bit;
123 raw_local_irq_save(flags); 123 raw_local_irq_save(flags);
124 res = (mask & *a); 124 res = (mask & *a) != 0;
125 *a |= mask; 125 *a |= mask;
126 raw_local_irq_restore(flags); 126 raw_local_irq_restore(flags);
127 return res; 127 return res;
@@ -141,12 +141,12 @@ int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
141 unsigned bit = nr & SZLONG_MASK; 141 unsigned bit = nr & SZLONG_MASK;
142 unsigned long mask; 142 unsigned long mask;
143 unsigned long flags; 143 unsigned long flags;
144 unsigned long res; 144 int res;
145 145
146 a += nr >> SZLONG_LOG; 146 a += nr >> SZLONG_LOG;
147 mask = 1UL << bit; 147 mask = 1UL << bit;
148 raw_local_irq_save(flags); 148 raw_local_irq_save(flags);
149 res = (mask & *a); 149 res = (mask & *a) != 0;
150 *a &= ~mask; 150 *a &= ~mask;
151 raw_local_irq_restore(flags); 151 raw_local_irq_restore(flags);
152 return res; 152 return res;
@@ -166,12 +166,12 @@ int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
166 unsigned bit = nr & SZLONG_MASK; 166 unsigned bit = nr & SZLONG_MASK;
167 unsigned long mask; 167 unsigned long mask;
168 unsigned long flags; 168 unsigned long flags;
169 unsigned long res; 169 int res;
170 170
171 a += nr >> SZLONG_LOG; 171 a += nr >> SZLONG_LOG;
172 mask = 1UL << bit; 172 mask = 1UL << bit;
173 raw_local_irq_save(flags); 173 raw_local_irq_save(flags);
174 res = (mask & *a); 174 res = (mask & *a) != 0;
175 *a ^= mask; 175 *a ^= mask;
176 raw_local_irq_restore(flags); 176 raw_local_irq_restore(flags);
177 return res; 177 return res;
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 507147aebd41..a6adffbb4e5f 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -270,7 +270,7 @@ LEAF(csum_partial)
270#endif 270#endif
271 271
272 /* odd buffer alignment? */ 272 /* odd buffer alignment? */
273#ifdef CPU_MIPSR2 273#ifdef CONFIG_CPU_MIPSR2
274 wsbh v1, sum 274 wsbh v1, sum
275 movn sum, v1, t7 275 movn sum, v1, t7
276#else 276#else
@@ -670,7 +670,7 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc)
670 addu sum, v1 670 addu sum, v1
671#endif 671#endif
672 672
673#ifdef CPU_MIPSR2 673#ifdef CONFIG_CPU_MIPSR2
674 wsbh v1, sum 674 wsbh v1, sum
675 movn sum, v1, odd 675 movn sum, v1, odd
676#else 676#else
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index ecca559b8d7b..2078915eacb9 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void)
1247 return; 1247 return;
1248 1248
1249 default: 1249 default:
1250 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1250 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1251 c->isa_level == MIPS_CPU_ISA_M32R2 || 1251 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1252 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1253 c->isa_level == MIPS_CPU_ISA_M64R2) {
1254#ifdef CONFIG_MIPS_CPU_SCACHE 1252#ifdef CONFIG_MIPS_CPU_SCACHE
1255 if (mips_sc_init ()) { 1253 if (mips_sc_init ()) {
1256 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; 1254 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 93d937b4b1ba..df96da7e939b 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void)
98 c->scache.flags |= MIPS_CACHE_NOT_PRESENT; 98 c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
99 99
100 /* Ignore anything but MIPSxx processors */ 100 /* Ignore anything but MIPSxx processors */
101 if (c->isa_level != MIPS_CPU_ISA_M32R1 && 101 if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
102 c->isa_level != MIPS_CPU_ISA_M32R2 && 102 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
103 c->isa_level != MIPS_CPU_ISA_M64R1 &&
104 c->isa_level != MIPS_CPU_ISA_M64R2)
105 return 0; 103 return 0;
106 104
107 /* Does this MIPS32/MIPS64 CPU have a config2 register? */ 105 /* Does this MIPS32/MIPS64 CPU have a config2 register? */
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index 38a80c83fd67..d1faece21b6a 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -19,7 +19,7 @@
19#include <asm/mach-au1x00/au1000.h> 19#include <asm/mach-au1x00/au1000.h>
20#include <asm/tlbmisc.h> 20#include <asm/tlbmisc.h>
21 21
22#ifdef CONFIG_DEBUG_PCI 22#ifdef CONFIG_PCI_DEBUG
23#define DBG(x...) printk(KERN_DEBUG x) 23#define DBG(x...) printk(KERN_DEBUG x)
24#else 24#else
25#define DBG(x...) do {} while (0) 25#define DBG(x...) do {} while (0)
@@ -162,7 +162,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
162 if (status & (1 << 29)) { 162 if (status & (1 << 29)) {
163 *data = 0xffffffff; 163 *data = 0xffffffff;
164 error = -1; 164 error = -1;
165 DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d", 165 DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n",
166 access_type, bus->number, device); 166 access_type, bus->number, device);
167 } else if ((status >> 28) & 0xf) { 167 } else if ((status >> 28) & 0xf) {
168 DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n", 168 DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 07:41:07 -0500