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-rw-r--r--arch/mips/Kconfig28
-rw-r--r--arch/mips/au1000/Kconfig1
-rw-r--r--arch/mips/au1000/pb1200/irqmap.c2
-rw-r--r--arch/mips/basler/excite/excite_irq.c2
-rw-r--r--arch/mips/bcm47xx/time.c7
-rw-r--r--arch/mips/configs/ip27_defconfig1
-rw-r--r--arch/mips/configs/mipssim_defconfig532
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig1
-rw-r--r--arch/mips/emma2rh/markeins/setup.c6
-rw-r--r--arch/mips/jazz/irq.c6
-rw-r--r--arch/mips/jazz/setup.c8
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c66
-rw-r--r--arch/mips/kernel/Makefile2
-rw-r--r--arch/mips/kernel/cevt-r4k.c273
-rw-r--r--arch/mips/kernel/head.S16
-rw-r--r--arch/mips/kernel/irixelf.c4
-rw-r--r--arch/mips/kernel/irixsig.c2
-rw-r--r--arch/mips/kernel/module.c2
-rw-r--r--arch/mips/kernel/sysirix.c4
-rw-r--r--arch/mips/kernel/time.c348
-rw-r--r--arch/mips/kernel/traps.c13
-rw-r--r--arch/mips/lemote/lm2e/setup.c5
-rw-r--r--arch/mips/mm/fault.c2
-rw-r--r--arch/mips/oprofile/Kconfig23
-rw-r--r--arch/mips/pci/pci-excite.c2
-rw-r--r--arch/mips/pmc-sierra/Kconfig2
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_time.c3
-rw-r--r--arch/mips/pmc-sierra/yosemite/setup.c5
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c5
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c155
-rw-r--r--arch/mips/sgi-ip32/ip32-setup.c6
-rw-r--r--arch/mips/sibyte/bcm1480/smp.c5
-rw-r--r--arch/mips/sibyte/bcm1480/time.c74
-rw-r--r--arch/mips/sibyte/sb1250/irq.c36
-rw-r--r--arch/mips/sibyte/sb1250/smp.c5
-rw-r--r--arch/mips/sibyte/sb1250/time.c104
-rw-r--r--arch/mips/sibyte/swarm/setup.c25
-rw-r--r--arch/mips/sni/pcimt.c2
-rw-r--r--arch/mips/sni/time.c18
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c16
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c10
-rw-r--r--arch/mips/tx4938/common/setup.c7
-rw-r--r--arch/mips/vr41xx/Kconfig6
-rw-r--r--arch/mips/vr41xx/common/init.c5
44 files changed, 732 insertions, 1113 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 235d4514e0a9..3ecff5e9e4f3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -21,6 +21,7 @@ config MACH_ALCHEMY
21 21
22config BASLER_EXCITE 22config BASLER_EXCITE
23 bool "Basler eXcite smart camera" 23 bool "Basler eXcite smart camera"
24 select CEVT_R4K
24 select DMA_COHERENT 25 select DMA_COHERENT
25 select HW_HAS_PCI 26 select HW_HAS_PCI
26 select IRQ_CPU 27 select IRQ_CPU
@@ -47,6 +48,7 @@ config BASLER_EXCITE_PROTOTYPE
47 48
48config BCM47XX 49config BCM47XX
49 bool "BCM47XX based boards" 50 bool "BCM47XX based boards"
51 select CEVT_R4K
50 select DMA_NONCOHERENT 52 select DMA_NONCOHERENT
51 select HW_HAS_PCI 53 select HW_HAS_PCI
52 select IRQ_CPU 54 select IRQ_CPU
@@ -63,6 +65,7 @@ config BCM47XX
63 65
64config MIPS_COBALT 66config MIPS_COBALT
65 bool "Cobalt Server" 67 bool "Cobalt Server"
68 select CEVT_R4K
66 select DMA_NONCOHERENT 69 select DMA_NONCOHERENT
67 select HW_HAS_PCI 70 select HW_HAS_PCI
68 select I8253 71 select I8253
@@ -80,6 +83,7 @@ config MIPS_COBALT
80config MACH_DECSTATION 83config MACH_DECSTATION
81 bool "DECstations" 84 bool "DECstations"
82 select BOOT_ELF32 85 select BOOT_ELF32
86 select CEVT_R4K
83 select DMA_NONCOHERENT 87 select DMA_NONCOHERENT
84 select NO_IOPORT 88 select NO_IOPORT
85 select IRQ_CPU 89 select IRQ_CPU
@@ -111,6 +115,7 @@ config MACH_JAZZ
111 select ARC 115 select ARC
112 select ARC32 116 select ARC32
113 select ARCH_MAY_HAVE_PC_FDC 117 select ARCH_MAY_HAVE_PC_FDC
118 select CEVT_R4K
114 select GENERIC_ISA_DMA 119 select GENERIC_ISA_DMA
115 select IRQ_CPU 120 select IRQ_CPU
116 select I8253 121 select I8253
@@ -130,6 +135,7 @@ config MACH_JAZZ
130 135
131config LASAT 136config LASAT
132 bool "LASAT Networks platforms" 137 bool "LASAT Networks platforms"
138 select CEVT_R4K
133 select DMA_NONCOHERENT 139 select DMA_NONCOHERENT
134 select SYS_HAS_EARLY_PRINTK 140 select SYS_HAS_EARLY_PRINTK
135 select HW_HAS_PCI 141 select HW_HAS_PCI
@@ -146,6 +152,7 @@ config LASAT
146config LEMOTE_FULONG 152config LEMOTE_FULONG
147 bool "Lemote Fulong mini-PC" 153 bool "Lemote Fulong mini-PC"
148 select ARCH_SPARSEMEM_ENABLE 154 select ARCH_SPARSEMEM_ENABLE
155 select CEVT_R4K
149 select SYS_HAS_CPU_LOONGSON2 156 select SYS_HAS_CPU_LOONGSON2
150 select DMA_NONCOHERENT 157 select DMA_NONCOHERENT
151 select BOOT_ELF32 158 select BOOT_ELF32
@@ -170,6 +177,7 @@ config LEMOTE_FULONG
170config MIPS_ATLAS 177config MIPS_ATLAS
171 bool "MIPS Atlas board" 178 bool "MIPS Atlas board"
172 select BOOT_ELF32 179 select BOOT_ELF32
180 select CEVT_R4K
173 select DMA_NONCOHERENT 181 select DMA_NONCOHERENT
174 select SYS_HAS_EARLY_PRINTK 182 select SYS_HAS_EARLY_PRINTK
175 select IRQ_CPU 183 select IRQ_CPU
@@ -200,6 +208,7 @@ config MIPS_MALTA
200 bool "MIPS Malta board" 208 bool "MIPS Malta board"
201 select ARCH_MAY_HAVE_PC_FDC 209 select ARCH_MAY_HAVE_PC_FDC
202 select BOOT_ELF32 210 select BOOT_ELF32
211 select CEVT_R4K
203 select DMA_NONCOHERENT 212 select DMA_NONCOHERENT
204 select GENERIC_ISA_DMA 213 select GENERIC_ISA_DMA
205 select IRQ_CPU 214 select IRQ_CPU
@@ -230,6 +239,7 @@ config MIPS_MALTA
230 239
231config MIPS_SEAD 240config MIPS_SEAD
232 bool "MIPS SEAD board" 241 bool "MIPS SEAD board"
242 select CEVT_R4K
233 select IRQ_CPU 243 select IRQ_CPU
234 select DMA_NONCOHERENT 244 select DMA_NONCOHERENT
235 select SYS_HAS_EARLY_PRINTK 245 select SYS_HAS_EARLY_PRINTK
@@ -248,6 +258,7 @@ config MIPS_SEAD
248 258
249config MIPS_SIM 259config MIPS_SIM
250 bool 'MIPS simulator (MIPSsim)' 260 bool 'MIPS simulator (MIPSsim)'
261 select CEVT_R4K
251 select DMA_NONCOHERENT 262 select DMA_NONCOHERENT
252 select SYS_HAS_EARLY_PRINTK 263 select SYS_HAS_EARLY_PRINTK
253 select IRQ_CPU 264 select IRQ_CPU
@@ -265,6 +276,7 @@ config MIPS_SIM
265 276
266config MARKEINS 277config MARKEINS
267 bool "NEC EMMA2RH Mark-eins" 278 bool "NEC EMMA2RH Mark-eins"
279 select CEVT_R4K
268 select DMA_NONCOHERENT 280 select DMA_NONCOHERENT
269 select HW_HAS_PCI 281 select HW_HAS_PCI
270 select IRQ_CPU 282 select IRQ_CPU
@@ -279,6 +291,7 @@ config MARKEINS
279 291
280config MACH_VR41XX 292config MACH_VR41XX
281 bool "NEC VR4100 series based machines" 293 bool "NEC VR4100 series based machines"
294 select CEVT_R4K
282 select SYS_HAS_CPU_VR41XX 295 select SYS_HAS_CPU_VR41XX
283 select GENERIC_HARDIRQS_NO__DO_IRQ 296 select GENERIC_HARDIRQS_NO__DO_IRQ
284 297
@@ -315,6 +328,7 @@ config PMC_MSP
315 328
316config PMC_YOSEMITE 329config PMC_YOSEMITE
317 bool "PMC-Sierra Yosemite eval board" 330 bool "PMC-Sierra Yosemite eval board"
331 select CEVT_R4K
318 select DMA_COHERENT 332 select DMA_COHERENT
319 select HW_HAS_PCI 333 select HW_HAS_PCI
320 select IRQ_CPU 334 select IRQ_CPU
@@ -335,6 +349,7 @@ config PMC_YOSEMITE
335 349
336config QEMU 350config QEMU
337 bool "Qemu" 351 bool "Qemu"
352 select CEVT_R4K
338 select DMA_COHERENT 353 select DMA_COHERENT
339 select GENERIC_ISA_DMA 354 select GENERIC_ISA_DMA
340 select HAVE_STD_PC_SERIAL_PORT 355 select HAVE_STD_PC_SERIAL_PORT
@@ -365,6 +380,7 @@ config SGI_IP22
365 select ARC 380 select ARC
366 select ARC32 381 select ARC32
367 select BOOT_ELF32 382 select BOOT_ELF32
383 select CEVT_R4K
368 select DMA_NONCOHERENT 384 select DMA_NONCOHERENT
369 select HW_HAS_EISA 385 select HW_HAS_EISA
370 select I8253 386 select I8253
@@ -409,6 +425,7 @@ config SGI_IP32
409 select ARC 425 select ARC
410 select ARC32 426 select ARC32
411 select BOOT_ELF32 427 select BOOT_ELF32
428 select CEVT_R4K
412 select DMA_NONCOHERENT 429 select DMA_NONCOHERENT
413 select HW_HAS_PCI 430 select HW_HAS_PCI
414 select IRQ_CPU 431 select IRQ_CPU
@@ -536,6 +553,7 @@ config SNI_RM
536 select ARC32 if CPU_LITTLE_ENDIAN 553 select ARC32 if CPU_LITTLE_ENDIAN
537 select ARCH_MAY_HAVE_PC_FDC 554 select ARCH_MAY_HAVE_PC_FDC
538 select BOOT_ELF32 555 select BOOT_ELF32
556 select CEVT_R4K
539 select DMA_NONCOHERENT 557 select DMA_NONCOHERENT
540 select GENERIC_ISA_DMA 558 select GENERIC_ISA_DMA
541 select HW_HAS_EISA 559 select HW_HAS_EISA
@@ -577,6 +595,7 @@ config TOSHIBA_JMR3927
577 595
578config TOSHIBA_RBTX4927 596config TOSHIBA_RBTX4927
579 bool "Toshiba RBTX49[23]7 board" 597 bool "Toshiba RBTX49[23]7 board"
598 select CEVT_R4K
580 select DMA_NONCOHERENT 599 select DMA_NONCOHERENT
581 select HAS_TXX9_SERIAL 600 select HAS_TXX9_SERIAL
582 select HW_HAS_PCI 601 select HW_HAS_PCI
@@ -597,6 +616,7 @@ config TOSHIBA_RBTX4927
597 616
598config TOSHIBA_RBTX4938 617config TOSHIBA_RBTX4938
599 bool "Toshiba RBTX4938 board" 618 bool "Toshiba RBTX4938 board"
619 select CEVT_R4K
600 select DMA_NONCOHERENT 620 select DMA_NONCOHERENT
601 select HAS_TXX9_SERIAL 621 select HAS_TXX9_SERIAL
602 select HW_HAS_PCI 622 select HW_HAS_PCI
@@ -616,6 +636,7 @@ config TOSHIBA_RBTX4938
616 636
617config WR_PPMC 637config WR_PPMC
618 bool "Wind River PPMC board" 638 bool "Wind River PPMC board"
639 select CEVT_R4K
619 select IRQ_CPU 640 select IRQ_CPU
620 select BOOT_ELF32 641 select BOOT_ELF32
621 select DMA_NONCOHERENT 642 select DMA_NONCOHERENT
@@ -708,6 +729,9 @@ config ARCH_MAY_HAVE_PC_FDC
708config BOOT_RAW 729config BOOT_RAW
709 bool 730 bool
710 731
732config CEVT_R4K
733 bool
734
711config CFE 735config CFE
712 bool 736 bool
713 737
@@ -1788,7 +1812,7 @@ config KEXEC
1788 but it is independent of the system firmware. And like a reboot 1812 but it is independent of the system firmware. And like a reboot
1789 you can start any kernel with it, not just Linux. 1813 you can start any kernel with it, not just Linux.
1790 1814
1791 The name comes from the similiarity to the exec system call. 1815 The name comes from the similarity to the exec system call.
1792 1816
1793 It is an ongoing process to be certain the hardware in a machine 1817 It is an ongoing process to be certain the hardware in a machine
1794 is properly shutdown, so do not be surprised if this code does not 1818 is properly shutdown, so do not be surprised if this code does not
@@ -1981,7 +2005,7 @@ source "drivers/Kconfig"
1981 2005
1982source "fs/Kconfig" 2006source "fs/Kconfig"
1983 2007
1984source "arch/mips/oprofile/Kconfig" 2008source "kernel/Kconfig.instrumentation"
1985 2009
1986source "arch/mips/Kconfig.debug" 2010source "arch/mips/Kconfig.debug"
1987 2011
diff --git a/arch/mips/au1000/Kconfig b/arch/mips/au1000/Kconfig
index a23d4154da01..b36cec58a9a8 100644
--- a/arch/mips/au1000/Kconfig
+++ b/arch/mips/au1000/Kconfig
@@ -137,6 +137,7 @@ config SOC_AU1200
137config SOC_AU1X00 137config SOC_AU1X00
138 bool 138 bool
139 select 64BIT_PHYS_ADDR 139 select 64BIT_PHYS_ADDR
140 select CEVT_R4K
140 select IRQ_CPU 141 select IRQ_CPU
141 select SYS_HAS_CPU_MIPS32_R1 142 select SYS_HAS_CPU_MIPS32_R1
142 select SYS_SUPPORTS_32BIT_KERNEL 143 select SYS_SUPPORTS_32BIT_KERNEL
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
index 5f48b0603796..bdf00e2a35e4 100644
--- a/arch/mips/au1000/pb1200/irqmap.c
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -36,8 +36,8 @@
36#include <linux/slab.h> 36#include <linux/slab.h>
37#include <linux/random.h> 37#include <linux/random.h>
38#include <linux/delay.h> 38#include <linux/delay.h>
39#include <linux/bitops.h>
39 40
40#include <asm/bitops.h>
41#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
42#include <asm/io.h> 42#include <asm/io.h>
43#include <asm/mipsregs.h> 43#include <asm/mipsregs.h>
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
index 1ecab6350421..4903e067916b 100644
--- a/arch/mips/basler/excite/excite_irq.c
+++ b/arch/mips/basler/excite/excite_irq.c
@@ -29,7 +29,7 @@
29#include <linux/timex.h> 29#include <linux/timex.h>
30#include <linux/slab.h> 30#include <linux/slab.h>
31#include <linux/random.h> 31#include <linux/random.h>
32#include <asm/bitops.h> 32#include <linux/bitops.h>
33#include <asm/bootinfo.h> 33#include <asm/bootinfo.h>
34#include <asm/io.h> 34#include <asm/io.h>
35#include <asm/irq.h> 35#include <asm/irq.h>
diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c
index 0ab4676c8bd3..0c6f47b3fd94 100644
--- a/arch/mips/bcm47xx/time.c
+++ b/arch/mips/bcm47xx/time.c
@@ -46,10 +46,3 @@ void __init plat_time_init(void)
46 /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */ 46 /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
47 mips_hpt_frequency = hz; 47 mips_hpt_frequency = hz;
48} 48}
49
50void __init
51plat_timer_setup(struct irqaction *irq)
52{
53 /* Enable the timer interrupt */
54 setup_irq(7, irq);
55}
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 49bcc58929ba..892d4c38fd0d 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -175,6 +175,7 @@ CONFIG_POSIX_MQUEUE=y
175CONFIG_IKCONFIG=y 175CONFIG_IKCONFIG=y
176CONFIG_IKCONFIG_PROC=y 176CONFIG_IKCONFIG_PROC=y
177CONFIG_LOG_BUF_SHIFT=15 177CONFIG_LOG_BUF_SHIFT=15
178CONFIG_CGROUPS=y
178CONFIG_CPUSETS=y 179CONFIG_CPUSETS=y
179CONFIG_SYSFS_DEPRECATED=y 180CONFIG_SYSFS_DEPRECATED=y
180CONFIG_RELAY=y 181CONFIG_RELAY=y
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
index 86dcb7464353..61b72f5a953e 100644
--- a/arch/mips/configs/mipssim_defconfig
+++ b/arch/mips/configs/mipssim_defconfig
@@ -1,71 +1,68 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.20 3# Linux kernel version: 2.6.23
4# Tue Feb 20 21:47:35 2007 4# Thu Oct 18 22:45:52 2007
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
8# 8#
9# Machine selection 9# Machine selection
10# 10#
11CONFIG_ZONE_DMA=y 11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_MIPS_MTX1 is not set
13# CONFIG_MIPS_BOSPORUS is not set
14# CONFIG_MIPS_PB1000 is not set
15# CONFIG_MIPS_PB1100 is not set
16# CONFIG_MIPS_PB1500 is not set
17# CONFIG_MIPS_PB1550 is not set
18# CONFIG_MIPS_PB1200 is not set
19# CONFIG_MIPS_DB1000 is not set
20# CONFIG_MIPS_DB1100 is not set
21# CONFIG_MIPS_DB1500 is not set
22# CONFIG_MIPS_DB1550 is not set
23# CONFIG_MIPS_DB1200 is not set
24# CONFIG_MIPS_MIRAGE is not set
25# CONFIG_BASLER_EXCITE is not set 12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set
26# CONFIG_MIPS_COBALT is not set 14# CONFIG_MIPS_COBALT is not set
27# CONFIG_MACH_DECSTATION is not set 15# CONFIG_MACH_DECSTATION is not set
28# CONFIG_MACH_JAZZ is not set 16# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set
18# CONFIG_LEMOTE_FULONG is not set
29# CONFIG_MIPS_ATLAS is not set 19# CONFIG_MIPS_ATLAS is not set
30# CONFIG_MIPS_MALTA is not set 20# CONFIG_MIPS_MALTA is not set
31# CONFIG_MIPS_SEAD is not set 21# CONFIG_MIPS_SEAD is not set
32# CONFIG_WR_PPMC is not set
33CONFIG_MIPS_SIM=y 22CONFIG_MIPS_SIM=y
34# CONFIG_MOMENCO_JAGUAR_ATX is not set 23# CONFIG_MARKEINS is not set
35# CONFIG_MIPS_XXS1500 is not set 24# CONFIG_MACH_VR41XX is not set
36# CONFIG_PNX8550_JBS is not set 25# CONFIG_PNX8550_JBS is not set
37# CONFIG_PNX8550_STB810 is not set 26# CONFIG_PNX8550_STB810 is not set
38# CONFIG_MACH_VR41XX is not set 27# CONFIG_PMC_MSP is not set
39# CONFIG_PMC_YOSEMITE is not set 28# CONFIG_PMC_YOSEMITE is not set
40# CONFIG_QEMU is not set 29# CONFIG_QEMU is not set
41# CONFIG_MARKEINS is not set
42# CONFIG_SGI_IP22 is not set 30# CONFIG_SGI_IP22 is not set
43# CONFIG_SGI_IP27 is not set 31# CONFIG_SGI_IP27 is not set
44# CONFIG_SGI_IP32 is not set 32# CONFIG_SGI_IP32 is not set
45# CONFIG_SIBYTE_BIGSUR is not set 33# CONFIG_SIBYTE_CRHINE is not set
34# CONFIG_SIBYTE_CARMEL is not set
35# CONFIG_SIBYTE_CRHONE is not set
36# CONFIG_SIBYTE_RHONE is not set
46# CONFIG_SIBYTE_SWARM is not set 37# CONFIG_SIBYTE_SWARM is not set
38# CONFIG_SIBYTE_LITTLESUR is not set
47# CONFIG_SIBYTE_SENTOSA is not set 39# CONFIG_SIBYTE_SENTOSA is not set
48# CONFIG_SIBYTE_RHONE is not set
49# CONFIG_SIBYTE_CARMEL is not set
50# CONFIG_SIBYTE_PTSWARM is not set 40# CONFIG_SIBYTE_PTSWARM is not set
51# CONFIG_SIBYTE_LITTLESUR is not set 41# CONFIG_SIBYTE_BIGSUR is not set
52# CONFIG_SIBYTE_CRHINE is not set
53# CONFIG_SIBYTE_CRHONE is not set
54# CONFIG_SNI_RM is not set 42# CONFIG_SNI_RM is not set
55# CONFIG_TOSHIBA_JMR3927 is not set 43# CONFIG_TOSHIBA_JMR3927 is not set
56# CONFIG_TOSHIBA_RBTX4927 is not set 44# CONFIG_TOSHIBA_RBTX4927 is not set
57# CONFIG_TOSHIBA_RBTX4938 is not set 45# CONFIG_TOSHIBA_RBTX4938 is not set
46# CONFIG_WR_PPMC is not set
58CONFIG_RWSEM_GENERIC_SPINLOCK=y 47CONFIG_RWSEM_GENERIC_SPINLOCK=y
59# CONFIG_ARCH_HAS_ILOG2_U32 is not set 48# CONFIG_ARCH_HAS_ILOG2_U32 is not set
60# CONFIG_ARCH_HAS_ILOG2_U64 is not set 49# CONFIG_ARCH_HAS_ILOG2_U64 is not set
61CONFIG_GENERIC_FIND_NEXT_BIT=y 50CONFIG_GENERIC_FIND_NEXT_BIT=y
62CONFIG_GENERIC_HWEIGHT=y 51CONFIG_GENERIC_HWEIGHT=y
63CONFIG_GENERIC_CALIBRATE_DELAY=y 52CONFIG_GENERIC_CALIBRATE_DELAY=y
53CONFIG_GENERIC_CLOCKEVENTS=y
64CONFIG_GENERIC_TIME=y 54CONFIG_GENERIC_TIME=y
55CONFIG_GENERIC_CMOS_UPDATE=y
65CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 56CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
66# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set 57# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
58CONFIG_BOOT_RAW=y
59CONFIG_CEVT_R4K=y
67CONFIG_DMA_NONCOHERENT=y 60CONFIG_DMA_NONCOHERENT=y
68CONFIG_DMA_NEED_PCI_MAP_STATE=y 61CONFIG_DMA_NEED_PCI_MAP_STATE=y
62CONFIG_EARLY_PRINTK=y
63CONFIG_SYS_HAS_EARLY_PRINTK=y
64# CONFIG_HOTPLUG_CPU is not set
65# CONFIG_NO_IOPORT is not set
69# CONFIG_CPU_BIG_ENDIAN is not set 66# CONFIG_CPU_BIG_ENDIAN is not set
70CONFIG_CPU_LITTLE_ENDIAN=y 67CONFIG_CPU_LITTLE_ENDIAN=y
71CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y 68CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
@@ -76,6 +73,11 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
76# 73#
77# CPU selection 74# CPU selection
78# 75#
76# CONFIG_TICK_ONESHOT is not set
77# CONFIG_NO_HZ is not set
78# CONFIG_HIGH_RES_TIMERS is not set
79CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
80# CONFIG_CPU_LOONGSON2 is not set
79CONFIG_CPU_MIPS32_R1=y 81CONFIG_CPU_MIPS32_R1=y
80# CONFIG_CPU_MIPS32_R2 is not set 82# CONFIG_CPU_MIPS32_R2 is not set
81# CONFIG_CPU_MIPS64_R1 is not set 83# CONFIG_CPU_MIPS64_R1 is not set
@@ -115,8 +117,8 @@ CONFIG_CPU_HAS_PREFETCH=y
115CONFIG_MIPS_MT_DISABLED=y 117CONFIG_MIPS_MT_DISABLED=y
116# CONFIG_MIPS_MT_SMP is not set 118# CONFIG_MIPS_MT_SMP is not set
117# CONFIG_MIPS_MT_SMTC is not set 119# CONFIG_MIPS_MT_SMTC is not set
120CONFIG_SYS_SUPPORTS_MULTITHREADING=y
118# CONFIG_MIPS_VPE_LOADER is not set 121# CONFIG_MIPS_VPE_LOADER is not set
119# CONFIG_64BIT_PHYS_ADDR is not set
120CONFIG_CPU_HAS_LLSC=y 122CONFIG_CPU_HAS_LLSC=y
121CONFIG_CPU_HAS_SYNC=y 123CONFIG_CPU_HAS_SYNC=y
122CONFIG_GENERIC_HARDIRQS=y 124CONFIG_GENERIC_HARDIRQS=y
@@ -130,50 +132,52 @@ CONFIG_FLATMEM_MANUAL=y
130CONFIG_FLATMEM=y 132CONFIG_FLATMEM=y
131CONFIG_FLAT_NODE_MEM_MAP=y 133CONFIG_FLAT_NODE_MEM_MAP=y
132# CONFIG_SPARSEMEM_STATIC is not set 134# CONFIG_SPARSEMEM_STATIC is not set
135# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
133CONFIG_SPLIT_PTLOCK_CPUS=4 136CONFIG_SPLIT_PTLOCK_CPUS=4
134# CONFIG_RESOURCES_64BIT is not set 137# CONFIG_RESOURCES_64BIT is not set
135CONFIG_ZONE_DMA_FLAG=1 138CONFIG_ZONE_DMA_FLAG=0
139CONFIG_VIRT_TO_BUS=y
136# CONFIG_HZ_48 is not set 140# CONFIG_HZ_48 is not set
137# CONFIG_HZ_100 is not set 141CONFIG_HZ_100=y
138# CONFIG_HZ_128 is not set 142# CONFIG_HZ_128 is not set
139# CONFIG_HZ_250 is not set 143# CONFIG_HZ_250 is not set
140# CONFIG_HZ_256 is not set 144# CONFIG_HZ_256 is not set
141CONFIG_HZ_1000=y 145# CONFIG_HZ_1000 is not set
142# CONFIG_HZ_1024 is not set 146# CONFIG_HZ_1024 is not set
143CONFIG_SYS_SUPPORTS_ARBIT_HZ=y 147CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
144CONFIG_HZ=1000 148CONFIG_HZ=100
145CONFIG_PREEMPT_NONE=y 149CONFIG_PREEMPT_NONE=y
146# CONFIG_PREEMPT_VOLUNTARY is not set 150# CONFIG_PREEMPT_VOLUNTARY is not set
147# CONFIG_PREEMPT is not set 151# CONFIG_PREEMPT is not set
148# CONFIG_KEXEC is not set 152# CONFIG_KEXEC is not set
153# CONFIG_SECCOMP is not set
149CONFIG_LOCKDEP_SUPPORT=y 154CONFIG_LOCKDEP_SUPPORT=y
150CONFIG_STACKTRACE_SUPPORT=y 155CONFIG_STACKTRACE_SUPPORT=y
151CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 156CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
152 157
153# 158#
154# Code maturity level options 159# General setup
155# 160#
156CONFIG_EXPERIMENTAL=y 161CONFIG_EXPERIMENTAL=y
157CONFIG_BROKEN_ON_SMP=y 162CONFIG_BROKEN_ON_SMP=y
158CONFIG_INIT_ENV_ARG_LIMIT=32 163CONFIG_INIT_ENV_ARG_LIMIT=32
159
160#
161# General setup
162#
163CONFIG_LOCALVERSION="" 164CONFIG_LOCALVERSION=""
164CONFIG_LOCALVERSION_AUTO=y 165CONFIG_LOCALVERSION_AUTO=y
165CONFIG_SWAP=y 166# CONFIG_SWAP is not set
166CONFIG_SYSVIPC=y 167CONFIG_SYSVIPC=y
167# CONFIG_IPC_NS is not set
168CONFIG_SYSVIPC_SYSCTL=y 168CONFIG_SYSVIPC_SYSCTL=y
169# CONFIG_POSIX_MQUEUE is not set 169# CONFIG_POSIX_MQUEUE is not set
170# CONFIG_BSD_PROCESS_ACCT is not set 170# CONFIG_BSD_PROCESS_ACCT is not set
171# CONFIG_TASKSTATS is not set 171# CONFIG_TASKSTATS is not set
172# CONFIG_UTS_NS is not set 172# CONFIG_USER_NS is not set
173# CONFIG_AUDIT is not set 173# CONFIG_AUDIT is not set
174# CONFIG_IKCONFIG is not set 174# CONFIG_IKCONFIG is not set
175CONFIG_LOG_BUF_SHIFT=14
176CONFIG_FAIR_GROUP_SCHED=y
177CONFIG_FAIR_USER_SCHED=y
175CONFIG_SYSFS_DEPRECATED=y 178CONFIG_SYSFS_DEPRECATED=y
176# CONFIG_RELAY is not set 179# CONFIG_RELAY is not set
180# CONFIG_BLK_DEV_INITRD is not set
177# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 181# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
178CONFIG_SYSCTL=y 182CONFIG_SYSCTL=y
179CONFIG_EMBEDDED=y 183CONFIG_EMBEDDED=y
@@ -187,31 +191,29 @@ CONFIG_BUG=y
187CONFIG_ELF_CORE=y 191CONFIG_ELF_CORE=y
188CONFIG_BASE_FULL=y 192CONFIG_BASE_FULL=y
189CONFIG_FUTEX=y 193CONFIG_FUTEX=y
194CONFIG_ANON_INODES=y
190CONFIG_EPOLL=y 195CONFIG_EPOLL=y
196CONFIG_SIGNALFD=y
197CONFIG_EVENTFD=y
191CONFIG_SHMEM=y 198CONFIG_SHMEM=y
192CONFIG_SLAB=y
193CONFIG_VM_EVENT_COUNTERS=y 199CONFIG_VM_EVENT_COUNTERS=y
200CONFIG_SLAB=y
201# CONFIG_SLUB is not set
202# CONFIG_SLOB is not set
194CONFIG_RT_MUTEXES=y 203CONFIG_RT_MUTEXES=y
195# CONFIG_TINY_SHMEM is not set 204# CONFIG_TINY_SHMEM is not set
196CONFIG_BASE_SMALL=0 205CONFIG_BASE_SMALL=0
197# CONFIG_SLOB is not set
198
199#
200# Loadable module support
201#
202CONFIG_MODULES=y 206CONFIG_MODULES=y
203CONFIG_MODULE_UNLOAD=y 207CONFIG_MODULE_UNLOAD=y
204# CONFIG_MODULE_FORCE_UNLOAD is not set 208# CONFIG_MODULE_FORCE_UNLOAD is not set
205CONFIG_MODVERSIONS=y 209CONFIG_MODVERSIONS=y
206CONFIG_MODULE_SRCVERSION_ALL=y 210CONFIG_MODULE_SRCVERSION_ALL=y
207CONFIG_KMOD=y 211CONFIG_KMOD=y
208
209#
210# Block layer
211#
212CONFIG_BLOCK=y 212CONFIG_BLOCK=y
213# CONFIG_LBD is not set 213# CONFIG_LBD is not set
214# CONFIG_BLK_DEV_IO_TRACE is not set
214# CONFIG_LSF is not set 215# CONFIG_LSF is not set
216# CONFIG_BLK_DEV_BSG is not set
215 217
216# 218#
217# IO Schedulers 219# IO Schedulers
@@ -229,18 +231,11 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
229# 231#
230# Bus options (PCI, PCMCIA, EISA, ISA, TC) 232# Bus options (PCI, PCMCIA, EISA, ISA, TC)
231# 233#
234# CONFIG_ARCH_SUPPORTS_MSI is not set
232CONFIG_MMU=y 235CONFIG_MMU=y
233
234#
235# PCCARD (PCMCIA/CardBus) support
236#
237# CONFIG_PCCARD is not set 236# CONFIG_PCCARD is not set
238 237
239# 238#
240# PCI Hotplug Support
241#
242
243#
244# Executable file formats 239# Executable file formats
245# 240#
246CONFIG_BINFMT_ELF=y 241CONFIG_BINFMT_ELF=y
@@ -250,9 +245,8 @@ CONFIG_TRAD_SIGNALS=y
250# 245#
251# Power management options 246# Power management options
252# 247#
253CONFIG_PM=y 248# CONFIG_PM is not set
254# CONFIG_PM_LEGACY is not set 249CONFIG_SUSPEND_UP_POSSIBLE=y
255# CONFIG_PM_DEBUG is not set
256 250
257# 251#
258# Networking 252# Networking
@@ -262,75 +256,50 @@ CONFIG_NET=y
262# 256#
263# Networking options 257# Networking options
264# 258#
265# CONFIG_NETDEBUG is not set
266CONFIG_PACKET=y 259CONFIG_PACKET=y
267CONFIG_PACKET_MMAP=y 260CONFIG_PACKET_MMAP=y
268CONFIG_UNIX=y 261CONFIG_UNIX=y
269CONFIG_XFRM=y 262# CONFIG_NET_KEY is not set
270# CONFIG_XFRM_USER is not set
271# CONFIG_XFRM_SUB_POLICY is not set
272CONFIG_XFRM_MIGRATE=y
273CONFIG_NET_KEY=y
274CONFIG_NET_KEY_MIGRATE=y
275CONFIG_INET=y 263CONFIG_INET=y
276CONFIG_IP_MULTICAST=y 264CONFIG_IP_MULTICAST=y
277CONFIG_IP_ADVANCED_ROUTER=y 265CONFIG_IP_ADVANCED_ROUTER=y
278CONFIG_ASK_IP_FIB_HASH=y 266CONFIG_ASK_IP_FIB_HASH=y
279# CONFIG_IP_FIB_TRIE is not set 267# CONFIG_IP_FIB_TRIE is not set
280CONFIG_IP_FIB_HASH=y 268CONFIG_IP_FIB_HASH=y
281CONFIG_IP_MULTIPLE_TABLES=y 269# CONFIG_IP_MULTIPLE_TABLES is not set
282CONFIG_IP_ROUTE_MULTIPATH=y 270# CONFIG_IP_ROUTE_MULTIPATH is not set
283# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set 271# CONFIG_IP_ROUTE_VERBOSE is not set
284CONFIG_IP_ROUTE_VERBOSE=y
285CONFIG_IP_PNP=y 272CONFIG_IP_PNP=y
286CONFIG_IP_PNP_DHCP=y 273CONFIG_IP_PNP_DHCP=y
287CONFIG_IP_PNP_BOOTP=y 274CONFIG_IP_PNP_BOOTP=y
288# CONFIG_IP_PNP_RARP is not set 275# CONFIG_IP_PNP_RARP is not set
289# CONFIG_NET_IPIP is not set 276# CONFIG_NET_IPIP is not set
290# CONFIG_NET_IPGRE is not set 277# CONFIG_NET_IPGRE is not set
291CONFIG_IP_MROUTE=y 278# CONFIG_IP_MROUTE is not set
292CONFIG_IP_PIMSM_V1=y
293CONFIG_IP_PIMSM_V2=y
294# CONFIG_ARPD is not set 279# CONFIG_ARPD is not set
295CONFIG_SYN_COOKIES=y 280# CONFIG_SYN_COOKIES is not set
296# CONFIG_INET_AH is not set 281# CONFIG_INET_AH is not set
297# CONFIG_INET_ESP is not set 282# CONFIG_INET_ESP is not set
298# CONFIG_INET_IPCOMP is not set 283# CONFIG_INET_IPCOMP is not set
299# CONFIG_INET_XFRM_TUNNEL is not set 284# CONFIG_INET_XFRM_TUNNEL is not set
300# CONFIG_INET_TUNNEL is not set 285# CONFIG_INET_TUNNEL is not set
301CONFIG_INET_XFRM_MODE_TRANSPORT=m 286# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
302CONFIG_INET_XFRM_MODE_TUNNEL=m 287# CONFIG_INET_XFRM_MODE_TUNNEL is not set
303CONFIG_INET_XFRM_MODE_BEET=m 288# CONFIG_INET_XFRM_MODE_BEET is not set
289# CONFIG_INET_LRO is not set
304CONFIG_INET_DIAG=y 290CONFIG_INET_DIAG=y
305CONFIG_INET_TCP_DIAG=y 291CONFIG_INET_TCP_DIAG=y
306# CONFIG_TCP_CONG_ADVANCED is not set 292# CONFIG_TCP_CONG_ADVANCED is not set
307CONFIG_TCP_CONG_CUBIC=y 293CONFIG_TCP_CONG_CUBIC=y
308CONFIG_DEFAULT_TCP_CONG="cubic" 294CONFIG_DEFAULT_TCP_CONG="cubic"
309CONFIG_TCP_MD5SIG=y 295# CONFIG_TCP_MD5SIG is not set
310# CONFIG_IPV6 is not set 296# CONFIG_IPV6 is not set
311# CONFIG_INET6_XFRM_TUNNEL is not set 297# CONFIG_INET6_XFRM_TUNNEL is not set
312# CONFIG_INET6_TUNNEL is not set 298# CONFIG_INET6_TUNNEL is not set
313CONFIG_NETWORK_SECMARK=y 299# CONFIG_NETWORK_SECMARK is not set
314# CONFIG_NETFILTER is not set 300# CONFIG_NETFILTER is not set
315
316#
317# DCCP Configuration (EXPERIMENTAL)
318#
319# CONFIG_IP_DCCP is not set 301# CONFIG_IP_DCCP is not set
320 302# CONFIG_IP_SCTP is not set
321#
322# SCTP Configuration (EXPERIMENTAL)
323#
324CONFIG_IP_SCTP=m
325# CONFIG_SCTP_DBG_MSG is not set
326# CONFIG_SCTP_DBG_OBJCNT is not set
327# CONFIG_SCTP_HMAC_NONE is not set
328# CONFIG_SCTP_HMAC_SHA1 is not set
329CONFIG_SCTP_HMAC_MD5=y
330
331#
332# TIPC Configuration (EXPERIMENTAL)
333#
334# CONFIG_TIPC is not set 303# CONFIG_TIPC is not set
335# CONFIG_ATM is not set 304# CONFIG_ATM is not set
336# CONFIG_BRIDGE is not set 305# CONFIG_BRIDGE is not set
@@ -347,44 +316,7 @@ CONFIG_SCTP_HMAC_MD5=y
347# 316#
348# QoS and/or fair queueing 317# QoS and/or fair queueing
349# 318#
350CONFIG_NET_SCHED=y 319# CONFIG_NET_SCHED is not set
351CONFIG_NET_SCH_FIFO=y
352CONFIG_NET_SCH_CLK_JIFFIES=y
353# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
354# CONFIG_NET_SCH_CLK_CPU is not set
355
356#
357# Queueing/Scheduling
358#
359CONFIG_NET_SCH_CBQ=m
360CONFIG_NET_SCH_HTB=m
361CONFIG_NET_SCH_HFSC=m
362CONFIG_NET_SCH_PRIO=m
363CONFIG_NET_SCH_RED=m
364CONFIG_NET_SCH_SFQ=m
365CONFIG_NET_SCH_TEQL=m
366CONFIG_NET_SCH_TBF=m
367CONFIG_NET_SCH_GRED=m
368CONFIG_NET_SCH_DSMARK=m
369CONFIG_NET_SCH_NETEM=m
370CONFIG_NET_SCH_INGRESS=m
371
372#
373# Classification
374#
375CONFIG_NET_CLS=y
376CONFIG_NET_CLS_BASIC=m
377CONFIG_NET_CLS_TCINDEX=m
378CONFIG_NET_CLS_ROUTE4=m
379CONFIG_NET_CLS_ROUTE=y
380# CONFIG_NET_CLS_FW is not set
381# CONFIG_NET_CLS_U32 is not set
382# CONFIG_NET_CLS_RSVP is not set
383# CONFIG_NET_CLS_RSVP6 is not set
384# CONFIG_NET_EMATCH is not set
385# CONFIG_NET_CLS_ACT is not set
386# CONFIG_NET_CLS_POLICE is not set
387CONFIG_NET_ESTIMATOR=y
388 320
389# 321#
390# Network testing 322# Network testing
@@ -393,8 +325,17 @@ CONFIG_NET_ESTIMATOR=y
393# CONFIG_HAMRADIO is not set 325# CONFIG_HAMRADIO is not set
394# CONFIG_IRDA is not set 326# CONFIG_IRDA is not set
395# CONFIG_BT is not set 327# CONFIG_BT is not set
328# CONFIG_AF_RXRPC is not set
329
330#
331# Wireless
332#
333# CONFIG_CFG80211 is not set
334# CONFIG_WIRELESS_EXT is not set
335# CONFIG_MAC80211 is not set
396# CONFIG_IEEE80211 is not set 336# CONFIG_IEEE80211 is not set
397CONFIG_FIB_RULES=y 337# CONFIG_RFKILL is not set
338# CONFIG_NET_9P is not set
398 339
399# 340#
400# Device Drivers 341# Device Drivers
@@ -403,52 +344,25 @@ CONFIG_FIB_RULES=y
403# 344#
404# Generic Driver Options 345# Generic Driver Options
405# 346#
347CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
406# CONFIG_STANDALONE is not set 348# CONFIG_STANDALONE is not set
407# CONFIG_PREVENT_FIRMWARE_BUILD is not set 349# CONFIG_PREVENT_FIRMWARE_BUILD is not set
408# CONFIG_FW_LOADER is not set 350# CONFIG_FW_LOADER is not set
409# CONFIG_DEBUG_DRIVER is not set 351# CONFIG_DEBUG_DRIVER is not set
410# CONFIG_DEBUG_DEVRES is not set 352# CONFIG_DEBUG_DEVRES is not set
411# CONFIG_SYS_HYPERVISOR is not set 353# CONFIG_SYS_HYPERVISOR is not set
412
413#
414# Connector - unified userspace <-> kernelspace linker
415#
416# CONFIG_CONNECTOR is not set 354# CONFIG_CONNECTOR is not set
417
418#
419# Memory Technology Devices (MTD)
420#
421# CONFIG_MTD is not set 355# CONFIG_MTD is not set
422
423#
424# Parallel port support
425#
426# CONFIG_PARPORT is not set 356# CONFIG_PARPORT is not set
427 357CONFIG_BLK_DEV=y
428#
429# Plug and Play support
430#
431# CONFIG_PNPACPI is not set
432
433#
434# Block devices
435#
436# CONFIG_BLK_DEV_COW_COMMON is not set 358# CONFIG_BLK_DEV_COW_COMMON is not set
437CONFIG_BLK_DEV_LOOP=y 359CONFIG_BLK_DEV_LOOP=y
438# CONFIG_BLK_DEV_CRYPTOLOOP is not set 360# CONFIG_BLK_DEV_CRYPTOLOOP is not set
439CONFIG_BLK_DEV_NBD=y 361CONFIG_BLK_DEV_NBD=y
440# CONFIG_BLK_DEV_RAM is not set 362# CONFIG_BLK_DEV_RAM is not set
441# CONFIG_BLK_DEV_INITRD is not set
442# CONFIG_CDROM_PKTCDVD is not set 363# CONFIG_CDROM_PKTCDVD is not set
443# CONFIG_ATA_OVER_ETH is not set 364# CONFIG_ATA_OVER_ETH is not set
444 365# CONFIG_MISC_DEVICES is not set
445#
446# Misc devices
447#
448
449#
450# ATA/ATAPI/MFM/RLL support
451#
452# CONFIG_IDE is not set 366# CONFIG_IDE is not set
453 367
454# 368#
@@ -456,48 +370,29 @@ CONFIG_BLK_DEV_NBD=y
456# 370#
457# CONFIG_RAID_ATTRS is not set 371# CONFIG_RAID_ATTRS is not set
458# CONFIG_SCSI is not set 372# CONFIG_SCSI is not set
373# CONFIG_SCSI_DMA is not set
459# CONFIG_SCSI_NETLINK is not set 374# CONFIG_SCSI_NETLINK is not set
460
461#
462# Serial ATA (prod) and Parallel ATA (experimental) drivers
463#
464# CONFIG_ATA is not set 375# CONFIG_ATA is not set
465
466#
467# Multi-device support (RAID and LVM)
468#
469# CONFIG_MD is not set 376# CONFIG_MD is not set
470
471#
472# Fusion MPT device support
473#
474# CONFIG_FUSION is not set
475
476#
477# IEEE 1394 (FireWire) support
478#
479
480#
481# I2O device support
482#
483
484#
485# Network device support
486#
487CONFIG_NETDEVICES=y 377CONFIG_NETDEVICES=y
378# CONFIG_NETDEVICES_MULTIQUEUE is not set
488# CONFIG_DUMMY is not set 379# CONFIG_DUMMY is not set
489# CONFIG_BONDING is not set 380# CONFIG_BONDING is not set
381# CONFIG_MACVLAN is not set
490# CONFIG_EQUALIZER is not set 382# CONFIG_EQUALIZER is not set
491# CONFIG_TUN is not set 383# CONFIG_TUN is not set
384# CONFIG_VETH is not set
492# CONFIG_PHYLIB is not set 385# CONFIG_PHYLIB is not set
493
494#
495# Ethernet (10 or 100Mbit)
496#
497CONFIG_NET_ETHERNET=y 386CONFIG_NET_ETHERNET=y
498# CONFIG_MII is not set 387# CONFIG_MII is not set
388# CONFIG_AX88796 is not set
499CONFIG_MIPS_SIM_NET=y 389CONFIG_MIPS_SIM_NET=y
500# CONFIG_DM9000 is not set 390# CONFIG_DM9000 is not set
391# CONFIG_IBM_NEW_EMAC_ZMII is not set
392# CONFIG_IBM_NEW_EMAC_RGMII is not set
393# CONFIG_IBM_NEW_EMAC_TAH is not set
394# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
395# CONFIG_B44 is not set
501# CONFIG_NETDEV_1000 is not set 396# CONFIG_NETDEV_1000 is not set
502# CONFIG_NETDEV_10000 is not set 397# CONFIG_NETDEV_10000 is not set
503 398
@@ -513,49 +408,18 @@ CONFIG_MIPS_SIM_NET=y
513# CONFIG_NETCONSOLE is not set 408# CONFIG_NETCONSOLE is not set
514# CONFIG_NETPOLL is not set 409# CONFIG_NETPOLL is not set
515# CONFIG_NET_POLL_CONTROLLER is not set 410# CONFIG_NET_POLL_CONTROLLER is not set
516
517#
518# ISDN subsystem
519#
520# CONFIG_ISDN is not set 411# CONFIG_ISDN is not set
521
522#
523# Telephony Support
524#
525# CONFIG_PHONE is not set 412# CONFIG_PHONE is not set
526 413
527# 414#
528# Input device support 415# Input device support
529# 416#
530CONFIG_INPUT=y 417# CONFIG_INPUT is not set
531# CONFIG_INPUT_FF_MEMLESS is not set
532
533#
534# Userland interfaces
535#
536# CONFIG_INPUT_MOUSEDEV is not set
537# CONFIG_INPUT_JOYDEV is not set
538# CONFIG_INPUT_TSDEV is not set
539# CONFIG_INPUT_EVDEV is not set
540# CONFIG_INPUT_EVBUG is not set
541
542#
543# Input Device Drivers
544#
545# CONFIG_INPUT_KEYBOARD is not set
546# CONFIG_INPUT_MOUSE is not set
547# CONFIG_INPUT_JOYSTICK is not set
548# CONFIG_INPUT_TOUCHSCREEN is not set
549# CONFIG_INPUT_MISC is not set
550 418
551# 419#
552# Hardware I/O ports 420# Hardware I/O ports
553# 421#
554CONFIG_SERIO=y 422# CONFIG_SERIO is not set
555# CONFIG_SERIO_I8042 is not set
556CONFIG_SERIO_SERPORT=y
557# CONFIG_SERIO_LIBPS2 is not set
558# CONFIG_SERIO_RAW is not set
559# CONFIG_GAMEPORT is not set 423# CONFIG_GAMEPORT is not set
560 424
561# 425#
@@ -581,31 +445,13 @@ CONFIG_SERIAL_CORE_CONSOLE=y
581CONFIG_UNIX98_PTYS=y 445CONFIG_UNIX98_PTYS=y
582CONFIG_LEGACY_PTYS=y 446CONFIG_LEGACY_PTYS=y
583CONFIG_LEGACY_PTY_COUNT=256 447CONFIG_LEGACY_PTY_COUNT=256
584
585#
586# IPMI
587#
588# CONFIG_IPMI_HANDLER is not set 448# CONFIG_IPMI_HANDLER is not set
589
590#
591# Watchdog Cards
592#
593# CONFIG_WATCHDOG is not set 449# CONFIG_WATCHDOG is not set
594# CONFIG_HW_RANDOM is not set 450# CONFIG_HW_RANDOM is not set
595# CONFIG_RTC is not set 451# CONFIG_RTC is not set
596# CONFIG_GEN_RTC is not set
597# CONFIG_DTLK is not set
598# CONFIG_R3964 is not set 452# CONFIG_R3964 is not set
599# CONFIG_RAW_DRIVER is not set 453# CONFIG_RAW_DRIVER is not set
600
601#
602# TPM devices
603#
604# CONFIG_TCG_TPM is not set 454# CONFIG_TCG_TPM is not set
605
606#
607# I2C support
608#
609# CONFIG_I2C is not set 455# CONFIG_I2C is not set
610 456
611# 457#
@@ -613,118 +459,60 @@ CONFIG_LEGACY_PTY_COUNT=256
613# 459#
614# CONFIG_SPI is not set 460# CONFIG_SPI is not set
615# CONFIG_SPI_MASTER is not set 461# CONFIG_SPI_MASTER is not set
462# CONFIG_W1 is not set
463# CONFIG_POWER_SUPPLY is not set
464# CONFIG_HWMON is not set
616 465
617# 466#
618# Dallas's 1-wire bus 467# Sonics Silicon Backplane
619# 468#
620# CONFIG_W1 is not set 469CONFIG_SSB_POSSIBLE=y
470# CONFIG_SSB is not set
621 471
622# 472#
623# Hardware Monitoring support 473# Multifunction device drivers
624# 474#
625# CONFIG_HWMON is not set 475# CONFIG_MFD_SM501 is not set
626# CONFIG_HWMON_VID is not set
627 476
628# 477#
629# Multimedia devices 478# Multimedia devices
630# 479#
631# CONFIG_VIDEO_DEV is not set 480# CONFIG_VIDEO_DEV is not set
632 481# CONFIG_DVB_CORE is not set
633# 482# CONFIG_DAB is not set
634# Digital Video Broadcasting Devices
635#
636# CONFIG_DVB is not set
637 483
638# 484#
639# Graphics support 485# Graphics support
640# 486#
641# CONFIG_FIRMWARE_EDID is not set 487# CONFIG_VGASTATE is not set
488# CONFIG_VIDEO_OUTPUT_CONTROL is not set
642# CONFIG_FB is not set 489# CONFIG_FB is not set
490# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
643 491
644# 492#
645# Sound 493# Display device support
646# 494#
647# CONFIG_SOUND is not set 495# CONFIG_DISPLAY_SUPPORT is not set
648 496
649# 497#
650# HID Devices 498# Sound
651#
652# CONFIG_HID is not set
653
654#
655# USB support
656#
657# CONFIG_USB_ARCH_HAS_HCD is not set
658# CONFIG_USB_ARCH_HAS_OHCI is not set
659# CONFIG_USB_ARCH_HAS_EHCI is not set
660
661#
662# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
663#
664
665#
666# USB Gadget Support
667#
668# CONFIG_USB_GADGET is not set
669
670#
671# MMC/SD Card support
672# 499#
500# CONFIG_SOUND is not set
501# CONFIG_USB_SUPPORT is not set
673# CONFIG_MMC is not set 502# CONFIG_MMC is not set
674
675#
676# LED devices
677#
678# CONFIG_NEW_LEDS is not set 503# CONFIG_NEW_LEDS is not set
679 504CONFIG_RTC_LIB=y
680#
681# LED drivers
682#
683
684#
685# LED Triggers
686#
687
688#
689# InfiniBand support
690#
691
692#
693# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
694#
695
696#
697# Real Time Clock
698#
699# CONFIG_RTC_CLASS is not set 505# CONFIG_RTC_CLASS is not set
700 506
701# 507#
702# DMA Engine support 508# Userspace I/O
703#
704# CONFIG_DMA_ENGINE is not set
705
706#
707# DMA Clients
708#
709
710#
711# DMA Devices
712#
713
714#
715# Auxiliary Display support
716#
717
718#
719# Virtualization
720# 509#
510# CONFIG_UIO is not set
721 511
722# 512#
723# File systems 513# File systems
724# 514#
725CONFIG_EXT2_FS=y 515# CONFIG_EXT2_FS is not set
726# CONFIG_EXT2_FS_XATTR is not set
727# CONFIG_EXT2_FS_XIP is not set
728# CONFIG_EXT3_FS is not set 516# CONFIG_EXT3_FS is not set
729# CONFIG_EXT4DEV_FS is not set 517# CONFIG_EXT4DEV_FS is not set
730# CONFIG_REISERFS_FS is not set 518# CONFIG_REISERFS_FS is not set
@@ -732,6 +520,7 @@ CONFIG_EXT2_FS=y
732# CONFIG_FS_POSIX_ACL is not set 520# CONFIG_FS_POSIX_ACL is not set
733# CONFIG_XFS_FS is not set 521# CONFIG_XFS_FS is not set
734# CONFIG_GFS2_FS is not set 522# CONFIG_GFS2_FS is not set
523# CONFIG_OCFS2_FS is not set
735# CONFIG_MINIX_FS is not set 524# CONFIG_MINIX_FS is not set
736CONFIG_ROMFS_FS=y 525CONFIG_ROMFS_FS=y
737# CONFIG_INOTIFY is not set 526# CONFIG_INOTIFY is not set
@@ -760,10 +549,11 @@ CONFIG_ROMFS_FS=y
760CONFIG_PROC_FS=y 549CONFIG_PROC_FS=y
761# CONFIG_PROC_KCORE is not set 550# CONFIG_PROC_KCORE is not set
762CONFIG_PROC_SYSCTL=y 551CONFIG_PROC_SYSCTL=y
763# CONFIG_SYSFS is not set 552CONFIG_SYSFS=y
764# CONFIG_TMPFS is not set 553CONFIG_TMPFS=y
554# CONFIG_TMPFS_POSIX_ACL is not set
765# CONFIG_HUGETLB_PAGE is not set 555# CONFIG_HUGETLB_PAGE is not set
766CONFIG_RAMFS=y 556# CONFIG_CONFIGFS_FS is not set
767 557
768# 558#
769# Miscellaneous filesystems 559# Miscellaneous filesystems
@@ -781,10 +571,7 @@ CONFIG_RAMFS=y
781# CONFIG_QNX4FS_FS is not set 571# CONFIG_QNX4FS_FS is not set
782# CONFIG_SYSV_FS is not set 572# CONFIG_SYSV_FS is not set
783# CONFIG_UFS_FS is not set 573# CONFIG_UFS_FS is not set
784 574CONFIG_NETWORK_FILESYSTEMS=y
785#
786# Network File Systems
787#
788CONFIG_NFS_FS=y 575CONFIG_NFS_FS=y
789CONFIG_NFS_V3=y 576CONFIG_NFS_V3=y
790# CONFIG_NFS_V3_ACL is not set 577# CONFIG_NFS_V3_ACL is not set
@@ -796,6 +583,7 @@ CONFIG_LOCKD=y
796CONFIG_LOCKD_V4=y 583CONFIG_LOCKD_V4=y
797CONFIG_NFS_COMMON=y 584CONFIG_NFS_COMMON=y
798CONFIG_SUNRPC=y 585CONFIG_SUNRPC=y
586# CONFIG_SUNRPC_BIND34 is not set
799# CONFIG_RPCSEC_GSS_KRB5 is not set 587# CONFIG_RPCSEC_GSS_KRB5 is not set
800# CONFIG_RPCSEC_GSS_SPKM3 is not set 588# CONFIG_RPCSEC_GSS_SPKM3 is not set
801# CONFIG_SMB_FS is not set 589# CONFIG_SMB_FS is not set
@@ -803,22 +591,14 @@ CONFIG_SUNRPC=y
803# CONFIG_NCP_FS is not set 591# CONFIG_NCP_FS is not set
804# CONFIG_CODA_FS is not set 592# CONFIG_CODA_FS is not set
805# CONFIG_AFS_FS is not set 593# CONFIG_AFS_FS is not set
806# CONFIG_9P_FS is not set
807 594
808# 595#
809# Partition Types 596# Partition Types
810# 597#
811# CONFIG_PARTITION_ADVANCED is not set 598# CONFIG_PARTITION_ADVANCED is not set
812CONFIG_MSDOS_PARTITION=y 599CONFIG_MSDOS_PARTITION=y
813
814#
815# Native Language Support
816#
817# CONFIG_NLS is not set 600# CONFIG_NLS is not set
818 601# CONFIG_DLM is not set
819#
820# Distributed Lock Manager
821#
822 602
823# 603#
824# Profiling support 604# Profiling support
@@ -833,20 +613,22 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
833CONFIG_ENABLE_MUST_CHECK=y 613CONFIG_ENABLE_MUST_CHECK=y
834# CONFIG_MAGIC_SYSRQ is not set 614# CONFIG_MAGIC_SYSRQ is not set
835# CONFIG_UNUSED_SYMBOLS is not set 615# CONFIG_UNUSED_SYMBOLS is not set
616# CONFIG_DEBUG_FS is not set
836# CONFIG_HEADERS_CHECK is not set 617# CONFIG_HEADERS_CHECK is not set
837CONFIG_DEBUG_KERNEL=y 618CONFIG_DEBUG_KERNEL=y
838# CONFIG_DEBUG_SHIRQ is not set 619# CONFIG_DEBUG_SHIRQ is not set
839CONFIG_LOG_BUF_SHIFT=14
840# CONFIG_DETECT_SOFTLOCKUP is not set 620# CONFIG_DETECT_SOFTLOCKUP is not set
621# CONFIG_SCHED_DEBUG is not set
841# CONFIG_SCHEDSTATS is not set 622# CONFIG_SCHEDSTATS is not set
842# CONFIG_TIMER_STATS is not set 623# CONFIG_TIMER_STATS is not set
843# CONFIG_DEBUG_SLAB is not set 624# CONFIG_DEBUG_SLAB is not set
844# CONFIG_DEBUG_RT_MUTEXES is not set 625# CONFIG_DEBUG_RT_MUTEXES is not set
845# CONFIG_RT_MUTEX_TESTER is not set 626# CONFIG_RT_MUTEX_TESTER is not set
846# CONFIG_DEBUG_SPINLOCK is not set 627# CONFIG_DEBUG_SPINLOCK is not set
847CONFIG_DEBUG_MUTEXES=y 628# CONFIG_DEBUG_MUTEXES is not set
848# CONFIG_DEBUG_LOCK_ALLOC is not set 629# CONFIG_DEBUG_LOCK_ALLOC is not set
849# CONFIG_PROVE_LOCKING is not set 630# CONFIG_PROVE_LOCKING is not set
631# CONFIG_LOCK_STAT is not set
850# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 632# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
851# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 633# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
852# CONFIG_DEBUG_KOBJECT is not set 634# CONFIG_DEBUG_KOBJECT is not set
@@ -854,7 +636,9 @@ CONFIG_DEBUG_INFO=y
854# CONFIG_DEBUG_VM is not set 636# CONFIG_DEBUG_VM is not set
855# CONFIG_DEBUG_LIST is not set 637# CONFIG_DEBUG_LIST is not set
856CONFIG_FORCED_INLINING=y 638CONFIG_FORCED_INLINING=y
639# CONFIG_BOOT_PRINTK_DELAY is not set
857# CONFIG_RCU_TORTURE_TEST is not set 640# CONFIG_RCU_TORTURE_TEST is not set
641# CONFIG_FAULT_INJECTION is not set
858CONFIG_CROSSCOMPILE=y 642CONFIG_CROSSCOMPILE=y
859CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp" 643CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
860# CONFIG_DEBUG_STACK_USAGE is not set 644# CONFIG_DEBUG_STACK_USAGE is not set
@@ -865,60 +649,20 @@ CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
865# Security options 649# Security options
866# 650#
867# CONFIG_KEYS is not set 651# CONFIG_KEYS is not set
868 652# CONFIG_SECURITY is not set
869# 653# CONFIG_SECURITY_FILE_CAPABILITIES is not set
870# Cryptographic options 654# CONFIG_CRYPTO is not set
871#
872CONFIG_CRYPTO=y
873CONFIG_CRYPTO_ALGAPI=y
874CONFIG_CRYPTO_BLKCIPHER=m
875CONFIG_CRYPTO_HASH=y
876CONFIG_CRYPTO_MANAGER=y
877CONFIG_CRYPTO_HMAC=y
878CONFIG_CRYPTO_XCBC=m
879# CONFIG_CRYPTO_NULL is not set
880# CONFIG_CRYPTO_MD4 is not set
881CONFIG_CRYPTO_MD5=y
882# CONFIG_CRYPTO_SHA1 is not set
883# CONFIG_CRYPTO_SHA256 is not set
884# CONFIG_CRYPTO_SHA512 is not set
885# CONFIG_CRYPTO_WP512 is not set
886# CONFIG_CRYPTO_TGR192 is not set
887CONFIG_CRYPTO_GF128MUL=m
888CONFIG_CRYPTO_ECB=m
889CONFIG_CRYPTO_CBC=m
890CONFIG_CRYPTO_PCBC=m
891CONFIG_CRYPTO_LRW=m
892# CONFIG_CRYPTO_DES is not set
893CONFIG_CRYPTO_FCRYPT=m
894# CONFIG_CRYPTO_BLOWFISH is not set
895# CONFIG_CRYPTO_TWOFISH is not set
896# CONFIG_CRYPTO_SERPENT is not set
897# CONFIG_CRYPTO_AES is not set
898# CONFIG_CRYPTO_CAST5 is not set
899# CONFIG_CRYPTO_CAST6 is not set
900# CONFIG_CRYPTO_TEA is not set
901# CONFIG_CRYPTO_ARC4 is not set
902# CONFIG_CRYPTO_KHAZAD is not set
903# CONFIG_CRYPTO_ANUBIS is not set
904# CONFIG_CRYPTO_DEFLATE is not set
905# CONFIG_CRYPTO_MICHAEL_MIC is not set
906# CONFIG_CRYPTO_CRC32C is not set
907CONFIG_CRYPTO_CAMELLIA=m
908# CONFIG_CRYPTO_TEST is not set
909
910#
911# Hardware crypto devices
912#
913 655
914# 656#
915# Library routines 657# Library routines
916# 658#
917CONFIG_BITREVERSE=y
918# CONFIG_CRC_CCITT is not set 659# CONFIG_CRC_CCITT is not set
919CONFIG_CRC16=y 660# CONFIG_CRC16 is not set
920CONFIG_CRC32=y 661# CONFIG_CRC_ITU_T is not set
662# CONFIG_CRC32 is not set
663# CONFIG_CRC7 is not set
921# CONFIG_LIBCRC32C is not set 664# CONFIG_LIBCRC32C is not set
922CONFIG_PLIST=y 665CONFIG_PLIST=y
923CONFIG_HAS_IOMEM=y 666CONFIG_HAS_IOMEM=y
924CONFIG_HAS_IOPORT=y 667CONFIG_HAS_IOPORT=y
668CONFIG_HAS_DMA=y
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 3ed991ae0ebe..49dfcef2518c 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -196,6 +196,7 @@ CONFIG_SYSVIPC_SYSCTL=y
196# CONFIG_UTS_NS is not set 196# CONFIG_UTS_NS is not set
197# CONFIG_AUDIT is not set 197# CONFIG_AUDIT is not set
198# CONFIG_IKCONFIG is not set 198# CONFIG_IKCONFIG is not set
199CONFIG_CGROUPS=y
199CONFIG_CPUSETS=y 200CONFIG_CPUSETS=y
200CONFIG_SYSFS_DEPRECATED=y 201CONFIG_SYSFS_DEPRECATED=y
201CONFIG_RELAY=y 202CONFIG_RELAY=y
diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c
index 5e1da53b04a7..82f9e9013e70 100644
--- a/arch/mips/emma2rh/markeins/setup.c
+++ b/arch/mips/emma2rh/markeins/setup.c
@@ -104,12 +104,6 @@ void __init plat_time_init(void)
104 mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2; 104 mips_hpt_frequency = (bus_frequency * (4 + reg)) / 4 / 2;
105} 105}
106 106
107void __init plat_timer_setup(struct irqaction *irq)
108{
109 /* we are using the cpu counter for timer interrupts */
110 setup_irq(CPU_IRQ_BASE + 7, irq);
111}
112
113static void markeins_board_init(void); 107static void markeins_board_init(void);
114extern void markeins_irq_setup(void); 108extern void markeins_irq_setup(void);
115 109
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 835b056cea36..ae25b480723e 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -4,7 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1992 Linus Torvalds 6 * Copyright (C) 1992 Linus Torvalds
7 * Copyright (C) 1994 - 2001, 2003 Ralf Baechle 7 * Copyright (C) 1994 - 2001, 2003, 07 Ralf Baechle
8 */ 8 */
9#include <linux/clockchips.h> 9#include <linux/clockchips.h>
10#include <linux/init.h> 10#include <linux/init.h>
@@ -13,6 +13,7 @@
13#include <linux/spinlock.h> 13#include <linux/spinlock.h>
14 14
15#include <asm/irq_cpu.h> 15#include <asm/irq_cpu.h>
16#include <asm/i8253.h>
16#include <asm/i8259.h> 17#include <asm/i8259.h>
17#include <asm/io.h> 18#include <asm/io.h>
18#include <asm/jazz.h> 19#include <asm/jazz.h>
@@ -136,7 +137,7 @@ static struct irqaction r4030_timer_irqaction = {
136 .name = "timer", 137 .name = "timer",
137}; 138};
138 139
139void __init plat_timer_setup(struct irqaction *ignored) 140void __init plat_time_init(void)
140{ 141{
141 struct irqaction *irq = &r4030_timer_irqaction; 142 struct irqaction *irq = &r4030_timer_irqaction;
142 143
@@ -152,4 +153,5 @@ void __init plat_timer_setup(struct irqaction *ignored)
152 setup_irq(JAZZ_TIMER_IRQ, irq); 153 setup_irq(JAZZ_TIMER_IRQ, irq);
153 154
154 clockevents_register_device(&r4030_clockevent); 155 clockevents_register_device(&r4030_clockevent);
156 setup_pit_timer();
155} 157}
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index cfc7dce78dab..a7857973ca03 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -5,7 +5,7 @@
5 * License. See the file "COPYING" in the main directory of this archive 5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle 8 * Copyright (C) 1996, 1997, 1998, 2001, 07 by Ralf Baechle
9 * Copyright (C) 2001 MIPS Technologies, Inc. 9 * Copyright (C) 2001 MIPS Technologies, Inc.
10 * Copyright (C) 2007 by Thomas Bogendoerfer 10 * Copyright (C) 2007 by Thomas Bogendoerfer
11 */ 11 */
@@ -25,7 +25,6 @@
25#include <linux/serial_8250.h> 25#include <linux/serial_8250.h>
26 26
27#include <asm/bootinfo.h> 27#include <asm/bootinfo.h>
28#include <asm/i8253.h>
29#include <asm/irq.h> 28#include <asm/irq.h>
30#include <asm/jazz.h> 29#include <asm/jazz.h>
31#include <asm/jazzdma.h> 30#include <asm/jazzdma.h>
@@ -64,11 +63,6 @@ static struct resource jazz_io_resources[] = {
64 } 63 }
65}; 64};
66 65
67void __init plat_time_init(void)
68{
69 setup_pit_timer();
70}
71
72void __init plat_mem_setup(void) 66void __init plat_mem_setup(void)
73{ 67{
74 int i; 68 int i;
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index 0c7aee1682cd..edb9e59248ec 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -1,15 +1,4 @@
1/*********************************************************************** 1/*
2 *
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: MontaVista Software, Inc.
5 * ahennessy@mvista.com
6 *
7 * Based on arch/mips/ddb5xxx/ddb5477/setup.c
8 *
9 * Setup file for JMR3927.
10 *
11 * Copyright (C) 2000-2001 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify it 2 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the 3 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your 4 * Free Software Foundation; either version 2 of the License, or (at your
@@ -30,9 +19,15 @@
30 * with this program; if not, write to the Free Software Foundation, Inc., 19 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA. 20 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 * 21 *
33 *********************************************************************** 22 * Copyright 2001 MontaVista Software Inc.
23 * Author: MontaVista Software, Inc.
24 * ahennessy@mvista.com
25 *
26 * Copyright (C) 2000-2001 Toshiba Corporation
27 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
34 */ 28 */
35 29
30#include <linux/clockchips.h>
36#include <linux/init.h> 31#include <linux/init.h>
37#include <linux/kernel.h> 32#include <linux/kernel.h>
38#include <linux/kdev_t.h> 33#include <linux/kdev_t.h>
@@ -104,27 +99,60 @@ static cycle_t jmr3927_hpt_read(void)
104 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr; 99 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
105} 100}
106 101
107static void jmr3927_timer_ack(void) 102static void jmr3927_set_mode(enum clock_event_mode mode,
103 struct clock_event_device *evt)
104{
105 /* Nothing to do here */
106}
107
108struct clock_event_device jmr3927_clock_event_device = {
109 .name = "MIPS",
110 .features = CLOCK_EVT_FEAT_PERIODIC,
111 .shift = 32,
112 .rating = 300,
113 .cpumask = CPU_MASK_CPU0,
114 .irq = JMR3927_IRQ_TICK,
115 .set_mode = jmr3927_set_mode,
116};
117
118static irqreturn_t jmr3927_timer_interrupt(int irq, void *dev_id)
108{ 119{
120 struct clock_event_device *cd = &jmr3927_clock_event_device;
121
109 jmr3927_tmrptr->tisr = 0; /* ack interrupt */ 122 jmr3927_tmrptr->tisr = 0; /* ack interrupt */
123
124 cd->event_handler(cd);
125
126 return IRQ_HANDLED;
110} 127}
111 128
129static struct irqaction jmr3927_timer_irqaction = {
130 .handler = jmr3927_timer_interrupt,
131 .flags = IRQF_DISABLED | IRQF_PERCPU,
132 .name = "jmr3927-timer",
133};
134
112void __init plat_time_init(void) 135void __init plat_time_init(void)
113{ 136{
137 struct clock_event_device *cd;
138
114 clocksource_mips.read = jmr3927_hpt_read; 139 clocksource_mips.read = jmr3927_hpt_read;
115 mips_timer_ack = jmr3927_timer_ack;
116 mips_hpt_frequency = JMR3927_TIMER_CLK; 140 mips_hpt_frequency = JMR3927_TIMER_CLK;
117}
118 141
119void __init plat_timer_setup(struct irqaction *irq)
120{
121 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ; 142 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
122 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE; 143 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
123 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD; 144 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
124 jmr3927_tmrptr->tcr = 145 jmr3927_tmrptr->tcr =
125 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL; 146 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
126 147
127 setup_irq(JMR3927_IRQ_TICK, irq); 148 cd = &jmr3927_clock_event_device;
149 /* Calculate the min / max delta */
150 cd->mult = div_sc((unsigned long) JMR3927_IMCLK, NSEC_PER_SEC, 32);
151 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
152 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
153 clockevents_register_device(cd);
154
155 setup_irq(JMR3927_IRQ_TICK, &jmr3927_timer_irqaction);
128} 156}
129 157
130#define DO_WRITE_THROUGH 158#define DO_WRITE_THROUGH
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 95a356ef3910..a3afa39faae5 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -8,6 +8,8 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
8 ptrace.o reset.o semaphore.o setup.o signal.o syscall.o \ 8 ptrace.o reset.o semaphore.o setup.o signal.o syscall.o \
9 time.o topology.o traps.o unaligned.o 9 time.o topology.o traps.o unaligned.o
10 10
11obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
12
11binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ 13binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
12 irix5sys.o sysirix.o 14 irix5sys.o sysirix.o
13 15
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
new file mode 100644
index 000000000000..a915e5693421
--- /dev/null
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -0,0 +1,273 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 MIPS Technologies, Inc.
7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
8 */
9#include <linux/clockchips.h>
10#include <linux/interrupt.h>
11#include <linux/percpu.h>
12
13#include <asm/smtc_ipi.h>
14#include <asm/time.h>
15
16static int mips_next_event(unsigned long delta,
17 struct clock_event_device *evt)
18{
19 unsigned int cnt;
20 int res;
21
22#ifdef CONFIG_MIPS_MT_SMTC
23 {
24 unsigned long flags, vpflags;
25 local_irq_save(flags);
26 vpflags = dvpe();
27#endif
28 cnt = read_c0_count();
29 cnt += delta;
30 write_c0_compare(cnt);
31 res = ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0;
32#ifdef CONFIG_MIPS_MT_SMTC
33 evpe(vpflags);
34 local_irq_restore(flags);
35 }
36#endif
37 return res;
38}
39
40static void mips_set_mode(enum clock_event_mode mode,
41 struct clock_event_device *evt)
42{
43 /* Nothing to do ... */
44}
45
46static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
47static int cp0_timer_irq_installed;
48
49/*
50 * Timer ack for an R4k-compatible timer of a known frequency.
51 */
52static void c0_timer_ack(void)
53{
54 write_c0_compare(read_c0_compare());
55}
56
57/*
58 * Possibly handle a performance counter interrupt.
59 * Return true if the timer interrupt should not be checked
60 */
61static inline int handle_perf_irq(int r2)
62{
63 /*
64 * The performance counter overflow interrupt may be shared with the
65 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
66 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
67 * and we can't reliably determine if a counter interrupt has also
68 * happened (!r2) then don't check for a timer interrupt.
69 */
70 return (cp0_perfcount_irq < 0) &&
71 perf_irq() == IRQ_HANDLED &&
72 !r2;
73}
74
75static irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
76{
77 const int r2 = cpu_has_mips_r2;
78 struct clock_event_device *cd;
79 int cpu = smp_processor_id();
80
81 /*
82 * Suckage alert:
83 * Before R2 of the architecture there was no way to see if a
84 * performance counter interrupt was pending, so we have to run
85 * the performance counter interrupt handler anyway.
86 */
87 if (handle_perf_irq(r2))
88 goto out;
89
90 /*
91 * The same applies to performance counter interrupts. But with the
92 * above we now know that the reason we got here must be a timer
93 * interrupt. Being the paranoiacs we are we check anyway.
94 */
95 if (!r2 || (read_c0_cause() & (1 << 30))) {
96 c0_timer_ack();
97#ifdef CONFIG_MIPS_MT_SMTC
98 if (cpu_data[cpu].vpe_id)
99 goto out;
100 cpu = 0;
101#endif
102 cd = &per_cpu(mips_clockevent_device, cpu);
103 cd->event_handler(cd);
104 }
105
106out:
107 return IRQ_HANDLED;
108}
109
110static struct irqaction c0_compare_irqaction = {
111 .handler = c0_compare_interrupt,
112#ifdef CONFIG_MIPS_MT_SMTC
113 .flags = IRQF_DISABLED,
114#else
115 .flags = IRQF_DISABLED | IRQF_PERCPU,
116#endif
117 .name = "timer",
118};
119
120#ifdef CONFIG_MIPS_MT_SMTC
121DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
122
123static void smtc_set_mode(enum clock_event_mode mode,
124 struct clock_event_device *evt)
125{
126}
127
128static void mips_broadcast(cpumask_t mask)
129{
130 unsigned int cpu;
131
132 for_each_cpu_mask(cpu, mask)
133 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
134}
135
136static void setup_smtc_dummy_clockevent_device(void)
137{
138 //uint64_t mips_freq = mips_hpt_^frequency;
139 unsigned int cpu = smp_processor_id();
140 struct clock_event_device *cd;
141
142 cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
143
144 cd->name = "SMTC";
145 cd->features = CLOCK_EVT_FEAT_DUMMY;
146
147 /* Calculate the min / max delta */
148 cd->mult = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
149 cd->shift = 0; //32;
150 cd->max_delta_ns = 0; //clockevent_delta2ns(0x7fffffff, cd);
151 cd->min_delta_ns = 0; //clockevent_delta2ns(0x30, cd);
152
153 cd->rating = 200;
154 cd->irq = 17; //-1;
155// if (cpu)
156// cd->cpumask = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
157// else
158 cd->cpumask = cpumask_of_cpu(cpu);
159
160 cd->set_mode = smtc_set_mode;
161
162 cd->broadcast = mips_broadcast;
163
164 clockevents_register_device(cd);
165}
166#endif
167
168static void mips_event_handler(struct clock_event_device *dev)
169{
170}
171
172/*
173 * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
174 */
175static int c0_compare_int_pending(void)
176{
177 return (read_c0_cause() >> cp0_compare_irq) & 0x100;
178}
179
180static int c0_compare_int_usable(void)
181{
182 const unsigned int delta = 0x300000;
183 unsigned int cnt;
184
185 /*
186 * IP7 already pending? Try to clear it by acking the timer.
187 */
188 if (c0_compare_int_pending()) {
189 write_c0_compare(read_c0_compare());
190 irq_disable_hazard();
191 if (c0_compare_int_pending())
192 return 0;
193 }
194
195 cnt = read_c0_count();
196 cnt += delta;
197 write_c0_compare(cnt);
198
199 while ((long)(read_c0_count() - cnt) <= 0)
200 ; /* Wait for expiry */
201
202 if (!c0_compare_int_pending())
203 return 0;
204
205 write_c0_compare(read_c0_compare());
206 irq_disable_hazard();
207 if (c0_compare_int_pending())
208 return 0;
209
210 /*
211 * Feels like a real count / compare timer.
212 */
213 return 1;
214}
215
216void __cpuinit mips_clockevent_init(void)
217{
218 uint64_t mips_freq = mips_hpt_frequency;
219 unsigned int cpu = smp_processor_id();
220 struct clock_event_device *cd;
221 unsigned int irq = MIPS_CPU_IRQ_BASE + 7;
222
223 if (!cpu_has_counter)
224 return;
225
226#ifdef CONFIG_MIPS_MT_SMTC
227 setup_smtc_dummy_clockevent_device();
228
229 /*
230 * On SMTC we only register VPE0's compare interrupt as clockevent
231 * device.
232 */
233 if (cpu)
234 return;
235#endif
236
237 if (!c0_compare_int_usable())
238 return;
239
240 cd = &per_cpu(mips_clockevent_device, cpu);
241
242 cd->name = "MIPS";
243 cd->features = CLOCK_EVT_FEAT_ONESHOT;
244
245 /* Calculate the min / max delta */
246 cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
247 cd->shift = 32;
248 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
249 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
250
251 cd->rating = 300;
252 cd->irq = irq;
253#ifdef CONFIG_MIPS_MT_SMTC
254 cd->cpumask = CPU_MASK_ALL;
255#else
256 cd->cpumask = cpumask_of_cpu(cpu);
257#endif
258 cd->set_next_event = mips_next_event;
259 cd->set_mode = mips_set_mode;
260 cd->event_handler = mips_event_handler;
261
262 clockevents_register_device(cd);
263
264 if (!cp0_timer_irq_installed) {
265#ifdef CONFIG_MIPS_MT_SMTC
266#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
267 setup_irq_smtc(irq, &c0_compare_irqaction, CPUCTR_IMASKBIT);
268#else
269 setup_irq(irq, &c0_compare_irqaction);
270#endif /* CONFIG_MIPS_MT_SMTC */
271 cp0_timer_irq_installed = 1;
272 }
273}
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index bf164a562acb..236768731063 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -27,16 +27,6 @@
27 27
28#include <kernel-entry-init.h> 28#include <kernel-entry-init.h>
29 29
30 .macro ARC64_TWIDDLE_PC
31#if defined(CONFIG_ARC64) || defined(CONFIG_MAPPED_KERNEL)
32 /* We get launched at a XKPHYS address but the kernel is linked to
33 run at a KSEG0 address, so jump there. */
34 PTR_LA t0, \@f
35 jr t0
36\@:
37#endif
38 .endm
39
40 /* 30 /*
41 * inputs are the text nasid in t1, data nasid in t2. 31 * inputs are the text nasid in t1, data nasid in t2.
42 */ 32 */
@@ -157,7 +147,11 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
157 147
158 setup_c0_status_pri 148 setup_c0_status_pri
159 149
160 ARC64_TWIDDLE_PC 150 /* We might not get launched at the address the kernel is linked to,
151 so we jump there. */
152 PTR_LA t0, 0f
153 jr t0
1540:
161 155
162#ifdef CONFIG_MIPS_MT_SMTC 156#ifdef CONFIG_MIPS_MT_SMTC
163 /* 157 /*
diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c
index b997af713eb3..7852c7cdf29e 100644
--- a/arch/mips/kernel/irixelf.c
+++ b/arch/mips/kernel/irixelf.c
@@ -1172,8 +1172,8 @@ static int irix_core_dump(long signr, struct pt_regs *regs, struct file *file, u
1172 prstatus.pr_sighold = current->blocked.sig[0]; 1172 prstatus.pr_sighold = current->blocked.sig[0];
1173 psinfo.pr_pid = prstatus.pr_pid = current->pid; 1173 psinfo.pr_pid = prstatus.pr_pid = current->pid;
1174 psinfo.pr_ppid = prstatus.pr_ppid = current->parent->pid; 1174 psinfo.pr_ppid = prstatus.pr_ppid = current->parent->pid;
1175 psinfo.pr_pgrp = prstatus.pr_pgrp = process_group(current); 1175 psinfo.pr_pgrp = prstatus.pr_pgrp = task_pgrp_nr(current);
1176 psinfo.pr_sid = prstatus.pr_sid = process_session(current); 1176 psinfo.pr_sid = prstatus.pr_sid = task_session_nr(current);
1177 if (current->pid == current->tgid) { 1177 if (current->pid == current->tgid) {
1178 /* 1178 /*
1179 * This is the record for the group leader. Add in the 1179 * This is the record for the group leader. Add in the
diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c
index 85c2e389edd6..a0a91056fda7 100644
--- a/arch/mips/kernel/irixsig.c
+++ b/arch/mips/kernel/irixsig.c
@@ -609,7 +609,7 @@ repeat:
609 p = list_entry(_p, struct task_struct, sibling); 609 p = list_entry(_p, struct task_struct, sibling);
610 if ((type == IRIX_P_PID) && p->pid != pid) 610 if ((type == IRIX_P_PID) && p->pid != pid)
611 continue; 611 continue;
612 if ((type == IRIX_P_PGID) && process_group(p) != pid) 612 if ((type == IRIX_P_PGID) && task_pgrp_nr(p) != pid)
613 continue; 613 continue;
614 if ((p->exit_signal != SIGCHLD)) 614 if ((p->exit_signal != SIGCHLD))
615 continue; 615 continue;
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index cb0801437b66..e7ed0ac48537 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -381,7 +381,7 @@ const struct exception_table_entry *search_module_dbetables(unsigned long addr)
381 return e; 381 return e;
382} 382}
383 383
384/* Put in dbe list if neccessary. */ 384/* Put in dbe list if necessary. */
385int module_finalize(const Elf_Ehdr *hdr, 385int module_finalize(const Elf_Ehdr *hdr,
386 const Elf_Shdr *sechdrs, 386 const Elf_Shdr *sechdrs,
387 struct module *me) 387 struct module *me)
diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c
index ee7790d9debe..4c477c7ff74a 100644
--- a/arch/mips/kernel/sysirix.c
+++ b/arch/mips/kernel/sysirix.c
@@ -763,11 +763,11 @@ asmlinkage int irix_setpgrp(int flags)
763 printk("[%s:%d] setpgrp(%d) ", current->comm, current->pid, flags); 763 printk("[%s:%d] setpgrp(%d) ", current->comm, current->pid, flags);
764#endif 764#endif
765 if(!flags) 765 if(!flags)
766 error = process_group(current); 766 error = task_pgrp_nr(current);
767 else 767 else
768 error = sys_setsid(); 768 error = sys_setsid();
769#ifdef DEBUG_PROCGRPS 769#ifdef DEBUG_PROCGRPS
770 printk("returning %d\n", process_group(current)); 770 printk("returning %d\n", task_pgrp_nr(current));
771#endif 771#endif
772 772
773 return error; 773 return error;
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index e4b5e647b142..c4e6866d5cbc 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -40,17 +40,6 @@
40#include <irq.h> 40#include <irq.h>
41 41
42/* 42/*
43 * The integer part of the number of usecs per jiffy is taken from tick,
44 * but the fractional part is not recorded, so we calculate it using the
45 * initial value of HZ. This aids systems where tick isn't really an
46 * integer (e.g. for HZ = 128).
47 */
48#define USECS_PER_JIFFY TICK_SIZE
49#define USECS_PER_JIFFY_FRAC ((unsigned long)(u32)((1000000ULL << 32) / HZ))
50
51#define TICK_SIZE (tick_nsec / 1000)
52
53/*
54 * forward reference 43 * forward reference
55 */ 44 */
56DEFINE_SPINLOCK(rtc_lock); 45DEFINE_SPINLOCK(rtc_lock);
@@ -72,14 +61,6 @@ int update_persistent_clock(struct timespec now)
72 return rtc_mips_set_mmss(now.tv_sec); 61 return rtc_mips_set_mmss(now.tv_sec);
73} 62}
74 63
75/* how many counter cycles in a jiffy */
76static unsigned long cycles_per_jiffy __read_mostly;
77
78/*
79 * Null timer ack for systems not needing one (e.g. i8254).
80 */
81static void null_timer_ack(void) { /* nothing */ }
82
83/* 64/*
84 * Null high precision timer functions for systems lacking one. 65 * Null high precision timer functions for systems lacking one.
85 */ 66 */
@@ -89,14 +70,6 @@ static cycle_t null_hpt_read(void)
89} 70}
90 71
91/* 72/*
92 * Timer ack for an R4k-compatible timer of a known frequency.
93 */
94static void c0_timer_ack(void)
95{
96 write_c0_compare(read_c0_compare());
97}
98
99/*
100 * High precision timer functions for a R4k-compatible timer. 73 * High precision timer functions for a R4k-compatible timer.
101 */ 74 */
102static cycle_t c0_hpt_read(void) 75static cycle_t c0_hpt_read(void)
@@ -105,7 +78,6 @@ static cycle_t c0_hpt_read(void)
105} 78}
106 79
107int (*mips_timer_state)(void); 80int (*mips_timer_state)(void);
108void (*mips_timer_ack)(void);
109 81
110/* 82/*
111 * local_timer_interrupt() does profiling and process accounting 83 * local_timer_interrupt() does profiling and process accounting
@@ -135,35 +107,6 @@ int (*perf_irq)(void) = null_perf_irq;
135EXPORT_SYMBOL(perf_irq); 107EXPORT_SYMBOL(perf_irq);
136 108
137/* 109/*
138 * Timer interrupt
139 */
140int cp0_compare_irq;
141
142/*
143 * Performance counter IRQ or -1 if shared with timer
144 */
145int cp0_perfcount_irq;
146EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
147
148/*
149 * Possibly handle a performance counter interrupt.
150 * Return true if the timer interrupt should not be checked
151 */
152static inline int handle_perf_irq(int r2)
153{
154 /*
155 * The performance counter overflow interrupt may be shared with the
156 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
157 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
158 * and we can't reliably determine if a counter interrupt has also
159 * happened (!r2) then don't check for a timer interrupt.
160 */
161 return (cp0_perfcount_irq < 0) &&
162 perf_irq() == IRQ_HANDLED &&
163 !r2;
164}
165
166/*
167 * time_init() - it does the following things. 110 * time_init() - it does the following things.
168 * 111 *
169 * 1) plat_time_init() - 112 * 1) plat_time_init() -
@@ -228,270 +171,58 @@ struct clocksource clocksource_mips = {
228 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 171 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
229}; 172};
230 173
231static int mips_next_event(unsigned long delta, 174void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
232 struct clock_event_device *evt)
233{ 175{
234 unsigned int cnt; 176 u64 temp;
235 int res; 177 u32 shift;
236
237#ifdef CONFIG_MIPS_MT_SMTC
238 {
239 unsigned long flags, vpflags;
240 local_irq_save(flags);
241 vpflags = dvpe();
242#endif
243 cnt = read_c0_count();
244 cnt += delta;
245 write_c0_compare(cnt);
246 res = ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0;
247#ifdef CONFIG_MIPS_MT_SMTC
248 evpe(vpflags);
249 local_irq_restore(flags);
250 }
251#endif
252 return res;
253}
254
255static void mips_set_mode(enum clock_event_mode mode,
256 struct clock_event_device *evt)
257{
258 /* Nothing to do ... */
259}
260
261static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
262static int cp0_timer_irq_installed;
263
264static irqreturn_t timer_interrupt(int irq, void *dev_id)
265{
266 const int r2 = cpu_has_mips_r2;
267 struct clock_event_device *cd;
268 int cpu = smp_processor_id();
269
270 /*
271 * Suckage alert:
272 * Before R2 of the architecture there was no way to see if a
273 * performance counter interrupt was pending, so we have to run
274 * the performance counter interrupt handler anyway.
275 */
276 if (handle_perf_irq(r2))
277 goto out;
278 178
279 /* 179 /* Find a shift value */
280 * The same applies to performance counter interrupts. But with the 180 for (shift = 32; shift > 0; shift--) {
281 * above we now know that the reason we got here must be a timer 181 temp = (u64) NSEC_PER_SEC << shift;
282 * interrupt. Being the paranoiacs we are we check anyway. 182 do_div(temp, clock);
283 */ 183 if ((temp >> 32) == 0)
284 if (!r2 || (read_c0_cause() & (1 << 30))) { 184 break;
285 c0_timer_ack();
286#ifdef CONFIG_MIPS_MT_SMTC
287 if (cpu_data[cpu].vpe_id)
288 goto out;
289 cpu = 0;
290#endif
291 cd = &per_cpu(mips_clockevent_device, cpu);
292 cd->event_handler(cd);
293 } 185 }
294 186 cs->shift = shift;
295out: 187 cs->mult = (u32) temp;
296 return IRQ_HANDLED;
297} 188}
298 189
299static struct irqaction timer_irqaction = { 190void __cpuinit clockevent_set_clock(struct clock_event_device *cd,
300 .handler = timer_interrupt, 191 unsigned int clock)
301#ifdef CONFIG_MIPS_MT_SMTC
302 .flags = IRQF_DISABLED,
303#else
304 .flags = IRQF_DISABLED | IRQF_PERCPU,
305#endif
306 .name = "timer",
307};
308
309static void __init init_mips_clocksource(void)
310{ 192{
311 u64 temp; 193 u64 temp;
312 u32 shift; 194 u32 shift;
313 195
314 if (!mips_hpt_frequency || clocksource_mips.read == null_hpt_read)
315 return;
316
317 /* Calclate a somewhat reasonable rating value */
318 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
319 /* Find a shift value */ 196 /* Find a shift value */
320 for (shift = 32; shift > 0; shift--) { 197 for (shift = 32; shift > 0; shift--) {
321 temp = (u64) NSEC_PER_SEC << shift; 198 temp = (u64) NSEC_PER_SEC << shift;
322 do_div(temp, mips_hpt_frequency); 199 do_div(temp, clock);
323 if ((temp >> 32) == 0) 200 if ((temp >> 32) == 0)
324 break; 201 break;
325 } 202 }
326 clocksource_mips.shift = shift; 203 cd->shift = shift;
327 clocksource_mips.mult = (u32)temp; 204 cd->mult = (u32) temp;
328
329 clocksource_register(&clocksource_mips);
330}
331
332void __init __weak plat_time_init(void)
333{
334} 205}
335 206
336void __init __weak plat_timer_setup(struct irqaction *irq) 207static void __init init_mips_clocksource(void)
337{
338}
339
340#ifdef CONFIG_MIPS_MT_SMTC
341DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
342
343static void smtc_set_mode(enum clock_event_mode mode,
344 struct clock_event_device *evt)
345{
346}
347
348int dummycnt[NR_CPUS];
349
350static void mips_broadcast(cpumask_t mask)
351{
352 unsigned int cpu;
353
354 for_each_cpu_mask(cpu, mask)
355 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
356}
357
358static void setup_smtc_dummy_clockevent_device(void)
359{ 208{
360 //uint64_t mips_freq = mips_hpt_^frequency; 209 if (!mips_hpt_frequency || clocksource_mips.read == null_hpt_read)
361 unsigned int cpu = smp_processor_id(); 210 return;
362 struct clock_event_device *cd;
363
364 cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
365
366 cd->name = "SMTC";
367 cd->features = CLOCK_EVT_FEAT_DUMMY;
368
369 /* Calculate the min / max delta */
370 cd->mult = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
371 cd->shift = 0; //32;
372 cd->max_delta_ns = 0; //clockevent_delta2ns(0x7fffffff, cd);
373 cd->min_delta_ns = 0; //clockevent_delta2ns(0x30, cd);
374
375 cd->rating = 200;
376 cd->irq = 17; //-1;
377// if (cpu)
378// cd->cpumask = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
379// else
380 cd->cpumask = cpumask_of_cpu(cpu);
381
382 cd->set_mode = smtc_set_mode;
383
384 cd->broadcast = mips_broadcast;
385 211
386 clockevents_register_device(cd); 212 /* Calclate a somewhat reasonable rating value */
387} 213 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
388#endif
389 214
390static void mips_event_handler(struct clock_event_device *dev) 215 clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
391{
392}
393 216
394/* 217 clocksource_register(&clocksource_mips);
395 * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
396 */
397static int c0_compare_int_pending(void)
398{
399 return (read_c0_cause() >> cp0_compare_irq) & 0x100;
400} 218}
401 219
402static int c0_compare_int_usable(void) 220void __init __weak plat_time_init(void)
403{ 221{
404 const unsigned int delta = 0x300000;
405 unsigned int cnt;
406
407 /*
408 * IP7 already pending? Try to clear it by acking the timer.
409 */
410 if (c0_compare_int_pending()) {
411 write_c0_compare(read_c0_compare());
412 irq_disable_hazard();
413 if (c0_compare_int_pending())
414 return 0;
415 }
416
417 cnt = read_c0_count();
418 cnt += delta;
419 write_c0_compare(cnt);
420
421 while ((long)(read_c0_count() - cnt) <= 0)
422 ; /* Wait for expiry */
423
424 if (!c0_compare_int_pending())
425 return 0;
426
427 write_c0_compare(read_c0_compare());
428 irq_disable_hazard();
429 if (c0_compare_int_pending())
430 return 0;
431
432 /*
433 * Feels like a real count / compare timer.
434 */
435 return 1;
436} 222}
437 223
438void __cpuinit mips_clockevent_init(void) 224void __init __weak plat_timer_setup(struct irqaction *irq)
439{ 225{
440 uint64_t mips_freq = mips_hpt_frequency;
441 unsigned int cpu = smp_processor_id();
442 struct clock_event_device *cd;
443 unsigned int irq = MIPS_CPU_IRQ_BASE + 7;
444
445 if (!cpu_has_counter)
446 return;
447
448#ifdef CONFIG_MIPS_MT_SMTC
449 setup_smtc_dummy_clockevent_device();
450
451 /*
452 * On SMTC we only register VPE0's compare interrupt as clockevent
453 * device.
454 */
455 if (cpu)
456 return;
457#endif
458
459 if (!c0_compare_int_usable())
460 return;
461
462 cd = &per_cpu(mips_clockevent_device, cpu);
463
464 cd->name = "MIPS";
465 cd->features = CLOCK_EVT_FEAT_ONESHOT;
466
467 /* Calculate the min / max delta */
468 cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
469 cd->shift = 32;
470 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
471 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
472
473 cd->rating = 300;
474 cd->irq = irq;
475#ifdef CONFIG_MIPS_MT_SMTC
476 cd->cpumask = CPU_MASK_ALL;
477#else
478 cd->cpumask = cpumask_of_cpu(cpu);
479#endif
480 cd->set_next_event = mips_next_event;
481 cd->set_mode = mips_set_mode;
482 cd->event_handler = mips_event_handler;
483
484 clockevents_register_device(cd);
485
486 if (!cp0_timer_irq_installed) {
487#ifdef CONFIG_MIPS_MT_SMTC
488#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
489 setup_irq_smtc(irq, &timer_irqaction, CPUCTR_IMASKBIT);
490#else
491 setup_irq(irq, &timer_irqaction);
492#endif /* CONFIG_MIPS_MT_SMTC */
493 cp0_timer_irq_installed = 1;
494 }
495} 226}
496 227
497void __init time_init(void) 228void __init time_init(void)
@@ -512,14 +243,6 @@ void __init time_init(void)
512 if (!clocksource_mips.read) { 243 if (!clocksource_mips.read) {
513 /* No external high precision timer -- use R4k. */ 244 /* No external high precision timer -- use R4k. */
514 clocksource_mips.read = c0_hpt_read; 245 clocksource_mips.read = c0_hpt_read;
515
516 if (!mips_timer_state) {
517 /* No external timer interrupt -- use R4k. */
518 mips_timer_ack = c0_timer_ack;
519 /* Calculate cache parameters. */
520 cycles_per_jiffy =
521 (mips_hpt_frequency + HZ / 2) / HZ;
522 }
523 } 246 }
524 if (!mips_hpt_frequency) 247 if (!mips_hpt_frequency)
525 mips_hpt_frequency = calibrate_hpt(); 248 mips_hpt_frequency = calibrate_hpt();
@@ -528,29 +251,8 @@ void __init time_init(void)
528 printk("Using %u.%03u MHz high precision timer.\n", 251 printk("Using %u.%03u MHz high precision timer.\n",
529 ((mips_hpt_frequency + 500) / 1000) / 1000, 252 ((mips_hpt_frequency + 500) / 1000) / 1000,
530 ((mips_hpt_frequency + 500) / 1000) % 1000); 253 ((mips_hpt_frequency + 500) / 1000) % 1000);
531
532#ifdef CONFIG_IRQ_CPU
533 setup_irq(MIPS_CPU_IRQ_BASE + 7, &timer_irqaction);
534#endif
535 } 254 }
536 255
537 if (!mips_timer_ack)
538 /* No timer interrupt ack (e.g. i8254). */
539 mips_timer_ack = null_timer_ack;
540
541 /*
542 * Call board specific timer interrupt setup.
543 *
544 * this pointer must be setup in machine setup routine.
545 *
546 * Even if a machine chooses to use a low-level timer interrupt,
547 * it still needs to setup the timer_irqaction.
548 * In that case, it might be better to set timer_irqaction.handler
549 * to be NULL function so that we are sure the high-level code
550 * is not invoked accidentally.
551 */
552 plat_timer_setup(&timer_irqaction);
553
554 init_mips_clocksource(); 256 init_mips_clocksource();
555 mips_clockevent_init(); 257 mips_clockevent_init();
556} 258}
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index bbf01b81a4ff..fa500787152d 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -314,7 +314,7 @@ void show_registers(const struct pt_regs *regs)
314 __show_regs(regs); 314 __show_regs(regs);
315 print_modules(); 315 print_modules();
316 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", 316 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
317 current->comm, current->pid, current_thread_info(), current); 317 current->comm, task_pid_nr(current), current_thread_info(), current);
318 show_stacktrace(current, regs); 318 show_stacktrace(current, regs);
319 show_code((unsigned int __user *) regs->cp0_epc); 319 show_code((unsigned int __user *) regs->cp0_epc);
320 printk("\n"); 320 printk("\n");
@@ -1336,6 +1336,17 @@ extern void cpu_cache_init(void);
1336extern void tlb_init(void); 1336extern void tlb_init(void);
1337extern void flush_tlb_handlers(void); 1337extern void flush_tlb_handlers(void);
1338 1338
1339/*
1340 * Timer interrupt
1341 */
1342int cp0_compare_irq;
1343
1344/*
1345 * Performance counter IRQ or -1 if shared with timer
1346 */
1347int cp0_perfcount_irq;
1348EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1349
1339void __init per_cpu_trap_init(void) 1350void __init per_cpu_trap_init(void)
1340{ 1351{
1341 unsigned int cpu = smp_processor_id(); 1352 unsigned int cpu = smp_processor_id();
diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c
index 09314a20f9fb..2cc6745991ab 100644
--- a/arch/mips/lemote/lm2e/setup.c
+++ b/arch/mips/lemote/lm2e/setup.c
@@ -53,11 +53,6 @@ unsigned long bus_clock;
53unsigned int memsize; 53unsigned int memsize;
54unsigned int highmemsize = 0; 54unsigned int highmemsize = 0;
55 55
56void __init plat_timer_setup(struct irqaction *irq)
57{
58 setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
59}
60
61void __init plat_time_init(void) 56void __init plat_time_init(void)
62{ 57{
63 /* setup mips r4k timer */ 58 /* setup mips r4k timer */
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 5699c7713e2f..fa636fc6b7b9 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -173,7 +173,7 @@ no_context:
173 */ 173 */
174out_of_memory: 174out_of_memory:
175 up_read(&mm->mmap_sem); 175 up_read(&mm->mmap_sem);
176 if (is_init(tsk)) { 176 if (is_global_init(tsk)) {
177 yield(); 177 yield();
178 down_read(&mm->mmap_sem); 178 down_read(&mm->mmap_sem);
179 goto survive; 179 goto survive;
diff --git a/arch/mips/oprofile/Kconfig b/arch/mips/oprofile/Kconfig
deleted file mode 100644
index fb6f235348b0..000000000000
--- a/arch/mips/oprofile/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
1
2menu "Profiling support"
3 depends on EXPERIMENTAL
4
5config PROFILING
6 bool "Profiling support (EXPERIMENTAL)"
7 help
8 Say Y here to enable the extended profiling support mechanisms used
9 by profilers such as OProfile.
10
11
12config OPROFILE
13 tristate "OProfile system profiling (EXPERIMENTAL)"
14 depends on PROFILING && !MIPS_MT_SMTC && EXPERIMENTAL
15 help
16 OProfile is a profiling system capable of profiling the
17 whole system, include the kernel, kernel modules, libraries,
18 and applications.
19
20 If unsure, say N.
21
22endmenu
23
diff --git a/arch/mips/pci/pci-excite.c b/arch/mips/pci/pci-excite.c
index 3c86c77cb74f..8a56876afcc6 100644
--- a/arch/mips/pci/pci-excite.c
+++ b/arch/mips/pci/pci-excite.c
@@ -131,7 +131,7 @@ static int __init basler_excite_pci_setup(void)
131 ocd_writel(0x00000000, bar + 0x100); 131 ocd_writel(0x00000000, bar + 0x100);
132 } 132 }
133 133
134 /* Finally, enable the PCI interupt */ 134 /* Finally, enable the PCI interrupt */
135#if USB_IRQ > 7 135#if USB_IRQ > 7
136 set_c0_intcontrol(1 << USB_IRQ); 136 set_c0_intcontrol(1 << USB_IRQ);
137#else 137#else
diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig
index abbd0bbfabd7..6b293ce0935f 100644
--- a/arch/mips/pmc-sierra/Kconfig
+++ b/arch/mips/pmc-sierra/Kconfig
@@ -4,11 +4,13 @@ choice
4 4
5config PMC_MSP4200_EVAL 5config PMC_MSP4200_EVAL
6 bool "PMC-Sierra MSP4200 Eval Board" 6 bool "PMC-Sierra MSP4200 Eval Board"
7 select CEVT_R4K
7 select IRQ_MSP_SLP 8 select IRQ_MSP_SLP
8 select HW_HAS_PCI 9 select HW_HAS_PCI
9 10
10config PMC_MSP4200_GW 11config PMC_MSP4200_GW
11 bool "PMC-Sierra MSP4200 VoIP Gateway" 12 bool "PMC-Sierra MSP4200 VoIP Gateway"
13 select CEVT_R4K
12 select IRQ_MSP_SLP 14 select IRQ_MSP_SLP
13 select HW_HAS_PCI 15 select HW_HAS_PCI
14 16
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c
index f221d4763625..7cfeda5a651b 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_time.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c
@@ -86,8 +86,5 @@ void __init plat_timer_setup(struct irqaction *irq)
86#ifdef CONFIG_IRQ_MSP_CIC 86#ifdef CONFIG_IRQ_MSP_CIC
87 /* we are using the vpe0 counter for timer interrupts */ 87 /* we are using the vpe0 counter for timer interrupts */
88 setup_irq(MSP_INT_VPE0_TIMER, irq); 88 setup_irq(MSP_INT_VPE0_TIMER, irq);
89#else
90 /* we are using the mips counter for timer interrupts */
91 setup_irq(MSP_INT_TIMER, irq);
92#endif 89#endif
93} 90}
diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c
index 015fcc363dc0..855977ca51cd 100644
--- a/arch/mips/pmc-sierra/yosemite/setup.c
+++ b/arch/mips/pmc-sierra/yosemite/setup.c
@@ -137,11 +137,6 @@ int rtc_mips_set_time(unsigned long tim)
137 return 0; 137 return 0;
138} 138}
139 139
140void __init plat_timer_setup(struct irqaction *irq)
141{
142 setup_irq(7, irq);
143}
144
145void __init plat_time_init(void) 140void __init plat_time_init(void)
146{ 141{
147 mips_hpt_frequency = cpu_clock_freq / 2; 142 mips_hpt_frequency = cpu_clock_freq / 2;
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 856649cf9f1e..1bb692a3b319 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -374,14 +374,13 @@ int __devinit request_bridge_irq(struct bridge_controller *bc)
374 return irq; 374 return irq;
375} 375}
376 376
377extern void ip27_rt_timer_interrupt(void);
378
379asmlinkage void plat_irq_dispatch(void) 377asmlinkage void plat_irq_dispatch(void)
380{ 378{
381 unsigned long pending = read_c0_cause() & read_c0_status(); 379 unsigned long pending = read_c0_cause() & read_c0_status();
380 extern unsigned int rt_timer_irq;
382 381
383 if (pending & CAUSEF_IP4) 382 if (pending & CAUSEF_IP4)
384 ip27_rt_timer_interrupt(); 383 do_IRQ(rt_timer_irq);
385 else if (pending & CAUSEF_IP2) /* PI_INT_PEND_0 or CC_PEND_{A|B} */ 384 else if (pending & CAUSEF_IP2) /* PI_INT_PEND_0 or CC_PEND_{A|B} */
386 ip27_do_irq_mask0(); 385 ip27_do_irq_mask0();
387 else if (pending & CAUSEF_IP3) /* PI_INT_PEND_1 */ 386 else if (pending & CAUSEF_IP3) /* PI_INT_PEND_1 */
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index b7b3479b6bce..d467bf4f6c3f 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -3,6 +3,7 @@
3 * Copytight (C) 1999, 2000 Silicon Graphics, Inc. 3 * Copytight (C) 1999, 2000 Silicon Graphics, Inc.
4 */ 4 */
5#include <linux/bcd.h> 5#include <linux/bcd.h>
6#include <linux/clockchips.h>
6#include <linux/init.h> 7#include <linux/init.h>
7#include <linux/kernel.h> 8#include <linux/kernel.h>
8#include <linux/sched.h> 9#include <linux/sched.h>
@@ -25,22 +26,8 @@
25#include <asm/sn/sn0/ip27.h> 26#include <asm/sn/sn0/ip27.h>
26#include <asm/sn/sn0/hub.h> 27#include <asm/sn/sn0/hub.h>
27 28
28/*
29 * This is a hack; we really need to figure these values out dynamically
30 *
31 * Since 800 ns works very well with various HUB frequencies, such as
32 * 360, 380, 390 and 400 MHZ, we use 800 ns rtc cycle time.
33 *
34 * Ralf: which clock rate is used to feed the counter?
35 */
36#define NSEC_PER_CYCLE 800
37#define CYCLES_PER_SEC (NSEC_PER_SEC/NSEC_PER_CYCLE)
38#define CYCLES_PER_JIFFY (CYCLES_PER_SEC/HZ)
39
40#define TICK_SIZE (tick_nsec / 1000) 29#define TICK_SIZE (tick_nsec / 1000)
41 30
42static unsigned long ct_cur[NR_CPUS]; /* What counter should be at next timer irq */
43
44#if 0 31#if 0
45static int set_rtc_mmss(unsigned long nowtime) 32static int set_rtc_mmss(unsigned long nowtime)
46{ 33{
@@ -86,36 +73,6 @@ static int set_rtc_mmss(unsigned long nowtime)
86} 73}
87#endif 74#endif
88 75
89static unsigned int rt_timer_irq;
90
91void ip27_rt_timer_interrupt(void)
92{
93 int cpu = smp_processor_id();
94 int cpuA = cputoslice(cpu) == 0;
95 unsigned int irq = rt_timer_irq;
96
97 irq_enter();
98 write_seqlock(&xtime_lock);
99
100again:
101 LOCAL_HUB_S(cpuA ? PI_RT_PEND_A : PI_RT_PEND_B, 0); /* Ack */
102 ct_cur[cpu] += CYCLES_PER_JIFFY;
103 LOCAL_HUB_S(cpuA ? PI_RT_COMPARE_A : PI_RT_COMPARE_B, ct_cur[cpu]);
104
105 if (LOCAL_HUB_L(PI_RT_COUNT) >= ct_cur[cpu])
106 goto again;
107
108 kstat_this_cpu.irqs[irq]++; /* kstat only for bootcpu? */
109
110 if (cpu == 0)
111 do_timer(1);
112
113 update_process_times(user_mode(get_irq_regs()));
114
115 write_sequnlock(&xtime_lock);
116 irq_exit();
117}
118
119/* Includes for ioc3_init(). */ 76/* Includes for ioc3_init(). */
120#include <asm/sn/types.h> 77#include <asm/sn/types.h>
121#include <asm/sn/sn0/addrs.h> 78#include <asm/sn/sn0/addrs.h>
@@ -154,6 +111,46 @@ unsigned long read_persistent_clock(void)
154 return mktime(year, month, date, hour, min, sec); 111 return mktime(year, month, date, hour, min, sec);
155} 112}
156 113
114static int rt_set_next_event(unsigned long delta,
115 struct clock_event_device *evt)
116{
117 unsigned int cpu = smp_processor_id();
118 int slice = cputoslice(cpu) == 0;
119 unsigned long cnt;
120
121 cnt = LOCAL_HUB_L(PI_RT_COUNT);
122 cnt += delta;
123 LOCAL_HUB_S(slice ? PI_RT_COMPARE_A : PI_RT_COMPARE_B, cnt);
124
125 return LOCAL_HUB_L(PI_RT_COUNT) >= cnt ? -ETIME : 0;
126}
127
128static void rt_set_mode(enum clock_event_mode mode,
129 struct clock_event_device *evt)
130{
131 switch (mode) {
132 case CLOCK_EVT_MODE_PERIODIC:
133 /* The only mode supported */
134 break;
135
136 case CLOCK_EVT_MODE_UNUSED:
137 case CLOCK_EVT_MODE_SHUTDOWN:
138 case CLOCK_EVT_MODE_ONESHOT:
139 case CLOCK_EVT_MODE_RESUME:
140 /* Nothing to do */
141 break;
142 }
143}
144
145struct clock_event_device rt_clock_event_device = {
146 .name = "HUB-RT",
147 .features = CLOCK_EVT_FEAT_ONESHOT,
148
149 .rating = 300,
150 .set_next_event = rt_set_next_event,
151 .set_mode = rt_set_mode,
152};
153
157static void enable_rt_irq(unsigned int irq) 154static void enable_rt_irq(unsigned int irq)
158{ 155{
159} 156}
@@ -171,6 +168,20 @@ static struct irq_chip rt_irq_type = {
171 .eoi = enable_rt_irq, 168 .eoi = enable_rt_irq,
172}; 169};
173 170
171unsigned int rt_timer_irq;
172
173static irqreturn_t ip27_rt_timer_interrupt(int irq, void *dev_id)
174{
175 struct clock_event_device *cd = &rt_clock_event_device;
176 unsigned int cpu = smp_processor_id();
177 int slice = cputoslice(cpu) == 0;
178
179 LOCAL_HUB_S(slice ? PI_RT_PEND_A : PI_RT_PEND_B, 0); /* Ack */
180 cd->event_handler(cd);
181
182 return IRQ_HANDLED;
183}
184
174static struct irqaction rt_irqaction = { 185static struct irqaction rt_irqaction = {
175 .handler = (irq_handler_t) ip27_rt_timer_interrupt, 186 .handler = (irq_handler_t) ip27_rt_timer_interrupt,
176 .flags = IRQF_DISABLED, 187 .flags = IRQF_DISABLED,
@@ -178,26 +189,43 @@ static struct irqaction rt_irqaction = {
178 .name = "timer" 189 .name = "timer"
179}; 190};
180 191
181void __init plat_timer_setup(struct irqaction *irq) 192/*
193 * This is a hack; we really need to figure these values out dynamically
194 *
195 * Since 800 ns works very well with various HUB frequencies, such as
196 * 360, 380, 390 and 400 MHZ, we use 800 ns rtc cycle time.
197 *
198 * Ralf: which clock rate is used to feed the counter?
199 */
200#define NSEC_PER_CYCLE 800
201#define CYCLES_PER_SEC (NSEC_PER_SEC / NSEC_PER_CYCLE)
202
203static void __init ip27_rt_clock_event_init(void)
182{ 204{
183 int irqno = allocate_irqno(); 205 struct clock_event_device *cd = &rt_clock_event_device;
206 unsigned int cpu = smp_processor_id();
207 int irq = allocate_irqno();
184 208
185 if (irqno < 0) 209 if (irq < 0)
186 panic("Can't allocate interrupt number for timer interrupt"); 210 panic("Can't allocate interrupt number for timer interrupt");
187 211
188 set_irq_chip_and_handler(irqno, &rt_irq_type, handle_percpu_irq); 212 rt_timer_irq = irq;
189 213
190 /* over-write the handler, we use our own way */ 214 cd->irq = irq,
191 irq->handler = no_action; 215 cd->cpumask = cpumask_of_cpu(cpu),
192 216
193 /* setup irqaction */
194 irq_desc[irqno].status |= IRQ_PER_CPU;
195
196 rt_timer_irq = irqno;
197 /* 217 /*
198 * Only needed to get /proc/interrupt to display timer irq stats 218 * Calculate the min / max delta
199 */ 219 */
200 setup_irq(irqno, &rt_irqaction); 220 cd->mult =
221 div_sc((unsigned long) CYCLES_PER_SEC, NSEC_PER_SEC, 32);
222 cd->shift = 32;
223 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
224 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
225 clockevents_register_device(cd);
226
227 set_irq_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq);
228 setup_irq(irq, &rt_irqaction);
201} 229}
202 230
203static cycle_t hub_rt_read(void) 231static cycle_t hub_rt_read(void)
@@ -206,7 +234,7 @@ static cycle_t hub_rt_read(void)
206} 234}
207 235
208struct clocksource ht_rt_clocksource = { 236struct clocksource ht_rt_clocksource = {
209 .name = "HUB", 237 .name = "HUB-RT",
210 .rating = 200, 238 .rating = 200,
211 .read = hub_rt_read, 239 .read = hub_rt_read,
212 .mask = CLOCKSOURCE_MASK(52), 240 .mask = CLOCKSOURCE_MASK(52),
@@ -214,11 +242,17 @@ struct clocksource ht_rt_clocksource = {
214 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 242 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
215}; 243};
216 244
217void __init plat_time_init(void) 245static void __init ip27_rt_clocksource_init(void)
218{ 246{
219 clocksource_register(&ht_rt_clocksource); 247 clocksource_register(&ht_rt_clocksource);
220} 248}
221 249
250void __init plat_time_init(void)
251{
252 ip27_rt_clock_event_init();
253 ip27_rt_clocksource_init();
254}
255
222void __init cpu_time_init(void) 256void __init cpu_time_init(void)
223{ 257{
224 lboard_t *board; 258 lboard_t *board;
@@ -248,17 +282,12 @@ void __init hub_rtc_init(cnodeid_t cnode)
248 * node and timeouts will not happen there. 282 * node and timeouts will not happen there.
249 */ 283 */
250 if (get_compact_nodeid() == cnode) { 284 if (get_compact_nodeid() == cnode) {
251 int cpu = smp_processor_id();
252 LOCAL_HUB_S(PI_RT_EN_A, 1); 285 LOCAL_HUB_S(PI_RT_EN_A, 1);
253 LOCAL_HUB_S(PI_RT_EN_B, 1); 286 LOCAL_HUB_S(PI_RT_EN_B, 1);
254 LOCAL_HUB_S(PI_PROF_EN_A, 0); 287 LOCAL_HUB_S(PI_PROF_EN_A, 0);
255 LOCAL_HUB_S(PI_PROF_EN_B, 0); 288 LOCAL_HUB_S(PI_PROF_EN_B, 0);
256 ct_cur[cpu] = CYCLES_PER_JIFFY;
257 LOCAL_HUB_S(PI_RT_COMPARE_A, ct_cur[cpu]);
258 LOCAL_HUB_S(PI_RT_COUNT, 0); 289 LOCAL_HUB_S(PI_RT_COUNT, 0);
259 LOCAL_HUB_S(PI_RT_PEND_A, 0); 290 LOCAL_HUB_S(PI_RT_PEND_A, 0);
260 LOCAL_HUB_S(PI_RT_COMPARE_B, ct_cur[cpu]);
261 LOCAL_HUB_S(PI_RT_COUNT, 0);
262 LOCAL_HUB_S(PI_RT_PEND_B, 0); 291 LOCAL_HUB_S(PI_RT_PEND_B, 0);
263 } 292 }
264} 293}
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
index fc75bfcb0c0e..1024bf40bd9e 100644
--- a/arch/mips/sgi-ip32/ip32-setup.c
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -80,12 +80,6 @@ void __init plat_time_init(void)
80 printk("%d MHz CPU detected\n", mips_hpt_frequency * 2 / 1000000); 80 printk("%d MHz CPU detected\n", mips_hpt_frequency * 2 / 1000000);
81} 81}
82 82
83void __init plat_timer_setup(struct irqaction *irq)
84{
85 irq->handler = no_action;
86 setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
87}
88
89void __init plat_mem_setup(void) 83void __init plat_mem_setup(void)
90{ 84{
91 board_be_init = ip32_be_init; 85 board_be_init = ip32_be_init;
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index 6eac36d1b8c8..02b266a31c46 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -69,8 +69,9 @@ void bcm1480_smp_init(void)
69 69
70void bcm1480_smp_finish(void) 70void bcm1480_smp_finish(void)
71{ 71{
72 extern void bcm1480_time_init(void); 72 extern void sb1480_clockevent_init(void);
73 bcm1480_time_init(); 73
74 sb1480_clockevent_init();
74 local_irq_enable(); 75 local_irq_enable();
75} 76}
76 77
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index 5b4bfbbb5a24..c730744aa474 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -27,9 +27,8 @@
27 */ 27 */
28#include <linux/clockchips.h> 28#include <linux/clockchips.h>
29#include <linux/interrupt.h> 29#include <linux/interrupt.h>
30#include <linux/sched.h> 30#include <linux/percpu.h>
31#include <linux/spinlock.h> 31#include <linux/spinlock.h>
32#include <linux/kernel_stat.h>
33 32
34#include <asm/irq.h> 33#include <asm/irq.h>
35#include <asm/addrspace.h> 34#include <asm/addrspace.h>
@@ -101,25 +100,36 @@ static void sibyte_set_mode(enum clock_event_mode mode,
101 break; 100 break;
102 101
103 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ 102 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
103 case CLOCK_EVT_MODE_RESUME:
104 ; 104 ;
105 } 105 }
106} 106}
107 107
108struct clock_event_device sibyte_hpt_clockevent = { 108static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
109 .name = "bcm1480-counter", 109{
110 .features = CLOCK_EVT_FEAT_PERIODIC, 110 unsigned int cpu = smp_processor_id();
111 .set_mode = sibyte_set_mode, 111 void __iomem *timer_init;
112 .shift = 32, 112 unsigned int cnt;
113 .irq = 0, 113 int res;
114}; 114
115 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
116 cnt = __raw_readq(timer_init);
117 cnt += delta;
118 __raw_writeq(cnt, timer_init);
119 res = ((long)(__raw_readq(timer_init) - cnt ) > 0) ? -ETIME : 0;
120
121 return res;
122}
123
124static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
115 125
116static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) 126static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
117{ 127{
118 struct clock_event_device *cd = &sibyte_hpt_clockevent;
119 unsigned int cpu = smp_processor_id(); 128 unsigned int cpu = smp_processor_id();
129 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
120 130
121 /* Reset the timer */ 131 /* Reset the timer */
122 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, 132 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
123 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 133 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
124 cd->event_handler(cd); 134 cd->event_handler(cd);
125 135
@@ -140,24 +150,21 @@ static struct irqaction sibyte_counter_irqaction = {
140 * called directly from irq_handler.S when IP[4] is set during an 150 * called directly from irq_handler.S when IP[4] is set during an
141 * interrupt 151 * interrupt
142 */ 152 */
143static void __init sb1480_clockevent_init(void) 153void __cpuinit sb1480_clockevent_init(void)
144{ 154{
145 unsigned int cpu = smp_processor_id(); 155 unsigned int cpu = smp_processor_id();
146 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; 156 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
157 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
147 158
148 setup_irq(irq, &sibyte_counter_irqaction); 159 cd->name = "bcm1480-counter";
149} 160 cd->features = CLOCK_EVT_FEAT_PERIODIC |
161 CLOCK_EVT_MODE_ONESHOT;
162 cd->set_next_event = sibyte_next_event;
163 cd->set_mode = sibyte_set_mode;
164 cd->irq = irq;
165 clockevent_set_clock(cd, BCM1480_HPT_VALUE);
150 166
151void bcm1480_timer_interrupt(void) 167 setup_irq(irq, &sibyte_counter_irqaction);
152{
153 int cpu = smp_processor_id();
154 int irq = K_BCM1480_INT_TIMER_0 + cpu;
155
156 /* Reset the timer */
157 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
158 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
159
160 ll_timer_interrupt(irq);
161} 168}
162 169
163static cycle_t bcm1480_hpt_read(void) 170static cycle_t bcm1480_hpt_read(void)
@@ -168,9 +175,26 @@ static cycle_t bcm1480_hpt_read(void)
168 return (jiffies + 1) * (BCM1480_HPT_VALUE / HZ) - count; 175 return (jiffies + 1) * (BCM1480_HPT_VALUE / HZ) - count;
169} 176}
170 177
178struct clocksource bcm1480_clocksource = {
179 .name = "MIPS",
180 .rating = 200,
181 .read = bcm1480_hpt_read,
182 .mask = CLOCKSOURCE_MASK(32),
183 .shift = 32,
184 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
185};
186
187void __init sb1480_clocksource_init(void)
188{
189 struct clocksource *cs = &bcm1480_clocksource;
190
191 clocksource_set_clock(cs, BCM1480_HPT_VALUE);
192 clocksource_register(cs);
193}
194
171void __init bcm1480_hpt_setup(void) 195void __init bcm1480_hpt_setup(void)
172{ 196{
173 clocksource_mips.read = bcm1480_hpt_read;
174 mips_hpt_frequency = BCM1480_HPT_VALUE; 197 mips_hpt_frequency = BCM1480_HPT_VALUE;
198 sb1480_clocksource_init();
175 sb1480_clockevent_init(); 199 sb1480_clockevent_init();
176} 200}
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 7659174819c6..500d17e84c09 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -400,43 +400,11 @@ static void sb1250_kgdb_interrupt(void)
400 400
401#endif /* CONFIG_KGDB */ 401#endif /* CONFIG_KGDB */
402 402
403static inline void sb1250_timer_interrupt(void)
404{
405 int cpu = smp_processor_id();
406 int irq = K_INT_TIMER_0 + cpu;
407
408 irq_enter();
409 kstat_this_cpu.irqs[irq]++;
410
411 write_seqlock(&xtime_lock);
412
413 /* ACK interrupt */
414 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
415 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
416
417 /*
418 * call the generic timer interrupt handling
419 */
420 do_timer(1);
421
422 write_sequnlock(&xtime_lock);
423
424 /*
425 * In UP mode, we call local_timer_interrupt() to do profiling
426 * and process accouting.
427 *
428 * In SMP mode, local_timer_interrupt() is invoked by appropriate
429 * low-level local timer interrupt handler.
430 */
431 local_timer_interrupt(irq);
432
433 irq_exit();
434}
435
436extern void sb1250_mailbox_interrupt(void); 403extern void sb1250_mailbox_interrupt(void);
437 404
438asmlinkage void plat_irq_dispatch(void) 405asmlinkage void plat_irq_dispatch(void)
439{ 406{
407 unsigned int cpu = smp_processor_id();
440 unsigned int pending; 408 unsigned int pending;
441 409
442 /* 410 /*
@@ -454,7 +422,7 @@ asmlinkage void plat_irq_dispatch(void)
454 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */ 422 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
455 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 423 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
456 else if (pending & CAUSEF_IP4) 424 else if (pending & CAUSEF_IP4)
457 sb1250_timer_interrupt(); 425 do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */
458 426
459#ifdef CONFIG_SMP 427#ifdef CONFIG_SMP
460 else if (pending & CAUSEF_IP3) 428 else if (pending & CAUSEF_IP3)
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
index c38e1f34460d..aaa4f30dda79 100644
--- a/arch/mips/sibyte/sb1250/smp.c
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -57,8 +57,9 @@ void sb1250_smp_init(void)
57 57
58void sb1250_smp_finish(void) 58void sb1250_smp_finish(void)
59{ 59{
60 extern void sb1250_time_init(void); 60 extern void sb1250_clockevent_init(void);
61 sb1250_time_init(); 61
62 sb1250_clockevent_init();
62 local_irq_enable(); 63 local_irq_enable();
63} 64}
64 65
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index fe11fed8e0d7..9ef54628bc9c 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -100,6 +100,7 @@ static void sibyte_set_mode(enum clock_event_mode mode,
100 break; 100 break;
101 101
102 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ 102 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
103 case CLOCK_EVT_MODE_RESUME:
103 ; 104 ;
104 } 105 }
105} 106}
@@ -144,79 +145,7 @@ static struct irqaction sibyte_irqaction = {
144 .name = "timer", 145 .name = "timer",
145}; 146};
146 147
147/* 148void __cpuinit sb1250_clockevent_init(void)
148 * The general purpose timer ticks at 1 Mhz independent if
149 * the rest of the system
150 */
151static void sibyte_set_mode(enum clock_event_mode mode,
152 struct clock_event_device *evt)
153{
154 unsigned int cpu = smp_processor_id();
155 void __iomem *timer_cfg, *timer_init;
156
157 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
158 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
159
160 switch (mode) {
161 case CLOCK_EVT_MODE_PERIODIC:
162 __raw_writeq(0, timer_cfg);
163 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
164 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
165 timer_cfg);
166 break;
167
168 case CLOCK_EVT_MODE_ONESHOT:
169 /* Stop the timer until we actually program a shot */
170 case CLOCK_EVT_MODE_SHUTDOWN:
171 __raw_writeq(0, timer_cfg);
172 break;
173
174 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
175 ;
176 }
177}
178
179static int
180sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
181{
182 unsigned int cpu = smp_processor_id();
183 void __iomem *timer_cfg, *timer_init;
184
185 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
186 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
187
188 __raw_writeq(0, timer_cfg);
189 __raw_writeq(delta, timer_init);
190 __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
191
192 return 0;
193}
194
195struct clock_event_device sibyte_hpt_clockevent = {
196 .name = "sb1250-counter",
197 .features = CLOCK_EVT_FEAT_PERIODIC,
198 .set_mode = sibyte_set_mode,
199 .set_next_event = sibyte_next_event,
200 .shift = 32,
201 .irq = 0,
202};
203
204static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
205{
206 struct clock_event_device *cd = &sibyte_hpt_clockevent;
207
208 cd->event_handler(cd);
209
210 return IRQ_HANDLED;
211}
212
213static struct irqaction sibyte_irqaction = {
214 .handler = sibyte_counter_handler,
215 .flags = IRQF_DISABLED | IRQF_PERCPU,
216 .name = "timer",
217};
218
219static void __init sb1250_clockevent_init(void)
220{ 149{
221 struct clock_event_device *cd = &sibyte_hpt_clockevent; 150 struct clock_event_device *cd = &sibyte_hpt_clockevent;
222 unsigned int cpu = smp_processor_id(); 151 unsigned int cpu = smp_processor_id();
@@ -249,12 +178,6 @@ static void __init sb1250_clockevent_init(void)
249 clockevents_register_device(cd); 178 clockevents_register_device(cd);
250} 179}
251 180
252void __init plat_time_init(void)
253{
254 sb1250_clocksource_init();
255 sb1250_clockevent_init();
256}
257
258/* 181/*
259 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over 182 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
260 * again. 183 * again.
@@ -267,3 +190,26 @@ static cycle_t sb1250_hpt_read(void)
267 190
268 return SB1250_HPT_VALUE - count; 191 return SB1250_HPT_VALUE - count;
269} 192}
193
194struct clocksource bcm1250_clocksource = {
195 .name = "MIPS",
196 .rating = 200,
197 .read = sb1250_hpt_read,
198 .mask = CLOCKSOURCE_MASK(32),
199 .shift = 32,
200 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
201};
202
203void __init sb1250_clocksource_init(void)
204{
205 struct clocksource *cs = &bcm1250_clocksource;
206
207 clocksource_set_clock(cs, V_SCD_TIMER_FREQ);
208 clocksource_register(cs);
209}
210
211void __init plat_time_init(void)
212{
213 sb1250_clocksource_init();
214 sb1250_clockevent_init();
215}
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index 8b3ef0e4cd55..080c966263b7 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -69,31 +69,6 @@ const char *get_system_type(void)
69 return "SiByte " SIBYTE_BOARD_NAME; 69 return "SiByte " SIBYTE_BOARD_NAME;
70} 70}
71 71
72void __init plat_time_init(void)
73{
74#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
75 /* Setup HPT */
76 sb1250_hpt_setup();
77#endif
78}
79
80void __init plat_timer_setup(struct irqaction *irq)
81{
82 /*
83 * we don't set up irqaction, because we will deliver timer
84 * interrupts through low-level (direct) meachanism.
85 */
86
87 /* We only need to setup the generic timer */
88#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
89 bcm1480_time_init();
90#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
91 sb1250_time_init();
92#else
93#error invalid SiByte board configuration
94#endif
95}
96
97int swarm_be_handler(struct pt_regs *regs, int is_fixup) 72int swarm_be_handler(struct pt_regs *regs, int is_fixup)
98{ 73{
99 if (!is_fixup && (regs->cp0_cause & 4)) { 74 if (!is_fixup && (regs->cp0_cause & 4)) {
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 39bb15f1f2a6..4df070f2ff5d 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -246,7 +246,7 @@ static void pcimt_hwint1(void)
246 /* 246 /*
247 * Note: ASIC PCI's builtin interrupt achknowledge feature is 247 * Note: ASIC PCI's builtin interrupt achknowledge feature is
248 * broken. Using it may result in loss of some or all i8259 248 * broken. Using it may result in loss of some or all i8259
249 * interupts, so don't use PCIMT_INT_ACKNOWLEDGE ... 249 * interrupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
250 */ 250 */
251 irq = i8259_irq(); 251 irq = i8259_irq();
252 if (unlikely(irq < 0)) 252 if (unlikely(irq < 0))
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index b80877349d38..0910b35cb71f 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -121,15 +121,6 @@ void __init plat_time_init(void)
121 setup_pit_timer(); 121 setup_pit_timer();
122} 122}
123 123
124/*
125 * R4k counter based timer interrupt. Works on RM200-225 and possibly
126 * others but not on RM400
127 */
128static void __init sni_cpu_timer_setup(struct irqaction *irq)
129{
130 setup_irq(SNI_MIPS_IRQ_CPU_TIMER, irq);
131}
132
133void __init plat_timer_setup(struct irqaction *irq) 124void __init plat_timer_setup(struct irqaction *irq)
134{ 125{
135 switch (sni_brd_type) { 126 switch (sni_brd_type) {
@@ -139,15 +130,6 @@ void __init plat_timer_setup(struct irqaction *irq)
139 case SNI_BRD_MINITOWER: 130 case SNI_BRD_MINITOWER:
140 sni_a20r_timer_setup(irq); 131 sni_a20r_timer_setup(irq);
141 break; 132 break;
142
143 case SNI_BRD_PCI_TOWER:
144 case SNI_BRD_RM200:
145 case SNI_BRD_PCI_MTOWER:
146 case SNI_BRD_PCI_DESKTOP:
147 case SNI_BRD_PCI_TOWER_CPLUS:
148 case SNI_BRD_PCI_MTOWER_CPLUS:
149 sni_cpu_timer_setup(irq);
150 break;
151 } 133 }
152} 134}
153 135
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
index 8ce0989671d8..36c5f200eb3d 100644
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -72,22 +72,6 @@ void __init plat_time_init(void)
72#endif 72#endif
73} 73}
74 74
75void __init plat_timer_setup(struct irqaction *irq)
76{
77 setup_irq(TX4927_IRQ_CPU_TIMER, irq);
78
79#ifdef CONFIG_TOSHIBA_RBTX4927
80 {
81 extern void toshiba_rbtx4927_timer_setup(struct irqaction
82 *irq);
83 toshiba_rbtx4927_timer_setup(irq);
84 }
85#endif
86
87 return;
88}
89
90
91#ifdef DEBUG 75#ifdef DEBUG
92void print_cp0(char *key, int num, char *name, u32 val) 76void print_cp0(char *key, int num, char *name, u32 val)
93{ 77{
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index b97102a1c635..c7470fba6180 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -94,7 +94,6 @@
94#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 ) 94#define TOSHIBA_RBTX4927_SETUP_EFWFU ( 1 << 3 )
95#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 ) 95#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
96#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 ) 96#define TOSHIBA_RBTX4927_SETUP_TIME_INIT ( 1 << 5 )
97#define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 << 6 )
98#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 ) 97#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
99#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 ) 98#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
100#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 ) 99#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
@@ -108,7 +107,6 @@ static const u32 toshiba_rbtx4927_setup_debug_flag =
108 (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO | 107 (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
109 TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR | 108 TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
110 TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP | 109 TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
111 TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
112 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 | 110 | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
113 TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66); 111 TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
114#endif 112#endif
@@ -947,14 +945,6 @@ toshiba_rbtx4927_time_init(void)
947 945
948} 946}
949 947
950void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
951{
952 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
953 "-\n");
954 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
955 "+\n");
956}
957
958static int __init toshiba_rbtx4927_rtc_init(void) 948static int __init toshiba_rbtx4927_rtc_init(void)
959{ 949{
960 static struct resource __initdata res = { 950 static struct resource __initdata res = {
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
index ab4082267553..3ba4101d141e 100644
--- a/arch/mips/tx4938/common/setup.c
+++ b/arch/mips/tx4938/common/setup.c
@@ -24,7 +24,7 @@
24#include <linux/slab.h> 24#include <linux/slab.h>
25#include <linux/random.h> 25#include <linux/random.h>
26#include <linux/irq.h> 26#include <linux/irq.h>
27#include <asm/bitops.h> 27#include <linux/bitops.h>
28#include <asm/bootinfo.h> 28#include <asm/bootinfo.h>
29#include <asm/io.h> 29#include <asm/io.h>
30#include <asm/irq.h> 30#include <asm/irq.h>
@@ -43,8 +43,3 @@ plat_mem_setup(void)
43{ 43{
44 toshiba_rbtx4938_setup(); 44 toshiba_rbtx4938_setup();
45} 45}
46
47void __init plat_timer_setup(struct irqaction *irq)
48{
49 setup_irq(TX4938_IRQ_CPU_TIMER, irq);
50}
diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig
index 8f4d3e74c230..eeb089f20c0d 100644
--- a/arch/mips/vr41xx/Kconfig
+++ b/arch/mips/vr41xx/Kconfig
@@ -5,6 +5,7 @@ choice
5 5
6config CASIO_E55 6config CASIO_E55
7 bool "CASIO CASSIOPEIA E-10/15/55/65" 7 bool "CASIO CASSIOPEIA E-10/15/55/65"
8 select CEVT_R4K
8 select DMA_NONCOHERENT 9 select DMA_NONCOHERENT
9 select IRQ_CPU 10 select IRQ_CPU
10 select ISA 11 select ISA
@@ -13,6 +14,7 @@ config CASIO_E55
13 14
14config IBM_WORKPAD 15config IBM_WORKPAD
15 bool "IBM WorkPad z50" 16 bool "IBM WorkPad z50"
17 select CEVT_R4K
16 select DMA_NONCOHERENT 18 select DMA_NONCOHERENT
17 select IRQ_CPU 19 select IRQ_CPU
18 select ISA 20 select ISA
@@ -21,6 +23,7 @@ config IBM_WORKPAD
21 23
22config NEC_CMBVR4133 24config NEC_CMBVR4133
23 bool "NEC CMB-VR4133" 25 bool "NEC CMB-VR4133"
26 select CEVT_R4K
24 select DMA_NONCOHERENT 27 select DMA_NONCOHERENT
25 select IRQ_CPU 28 select IRQ_CPU
26 select HW_HAS_PCI 29 select HW_HAS_PCI
@@ -29,6 +32,7 @@ config NEC_CMBVR4133
29 32
30config TANBAC_TB022X 33config TANBAC_TB022X
31 bool "TANBAC VR4131 multichip module and TANBAC VR4131DIMM" 34 bool "TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
35 select CEVT_R4K
32 select DMA_NONCOHERENT 36 select DMA_NONCOHERENT
33 select IRQ_CPU 37 select IRQ_CPU
34 select HW_HAS_PCI 38 select HW_HAS_PCI
@@ -43,6 +47,7 @@ config TANBAC_TB022X
43 47
44config VICTOR_MPC30X 48config VICTOR_MPC30X
45 bool "Victor MP-C303/304" 49 bool "Victor MP-C303/304"
50 select CEVT_R4K
46 select DMA_NONCOHERENT 51 select DMA_NONCOHERENT
47 select IRQ_CPU 52 select IRQ_CPU
48 select HW_HAS_PCI 53 select HW_HAS_PCI
@@ -52,6 +57,7 @@ config VICTOR_MPC30X
52 57
53config ZAO_CAPCELLA 58config ZAO_CAPCELLA
54 bool "ZAO Networks Capcella" 59 bool "ZAO Networks Capcella"
60 select CEVT_R4K
55 select DMA_NONCOHERENT 61 select DMA_NONCOHERENT
56 select IRQ_CPU 62 select IRQ_CPU
57 select HW_HAS_PCI 63 select HW_HAS_PCI
diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c
index 407cec203b29..8d760df686c4 100644
--- a/arch/mips/vr41xx/common/init.c
+++ b/arch/mips/vr41xx/common/init.c
@@ -48,11 +48,6 @@ void __init plat_time_init(void)
48 mips_hpt_frequency = tclock / 4; 48 mips_hpt_frequency = tclock / 4;
49} 49}
50 50
51void __init plat_timer_setup(struct irqaction *irq)
52{
53 setup_irq(TIMER_IRQ, irq);
54}
55
56void __init plat_mem_setup(void) 51void __init plat_mem_setup(void)
57{ 52{
58 vr41xx_calculate_clock_frequency(); 53 vr41xx_calculate_clock_frequency();
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-07 14:20:39 -0400