diff options
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 75 | ||||
-rw-r--r-- | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 147 |
2 files changed, 221 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index c0e63334039b..1ac5704623f2 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | |||
@@ -120,6 +120,8 @@ enum bcm63xx_regs_set { | |||
120 | RSET_OHCI0, | 120 | RSET_OHCI0, |
121 | RSET_OHCI_PRIV, | 121 | RSET_OHCI_PRIV, |
122 | RSET_USBH_PRIV, | 122 | RSET_USBH_PRIV, |
123 | RSET_USBD, | ||
124 | RSET_USBDMA, | ||
123 | RSET_MPI, | 125 | RSET_MPI, |
124 | RSET_PCMCIA, | 126 | RSET_PCMCIA, |
125 | RSET_PCIE, | 127 | RSET_PCIE, |
@@ -162,6 +164,8 @@ enum bcm63xx_regs_set { | |||
162 | #define RSET_UDC_SIZE 256 | 164 | #define RSET_UDC_SIZE 256 |
163 | #define RSET_OHCI_SIZE 256 | 165 | #define RSET_OHCI_SIZE 256 |
164 | #define RSET_EHCI_SIZE 256 | 166 | #define RSET_EHCI_SIZE 256 |
167 | #define RSET_USBD_SIZE 256 | ||
168 | #define RSET_USBDMA_SIZE 1280 | ||
165 | #define RSET_PCMCIA_SIZE 12 | 169 | #define RSET_PCMCIA_SIZE 12 |
166 | #define RSET_M2M_SIZE 256 | 170 | #define RSET_M2M_SIZE 256 |
167 | #define RSET_ATM_SIZE 4096 | 171 | #define RSET_ATM_SIZE 4096 |
@@ -183,10 +187,11 @@ enum bcm63xx_regs_set { | |||
183 | #define BCM_6328_GPIO_BASE (0xb0000080) | 187 | #define BCM_6328_GPIO_BASE (0xb0000080) |
184 | #define BCM_6328_SPI_BASE (0xdeadbeef) | 188 | #define BCM_6328_SPI_BASE (0xdeadbeef) |
185 | #define BCM_6328_UDC0_BASE (0xdeadbeef) | 189 | #define BCM_6328_UDC0_BASE (0xdeadbeef) |
186 | #define BCM_6328_USBDMA_BASE (0xdeadbeef) | 190 | #define BCM_6328_USBDMA_BASE (0xb000c000) |
187 | #define BCM_6328_OHCI0_BASE (0xb0002600) | 191 | #define BCM_6328_OHCI0_BASE (0xb0002600) |
188 | #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) | 192 | #define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) |
189 | #define BCM_6328_USBH_PRIV_BASE (0xb0002700) | 193 | #define BCM_6328_USBH_PRIV_BASE (0xb0002700) |
194 | #define BCM_6328_USBD_BASE (0xb0002400) | ||
190 | #define BCM_6328_MPI_BASE (0xdeadbeef) | 195 | #define BCM_6328_MPI_BASE (0xdeadbeef) |
191 | #define BCM_6328_PCMCIA_BASE (0xdeadbeef) | 196 | #define BCM_6328_PCMCIA_BASE (0xdeadbeef) |
192 | #define BCM_6328_PCIE_BASE (0xb0e40000) | 197 | #define BCM_6328_PCIE_BASE (0xb0e40000) |
@@ -232,6 +237,7 @@ enum bcm63xx_regs_set { | |||
232 | #define BCM_6338_OHCI0_BASE (0xdeadbeef) | 237 | #define BCM_6338_OHCI0_BASE (0xdeadbeef) |
233 | #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) | 238 | #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) |
234 | #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) | 239 | #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) |
240 | #define BCM_6338_USBD_BASE (0xdeadbeef) | ||
235 | #define BCM_6338_MPI_BASE (0xfffe3160) | 241 | #define BCM_6338_MPI_BASE (0xfffe3160) |
236 | #define BCM_6338_PCMCIA_BASE (0xdeadbeef) | 242 | #define BCM_6338_PCMCIA_BASE (0xdeadbeef) |
237 | #define BCM_6338_PCIE_BASE (0xdeadbeef) | 243 | #define BCM_6338_PCIE_BASE (0xdeadbeef) |
@@ -286,6 +292,7 @@ enum bcm63xx_regs_set { | |||
286 | #define BCM_6345_OHCI0_BASE (0xfffe2100) | 292 | #define BCM_6345_OHCI0_BASE (0xfffe2100) |
287 | #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) | 293 | #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) |
288 | #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) | 294 | #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) |
295 | #define BCM_6345_USBD_BASE (0xdeadbeef) | ||
289 | #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) | 296 | #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) |
290 | #define BCM_6345_DSL_BASE (0xdeadbeef) | 297 | #define BCM_6345_DSL_BASE (0xdeadbeef) |
291 | #define BCM_6345_UBUS_BASE (0xdeadbeef) | 298 | #define BCM_6345_UBUS_BASE (0xdeadbeef) |
@@ -319,9 +326,11 @@ enum bcm63xx_regs_set { | |||
319 | #define BCM_6348_GPIO_BASE (0xfffe0400) | 326 | #define BCM_6348_GPIO_BASE (0xfffe0400) |
320 | #define BCM_6348_SPI_BASE (0xfffe0c00) | 327 | #define BCM_6348_SPI_BASE (0xfffe0c00) |
321 | #define BCM_6348_UDC0_BASE (0xfffe1000) | 328 | #define BCM_6348_UDC0_BASE (0xfffe1000) |
329 | #define BCM_6348_USBDMA_BASE (0xdeadbeef) | ||
322 | #define BCM_6348_OHCI0_BASE (0xfffe1b00) | 330 | #define BCM_6348_OHCI0_BASE (0xfffe1b00) |
323 | #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) | 331 | #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) |
324 | #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) | 332 | #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) |
333 | #define BCM_6348_USBD_BASE (0xdeadbeef) | ||
325 | #define BCM_6348_MPI_BASE (0xfffe2000) | 334 | #define BCM_6348_MPI_BASE (0xfffe2000) |
326 | #define BCM_6348_PCMCIA_BASE (0xfffe2054) | 335 | #define BCM_6348_PCMCIA_BASE (0xfffe2054) |
327 | #define BCM_6348_PCIE_BASE (0xdeadbeef) | 336 | #define BCM_6348_PCIE_BASE (0xdeadbeef) |
@@ -362,9 +371,11 @@ enum bcm63xx_regs_set { | |||
362 | #define BCM_6358_GPIO_BASE (0xfffe0080) | 371 | #define BCM_6358_GPIO_BASE (0xfffe0080) |
363 | #define BCM_6358_SPI_BASE (0xfffe0800) | 372 | #define BCM_6358_SPI_BASE (0xfffe0800) |
364 | #define BCM_6358_UDC0_BASE (0xfffe0800) | 373 | #define BCM_6358_UDC0_BASE (0xfffe0800) |
374 | #define BCM_6358_USBDMA_BASE (0xdeadbeef) | ||
365 | #define BCM_6358_OHCI0_BASE (0xfffe1400) | 375 | #define BCM_6358_OHCI0_BASE (0xfffe1400) |
366 | #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) | 376 | #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) |
367 | #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) | 377 | #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) |
378 | #define BCM_6358_USBD_BASE (0xdeadbeef) | ||
368 | #define BCM_6358_MPI_BASE (0xfffe1000) | 379 | #define BCM_6358_MPI_BASE (0xfffe1000) |
369 | #define BCM_6358_PCMCIA_BASE (0xfffe1054) | 380 | #define BCM_6358_PCMCIA_BASE (0xfffe1054) |
370 | #define BCM_6358_PCIE_BASE (0xdeadbeef) | 381 | #define BCM_6358_PCIE_BASE (0xdeadbeef) |
@@ -406,9 +417,11 @@ enum bcm63xx_regs_set { | |||
406 | #define BCM_6368_GPIO_BASE (0xb0000080) | 417 | #define BCM_6368_GPIO_BASE (0xb0000080) |
407 | #define BCM_6368_SPI_BASE (0xb0000800) | 418 | #define BCM_6368_SPI_BASE (0xb0000800) |
408 | #define BCM_6368_UDC0_BASE (0xdeadbeef) | 419 | #define BCM_6368_UDC0_BASE (0xdeadbeef) |
420 | #define BCM_6368_USBDMA_BASE (0xb0004800) | ||
409 | #define BCM_6368_OHCI0_BASE (0xb0001600) | 421 | #define BCM_6368_OHCI0_BASE (0xb0001600) |
410 | #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) | 422 | #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) |
411 | #define BCM_6368_USBH_PRIV_BASE (0xb0001700) | 423 | #define BCM_6368_USBH_PRIV_BASE (0xb0001700) |
424 | #define BCM_6368_USBD_BASE (0xb0001400) | ||
412 | #define BCM_6368_MPI_BASE (0xb0001000) | 425 | #define BCM_6368_MPI_BASE (0xb0001000) |
413 | #define BCM_6368_PCMCIA_BASE (0xb0001054) | 426 | #define BCM_6368_PCMCIA_BASE (0xb0001054) |
414 | #define BCM_6368_PCIE_BASE (0xdeadbeef) | 427 | #define BCM_6368_PCIE_BASE (0xdeadbeef) |
@@ -458,6 +471,8 @@ extern const unsigned long *bcm63xx_regs_base; | |||
458 | __GEN_RSET_BASE(__cpu, OHCI0) \ | 471 | __GEN_RSET_BASE(__cpu, OHCI0) \ |
459 | __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ | 472 | __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ |
460 | __GEN_RSET_BASE(__cpu, USBH_PRIV) \ | 473 | __GEN_RSET_BASE(__cpu, USBH_PRIV) \ |
474 | __GEN_RSET_BASE(__cpu, USBD) \ | ||
475 | __GEN_RSET_BASE(__cpu, USBDMA) \ | ||
461 | __GEN_RSET_BASE(__cpu, MPI) \ | 476 | __GEN_RSET_BASE(__cpu, MPI) \ |
462 | __GEN_RSET_BASE(__cpu, PCMCIA) \ | 477 | __GEN_RSET_BASE(__cpu, PCMCIA) \ |
463 | __GEN_RSET_BASE(__cpu, PCIE) \ | 478 | __GEN_RSET_BASE(__cpu, PCIE) \ |
@@ -499,6 +514,8 @@ extern const unsigned long *bcm63xx_regs_base; | |||
499 | [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ | 514 | [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ |
500 | [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ | 515 | [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ |
501 | [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ | 516 | [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ |
517 | [RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \ | ||
518 | [RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \ | ||
502 | [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ | 519 | [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ |
503 | [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ | 520 | [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ |
504 | [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \ | 521 | [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \ |
@@ -569,6 +586,13 @@ enum bcm63xx_irq { | |||
569 | IRQ_ENET_PHY, | 586 | IRQ_ENET_PHY, |
570 | IRQ_OHCI0, | 587 | IRQ_OHCI0, |
571 | IRQ_EHCI0, | 588 | IRQ_EHCI0, |
589 | IRQ_USBD, | ||
590 | IRQ_USBD_RXDMA0, | ||
591 | IRQ_USBD_TXDMA0, | ||
592 | IRQ_USBD_RXDMA1, | ||
593 | IRQ_USBD_TXDMA1, | ||
594 | IRQ_USBD_RXDMA2, | ||
595 | IRQ_USBD_TXDMA2, | ||
572 | IRQ_ENET0_RXDMA, | 596 | IRQ_ENET0_RXDMA, |
573 | IRQ_ENET0_TXDMA, | 597 | IRQ_ENET0_TXDMA, |
574 | IRQ_ENET1_RXDMA, | 598 | IRQ_ENET1_RXDMA, |
@@ -604,6 +628,13 @@ enum bcm63xx_irq { | |||
604 | #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) | 628 | #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) |
605 | #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) | 629 | #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) |
606 | #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) | 630 | #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) |
631 | #define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) | ||
632 | #define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5) | ||
633 | #define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6) | ||
634 | #define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7) | ||
635 | #define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8) | ||
636 | #define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9) | ||
637 | #define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10) | ||
607 | #define BCM_6328_PCMCIA_IRQ 0 | 638 | #define BCM_6328_PCMCIA_IRQ 0 |
608 | #define BCM_6328_ENET0_RXDMA_IRQ 0 | 639 | #define BCM_6328_ENET0_RXDMA_IRQ 0 |
609 | #define BCM_6328_ENET0_TXDMA_IRQ 0 | 640 | #define BCM_6328_ENET0_TXDMA_IRQ 0 |
@@ -642,6 +673,13 @@ enum bcm63xx_irq { | |||
642 | #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) | 673 | #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) |
643 | #define BCM_6338_OHCI0_IRQ 0 | 674 | #define BCM_6338_OHCI0_IRQ 0 |
644 | #define BCM_6338_EHCI0_IRQ 0 | 675 | #define BCM_6338_EHCI0_IRQ 0 |
676 | #define BCM_6338_USBD_IRQ 0 | ||
677 | #define BCM_6338_USBD_RXDMA0_IRQ 0 | ||
678 | #define BCM_6338_USBD_TXDMA0_IRQ 0 | ||
679 | #define BCM_6338_USBD_RXDMA1_IRQ 0 | ||
680 | #define BCM_6338_USBD_TXDMA1_IRQ 0 | ||
681 | #define BCM_6338_USBD_RXDMA2_IRQ 0 | ||
682 | #define BCM_6338_USBD_TXDMA2_IRQ 0 | ||
645 | #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) | 683 | #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) |
646 | #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) | 684 | #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) |
647 | #define BCM_6338_ENET1_RXDMA_IRQ 0 | 685 | #define BCM_6338_ENET1_RXDMA_IRQ 0 |
@@ -673,6 +711,13 @@ enum bcm63xx_irq { | |||
673 | #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) | 711 | #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) |
674 | #define BCM_6345_OHCI0_IRQ 0 | 712 | #define BCM_6345_OHCI0_IRQ 0 |
675 | #define BCM_6345_EHCI0_IRQ 0 | 713 | #define BCM_6345_EHCI0_IRQ 0 |
714 | #define BCM_6345_USBD_IRQ 0 | ||
715 | #define BCM_6345_USBD_RXDMA0_IRQ 0 | ||
716 | #define BCM_6345_USBD_TXDMA0_IRQ 0 | ||
717 | #define BCM_6345_USBD_RXDMA1_IRQ 0 | ||
718 | #define BCM_6345_USBD_TXDMA1_IRQ 0 | ||
719 | #define BCM_6345_USBD_RXDMA2_IRQ 0 | ||
720 | #define BCM_6345_USBD_TXDMA2_IRQ 0 | ||
676 | #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) | 721 | #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) |
677 | #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) | 722 | #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) |
678 | #define BCM_6345_ENET1_RXDMA_IRQ 0 | 723 | #define BCM_6345_ENET1_RXDMA_IRQ 0 |
@@ -704,6 +749,13 @@ enum bcm63xx_irq { | |||
704 | #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) | 749 | #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) |
705 | #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) | 750 | #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) |
706 | #define BCM_6348_EHCI0_IRQ 0 | 751 | #define BCM_6348_EHCI0_IRQ 0 |
752 | #define BCM_6348_USBD_IRQ 0 | ||
753 | #define BCM_6348_USBD_RXDMA0_IRQ 0 | ||
754 | #define BCM_6348_USBD_TXDMA0_IRQ 0 | ||
755 | #define BCM_6348_USBD_RXDMA1_IRQ 0 | ||
756 | #define BCM_6348_USBD_TXDMA1_IRQ 0 | ||
757 | #define BCM_6348_USBD_RXDMA2_IRQ 0 | ||
758 | #define BCM_6348_USBD_TXDMA2_IRQ 0 | ||
707 | #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) | 759 | #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) |
708 | #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) | 760 | #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) |
709 | #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) | 761 | #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) |
@@ -735,6 +787,13 @@ enum bcm63xx_irq { | |||
735 | #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) | 787 | #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) |
736 | #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) | 788 | #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) |
737 | #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) | 789 | #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) |
790 | #define BCM_6358_USBD_IRQ 0 | ||
791 | #define BCM_6358_USBD_RXDMA0_IRQ 0 | ||
792 | #define BCM_6358_USBD_TXDMA0_IRQ 0 | ||
793 | #define BCM_6358_USBD_RXDMA1_IRQ 0 | ||
794 | #define BCM_6358_USBD_TXDMA1_IRQ 0 | ||
795 | #define BCM_6358_USBD_RXDMA2_IRQ 0 | ||
796 | #define BCM_6358_USBD_TXDMA2_IRQ 0 | ||
738 | #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) | 797 | #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) |
739 | #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) | 798 | #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) |
740 | #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) | 799 | #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) |
@@ -775,6 +834,13 @@ enum bcm63xx_irq { | |||
775 | #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) | 834 | #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) |
776 | #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) | 835 | #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) |
777 | #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) | 836 | #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) |
837 | #define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) | ||
838 | #define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26) | ||
839 | #define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27) | ||
840 | #define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28) | ||
841 | #define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29) | ||
842 | #define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30) | ||
843 | #define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31) | ||
778 | #define BCM_6368_PCMCIA_IRQ 0 | 844 | #define BCM_6368_PCMCIA_IRQ 0 |
779 | #define BCM_6368_ENET0_RXDMA_IRQ 0 | 845 | #define BCM_6368_ENET0_RXDMA_IRQ 0 |
780 | #define BCM_6368_ENET0_TXDMA_IRQ 0 | 846 | #define BCM_6368_ENET0_TXDMA_IRQ 0 |
@@ -815,6 +881,13 @@ extern const int *bcm63xx_irqs; | |||
815 | [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ | 881 | [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ |
816 | [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ | 882 | [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ |
817 | [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ | 883 | [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ |
884 | [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \ | ||
885 | [IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \ | ||
886 | [IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \ | ||
887 | [IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \ | ||
888 | [IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \ | ||
889 | [IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \ | ||
890 | [IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \ | ||
818 | [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ | 891 | [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ |
819 | [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ | 892 | [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ |
820 | [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ | 893 | [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ |
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 29654aeea9a7..fa74a37ccb6c 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | |||
@@ -795,6 +795,12 @@ | |||
795 | #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 | 795 | #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 |
796 | #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) | 796 | #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) |
797 | 797 | ||
798 | #define USBH_PRIV_UTMI_CTL_6368_REG 0x10 | ||
799 | #define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12 | ||
800 | #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT) | ||
801 | #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0 | ||
802 | #define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT) | ||
803 | |||
798 | #define USBH_PRIV_TEST_6358_REG 0x24 | 804 | #define USBH_PRIV_TEST_6358_REG 0x24 |
799 | #define USBH_PRIV_TEST_6368_REG 0x14 | 805 | #define USBH_PRIV_TEST_6368_REG 0x14 |
800 | 806 | ||
@@ -803,6 +809,147 @@ | |||
803 | #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) | 809 | #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT) |
804 | 810 | ||
805 | 811 | ||
812 | /************************************************************************* | ||
813 | * _REG relative to RSET_USBD | ||
814 | *************************************************************************/ | ||
815 | |||
816 | /* General control */ | ||
817 | #define USBD_CONTROL_REG 0x00 | ||
818 | #define USBD_CONTROL_TXZLENINS_SHIFT 14 | ||
819 | #define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT) | ||
820 | #define USBD_CONTROL_AUTO_CSRS_SHIFT 13 | ||
821 | #define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT) | ||
822 | #define USBD_CONTROL_RXZSCFG_SHIFT 12 | ||
823 | #define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT) | ||
824 | #define USBD_CONTROL_INIT_SEL_SHIFT 8 | ||
825 | #define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT) | ||
826 | #define USBD_CONTROL_FIFO_RESET_SHIFT 6 | ||
827 | #define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT) | ||
828 | #define USBD_CONTROL_SETUPERRLOCK_SHIFT 5 | ||
829 | #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT) | ||
830 | #define USBD_CONTROL_DONE_CSRS_SHIFT 0 | ||
831 | #define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT) | ||
832 | |||
833 | /* Strap options */ | ||
834 | #define USBD_STRAPS_REG 0x04 | ||
835 | #define USBD_STRAPS_APP_SELF_PWR_SHIFT 10 | ||
836 | #define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT) | ||
837 | #define USBD_STRAPS_APP_DISCON_SHIFT 9 | ||
838 | #define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT) | ||
839 | #define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8 | ||
840 | #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT) | ||
841 | #define USBD_STRAPS_APP_RMTWKUP_SHIFT 6 | ||
842 | #define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT) | ||
843 | #define USBD_STRAPS_APP_RAM_IF_SHIFT 7 | ||
844 | #define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT) | ||
845 | #define USBD_STRAPS_APP_8BITPHY_SHIFT 2 | ||
846 | #define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT) | ||
847 | #define USBD_STRAPS_SPEED_SHIFT 0 | ||
848 | #define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT) | ||
849 | |||
850 | /* Stall control */ | ||
851 | #define USBD_STALL_REG 0x08 | ||
852 | #define USBD_STALL_UPDATE_SHIFT 7 | ||
853 | #define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT) | ||
854 | #define USBD_STALL_ENABLE_SHIFT 6 | ||
855 | #define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT) | ||
856 | #define USBD_STALL_EPNUM_SHIFT 0 | ||
857 | #define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT) | ||
858 | |||
859 | /* General status */ | ||
860 | #define USBD_STATUS_REG 0x0c | ||
861 | #define USBD_STATUS_SOF_SHIFT 16 | ||
862 | #define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT) | ||
863 | #define USBD_STATUS_SPD_SHIFT 12 | ||
864 | #define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT) | ||
865 | #define USBD_STATUS_ALTINTF_SHIFT 8 | ||
866 | #define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT) | ||
867 | #define USBD_STATUS_INTF_SHIFT 4 | ||
868 | #define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT) | ||
869 | #define USBD_STATUS_CFG_SHIFT 0 | ||
870 | #define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT) | ||
871 | |||
872 | /* Other events */ | ||
873 | #define USBD_EVENTS_REG 0x10 | ||
874 | #define USBD_EVENTS_USB_LINK_SHIFT 10 | ||
875 | #define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT) | ||
876 | |||
877 | /* IRQ status */ | ||
878 | #define USBD_EVENT_IRQ_STATUS_REG 0x14 | ||
879 | |||
880 | /* IRQ level (2 bits per IRQ event) */ | ||
881 | #define USBD_EVENT_IRQ_CFG_HI_REG 0x18 | ||
882 | |||
883 | #define USBD_EVENT_IRQ_CFG_LO_REG 0x1c | ||
884 | |||
885 | #define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1) | ||
886 | #define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x)) | ||
887 | #define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x)) | ||
888 | #define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x)) | ||
889 | |||
890 | /* IRQ mask (1=unmasked) */ | ||
891 | #define USBD_EVENT_IRQ_MASK_REG 0x20 | ||
892 | |||
893 | /* IRQ bits */ | ||
894 | #define USBD_EVENT_IRQ_USB_LINK 10 | ||
895 | #define USBD_EVENT_IRQ_SETCFG 9 | ||
896 | #define USBD_EVENT_IRQ_SETINTF 8 | ||
897 | #define USBD_EVENT_IRQ_ERRATIC_ERR 7 | ||
898 | #define USBD_EVENT_IRQ_SET_CSRS 6 | ||
899 | #define USBD_EVENT_IRQ_SUSPEND 5 | ||
900 | #define USBD_EVENT_IRQ_EARLY_SUSPEND 4 | ||
901 | #define USBD_EVENT_IRQ_SOF 3 | ||
902 | #define USBD_EVENT_IRQ_ENUM_ON 2 | ||
903 | #define USBD_EVENT_IRQ_SETUP 1 | ||
904 | #define USBD_EVENT_IRQ_USB_RESET 0 | ||
905 | |||
906 | /* TX FIFO partitioning */ | ||
907 | #define USBD_TXFIFO_CONFIG_REG 0x40 | ||
908 | #define USBD_TXFIFO_CONFIG_END_SHIFT 16 | ||
909 | #define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) | ||
910 | #define USBD_TXFIFO_CONFIG_START_SHIFT 0 | ||
911 | #define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) | ||
912 | |||
913 | /* RX FIFO partitioning */ | ||
914 | #define USBD_RXFIFO_CONFIG_REG 0x44 | ||
915 | #define USBD_RXFIFO_CONFIG_END_SHIFT 16 | ||
916 | #define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT) | ||
917 | #define USBD_RXFIFO_CONFIG_START_SHIFT 0 | ||
918 | #define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT) | ||
919 | |||
920 | /* TX FIFO/endpoint configuration */ | ||
921 | #define USBD_TXFIFO_EPSIZE_REG 0x48 | ||
922 | |||
923 | /* RX FIFO/endpoint configuration */ | ||
924 | #define USBD_RXFIFO_EPSIZE_REG 0x4c | ||
925 | |||
926 | /* Endpoint<->DMA mappings */ | ||
927 | #define USBD_EPNUM_TYPEMAP_REG 0x50 | ||
928 | #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8 | ||
929 | #define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT) | ||
930 | #define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0 | ||
931 | #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT) | ||
932 | |||
933 | /* Misc per-endpoint settings */ | ||
934 | #define USBD_CSR_SETUPADDR_REG 0x80 | ||
935 | #define USBD_CSR_SETUPADDR_DEF 0xb550 | ||
936 | |||
937 | #define USBD_CSR_EP_REG(x) (0x84 + (x) * 4) | ||
938 | #define USBD_CSR_EP_MAXPKT_SHIFT 19 | ||
939 | #define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT) | ||
940 | #define USBD_CSR_EP_ALTIFACE_SHIFT 15 | ||
941 | #define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT) | ||
942 | #define USBD_CSR_EP_IFACE_SHIFT 11 | ||
943 | #define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT) | ||
944 | #define USBD_CSR_EP_CFG_SHIFT 7 | ||
945 | #define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT) | ||
946 | #define USBD_CSR_EP_TYPE_SHIFT 5 | ||
947 | #define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT) | ||
948 | #define USBD_CSR_EP_DIR_SHIFT 4 | ||
949 | #define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT) | ||
950 | #define USBD_CSR_EP_LOG_SHIFT 0 | ||
951 | #define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT) | ||
952 | |||
806 | 953 | ||
807 | /************************************************************************* | 954 | /************************************************************************* |
808 | * _REG relative to RSET_MPI | 955 | * _REG relative to RSET_MPI |