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-rw-r--r--arch/mips/alchemy/common/platform.c9
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c8
-rw-r--r--arch/mips/bcm63xx/dev-enet.c3
-rw-r--r--arch/mips/include/asm/atomic.h24
-rw-r--r--arch/mips/include/asm/unistd.h5
-rw-r--r--arch/mips/kernel/scall64-n32.S1
-rw-r--r--arch/mips/kernel/vdso.c4
-rw-r--r--arch/mips/mti-malta/malta-pci.c2
-rw-r--r--arch/mips/nxp/pnx8550/common/pci.c1
-rw-r--r--arch/mips/nxp/pnx8550/common/setup.c2
-rw-r--r--arch/mips/pci/ops-pmcmsp.c1
-rw-r--r--arch/mips/pci/pci-yosemite.c1
-rw-r--r--arch/mips/powertv/asic/asic_devices.c5
13 files changed, 37 insertions, 29 deletions
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 2580e77624d2..f9e5622ebc95 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -435,20 +435,21 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
435static int __init au1xxx_platform_init(void) 435static int __init au1xxx_platform_init(void)
436{ 436{
437 unsigned int uartclk = get_au1x00_uart_baud_base() * 16; 437 unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
438 int i; 438 int err, i;
439 439
440 /* Fill up uartclk. */ 440 /* Fill up uartclk. */
441 for (i = 0; au1x00_uart_data[i].flags; i++) 441 for (i = 0; au1x00_uart_data[i].flags; i++)
442 au1x00_uart_data[i].uartclk = uartclk; 442 au1x00_uart_data[i].uartclk = uartclk;
443 443
444 err = platform_add_devices(au1xxx_platform_devices,
445 ARRAY_SIZE(au1xxx_platform_devices));
444#ifndef CONFIG_SOC_AU1100 446#ifndef CONFIG_SOC_AU1100
445 /* Register second MAC if enabled in pinfunc */ 447 /* Register second MAC if enabled in pinfunc */
446 if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) 448 if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
447 platform_device_register(&au1xxx_eth1_device); 449 platform_device_register(&au1xxx_eth1_device);
448#endif 450#endif
449 451
450 return platform_add_devices(au1xxx_platform_devices, 452 return err;
451 ARRAY_SIZE(au1xxx_platform_devices));
452} 453}
453 454
454arch_initcall(au1xxx_platform_init); 455arch_initcall(au1xxx_platform_init);
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index a9f0336e1f1f..52d883d37dd7 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -67,8 +67,6 @@ static void mtx1_power_off(void)
67 67
68void __init board_setup(void) 68void __init board_setup(void)
69{ 69{
70 alchemy_gpio2_enable();
71
72#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 70#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
73 /* Enable USB power switch */ 71 /* Enable USB power switch */
74 alchemy_gpio_direction_output(204, 0); 72 alchemy_gpio_direction_output(204, 0);
@@ -117,11 +115,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
117 115
118 if (assert && devsel != 0) 116 if (assert && devsel != 0)
119 /* Suppress signal to Cardbus */ 117 /* Suppress signal to Cardbus */
120 gpio_set_value(1, 0); /* set EXT_IO3 OFF */ 118 alchemy_gpio_set_value(1, 0); /* set EXT_IO3 OFF */
121 else 119 else
122 gpio_set_value(1, 1); /* set EXT_IO3 ON */ 120 alchemy_gpio_set_value(1, 1); /* set EXT_IO3 ON */
123 121
124 au_sync_udelay(1); 122 udelay(1);
125 return 1; 123 return 1;
126} 124}
127 125
diff --git a/arch/mips/bcm63xx/dev-enet.c b/arch/mips/bcm63xx/dev-enet.c
index 9f544badd0b4..39c23366c5c7 100644
--- a/arch/mips/bcm63xx/dev-enet.c
+++ b/arch/mips/bcm63xx/dev-enet.c
@@ -104,6 +104,9 @@ int __init bcm63xx_enet_register(int unit,
104 if (unit > 1) 104 if (unit > 1)
105 return -ENODEV; 105 return -ENODEV;
106 106
107 if (unit == 1 && BCMCPU_IS_6338())
108 return -ENODEV;
109
107 if (!shared_device_registered) { 110 if (!shared_device_registered) {
108 shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA); 111 shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
109 shared_res[0].end = shared_res[0].start; 112 shared_res[0].end = shared_res[0].start;
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 59dc0c7ef733..c63c56bfd184 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -434,7 +434,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
434 __asm__ __volatile__( 434 __asm__ __volatile__(
435 " .set mips3 \n" 435 " .set mips3 \n"
436 "1: lld %0, %1 # atomic64_add \n" 436 "1: lld %0, %1 # atomic64_add \n"
437 " addu %0, %2 \n" 437 " daddu %0, %2 \n"
438 " scd %0, %1 \n" 438 " scd %0, %1 \n"
439 " beqzl %0, 1b \n" 439 " beqzl %0, 1b \n"
440 " .set mips0 \n" 440 " .set mips0 \n"
@@ -446,7 +446,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
446 __asm__ __volatile__( 446 __asm__ __volatile__(
447 " .set mips3 \n" 447 " .set mips3 \n"
448 "1: lld %0, %1 # atomic64_add \n" 448 "1: lld %0, %1 # atomic64_add \n"
449 " addu %0, %2 \n" 449 " daddu %0, %2 \n"
450 " scd %0, %1 \n" 450 " scd %0, %1 \n"
451 " beqz %0, 2f \n" 451 " beqz %0, 2f \n"
452 " .subsection 2 \n" 452 " .subsection 2 \n"
@@ -479,7 +479,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
479 __asm__ __volatile__( 479 __asm__ __volatile__(
480 " .set mips3 \n" 480 " .set mips3 \n"
481 "1: lld %0, %1 # atomic64_sub \n" 481 "1: lld %0, %1 # atomic64_sub \n"
482 " subu %0, %2 \n" 482 " dsubu %0, %2 \n"
483 " scd %0, %1 \n" 483 " scd %0, %1 \n"
484 " beqzl %0, 1b \n" 484 " beqzl %0, 1b \n"
485 " .set mips0 \n" 485 " .set mips0 \n"
@@ -491,7 +491,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
491 __asm__ __volatile__( 491 __asm__ __volatile__(
492 " .set mips3 \n" 492 " .set mips3 \n"
493 "1: lld %0, %1 # atomic64_sub \n" 493 "1: lld %0, %1 # atomic64_sub \n"
494 " subu %0, %2 \n" 494 " dsubu %0, %2 \n"
495 " scd %0, %1 \n" 495 " scd %0, %1 \n"
496 " beqz %0, 2f \n" 496 " beqz %0, 2f \n"
497 " .subsection 2 \n" 497 " .subsection 2 \n"
@@ -524,10 +524,10 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
524 __asm__ __volatile__( 524 __asm__ __volatile__(
525 " .set mips3 \n" 525 " .set mips3 \n"
526 "1: lld %1, %2 # atomic64_add_return \n" 526 "1: lld %1, %2 # atomic64_add_return \n"
527 " addu %0, %1, %3 \n" 527 " daddu %0, %1, %3 \n"
528 " scd %0, %2 \n" 528 " scd %0, %2 \n"
529 " beqzl %0, 1b \n" 529 " beqzl %0, 1b \n"
530 " addu %0, %1, %3 \n" 530 " daddu %0, %1, %3 \n"
531 " .set mips0 \n" 531 " .set mips0 \n"
532 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 532 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
533 : "Ir" (i), "m" (v->counter) 533 : "Ir" (i), "m" (v->counter)
@@ -538,10 +538,10 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
538 __asm__ __volatile__( 538 __asm__ __volatile__(
539 " .set mips3 \n" 539 " .set mips3 \n"
540 "1: lld %1, %2 # atomic64_add_return \n" 540 "1: lld %1, %2 # atomic64_add_return \n"
541 " addu %0, %1, %3 \n" 541 " daddu %0, %1, %3 \n"
542 " scd %0, %2 \n" 542 " scd %0, %2 \n"
543 " beqz %0, 2f \n" 543 " beqz %0, 2f \n"
544 " addu %0, %1, %3 \n" 544 " daddu %0, %1, %3 \n"
545 " .subsection 2 \n" 545 " .subsection 2 \n"
546 "2: b 1b \n" 546 "2: b 1b \n"
547 " .previous \n" 547 " .previous \n"
@@ -576,10 +576,10 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
576 __asm__ __volatile__( 576 __asm__ __volatile__(
577 " .set mips3 \n" 577 " .set mips3 \n"
578 "1: lld %1, %2 # atomic64_sub_return \n" 578 "1: lld %1, %2 # atomic64_sub_return \n"
579 " subu %0, %1, %3 \n" 579 " dsubu %0, %1, %3 \n"
580 " scd %0, %2 \n" 580 " scd %0, %2 \n"
581 " beqzl %0, 1b \n" 581 " beqzl %0, 1b \n"
582 " subu %0, %1, %3 \n" 582 " dsubu %0, %1, %3 \n"
583 " .set mips0 \n" 583 " .set mips0 \n"
584 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 584 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
585 : "Ir" (i), "m" (v->counter) 585 : "Ir" (i), "m" (v->counter)
@@ -590,10 +590,10 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
590 __asm__ __volatile__( 590 __asm__ __volatile__(
591 " .set mips3 \n" 591 " .set mips3 \n"
592 "1: lld %1, %2 # atomic64_sub_return \n" 592 "1: lld %1, %2 # atomic64_sub_return \n"
593 " subu %0, %1, %3 \n" 593 " dsubu %0, %1, %3 \n"
594 " scd %0, %2 \n" 594 " scd %0, %2 \n"
595 " beqz %0, 2f \n" 595 " beqz %0, 2f \n"
596 " subu %0, %1, %3 \n" 596 " dsubu %0, %1, %3 \n"
597 " .subsection 2 \n" 597 " .subsection 2 \n"
598 "2: b 1b \n" 598 "2: b 1b \n"
599 " .previous \n" 599 " .previous \n"
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index 1b5a6648eb86..baa318a59c97 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -984,16 +984,17 @@
984#define __NR_perf_event_open (__NR_Linux + 296) 984#define __NR_perf_event_open (__NR_Linux + 296)
985#define __NR_accept4 (__NR_Linux + 297) 985#define __NR_accept4 (__NR_Linux + 297)
986#define __NR_recvmmsg (__NR_Linux + 298) 986#define __NR_recvmmsg (__NR_Linux + 298)
987#define __NR_getdents64 (__NR_Linux + 299)
987 988
988/* 989/*
989 * Offset of the last N32 flavoured syscall 990 * Offset of the last N32 flavoured syscall
990 */ 991 */
991#define __NR_Linux_syscalls 298 992#define __NR_Linux_syscalls 299
992 993
993#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 994#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
994 995
995#define __NR_N32_Linux 6000 996#define __NR_N32_Linux 6000
996#define __NR_N32_Linux_syscalls 298 997#define __NR_N32_Linux_syscalls 299
997 998
998#ifdef __KERNEL__ 999#ifdef __KERNEL__
999 1000
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index a5297e2a353a..a4faceea9d88 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -419,4 +419,5 @@ EXPORT(sysn32_call_table)
419 PTR sys_perf_event_open 419 PTR sys_perf_event_open
420 PTR sys_accept4 420 PTR sys_accept4
421 PTR compat_sys_recvmmsg 421 PTR compat_sys_recvmmsg
422 PTR sys_getdents
422 .size sysn32_call_table,.-sysn32_call_table 423 .size sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/vdso.c b/arch/mips/kernel/vdso.c
index b773c1112b14..e5cdfd603f8f 100644
--- a/arch/mips/kernel/vdso.c
+++ b/arch/mips/kernel/vdso.c
@@ -61,11 +61,9 @@ static int __init init_vdso(void)
61 61
62 vunmap(vdso); 62 vunmap(vdso);
63 63
64 pr_notice("init_vdso successfull\n");
65
66 return 0; 64 return 0;
67} 65}
68device_initcall(init_vdso); 66subsys_initcall(init_vdso);
69 67
70static unsigned long vdso_addr(unsigned long start) 68static unsigned long vdso_addr(unsigned long start)
71{ 69{
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c
index 2fbfa1a8c3a9..bf80921f2f56 100644
--- a/arch/mips/mti-malta/malta-pci.c
+++ b/arch/mips/mti-malta/malta-pci.c
@@ -247,6 +247,8 @@ void __init mips_pcibios_init(void)
247 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ 247 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
248 ioport_resource.end = controller->io_resource->end; 248 ioport_resource.end = controller->io_resource->end;
249 249
250 controller->io_map_base = mips_io_port_base;
251
250 register_pci_controller(controller); 252 register_pci_controller(controller);
251} 253}
252 254
diff --git a/arch/mips/nxp/pnx8550/common/pci.c b/arch/mips/nxp/pnx8550/common/pci.c
index eee4f3dfc410..98e86ddb86cc 100644
--- a/arch/mips/nxp/pnx8550/common/pci.c
+++ b/arch/mips/nxp/pnx8550/common/pci.c
@@ -44,6 +44,7 @@ extern struct pci_ops pnx8550_pci_ops;
44 44
45static struct pci_controller pnx8550_controller = { 45static struct pci_controller pnx8550_controller = {
46 .pci_ops = &pnx8550_pci_ops, 46 .pci_ops = &pnx8550_pci_ops,
47 .io_map_base = PNX8550_PORT_BASE,
47 .io_resource = &pci_io_resource, 48 .io_resource = &pci_io_resource,
48 .mem_resource = &pci_mem_resource, 49 .mem_resource = &pci_mem_resource,
49}; 50};
diff --git a/arch/mips/nxp/pnx8550/common/setup.c b/arch/mips/nxp/pnx8550/common/setup.c
index 2aed50fef10f..64246c9c875c 100644
--- a/arch/mips/nxp/pnx8550/common/setup.c
+++ b/arch/mips/nxp/pnx8550/common/setup.c
@@ -113,7 +113,7 @@ void __init plat_mem_setup(void)
113 PNX8550_GLB2_ENAB_INTA_O = 0; 113 PNX8550_GLB2_ENAB_INTA_O = 0;
114 114
115 /* IO/MEM resources. */ 115 /* IO/MEM resources. */
116 set_io_port_base(KSEG1); 116 set_io_port_base(PNX8550_PORT_BASE);
117 ioport_resource.start = 0; 117 ioport_resource.start = 0;
118 ioport_resource.end = ~0; 118 ioport_resource.end = ~0;
119 iomem_resource.start = 0; 119 iomem_resource.start = 0;
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 04b31478a6d7..b7c03d80c88c 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -944,6 +944,7 @@ static struct pci_controller msp_pci_controller = {
944 .pci_ops = &msp_pci_ops, 944 .pci_ops = &msp_pci_ops,
945 .mem_resource = &pci_mem_resource, 945 .mem_resource = &pci_mem_resource,
946 .mem_offset = 0, 946 .mem_offset = 0,
947 .io_map_base = MSP_PCI_IOSPACE_BASE,
947 .io_resource = &pci_io_resource, 948 .io_resource = &pci_io_resource,
948 .io_offset = 0 949 .io_offset = 0
949}; 950};
diff --git a/arch/mips/pci/pci-yosemite.c b/arch/mips/pci/pci-yosemite.c
index 0357946f30e6..cf5e1a25cb7d 100644
--- a/arch/mips/pci/pci-yosemite.c
+++ b/arch/mips/pci/pci-yosemite.c
@@ -54,6 +54,7 @@ static int __init pmc_yosemite_setup(void)
54 panic(ioremap_failed); 54 panic(ioremap_failed);
55 55
56 set_io_port_base(io_v_base); 56 set_io_port_base(io_v_base);
57 py_controller.io_map_base = io_v_base;
57 TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1); 58 TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
58 59
59 ioport_resource.end = TITAN_IO_SIZE - 1; 60 ioport_resource.end = TITAN_IO_SIZE - 1;
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
index 8ee77887306a..9ec523e4dd06 100644
--- a/arch/mips/powertv/asic/asic_devices.c
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -472,6 +472,9 @@ void __init configure_platform(void)
472 * it*/ 472 * it*/
473 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; 473 platform_features = FFS_CAPABLE | DISPLAY_CAPABLE;
474 474
475 /* Cronus and Cronus Lite have the same register map */
476 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
477
475 /* ASIC version will determine if this is a real CronusLite or 478 /* ASIC version will determine if this is a real CronusLite or
476 * Castrati(Cronus) */ 479 * Castrati(Cronus) */
477 chipversion = asic_read(chipver3) << 24; 480 chipversion = asic_read(chipver3) << 24;
@@ -484,8 +487,6 @@ void __init configure_platform(void)
484 else 487 else
485 asic = ASIC_CRONUSLITE; 488 asic = ASIC_CRONUSLITE;
486 489
487 /* Cronus and Cronus Lite have the same register map */
488 set_register_map(CRONUS_IO_BASE, &cronus_register_map);
489 gp_resources = non_dvr_cronuslite_resources; 490 gp_resources = non_dvr_cronuslite_resources;
490 pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, " 491 pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, "
491 "chipversion=0x%08X\n", 492 "chipversion=0x%08X\n",
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 08:54:21 -0500