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-rw-r--r--arch/mips/Makefile2
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c2
-rw-r--r--arch/mips/dec/ecc-berr.c1
-rw-r--r--arch/mips/dec/kn02xa-berr.c1
-rw-r--r--arch/mips/dec/prom/Makefile1
-rw-r--r--arch/mips/dec/prom/call_o32.S89
-rw-r--r--arch/mips/fw/lib/call_o32.S57
-rw-r--r--arch/mips/fw/sni/sniprom.c3
-rw-r--r--arch/mips/include/asm/cpu-info.h4
-rw-r--r--arch/mips/include/asm/dec/prom.h48
-rw-r--r--arch/mips/include/asm/rm9k-ocd.h56
-rw-r--r--arch/mips/include/asm/syscall.h2
-rw-r--r--arch/mips/include/uapi/asm/inst.h398
-rw-r--r--arch/mips/include/uapi/asm/unistd.h15
-rw-r--r--arch/mips/kernel/branch.c8
-rw-r--r--arch/mips/kernel/proc.c9
-rw-r--r--arch/mips/kernel/ptrace.c14
-rw-r--r--arch/mips/kernel/scall32-o32.S1
-rw-r--r--arch/mips/kernel/scall64-64.S1
-rw-r--r--arch/mips/kernel/scall64-n32.S1
-rw-r--r--arch/mips/kernel/scall64-o32.S1
-rw-r--r--arch/mips/kernel/traps.c4
-rw-r--r--arch/mips/lantiq/dts/easy50712.dts1
-rw-r--r--arch/mips/lib/csum_partial.S9
-rw-r--r--arch/mips/lib/delay.c14
-rw-r--r--arch/mips/lib/strncpy_user.S13
-rw-r--r--arch/mips/loongson/Kconfig1
-rw-r--r--arch/mips/loongson/common/cs5536/cs5536_mfgpt.c11
-rw-r--r--arch/mips/loongson/lemote-2f/clock.c5
-rw-r--r--arch/mips/mm/cache.c4
-rw-r--r--arch/mips/mm/page.c4
-rw-r--r--arch/mips/mm/tlb-funcs.S4
-rw-r--r--arch/mips/mm/tlbex.c7
-rw-r--r--arch/mips/mti-malta/malta-memory.c2
-rw-r--r--arch/mips/pci/pci-rc32434.c1
-rw-r--r--arch/mips/ralink/dts/mt7620a_eval.dts1
-rw-r--r--arch/mips/ralink/dts/rt2880_eval.dts1
-rw-r--r--arch/mips/ralink/dts/rt3052_eval.dts1
-rw-r--r--arch/mips/ralink/dts/rt3883_eval.dts1
39 files changed, 345 insertions, 453 deletions
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 1a5b4032cb66..60a359cfa328 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -151,7 +151,7 @@ cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \
151 -Wa,--trap 151 -Wa,--trap
152cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \ 152cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \
153 -Wa,--trap 153 -Wa,--trap
154cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \ 154cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1 -mno-mdmx -mno-mips3d,-march=r5000) \
155 -Wa,--trap 155 -Wa,--trap
156cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap 156cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap
157cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ 157cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index c2bb4f896ce7..3aa5b46b2d40 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -635,7 +635,7 @@ static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
635 cpumask_clear(&new_affinity); 635 cpumask_clear(&new_affinity);
636 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity); 636 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
637 } 637 }
638 __irq_set_affinity_locked(data, &new_affinity); 638 irq_set_affinity_locked(data, &new_affinity, false);
639} 639}
640 640
641static int octeon_irq_ciu_set_affinity(struct irq_data *data, 641static int octeon_irq_ciu_set_affinity(struct irq_data *data,
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 5abf4e894216..2a66e908f6a9 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -21,6 +21,7 @@
21#include <asm/addrspace.h> 21#include <asm/addrspace.h>
22#include <asm/bootinfo.h> 22#include <asm/bootinfo.h>
23#include <asm/cpu.h> 23#include <asm/cpu.h>
24#include <asm/cpu-type.h>
24#include <asm/irq_regs.h> 25#include <asm/irq_regs.h>
25#include <asm/processor.h> 26#include <asm/processor.h>
26#include <asm/ptrace.h> 27#include <asm/ptrace.h>
diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c
index f434b759e3b9..ec606363b806 100644
--- a/arch/mips/dec/kn02xa-berr.c
+++ b/arch/mips/dec/kn02xa-berr.c
@@ -19,6 +19,7 @@
19#include <linux/types.h> 19#include <linux/types.h>
20 20
21#include <asm/addrspace.h> 21#include <asm/addrspace.h>
22#include <asm/cpu-type.h>
22#include <asm/irq_regs.h> 23#include <asm/irq_regs.h>
23#include <asm/ptrace.h> 24#include <asm/ptrace.h>
24#include <asm/traps.h> 25#include <asm/traps.h>
diff --git a/arch/mips/dec/prom/Makefile b/arch/mips/dec/prom/Makefile
index 064ae7a76bdc..ae73e42ac20b 100644
--- a/arch/mips/dec/prom/Makefile
+++ b/arch/mips/dec/prom/Makefile
@@ -6,4 +6,3 @@
6lib-y += init.o memory.o cmdline.o identify.o console.o 6lib-y += init.o memory.o cmdline.o identify.o console.o
7 7
8lib-$(CONFIG_32BIT) += locore.o 8lib-$(CONFIG_32BIT) += locore.o
9lib-$(CONFIG_64BIT) += call_o32.o
diff --git a/arch/mips/dec/prom/call_o32.S b/arch/mips/dec/prom/call_o32.S
deleted file mode 100644
index 8c8498159e43..000000000000
--- a/arch/mips/dec/prom/call_o32.S
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * O32 interface for the 64 (or N32) ABI.
3 *
4 * Copyright (C) 2002 Maciej W. Rozycki
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <asm/asm.h>
13#include <asm/regdef.h>
14
15/* Maximum number of arguments supported. Must be even! */
16#define O32_ARGC 32
17/* Number of static registers we save. */
18#define O32_STATC 11
19/* Frame size for both of the above. */
20#define O32_FRAMESZ (4 * O32_ARGC + SZREG * O32_STATC)
21
22 .text
23
24/*
25 * O32 function call dispatcher, for interfacing 32-bit ROM routines.
26 *
27 * The standard 64 (N32) calling sequence is supported, with a0
28 * holding a function pointer, a1-a7 -- its first seven arguments
29 * and the stack -- remaining ones (up to O32_ARGC, including a1-a7).
30 * Static registers, gp and fp are preserved, v0 holds a result.
31 * This code relies on the called o32 function for sp and ra
32 * restoration and thus both this dispatcher and the current stack
33 * have to be placed in a KSEGx (or KUSEG) address space. Any
34 * pointers passed have to point to addresses within one of these
35 * spaces as well.
36 */
37NESTED(call_o32, O32_FRAMESZ, ra)
38 REG_SUBU sp,O32_FRAMESZ
39
40 REG_S ra,O32_FRAMESZ-1*SZREG(sp)
41 REG_S fp,O32_FRAMESZ-2*SZREG(sp)
42 REG_S gp,O32_FRAMESZ-3*SZREG(sp)
43 REG_S s7,O32_FRAMESZ-4*SZREG(sp)
44 REG_S s6,O32_FRAMESZ-5*SZREG(sp)
45 REG_S s5,O32_FRAMESZ-6*SZREG(sp)
46 REG_S s4,O32_FRAMESZ-7*SZREG(sp)
47 REG_S s3,O32_FRAMESZ-8*SZREG(sp)
48 REG_S s2,O32_FRAMESZ-9*SZREG(sp)
49 REG_S s1,O32_FRAMESZ-10*SZREG(sp)
50 REG_S s0,O32_FRAMESZ-11*SZREG(sp)
51
52 move jp,a0
53
54 sll a0,a1,zero
55 sll a1,a2,zero
56 sll a2,a3,zero
57 sll a3,a4,zero
58 sw a5,0x10(sp)
59 sw a6,0x14(sp)
60 sw a7,0x18(sp)
61
62 PTR_LA t0,O32_FRAMESZ(sp)
63 PTR_LA t1,0x1c(sp)
64 li t2,O32_ARGC-7
651:
66 lw t3,(t0)
67 REG_ADDU t0,SZREG
68 sw t3,(t1)
69 REG_SUBU t2,1
70 REG_ADDU t1,4
71 bnez t2,1b
72
73 jalr jp
74
75 REG_L s0,O32_FRAMESZ-11*SZREG(sp)
76 REG_L s1,O32_FRAMESZ-10*SZREG(sp)
77 REG_L s2,O32_FRAMESZ-9*SZREG(sp)
78 REG_L s3,O32_FRAMESZ-8*SZREG(sp)
79 REG_L s4,O32_FRAMESZ-7*SZREG(sp)
80 REG_L s5,O32_FRAMESZ-6*SZREG(sp)
81 REG_L s6,O32_FRAMESZ-5*SZREG(sp)
82 REG_L s7,O32_FRAMESZ-4*SZREG(sp)
83 REG_L gp,O32_FRAMESZ-3*SZREG(sp)
84 REG_L fp,O32_FRAMESZ-2*SZREG(sp)
85 REG_L ra,O32_FRAMESZ-1*SZREG(sp)
86
87 REG_ADDU sp,O32_FRAMESZ
88 jr ra
89END(call_o32)
diff --git a/arch/mips/fw/lib/call_o32.S b/arch/mips/fw/lib/call_o32.S
index b308b2a0613e..4703fe4dbd9a 100644
--- a/arch/mips/fw/lib/call_o32.S
+++ b/arch/mips/fw/lib/call_o32.S
@@ -1,7 +1,7 @@
1/* 1/*
2 * O32 interface for the 64 (or N32) ABI. 2 * O32 interface for the 64 (or N32) ABI.
3 * 3 *
4 * Copyright (C) 2002 Maciej W. Rozycki 4 * Copyright (C) 2002, 2014 Maciej W. Rozycki
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License 7 * modify it under the terms of the GNU General Public License
@@ -12,28 +12,37 @@
12#include <asm/asm.h> 12#include <asm/asm.h>
13#include <asm/regdef.h> 13#include <asm/regdef.h>
14 14
15/* O32 register size. */
16#define O32_SZREG 4
15/* Maximum number of arguments supported. Must be even! */ 17/* Maximum number of arguments supported. Must be even! */
16#define O32_ARGC 32 18#define O32_ARGC 32
17/* Number of static registers we save. */ 19/* Number of static registers we save. */
18#define O32_STATC 11 20#define O32_STATC 11
19/* Frame size for static register */ 21/* Argument area frame size. */
20#define O32_FRAMESZ (SZREG * O32_STATC) 22#define O32_ARGSZ (O32_SZREG * O32_ARGC)
21/* Frame size on new stack */ 23/* Static register save area frame size. */
22#define O32_FRAMESZ_NEW (SZREG + 4 * O32_ARGC) 24#define O32_STATSZ (SZREG * O32_STATC)
25/* Stack pointer register save area frame size. */
26#define O32_SPSZ SZREG
27/* Combined area frame size. */
28#define O32_FRAMESZ (O32_ARGSZ + O32_SPSZ + O32_STATSZ)
29/* Switched stack frame size. */
30#define O32_NFRAMESZ (O32_ARGSZ + O32_SPSZ)
23 31
24 .text 32 .text
25 33
26/* 34/*
27 * O32 function call dispatcher, for interfacing 32-bit ROM routines. 35 * O32 function call dispatcher, for interfacing 32-bit ROM routines.
28 * 36 *
29 * The standard 64 (N32) calling sequence is supported, with a0 37 * The standard 64 (N32) calling sequence is supported, with a0 holding
30 * holding a function pointer, a1 a new stack pointer, a2-a7 -- its 38 * a function pointer, a1 a pointer to the new stack to call the
31 * first six arguments and the stack -- remaining ones (up to O32_ARGC, 39 * function with or 0 if no stack switching is requested, a2-a7 -- the
32 * including a2-a7). Static registers, gp and fp are preserved, v0 holds 40 * function call's first six arguments, and the stack -- the remaining
33 * a result. This code relies on the called o32 function for sp and ra 41 * arguments (up to O32_ARGC, including a2-a7). Static registers, gp
34 * restoration and this dispatcher has to be placed in a KSEGx (or KUSEG) 42 * and fp are preserved, v0 holds the result. This code relies on the
35 * address space. Any pointers passed have to point to addresses within 43 * called o32 function for sp and ra restoration and this dispatcher has
36 * one of these spaces as well. 44 * to be placed in a KSEGx (or KUSEG) address space. Any pointers
45 * passed have to point to addresses within one of these spaces as well.
37 */ 46 */
38NESTED(call_o32, O32_FRAMESZ, ra) 47NESTED(call_o32, O32_FRAMESZ, ra)
39 REG_SUBU sp,O32_FRAMESZ 48 REG_SUBU sp,O32_FRAMESZ
@@ -51,32 +60,36 @@ NESTED(call_o32, O32_FRAMESZ, ra)
51 REG_S s0,O32_FRAMESZ-11*SZREG(sp) 60 REG_S s0,O32_FRAMESZ-11*SZREG(sp)
52 61
53 move jp,a0 62 move jp,a0
54 REG_SUBU s0,a1,O32_FRAMESZ_NEW 63
55 REG_S sp,O32_FRAMESZ_NEW-1*SZREG(s0) 64 move fp,sp
65 beqz a1,0f
66 REG_SUBU fp,a1,O32_NFRAMESZ
670:
68 REG_S sp,O32_NFRAMESZ-1*SZREG(fp)
56 69
57 sll a0,a2,zero 70 sll a0,a2,zero
58 sll a1,a3,zero 71 sll a1,a3,zero
59 sll a2,a4,zero 72 sll a2,a4,zero
60 sll a3,a5,zero 73 sll a3,a5,zero
61 sw a6,0x10(s0) 74 sw a6,4*O32_SZREG(fp)
62 sw a7,0x14(s0) 75 sw a7,5*O32_SZREG(fp)
63 76
64 PTR_LA t0,O32_FRAMESZ(sp) 77 PTR_LA t0,O32_FRAMESZ(sp)
65 PTR_LA t1,0x18(s0) 78 PTR_LA t1,6*O32_SZREG(fp)
66 li t2,O32_ARGC-6 79 li t2,O32_ARGC-6
671: 801:
68 lw t3,(t0) 81 lw t3,(t0)
69 REG_ADDU t0,SZREG 82 REG_ADDU t0,SZREG
70 sw t3,(t1) 83 sw t3,(t1)
71 REG_SUBU t2,1 84 REG_SUBU t2,1
72 REG_ADDU t1,4 85 REG_ADDU t1,O32_SZREG
73 bnez t2,1b 86 bnez t2,1b
74 87
75 move sp,s0 88 move sp,fp
76 89
77 jalr jp 90 jalr jp
78 91
79 REG_L sp,O32_FRAMESZ_NEW-1*SZREG(sp) 92 REG_L sp,O32_NFRAMESZ-1*SZREG(sp)
80 93
81 REG_L s0,O32_FRAMESZ-11*SZREG(sp) 94 REG_L s0,O32_FRAMESZ-11*SZREG(sp)
82 REG_L s1,O32_FRAMESZ-10*SZREG(sp) 95 REG_L s1,O32_FRAMESZ-10*SZREG(sp)
diff --git a/arch/mips/fw/sni/sniprom.c b/arch/mips/fw/sni/sniprom.c
index 2c2cb182af4e..6aa264b9856a 100644
--- a/arch/mips/fw/sni/sniprom.c
+++ b/arch/mips/fw/sni/sniprom.c
@@ -40,7 +40,8 @@
40 40
41#ifdef CONFIG_64BIT 41#ifdef CONFIG_64BIT
42 42
43static u8 o32_stk[16384]; 43/* O32 stack has to be 8-byte aligned. */
44static u64 o32_stk[4096];
44#define O32_STK &o32_stk[sizeof(o32_stk)] 45#define O32_STK &o32_stk[sizeof(o32_stk)]
45 46
46#define __PROM_O32(fun, arg) fun arg __asm__(#fun); \ 47#define __PROM_O32(fun, arg) fun arg __asm__(#fun); \
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index dc2135be2a3a..ff2707ab3295 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -39,14 +39,14 @@ struct cache_desc {
39#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ 39#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
40 40
41struct cpuinfo_mips { 41struct cpuinfo_mips {
42 unsigned int udelay_val; 42 unsigned long asid_cache;
43 unsigned int asid_cache;
44 43
45 /* 44 /*
46 * Capability and feature descriptor structure for MIPS CPU 45 * Capability and feature descriptor structure for MIPS CPU
47 */ 46 */
48 unsigned long options; 47 unsigned long options;
49 unsigned long ases; 48 unsigned long ases;
49 unsigned int udelay_val;
50 unsigned int processor_id; 50 unsigned int processor_id;
51 unsigned int fpu_id; 51 unsigned int fpu_id;
52 unsigned int msa_id; 52 unsigned int msa_id;
diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
index c0ead6313845..b59a2103b61a 100644
--- a/arch/mips/include/asm/dec/prom.h
+++ b/arch/mips/include/asm/dec/prom.h
@@ -113,31 +113,31 @@ extern int (*__pmax_close)(int);
113#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \ 113#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
114 __asm__(#fun " = call_o32") 114 __asm__(#fun " = call_o32")
115 115
116int __DEC_PROM_O32(_rex_bootinit, (int (*)(void))); 116int __DEC_PROM_O32(_rex_bootinit, (int (*)(void), void *));
117int __DEC_PROM_O32(_rex_bootread, (int (*)(void))); 117int __DEC_PROM_O32(_rex_bootread, (int (*)(void), void *));
118int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *)); 118int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), void *, memmap *));
119unsigned long *__DEC_PROM_O32(_rex_slot_address, 119unsigned long *__DEC_PROM_O32(_rex_slot_address,
120 (unsigned long *(*)(int), int)); 120 (unsigned long *(*)(int), void *, int));
121void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void))); 121void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void), void *));
122int __DEC_PROM_O32(_rex_getsysid, (int (*)(void))); 122int __DEC_PROM_O32(_rex_getsysid, (int (*)(void), void *));
123void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void))); 123void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void), void *));
124 124
125int __DEC_PROM_O32(_prom_getchar, (int (*)(void))); 125int __DEC_PROM_O32(_prom_getchar, (int (*)(void), void *));
126char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *)); 126char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), void *, char *));
127int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...)); 127int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), void *, char *, ...));
128 128
129 129
130#define rex_bootinit() _rex_bootinit(__rex_bootinit) 130#define rex_bootinit() _rex_bootinit(__rex_bootinit, NULL)
131#define rex_bootread() _rex_bootread(__rex_bootread) 131#define rex_bootread() _rex_bootread(__rex_bootread, NULL)
132#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, x) 132#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, NULL, x)
133#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, x) 133#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, NULL, x)
134#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo) 134#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo, NULL)
135#define rex_getsysid() _rex_getsysid(__rex_getsysid) 135#define rex_getsysid() _rex_getsysid(__rex_getsysid, NULL)
136#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache) 136#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache, NULL)
137 137
138#define prom_getchar() _prom_getchar(__prom_getchar) 138#define prom_getchar() _prom_getchar(__prom_getchar, NULL)
139#define prom_getenv(x) _prom_getenv(__prom_getenv, x) 139#define prom_getenv(x) _prom_getenv(__prom_getenv, NULL, x)
140#define prom_printf(x...) _prom_printf(__prom_printf, x) 140#define prom_printf(x...) _prom_printf(__prom_printf, NULL, x)
141 141
142#else /* !CONFIG_64BIT */ 142#else /* !CONFIG_64BIT */
143 143
diff --git a/arch/mips/include/asm/rm9k-ocd.h b/arch/mips/include/asm/rm9k-ocd.h
deleted file mode 100644
index b0b80d9ecf96..000000000000
--- a/arch/mips/include/asm/rm9k-ocd.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#if !defined(_ASM_RM9K_OCD_H)
21#define _ASM_RM9K_OCD_H
22
23#include <linux/types.h>
24#include <linux/spinlock.h>
25#include <asm/io.h>
26
27extern volatile void __iomem * const ocd_base;
28extern volatile void __iomem * const titan_base;
29
30#define ocd_addr(__x__) (ocd_base + (__x__))
31#define titan_addr(__x__) (titan_base + (__x__))
32#define scram_addr(__x__) (scram_base + (__x__))
33
34/* OCD register access */
35#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
36#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
37#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
38#define ocd_writel(__val__, __offs__) \
39 __raw_writel((__val__), ocd_addr(__offs__))
40#define ocd_writew(__val__, __offs__) \
41 __raw_writew((__val__), ocd_addr(__offs__))
42#define ocd_writeb(__val__, __offs__) \
43 __raw_writeb((__val__), ocd_addr(__offs__))
44
45/* TITAN register access - 32 bit-wide only */
46#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
47#define titan_writel(__val__, __offs__) \
48 __raw_writel((__val__), titan_addr(__offs__))
49
50/* Protect access to shared TITAN registers */
51extern spinlock_t titan_lock;
52extern int titan_irqflags;
53#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
54#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
55
56#endif /* !defined(_ASM_RM9K_OCD_H) */
diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h
index c6e9cd2bca8d..17960fe7a8ce 100644
--- a/arch/mips/include/asm/syscall.h
+++ b/arch/mips/include/asm/syscall.h
@@ -133,6 +133,8 @@ static inline int syscall_get_arch(void)
133#ifdef CONFIG_64BIT 133#ifdef CONFIG_64BIT
134 if (!test_thread_flag(TIF_32BIT_REGS)) 134 if (!test_thread_flag(TIF_32BIT_REGS))
135 arch |= __AUDIT_ARCH_64BIT; 135 arch |= __AUDIT_ARCH_64BIT;
136 if (test_thread_flag(TIF_32BIT_ADDR))
137 arch |= __AUDIT_ARCH_CONVENTION_MIPS64_N32;
136#endif 138#endif
137#if defined(__LITTLE_ENDIAN) 139#if defined(__LITTLE_ENDIAN)
138 arch |= __AUDIT_ARCH_LE; 140 arch |= __AUDIT_ARCH_LE;
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index df6e775f3fef..3125797f2a88 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -484,13 +484,13 @@ enum MIPS6e_i8_func {
484 * Damn ... bitfields depend from byteorder :-( 484 * Damn ... bitfields depend from byteorder :-(
485 */ 485 */
486#ifdef __MIPSEB__ 486#ifdef __MIPSEB__
487#define BITFIELD_FIELD(field, more) \ 487#define __BITFIELD_FIELD(field, more) \
488 field; \ 488 field; \
489 more 489 more
490 490
491#elif defined(__MIPSEL__) 491#elif defined(__MIPSEL__)
492 492
493#define BITFIELD_FIELD(field, more) \ 493#define __BITFIELD_FIELD(field, more) \
494 more \ 494 more \
495 field; 495 field;
496 496
@@ -499,112 +499,112 @@ enum MIPS6e_i8_func {
499#endif 499#endif
500 500
501struct j_format { 501struct j_format {
502 BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */ 502 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
503 BITFIELD_FIELD(unsigned int target : 26, 503 __BITFIELD_FIELD(unsigned int target : 26,
504 ;)) 504 ;))
505}; 505};
506 506
507struct i_format { /* signed immediate format */ 507struct i_format { /* signed immediate format */
508 BITFIELD_FIELD(unsigned int opcode : 6, 508 __BITFIELD_FIELD(unsigned int opcode : 6,
509 BITFIELD_FIELD(unsigned int rs : 5, 509 __BITFIELD_FIELD(unsigned int rs : 5,
510 BITFIELD_FIELD(unsigned int rt : 5, 510 __BITFIELD_FIELD(unsigned int rt : 5,
511 BITFIELD_FIELD(signed int simmediate : 16, 511 __BITFIELD_FIELD(signed int simmediate : 16,
512 ;)))) 512 ;))))
513}; 513};
514 514
515struct u_format { /* unsigned immediate format */ 515struct u_format { /* unsigned immediate format */
516 BITFIELD_FIELD(unsigned int opcode : 6, 516 __BITFIELD_FIELD(unsigned int opcode : 6,
517 BITFIELD_FIELD(unsigned int rs : 5, 517 __BITFIELD_FIELD(unsigned int rs : 5,
518 BITFIELD_FIELD(unsigned int rt : 5, 518 __BITFIELD_FIELD(unsigned int rt : 5,
519 BITFIELD_FIELD(unsigned int uimmediate : 16, 519 __BITFIELD_FIELD(unsigned int uimmediate : 16,
520 ;)))) 520 ;))))
521}; 521};
522 522
523struct c_format { /* Cache (>= R6000) format */ 523struct c_format { /* Cache (>= R6000) format */
524 BITFIELD_FIELD(unsigned int opcode : 6, 524 __BITFIELD_FIELD(unsigned int opcode : 6,
525 BITFIELD_FIELD(unsigned int rs : 5, 525 __BITFIELD_FIELD(unsigned int rs : 5,
526 BITFIELD_FIELD(unsigned int c_op : 3, 526 __BITFIELD_FIELD(unsigned int c_op : 3,
527 BITFIELD_FIELD(unsigned int cache : 2, 527 __BITFIELD_FIELD(unsigned int cache : 2,
528 BITFIELD_FIELD(unsigned int simmediate : 16, 528 __BITFIELD_FIELD(unsigned int simmediate : 16,
529 ;))))) 529 ;)))))
530}; 530};
531 531
532struct r_format { /* Register format */ 532struct r_format { /* Register format */
533 BITFIELD_FIELD(unsigned int opcode : 6, 533 __BITFIELD_FIELD(unsigned int opcode : 6,
534 BITFIELD_FIELD(unsigned int rs : 5, 534 __BITFIELD_FIELD(unsigned int rs : 5,
535 BITFIELD_FIELD(unsigned int rt : 5, 535 __BITFIELD_FIELD(unsigned int rt : 5,
536 BITFIELD_FIELD(unsigned int rd : 5, 536 __BITFIELD_FIELD(unsigned int rd : 5,
537 BITFIELD_FIELD(unsigned int re : 5, 537 __BITFIELD_FIELD(unsigned int re : 5,
538 BITFIELD_FIELD(unsigned int func : 6, 538 __BITFIELD_FIELD(unsigned int func : 6,
539 ;)))))) 539 ;))))))
540}; 540};
541 541
542struct p_format { /* Performance counter format (R10000) */ 542struct p_format { /* Performance counter format (R10000) */
543 BITFIELD_FIELD(unsigned int opcode : 6, 543 __BITFIELD_FIELD(unsigned int opcode : 6,
544 BITFIELD_FIELD(unsigned int rs : 5, 544 __BITFIELD_FIELD(unsigned int rs : 5,
545 BITFIELD_FIELD(unsigned int rt : 5, 545 __BITFIELD_FIELD(unsigned int rt : 5,
546 BITFIELD_FIELD(unsigned int rd : 5, 546 __BITFIELD_FIELD(unsigned int rd : 5,
547 BITFIELD_FIELD(unsigned int re : 5, 547 __BITFIELD_FIELD(unsigned int re : 5,
548 BITFIELD_FIELD(unsigned int func : 6, 548 __BITFIELD_FIELD(unsigned int func : 6,
549 ;)))))) 549 ;))))))
550}; 550};
551 551
552struct f_format { /* FPU register format */ 552struct f_format { /* FPU register format */
553 BITFIELD_FIELD(unsigned int opcode : 6, 553 __BITFIELD_FIELD(unsigned int opcode : 6,
554 BITFIELD_FIELD(unsigned int : 1, 554 __BITFIELD_FIELD(unsigned int : 1,
555 BITFIELD_FIELD(unsigned int fmt : 4, 555 __BITFIELD_FIELD(unsigned int fmt : 4,
556 BITFIELD_FIELD(unsigned int rt : 5, 556 __BITFIELD_FIELD(unsigned int rt : 5,
557 BITFIELD_FIELD(unsigned int rd : 5, 557 __BITFIELD_FIELD(unsigned int rd : 5,
558 BITFIELD_FIELD(unsigned int re : 5, 558 __BITFIELD_FIELD(unsigned int re : 5,
559 BITFIELD_FIELD(unsigned int func : 6, 559 __BITFIELD_FIELD(unsigned int func : 6,
560 ;))))))) 560 ;)))))))
561}; 561};
562 562
563struct ma_format { /* FPU multiply and add format (MIPS IV) */ 563struct ma_format { /* FPU multiply and add format (MIPS IV) */
564 BITFIELD_FIELD(unsigned int opcode : 6, 564 __BITFIELD_FIELD(unsigned int opcode : 6,
565 BITFIELD_FIELD(unsigned int fr : 5, 565 __BITFIELD_FIELD(unsigned int fr : 5,
566 BITFIELD_FIELD(unsigned int ft : 5, 566 __BITFIELD_FIELD(unsigned int ft : 5,
567 BITFIELD_FIELD(unsigned int fs : 5, 567 __BITFIELD_FIELD(unsigned int fs : 5,
568 BITFIELD_FIELD(unsigned int fd : 5, 568 __BITFIELD_FIELD(unsigned int fd : 5,
569 BITFIELD_FIELD(unsigned int func : 4, 569 __BITFIELD_FIELD(unsigned int func : 4,
570 BITFIELD_FIELD(unsigned int fmt : 2, 570 __BITFIELD_FIELD(unsigned int fmt : 2,
571 ;))))))) 571 ;)))))))
572}; 572};
573 573
574struct b_format { /* BREAK and SYSCALL */ 574struct b_format { /* BREAK and SYSCALL */
575 BITFIELD_FIELD(unsigned int opcode : 6, 575 __BITFIELD_FIELD(unsigned int opcode : 6,
576 BITFIELD_FIELD(unsigned int code : 20, 576 __BITFIELD_FIELD(unsigned int code : 20,
577 BITFIELD_FIELD(unsigned int func : 6, 577 __BITFIELD_FIELD(unsigned int func : 6,
578 ;))) 578 ;)))
579}; 579};
580 580
581struct ps_format { /* MIPS-3D / paired single format */ 581struct ps_format { /* MIPS-3D / paired single format */
582 BITFIELD_FIELD(unsigned int opcode : 6, 582 __BITFIELD_FIELD(unsigned int opcode : 6,
583 BITFIELD_FIELD(unsigned int rs : 5, 583 __BITFIELD_FIELD(unsigned int rs : 5,
584 BITFIELD_FIELD(unsigned int ft : 5, 584 __BITFIELD_FIELD(unsigned int ft : 5,
585 BITFIELD_FIELD(unsigned int fs : 5, 585 __BITFIELD_FIELD(unsigned int fs : 5,
586 BITFIELD_FIELD(unsigned int fd : 5, 586 __BITFIELD_FIELD(unsigned int fd : 5,
587 BITFIELD_FIELD(unsigned int func : 6, 587 __BITFIELD_FIELD(unsigned int func : 6,
588 ;)))))) 588 ;))))))
589}; 589};
590 590
591struct v_format { /* MDMX vector format */ 591struct v_format { /* MDMX vector format */
592 BITFIELD_FIELD(unsigned int opcode : 6, 592 __BITFIELD_FIELD(unsigned int opcode : 6,
593 BITFIELD_FIELD(unsigned int sel : 4, 593 __BITFIELD_FIELD(unsigned int sel : 4,
594 BITFIELD_FIELD(unsigned int fmt : 1, 594 __BITFIELD_FIELD(unsigned int fmt : 1,
595 BITFIELD_FIELD(unsigned int vt : 5, 595 __BITFIELD_FIELD(unsigned int vt : 5,
596 BITFIELD_FIELD(unsigned int vs : 5, 596 __BITFIELD_FIELD(unsigned int vs : 5,
597 BITFIELD_FIELD(unsigned int vd : 5, 597 __BITFIELD_FIELD(unsigned int vd : 5,
598 BITFIELD_FIELD(unsigned int func : 6, 598 __BITFIELD_FIELD(unsigned int func : 6,
599 ;))))))) 599 ;)))))))
600}; 600};
601 601
602struct spec3_format { /* SPEC3 */ 602struct spec3_format { /* SPEC3 */
603 BITFIELD_FIELD(unsigned int opcode:6, 603 __BITFIELD_FIELD(unsigned int opcode:6,
604 BITFIELD_FIELD(unsigned int rs:5, 604 __BITFIELD_FIELD(unsigned int rs:5,
605 BITFIELD_FIELD(unsigned int rt:5, 605 __BITFIELD_FIELD(unsigned int rt:5,
606 BITFIELD_FIELD(signed int simmediate:9, 606 __BITFIELD_FIELD(signed int simmediate:9,
607 BITFIELD_FIELD(unsigned int func:7, 607 __BITFIELD_FIELD(unsigned int func:7,
608 ;))))) 608 ;)))))
609}; 609};
610 610
@@ -616,141 +616,141 @@ struct spec3_format { /* SPEC3 */
616 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE. 616 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
617 */ 617 */
618struct fb_format { /* FPU branch format (MIPS32) */ 618struct fb_format { /* FPU branch format (MIPS32) */
619 BITFIELD_FIELD(unsigned int opcode : 6, 619 __BITFIELD_FIELD(unsigned int opcode : 6,
620 BITFIELD_FIELD(unsigned int bc : 5, 620 __BITFIELD_FIELD(unsigned int bc : 5,
621 BITFIELD_FIELD(unsigned int cc : 3, 621 __BITFIELD_FIELD(unsigned int cc : 3,
622 BITFIELD_FIELD(unsigned int flag : 2, 622 __BITFIELD_FIELD(unsigned int flag : 2,
623 BITFIELD_FIELD(signed int simmediate : 16, 623 __BITFIELD_FIELD(signed int simmediate : 16,
624 ;))))) 624 ;)))))
625}; 625};
626 626
627struct fp0_format { /* FPU multiply and add format (MIPS32) */ 627struct fp0_format { /* FPU multiply and add format (MIPS32) */
628 BITFIELD_FIELD(unsigned int opcode : 6, 628 __BITFIELD_FIELD(unsigned int opcode : 6,
629 BITFIELD_FIELD(unsigned int fmt : 5, 629 __BITFIELD_FIELD(unsigned int fmt : 5,
630 BITFIELD_FIELD(unsigned int ft : 5, 630 __BITFIELD_FIELD(unsigned int ft : 5,
631 BITFIELD_FIELD(unsigned int fs : 5, 631 __BITFIELD_FIELD(unsigned int fs : 5,
632 BITFIELD_FIELD(unsigned int fd : 5, 632 __BITFIELD_FIELD(unsigned int fd : 5,
633 BITFIELD_FIELD(unsigned int func : 6, 633 __BITFIELD_FIELD(unsigned int func : 6,
634 ;)))))) 634 ;))))))
635}; 635};
636 636
637struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */ 637struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */
638 BITFIELD_FIELD(unsigned int opcode : 6, 638 __BITFIELD_FIELD(unsigned int opcode : 6,
639 BITFIELD_FIELD(unsigned int ft : 5, 639 __BITFIELD_FIELD(unsigned int ft : 5,
640 BITFIELD_FIELD(unsigned int fs : 5, 640 __BITFIELD_FIELD(unsigned int fs : 5,
641 BITFIELD_FIELD(unsigned int fd : 5, 641 __BITFIELD_FIELD(unsigned int fd : 5,
642 BITFIELD_FIELD(unsigned int fmt : 3, 642 __BITFIELD_FIELD(unsigned int fmt : 3,
643 BITFIELD_FIELD(unsigned int op : 2, 643 __BITFIELD_FIELD(unsigned int op : 2,
644 BITFIELD_FIELD(unsigned int func : 6, 644 __BITFIELD_FIELD(unsigned int func : 6,
645 ;))))))) 645 ;)))))))
646}; 646};
647 647
648struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */ 648struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
649 BITFIELD_FIELD(unsigned int opcode : 6, 649 __BITFIELD_FIELD(unsigned int opcode : 6,
650 BITFIELD_FIELD(unsigned int op : 5, 650 __BITFIELD_FIELD(unsigned int op : 5,
651 BITFIELD_FIELD(unsigned int rt : 5, 651 __BITFIELD_FIELD(unsigned int rt : 5,
652 BITFIELD_FIELD(unsigned int fs : 5, 652 __BITFIELD_FIELD(unsigned int fs : 5,
653 BITFIELD_FIELD(unsigned int fd : 5, 653 __BITFIELD_FIELD(unsigned int fd : 5,
654 BITFIELD_FIELD(unsigned int func : 6, 654 __BITFIELD_FIELD(unsigned int func : 6,
655 ;)))))) 655 ;))))))
656}; 656};
657 657
658struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */ 658struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
659 BITFIELD_FIELD(unsigned int opcode : 6, 659 __BITFIELD_FIELD(unsigned int opcode : 6,
660 BITFIELD_FIELD(unsigned int rt : 5, 660 __BITFIELD_FIELD(unsigned int rt : 5,
661 BITFIELD_FIELD(unsigned int fs : 5, 661 __BITFIELD_FIELD(unsigned int fs : 5,
662 BITFIELD_FIELD(unsigned int fmt : 2, 662 __BITFIELD_FIELD(unsigned int fmt : 2,
663 BITFIELD_FIELD(unsigned int op : 8, 663 __BITFIELD_FIELD(unsigned int op : 8,
664 BITFIELD_FIELD(unsigned int func : 6, 664 __BITFIELD_FIELD(unsigned int func : 6,
665 ;)))))) 665 ;))))))
666}; 666};
667 667
668struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */ 668struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
669 BITFIELD_FIELD(unsigned int opcode : 6, 669 __BITFIELD_FIELD(unsigned int opcode : 6,
670 BITFIELD_FIELD(unsigned int fd : 5, 670 __BITFIELD_FIELD(unsigned int fd : 5,
671 BITFIELD_FIELD(unsigned int fs : 5, 671 __BITFIELD_FIELD(unsigned int fs : 5,
672 BITFIELD_FIELD(unsigned int cc : 3, 672 __BITFIELD_FIELD(unsigned int cc : 3,
673 BITFIELD_FIELD(unsigned int zero : 2, 673 __BITFIELD_FIELD(unsigned int zero : 2,
674 BITFIELD_FIELD(unsigned int fmt : 2, 674 __BITFIELD_FIELD(unsigned int fmt : 2,
675 BITFIELD_FIELD(unsigned int op : 3, 675 __BITFIELD_FIELD(unsigned int op : 3,
676 BITFIELD_FIELD(unsigned int func : 6, 676 __BITFIELD_FIELD(unsigned int func : 6,
677 ;)))))))) 677 ;))))))))
678}; 678};
679 679
680struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */ 680struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
681 BITFIELD_FIELD(unsigned int opcode : 6, 681 __BITFIELD_FIELD(unsigned int opcode : 6,
682 BITFIELD_FIELD(unsigned int rt : 5, 682 __BITFIELD_FIELD(unsigned int rt : 5,
683 BITFIELD_FIELD(unsigned int fs : 5, 683 __BITFIELD_FIELD(unsigned int fs : 5,
684 BITFIELD_FIELD(unsigned int fmt : 3, 684 __BITFIELD_FIELD(unsigned int fmt : 3,
685 BITFIELD_FIELD(unsigned int op : 7, 685 __BITFIELD_FIELD(unsigned int op : 7,
686 BITFIELD_FIELD(unsigned int func : 6, 686 __BITFIELD_FIELD(unsigned int func : 6,
687 ;)))))) 687 ;))))))
688}; 688};
689 689
690struct mm_fp4_format { /* FPU c.cond format (microMIPS) */ 690struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
691 BITFIELD_FIELD(unsigned int opcode : 6, 691 __BITFIELD_FIELD(unsigned int opcode : 6,
692 BITFIELD_FIELD(unsigned int rt : 5, 692 __BITFIELD_FIELD(unsigned int rt : 5,
693 BITFIELD_FIELD(unsigned int fs : 5, 693 __BITFIELD_FIELD(unsigned int fs : 5,
694 BITFIELD_FIELD(unsigned int cc : 3, 694 __BITFIELD_FIELD(unsigned int cc : 3,
695 BITFIELD_FIELD(unsigned int fmt : 3, 695 __BITFIELD_FIELD(unsigned int fmt : 3,
696 BITFIELD_FIELD(unsigned int cond : 4, 696 __BITFIELD_FIELD(unsigned int cond : 4,
697 BITFIELD_FIELD(unsigned int func : 6, 697 __BITFIELD_FIELD(unsigned int func : 6,
698 ;))))))) 698 ;)))))))
699}; 699};
700 700
701struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */ 701struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
702 BITFIELD_FIELD(unsigned int opcode : 6, 702 __BITFIELD_FIELD(unsigned int opcode : 6,
703 BITFIELD_FIELD(unsigned int index : 5, 703 __BITFIELD_FIELD(unsigned int index : 5,
704 BITFIELD_FIELD(unsigned int base : 5, 704 __BITFIELD_FIELD(unsigned int base : 5,
705 BITFIELD_FIELD(unsigned int fd : 5, 705 __BITFIELD_FIELD(unsigned int fd : 5,
706 BITFIELD_FIELD(unsigned int op : 5, 706 __BITFIELD_FIELD(unsigned int op : 5,
707 BITFIELD_FIELD(unsigned int func : 6, 707 __BITFIELD_FIELD(unsigned int func : 6,
708 ;)))))) 708 ;))))))
709}; 709};
710 710
711struct fp6_format { /* FPU madd and msub format (MIPS IV) */ 711struct fp6_format { /* FPU madd and msub format (MIPS IV) */
712 BITFIELD_FIELD(unsigned int opcode : 6, 712 __BITFIELD_FIELD(unsigned int opcode : 6,
713 BITFIELD_FIELD(unsigned int fr : 5, 713 __BITFIELD_FIELD(unsigned int fr : 5,
714 BITFIELD_FIELD(unsigned int ft : 5, 714 __BITFIELD_FIELD(unsigned int ft : 5,
715 BITFIELD_FIELD(unsigned int fs : 5, 715 __BITFIELD_FIELD(unsigned int fs : 5,
716 BITFIELD_FIELD(unsigned int fd : 5, 716 __BITFIELD_FIELD(unsigned int fd : 5,
717 BITFIELD_FIELD(unsigned int func : 6, 717 __BITFIELD_FIELD(unsigned int func : 6,
718 ;)))))) 718 ;))))))
719}; 719};
720 720
721struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */ 721struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
722 BITFIELD_FIELD(unsigned int opcode : 6, 722 __BITFIELD_FIELD(unsigned int opcode : 6,
723 BITFIELD_FIELD(unsigned int ft : 5, 723 __BITFIELD_FIELD(unsigned int ft : 5,
724 BITFIELD_FIELD(unsigned int fs : 5, 724 __BITFIELD_FIELD(unsigned int fs : 5,
725 BITFIELD_FIELD(unsigned int fd : 5, 725 __BITFIELD_FIELD(unsigned int fd : 5,
726 BITFIELD_FIELD(unsigned int fr : 5, 726 __BITFIELD_FIELD(unsigned int fr : 5,
727 BITFIELD_FIELD(unsigned int func : 6, 727 __BITFIELD_FIELD(unsigned int func : 6,
728 ;)))))) 728 ;))))))
729}; 729};
730 730
731struct mm_i_format { /* Immediate format (microMIPS) */ 731struct mm_i_format { /* Immediate format (microMIPS) */
732 BITFIELD_FIELD(unsigned int opcode : 6, 732 __BITFIELD_FIELD(unsigned int opcode : 6,
733 BITFIELD_FIELD(unsigned int rt : 5, 733 __BITFIELD_FIELD(unsigned int rt : 5,
734 BITFIELD_FIELD(unsigned int rs : 5, 734 __BITFIELD_FIELD(unsigned int rs : 5,
735 BITFIELD_FIELD(signed int simmediate : 16, 735 __BITFIELD_FIELD(signed int simmediate : 16,
736 ;)))) 736 ;))))
737}; 737};
738 738
739struct mm_m_format { /* Multi-word load/store format (microMIPS) */ 739struct mm_m_format { /* Multi-word load/store format (microMIPS) */
740 BITFIELD_FIELD(unsigned int opcode : 6, 740 __BITFIELD_FIELD(unsigned int opcode : 6,
741 BITFIELD_FIELD(unsigned int rd : 5, 741 __BITFIELD_FIELD(unsigned int rd : 5,
742 BITFIELD_FIELD(unsigned int base : 5, 742 __BITFIELD_FIELD(unsigned int base : 5,
743 BITFIELD_FIELD(unsigned int func : 4, 743 __BITFIELD_FIELD(unsigned int func : 4,
744 BITFIELD_FIELD(signed int simmediate : 12, 744 __BITFIELD_FIELD(signed int simmediate : 12,
745 ;))))) 745 ;)))))
746}; 746};
747 747
748struct mm_x_format { /* Scaled indexed load format (microMIPS) */ 748struct mm_x_format { /* Scaled indexed load format (microMIPS) */
749 BITFIELD_FIELD(unsigned int opcode : 6, 749 __BITFIELD_FIELD(unsigned int opcode : 6,
750 BITFIELD_FIELD(unsigned int index : 5, 750 __BITFIELD_FIELD(unsigned int index : 5,
751 BITFIELD_FIELD(unsigned int base : 5, 751 __BITFIELD_FIELD(unsigned int base : 5,
752 BITFIELD_FIELD(unsigned int rd : 5, 752 __BITFIELD_FIELD(unsigned int rd : 5,
753 BITFIELD_FIELD(unsigned int func : 11, 753 __BITFIELD_FIELD(unsigned int func : 11,
754 ;))))) 754 ;)))))
755}; 755};
756 756
@@ -758,51 +758,51 @@ struct mm_x_format { /* Scaled indexed load format (microMIPS) */
758 * microMIPS instruction formats (16-bit length) 758 * microMIPS instruction formats (16-bit length)
759 */ 759 */
760struct mm_b0_format { /* Unconditional branch format (microMIPS) */ 760struct mm_b0_format { /* Unconditional branch format (microMIPS) */
761 BITFIELD_FIELD(unsigned int opcode : 6, 761 __BITFIELD_FIELD(unsigned int opcode : 6,
762 BITFIELD_FIELD(signed int simmediate : 10, 762 __BITFIELD_FIELD(signed int simmediate : 10,
763 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 763 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
764 ;))) 764 ;)))
765}; 765};
766 766
767struct mm_b1_format { /* Conditional branch format (microMIPS) */ 767struct mm_b1_format { /* Conditional branch format (microMIPS) */
768 BITFIELD_FIELD(unsigned int opcode : 6, 768 __BITFIELD_FIELD(unsigned int opcode : 6,
769 BITFIELD_FIELD(unsigned int rs : 3, 769 __BITFIELD_FIELD(unsigned int rs : 3,
770 BITFIELD_FIELD(signed int simmediate : 7, 770 __BITFIELD_FIELD(signed int simmediate : 7,
771 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 771 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
772 ;)))) 772 ;))))
773}; 773};
774 774
775struct mm16_m_format { /* Multi-word load/store format */ 775struct mm16_m_format { /* Multi-word load/store format */
776 BITFIELD_FIELD(unsigned int opcode : 6, 776 __BITFIELD_FIELD(unsigned int opcode : 6,
777 BITFIELD_FIELD(unsigned int func : 4, 777 __BITFIELD_FIELD(unsigned int func : 4,
778 BITFIELD_FIELD(unsigned int rlist : 2, 778 __BITFIELD_FIELD(unsigned int rlist : 2,
779 BITFIELD_FIELD(unsigned int imm : 4, 779 __BITFIELD_FIELD(unsigned int imm : 4,
780 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 780 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
781 ;))))) 781 ;)))))
782}; 782};
783 783
784struct mm16_rb_format { /* Signed immediate format */ 784struct mm16_rb_format { /* Signed immediate format */
785 BITFIELD_FIELD(unsigned int opcode : 6, 785 __BITFIELD_FIELD(unsigned int opcode : 6,
786 BITFIELD_FIELD(unsigned int rt : 3, 786 __BITFIELD_FIELD(unsigned int rt : 3,
787 BITFIELD_FIELD(unsigned int base : 3, 787 __BITFIELD_FIELD(unsigned int base : 3,
788 BITFIELD_FIELD(signed int simmediate : 4, 788 __BITFIELD_FIELD(signed int simmediate : 4,
789 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 789 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
790 ;))))) 790 ;)))))
791}; 791};
792 792
793struct mm16_r3_format { /* Load from global pointer format */ 793struct mm16_r3_format { /* Load from global pointer format */
794 BITFIELD_FIELD(unsigned int opcode : 6, 794 __BITFIELD_FIELD(unsigned int opcode : 6,
795 BITFIELD_FIELD(unsigned int rt : 3, 795 __BITFIELD_FIELD(unsigned int rt : 3,
796 BITFIELD_FIELD(signed int simmediate : 7, 796 __BITFIELD_FIELD(signed int simmediate : 7,
797 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 797 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
798 ;)))) 798 ;))))
799}; 799};
800 800
801struct mm16_r5_format { /* Load/store from stack pointer format */ 801struct mm16_r5_format { /* Load/store from stack pointer format */
802 BITFIELD_FIELD(unsigned int opcode : 6, 802 __BITFIELD_FIELD(unsigned int opcode : 6,
803 BITFIELD_FIELD(unsigned int rt : 5, 803 __BITFIELD_FIELD(unsigned int rt : 5,
804 BITFIELD_FIELD(signed int simmediate : 5, 804 __BITFIELD_FIELD(signed int simmediate : 5,
805 BITFIELD_FIELD(unsigned int : 16, /* Ignored */ 805 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
806 ;)))) 806 ;))))
807}; 807};
808 808
@@ -810,57 +810,57 @@ struct mm16_r5_format { /* Load/store from stack pointer format */
810 * MIPS16e instruction formats (16-bit length) 810 * MIPS16e instruction formats (16-bit length)
811 */ 811 */
812struct m16e_rr { 812struct m16e_rr {
813 BITFIELD_FIELD(unsigned int opcode : 5, 813 __BITFIELD_FIELD(unsigned int opcode : 5,
814 BITFIELD_FIELD(unsigned int rx : 3, 814 __BITFIELD_FIELD(unsigned int rx : 3,
815 BITFIELD_FIELD(unsigned int nd : 1, 815 __BITFIELD_FIELD(unsigned int nd : 1,
816 BITFIELD_FIELD(unsigned int l : 1, 816 __BITFIELD_FIELD(unsigned int l : 1,
817 BITFIELD_FIELD(unsigned int ra : 1, 817 __BITFIELD_FIELD(unsigned int ra : 1,
818 BITFIELD_FIELD(unsigned int func : 5, 818 __BITFIELD_FIELD(unsigned int func : 5,
819 ;)))))) 819 ;))))))
820}; 820};
821 821
822struct m16e_jal { 822struct m16e_jal {
823 BITFIELD_FIELD(unsigned int opcode : 5, 823 __BITFIELD_FIELD(unsigned int opcode : 5,
824 BITFIELD_FIELD(unsigned int x : 1, 824 __BITFIELD_FIELD(unsigned int x : 1,
825 BITFIELD_FIELD(unsigned int imm20_16 : 5, 825 __BITFIELD_FIELD(unsigned int imm20_16 : 5,
826 BITFIELD_FIELD(signed int imm25_21 : 5, 826 __BITFIELD_FIELD(signed int imm25_21 : 5,
827 ;)))) 827 ;))))
828}; 828};
829 829
830struct m16e_i64 { 830struct m16e_i64 {
831 BITFIELD_FIELD(unsigned int opcode : 5, 831 __BITFIELD_FIELD(unsigned int opcode : 5,
832 BITFIELD_FIELD(unsigned int func : 3, 832 __BITFIELD_FIELD(unsigned int func : 3,
833 BITFIELD_FIELD(unsigned int imm : 8, 833 __BITFIELD_FIELD(unsigned int imm : 8,
834 ;))) 834 ;)))
835}; 835};
836 836
837struct m16e_ri64 { 837struct m16e_ri64 {
838 BITFIELD_FIELD(unsigned int opcode : 5, 838 __BITFIELD_FIELD(unsigned int opcode : 5,
839 BITFIELD_FIELD(unsigned int func : 3, 839 __BITFIELD_FIELD(unsigned int func : 3,
840 BITFIELD_FIELD(unsigned int ry : 3, 840 __BITFIELD_FIELD(unsigned int ry : 3,
841 BITFIELD_FIELD(unsigned int imm : 5, 841 __BITFIELD_FIELD(unsigned int imm : 5,
842 ;)))) 842 ;))))
843}; 843};
844 844
845struct m16e_ri { 845struct m16e_ri {
846 BITFIELD_FIELD(unsigned int opcode : 5, 846 __BITFIELD_FIELD(unsigned int opcode : 5,
847 BITFIELD_FIELD(unsigned int rx : 3, 847 __BITFIELD_FIELD(unsigned int rx : 3,
848 BITFIELD_FIELD(unsigned int imm : 8, 848 __BITFIELD_FIELD(unsigned int imm : 8,
849 ;))) 849 ;)))
850}; 850};
851 851
852struct m16e_rri { 852struct m16e_rri {
853 BITFIELD_FIELD(unsigned int opcode : 5, 853 __BITFIELD_FIELD(unsigned int opcode : 5,
854 BITFIELD_FIELD(unsigned int rx : 3, 854 __BITFIELD_FIELD(unsigned int rx : 3,
855 BITFIELD_FIELD(unsigned int ry : 3, 855 __BITFIELD_FIELD(unsigned int ry : 3,
856 BITFIELD_FIELD(unsigned int imm : 5, 856 __BITFIELD_FIELD(unsigned int imm : 5,
857 ;)))) 857 ;))))
858}; 858};
859 859
860struct m16e_i8 { 860struct m16e_i8 {
861 BITFIELD_FIELD(unsigned int opcode : 5, 861 __BITFIELD_FIELD(unsigned int opcode : 5,
862 BITFIELD_FIELD(unsigned int func : 3, 862 __BITFIELD_FIELD(unsigned int func : 3,
863 BITFIELD_FIELD(unsigned int imm : 8, 863 __BITFIELD_FIELD(unsigned int imm : 8,
864 ;))) 864 ;)))
865}; 865};
866 866
diff --git a/arch/mips/include/uapi/asm/unistd.h b/arch/mips/include/uapi/asm/unistd.h
index d6e154a9e6a5..5805414777e0 100644
--- a/arch/mips/include/uapi/asm/unistd.h
+++ b/arch/mips/include/uapi/asm/unistd.h
@@ -371,16 +371,17 @@
371#define __NR_finit_module (__NR_Linux + 348) 371#define __NR_finit_module (__NR_Linux + 348)
372#define __NR_sched_setattr (__NR_Linux + 349) 372#define __NR_sched_setattr (__NR_Linux + 349)
373#define __NR_sched_getattr (__NR_Linux + 350) 373#define __NR_sched_getattr (__NR_Linux + 350)
374#define __NR_renameat2 (__NR_Linux + 351)
374 375
375/* 376/*
376 * Offset of the last Linux o32 flavoured syscall 377 * Offset of the last Linux o32 flavoured syscall
377 */ 378 */
378#define __NR_Linux_syscalls 350 379#define __NR_Linux_syscalls 351
379 380
380#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 381#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
381 382
382#define __NR_O32_Linux 4000 383#define __NR_O32_Linux 4000
383#define __NR_O32_Linux_syscalls 350 384#define __NR_O32_Linux_syscalls 351
384 385
385#if _MIPS_SIM == _MIPS_SIM_ABI64 386#if _MIPS_SIM == _MIPS_SIM_ABI64
386 387
@@ -699,16 +700,17 @@
699#define __NR_getdents64 (__NR_Linux + 308) 700#define __NR_getdents64 (__NR_Linux + 308)
700#define __NR_sched_setattr (__NR_Linux + 309) 701#define __NR_sched_setattr (__NR_Linux + 309)
701#define __NR_sched_getattr (__NR_Linux + 310) 702#define __NR_sched_getattr (__NR_Linux + 310)
703#define __NR_renameat2 (__NR_Linux + 311)
702 704
703/* 705/*
704 * Offset of the last Linux 64-bit flavoured syscall 706 * Offset of the last Linux 64-bit flavoured syscall
705 */ 707 */
706#define __NR_Linux_syscalls 310 708#define __NR_Linux_syscalls 311
707 709
708#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 710#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
709 711
710#define __NR_64_Linux 5000 712#define __NR_64_Linux 5000
711#define __NR_64_Linux_syscalls 310 713#define __NR_64_Linux_syscalls 311
712 714
713#if _MIPS_SIM == _MIPS_SIM_NABI32 715#if _MIPS_SIM == _MIPS_SIM_NABI32
714 716
@@ -1031,15 +1033,16 @@
1031#define __NR_finit_module (__NR_Linux + 312) 1033#define __NR_finit_module (__NR_Linux + 312)
1032#define __NR_sched_setattr (__NR_Linux + 313) 1034#define __NR_sched_setattr (__NR_Linux + 313)
1033#define __NR_sched_getattr (__NR_Linux + 314) 1035#define __NR_sched_getattr (__NR_Linux + 314)
1036#define __NR_renameat2 (__NR_Linux + 315)
1034 1037
1035/* 1038/*
1036 * Offset of the last N32 flavoured syscall 1039 * Offset of the last N32 flavoured syscall
1037 */ 1040 */
1038#define __NR_Linux_syscalls 314 1041#define __NR_Linux_syscalls 315
1039 1042
1040#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 1043#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
1041 1044
1042#define __NR_N32_Linux 6000 1045#define __NR_N32_Linux 6000
1043#define __NR_N32_Linux_syscalls 314 1046#define __NR_N32_Linux_syscalls 315
1044 1047
1045#endif /* _UAPI_ASM_UNISTD_H */ 1048#endif /* _UAPI_ASM_UNISTD_H */
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 4d78bf445a9c..76122ff5cb5e 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -317,7 +317,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
317 if (regs->regs[insn.i_format.rs] == 317 if (regs->regs[insn.i_format.rs] ==
318 regs->regs[insn.i_format.rt]) { 318 regs->regs[insn.i_format.rt]) {
319 epc = epc + 4 + (insn.i_format.simmediate << 2); 319 epc = epc + 4 + (insn.i_format.simmediate << 2);
320 if (insn.i_format.rt == beql_op) 320 if (insn.i_format.opcode == beql_op)
321 ret = BRANCH_LIKELY_TAKEN; 321 ret = BRANCH_LIKELY_TAKEN;
322 } else 322 } else
323 epc += 8; 323 epc += 8;
@@ -329,7 +329,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
329 if (regs->regs[insn.i_format.rs] != 329 if (regs->regs[insn.i_format.rs] !=
330 regs->regs[insn.i_format.rt]) { 330 regs->regs[insn.i_format.rt]) {
331 epc = epc + 4 + (insn.i_format.simmediate << 2); 331 epc = epc + 4 + (insn.i_format.simmediate << 2);
332 if (insn.i_format.rt == bnel_op) 332 if (insn.i_format.opcode == bnel_op)
333 ret = BRANCH_LIKELY_TAKEN; 333 ret = BRANCH_LIKELY_TAKEN;
334 } else 334 } else
335 epc += 8; 335 epc += 8;
@@ -341,7 +341,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
341 /* rt field assumed to be zero */ 341 /* rt field assumed to be zero */
342 if ((long)regs->regs[insn.i_format.rs] <= 0) { 342 if ((long)regs->regs[insn.i_format.rs] <= 0) {
343 epc = epc + 4 + (insn.i_format.simmediate << 2); 343 epc = epc + 4 + (insn.i_format.simmediate << 2);
344 if (insn.i_format.rt == bnel_op) 344 if (insn.i_format.opcode == blezl_op)
345 ret = BRANCH_LIKELY_TAKEN; 345 ret = BRANCH_LIKELY_TAKEN;
346 } else 346 } else
347 epc += 8; 347 epc += 8;
@@ -353,7 +353,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
353 /* rt field assumed to be zero */ 353 /* rt field assumed to be zero */
354 if ((long)regs->regs[insn.i_format.rs] > 0) { 354 if ((long)regs->regs[insn.i_format.rs] > 0) {
355 epc = epc + 4 + (insn.i_format.simmediate << 2); 355 epc = epc + 4 + (insn.i_format.simmediate << 2);
356 if (insn.i_format.rt == bnel_op) 356 if (insn.i_format.opcode == bgtzl_op)
357 ret = BRANCH_LIKELY_TAKEN; 357 ret = BRANCH_LIKELY_TAKEN;
358 } else 358 } else
359 epc += 8; 359 epc += 8;
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index e40971b51d2f..037a44d962f3 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -124,14 +124,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
124 seq_printf(m, "kscratch registers\t: %d\n", 124 seq_printf(m, "kscratch registers\t: %d\n",
125 hweight8(cpu_data[n].kscratch_mask)); 125 hweight8(cpu_data[n].kscratch_mask));
126 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); 126 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
127#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) 127
128 if (cpu_has_mipsmt) {
129 seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
130#if defined(CONFIG_MIPS_MT_SMTC)
131 seq_printf(m, "TC\t\t\t: %d\n", cpu_data[n].tc_id);
132#endif
133 }
134#endif
135 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", 128 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
136 cpu_has_vce ? "%u" : "not available"); 129 cpu_has_vce ? "%u" : "not available");
137 seq_printf(m, fmt, 'D', vced_count); 130 seq_printf(m, fmt, 'D', vced_count);
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 71f85f427034..f639ccd5060c 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -163,7 +163,7 @@ int ptrace_get_watch_regs(struct task_struct *child,
163 enum pt_watch_style style; 163 enum pt_watch_style style;
164 int i; 164 int i;
165 165
166 if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0) 166 if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
167 return -EIO; 167 return -EIO;
168 if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs))) 168 if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
169 return -EIO; 169 return -EIO;
@@ -177,14 +177,14 @@ int ptrace_get_watch_regs(struct task_struct *child,
177#endif 177#endif
178 178
179 __put_user(style, &addr->style); 179 __put_user(style, &addr->style);
180 __put_user(current_cpu_data.watch_reg_use_cnt, 180 __put_user(boot_cpu_data.watch_reg_use_cnt,
181 &addr->WATCH_STYLE.num_valid); 181 &addr->WATCH_STYLE.num_valid);
182 for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) { 182 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
183 __put_user(child->thread.watch.mips3264.watchlo[i], 183 __put_user(child->thread.watch.mips3264.watchlo[i],
184 &addr->WATCH_STYLE.watchlo[i]); 184 &addr->WATCH_STYLE.watchlo[i]);
185 __put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff, 185 __put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
186 &addr->WATCH_STYLE.watchhi[i]); 186 &addr->WATCH_STYLE.watchhi[i]);
187 __put_user(current_cpu_data.watch_reg_masks[i], 187 __put_user(boot_cpu_data.watch_reg_masks[i],
188 &addr->WATCH_STYLE.watch_masks[i]); 188 &addr->WATCH_STYLE.watch_masks[i]);
189 } 189 }
190 for (; i < 8; i++) { 190 for (; i < 8; i++) {
@@ -204,12 +204,12 @@ int ptrace_set_watch_regs(struct task_struct *child,
204 unsigned long lt[NUM_WATCH_REGS]; 204 unsigned long lt[NUM_WATCH_REGS];
205 u16 ht[NUM_WATCH_REGS]; 205 u16 ht[NUM_WATCH_REGS];
206 206
207 if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0) 207 if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0)
208 return -EIO; 208 return -EIO;
209 if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs))) 209 if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
210 return -EIO; 210 return -EIO;
211 /* Check the values. */ 211 /* Check the values. */
212 for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) { 212 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
213 __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]); 213 __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
214#ifdef CONFIG_32BIT 214#ifdef CONFIG_32BIT
215 if (lt[i] & __UA_LIMIT) 215 if (lt[i] & __UA_LIMIT)
@@ -228,7 +228,7 @@ int ptrace_set_watch_regs(struct task_struct *child,
228 return -EINVAL; 228 return -EINVAL;
229 } 229 }
230 /* Install them. */ 230 /* Install them. */
231 for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) { 231 for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
232 if (lt[i] & 7) 232 if (lt[i] & 7)
233 watch_active = 1; 233 watch_active = 1;
234 child->thread.watch.mips3264.watchlo[i] = lt[i]; 234 child->thread.watch.mips3264.watchlo[i] = lt[i];
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index fdc70b400442..3245474f19d5 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -577,3 +577,4 @@ EXPORT(sys_call_table)
577 PTR sys_finit_module 577 PTR sys_finit_module
578 PTR sys_sched_setattr 578 PTR sys_sched_setattr
579 PTR sys_sched_getattr /* 4350 */ 579 PTR sys_sched_getattr /* 4350 */
580 PTR sys_renameat2
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index dd99c3285aea..be2fedd4ae33 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -430,4 +430,5 @@ EXPORT(sys_call_table)
430 PTR sys_getdents64 430 PTR sys_getdents64
431 PTR sys_sched_setattr 431 PTR sys_sched_setattr
432 PTR sys_sched_getattr /* 5310 */ 432 PTR sys_sched_getattr /* 5310 */
433 PTR sys_renameat2
433 .size sys_call_table,.-sys_call_table 434 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index f68d2f4f0090..c1dbcda4b816 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -423,4 +423,5 @@ EXPORT(sysn32_call_table)
423 PTR sys_finit_module 423 PTR sys_finit_module
424 PTR sys_sched_setattr 424 PTR sys_sched_setattr
425 PTR sys_sched_getattr 425 PTR sys_sched_getattr
426 PTR sys_renameat2 /* 6315 */
426 .size sysn32_call_table,.-sysn32_call_table 427 .size sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 70f6acecd928..f1343ccd7ed7 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -556,4 +556,5 @@ EXPORT(sys32_call_table)
556 PTR sys_finit_module 556 PTR sys_finit_module
557 PTR sys_sched_setattr 557 PTR sys_sched_setattr
558 PTR sys_sched_getattr /* 4350 */ 558 PTR sys_sched_getattr /* 4350 */
559 PTR sys_renameat2
559 .size sys32_call_table,.-sys32_call_table 560 .size sys32_call_table,.-sys32_call_table
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 074e857ced28..8119ac2fdfc9 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1545,7 +1545,7 @@ asmlinkage void cache_parity_error(void)
1545 reg_val & (1<<30) ? "secondary" : "primary", 1545 reg_val & (1<<30) ? "secondary" : "primary",
1546 reg_val & (1<<31) ? "data" : "insn"); 1546 reg_val & (1<<31) ? "data" : "insn");
1547 if (cpu_has_mips_r2 && 1547 if (cpu_has_mips_r2 &&
1548 ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { 1548 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1549 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1549 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1550 reg_val & (1<<29) ? "ED " : "", 1550 reg_val & (1<<29) ? "ED " : "",
1551 reg_val & (1<<28) ? "ET " : "", 1551 reg_val & (1<<28) ? "ET " : "",
@@ -1585,7 +1585,7 @@ asmlinkage void do_ftlb(void)
1585 1585
1586 /* For the moment, report the problem and hang. */ 1586 /* For the moment, report the problem and hang. */
1587 if (cpu_has_mips_r2 && 1587 if (cpu_has_mips_r2 &&
1588 ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { 1588 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
1589 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1589 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1590 read_c0_ecc()); 1590 read_c0_ecc());
1591 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1591 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
diff --git a/arch/mips/lantiq/dts/easy50712.dts b/arch/mips/lantiq/dts/easy50712.dts
index fac1f5b178eb..143b8a37b5e4 100644
--- a/arch/mips/lantiq/dts/easy50712.dts
+++ b/arch/mips/lantiq/dts/easy50712.dts
@@ -8,6 +8,7 @@
8 }; 8 };
9 9
10 memory@0 { 10 memory@0 {
11 device_type = "memory";
11 reg = <0x0 0x2000000>; 12 reg = <0x0 0x2000000>;
12 }; 13 };
13 14
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 2e4825e48388..9901237563c5 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -56,14 +56,20 @@
56#define UNIT(unit) ((unit)*NBYTES) 56#define UNIT(unit) ((unit)*NBYTES)
57 57
58#define ADDC(sum,reg) \ 58#define ADDC(sum,reg) \
59 .set push; \
60 .set noat; \
59 ADD sum, reg; \ 61 ADD sum, reg; \
60 sltu v1, sum, reg; \ 62 sltu v1, sum, reg; \
61 ADD sum, v1; \ 63 ADD sum, v1; \
64 .set pop
62 65
63#define ADDC32(sum,reg) \ 66#define ADDC32(sum,reg) \
67 .set push; \
68 .set noat; \
64 addu sum, reg; \ 69 addu sum, reg; \
65 sltu v1, sum, reg; \ 70 sltu v1, sum, reg; \
66 addu sum, v1; \ 71 addu sum, v1; \
72 .set pop
67 73
68#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \ 74#define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \
69 LOAD _t0, (offset + UNIT(0))(src); \ 75 LOAD _t0, (offset + UNIT(0))(src); \
@@ -710,6 +716,8 @@ LEAF(csum_partial)
710 ADDC(sum, t2) 716 ADDC(sum, t2)
711.Ldone\@: 717.Ldone\@:
712 /* fold checksum */ 718 /* fold checksum */
719 .set push
720 .set noat
713#ifdef USE_DOUBLE 721#ifdef USE_DOUBLE
714 dsll32 v1, sum, 0 722 dsll32 v1, sum, 0
715 daddu sum, v1 723 daddu sum, v1
@@ -732,6 +740,7 @@ LEAF(csum_partial)
732 or sum, sum, t0 740 or sum, sum, t0
7331: 7411:
734#endif 742#endif
743 .set pop
735 .set reorder 744 .set reorder
736 ADDC32(sum, psum) 745 ADDC32(sum, psum)
737 jr ra 746 jr ra
diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c
index 44713af15a62..705cfb7c1a74 100644
--- a/arch/mips/lib/delay.c
+++ b/arch/mips/lib/delay.c
@@ -6,7 +6,7 @@
6 * Copyright (C) 1994 by Waldorf Electronics 6 * Copyright (C) 1994 by Waldorf Electronics
7 * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle 7 * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki 9 * Copyright (C) 2007, 2014 Maciej W. Rozycki
10 */ 10 */
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/param.h> 12#include <linux/param.h>
@@ -15,6 +15,12 @@
15#include <asm/compiler.h> 15#include <asm/compiler.h>
16#include <asm/war.h> 16#include <asm/war.h>
17 17
18#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
19#define GCC_DADDI_IMM_ASM() "I"
20#else
21#define GCC_DADDI_IMM_ASM() "r"
22#endif
23
18void __delay(unsigned long loops) 24void __delay(unsigned long loops)
19{ 25{
20 __asm__ __volatile__ ( 26 __asm__ __volatile__ (
@@ -22,13 +28,13 @@ void __delay(unsigned long loops)
22 " .align 3 \n" 28 " .align 3 \n"
23 "1: bnez %0, 1b \n" 29 "1: bnez %0, 1b \n"
24#if BITS_PER_LONG == 32 30#if BITS_PER_LONG == 32
25 " subu %0, 1 \n" 31 " subu %0, %1 \n"
26#else 32#else
27 " dsubu %0, 1 \n" 33 " dsubu %0, %1 \n"
28#endif 34#endif
29 " .set reorder \n" 35 " .set reorder \n"
30 : "=r" (loops) 36 : "=r" (loops)
31 : "0" (loops)); 37 : GCC_DADDI_IMM_ASM() (1), "0" (loops));
32} 38}
33EXPORT_SYMBOL(__delay); 39EXPORT_SYMBOL(__delay);
34 40
diff --git a/arch/mips/lib/strncpy_user.S b/arch/mips/lib/strncpy_user.S
index d3301cd1e9a5..3c32baf8b494 100644
--- a/arch/mips/lib/strncpy_user.S
+++ b/arch/mips/lib/strncpy_user.S
@@ -35,7 +35,6 @@ LEAF(__strncpy_from_\func\()_asm)
35 bnez v0, .Lfault\@ 35 bnez v0, .Lfault\@
36 36
37FEXPORT(__strncpy_from_\func\()_nocheck_asm) 37FEXPORT(__strncpy_from_\func\()_nocheck_asm)
38 .set noreorder
39 move t0, zero 38 move t0, zero
40 move v1, a1 39 move v1, a1
41.ifeqs "\func","kernel" 40.ifeqs "\func","kernel"
@@ -45,21 +44,21 @@ FEXPORT(__strncpy_from_\func\()_nocheck_asm)
45.endif 44.endif
46 PTR_ADDIU v1, 1 45 PTR_ADDIU v1, 1
47 R10KCBARRIER(0(ra)) 46 R10KCBARRIER(0(ra))
47 sb v0, (a0)
48 beqz v0, 2f 48 beqz v0, 2f
49 sb v0, (a0)
50 PTR_ADDIU t0, 1 49 PTR_ADDIU t0, 1
50 PTR_ADDIU a0, 1
51 bne t0, a2, 1b 51 bne t0, a2, 1b
52 PTR_ADDIU a0, 1
532: PTR_ADDU v0, a1, t0 522: PTR_ADDU v0, a1, t0
54 xor v0, a1 53 xor v0, a1
55 bltz v0, .Lfault\@ 54 bltz v0, .Lfault\@
56 nop 55 move v0, t0
57 jr ra # return n 56 jr ra # return n
58 move v0, t0
59 END(__strncpy_from_\func\()_asm) 57 END(__strncpy_from_\func\()_asm)
60 58
61.Lfault\@: jr ra 59.Lfault\@:
62 li v0, -EFAULT 60 li v0, -EFAULT
61 jr ra
63 62
64 .section __ex_table,"a" 63 .section __ex_table,"a"
65 PTR 1b, .Lfault\@ 64 PTR 1b, .Lfault\@
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index 7397be226a06..603d79a95f47 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -64,7 +64,6 @@ config LEMOTE_MACH3A
64 bool "Lemote Loongson 3A family machines" 64 bool "Lemote Loongson 3A family machines"
65 select ARCH_SPARSEMEM_ENABLE 65 select ARCH_SPARSEMEM_ENABLE
66 select GENERIC_ISA_DMA_SUPPORT_BROKEN 66 select GENERIC_ISA_DMA_SUPPORT_BROKEN
67 select GENERIC_HARDIRQS_NO__DO_IRQ
68 select BOOT_ELF32 67 select BOOT_ELF32
69 select BOARD_SCACHE 68 select BOARD_SCACHE
70 select CSRC_R4K 69 select CSRC_R4K
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
index c639b9db0012..12c75db23420 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -27,8 +27,7 @@
27 27
28#include <cs5536/cs5536_mfgpt.h> 28#include <cs5536/cs5536_mfgpt.h>
29 29
30DEFINE_SPINLOCK(mfgpt_lock); 30static DEFINE_RAW_SPINLOCK(mfgpt_lock);
31EXPORT_SYMBOL(mfgpt_lock);
32 31
33static u32 mfgpt_base; 32static u32 mfgpt_base;
34 33
@@ -55,7 +54,7 @@ EXPORT_SYMBOL(enable_mfgpt0_counter);
55static void init_mfgpt_timer(enum clock_event_mode mode, 54static void init_mfgpt_timer(enum clock_event_mode mode,
56 struct clock_event_device *evt) 55 struct clock_event_device *evt)
57{ 56{
58 spin_lock(&mfgpt_lock); 57 raw_spin_lock(&mfgpt_lock);
59 58
60 switch (mode) { 59 switch (mode) {
61 case CLOCK_EVT_MODE_PERIODIC: 60 case CLOCK_EVT_MODE_PERIODIC:
@@ -79,7 +78,7 @@ static void init_mfgpt_timer(enum clock_event_mode mode,
79 /* Nothing to do here */ 78 /* Nothing to do here */
80 break; 79 break;
81 } 80 }
82 spin_unlock(&mfgpt_lock); 81 raw_spin_unlock(&mfgpt_lock);
83} 82}
84 83
85static struct clock_event_device mfgpt_clockevent = { 84static struct clock_event_device mfgpt_clockevent = {
@@ -157,7 +156,7 @@ static cycle_t mfgpt_read(struct clocksource *cs)
157 static int old_count; 156 static int old_count;
158 static u32 old_jifs; 157 static u32 old_jifs;
159 158
160 spin_lock_irqsave(&mfgpt_lock, flags); 159 raw_spin_lock_irqsave(&mfgpt_lock, flags);
161 /* 160 /*
162 * Although our caller may have the read side of xtime_lock, 161 * Although our caller may have the read side of xtime_lock,
163 * this is now a seqlock, and we are cheating in this routine 162 * this is now a seqlock, and we are cheating in this routine
@@ -191,7 +190,7 @@ static cycle_t mfgpt_read(struct clocksource *cs)
191 old_count = count; 190 old_count = count;
192 old_jifs = jifs; 191 old_jifs = jifs;
193 192
194 spin_unlock_irqrestore(&mfgpt_lock, flags); 193 raw_spin_unlock_irqrestore(&mfgpt_lock, flags);
195 194
196 return (cycle_t) (jifs * COMPARE) + count; 195 return (cycle_t) (jifs * COMPARE) + count;
197} 196}
diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c
index e1f427f4f5f3..67dd94ef28e6 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -91,6 +91,7 @@ EXPORT_SYMBOL(clk_put);
91 91
92int clk_set_rate(struct clk *clk, unsigned long rate) 92int clk_set_rate(struct clk *clk, unsigned long rate)
93{ 93{
94 unsigned int rate_khz = rate / 1000;
94 int ret = 0; 95 int ret = 0;
95 int regval; 96 int regval;
96 int i; 97 int i;
@@ -111,10 +112,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
111 if (loongson2_clockmod_table[i].frequency == 112 if (loongson2_clockmod_table[i].frequency ==
112 CPUFREQ_ENTRY_INVALID) 113 CPUFREQ_ENTRY_INVALID)
113 continue; 114 continue;
114 if (rate == loongson2_clockmod_table[i].frequency) 115 if (rate_khz == loongson2_clockmod_table[i].frequency)
115 break; 116 break;
116 } 117 }
117 if (rate != loongson2_clockmod_table[i].frequency) 118 if (rate_khz != loongson2_clockmod_table[i].frequency)
118 return -ENOTSUPP; 119 return -ENOTSUPP;
119 120
120 clk->rate = rate; 121 clk->rate = rate;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index e422b38d3113..9e67cdea3c74 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -29,15 +29,15 @@ void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
29void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, 29void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
30 unsigned long pfn); 30 unsigned long pfn);
31void (*flush_icache_range)(unsigned long start, unsigned long end); 31void (*flush_icache_range)(unsigned long start, unsigned long end);
32EXPORT_SYMBOL_GPL(flush_icache_range);
32void (*local_flush_icache_range)(unsigned long start, unsigned long end); 33void (*local_flush_icache_range)(unsigned long start, unsigned long end);
33 34
34void (*__flush_cache_vmap)(void); 35void (*__flush_cache_vmap)(void);
35void (*__flush_cache_vunmap)(void); 36void (*__flush_cache_vunmap)(void);
36 37
37void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size); 38void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
38void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size);
39
40EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range); 39EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range);
40void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size);
41 41
42/* MIPS specific cache operations */ 42/* MIPS specific cache operations */
43void (*flush_cache_sigtramp)(unsigned long addr); 43void (*flush_cache_sigtramp)(unsigned long addr);
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 58033c44690d..b611102e23b5 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -273,7 +273,7 @@ void build_clear_page(void)
273 uasm_i_ori(&buf, A2, A0, off); 273 uasm_i_ori(&buf, A2, A0, off);
274 274
275 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) 275 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
276 uasm_i_lui(&buf, AT, 0xa000); 276 uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
277 277
278 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size) 278 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
279 * cache_line_size : 0; 279 * cache_line_size : 0;
@@ -424,7 +424,7 @@ void build_copy_page(void)
424 uasm_i_ori(&buf, A2, A0, off); 424 uasm_i_ori(&buf, A2, A0, off);
425 425
426 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) 426 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
427 uasm_i_lui(&buf, AT, 0xa000); 427 uasm_i_lui(&buf, AT, uasm_rel_hi(0xa0000000));
428 428
429 off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) * 429 off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
430 cache_line_size : 0; 430 cache_line_size : 0;
diff --git a/arch/mips/mm/tlb-funcs.S b/arch/mips/mm/tlb-funcs.S
index 30a494db99c2..a5427c6e9757 100644
--- a/arch/mips/mm/tlb-funcs.S
+++ b/arch/mips/mm/tlb-funcs.S
@@ -16,8 +16,10 @@
16 16
17#define FASTPATH_SIZE 128 17#define FASTPATH_SIZE 128
18 18
19EXPORT(tlbmiss_handler_setup_pgd_start)
19LEAF(tlbmiss_handler_setup_pgd) 20LEAF(tlbmiss_handler_setup_pgd)
20 .space 16 * 4 211: j 1b /* Dummy, will be replaced. */
22 .space 64
21END(tlbmiss_handler_setup_pgd) 23END(tlbmiss_handler_setup_pgd)
22EXPORT(tlbmiss_handler_setup_pgd_end) 24EXPORT(tlbmiss_handler_setup_pgd_end)
23 25
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index ee88367ab3ad..f99ec587b151 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1422,16 +1422,17 @@ static void build_r4000_tlb_refill_handler(void)
1422extern u32 handle_tlbl[], handle_tlbl_end[]; 1422extern u32 handle_tlbl[], handle_tlbl_end[];
1423extern u32 handle_tlbs[], handle_tlbs_end[]; 1423extern u32 handle_tlbs[], handle_tlbs_end[];
1424extern u32 handle_tlbm[], handle_tlbm_end[]; 1424extern u32 handle_tlbm[], handle_tlbm_end[];
1425extern u32 tlbmiss_handler_setup_pgd[], tlbmiss_handler_setup_pgd_end[]; 1425extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[];
1426extern u32 tlbmiss_handler_setup_pgd_end[];
1426 1427
1427static void build_setup_pgd(void) 1428static void build_setup_pgd(void)
1428{ 1429{
1429 const int a0 = 4; 1430 const int a0 = 4;
1430 const int __maybe_unused a1 = 5; 1431 const int __maybe_unused a1 = 5;
1431 const int __maybe_unused a2 = 6; 1432 const int __maybe_unused a2 = 6;
1432 u32 *p = tlbmiss_handler_setup_pgd; 1433 u32 *p = tlbmiss_handler_setup_pgd_start;
1433 const int tlbmiss_handler_setup_pgd_size = 1434 const int tlbmiss_handler_setup_pgd_size =
1434 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd; 1435 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start;
1435#ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1436#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1436 long pgdc = (long)pgd_current; 1437 long pgdc = (long)pgd_current;
1437#endif 1438#endif
diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index 6d0f4ab3632d..f2364e419682 100644
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -27,7 +27,7 @@ unsigned long physical_memsize = 0L;
27fw_memblock_t * __init fw_getmdesc(int eva) 27fw_memblock_t * __init fw_getmdesc(int eva)
28{ 28{
29 char *memsize_str, *ememsize_str __maybe_unused = NULL, *ptr; 29 char *memsize_str, *ememsize_str __maybe_unused = NULL, *ptr;
30 unsigned long memsize, ememsize __maybe_unused = 0; 30 unsigned long memsize = 0, ememsize __maybe_unused = 0;
31 static char cmdline[COMMAND_LINE_SIZE] __initdata; 31 static char cmdline[COMMAND_LINE_SIZE] __initdata;
32 int tmp; 32 int tmp;
33 33
diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
index b128cb973ebe..7f6ce6d734c0 100644
--- a/arch/mips/pci/pci-rc32434.c
+++ b/arch/mips/pci/pci-rc32434.c
@@ -53,7 +53,6 @@ static struct resource rc32434_res_pci_mem1 = {
53 .start = 0x50000000, 53 .start = 0x50000000,
54 .end = 0x5FFFFFFF, 54 .end = 0x5FFFFFFF,
55 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
56 .parent = &rc32434_res_pci_mem1,
57 .sibling = NULL, 56 .sibling = NULL,
58 .child = &rc32434_res_pci_mem2 57 .child = &rc32434_res_pci_mem2
59}; 58};
diff --git a/arch/mips/ralink/dts/mt7620a_eval.dts b/arch/mips/ralink/dts/mt7620a_eval.dts
index 35eb874ab7f1..709f58132f5c 100644
--- a/arch/mips/ralink/dts/mt7620a_eval.dts
+++ b/arch/mips/ralink/dts/mt7620a_eval.dts
@@ -7,6 +7,7 @@
7 model = "Ralink MT7620A evaluation board"; 7 model = "Ralink MT7620A evaluation board";
8 8
9 memory@0 { 9 memory@0 {
10 device_type = "memory";
10 reg = <0x0 0x2000000>; 11 reg = <0x0 0x2000000>;
11 }; 12 };
12 13
diff --git a/arch/mips/ralink/dts/rt2880_eval.dts b/arch/mips/ralink/dts/rt2880_eval.dts
index 322d7002595b..0a685db093d4 100644
--- a/arch/mips/ralink/dts/rt2880_eval.dts
+++ b/arch/mips/ralink/dts/rt2880_eval.dts
@@ -7,6 +7,7 @@
7 model = "Ralink RT2880 evaluation board"; 7 model = "Ralink RT2880 evaluation board";
8 8
9 memory@0 { 9 memory@0 {
10 device_type = "memory";
10 reg = <0x8000000 0x2000000>; 11 reg = <0x8000000 0x2000000>;
11 }; 12 };
12 13
diff --git a/arch/mips/ralink/dts/rt3052_eval.dts b/arch/mips/ralink/dts/rt3052_eval.dts
index 0ac73ea28198..ec9e9a035541 100644
--- a/arch/mips/ralink/dts/rt3052_eval.dts
+++ b/arch/mips/ralink/dts/rt3052_eval.dts
@@ -7,6 +7,7 @@
7 model = "Ralink RT3052 evaluation board"; 7 model = "Ralink RT3052 evaluation board";
8 8
9 memory@0 { 9 memory@0 {
10 device_type = "memory";
10 reg = <0x0 0x2000000>; 11 reg = <0x0 0x2000000>;
11 }; 12 };
12 13
diff --git a/arch/mips/ralink/dts/rt3883_eval.dts b/arch/mips/ralink/dts/rt3883_eval.dts
index 2fa6b330bf4f..e8df21a5d10d 100644
--- a/arch/mips/ralink/dts/rt3883_eval.dts
+++ b/arch/mips/ralink/dts/rt3883_eval.dts
@@ -7,6 +7,7 @@
7 model = "Ralink RT3883 evaluation board"; 7 model = "Ralink RT3883 evaluation board";
8 8
9 memory@0 { 9 memory@0 {
10 device_type = "memory";
10 reg = <0x0 0x2000000>; 11 reg = <0x0 0x2000000>;
11 }; 12 };
12 13
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 23:42:54 -0400