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-rw-r--r--arch/mips/mm/pg-sb1.c3
-rw-r--r--arch/mips/pci/pci-bcm1480.c2
-rw-r--r--arch/mips/pci/pci-sb1250.c2
-rw-r--r--arch/mips/sibyte/bcm1480/smp.c6
-rw-r--r--arch/mips/sibyte/swarm/setup.c18
5 files changed, 16 insertions, 15 deletions
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index fc3c7878fb45..adb37d0a30ea 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -218,8 +218,7 @@ void sb1_dma_init(void)
218 for (i = 0; i < DM_NUM_CHANNELS; i++) { 218 for (i = 0; i < DM_NUM_CHANNELS; i++) {
219 const u64 base_val = CPHYSADDR(&page_descr[i]) | 219 const u64 base_val = CPHYSADDR(&page_descr[i]) |
220 V_DM_DSCR_BASE_RINGSZ(1); 220 V_DM_DSCR_BASE_RINGSZ(1);
221 volatile void *base_reg = 221 void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
222 IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
223 222
224 __raw_writeq(base_val, base_reg); 223 __raw_writeq(base_val, base_reg);
225 __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg); 224 __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg);
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index f6774f54cd3c..d7b9e1349f6d 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -216,7 +216,7 @@ static int __init bcm1480_pcibios_init(void)
216 /* 216 /*
217 * See if the PCI bus has been configured by the firmware. 217 * See if the PCI bus has been configured by the firmware.
218 */ 218 */
219 reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG)); 219 reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
220 if (!(reg & M_BCM1480_SYS_PCI_HOST)) { 220 if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
221 bcm1480_bus_status |= PCI_DEVICE_MODE; 221 bcm1480_bus_status |= PCI_DEVICE_MODE;
222 } else { 222 } else {
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index 80f5e8c4bcd4..75c1246ced5f 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -228,7 +228,7 @@ static int __init sb1250_pcibios_init(void)
228 /* 228 /*
229 * See if the PCI bus has been configured by the firmware. 229 * See if the PCI bus has been configured by the firmware.
230 */ 230 */
231 reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG)); 231 reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
232 if (!(reg & M_SYS_PCI_HOST)) { 232 if (!(reg & M_SYS_PCI_HOST)) {
233 sb1250_bus_status |= PCI_DEVICE_MODE; 233 sb1250_bus_status |= PCI_DEVICE_MODE;
234 } else { 234 } else {
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index bf328277c775..6eac36d1b8c8 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -34,21 +34,21 @@ extern void smp_call_function_interrupt(void);
34 * independent of board/firmware 34 * independent of board/firmware
35 */ 35 */
36 36
37static volatile void *mailbox_0_set_regs[] = { 37static void *mailbox_0_set_regs[] = {
38 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 38 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
39 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 39 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
40 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 40 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
41 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), 41 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
42}; 42};
43 43
44static volatile void *mailbox_0_clear_regs[] = { 44static void *mailbox_0_clear_regs[] = {
45 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 45 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
46 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 46 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
47 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 47 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
48 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), 48 IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
49}; 49};
50 50
51static volatile void *mailbox_0_regs[] = { 51static void *mailbox_0_regs[] = {
52 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 52 IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
53 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 53 IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
54 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), 54 IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index defa1f1452ad..83572d8f3e14 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -169,17 +169,19 @@ void __init plat_mem_setup(void)
169#define LEDS_PHYS MLEDS_PHYS 169#define LEDS_PHYS MLEDS_PHYS
170#endif 170#endif
171 171
172#define setled(index, c) \
173 ((unsigned char *)(IOADDR(LEDS_PHYS)+0x20))[(3-(index))<<3] = (c)
174void setleds(char *str) 172void setleds(char *str)
175{ 173{
174 void *reg;
176 int i; 175 int i;
176
177 for (i = 0; i < 4; i++) { 177 for (i = 0; i < 4; i++) {
178 if (!str[i]) { 178 reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3);
179 setled(i, ' '); 179
180 } else { 180 if (!str[i])
181 setled(i, str[i]); 181 writeb(' ', reg);
182 } 182 else
183 writeb(str[i], reg);
183 } 184 }
184} 185}
185#endif 186
187#endif /* LEDS_PHYS */