diff options
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/include/asm/mach-pnx833x/gpio.h | 2 | ||||
-rw-r--r-- | arch/mips/include/asm/sgi/ioc.h | 2 | ||||
-rw-r--r-- | arch/mips/include/asm/sibyte/sb1250_mac.h | 2 | ||||
-rw-r--r-- | arch/mips/include/asm/sn/sn0/hubio.h | 2 | ||||
-rw-r--r-- | arch/mips/kernel/smtc.c | 2 | ||||
-rw-r--r-- | arch/mips/math-emu/dp_sub.c | 2 | ||||
-rw-r--r-- | arch/mips/txx9/generic/smsc_fdc37m81x.c | 2 |
7 files changed, 7 insertions, 7 deletions
diff --git a/arch/mips/include/asm/mach-pnx833x/gpio.h b/arch/mips/include/asm/mach-pnx833x/gpio.h index 8de0eb9c98a3..ed3a88da70f6 100644 --- a/arch/mips/include/asm/mach-pnx833x/gpio.h +++ b/arch/mips/include/asm/mach-pnx833x/gpio.h | |||
@@ -24,7 +24,7 @@ | |||
24 | 24 | ||
25 | /* BIG FAT WARNING: races danger! | 25 | /* BIG FAT WARNING: races danger! |
26 | No protections exist here. Current users are only early init code, | 26 | No protections exist here. Current users are only early init code, |
27 | when locking is not needed because no cuncurency yet exists there, | 27 | when locking is not needed because no concurrency yet exists there, |
28 | and GPIO IRQ dispatcher, which does locking. | 28 | and GPIO IRQ dispatcher, which does locking. |
29 | However, if many uses will ever happen, proper locking will be needed | 29 | However, if many uses will ever happen, proper locking will be needed |
30 | - including locking between different uses | 30 | - including locking between different uses |
diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h index 343ed15f8dc4..57a971904cfe 100644 --- a/arch/mips/include/asm/sgi/ioc.h +++ b/arch/mips/include/asm/sgi/ioc.h | |||
@@ -164,7 +164,7 @@ struct sgioc_regs { | |||
164 | u32 _unused5; | 164 | u32 _unused5; |
165 | u8 _write[3]; | 165 | u8 _write[3]; |
166 | volatile u8 write; | 166 | volatile u8 write; |
167 | #define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshhold */ | 167 | #define SGIOC_WRITE_NTHRESH 0x01 /* use 4.5db threshold */ |
168 | #define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */ | 168 | #define SGIOC_WRITE_TPSPEED 0x02 /* use 100ohm TP speed */ |
169 | #define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */ | 169 | #define SGIOC_WRITE_EPSEL 0x04 /* force cable mode: 1=AUI 0=TP */ |
170 | #define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */ | 170 | #define SGIOC_WRITE_EASEL 0x08 /* 1=autoselect 0=manual cable selection */ |
diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h index b6faf08ca81d..591b9061fd8e 100644 --- a/arch/mips/include/asm/sibyte/sb1250_mac.h +++ b/arch/mips/include/asm/sibyte/sb1250_mac.h | |||
@@ -212,7 +212,7 @@ | |||
212 | #define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) | 212 | #define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) |
213 | 213 | ||
214 | /* | 214 | /* |
215 | * MAC Fifo Threshhold registers (Table 9-14) | 215 | * MAC Fifo Threshold registers (Table 9-14) |
216 | * Register: MAC_THRSH_CFG_0 | 216 | * Register: MAC_THRSH_CFG_0 |
217 | * Register: MAC_THRSH_CFG_1 | 217 | * Register: MAC_THRSH_CFG_1 |
218 | * Register: MAC_THRSH_CFG_2 | 218 | * Register: MAC_THRSH_CFG_2 |
diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h index d0c29d4de084..31c76c021bb6 100644 --- a/arch/mips/include/asm/sn/sn0/hubio.h +++ b/arch/mips/include/asm/sn/sn0/hubio.h | |||
@@ -825,7 +825,7 @@ typedef union iprb_u { | |||
825 | struct { | 825 | struct { |
826 | u64 rsvd1: 15, | 826 | u64 rsvd1: 15, |
827 | error: 1, /* Widget rcvd wr resp pkt w/ error */ | 827 | error: 1, /* Widget rcvd wr resp pkt w/ error */ |
828 | ovflow: 5, /* Over flow count. perf measurement */ | 828 | ovflow: 5, /* Overflow count. perf measurement */ |
829 | fire_and_forget: 1, /* Launch Write without response */ | 829 | fire_and_forget: 1, /* Launch Write without response */ |
830 | mode: 2, /* Widget operation Mode */ | 830 | mode: 2, /* Widget operation Mode */ |
831 | rsvd2: 2, | 831 | rsvd2: 2, |
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 24630fd8ef60..a38e3ee95515 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c | |||
@@ -1331,7 +1331,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) | |||
1331 | if (!((asid += ASID_INC) & ASID_MASK) ) { | 1331 | if (!((asid += ASID_INC) & ASID_MASK) ) { |
1332 | if (cpu_has_vtag_icache) | 1332 | if (cpu_has_vtag_icache) |
1333 | flush_icache_all(); | 1333 | flush_icache_all(); |
1334 | /* Traverse all online CPUs (hack requires contigous range) */ | 1334 | /* Traverse all online CPUs (hack requires contiguous range) */ |
1335 | for_each_online_cpu(i) { | 1335 | for_each_online_cpu(i) { |
1336 | /* | 1336 | /* |
1337 | * We don't need to worry about our own CPU, nor those of | 1337 | * We don't need to worry about our own CPU, nor those of |
diff --git a/arch/mips/math-emu/dp_sub.c b/arch/mips/math-emu/dp_sub.c index b30c5b1f1a2c..a2127d685a0d 100644 --- a/arch/mips/math-emu/dp_sub.c +++ b/arch/mips/math-emu/dp_sub.c | |||
@@ -110,7 +110,7 @@ ieee754dp ieee754dp_sub(ieee754dp x, ieee754dp y) | |||
110 | 110 | ||
111 | case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): | 111 | case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): |
112 | DPDNORMX; | 112 | DPDNORMX; |
113 | /* FAAL THOROUGH */ | 113 | /* FALL THROUGH */ |
114 | 114 | ||
115 | case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): | 115 | case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): |
116 | /* normalize ym,ye */ | 116 | /* normalize ym,ye */ |
diff --git a/arch/mips/txx9/generic/smsc_fdc37m81x.c b/arch/mips/txx9/generic/smsc_fdc37m81x.c index a2b2d62d88e3..8ebc3848f3ac 100644 --- a/arch/mips/txx9/generic/smsc_fdc37m81x.c +++ b/arch/mips/txx9/generic/smsc_fdc37m81x.c | |||
@@ -117,7 +117,7 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port) | |||
117 | if (chip_id == SMSC_FDC37M81X_CHIP_ID) | 117 | if (chip_id == SMSC_FDC37M81X_CHIP_ID) |
118 | smsc_fdc37m81x_config_end(); | 118 | smsc_fdc37m81x_config_end(); |
119 | else { | 119 | else { |
120 | printk(KERN_WARNING "%s: unknow chip id 0x%02x\n", __func__, | 120 | printk(KERN_WARNING "%s: unknown chip id 0x%02x\n", __func__, |
121 | chip_id); | 121 | chip_id); |
122 | g_smsc_fdc37m81x_base = 0; | 122 | g_smsc_fdc37m81x_base = 0; |
123 | } | 123 | } |