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-rw-r--r--arch/mips/math-emu/cp1emu.c35
-rw-r--r--arch/mips/math-emu/dp_add.c4
-rw-r--r--arch/mips/math-emu/dp_sqrt.c8
-rw-r--r--arch/mips/math-emu/dp_sub.c4
-rw-r--r--arch/mips/math-emu/dp_tint.c8
-rw-r--r--arch/mips/math-emu/dp_tlong.c8
-rw-r--r--arch/mips/math-emu/ieee754.h7
-rw-r--r--arch/mips/math-emu/ieee754dp.c24
-rw-r--r--arch/mips/math-emu/ieee754sp.c24
-rw-r--r--arch/mips/math-emu/sp_add.c4
-rw-r--r--arch/mips/math-emu/sp_fdp.c4
-rw-r--r--arch/mips/math-emu/sp_sqrt.c4
-rw-r--r--arch/mips/math-emu/sp_sub.c4
-rw-r--r--arch/mips/math-emu/sp_tint.c8
-rw-r--r--arch/mips/math-emu/sp_tlong.c8
15 files changed, 63 insertions, 91 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index b31ce6cdb6b9..03e233223af7 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -67,21 +67,6 @@ static int fpux_emu(struct pt_regs *,
67/* Determine rounding mode from the RM bits of the FCSR */ 67/* Determine rounding mode from the RM bits of the FCSR */
68#define modeindex(v) ((v) & FPU_CSR_RM) 68#define modeindex(v) ((v) & FPU_CSR_RM)
69 69
70/* Convert MIPS rounding mode (0..3) to IEEE library modes. */
71static const unsigned char ieee_rm[4] = {
72 [FPU_CSR_RN] = IEEE754_RN,
73 [FPU_CSR_RZ] = IEEE754_RZ,
74 [FPU_CSR_RU] = IEEE754_RU,
75 [FPU_CSR_RD] = IEEE754_RD,
76};
77/* Convert IEEE library modes to MIPS rounding mode (0..3). */
78static const unsigned char mips_rm[4] = {
79 [IEEE754_RN] = FPU_CSR_RN,
80 [IEEE754_RZ] = FPU_CSR_RZ,
81 [IEEE754_RD] = FPU_CSR_RD,
82 [IEEE754_RU] = FPU_CSR_RU,
83};
84
85/* convert condition code register number to csr bit */ 70/* convert condition code register number to csr bit */
86static const unsigned int fpucondbit[8] = { 71static const unsigned int fpucondbit[8] = {
87 FPU_CSR_COND0, 72 FPU_CSR_COND0,
@@ -907,8 +892,7 @@ emul:
907 /* cop control register rd -> gpr[rt] */ 892 /* cop control register rd -> gpr[rt] */
908 if (MIPSInst_RD(ir) == FPCREG_CSR) { 893 if (MIPSInst_RD(ir) == FPCREG_CSR) {
909 value = ctx->fcr31; 894 value = ctx->fcr31;
910 value = (value & ~FPU_CSR_RM) | 895 value = (value & ~FPU_CSR_RM) | modeindex(value);
911 mips_rm[modeindex(value)];
912 pr_debug("%p gpr[%d]<-csr=%08x\n", 896 pr_debug("%p gpr[%d]<-csr=%08x\n",
913 (void *) (xcp->cp0_epc), 897 (void *) (xcp->cp0_epc),
914 MIPSInst_RT(ir), value); 898 MIPSInst_RT(ir), value);
@@ -939,9 +923,8 @@ emul:
939 * Don't write reserved bits, 923 * Don't write reserved bits,
940 * and convert to ieee library modes 924 * and convert to ieee library modes
941 */ 925 */
942 ctx->fcr31 = (value & 926 ctx->fcr31 = (value & ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
943 ~(FPU_CSR_RSVD | FPU_CSR_RM)) | 927 modeindex(value);
944 ieee_rm[modeindex(value)];
945 } 928 }
946 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { 929 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
947 return SIGFPE; 930 return SIGFPE;
@@ -1515,7 +1498,7 @@ copcsr:
1515 1498
1516 oldrm = ieee754_csr.rm; 1499 oldrm = ieee754_csr.rm;
1517 SPFROMREG(fs, MIPSInst_FS(ir)); 1500 SPFROMREG(fs, MIPSInst_FS(ir));
1518 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1501 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1519 rv.w = ieee754sp_tint(fs); 1502 rv.w = ieee754sp_tint(fs);
1520 ieee754_csr.rm = oldrm; 1503 ieee754_csr.rm = oldrm;
1521 rfmt = w_fmt; 1504 rfmt = w_fmt;
@@ -1539,7 +1522,7 @@ copcsr:
1539 1522
1540 oldrm = ieee754_csr.rm; 1523 oldrm = ieee754_csr.rm;
1541 SPFROMREG(fs, MIPSInst_FS(ir)); 1524 SPFROMREG(fs, MIPSInst_FS(ir));
1542 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1525 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1543 rv.l = ieee754sp_tlong(fs); 1526 rv.l = ieee754sp_tlong(fs);
1544 ieee754_csr.rm = oldrm; 1527 ieee754_csr.rm = oldrm;
1545 rfmt = l_fmt; 1528 rfmt = l_fmt;
@@ -1692,7 +1675,7 @@ dcopuop:
1692 1675
1693 oldrm = ieee754_csr.rm; 1676 oldrm = ieee754_csr.rm;
1694 DPFROMREG(fs, MIPSInst_FS(ir)); 1677 DPFROMREG(fs, MIPSInst_FS(ir));
1695 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1678 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1696 rv.w = ieee754dp_tint(fs); 1679 rv.w = ieee754dp_tint(fs);
1697 ieee754_csr.rm = oldrm; 1680 ieee754_csr.rm = oldrm;
1698 rfmt = w_fmt; 1681 rfmt = w_fmt;
@@ -1716,7 +1699,7 @@ dcopuop:
1716 1699
1717 oldrm = ieee754_csr.rm; 1700 oldrm = ieee754_csr.rm;
1718 DPFROMREG(fs, MIPSInst_FS(ir)); 1701 DPFROMREG(fs, MIPSInst_FS(ir));
1719 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; 1702 ieee754_csr.rm = modeindex(MIPSInst_FUNC(ir));
1720 rv.l = ieee754dp_tlong(fs); 1703 rv.l = ieee754dp_tlong(fs);
1721 ieee754_csr.rm = oldrm; 1704 ieee754_csr.rm = oldrm;
1722 rfmt = l_fmt; 1705 rfmt = l_fmt;
@@ -1926,11 +1909,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1926 * ieee754_csr. But ieee754_csr.rm is ieee 1909 * ieee754_csr. But ieee754_csr.rm is ieee
1927 * library modes. (not mips rounding mode) 1910 * library modes. (not mips rounding mode)
1928 */ 1911 */
1929 /* convert to ieee library modes */
1930 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
1931 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); 1912 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
1932 /* revert to mips rounding mode */
1933 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1934 } 1913 }
1935 1914
1936 if (has_fpu) 1915 if (has_fpu)
diff --git a/arch/mips/math-emu/dp_add.c b/arch/mips/math-emu/dp_add.c
index 9c98b96f7287..7f64577df984 100644
--- a/arch/mips/math-emu/dp_add.c
+++ b/arch/mips/math-emu/dp_add.c
@@ -91,7 +91,7 @@ union ieee754dp ieee754dp_add(union ieee754dp x, union ieee754dp y)
91 if (xs == ys) 91 if (xs == ys)
92 return x; 92 return x;
93 else 93 else
94 return ieee754dp_zero(ieee754_csr.rm == IEEE754_RD); 94 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
95 95
96 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): 96 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
97 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): 97 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
@@ -168,7 +168,7 @@ union ieee754dp ieee754dp_add(union ieee754dp x, union ieee754dp y)
168 xs = ys; 168 xs = ys;
169 } 169 }
170 if (xm == 0) 170 if (xm == 0)
171 return ieee754dp_zero(ieee754_csr.rm == IEEE754_RD); 171 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
172 172
173 /* 173 /*
174 * Normalize to rounding precision. 174 * Normalize to rounding precision.
diff --git a/arch/mips/math-emu/dp_sqrt.c b/arch/mips/math-emu/dp_sqrt.c
index 0384c094b1aa..041bbb6124bb 100644
--- a/arch/mips/math-emu/dp_sqrt.c
+++ b/arch/mips/math-emu/dp_sqrt.c
@@ -80,7 +80,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x)
80 oldcsr = ieee754_csr; 80 oldcsr = ieee754_csr;
81 ieee754_csr.mx &= ~IEEE754_INEXACT; 81 ieee754_csr.mx &= ~IEEE754_INEXACT;
82 ieee754_csr.sx &= ~IEEE754_INEXACT; 82 ieee754_csr.sx &= ~IEEE754_INEXACT;
83 ieee754_csr.rm = IEEE754_RN; 83 ieee754_csr.rm = FPU_CSR_RN;
84 84
85 /* adjust exponent to prevent overflow */ 85 /* adjust exponent to prevent overflow */
86 scalx = 0; 86 scalx = 0;
@@ -122,7 +122,7 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x)
122 /* twiddle last bit to force y correctly rounded */ 122 /* twiddle last bit to force y correctly rounded */
123 123
124 /* set RZ, clear INEX flag */ 124 /* set RZ, clear INEX flag */
125 ieee754_csr.rm = IEEE754_RZ; 125 ieee754_csr.rm = FPU_CSR_RZ;
126 ieee754_csr.sx &= ~IEEE754_INEXACT; 126 ieee754_csr.sx &= ~IEEE754_INEXACT;
127 127
128 /* t=x/y; ...chopped quotient, possibly inexact */ 128 /* t=x/y; ...chopped quotient, possibly inexact */
@@ -139,10 +139,10 @@ union ieee754dp ieee754dp_sqrt(union ieee754dp x)
139 oldcsr.sx |= IEEE754_INEXACT; 139 oldcsr.sx |= IEEE754_INEXACT;
140 140
141 switch (oldcsr.rm) { 141 switch (oldcsr.rm) {
142 case IEEE754_RU: 142 case FPU_CSR_RU:
143 y.bits += 1; 143 y.bits += 1;
144 /* drop through */ 144 /* drop through */
145 case IEEE754_RN: 145 case FPU_CSR_RN:
146 t.bits += 1; 146 t.bits += 1;
147 break; 147 break;
148 } 148 }
diff --git a/arch/mips/math-emu/dp_sub.c b/arch/mips/math-emu/dp_sub.c
index d502984df7cc..7a174029043a 100644
--- a/arch/mips/math-emu/dp_sub.c
+++ b/arch/mips/math-emu/dp_sub.c
@@ -91,7 +91,7 @@ union ieee754dp ieee754dp_sub(union ieee754dp x, union ieee754dp y)
91 if (xs != ys) 91 if (xs != ys)
92 return x; 92 return x;
93 else 93 else
94 return ieee754dp_zero(ieee754_csr.rm == IEEE754_RD); 94 return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
95 95
96 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): 96 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
97 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): 97 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
@@ -171,7 +171,7 @@ union ieee754dp ieee754dp_sub(union ieee754dp x, union ieee754dp y)
171 xs = ys; 171 xs = ys;
172 } 172 }
173 if (xm == 0) { 173 if (xm == 0) {
174 if (ieee754_csr.rm == IEEE754_RD) 174 if (ieee754_csr.rm == FPU_CSR_RD)
175 return ieee754dp_zero(1); /* round negative inf. => sign = -1 */ 175 return ieee754dp_zero(1); /* round negative inf. => sign = -1 */
176 else 176 else
177 return ieee754dp_zero(0); /* other round modes => sign = 1 */ 177 return ieee754dp_zero(0); /* other round modes => sign = 1 */
diff --git a/arch/mips/math-emu/dp_tint.c b/arch/mips/math-emu/dp_tint.c
index 972dba0baca0..6ffc336c530e 100644
--- a/arch/mips/math-emu/dp_tint.c
+++ b/arch/mips/math-emu/dp_tint.c
@@ -74,17 +74,17 @@ int ieee754dp_tint(union ieee754dp x)
74 to be zero */ 74 to be zero */
75 odd = (xm & 0x1) != 0x0; 75 odd = (xm & 0x1) != 0x0;
76 switch (ieee754_csr.rm) { 76 switch (ieee754_csr.rm) {
77 case IEEE754_RN: 77 case FPU_CSR_RN:
78 if (round && (sticky || odd)) 78 if (round && (sticky || odd))
79 xm++; 79 xm++;
80 break; 80 break;
81 case IEEE754_RZ: 81 case FPU_CSR_RZ:
82 break; 82 break;
83 case IEEE754_RU: /* toward +Infinity */ 83 case FPU_CSR_RU: /* toward +Infinity */
84 if ((round || sticky) && !xs) 84 if ((round || sticky) && !xs)
85 xm++; 85 xm++;
86 break; 86 break;
87 case IEEE754_RD: /* toward -Infinity */ 87 case FPU_CSR_RD: /* toward -Infinity */
88 if ((round || sticky) && xs) 88 if ((round || sticky) && xs)
89 xm++; 89 xm++;
90 break; 90 break;
diff --git a/arch/mips/math-emu/dp_tlong.c b/arch/mips/math-emu/dp_tlong.c
index afaf953e576d..9cdc145b75e0 100644
--- a/arch/mips/math-emu/dp_tlong.c
+++ b/arch/mips/math-emu/dp_tlong.c
@@ -79,17 +79,17 @@ s64 ieee754dp_tlong(union ieee754dp x)
79 } 79 }
80 odd = (xm & 0x1) != 0x0; 80 odd = (xm & 0x1) != 0x0;
81 switch (ieee754_csr.rm) { 81 switch (ieee754_csr.rm) {
82 case IEEE754_RN: 82 case FPU_CSR_RN:
83 if (round && (sticky || odd)) 83 if (round && (sticky || odd))
84 xm++; 84 xm++;
85 break; 85 break;
86 case IEEE754_RZ: 86 case FPU_CSR_RZ:
87 break; 87 break;
88 case IEEE754_RU: /* toward +Infinity */ 88 case FPU_CSR_RU: /* toward +Infinity */
89 if ((round || sticky) && !xs) 89 if ((round || sticky) && !xs)
90 xm++; 90 xm++;
91 break; 91 break;
92 case IEEE754_RD: /* toward -Infinity */ 92 case FPU_CSR_RD: /* toward -Infinity */
93 if ((round || sticky) && xs) 93 if ((round || sticky) && xs)
94 xm++; 94 xm++;
95 break; 95 break;
diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h
index 2fa939c612f6..43c4fb522ac2 100644
--- a/arch/mips/math-emu/ieee754.h
+++ b/arch/mips/math-emu/ieee754.h
@@ -126,13 +126,6 @@ enum {
126#define IEEE754_CGT 0x04 126#define IEEE754_CGT 0x04
127#define IEEE754_CUN 0x08 127#define IEEE754_CUN 0x08
128 128
129/* rounding mode
130*/
131#define IEEE754_RN 0 /* round to nearest */
132#define IEEE754_RZ 1 /* round toward zero */
133#define IEEE754_RD 2 /* round toward -Infinity */
134#define IEEE754_RU 3 /* round toward +Infinity */
135
136/* "normal" comparisons 129/* "normal" comparisons
137*/ 130*/
138static inline int ieee754sp_eq(union ieee754sp x, union ieee754sp y) 131static inline int ieee754sp_eq(union ieee754sp x, union ieee754sp y)
diff --git a/arch/mips/math-emu/ieee754dp.c b/arch/mips/math-emu/ieee754dp.c
index 087a6f38b149..fd134675fc2e 100644
--- a/arch/mips/math-emu/ieee754dp.c
+++ b/arch/mips/math-emu/ieee754dp.c
@@ -67,17 +67,17 @@ static u64 ieee754dp_get_rounding(int sn, u64 xm)
67 */ 67 */
68 if (xm & (DP_MBIT(3) - 1)) { 68 if (xm & (DP_MBIT(3) - 1)) {
69 switch (ieee754_csr.rm) { 69 switch (ieee754_csr.rm) {
70 case IEEE754_RZ: 70 case FPU_CSR_RZ:
71 break; 71 break;
72 case IEEE754_RN: 72 case FPU_CSR_RN:
73 xm += 0x3 + ((xm >> 3) & 1); 73 xm += 0x3 + ((xm >> 3) & 1);
74 /* xm += (xm&0x8)?0x4:0x3 */ 74 /* xm += (xm&0x8)?0x4:0x3 */
75 break; 75 break;
76 case IEEE754_RU: /* toward +Infinity */ 76 case FPU_CSR_RU: /* toward +Infinity */
77 if (!sn) /* ?? */ 77 if (!sn) /* ?? */
78 xm += 0x8; 78 xm += 0x8;
79 break; 79 break;
80 case IEEE754_RD: /* toward -Infinity */ 80 case FPU_CSR_RD: /* toward -Infinity */
81 if (sn) /* ?? */ 81 if (sn) /* ?? */
82 xm += 0x8; 82 xm += 0x8;
83 break; 83 break;
@@ -108,15 +108,15 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
108 ieee754_setcx(IEEE754_INEXACT); 108 ieee754_setcx(IEEE754_INEXACT);
109 109
110 switch(ieee754_csr.rm) { 110 switch(ieee754_csr.rm) {
111 case IEEE754_RN: 111 case FPU_CSR_RN:
112 case IEEE754_RZ: 112 case FPU_CSR_RZ:
113 return ieee754dp_zero(sn); 113 return ieee754dp_zero(sn);
114 case IEEE754_RU: /* toward +Infinity */ 114 case FPU_CSR_RU: /* toward +Infinity */
115 if (sn == 0) 115 if (sn == 0)
116 return ieee754dp_min(0); 116 return ieee754dp_min(0);
117 else 117 else
118 return ieee754dp_zero(1); 118 return ieee754dp_zero(1);
119 case IEEE754_RD: /* toward -Infinity */ 119 case FPU_CSR_RD: /* toward -Infinity */
120 if (sn == 0) 120 if (sn == 0)
121 return ieee754dp_zero(0); 121 return ieee754dp_zero(0);
122 else 122 else
@@ -172,16 +172,16 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
172 ieee754_setcx(IEEE754_INEXACT); 172 ieee754_setcx(IEEE754_INEXACT);
173 /* -O can be table indexed by (rm,sn) */ 173 /* -O can be table indexed by (rm,sn) */
174 switch (ieee754_csr.rm) { 174 switch (ieee754_csr.rm) {
175 case IEEE754_RN: 175 case FPU_CSR_RN:
176 return ieee754dp_inf(sn); 176 return ieee754dp_inf(sn);
177 case IEEE754_RZ: 177 case FPU_CSR_RZ:
178 return ieee754dp_max(sn); 178 return ieee754dp_max(sn);
179 case IEEE754_RU: /* toward +Infinity */ 179 case FPU_CSR_RU: /* toward +Infinity */
180 if (sn == 0) 180 if (sn == 0)
181 return ieee754dp_inf(0); 181 return ieee754dp_inf(0);
182 else 182 else
183 return ieee754dp_max(1); 183 return ieee754dp_max(1);
184 case IEEE754_RD: /* toward -Infinity */ 184 case FPU_CSR_RD: /* toward -Infinity */
185 if (sn == 0) 185 if (sn == 0)
186 return ieee754dp_max(0); 186 return ieee754dp_max(0);
187 else 187 else
diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c
index e4cec15845b9..d348efe91445 100644
--- a/arch/mips/math-emu/ieee754sp.c
+++ b/arch/mips/math-emu/ieee754sp.c
@@ -67,17 +67,17 @@ static unsigned ieee754sp_get_rounding(int sn, unsigned xm)
67 */ 67 */
68 if (xm & (SP_MBIT(3) - 1)) { 68 if (xm & (SP_MBIT(3) - 1)) {
69 switch (ieee754_csr.rm) { 69 switch (ieee754_csr.rm) {
70 case IEEE754_RZ: 70 case FPU_CSR_RZ:
71 break; 71 break;
72 case IEEE754_RN: 72 case FPU_CSR_RN:
73 xm += 0x3 + ((xm >> 3) & 1); 73 xm += 0x3 + ((xm >> 3) & 1);
74 /* xm += (xm&0x8)?0x4:0x3 */ 74 /* xm += (xm&0x8)?0x4:0x3 */
75 break; 75 break;
76 case IEEE754_RU: /* toward +Infinity */ 76 case FPU_CSR_RU: /* toward +Infinity */
77 if (!sn) /* ?? */ 77 if (!sn) /* ?? */
78 xm += 0x8; 78 xm += 0x8;
79 break; 79 break;
80 case IEEE754_RD: /* toward -Infinity */ 80 case FPU_CSR_RD: /* toward -Infinity */
81 if (sn) /* ?? */ 81 if (sn) /* ?? */
82 xm += 0x8; 82 xm += 0x8;
83 break; 83 break;
@@ -108,15 +108,15 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
108 ieee754_setcx(IEEE754_INEXACT); 108 ieee754_setcx(IEEE754_INEXACT);
109 109
110 switch(ieee754_csr.rm) { 110 switch(ieee754_csr.rm) {
111 case IEEE754_RN: 111 case FPU_CSR_RN:
112 case IEEE754_RZ: 112 case FPU_CSR_RZ:
113 return ieee754sp_zero(sn); 113 return ieee754sp_zero(sn);
114 case IEEE754_RU: /* toward +Infinity */ 114 case FPU_CSR_RU: /* toward +Infinity */
115 if (sn == 0) 115 if (sn == 0)
116 return ieee754sp_min(0); 116 return ieee754sp_min(0);
117 else 117 else
118 return ieee754sp_zero(1); 118 return ieee754sp_zero(1);
119 case IEEE754_RD: /* toward -Infinity */ 119 case FPU_CSR_RD: /* toward -Infinity */
120 if (sn == 0) 120 if (sn == 0)
121 return ieee754sp_zero(0); 121 return ieee754sp_zero(0);
122 else 122 else
@@ -170,16 +170,16 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
170 ieee754_setcx(IEEE754_INEXACT); 170 ieee754_setcx(IEEE754_INEXACT);
171 /* -O can be table indexed by (rm,sn) */ 171 /* -O can be table indexed by (rm,sn) */
172 switch (ieee754_csr.rm) { 172 switch (ieee754_csr.rm) {
173 case IEEE754_RN: 173 case FPU_CSR_RN:
174 return ieee754sp_inf(sn); 174 return ieee754sp_inf(sn);
175 case IEEE754_RZ: 175 case FPU_CSR_RZ:
176 return ieee754sp_max(sn); 176 return ieee754sp_max(sn);
177 case IEEE754_RU: /* toward +Infinity */ 177 case FPU_CSR_RU: /* toward +Infinity */
178 if (sn == 0) 178 if (sn == 0)
179 return ieee754sp_inf(0); 179 return ieee754sp_inf(0);
180 else 180 else
181 return ieee754sp_max(1); 181 return ieee754sp_max(1);
182 case IEEE754_RD: /* toward -Infinity */ 182 case FPU_CSR_RD: /* toward -Infinity */
183 if (sn == 0) 183 if (sn == 0)
184 return ieee754sp_max(0); 184 return ieee754sp_max(0);
185 else 185 else
diff --git a/arch/mips/math-emu/sp_add.c b/arch/mips/math-emu/sp_add.c
index a0bc95cea1cc..2d84d460cb67 100644
--- a/arch/mips/math-emu/sp_add.c
+++ b/arch/mips/math-emu/sp_add.c
@@ -91,7 +91,7 @@ union ieee754sp ieee754sp_add(union ieee754sp x, union ieee754sp y)
91 if (xs == ys) 91 if (xs == ys)
92 return x; 92 return x;
93 else 93 else
94 return ieee754sp_zero(ieee754_csr.rm == IEEE754_RD); 94 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
95 95
96 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): 96 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
97 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): 97 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
@@ -165,7 +165,7 @@ union ieee754sp ieee754sp_add(union ieee754sp x, union ieee754sp y)
165 xs = ys; 165 xs = ys;
166 } 166 }
167 if (xm == 0) 167 if (xm == 0)
168 return ieee754sp_zero(ieee754_csr.rm == IEEE754_RD); 168 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
169 169
170 /* 170 /*
171 * Normalize in extended single precision 171 * Normalize in extended single precision
diff --git a/arch/mips/math-emu/sp_fdp.c b/arch/mips/math-emu/sp_fdp.c
index 90b9ec45e984..1b266fb16973 100644
--- a/arch/mips/math-emu/sp_fdp.c
+++ b/arch/mips/math-emu/sp_fdp.c
@@ -57,8 +57,8 @@ union ieee754sp ieee754sp_fdp(union ieee754dp x)
57 /* can't possibly be sp representable */ 57 /* can't possibly be sp representable */
58 ieee754_setcx(IEEE754_UNDERFLOW); 58 ieee754_setcx(IEEE754_UNDERFLOW);
59 ieee754_setcx(IEEE754_INEXACT); 59 ieee754_setcx(IEEE754_INEXACT);
60 if ((ieee754_csr.rm == IEEE754_RU && !xs) || 60 if ((ieee754_csr.rm == FPU_CSR_RU && !xs) ||
61 (ieee754_csr.rm == IEEE754_RD && xs)) 61 (ieee754_csr.rm == FPU_CSR_RD && xs))
62 return ieee754sp_mind(xs); 62 return ieee754sp_mind(xs);
63 return ieee754sp_zero(xs); 63 return ieee754sp_zero(xs);
64 64
diff --git a/arch/mips/math-emu/sp_sqrt.c b/arch/mips/math-emu/sp_sqrt.c
index 94f5befa1d70..b7c098a86f95 100644
--- a/arch/mips/math-emu/sp_sqrt.c
+++ b/arch/mips/math-emu/sp_sqrt.c
@@ -100,10 +100,10 @@ union ieee754sp ieee754sp_sqrt(union ieee754sp x)
100 if (ix != 0) { 100 if (ix != 0) {
101 ieee754_setcx(IEEE754_INEXACT); 101 ieee754_setcx(IEEE754_INEXACT);
102 switch (ieee754_csr.rm) { 102 switch (ieee754_csr.rm) {
103 case IEEE754_RU: 103 case FPU_CSR_RU:
104 q += 2; 104 q += 2;
105 break; 105 break;
106 case IEEE754_RN: 106 case FPU_CSR_RN:
107 q += (q & 1); 107 q += (q & 1);
108 break; 108 break;
109 } 109 }
diff --git a/arch/mips/math-emu/sp_sub.c b/arch/mips/math-emu/sp_sub.c
index e813f4fee784..8592e49032b8 100644
--- a/arch/mips/math-emu/sp_sub.c
+++ b/arch/mips/math-emu/sp_sub.c
@@ -91,7 +91,7 @@ union ieee754sp ieee754sp_sub(union ieee754sp x, union ieee754sp y)
91 if (xs != ys) 91 if (xs != ys)
92 return x; 92 return x;
93 else 93 else
94 return ieee754sp_zero(ieee754_csr.rm == IEEE754_RD); 94 return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
95 95
96 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): 96 case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
97 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): 97 case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
@@ -165,7 +165,7 @@ union ieee754sp ieee754sp_sub(union ieee754sp x, union ieee754sp y)
165 xs = ys; 165 xs = ys;
166 } 166 }
167 if (xm == 0) { 167 if (xm == 0) {
168 if (ieee754_csr.rm == IEEE754_RD) 168 if (ieee754_csr.rm == FPU_CSR_RD)
169 return ieee754sp_zero(1); /* round negative inf. => sign = -1 */ 169 return ieee754sp_zero(1); /* round negative inf. => sign = -1 */
170 else 170 else
171 return ieee754sp_zero(0); /* other round modes => sign = 1 */ 171 return ieee754sp_zero(0); /* other round modes => sign = 1 */
diff --git a/arch/mips/math-emu/sp_tint.c b/arch/mips/math-emu/sp_tint.c
index e1dee56ebc54..091299a31798 100644
--- a/arch/mips/math-emu/sp_tint.c
+++ b/arch/mips/math-emu/sp_tint.c
@@ -79,17 +79,17 @@ int ieee754sp_tint(union ieee754sp x)
79 } 79 }
80 odd = (xm & 0x1) != 0x0; 80 odd = (xm & 0x1) != 0x0;
81 switch (ieee754_csr.rm) { 81 switch (ieee754_csr.rm) {
82 case IEEE754_RN: 82 case FPU_CSR_RN:
83 if (round && (sticky || odd)) 83 if (round && (sticky || odd))
84 xm++; 84 xm++;
85 break; 85 break;
86 case IEEE754_RZ: 86 case FPU_CSR_RZ:
87 break; 87 break;
88 case IEEE754_RU: /* toward +Infinity */ 88 case FPU_CSR_RU: /* toward +Infinity */
89 if ((round || sticky) && !xs) 89 if ((round || sticky) && !xs)
90 xm++; 90 xm++;
91 break; 91 break;
92 case IEEE754_RD: /* toward -Infinity */ 92 case FPU_CSR_RD: /* toward -Infinity */
93 if ((round || sticky) && xs) 93 if ((round || sticky) && xs)
94 xm++; 94 xm++;
95 break; 95 break;
diff --git a/arch/mips/math-emu/sp_tlong.c b/arch/mips/math-emu/sp_tlong.c
index 67eff6ba9e18..9f3c742c1cea 100644
--- a/arch/mips/math-emu/sp_tlong.c
+++ b/arch/mips/math-emu/sp_tlong.c
@@ -76,17 +76,17 @@ s64 ieee754sp_tlong(union ieee754sp x)
76 } 76 }
77 odd = (xm & 0x1) != 0x0; 77 odd = (xm & 0x1) != 0x0;
78 switch (ieee754_csr.rm) { 78 switch (ieee754_csr.rm) {
79 case IEEE754_RN: 79 case FPU_CSR_RN:
80 if (round && (sticky || odd)) 80 if (round && (sticky || odd))
81 xm++; 81 xm++;
82 break; 82 break;
83 case IEEE754_RZ: 83 case FPU_CSR_RZ:
84 break; 84 break;
85 case IEEE754_RU: /* toward +Infinity */ 85 case FPU_CSR_RU: /* toward +Infinity */
86 if ((round || sticky) && !xs) 86 if ((round || sticky) && !xs)
87 xm++; 87 xm++;
88 break; 88 break;
89 case IEEE754_RD: /* toward -Infinity */ 89 case FPU_CSR_RD: /* toward -Infinity */
90 if ((round || sticky) && xs) 90 if ((round || sticky) && xs)
91 xm++; 91 xm++;
92 break; 92 break;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 00:49:59 -0500