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-rw-r--r--arch/mips/Kconfig4
-rw-r--r--arch/mips/lib/Makefile2
-rw-r--r--arch/mips/lib/dec_and_lock.c47
-rw-r--r--arch/mips/pci/fixup-tb0226.c33
4 files changed, 18 insertions, 68 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0eb71ac303af..4cd724c05700 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1009,10 +1009,6 @@ config GENERIC_CALIBRATE_DELAY
1009 bool 1009 bool
1010 default y 1010 default y
1011 1011
1012config HAVE_DEC_LOCK
1013 bool
1014 default y
1015
1016# 1012#
1017# Select some configuration options automatically based on user selections. 1013# Select some configuration options automatically based on user selections.
1018# 1014#
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 21b92b9dd013..037303412909 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -2,7 +2,7 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial_copy.o dec_and_lock.o memcpy.o promlib.o \ 5lib-y += csum_partial_copy.o memcpy.o promlib.o \
6 strlen_user.o strncpy_user.o strnlen_user.o 6 strlen_user.o strncpy_user.o strnlen_user.o
7 7
8obj-y += iomap.o 8obj-y += iomap.o
diff --git a/arch/mips/lib/dec_and_lock.c b/arch/mips/lib/dec_and_lock.c
deleted file mode 100644
index fd82c84a93b7..000000000000
--- a/arch/mips/lib/dec_and_lock.c
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * MIPS version of atomic_dec_and_lock() using cmpxchg
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/module.h>
11#include <linux/spinlock.h>
12#include <asm/atomic.h>
13#include <asm/system.h>
14
15/*
16 * This is an implementation of the notion of "decrement a
17 * reference count, and return locked if it decremented to zero".
18 *
19 * This implementation can be used on any architecture that
20 * has a cmpxchg, and where atomic->value is an int holding
21 * the value of the atomic (i.e. the high bits aren't used
22 * for a lock or anything like that).
23 */
24int _atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock)
25{
26 int counter;
27 int newcount;
28
29 for (;;) {
30 counter = atomic_read(atomic);
31 newcount = counter - 1;
32 if (!newcount)
33 break; /* do it the slow way */
34
35 newcount = cmpxchg(&atomic->counter, counter, newcount);
36 if (newcount == counter)
37 return 0;
38 }
39
40 spin_lock(lock);
41 if (atomic_dec_and_test(atomic))
42 return 1;
43 spin_unlock(lock);
44 return 0;
45}
46
47EXPORT_SYMBOL(_atomic_dec_and_lock);
diff --git a/arch/mips/pci/fixup-tb0226.c b/arch/mips/pci/fixup-tb0226.c
index 61513d5d97da..b5d42b12de10 100644
--- a/arch/mips/pci/fixup-tb0226.c
+++ b/arch/mips/pci/fixup-tb0226.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups. 2 * fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups.
3 * 3 *
4 * Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 4 * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -20,6 +20,7 @@
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/pci.h> 21#include <linux/pci.h>
22 22
23#include <asm/vr41xx/giu.h>
23#include <asm/vr41xx/tb0226.h> 24#include <asm/vr41xx/tb0226.h>
24 25
25int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 26int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
@@ -29,42 +30,42 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
29 switch (slot) { 30 switch (slot) {
30 case 12: 31 case 12:
31 vr41xx_set_irq_trigger(GD82559_1_PIN, 32 vr41xx_set_irq_trigger(GD82559_1_PIN,
32 TRIGGER_LEVEL, 33 IRQ_TRIGGER_LEVEL,
33 SIGNAL_THROUGH); 34 IRQ_SIGNAL_THROUGH);
34 vr41xx_set_irq_level(GD82559_1_PIN, LEVEL_LOW); 35 vr41xx_set_irq_level(GD82559_1_PIN, IRQ_LEVEL_LOW);
35 irq = GD82559_1_IRQ; 36 irq = GD82559_1_IRQ;
36 break; 37 break;
37 case 13: 38 case 13:
38 vr41xx_set_irq_trigger(GD82559_2_PIN, 39 vr41xx_set_irq_trigger(GD82559_2_PIN,
39 TRIGGER_LEVEL, 40 IRQ_TRIGGER_LEVEL,
40 SIGNAL_THROUGH); 41 IRQ_SIGNAL_THROUGH);
41 vr41xx_set_irq_level(GD82559_2_PIN, LEVEL_LOW); 42 vr41xx_set_irq_level(GD82559_2_PIN, IRQ_LEVEL_LOW);
42 irq = GD82559_2_IRQ; 43 irq = GD82559_2_IRQ;
43 break; 44 break;
44 case 14: 45 case 14:
45 switch (pin) { 46 switch (pin) {
46 case 1: 47 case 1:
47 vr41xx_set_irq_trigger(UPD720100_INTA_PIN, 48 vr41xx_set_irq_trigger(UPD720100_INTA_PIN,
48 TRIGGER_LEVEL, 49 IRQ_TRIGGER_LEVEL,
49 SIGNAL_THROUGH); 50 IRQ_SIGNAL_THROUGH);
50 vr41xx_set_irq_level(UPD720100_INTA_PIN, 51 vr41xx_set_irq_level(UPD720100_INTA_PIN,
51 LEVEL_LOW); 52 IRQ_LEVEL_LOW);
52 irq = UPD720100_INTA_IRQ; 53 irq = UPD720100_INTA_IRQ;
53 break; 54 break;
54 case 2: 55 case 2:
55 vr41xx_set_irq_trigger(UPD720100_INTB_PIN, 56 vr41xx_set_irq_trigger(UPD720100_INTB_PIN,
56 TRIGGER_LEVEL, 57 IRQ_TRIGGER_LEVEL,
57 SIGNAL_THROUGH); 58 IRQ_SIGNAL_THROUGH);
58 vr41xx_set_irq_level(UPD720100_INTB_PIN, 59 vr41xx_set_irq_level(UPD720100_INTB_PIN,
59 LEVEL_LOW); 60 IRQ_LEVEL_LOW);
60 irq = UPD720100_INTB_IRQ; 61 irq = UPD720100_INTB_IRQ;
61 break; 62 break;
62 case 3: 63 case 3:
63 vr41xx_set_irq_trigger(UPD720100_INTC_PIN, 64 vr41xx_set_irq_trigger(UPD720100_INTC_PIN,
64 TRIGGER_LEVEL, 65 IRQ_TRIGGER_LEVEL,
65 SIGNAL_THROUGH); 66 IRQ_SIGNAL_THROUGH);
66 vr41xx_set_irq_level(UPD720100_INTC_PIN, 67 vr41xx_set_irq_level(UPD720100_INTC_PIN,
67 LEVEL_LOW); 68 IRQ_LEVEL_LOW);
68 irq = UPD720100_INTC_IRQ; 69 irq = UPD720100_INTC_IRQ;
69 break; 70 break;
70 default: 71 default:
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 09:30:43 -0500