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-rw-r--r--arch/mips/include/asm/processor.h69
1 files changed, 69 insertions, 0 deletions
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 18ee58e39445..0f926aa0cb47 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -118,6 +118,60 @@ union mips_watch_reg_state {
118 struct mips3264_watch_reg_state mips3264; 118 struct mips3264_watch_reg_state mips3264;
119}; 119};
120 120
121#ifdef CONFIG_CPU_CAVIUM_OCTEON
122
123struct octeon_cop2_state {
124 /* DMFC2 rt, 0x0201 */
125 unsigned long cop2_crc_iv;
126 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
127 unsigned long cop2_crc_length;
128 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
129 unsigned long cop2_crc_poly;
130 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
131 unsigned long cop2_llm_dat[2];
132 /* DMFC2 rt, 0x0084 */
133 unsigned long cop2_3des_iv;
134 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
135 unsigned long cop2_3des_key[3];
136 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
137 unsigned long cop2_3des_result;
138 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
139 unsigned long cop2_aes_inp0;
140 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
141 unsigned long cop2_aes_iv[2];
142 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
143 * rt, 0x0107 */
144 unsigned long cop2_aes_key[4];
145 /* DMFC2 rt, 0x0110 */
146 unsigned long cop2_aes_keylen;
147 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
148 unsigned long cop2_aes_result[2];
149 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
150 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
151 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
152 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
153 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
154 unsigned long cop2_hsh_datw[15];
155 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
156 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
157 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
158 unsigned long cop2_hsh_ivw[8];
159 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
160 unsigned long cop2_gfm_mult[2];
161 /* DMFC2 rt, 0x025E - Pass2 */
162 unsigned long cop2_gfm_poly;
163 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
164 unsigned long cop2_gfm_result[2];
165};
166#define INIT_OCTEON_COP2 {0,}
167
168struct octeon_cvmseg_state {
169 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
170 [cpu_dcache_line_size() / sizeof(unsigned long)];
171};
172
173#endif
174
121typedef struct { 175typedef struct {
122 unsigned long seg; 176 unsigned long seg;
123} mm_segment_t; 177} mm_segment_t;
@@ -160,6 +214,10 @@ struct thread_struct {
160 unsigned long trap_no; 214 unsigned long trap_no;
161 unsigned long irix_trampoline; /* Wheee... */ 215 unsigned long irix_trampoline; /* Wheee... */
162 unsigned long irix_oldctx; 216 unsigned long irix_oldctx;
217#ifdef CONFIG_CPU_CAVIUM_OCTEON
218 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
219 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
220#endif
163 struct mips_abi *abi; 221 struct mips_abi *abi;
164}; 222};
165 223
@@ -171,6 +229,13 @@ struct thread_struct {
171#define FPAFF_INIT 229#define FPAFF_INIT
172#endif /* CONFIG_MIPS_MT_FPAFF */ 230#endif /* CONFIG_MIPS_MT_FPAFF */
173 231
232#ifdef CONFIG_CPU_CAVIUM_OCTEON
233#define OCTEON_INIT \
234 .cp2 = INIT_OCTEON_COP2,
235#else
236#define OCTEON_INIT
237#endif /* CONFIG_CPU_CAVIUM_OCTEON */
238
174#define INIT_THREAD { \ 239#define INIT_THREAD { \
175 /* \ 240 /* \
176 * Saved main processor registers \ 241 * Saved main processor registers \
@@ -221,6 +286,10 @@ struct thread_struct {
221 .trap_no = 0, \ 286 .trap_no = 0, \
222 .irix_trampoline = 0, \ 287 .irix_trampoline = 0, \
223 .irix_oldctx = 0, \ 288 .irix_oldctx = 0, \
289 /* \
290 * Cavium Octeon specifics (null if not Octeon) \
291 */ \
292 OCTEON_INIT \
224} 293}
225 294
226struct task_struct; 295struct task_struct;