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-rw-r--r--arch/mips/Kconfig19
-rw-r--r--arch/mips/cobalt/pci.c4
-rw-r--r--arch/mips/gt64120/wrppmc/pci.c4
-rw-r--r--arch/mips/mips-boards/generic/pci.c4
-rw-r--r--arch/mips/pci/Makefile3
-rw-r--r--arch/mips/pci/ops-gt64111.c100
-rw-r--r--arch/mips/pci/ops-gt64xxx_pci0.c (renamed from arch/mips/pci/ops-gt64120.c)30
-rw-r--r--arch/mips/pci/pci-lasat.c4
-rw-r--r--arch/mips/pci/pci-ocelot.c2
9 files changed, 33 insertions, 137 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c78b14380b3e..2fd82e548187 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -165,7 +165,7 @@ config MIPS_COBALT
165 select HW_HAS_PCI 165 select HW_HAS_PCI
166 select I8259 166 select I8259
167 select IRQ_CPU 167 select IRQ_CPU
168 select MIPS_GT64111 168 select PCI_GT64XXX_PCI0
169 select SYS_HAS_CPU_NEVADA 169 select SYS_HAS_CPU_NEVADA
170 select SYS_HAS_EARLY_PRINTK 170 select SYS_HAS_EARLY_PRINTK
171 select SYS_SUPPORTS_32BIT_KERNEL 171 select SYS_SUPPORTS_32BIT_KERNEL
@@ -207,7 +207,7 @@ config MIPS_EV64120
207 depends on EXPERIMENTAL 207 depends on EXPERIMENTAL
208 select DMA_NONCOHERENT 208 select DMA_NONCOHERENT
209 select HW_HAS_PCI 209 select HW_HAS_PCI
210 select MIPS_GT64120 210 select PCI_GT64XXX_PCI0
211 select SYS_HAS_CPU_R5000 211 select SYS_HAS_CPU_R5000
212 select SYS_SUPPORTS_32BIT_KERNEL 212 select SYS_SUPPORTS_32BIT_KERNEL
213 select SYS_SUPPORTS_64BIT_KERNEL 213 select SYS_SUPPORTS_64BIT_KERNEL
@@ -245,7 +245,7 @@ config LASAT
245 select DMA_NONCOHERENT 245 select DMA_NONCOHERENT
246 select SYS_HAS_EARLY_PRINTK 246 select SYS_HAS_EARLY_PRINTK
247 select HW_HAS_PCI 247 select HW_HAS_PCI
248 select MIPS_GT64120 248 select PCI_GT64XXX_PCI0
249 select MIPS_NILE4 249 select MIPS_NILE4
250 select R5000_CPU_SCACHE 250 select R5000_CPU_SCACHE
251 select SYS_HAS_CPU_R5000 251 select SYS_HAS_CPU_R5000
@@ -263,7 +263,7 @@ config MIPS_ATLAS
263 select HW_HAS_PCI 263 select HW_HAS_PCI
264 select MIPS_BOARDS_GEN 264 select MIPS_BOARDS_GEN
265 select MIPS_BONITO64 265 select MIPS_BONITO64
266 select MIPS_GT64120 266 select PCI_GT64XXX_PCI0
267 select MIPS_MSC 267 select MIPS_MSC
268 select RM7000_CPU_SCACHE 268 select RM7000_CPU_SCACHE
269 select SWAP_IO_SPACE 269 select SWAP_IO_SPACE
@@ -296,7 +296,7 @@ config MIPS_MALTA
296 select MIPS_BOARDS_GEN 296 select MIPS_BOARDS_GEN
297 select MIPS_BONITO64 297 select MIPS_BONITO64
298 select MIPS_CPU_SCACHE 298 select MIPS_CPU_SCACHE
299 select MIPS_GT64120 299 select PCI_GT64XXX_PCI0
300 select MIPS_MSC 300 select MIPS_MSC
301 select SWAP_IO_SPACE 301 select SWAP_IO_SPACE
302 select SYS_HAS_CPU_MIPS32_R1 302 select SYS_HAS_CPU_MIPS32_R1
@@ -340,7 +340,7 @@ config WR_PPMC
340 select BOOT_ELF32 340 select BOOT_ELF32
341 select DMA_NONCOHERENT 341 select DMA_NONCOHERENT
342 select HW_HAS_PCI 342 select HW_HAS_PCI
343 select MIPS_GT64120 343 select PCI_GT64XXX_PCI0
344 select SWAP_IO_SPACE 344 select SWAP_IO_SPACE
345 select SYS_HAS_CPU_MIPS32_R1 345 select SYS_HAS_CPU_MIPS32_R1
346 select SYS_HAS_CPU_MIPS32_R2 346 select SYS_HAS_CPU_MIPS32_R2
@@ -398,7 +398,7 @@ config MOMENCO_OCELOT
398 select HW_HAS_PCI 398 select HW_HAS_PCI
399 select IRQ_CPU 399 select IRQ_CPU
400 select IRQ_CPU_RM7K 400 select IRQ_CPU_RM7K
401 select MIPS_GT64120 401 select PCI_GT64XXX_PCI0
402 select RM7000_CPU_SCACHE 402 select RM7000_CPU_SCACHE
403 select SWAP_IO_SPACE 403 select SWAP_IO_SPACE
404 select SYS_HAS_CPU_RM7000 404 select SYS_HAS_CPU_RM7000
@@ -999,10 +999,7 @@ config DDB5XXX_COMMON
999config MIPS_BOARDS_GEN 999config MIPS_BOARDS_GEN
1000 bool 1000 bool
1001 1001
1002config MIPS_GT64111 1002config PCI_GT64XXX_PCI0
1003 bool
1004
1005config MIPS_GT64120
1006 bool 1003 bool
1007 1004
1008config MIPS_TX3927 1005config MIPS_TX3927
diff --git a/arch/mips/cobalt/pci.c b/arch/mips/cobalt/pci.c
index d01600639546..d91027f43de6 100644
--- a/arch/mips/cobalt/pci.c
+++ b/arch/mips/cobalt/pci.c
@@ -14,7 +14,7 @@
14 14
15#include <asm/gt64120.h> 15#include <asm/gt64120.h>
16 16
17extern struct pci_ops gt64111_pci_ops; 17extern struct pci_ops gt64xxx_pci0_ops;
18 18
19static struct resource cobalt_mem_resource = { 19static struct resource cobalt_mem_resource = {
20 .start = GT_DEF_PCI0_MEM0_BASE, 20 .start = GT_DEF_PCI0_MEM0_BASE,
@@ -31,7 +31,7 @@ static struct resource cobalt_io_resource = {
31}; 31};
32 32
33static struct pci_controller cobalt_pci_controller = { 33static struct pci_controller cobalt_pci_controller = {
34 .pci_ops = &gt64111_pci_ops, 34 .pci_ops = &gt64xxx_pci0_ops,
35 .mem_resource = &cobalt_mem_resource, 35 .mem_resource = &cobalt_mem_resource,
36 .io_resource = &cobalt_io_resource, 36 .io_resource = &cobalt_io_resource,
37 .io_offset = 0 - GT_DEF_PCI0_IO_BASE, 37 .io_offset = 0 - GT_DEF_PCI0_IO_BASE,
diff --git a/arch/mips/gt64120/wrppmc/pci.c b/arch/mips/gt64120/wrppmc/pci.c
index 2fbe93467f78..0d5289bc1804 100644
--- a/arch/mips/gt64120/wrppmc/pci.c
+++ b/arch/mips/gt64120/wrppmc/pci.c
@@ -13,7 +13,7 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <asm/gt64120.h> 14#include <asm/gt64120.h>
15 15
16extern struct pci_ops gt64120_pci_ops; 16extern struct pci_ops gt64xxx_pci0_ops;
17 17
18static struct resource pci0_io_resource = { 18static struct resource pci0_io_resource = {
19 .name = "pci_0 io", 19 .name = "pci_0 io",
@@ -30,7 +30,7 @@ static struct resource pci0_mem_resource = {
30}; 30};
31 31
32static struct pci_controller hose_0 = { 32static struct pci_controller hose_0 = {
33 .pci_ops = &gt64120_pci_ops, 33 .pci_ops = &gt64xxx_pci0_ops,
34 .io_resource = &pci0_io_resource, 34 .io_resource = &pci0_io_resource,
35 .mem_resource = &pci0_mem_resource, 35 .mem_resource = &pci0_mem_resource,
36}; 36};
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index 3192a14698c8..f98d60f78658 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -65,7 +65,7 @@ static struct resource msc_io_resource = {
65}; 65};
66 66
67extern struct pci_ops bonito64_pci_ops; 67extern struct pci_ops bonito64_pci_ops;
68extern struct pci_ops gt64120_pci_ops; 68extern struct pci_ops gt64xxx_pci0_ops;
69extern struct pci_ops msc_pci_ops; 69extern struct pci_ops msc_pci_ops;
70 70
71static struct pci_controller bonito64_controller = { 71static struct pci_controller bonito64_controller = {
@@ -76,7 +76,7 @@ static struct pci_controller bonito64_controller = {
76}; 76};
77 77
78static struct pci_controller gt64120_controller = { 78static struct pci_controller gt64120_controller = {
79 .pci_ops = &gt64120_pci_ops, 79 .pci_ops = &gt64xxx_pci0_ops,
80 .io_resource = &gt64120_io_resource, 80 .io_resource = &gt64120_io_resource,
81 .mem_resource = &gt64120_mem_resource, 81 .mem_resource = &gt64120_mem_resource,
82}; 82};
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index bf85995ca042..df487c063b1d 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -8,8 +8,7 @@ obj-y += pci.o pci-dac.o
8# PCI bus host bridge specific code 8# PCI bus host bridge specific code
9# 9#
10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o 10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
11obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o 11obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
12obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o
13obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o 12obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o
14obj-$(CONFIG_MIPS_MSC) += ops-msc.o 13obj-$(CONFIG_MIPS_MSC) += ops-msc.o
15obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o 14obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
diff --git a/arch/mips/pci/ops-gt64111.c b/arch/mips/pci/ops-gt64111.c
deleted file mode 100644
index ecd3991bd0e4..000000000000
--- a/arch/mips/pci/ops-gt64111.c
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 1996, 1997, 2002 by Ralf Baechle
7 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
8 */
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13
14#include <asm/pci.h>
15#include <asm/io.h>
16#include <asm/gt64120.h>
17
18#include <asm/mach-cobalt/cobalt.h>
19
20/*
21 * Device 31 on the GT64111 is used to generate PCI special
22 * cycles, so we shouldn't expected to find a device there ...
23 */
24static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn)
25{
26 if (bus->number == 0 && PCI_SLOT(devfn) < 31)
27 return 0;
28
29 return -1;
30}
31
32static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
33 int where, int size, u32 * val)
34{
35 if (pci_range_ck(bus, devfn))
36 return PCIBIOS_DEVICE_NOT_FOUND;
37
38 switch (size) {
39 case 4:
40 PCI_CFG_SET(devfn, where);
41 *val = GT_READ(GT_PCI0_CFGDATA_OFS);
42 return PCIBIOS_SUCCESSFUL;
43
44 case 2:
45 PCI_CFG_SET(devfn, (where & ~0x3));
46 *val = GT_READ(GT_PCI0_CFGDATA_OFS)
47 >> ((where & 3) * 8);
48 return PCIBIOS_SUCCESSFUL;
49
50 case 1:
51 PCI_CFG_SET(devfn, (where & ~0x3));
52 *val = GT_READ(GT_PCI0_CFGDATA_OFS)
53 >> ((where & 3) * 8);
54 return PCIBIOS_SUCCESSFUL;
55 }
56
57 return PCIBIOS_BAD_REGISTER_NUMBER;
58}
59
60static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn,
61 int where, int size, u32 val)
62{
63 u32 tmp;
64
65 if (pci_range_ck(bus, devfn))
66 return PCIBIOS_DEVICE_NOT_FOUND;
67
68 switch (size) {
69 case 4:
70 PCI_CFG_SET(devfn, where);
71 GT_WRITE(GT_PCI0_CFGDATA_OFS, val);
72
73 return PCIBIOS_SUCCESSFUL;
74
75 case 2:
76 PCI_CFG_SET(devfn, (where & ~0x3));
77 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
78 tmp &= ~(0xffff << ((where & 0x3) * 8));
79 tmp |= (val << ((where & 0x3) * 8));
80 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
81
82 return PCIBIOS_SUCCESSFUL;
83
84 case 1:
85 PCI_CFG_SET(devfn, (where & ~0x3));
86 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
87 tmp &= ~(0xff << ((where & 0x3) * 8));
88 tmp |= (val << ((where & 0x3) * 8));
89 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
90
91 return PCIBIOS_SUCCESSFUL;
92 }
93
94 return PCIBIOS_BAD_REGISTER_NUMBER;
95}
96
97struct pci_ops gt64111_pci_ops = {
98 .read = gt64111_pci_read_config,
99 .write = gt64111_pci_write_config,
100};
diff --git a/arch/mips/pci/ops-gt64120.c b/arch/mips/pci/ops-gt64xxx_pci0.c
index 6335844d607a..3d896c5f413f 100644
--- a/arch/mips/pci/ops-gt64120.c
+++ b/arch/mips/pci/ops-gt64xxx_pci0.c
@@ -39,8 +39,8 @@
39#define PCI_CFG_TYPE1_DEV_SHF 11 39#define PCI_CFG_TYPE1_DEV_SHF 11
40#define PCI_CFG_TYPE1_BUS_SHF 16 40#define PCI_CFG_TYPE1_BUS_SHF 16
41 41
42static int gt64120_pcibios_config_access(unsigned char access_type, 42static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
43 struct pci_bus *bus, unsigned int devfn, int where, u32 * data) 43 struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
44{ 44{
45 unsigned char busnum = bus->number; 45 unsigned char busnum = bus->number;
46 u32 intr; 46 u32 intr;
@@ -100,13 +100,13 @@ static int gt64120_pcibios_config_access(unsigned char access_type,
100 * We can't address 8 and 16 bit words directly. Instead we have to 100 * We can't address 8 and 16 bit words directly. Instead we have to
101 * read/write a 32bit word and mask/modify the data we actually want. 101 * read/write a 32bit word and mask/modify the data we actually want.
102 */ 102 */
103static int gt64120_pcibios_read(struct pci_bus *bus, unsigned int devfn, 103static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn,
104 int where, int size, u32 * val) 104 int where, int size, u32 * val)
105{ 105{
106 u32 data = 0; 106 u32 data = 0;
107 107
108 if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, 108 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
109 &data)) 109 where, &data))
110 return PCIBIOS_DEVICE_NOT_FOUND; 110 return PCIBIOS_DEVICE_NOT_FOUND;
111 111
112 if (size == 1) 112 if (size == 1)
@@ -119,16 +119,16 @@ static int gt64120_pcibios_read(struct pci_bus *bus, unsigned int devfn,
119 return PCIBIOS_SUCCESSFUL; 119 return PCIBIOS_SUCCESSFUL;
120} 120}
121 121
122static int gt64120_pcibios_write(struct pci_bus *bus, unsigned int devfn, 122static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
123 int where, int size, u32 val) 123 int where, int size, u32 val)
124{ 124{
125 u32 data = 0; 125 u32 data = 0;
126 126
127 if (size == 4) 127 if (size == 4)
128 data = val; 128 data = val;
129 else { 129 else {
130 if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, 130 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,
131 where, &data)) 131 devfn, where, &data))
132 return PCIBIOS_DEVICE_NOT_FOUND; 132 return PCIBIOS_DEVICE_NOT_FOUND;
133 133
134 if (size == 1) 134 if (size == 1)
@@ -139,14 +139,14 @@ static int gt64120_pcibios_write(struct pci_bus *bus, unsigned int devfn,
139 (val << ((where & 3) << 3)); 139 (val << ((where & 3) << 3));
140 } 140 }
141 141
142 if (gt64120_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, 142 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
143 &data)) 143 where, &data))
144 return PCIBIOS_DEVICE_NOT_FOUND; 144 return PCIBIOS_DEVICE_NOT_FOUND;
145 145
146 return PCIBIOS_SUCCESSFUL; 146 return PCIBIOS_SUCCESSFUL;
147} 147}
148 148
149struct pci_ops gt64120_pci_ops = { 149struct pci_ops gt64xxx_pci0_ops = {
150 .read = gt64120_pcibios_read, 150 .read = gt64xxx_pci0_pcibios_read,
151 .write = gt64120_pcibios_write 151 .write = gt64xxx_pci0_pcibios_write
152}; 152};
diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c
index 88fb191ad2eb..985784a3e6f8 100644
--- a/arch/mips/pci/pci-lasat.c
+++ b/arch/mips/pci/pci-lasat.c
@@ -12,7 +12,7 @@
12#include <asm/bootinfo.h> 12#include <asm/bootinfo.h>
13 13
14extern struct pci_ops nile4_pci_ops; 14extern struct pci_ops nile4_pci_ops;
15extern struct pci_ops gt64120_pci_ops; 15extern struct pci_ops gt64xxx_pci0_ops;
16static struct resource lasat_pci_mem_resource = { 16static struct resource lasat_pci_mem_resource = {
17 .name = "LASAT PCI MEM", 17 .name = "LASAT PCI MEM",
18 .start = 0x18000000, 18 .start = 0x18000000,
@@ -38,7 +38,7 @@ static int __init lasat_pci_setup(void)
38 38
39 switch (mips_machtype) { 39 switch (mips_machtype) {
40 case MACH_LASAT_100: 40 case MACH_LASAT_100:
41 lasat_pci_controller.pci_ops = &gt64120_pci_ops; 41 lasat_pci_controller.pci_ops = &gt64xxx_pci0_ops;
42 break; 42 break;
43 case MACH_LASAT_200: 43 case MACH_LASAT_200:
44 lasat_pci_controller.pci_ops = &nile4_pci_ops; 44 lasat_pci_controller.pci_ops = &nile4_pci_ops;
diff --git a/arch/mips/pci/pci-ocelot.c b/arch/mips/pci/pci-ocelot.c
index 2b9495dce6ba..7f94f26d35ae 100644
--- a/arch/mips/pci/pci-ocelot.c
+++ b/arch/mips/pci/pci-ocelot.c
@@ -81,7 +81,7 @@ static struct resource ocelot_io_resource = {
81}; 81};
82 82
83static struct pci_controller ocelot_pci_controller = { 83static struct pci_controller ocelot_pci_controller = {
84 .pci_ops = gt64120_pci_ops; 84 .pci_ops = gt64xxx_pci0_ops;
85 .mem_resource = &ocelot_mem_resource; 85 .mem_resource = &ocelot_mem_resource;
86 .io_resource = &ocelot_io_resource; 86 .io_resource = &ocelot_io_resource;
87}; 87};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 16:17:50 -0500