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-rw-r--r--arch/mips/Kconfig292
-rw-r--r--arch/mips/Makefile46
-rw-r--r--arch/mips/au1000/common/pci.c8
-rw-r--r--arch/mips/au1000/common/setup.c2
-rw-r--r--arch/mips/au1000/common/time.c14
-rw-r--r--arch/mips/au1000/csb250/board_setup.c4
-rw-r--r--arch/mips/au1000/csb250/init.c2
-rw-r--r--arch/mips/au1000/db1x00/init.c2
-rw-r--r--arch/mips/au1000/hydrogen3/init.c2
-rw-r--r--arch/mips/au1000/pb1000/board_setup.c2
-rw-r--r--arch/mips/au1000/xxs1500/board_setup.c6
-rw-r--r--arch/mips/au1000/xxs1500/init.c2
-rw-r--r--arch/mips/au1000/xxs1500/irqmap.c2
-rw-r--r--arch/mips/configs/atlas_defconfig5
-rw-r--r--arch/mips/configs/capcella_defconfig5
-rw-r--r--arch/mips/configs/cobalt_defconfig5
-rw-r--r--arch/mips/configs/db1000_defconfig5
-rw-r--r--arch/mips/configs/db1100_defconfig5
-rw-r--r--arch/mips/configs/db1500_defconfig4
-rw-r--r--arch/mips/configs/db1550_defconfig4
-rw-r--r--arch/mips/configs/ddb5476_defconfig5
-rw-r--r--arch/mips/configs/ddb5477_defconfig5
-rw-r--r--arch/mips/configs/decstation_defconfig5
-rw-r--r--arch/mips/configs/e55_defconfig5
-rw-r--r--arch/mips/configs/ev64120_defconfig5
-rw-r--r--arch/mips/configs/ev96100_defconfig5
-rw-r--r--arch/mips/configs/ip22_defconfig5
-rw-r--r--arch/mips/configs/ip27_defconfig2
-rw-r--r--arch/mips/configs/ip32_defconfig3
-rw-r--r--arch/mips/configs/it8172_defconfig5
-rw-r--r--arch/mips/configs/ivr_defconfig5
-rw-r--r--arch/mips/configs/jaguar-atx_defconfig5
-rw-r--r--arch/mips/configs/jmr3927_defconfig5
-rw-r--r--arch/mips/configs/lasat200_defconfig5
-rw-r--r--arch/mips/configs/malta_defconfig5
-rw-r--r--arch/mips/configs/mpc30x_defconfig5
-rw-r--r--arch/mips/configs/ocelot_3_defconfig5
-rw-r--r--arch/mips/configs/ocelot_c_defconfig3
-rw-r--r--arch/mips/configs/ocelot_defconfig5
-rw-r--r--arch/mips/configs/ocelot_g_defconfig3
-rw-r--r--arch/mips/configs/pb1100_defconfig5
-rw-r--r--arch/mips/configs/pb1500_defconfig4
-rw-r--r--arch/mips/configs/pb1550_defconfig4
-rw-r--r--arch/mips/configs/qemu_defconfig (renamed from arch/mips/configs/osprey_defconfig)405
-rw-r--r--arch/mips/configs/rm200_defconfig5
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig4
-rw-r--r--arch/mips/configs/sead_defconfig5
-rw-r--r--arch/mips/configs/tb0226_defconfig5
-rw-r--r--arch/mips/configs/tb0229_defconfig5
-rw-r--r--arch/mips/configs/workpad_defconfig5
-rw-r--r--arch/mips/configs/yosemite_defconfig4
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq.c6
-rw-r--r--arch/mips/ddb5xxx/ddb5477/setup.c22
-rw-r--r--arch/mips/dec/ecc-berr.c2
-rw-r--r--arch/mips/dec/int-handler.S6
-rw-r--r--arch/mips/dec/prom/Makefile4
-rw-r--r--arch/mips/defconfig5
-rw-r--r--arch/mips/ite-boards/generic/it8172_setup.c2
-rw-r--r--arch/mips/ite-boards/generic/time.c16
-rw-r--r--arch/mips/kernel/Makefile10
-rw-r--r--arch/mips/kernel/binfmt_elfn32.c2
-rw-r--r--arch/mips/kernel/binfmt_elfo32.c2
-rw-r--r--arch/mips/kernel/cpu-bugs64.c4
-rw-r--r--arch/mips/kernel/cpu-probe.c6
-rw-r--r--arch/mips/kernel/gdb-low.S4
-rw-r--r--arch/mips/kernel/gdb-stub.c12
-rw-r--r--arch/mips/kernel/genex.S14
-rw-r--r--arch/mips/kernel/head.S6
-rw-r--r--arch/mips/kernel/ioctl32.c2
-rw-r--r--arch/mips/kernel/irixsig.c13
-rw-r--r--arch/mips/kernel/irq.c2
-rw-r--r--arch/mips/kernel/linux32.c22
-rw-r--r--arch/mips/kernel/mips_ksyms.c2
-rw-r--r--arch/mips/kernel/process.c8
-rw-r--r--arch/mips/kernel/ptrace.c12
-rw-r--r--arch/mips/kernel/r2300_switch.S4
-rw-r--r--arch/mips/kernel/r4k_fpu.S4
-rw-r--r--arch/mips/kernel/r4k_switch.S8
-rw-r--r--arch/mips/kernel/reset.c5
-rw-r--r--arch/mips/kernel/setup.c4
-rw-r--r--arch/mips/kernel/signal.c11
-rw-r--r--arch/mips/kernel/signal32.c15
-rw-r--r--arch/mips/kernel/traps.c2
-rw-r--r--arch/mips/kernel/unaligned.c12
-rw-r--r--arch/mips/kernel/vmlinux.lds.S2
-rw-r--r--arch/mips/lasat/at93c.c16
-rw-r--r--arch/mips/lasat/at93c.h4
-rw-r--r--arch/mips/lasat/ds1603.c12
-rw-r--r--arch/mips/lasat/ds1603.h6
-rw-r--r--arch/mips/lasat/image/Makefile2
-rw-r--r--arch/mips/lasat/image/head.S2
-rw-r--r--arch/mips/lasat/interrupt.c4
-rw-r--r--arch/mips/lasat/lasat_board.c8
-rw-r--r--arch/mips/lasat/picvue.c12
-rw-r--r--arch/mips/lasat/picvue.h4
-rw-r--r--arch/mips/lasat/picvue_proc.c10
-rw-r--r--arch/mips/lasat/prom.c2
-rw-r--r--arch/mips/lasat/reset.c2
-rw-r--r--arch/mips/lasat/setup.c4
-rw-r--r--arch/mips/lasat/sysctl.c26
-rw-r--r--arch/mips/lib-32/Makefile2
-rw-r--r--arch/mips/lib-64/Makefile2
-rw-r--r--arch/mips/lib/memcpy.S6
-rw-r--r--arch/mips/math-emu/cp1emu.c12
-rw-r--r--arch/mips/math-emu/kernel_linkage.c2
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c2
-rw-r--r--arch/mips/mips-boards/generic/init.c6
-rw-r--r--arch/mips/mips-boards/generic/time.c2
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c6
-rw-r--r--arch/mips/mm/Makefile4
-rw-r--r--arch/mips/mm/c-r4k.c20
-rw-r--r--arch/mips/mm/c-sb1.c2
-rw-r--r--arch/mips/mm/cerr-sb1.c24
-rw-r--r--arch/mips/mm/dma-noncoherent.c10
-rw-r--r--arch/mips/mm/init.c8
-rw-r--r--arch/mips/mm/pg-sb1.c10
-rw-r--r--arch/mips/mm/tlbex.c30
-rw-r--r--arch/mips/momentum/jaguar_atx/int-handler.S12
-rw-r--r--arch/mips/momentum/jaguar_atx/prom.c12
-rw-r--r--arch/mips/momentum/jaguar_atx/reset.c2
-rw-r--r--arch/mips/momentum/jaguar_atx/setup.c4
-rw-r--r--arch/mips/momentum/ocelot_3/prom.c12
-rw-r--r--arch/mips/momentum/ocelot_c/int-handler.S8
-rw-r--r--arch/mips/momentum/ocelot_c/ocelot_c_fpga.h2
-rw-r--r--arch/mips/momentum/ocelot_c/prom.c14
-rw-r--r--arch/mips/momentum/ocelot_c/reset.c2
-rw-r--r--arch/mips/momentum/ocelot_c/setup.c8
-rw-r--r--arch/mips/pci/fixup-ddb5074.c2
-rw-r--r--arch/mips/pci/fixup-ddb5477.c2
-rw-r--r--arch/mips/pci/fixup-malta.c2
-rw-r--r--arch/mips/pci/fixup-rbtx4927.c2
-rw-r--r--arch/mips/pci/fixup-sni.c2
-rw-r--r--arch/mips/pci/fixup-tb0219.c15
-rw-r--r--arch/mips/pci/ops-ddb5477.c4
-rw-r--r--arch/mips/pci/ops-tx4927.c6
-rw-r--r--arch/mips/pci/pci-ddb5477.c8
-rw-r--r--arch/mips/pci/pci-ip32.c2
-rw-r--r--arch/mips/pci/pci.c21
-rw-r--r--arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c14
-rw-r--r--arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h4
-rw-r--r--arch/mips/qemu/Makefile5
-rw-r--r--arch/mips/qemu/q-firmware.c7
-rw-r--r--arch/mips/qemu/q-int.S17
-rw-r--r--arch/mips/qemu/q-irq.c37
-rw-r--r--arch/mips/qemu/q-mem.c6
-rw-r--r--arch/mips/qemu/q-setup.c20
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-hpc.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c12
-rw-r--r--arch/mips/sgi-ip22/ip22-nvram.c8
-rw-r--r--arch/mips/sgi-ip22/ip22-reset.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-time.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-memory.c2
-rw-r--r--arch/mips/sgi-ip32/ip32-reset.c2
-rw-r--r--arch/mips/sibyte/cfe/cfe_error.h10
-rw-r--r--arch/mips/sibyte/cfe/console.c2
-rw-r--r--arch/mips/sibyte/cfe/setup.c4
-rw-r--r--arch/mips/sibyte/cfe/smp.c2
-rw-r--r--arch/mips/sibyte/sb1250/bus_watcher.c6
-rw-r--r--arch/mips/sibyte/sb1250/irq.c4
-rw-r--r--arch/mips/sibyte/swarm/rtc_m41t81.c10
-rw-r--r--arch/mips/sibyte/swarm/setup.c4
-rw-r--r--arch/mips/sni/irq.c2
-rw-r--r--arch/mips/sni/setup.c2
-rw-r--r--arch/mips/tx4927/common/tx4927_irq_handler.S6
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c2
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/Makefile6
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c42
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c2
-rw-r--r--arch/mips/vr4181/common/Makefile7
-rw-r--r--arch/mips/vr4181/common/int_handler.S206
-rw-r--r--arch/mips/vr4181/common/irq.c239
-rw-r--r--arch/mips/vr4181/common/serial.c51
-rw-r--r--arch/mips/vr4181/common/time.c145
-rw-r--r--arch/mips/vr4181/osprey/Makefile7
-rw-r--r--arch/mips/vr4181/osprey/dbg_io.c136
-rw-r--r--arch/mips/vr4181/osprey/prom.c49
-rw-r--r--arch/mips/vr4181/osprey/reset.c40
-rw-r--r--arch/mips/vr4181/osprey/setup.c68
-rw-r--r--arch/mips/vr41xx/casio-e55/setup.c5
-rw-r--r--arch/mips/vr41xx/common/Makefile2
-rw-r--r--arch/mips/vr41xx/common/giu.c455
-rw-r--r--arch/mips/vr41xx/common/icu.c270
-rw-r--r--arch/mips/vr41xx/common/int-handler.S10
-rw-r--r--arch/mips/vr41xx/common/irq.c94
-rw-r--r--arch/mips/vr41xx/common/type.c (renamed from arch/mips/vr41xx/tanbac-tb0226/setup.c)6
-rw-r--r--arch/mips/vr41xx/common/vrc4173.c2
-rw-r--r--arch/mips/vr41xx/ibm-workpad/setup.c5
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/init.c12
-rw-r--r--arch/mips/vr41xx/tanbac-tb0226/Makefile5
-rw-r--r--arch/mips/vr41xx/tanbac-tb0229/Makefile5
-rw-r--r--arch/mips/vr41xx/tanbac-tb0229/setup.c27
-rw-r--r--arch/mips/vr41xx/victor-mpc30x/Makefile5
-rw-r--r--arch/mips/vr41xx/victor-mpc30x/setup.c24
-rw-r--r--arch/mips/vr41xx/zao-capcella/Makefile5
-rw-r--r--arch/mips/vr41xx/zao-capcella/setup.c24
196 files changed, 1268 insertions, 2496 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index bd9de7b00c0a..d79fba0aa8bf 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -4,26 +4,46 @@ config MIPS
4 # Horrible source of confusion. Die, die, die ... 4 # Horrible source of confusion. Die, die, die ...
5 select EMBEDDED 5 select EMBEDDED
6 6
7config MIPS64 7mainmenu "Linux/MIPS Kernel Configuration"
8 bool "64-bit kernel"
9 help
10 Select this option if you want to build a 64-bit kernel. You should
11 only select this option if you have hardware that actually has a
12 64-bit processor and if your application will actually benefit from
13 64-bit processing, otherwise say N. You must say Y for kernels for
14 SGI IP27 (Origin 200 and 2000) and SGI IP32 (O2). If in doubt say N.
15 8
16config 64BIT 9source "init/Kconfig"
17 def_bool MIPS64
18 10
19config MIPS32 11config SYS_SUPPORTS_32BIT_KERNEL
12 bool
13config SYS_SUPPORTS_64BIT_KERNEL
14 bool
15config CPU_SUPPORTS_32BIT_KERNEL
16 bool
17config CPU_SUPPORTS_64BIT_KERNEL
20 bool 18 bool
21 depends on MIPS64 = 'n'
22 default y
23 19
24mainmenu "Linux/MIPS Kernel Configuration" 20menu "Kernel type"
25 21
26source "init/Kconfig" 22choice
23
24 prompt "Kernel code model"
25 help
26 You should only select this option if you have a workload that
27 actually benefits from 64-bit processing or if your machine has
28 large memory. You will only be presented a single option in this
29 menu if your system does not support both 32-bit and 64-bit kernels.
30
31config 32BIT
32 bool "32-bit kernel"
33 depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL
34 select TRAD_SIGNALS
35 help
36 Select this option if you want to build a 32-bit kernel.
37
38config 64BIT
39 bool "64-bit kernel"
40 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
41 help
42 Select this option if you want to build a 64-bit kernel.
43
44endchoice
45
46endmenu
27 47
28menu "Machine selection" 48menu "Machine selection"
29 49
@@ -34,6 +54,8 @@ config MACH_JAZZ
34 select GENERIC_ISA_DMA 54 select GENERIC_ISA_DMA
35 select I8259 55 select I8259
36 select ISA 56 select ISA
57 select SYS_SUPPORTS_32BIT_KERNEL
58 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
37 help 59 help
38 This a family of machines based on the MIPS R4030 chipset which was 60 This a family of machines based on the MIPS R4030 chipset which was
39 used by several vendors to build RISC/os and Windows NT workstations. 61 used by several vendors to build RISC/os and Windows NT workstations.
@@ -71,7 +93,9 @@ config OLIVETTI_M700
71 <http://www.linux-mips.org/>. 93 <http://www.linux-mips.org/>.
72 94
73config MACH_VR41XX 95config MACH_VR41XX
74 bool "Support for NEC VR41XX-based machines" 96 bool "Support for NEC VR4100 series based machines"
97 select SYS_SUPPORTS_32BIT_KERNEL
98 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
75 99
76config NEC_CMBVR4133 100config NEC_CMBVR4133
77 bool "Support for NEC CMB-VR4133" 101 bool "Support for NEC CMB-VR4133"
@@ -80,7 +104,6 @@ config NEC_CMBVR4133
80 select DMA_NONCOHERENT 104 select DMA_NONCOHERENT
81 select IRQ_CPU 105 select IRQ_CPU
82 select HW_HAS_PCI 106 select HW_HAS_PCI
83 select PCI_VR41XX
84 107
85config ROCKHOPPER 108config ROCKHOPPER
86 bool "Support for Rockhopper baseboard" 109 bool "Support for Rockhopper baseboard"
@@ -91,6 +114,7 @@ config ROCKHOPPER
91config CASIO_E55 114config CASIO_E55
92 bool "Support for CASIO CASSIOPEIA E-10/15/55/65" 115 bool "Support for CASIO CASSIOPEIA E-10/15/55/65"
93 depends on MACH_VR41XX 116 depends on MACH_VR41XX
117 select CPU_LITTLE_ENDIAN
94 select DMA_NONCOHERENT 118 select DMA_NONCOHERENT
95 select IRQ_CPU 119 select IRQ_CPU
96 select ISA 120 select ISA
@@ -98,53 +122,54 @@ config CASIO_E55
98config IBM_WORKPAD 122config IBM_WORKPAD
99 bool "Support for IBM WorkPad z50" 123 bool "Support for IBM WorkPad z50"
100 depends on MACH_VR41XX 124 depends on MACH_VR41XX
125 select CPU_LITTLE_ENDIAN
101 select DMA_NONCOHERENT 126 select DMA_NONCOHERENT
102 select IRQ_CPU 127 select IRQ_CPU
103 select ISA 128 select ISA
104 129
105config TANBAC_TB0226 130config TANBAC_TB022X
106 bool "Support for TANBAC TB0226 (Mbase)" 131 bool "Support for TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
107 depends on MACH_VR41XX 132 depends on MACH_VR41XX
133 select CPU_LITTLE_ENDIAN
108 select DMA_NONCOHERENT 134 select DMA_NONCOHERENT
109 select HW_HAS_PCI
110 select IRQ_CPU 135 select IRQ_CPU
136 select HW_HAS_PCI
111 help 137 help
112 The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by TANBAC. 138 The TANBAC VR4131 multichip module(TB0225) and
113 Please refer to <http://www.tanbac.co.jp/> about Mbase. 139 the TANBAC VR4131DIMM(TB0229) are MIPS-based platforms
140 manufactured by TANBAC.
141 Please refer to <http://www.tanbac.co.jp/>
142 about VR4131 multichip module and VR4131DIMM.
114 143
115config TANBAC_TB0229 144config TANBAC_TB0226
116 bool "Support for TANBAC TB0229 (VR4131DIMM)" 145 bool "Support for TANBAC Mbase(TB0226)"
117 depends on MACH_VR41XX 146 depends on TANBAC_TB022X
118 select DMA_NONCOHERENT 147 select GPIO_VR41XX
119 select HW_HAS_PCI
120 select IRQ_CPU
121 help 148 help
122 The TANBAC TB0229 (VR4131DIMM) is a MIPS-based platform manufactured by TANBAC. 149 The TANBAC Mbase(TB0226) is a MIPS-based platform manufactured by TANBAC.
123 Please refer to <http://www.tanbac.co.jp/> about VR4131DIMM. 150 Please refer to <http://www.tanbac.co.jp/> about Mbase.
124 151
125config VICTOR_MPC30X 152config VICTOR_MPC30X
126 bool "Support for Victor MP-C303/304" 153 bool "Support for Victor MP-C303/304"
154 depends on MACH_VR41XX
155 select CPU_LITTLE_ENDIAN
127 select DMA_NONCOHERENT 156 select DMA_NONCOHERENT
128 select HW_HAS_PCI
129 select IRQ_CPU 157 select IRQ_CPU
130 depends on MACH_VR41XX 158 select HW_HAS_PCI
131 159
132config ZAO_CAPCELLA 160config ZAO_CAPCELLA
133 bool "Support for ZAO Networks Capcella" 161 bool "Support for ZAO Networks Capcella"
134 depends on MACH_VR41XX 162 depends on MACH_VR41XX
163 select CPU_LITTLE_ENDIAN
135 select DMA_NONCOHERENT 164 select DMA_NONCOHERENT
136 select HW_HAS_PCI
137 select IRQ_CPU 165 select IRQ_CPU
166 select HW_HAS_PCI
138 167
139config PCI_VR41XX 168config PCI_VR41XX
140 bool "Add PCI control unit support of NEC VR4100 series" 169 bool "Add PCI control unit support of NEC VR4100 series"
141 depends on MACH_VR41XX && PCI 170 depends on MACH_VR41XX && HW_HAS_PCI
142 171 default y
143config VRC4171 172 select PCI
144 tristate "Add NEC VRC4171 companion chip support"
145 depends on MACH_VR41XX && ISA
146 ---help---
147 The NEC VRC4171/4171A is a companion chip for NEC VR4111/VR4121.
148 173
149config VRC4173 174config VRC4173
150 tristate "Add NEC VRC4173 companion chip support" 175 tristate "Add NEC VRC4173 companion chip support"
@@ -154,25 +179,28 @@ config VRC4173
154 179
155config TOSHIBA_JMR3927 180config TOSHIBA_JMR3927
156 bool "Support for Toshiba JMR-TX3927 board" 181 bool "Support for Toshiba JMR-TX3927 board"
157 depends on MIPS32
158 select DMA_NONCOHERENT 182 select DMA_NONCOHERENT
159 select HW_HAS_PCI 183 select HW_HAS_PCI
160 select SWAP_IO_SPACE 184 select SWAP_IO_SPACE
185 select SYS_SUPPORTS_32BIT_KERNEL
161 186
162config MIPS_COBALT 187config MIPS_COBALT
163 bool "Support for Cobalt Server (EXPERIMENTAL)" 188 bool "Support for Cobalt Server"
164 depends on EXPERIMENTAL 189 depends on EXPERIMENTAL
165 select DMA_NONCOHERENT 190 select DMA_NONCOHERENT
166 select HW_HAS_PCI 191 select HW_HAS_PCI
167 select I8259 192 select I8259
168 select IRQ_CPU 193 select IRQ_CPU
194 select SYS_SUPPORTS_32BIT_KERNEL
195 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
169 196
170config MACH_DECSTATION 197config MACH_DECSTATION
171 bool "Support for DECstations" 198 bool "Support for DECstations"
172 select BOOT_ELF32 199 select BOOT_ELF32
173 select DMA_NONCOHERENT 200 select DMA_NONCOHERENT
174 select IRQ_CPU 201 select IRQ_CPU
175 depends on MIPS32 || EXPERIMENTAL 202 select SYS_SUPPORTS_32BIT_KERNEL
203 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
176 ---help--- 204 ---help---
177 This enables support for DEC's MIPS based workstations. For details 205 This enables support for DEC's MIPS based workstations. For details
178 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the 206 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
@@ -194,6 +222,8 @@ config MIPS_EV64120
194 select DMA_NONCOHERENT 222 select DMA_NONCOHERENT
195 select HW_HAS_PCI 223 select HW_HAS_PCI
196 select MIPS_GT64120 224 select MIPS_GT64120
225 select SYS_SUPPORTS_32BIT_KERNEL
226 select SYS_SUPPORTS_64BIT_KERNEL
197 help 227 help
198 This is an evaluation board based on the Galileo GT-64120 228 This is an evaluation board based on the Galileo GT-64120
199 single-chip system controller that contains a MIPS R5000 compatible 229 single-chip system controller that contains a MIPS R5000 compatible
@@ -214,6 +244,8 @@ config MIPS_EV96100
214 select MIPS_GT96100 244 select MIPS_GT96100
215 select RM7000_CPU_SCACHE 245 select RM7000_CPU_SCACHE
216 select SWAP_IO_SPACE 246 select SWAP_IO_SPACE
247 select SYS_SUPPORTS_32BIT_KERNEL
248 select SYS_SUPPORTS_64BIT_KERNEL
217 help 249 help
218 This is an evaluation board based on the Galileo GT-96100 LAN/WAN 250 This is an evaluation board based on the Galileo GT-96100 LAN/WAN
219 communications controllers containing a MIPS R5000 compatible core 251 communications controllers containing a MIPS R5000 compatible core
@@ -224,6 +256,8 @@ config MIPS_IVR
224 bool "Support for Globespan IVR board" 256 bool "Support for Globespan IVR board"
225 select DMA_NONCOHERENT 257 select DMA_NONCOHERENT
226 select HW_HAS_PCI 258 select HW_HAS_PCI
259 select SYS_SUPPORTS_32BIT_KERNEL
260 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
227 help 261 help
228 This is an evaluation board built by Globespan to showcase thir 262 This is an evaluation board built by Globespan to showcase thir
229 iVR (Internet Video Recorder) design. It utilizes a QED RM5231 263 iVR (Internet Video Recorder) design. It utilizes a QED RM5231
@@ -237,6 +271,8 @@ config LASAT
237 select HW_HAS_PCI 271 select HW_HAS_PCI
238 select MIPS_GT64120 272 select MIPS_GT64120
239 select R5000_CPU_SCACHE 273 select R5000_CPU_SCACHE
274 select SYS_SUPPORTS_32BIT_KERNEL
275 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
240 276
241config PICVUE 277config PICVUE
242 tristate "PICVUE LCD display driver" 278 tristate "PICVUE LCD display driver"
@@ -258,6 +294,8 @@ config MIPS_ITE8172
258 bool "Support for ITE 8172G board" 294 bool "Support for ITE 8172G board"
259 select DMA_NONCOHERENT 295 select DMA_NONCOHERENT
260 select HW_HAS_PCI 296 select HW_HAS_PCI
297 select SYS_SUPPORTS_32BIT_KERNEL
298 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
261 help 299 help
262 Ths is an evaluation board made by ITE <http://www.ite.com.tw/> 300 Ths is an evaluation board made by ITE <http://www.ite.com.tw/>
263 with ATX form factor that utilizes a MIPS R5000 to work with its 301 with ATX form factor that utilizes a MIPS R5000 to work with its
@@ -281,6 +319,8 @@ config MIPS_ATLAS
281 select HW_HAS_PCI 319 select HW_HAS_PCI
282 select MIPS_GT64120 320 select MIPS_GT64120
283 select SWAP_IO_SPACE 321 select SWAP_IO_SPACE
322 select SYS_SUPPORTS_32BIT_KERNEL
323 select SYS_SUPPORTS_64BIT_KERNEL
284 help 324 help
285 This enables support for the QED R5231-based MIPS Atlas evaluation 325 This enables support for the QED R5231-based MIPS Atlas evaluation
286 board. 326 board.
@@ -295,6 +335,8 @@ config MIPS_MALTA
295 select I8259 335 select I8259
296 select MIPS_GT64120 336 select MIPS_GT64120
297 select SWAP_IO_SPACE 337 select SWAP_IO_SPACE
338 select SYS_SUPPORTS_32BIT_KERNEL
339 select SYS_SUPPORTS_64BIT_KERNEL
298 help 340 help
299 This enables support for the VR5000-based MIPS Malta evaluation 341 This enables support for the VR5000-based MIPS Malta evaluation
300 board. 342 board.
@@ -304,6 +346,8 @@ config MIPS_SEAD
304 depends on EXPERIMENTAL 346 depends on EXPERIMENTAL
305 select IRQ_CPU 347 select IRQ_CPU
306 select DMA_NONCOHERENT 348 select DMA_NONCOHERENT
349 select SYS_SUPPORTS_32BIT_KERNEL
350 select SYS_SUPPORTS_64BIT_KERNEL
307 351
308config MOMENCO_OCELOT 352config MOMENCO_OCELOT
309 bool "Support for Momentum Ocelot board" 353 bool "Support for Momentum Ocelot board"
@@ -314,6 +358,8 @@ config MOMENCO_OCELOT
314 select MIPS_GT64120 358 select MIPS_GT64120
315 select RM7000_CPU_SCACHE 359 select RM7000_CPU_SCACHE
316 select SWAP_IO_SPACE 360 select SWAP_IO_SPACE
361 select SYS_SUPPORTS_32BIT_KERNEL
362 select SYS_SUPPORTS_64BIT_KERNEL
317 help 363 help
318 The Ocelot is a MIPS-based Single Board Computer (SBC) made by 364 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
319 Momentum Computer <http://www.momenco.com/>. 365 Momentum Computer <http://www.momenco.com/>.
@@ -327,6 +373,8 @@ config MOMENCO_OCELOT_G
327 select PCI_MARVELL 373 select PCI_MARVELL
328 select RM7000_CPU_SCACHE 374 select RM7000_CPU_SCACHE
329 select SWAP_IO_SPACE 375 select SWAP_IO_SPACE
376 select SYS_SUPPORTS_32BIT_KERNEL
377 select SYS_SUPPORTS_64BIT_KERNEL
330 help 378 help
331 The Ocelot is a MIPS-based Single Board Computer (SBC) made by 379 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
332 Momentum Computer <http://www.momenco.com/>. 380 Momentum Computer <http://www.momenco.com/>.
@@ -340,6 +388,8 @@ config MOMENCO_OCELOT_C
340 select PCI_MARVELL 388 select PCI_MARVELL
341 select RM7000_CPU_SCACHE 389 select RM7000_CPU_SCACHE
342 select SWAP_IO_SPACE 390 select SWAP_IO_SPACE
391 select SYS_SUPPORTS_32BIT_KERNEL
392 select SYS_SUPPORTS_64BIT_KERNEL
343 help 393 help
344 The Ocelot is a MIPS-based Single Board Computer (SBC) made by 394 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
345 Momentum Computer <http://www.momenco.com/>. 395 Momentum Computer <http://www.momenco.com/>.
@@ -355,6 +405,8 @@ config MOMENCO_OCELOT_3
355 select PCI_MARVELL 405 select PCI_MARVELL
356 select RM7000_CPU_SCACHE 406 select RM7000_CPU_SCACHE
357 select SWAP_IO_SPACE 407 select SWAP_IO_SPACE
408 select SYS_SUPPORTS_32BIT_KERNEL
409 select SYS_SUPPORTS_64BIT_KERNEL
358 help 410 help
359 The Ocelot-3 is based off Discovery III System Controller and 411 The Ocelot-3 is based off Discovery III System Controller and
360 PMC-Sierra Rm79000 core. 412 PMC-Sierra Rm79000 core.
@@ -371,6 +423,8 @@ config MOMENCO_JAGUAR_ATX
371 select PCI_MARVELL 423 select PCI_MARVELL
372 select RM7000_CPU_SCACHE 424 select RM7000_CPU_SCACHE
373 select SWAP_IO_SPACE 425 select SWAP_IO_SPACE
426 select SYS_SUPPORTS_32BIT_KERNEL
427 select SYS_SUPPORTS_64BIT_KERNEL
374 help 428 help
375 The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by 429 The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
376 Momentum Computer <http://www.momenco.com/>. 430 Momentum Computer <http://www.momenco.com/>.
@@ -390,6 +444,8 @@ config PMC_YOSEMITE
390 select IRQ_CPU_RM7K 444 select IRQ_CPU_RM7K
391 select IRQ_CPU_RM9K 445 select IRQ_CPU_RM9K
392 select SWAP_IO_SPACE 446 select SWAP_IO_SPACE
447 select SYS_SUPPORTS_32BIT_KERNEL
448 select SYS_SUPPORTS_64BIT_KERNEL
393 help 449 help
394 Yosemite is an evaluation board for the RM9000x2 processor 450 Yosemite is an evaluation board for the RM9000x2 processor
395 manufactured by PMC-Sierra 451 manufactured by PMC-Sierra
@@ -407,6 +463,8 @@ config DDB5074
407 select IRQ_CPU 463 select IRQ_CPU
408 select I8259 464 select I8259
409 select ISA 465 select ISA
466 select SYS_SUPPORTS_32BIT_KERNEL
467 select SYS_SUPPORTS_64BIT_KERNEL
410 help 468 help
411 This enables support for the VR5000-based NEC DDB Vrc-5074 469 This enables support for the VR5000-based NEC DDB Vrc-5074
412 evaluation board. 470 evaluation board.
@@ -419,6 +477,8 @@ config DDB5476
419 select IRQ_CPU 477 select IRQ_CPU
420 select I8259 478 select I8259
421 select ISA 479 select ISA
480 select SYS_SUPPORTS_32BIT_KERNEL
481 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
422 help 482 help
423 This enables support for the R5432-based NEC DDB Vrc-5476 483 This enables support for the R5432-based NEC DDB Vrc-5476
424 evaluation board. 484 evaluation board.
@@ -433,6 +493,8 @@ config DDB5477
433 select HW_HAS_PCI 493 select HW_HAS_PCI
434 select I8259 494 select I8259
435 select IRQ_CPU 495 select IRQ_CPU
496 select SYS_SUPPORTS_32BIT_KERNEL
497 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
436 help 498 help
437 This enables support for the R5432-based NEC DDB Vrc-5477, 499 This enables support for the R5432-based NEC DDB Vrc-5477,
438 or Rockhopper/SolutionGear boards with R5432/R5500 CPUs. 500 or Rockhopper/SolutionGear boards with R5432/R5500 CPUs.
@@ -445,10 +507,23 @@ config DDB5477_BUS_FREQUENCY
445 depends on DDB5477 507 depends on DDB5477
446 default 0 508 default 0
447 509
448config NEC_OSPREY 510config QEMU
449 bool "Support for NEC Osprey board" 511 bool "Support for Qemu"
450 select DMA_NONCOHERENT 512 select DMA_COHERENT
451 select IRQ_CPU 513 select GENERIC_ISA_DMA
514 select HAVE_STD_PC_SERIAL_PORT
515 select I8259
516 select ISA
517 select SWAP_IO_SPACE
518 select SYS_SUPPORTS_32BIT_KERNEL
519 select SYS_SUPPORTS_BIG_ENDIAN
520 help
521 Qemu is a software emulator which among other architectures also
522 can simulate a MIPS32 4Kc system. This patch adds support for the
523 system architecture that currently is being simulated by Qemu. It
524 will eventually be removed again when Qemu has the capability to
525 simulate actual MIPS hardware platforms. More information on Qemu
526 can be found at http://www.linux-mips.org/wiki/Qemu.
452 527
453config SGI_IP22 528config SGI_IP22
454 bool "Support for SGI IP22 (Indy/Indigo2)" 529 bool "Support for SGI IP22 (Indy/Indigo2)"
@@ -459,6 +534,8 @@ config SGI_IP22
459 select IP22_CPU_SCACHE 534 select IP22_CPU_SCACHE
460 select IRQ_CPU 535 select IRQ_CPU
461 select SWAP_IO_SPACE 536 select SWAP_IO_SPACE
537 select SYS_SUPPORTS_32BIT_KERNEL
538 select SYS_SUPPORTS_64BIT_KERNEL
462 help 539 help
463 This are the SGI Indy, Challenge S and Indigo2, as well as certain 540 This are the SGI Indy, Challenge S and Indigo2, as well as certain
464 OEM variants like the Tandem CMN B006S. To compile a Linux kernel 541 OEM variants like the Tandem CMN B006S. To compile a Linux kernel
@@ -466,12 +543,12 @@ config SGI_IP22
466 543
467config SGI_IP27 544config SGI_IP27
468 bool "Support for SGI IP27 (Origin200/2000)" 545 bool "Support for SGI IP27 (Origin200/2000)"
469 depends on MIPS64
470 select ARC 546 select ARC
471 select ARC64 547 select ARC64
472 select DMA_IP27 548 select DMA_IP27
473 select HW_HAS_PCI 549 select HW_HAS_PCI
474 select PCI_DOMAINS 550 select PCI_DOMAINS
551 select SYS_SUPPORTS_64BIT_KERNEL
475 help 552 help
476 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics 553 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
477 workstations. To compile a Linux kernel that runs on these, say Y 554 workstations. To compile a Linux kernel that runs on these, say Y
@@ -534,7 +611,7 @@ config REPLICATE_EXHANDLERS
534 611
535config SGI_IP32 612config SGI_IP32
536 bool "Support for SGI IP32 (O2) (EXPERIMENTAL)" 613 bool "Support for SGI IP32 (O2) (EXPERIMENTAL)"
537 depends on MIPS64 && EXPERIMENTAL 614 depends on EXPERIMENTAL
538 select ARC 615 select ARC
539 select ARC32 616 select ARC32
540 select BOOT_ELF32 617 select BOOT_ELF32
@@ -544,12 +621,13 @@ config SGI_IP32
544 select HW_HAS_PCI 621 select HW_HAS_PCI
545 select R5000_CPU_SCACHE 622 select R5000_CPU_SCACHE
546 select RM7000_CPU_SCACHE 623 select RM7000_CPU_SCACHE
624 select SYS_SUPPORTS_64BIT_KERNEL
547 help 625 help
548 If you want this kernel to run on SGI O2 workstation, say Y here. 626 If you want this kernel to run on SGI O2 workstation, say Y here.
549 627
550config SOC_AU1X00 628config SOC_AU1X00
551 depends on MIPS32
552 bool "Support for AMD/Alchemy Au1X00 SOCs" 629 bool "Support for AMD/Alchemy Au1X00 SOCs"
630 select SYS_SUPPORTS_32BIT_KERNEL
553 631
554choice 632choice
555 prompt "Au1X00 SOC Type" 633 prompt "Au1X00 SOC Type"
@@ -661,6 +739,8 @@ config SIBYTE_SB1xxx_SOC
661 select BOOT_ELF32 739 select BOOT_ELF32
662 select DMA_COHERENT 740 select DMA_COHERENT
663 select SWAP_IO_SPACE 741 select SWAP_IO_SPACE
742 select SYS_SUPPORTS_32BIT_KERNEL
743 select SYS_SUPPORTS_64BIT_KERNEL
664 744
665choice 745choice
666 prompt "BCM1xxx SOC-based board" 746 prompt "BCM1xxx SOC-based board"
@@ -880,6 +960,8 @@ config SNI_RM200_PCI
880 select HW_HAS_PCI 960 select HW_HAS_PCI
881 select I8259 961 select I8259
882 select ISA 962 select ISA
963 select SYS_SUPPORTS_32BIT_KERNEL
964 select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
883 help 965 help
884 The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens 966 The SNI RM200 PCI was a MIPS-based platform manufactured by Siemens
885 Nixdorf Informationssysteme (SNI), parent company of Pyramid 967 Nixdorf Informationssysteme (SNI), parent company of Pyramid
@@ -888,13 +970,14 @@ config SNI_RM200_PCI
888 970
889config TOSHIBA_RBTX4927 971config TOSHIBA_RBTX4927
890 bool "Support for Toshiba TBTX49[23]7 board" 972 bool "Support for Toshiba TBTX49[23]7 board"
891 depends on MIPS32
892 select DMA_NONCOHERENT 973 select DMA_NONCOHERENT
893 select HAS_TXX9_SERIAL 974 select HAS_TXX9_SERIAL
894 select HW_HAS_PCI 975 select HW_HAS_PCI
895 select I8259 976 select I8259
896 select ISA 977 select ISA
897 select SWAP_IO_SPACE 978 select SWAP_IO_SPACE
979 select SYS_SUPPORTS_32BIT_KERNEL
980 select SYS_SUPPORTS_64BIT_KERNEL
898 help 981 help
899 This Toshiba board is based on the TX4927 processor. Say Y here to 982 This Toshiba board is based on the TX4927 processor. Say Y here to
900 support this machine type 983 support this machine type
@@ -926,13 +1009,21 @@ config ARC
926 depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61 1009 depends on SNI_RM200_PCI || SGI_IP32 || SGI_IP27 || SGI_IP22 || MIPS_MAGNUM_4000 || OLIVETTI_M700 || ACER_PICA_61
927 default y 1010 default y
928 1011
929config DMA_COHERENT 1012config DMA_COHERENT
1013 bool
1014
1015config DMA_IP27
930 bool 1016 bool
931 1017
932config DMA_IP27 1018config DMA_IP32
933 bool 1019 bool
1020 select DMA_NEED_PCI_MAP_STATE
934 1021
935config DMA_NONCOHERENT 1022config DMA_NONCOHERENT
1023 bool
1024 select DMA_NEED_PCI_MAP_STATE
1025
1026config DMA_NEED_PCI_MAP_STATE
936 bool 1027 bool
937 1028
938config EARLY_PRINTK 1029config EARLY_PRINTK
@@ -974,7 +1065,7 @@ config MIPS_DISABLE_OBSOLETE_IDE
974 1065
975config CPU_LITTLE_ENDIAN 1066config CPU_LITTLE_ENDIAN
976 bool "Generate little endian code" 1067 bool "Generate little endian code"
977 default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || NEC_OSPREY || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA 1068 default y if ACER_PICA_61 || CASIO_E55 || DDB5074 || DDB5476 || DDB5477 || MACH_DECSTATION || IBM_WORKPAD || LASAT || MIPS_COBALT || MIPS_ITE8172 || MIPS_IVR || SOC_AU1X00 || OLIVETTI_M700 || SNI_RM200_PCI || VICTOR_MPC30X || ZAO_CAPCELLA
978 default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927 1069 default n if MIPS_EV64120 || MIPS_EV96100 || MOMENCO_OCELOT || MOMENCO_OCELOT_G || SGI_IP22 || SGI_IP27 || SGI_IP32 || TOSHIBA_JMR3927
979 help 1070 help
980 Some MIPS machines can be configured for either little or big endian 1071 Some MIPS machines can be configured for either little or big endian
@@ -1088,49 +1179,9 @@ config ARC32
1088 depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32 1179 depends on MACH_JAZZ || SNI_RM200_PCI || SGI_IP22 || SGI_IP32
1089 default y 1180 default y
1090 1181
1091config FB
1092 bool
1093 depends on MIPS_MAGNUM_4000 || OLIVETTI_M700
1094 default y
1095 ---help---
1096 The frame buffer device provides an abstraction for the graphics
1097 hardware. It represents the frame buffer of some video hardware and
1098 allows application software to access the graphics hardware through
1099 a well-defined interface, so the software doesn't need to know
1100 anything about the low-level (hardware register) stuff.
1101
1102 Frame buffer devices work identically across the different
1103 architectures supported by Linux and make the implementation of
1104 application programs easier and more portable; at this point, an X
1105 server exists which uses the frame buffer device exclusively.
1106 On several non-X86 architectures, the frame buffer device is the
1107 only way to use the graphics hardware.
1108
1109 The device is accessed through special device nodes, usually located
1110 in the /dev directory, i.e. /dev/fb*.
1111
1112 You need an utility program called fbset to make full use of frame
1113 buffer devices. Please read <file:Documentation/fb/framebuffer.txt>
1114 and the Framebuffer-HOWTO at <http://www.tldp.org/docs.html#howto>
1115 for more information.
1116
1117 Say Y here and to the driver for your graphics board below if you
1118 are compiling a kernel for a non-x86 architecture.
1119
1120 If you are compiling for the x86 architecture, you can say Y if you
1121 want to play with it, but it is not essential. Please note that
1122 running graphical applications that directly touch the hardware
1123 (e.g. an accelerated X server) and that are not frame buffer
1124 device-aware may cause unexpected results. If unsure, say N.
1125
1126config HAVE_STD_PC_SERIAL_PORT 1182config HAVE_STD_PC_SERIAL_PORT
1127 bool 1183 bool
1128 1184
1129config VR4181
1130 bool
1131 depends on NEC_OSPREY
1132 default y
1133
1134config ARC_CONSOLE 1185config ARC_CONSOLE
1135 bool "ARC console support" 1186 bool "ARC console support"
1136 depends on SGI_IP22 || SNI_RM200_PCI 1187 depends on SGI_IP22 || SNI_RM200_PCI
@@ -1180,13 +1231,16 @@ choice
1180 1231
1181config CPU_MIPS32 1232config CPU_MIPS32
1182 bool "MIPS32" 1233 bool "MIPS32"
1234 select CPU_SUPPORTS_32BIT_KERNEL
1183 1235
1184config CPU_MIPS64 1236config CPU_MIPS64
1185 bool "MIPS64" 1237 bool "MIPS64"
1238 select CPU_SUPPORTS_32BIT_KERNEL
1239 select CPU_SUPPORTS_64BIT_KERNEL
1186 1240
1187config CPU_R3000 1241config CPU_R3000
1188 bool "R3000" 1242 bool "R3000"
1189 depends on MIPS32 1243 select CPU_SUPPORTS_32BIT_KERNEL
1190 help 1244 help
1191 Please make sure to pick the right CPU type. Linux/MIPS is not 1245 Please make sure to pick the right CPU type. Linux/MIPS is not
1192 designed to be generic, i.e. Kernels compiled for R3000 CPUs will 1246 designed to be generic, i.e. Kernels compiled for R3000 CPUs will
@@ -1197,10 +1251,12 @@ config CPU_R3000
1197 1251
1198config CPU_TX39XX 1252config CPU_TX39XX
1199 bool "R39XX" 1253 bool "R39XX"
1200 depends on MIPS32 1254 select CPU_SUPPORTS_32BIT_KERNEL
1201 1255
1202config CPU_VR41XX 1256config CPU_VR41XX
1203 bool "R41xx" 1257 bool "R41xx"
1258 select CPU_SUPPORTS_32BIT_KERNEL
1259 select CPU_SUPPORTS_64BIT_KERNEL
1204 help 1260 help
1205 The options selects support for the NEC VR41xx series of processors. 1261 The options selects support for the NEC VR41xx series of processors.
1206 Only choose this option if you have one of these processors as a 1262 Only choose this option if you have one of these processors as a
@@ -1209,20 +1265,28 @@ config CPU_VR41XX
1209 1265
1210config CPU_R4300 1266config CPU_R4300
1211 bool "R4300" 1267 bool "R4300"
1268 select CPU_SUPPORTS_32BIT_KERNEL
1269 select CPU_SUPPORTS_64BIT_KERNEL
1212 help 1270 help
1213 MIPS Technologies R4300-series processors. 1271 MIPS Technologies R4300-series processors.
1214 1272
1215config CPU_R4X00 1273config CPU_R4X00
1216 bool "R4x00" 1274 bool "R4x00"
1275 select CPU_SUPPORTS_32BIT_KERNEL
1276 select CPU_SUPPORTS_64BIT_KERNEL
1217 help 1277 help
1218 MIPS Technologies R4000-series processors other than 4300, including 1278 MIPS Technologies R4000-series processors other than 4300, including
1219 the R4000, R4400, R4600, and 4700. 1279 the R4000, R4400, R4600, and 4700.
1220 1280
1221config CPU_TX49XX 1281config CPU_TX49XX
1222 bool "R49XX" 1282 bool "R49XX"
1283 select CPU_SUPPORTS_32BIT_KERNEL
1284 select CPU_SUPPORTS_64BIT_KERNEL
1223 1285
1224config CPU_R5000 1286config CPU_R5000
1225 bool "R5000" 1287 bool "R5000"
1288 select CPU_SUPPORTS_32BIT_KERNEL
1289 select CPU_SUPPORTS_64BIT_KERNEL
1226 help 1290 help
1227 MIPS Technologies R5000-series processors other than the Nevada. 1291 MIPS Technologies R5000-series processors other than the Nevada.
1228 1292
@@ -1231,36 +1295,48 @@ config CPU_R5432
1231 1295
1232config CPU_R6000 1296config CPU_R6000
1233 bool "R6000" 1297 bool "R6000"
1234 depends on MIPS32 && EXPERIMENTAL 1298 depends on EXPERIMENTAL
1299 select CPU_SUPPORTS_32BIT_KERNEL
1235 help 1300 help
1236 MIPS Technologies R6000 and R6000A series processors. Note these 1301 MIPS Technologies R6000 and R6000A series processors. Note these
1237 processors are extremly rare and the support for them is incomplete. 1302 processors are extremly rare and the support for them is incomplete.
1238 1303
1239config CPU_NEVADA 1304config CPU_NEVADA
1240 bool "RM52xx" 1305 bool "RM52xx"
1306 select CPU_SUPPORTS_32BIT_KERNEL
1307 select CPU_SUPPORTS_64BIT_KERNEL
1241 help 1308 help
1242 QED / PMC-Sierra RM52xx-series ("Nevada") processors. 1309 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1243 1310
1244config CPU_R8000 1311config CPU_R8000
1245 bool "R8000" 1312 bool "R8000"
1246 depends on MIPS64 && EXPERIMENTAL 1313 depends on EXPERIMENTAL
1314 select CPU_SUPPORTS_64BIT_KERNEL
1247 help 1315 help
1248 MIPS Technologies R8000 processors. Note these processors are 1316 MIPS Technologies R8000 processors. Note these processors are
1249 uncommon and the support for them is incomplete. 1317 uncommon and the support for them is incomplete.
1250 1318
1251config CPU_R10000 1319config CPU_R10000
1252 bool "R10000" 1320 bool "R10000"
1321 select CPU_SUPPORTS_32BIT_KERNEL
1322 select CPU_SUPPORTS_64BIT_KERNEL
1253 help 1323 help
1254 MIPS Technologies R10000-series processors. 1324 MIPS Technologies R10000-series processors.
1255 1325
1256config CPU_RM7000 1326config CPU_RM7000
1257 bool "RM7000" 1327 bool "RM7000"
1328 select CPU_SUPPORTS_32BIT_KERNEL
1329 select CPU_SUPPORTS_64BIT_KERNEL
1258 1330
1259config CPU_RM9000 1331config CPU_RM9000
1260 bool "RM9000" 1332 bool "RM9000"
1333 select CPU_SUPPORTS_32BIT_KERNEL
1334 select CPU_SUPPORTS_64BIT_KERNEL
1261 1335
1262config CPU_SB1 1336config CPU_SB1
1263 bool "SB1" 1337 bool "SB1"
1338 select CPU_SUPPORTS_32BIT_KERNEL
1339 select CPU_SUPPORTS_64BIT_KERNEL
1264 1340
1265endchoice 1341endchoice
1266 1342
@@ -1356,11 +1432,11 @@ config SB1_PASS_2_1_WORKAROUNDS
1356 1432
1357config 64BIT_PHYS_ADDR 1433config 64BIT_PHYS_ADDR
1358 bool "Support for 64-bit physical address space" 1434 bool "Support for 64-bit physical address space"
1359 depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && MIPS32 1435 depends on (CPU_R4X00 || CPU_R5000 || CPU_RM7000 || CPU_RM9000 || CPU_R10000 || CPU_SB1 || CPU_MIPS32 || CPU_MIPS64) && 32BIT
1360 1436
1361config CPU_ADVANCED 1437config CPU_ADVANCED
1362 bool "Override CPU Options" 1438 bool "Override CPU Options"
1363 depends on MIPS32 1439 depends on 32BIT
1364 help 1440 help
1365 Saying yes here allows you to select support for various features 1441 Saying yes here allows you to select support for various features
1366 your CPU may or may not have. Most people should say N here. 1442 your CPU may or may not have. Most people should say N here.
@@ -1414,7 +1490,7 @@ config CPU_HAS_SYNC
1414# 1490#
1415config HIGHMEM 1491config HIGHMEM
1416 bool "High Memory Support" 1492 bool "High Memory Support"
1417 depends on MIPS32 && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX) 1493 depends on 32BIT && (CPU_R3000 || CPU_SB1 || CPU_R7000 || CPU_RM9000 || CPU_R10000) && !(MACH_DECSTATION || MOMENCO_JAGUAR_ATX)
1418 1494
1419config ARCH_FLATMEM_ENABLE 1495config ARCH_FLATMEM_ENABLE
1420 def_bool y 1496 def_bool y
@@ -1474,7 +1550,7 @@ config RTC_DS1742
1474 1550
1475config MIPS_INSANE_LARGE 1551config MIPS_INSANE_LARGE
1476 bool "Support for large 64-bit configurations" 1552 bool "Support for large 64-bit configurations"
1477 depends on CPU_R10000 && MIPS64 1553 depends on CPU_R10000 && 64BIT
1478 help 1554 help
1479 MIPS R10000 does support a 44 bit / 16TB address space as opposed to 1555 MIPS R10000 does support a 44 bit / 16TB address space as opposed to
1480 previous 64-bit processors which only supported 40 bit / 1TB. If you 1556 previous 64-bit processors which only supported 40 bit / 1TB. If you
@@ -1575,11 +1651,11 @@ source "fs/Kconfig.binfmt"
1575 1651
1576config TRAD_SIGNALS 1652config TRAD_SIGNALS
1577 bool 1653 bool
1578 default y if MIPS32 1654 default y if 32BIT
1579 1655
1580config BUILD_ELF64 1656config BUILD_ELF64
1581 bool "Use 64-bit ELF format for building" 1657 bool "Use 64-bit ELF format for building"
1582 depends on MIPS64 1658 depends on 64BIT
1583 help 1659 help
1584 A 64-bit kernel is usually built using the 64-bit ELF binary object 1660 A 64-bit kernel is usually built using the 64-bit ELF binary object
1585 format as it's one that allows arbitrary 64-bit constructs. For 1661 format as it's one that allows arbitrary 64-bit constructs. For
@@ -1594,11 +1670,11 @@ config BUILD_ELF64
1594 1670
1595config BINFMT_IRIX 1671config BINFMT_IRIX
1596 bool "Include IRIX binary compatibility" 1672 bool "Include IRIX binary compatibility"
1597 depends on !CPU_LITTLE_ENDIAN && MIPS32 && BROKEN 1673 depends on !CPU_LITTLE_ENDIAN && 32BIT && BROKEN
1598 1674
1599config MIPS32_COMPAT 1675config MIPS32_COMPAT
1600 bool "Kernel support for Linux/MIPS 32-bit binary compatibility" 1676 bool "Kernel support for Linux/MIPS 32-bit binary compatibility"
1601 depends on MIPS64 1677 depends on 64BIT
1602 help 1678 help
1603 Select this option if you want Linux/MIPS 32-bit binary 1679 Select this option if you want Linux/MIPS 32-bit binary
1604 compatibility. Since all software available for Linux/MIPS is 1680 compatibility. Since all software available for Linux/MIPS is
@@ -1640,6 +1716,8 @@ config PM
1640 1716
1641endmenu 1717endmenu
1642 1718
1719source "net/Kconfig"
1720
1643source "drivers/Kconfig" 1721source "drivers/Kconfig"
1644 1722
1645source "fs/Kconfig" 1723source "fs/Kconfig"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 26528b600b97..b0fdaee8d8d9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -37,12 +37,12 @@ else
3764bit-emul = elf64btsmip 3764bit-emul = elf64btsmip
38endif 38endif
39 39
40ifdef CONFIG_MIPS32 40ifdef CONFIG_32BIT
41gcc-abi = 32 41gcc-abi = 32
42tool-prefix = $(32bit-tool-prefix) 42tool-prefix = $(32bit-tool-prefix)
43UTS_MACHINE := mips 43UTS_MACHINE := mips
44endif 44endif
45ifdef CONFIG_MIPS64 45ifdef CONFIG_64BIT
46gcc-abi = 64 46gcc-abi = 64
47tool-prefix = $(64bit-tool-prefix) 47tool-prefix = $(64bit-tool-prefix)
48UTS_MACHINE := mips64 48UTS_MACHINE := mips64
@@ -63,7 +63,7 @@ ld-emul = $(32bit-emul)
63vmlinux-32 = vmlinux 63vmlinux-32 = vmlinux
64vmlinux-64 = vmlinux.64 64vmlinux-64 = vmlinux.64
65 65
66cflags-$(CONFIG_MIPS64) += $(call cc-option,-mno-explicit-relocs) 66cflags-$(CONFIG_64BIT) += $(call cc-option,-mno-explicit-relocs)
67endif 67endif
68 68
69# 69#
@@ -177,7 +177,7 @@ cflags-$(CONFIG_CPU_MIPS64) += \
177 177
178cflags-$(CONFIG_CPU_R5000) += \ 178cflags-$(CONFIG_CPU_R5000) += \
179 $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \ 179 $(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \
180 -Wa,--trap 180 -Wa,--trap
181 181
182cflags-$(CONFIG_CPU_R5432) += \ 182cflags-$(CONFIG_CPU_R5432) += \
183 $(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \ 183 $(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \
@@ -423,6 +423,12 @@ core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/
423cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite 423cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite
424load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 424load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000
425 425
426# Qemu simulating MIPS32 4Kc
427#
428core-$(CONFIG_QEMU) += arch/mips/qemu/
429cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu
430load-$(CONFIG_QEMU) += 0xffffffff80010000
431
426# 432#
427# Momentum Ocelot-3 433# Momentum Ocelot-3
428# 434#
@@ -469,13 +475,6 @@ cflags-$(CONFIG_LASAT) += -Iinclude/asm-mips/mach-lasat
469load-$(CONFIG_LASAT) += 0xffffffff80000000 475load-$(CONFIG_LASAT) += 0xffffffff80000000
470 476
471# 477#
472# NEC Osprey (vr4181) board
473#
474core-$(CONFIG_NEC_OSPREY) += arch/mips/vr4181/common/ \
475 arch/mips/vr4181/osprey/
476load-$(CONFIG_NEC_OSPREY) += 0xffffffff80002000
477
478#
479# Common VR41xx 478# Common VR41xx
480# 479#
481core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ 480core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/
@@ -490,13 +489,11 @@ load-$(CONFIG_NEC_CMBVR4133) += 0xffffffff80100000
490# 489#
491# ZAO Networks Capcella (VR4131) 490# ZAO Networks Capcella (VR4131)
492# 491#
493core-$(CONFIG_ZAO_CAPCELLA) += arch/mips/vr41xx/zao-capcella/
494load-$(CONFIG_ZAO_CAPCELLA) += 0xffffffff80000000 492load-$(CONFIG_ZAO_CAPCELLA) += 0xffffffff80000000
495 493
496# 494#
497# Victor MP-C303/304 (VR4122) 495# Victor MP-C303/304 (VR4122)
498# 496#
499core-$(CONFIG_VICTOR_MPC30X) += arch/mips/vr41xx/victor-mpc30x/
500load-$(CONFIG_VICTOR_MPC30X) += 0xffffffff80001000 497load-$(CONFIG_VICTOR_MPC30X) += 0xffffffff80001000
501 498
502# 499#
@@ -512,16 +509,9 @@ core-$(CONFIG_CASIO_E55) += arch/mips/vr41xx/casio-e55/
512load-$(CONFIG_CASIO_E55) += 0xffffffff80004000 509load-$(CONFIG_CASIO_E55) += 0xffffffff80004000
513 510
514# 511#
515# TANBAC TB0226 Mbase (VR4131) 512# TANBAC VR4131 multichip module(TB0225) and TANBAC VR4131DIMM(TB0229) (VR4131)
516#
517core-$(CONFIG_TANBAC_TB0226) += arch/mips/vr41xx/tanbac-tb0226/
518load-$(CONFIG_TANBAC_TB0226) += 0xffffffff80000000
519
520#
521# TANBAC TB0229 VR4131DIMM (VR4131)
522# 513#
523core-$(CONFIG_TANBAC_TB0229) += arch/mips/vr41xx/tanbac-tb0229/ 514load-$(CONFIG_TANBAC_TB022X) += 0xffffffff80000000
524load-$(CONFIG_TANBAC_TB0229) += 0xffffffff80000000
525 515
526# 516#
527# SGI IP22 (Indy/Indigo2) 517# SGI IP22 (Indy/Indigo2)
@@ -534,10 +524,10 @@ load-$(CONFIG_TANBAC_TB0229) += 0xffffffff80000000
534# 524#
535core-$(CONFIG_SGI_IP22) += arch/mips/sgi-ip22/ 525core-$(CONFIG_SGI_IP22) += arch/mips/sgi-ip22/
536cflags-$(CONFIG_SGI_IP22) += -Iinclude/asm-mips/mach-ip22 526cflags-$(CONFIG_SGI_IP22) += -Iinclude/asm-mips/mach-ip22
537ifdef CONFIG_MIPS32 527ifdef CONFIG_32BIT
538load-$(CONFIG_SGI_IP22) += 0xffffffff88002000 528load-$(CONFIG_SGI_IP22) += 0xffffffff88002000
539endif 529endif
540ifdef CONFIG_MIPS64 530ifdef CONFIG_64BIT
541load-$(CONFIG_SGI_IP22) += 0xffffffff88004000 531load-$(CONFIG_SGI_IP22) += 0xffffffff88004000
542endif 532endif
543 533
@@ -642,7 +632,7 @@ load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000
642cflags-y += -Iinclude/asm-mips/mach-generic 632cflags-y += -Iinclude/asm-mips/mach-generic
643drivers-$(CONFIG_PCI) += arch/mips/pci/ 633drivers-$(CONFIG_PCI) += arch/mips/pci/
644 634
645ifdef CONFIG_MIPS32 635ifdef CONFIG_32BIT
646ifdef CONFIG_CPU_LITTLE_ENDIAN 636ifdef CONFIG_CPU_LITTLE_ENDIAN
647JIFFIES = jiffies_64 637JIFFIES = jiffies_64
648else 638else
@@ -674,8 +664,8 @@ CPPFLAGS_vmlinux.lds := \
674head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o 664head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o
675 665
676libs-y += arch/mips/lib/ 666libs-y += arch/mips/lib/
677libs-$(CONFIG_MIPS32) += arch/mips/lib-32/ 667libs-$(CONFIG_32BIT) += arch/mips/lib-32/
678libs-$(CONFIG_MIPS64) += arch/mips/lib-64/ 668libs-$(CONFIG_64BIT) += arch/mips/lib-64/
679 669
680core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ 670core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
681 671
@@ -730,7 +720,7 @@ archclean:
730 @$(MAKE) $(clean)=arch/mips/boot 720 @$(MAKE) $(clean)=arch/mips/boot
731 @$(MAKE) $(clean)=arch/mips/lasat 721 @$(MAKE) $(clean)=arch/mips/lasat
732 722
733# Generate <asm/offset.h 723# Generate <asm/offset.h
734# 724#
735# The default rule is suffering from funny problems on MIPS so we using our 725# The default rule is suffering from funny problems on MIPS so we using our
736# own ... 726# own ...
diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c
index 533721eef6ae..4e5a6e1a9a6e 100644
--- a/arch/mips/au1000/common/pci.c
+++ b/arch/mips/au1000/common/pci.c
@@ -40,14 +40,14 @@
40 40
41/* TBD */ 41/* TBD */
42static struct resource pci_io_resource = { 42static struct resource pci_io_resource = {
43 "pci IO space", 43 "pci IO space",
44 (u32)PCI_IO_START, 44 (u32)PCI_IO_START,
45 (u32)PCI_IO_END, 45 (u32)PCI_IO_END,
46 IORESOURCE_IO 46 IORESOURCE_IO
47}; 47};
48 48
49static struct resource pci_mem_resource = { 49static struct resource pci_mem_resource = {
50 "pci memory space", 50 "pci memory space",
51 (u32)PCI_MEM_START, 51 (u32)PCI_MEM_START,
52 (u32)PCI_MEM_END, 52 (u32)PCI_MEM_END,
53 IORESOURCE_MEM 53 IORESOURCE_MEM
@@ -68,7 +68,7 @@ static unsigned long virt_io_addr;
68static int __init au1x_pci_setup(void) 68static int __init au1x_pci_setup(void)
69{ 69{
70#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 70#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
71 virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, 71 virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
72 Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); 72 Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
73 73
74 if (!virt_io_addr) { 74 if (!virt_io_addr) {
@@ -77,7 +77,7 @@ static int __init au1x_pci_setup(void)
77 } 77 }
78 78
79#ifdef CONFIG_DMA_NONCOHERENT 79#ifdef CONFIG_DMA_NONCOHERENT
80 /* 80 /*
81 * Set the NC bit in controller for Au1500 pre-AC silicon 81 * Set the NC bit in controller for Au1500 pre-AC silicon
82 */ 82 */
83 u32 prid = read_c0_prid(); 83 u32 prid = read_c0_prid();
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index dbc8b1bda963..eff89e109ce6 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -97,7 +97,7 @@ static int __init au1x00_setup(void)
97 argptr = prom_getcmdline(); 97 argptr = prom_getcmdline();
98 strcat(argptr, " console=ttyS0,115200"); 98 strcat(argptr, " console=ttyS0,115200");
99 } 99 }
100#endif 100#endif
101 101
102#ifdef CONFIG_FB_AU1100 102#ifdef CONFIG_FB_AU1100
103 if ((argptr = strstr(argptr, "video=")) == NULL) { 103 if ((argptr = strstr(argptr, "video=")) == NULL) {
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index fe418f1620c3..57675b41480e 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -281,7 +281,7 @@ unsigned long cal_r4koff(void)
281 cpu_speed = count * 2; 281 cpu_speed = count * 2;
282 } 282 }
283#else 283#else
284 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * 284 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
285 AU1000_SRC_CLK; 285 AU1000_SRC_CLK;
286 count = cpu_speed / 2; 286 count = cpu_speed / 2;
287#endif 287#endif
@@ -356,7 +356,7 @@ static unsigned long do_fast_cp0_gettimeoffset(void)
356 : "hi", "lo", GCC_REG_ACCUM); 356 : "hi", "lo", GCC_REG_ACCUM);
357 357
358 /* 358 /*
359 * Due to possible jiffies inconsistencies, we need to check 359 * Due to possible jiffies inconsistencies, we need to check
360 * the result so that we'll get a timer that is monotonic. 360 * the result so that we'll get a timer that is monotonic.
361 */ 361 */
362 if (res >= USECS_PER_JIFFY) 362 if (res >= USECS_PER_JIFFY)
@@ -375,8 +375,8 @@ static unsigned long do_fast_pm_gettimeoffset(void)
375 au_sync(); 375 au_sync();
376 offset = pc0 - last_pc0; 376 offset = pc0 - last_pc0;
377 if (offset > 2*MATCH20_INC) { 377 if (offset > 2*MATCH20_INC) {
378 printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n", 378 printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
379 (unsigned)offset, (unsigned)last_pc0, 379 (unsigned)offset, (unsigned)last_pc0,
380 (unsigned)last_match20, (unsigned)pc0); 380 (unsigned)last_match20, (unsigned)pc0);
381 } 381 }
382 offset = (unsigned long)((offset * 305) / 10); 382 offset = (unsigned long)((offset * 305) / 10);
@@ -394,11 +394,11 @@ void au1xxx_timer_setup(struct irqaction *irq)
394 r4k_offset = cal_r4koff(); 394 r4k_offset = cal_r4koff();
395 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); 395 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
396 396
397 //est_freq = 2*r4k_offset*HZ; 397 //est_freq = 2*r4k_offset*HZ;
398 est_freq = r4k_offset*HZ; 398 est_freq = r4k_offset*HZ;
399 est_freq += 5000; /* round */ 399 est_freq += 5000; /* round */
400 est_freq -= est_freq%10000; 400 est_freq -= est_freq%10000;
401 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 401 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
402 (est_freq%1000000)*100/1000000); 402 (est_freq%1000000)*100/1000000);
403 set_au1x00_speed(est_freq); 403 set_au1x00_speed(est_freq);
404 set_au1x00_lcd_clock(); // program the LCD clock 404 set_au1x00_lcd_clock(); // program the LCD clock
diff --git a/arch/mips/au1000/csb250/board_setup.c b/arch/mips/au1000/csb250/board_setup.c
index 90426eaffb23..1c55c5f59d75 100644
--- a/arch/mips/au1000/csb250/board_setup.c
+++ b/arch/mips/au1000/csb250/board_setup.c
@@ -182,7 +182,7 @@ void __init board_setup(void)
182 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV); 182 au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
183 au_writel(0, Au1500_PCI_MWBASE_REV_CCL); 183 au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
184 au_writel(0x02a00356, Au1500_PCI_STATCMD); 184 au_writel(0x02a00356, Au1500_PCI_STATCMD);
185 au_writel(0x00003c04, Au1500_PCI_HDRTYPE); 185 au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
186 au_writel(0x00000008, Au1500_PCI_MBAR); 186 au_writel(0x00000008, Au1500_PCI_MBAR);
187 au_sync(); 187 au_sync();
188 188
@@ -216,7 +216,7 @@ csb250_pci_idsel(unsigned int devsel, int assert)
216 unsigned int gpio2_pins; 216 unsigned int gpio2_pins;
217 217
218 retval = 1; 218 retval = 1;
219 219
220 /* First, disable both selects, then assert the one requested. 220 /* First, disable both selects, then assert the one requested.
221 */ 221 */
222 au_writel(0xc000c000, GPIO2_OUTPUT); 222 au_writel(0xc000c000, GPIO2_OUTPUT);
diff --git a/arch/mips/au1000/csb250/init.c b/arch/mips/au1000/csb250/init.c
index 4320057fc439..bd99733abc0b 100644
--- a/arch/mips/au1000/csb250/init.c
+++ b/arch/mips/au1000/csb250/init.c
@@ -81,7 +81,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
81 csb_env[0] = env1; 81 csb_env[0] = env1;
82 82
83 mips_machgroup = MACH_GROUP_ALCHEMY; 83 mips_machgroup = MACH_GROUP_ALCHEMY;
84 mips_machtype = MACH_CSB250; 84 mips_machtype = MACH_CSB250;
85 85
86 prom_init_cmdline(); 86 prom_init_cmdline();
87 memsize_str = prom_getenv("memsize"); 87 memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c
index 51eee94a5e82..4b9d5e46edbb 100644
--- a/arch/mips/au1000/db1x00/init.c
+++ b/arch/mips/au1000/db1x00/init.c
@@ -61,7 +61,7 @@ void __init prom_init(void)
61 prom_envp = (char **) fw_arg2; 61 prom_envp = (char **) fw_arg2;
62 62
63 mips_machgroup = MACH_GROUP_ALCHEMY; 63 mips_machgroup = MACH_GROUP_ALCHEMY;
64 mips_machtype = MACH_DB1000; /* set the platform # */ 64 mips_machtype = MACH_DB1000; /* set the platform # */
65 65
66 prom_init_cmdline(); 66 prom_init_cmdline();
67 67
diff --git a/arch/mips/au1000/hydrogen3/init.c b/arch/mips/au1000/hydrogen3/init.c
index eee4adf98711..8cc9879dd582 100644
--- a/arch/mips/au1000/hydrogen3/init.c
+++ b/arch/mips/au1000/hydrogen3/init.c
@@ -63,7 +63,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
63 prom_envp = envp; 63 prom_envp = envp;
64 64
65 mips_machgroup = MACH_GROUP_ALCHEMY; 65 mips_machgroup = MACH_GROUP_ALCHEMY;
66 mips_machtype = MACH_DB1000; /* set the platform # */ 66 mips_machtype = MACH_DB1000; /* set the platform # */
67 prom_init_cmdline(); 67 prom_init_cmdline();
68 68
69 memsize_str = prom_getenv("memsize"); 69 memsize_str = prom_getenv("memsize");
diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/au1000/pb1000/board_setup.c
index 2fa211b69329..0b4807dc9f44 100644
--- a/arch/mips/au1000/pb1000/board_setup.c
+++ b/arch/mips/au1000/pb1000/board_setup.c
@@ -174,7 +174,7 @@ void __init board_setup(void)
174 case 0x02: /* HB */ 174 case 0x02: /* HB */
175 break; 175 break;
176 default: /* HC and newer */ 176 default: /* HC and newer */
177 /* Enable sys bus clock divider when IDLE state or no bus 177 /* Enable sys bus clock divider when IDLE state or no bus
178 activity. */ 178 activity. */
179 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); 179 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
180 break; 180 break;
diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/au1000/xxs1500/board_setup.c
index 9dadc82536f4..1e59433dfd66 100644
--- a/arch/mips/au1000/xxs1500/board_setup.c
+++ b/arch/mips/au1000/xxs1500/board_setup.c
@@ -49,7 +49,7 @@ void board_reset (void)
49void __init board_setup(void) 49void __init board_setup(void)
50{ 50{
51 u32 pin_func; 51 u32 pin_func;
52 52
53 // set multiple use pins (UART3/GPIO) to UART (it's used as UART too) 53 // set multiple use pins (UART3/GPIO) to UART (it's used as UART too)
54 pin_func = au_readl(SYS_PINFUNC) & (u32)(~SYS_PF_UR3); 54 pin_func = au_readl(SYS_PINFUNC) & (u32)(~SYS_PF_UR3);
55 pin_func |= SYS_PF_UR3; 55 pin_func |= SYS_PF_UR3;
@@ -75,11 +75,11 @@ void __init board_setup(void)
75 au_writel(1, GPIO2_ENABLE); 75 au_writel(1, GPIO2_ENABLE);
76 /* gpio2 208/9/10/11 are inputs */ 76 /* gpio2 208/9/10/11 are inputs */
77 au_writel((1<<8) | (1<<9) | (1<<10) | (1<<11), GPIO2_DIR); 77 au_writel((1<<8) | (1<<9) | (1<<10) | (1<<11), GPIO2_DIR);
78 78
79 /* turn off power */ 79 /* turn off power */
80 au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT); 80 au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT);
81#endif 81#endif
82 82
83 83
84#ifdef CONFIG_PCI 84#ifdef CONFIG_PCI
85#if defined(__MIPSEB__) 85#if defined(__MIPSEB__)
diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/au1000/xxs1500/init.c
index 03f755291b51..f1c76533b6fc 100644
--- a/arch/mips/au1000/xxs1500/init.c
+++ b/arch/mips/au1000/xxs1500/init.c
@@ -55,7 +55,7 @@ void __init prom_init(void)
55 prom_envp = (char **) fw_arg2; 55 prom_envp = (char **) fw_arg2;
56 56
57 mips_machgroup = MACH_GROUP_ALCHEMY; 57 mips_machgroup = MACH_GROUP_ALCHEMY;
58 mips_machtype = MACH_XXS1500; /* set the platform # */ 58 mips_machtype = MACH_XXS1500; /* set the platform # */
59 59
60 prom_init_cmdline(); 60 prom_init_cmdline();
61 61
diff --git a/arch/mips/au1000/xxs1500/irqmap.c b/arch/mips/au1000/xxs1500/irqmap.c
index 954800a0ab52..52f2f7daeb05 100644
--- a/arch/mips/au1000/xxs1500/irqmap.c
+++ b/arch/mips/au1000/xxs1500/irqmap.c
@@ -56,7 +56,7 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
56 { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, 56 { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 },
57 57
58 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, 58 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
59 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, 59 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
60 { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, 60 { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 },
61 { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, 61 { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 },
62 { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */ 62 { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */
diff --git a/arch/mips/configs/atlas_defconfig b/arch/mips/configs/atlas_defconfig
index caad7ca27abd..3120a02b8670 100644
--- a/arch/mips/configs/atlas_defconfig
+++ b/arch/mips/configs/atlas_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:00 2005 4# Wed Jan 26 02:49:00 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
88CONFIG_GENERIC_CALIBRATE_DELAY=y 88CONFIG_GENERIC_CALIBRATE_DELAY=y
89CONFIG_HAVE_DEC_LOCK=y 89CONFIG_HAVE_DEC_LOCK=y
90CONFIG_DMA_NONCOHERENT=y 90CONFIG_DMA_NONCOHERENT=y
91CONFIG_DMA_NEED_PCI_MAP_STATE=y
91CONFIG_MIPS_BONITO64=y 92CONFIG_MIPS_BONITO64=y
92CONFIG_MIPS_MSC=y 93CONFIG_MIPS_MSC=y
93# CONFIG_CPU_LITTLE_ENDIAN is not set 94# CONFIG_CPU_LITTLE_ENDIAN is not set
diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig
index 1b7f8a702d06..158e7165f4e3 100644
--- a/arch/mips/configs/capcella_defconfig
+++ b/arch/mips/configs/capcella_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:00 2005 4# Wed Jan 26 02:49:00 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -97,6 +97,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
97CONFIG_GENERIC_CALIBRATE_DELAY=y 97CONFIG_GENERIC_CALIBRATE_DELAY=y
98CONFIG_HAVE_DEC_LOCK=y 98CONFIG_HAVE_DEC_LOCK=y
99CONFIG_DMA_NONCOHERENT=y 99CONFIG_DMA_NONCOHERENT=y
100CONFIG_DMA_NEED_PCI_MAP_STATE=y
100CONFIG_CPU_LITTLE_ENDIAN=y 101CONFIG_CPU_LITTLE_ENDIAN=y
101CONFIG_IRQ_CPU=y 102CONFIG_IRQ_CPU=y
102CONFIG_MIPS_L1_CACHE_SHIFT=5 103CONFIG_MIPS_L1_CACHE_SHIFT=5
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index 8861854561e5..4302c6f914f5 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:00 2005 4# Wed Jan 26 02:49:00 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
82CONFIG_GENERIC_CALIBRATE_DELAY=y 82CONFIG_GENERIC_CALIBRATE_DELAY=y
83CONFIG_HAVE_DEC_LOCK=y 83CONFIG_HAVE_DEC_LOCK=y
84CONFIG_DMA_NONCOHERENT=y 84CONFIG_DMA_NONCOHERENT=y
85CONFIG_DMA_NEED_PCI_MAP_STATE=y
85CONFIG_I8259=y 86CONFIG_I8259=y
86CONFIG_CPU_LITTLE_ENDIAN=y 87CONFIG_CPU_LITTLE_ENDIAN=y
87CONFIG_IRQ_CPU=y 88CONFIG_IRQ_CPU=y
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 19cac1bf4f01..962fc14b58c2 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:01 2005 4# Wed Jan 26 02:49:01 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -104,6 +104,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
104CONFIG_GENERIC_CALIBRATE_DELAY=y 104CONFIG_GENERIC_CALIBRATE_DELAY=y
105CONFIG_HAVE_DEC_LOCK=y 105CONFIG_HAVE_DEC_LOCK=y
106CONFIG_DMA_NONCOHERENT=y 106CONFIG_DMA_NONCOHERENT=y
107CONFIG_DMA_NEED_PCI_MAP_STATE=y
107CONFIG_CPU_LITTLE_ENDIAN=y 108CONFIG_CPU_LITTLE_ENDIAN=y
108CONFIG_MIPS_L1_CACHE_SHIFT=5 109CONFIG_MIPS_L1_CACHE_SHIFT=5
109 110
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index 035ac95d197e..6a528d479d70 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:01 2005 4# Wed Jan 26 02:49:01 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -104,6 +104,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
104CONFIG_GENERIC_CALIBRATE_DELAY=y 104CONFIG_GENERIC_CALIBRATE_DELAY=y
105CONFIG_HAVE_DEC_LOCK=y 105CONFIG_HAVE_DEC_LOCK=y
106CONFIG_DMA_NONCOHERENT=y 106CONFIG_DMA_NONCOHERENT=y
107CONFIG_DMA_NEED_PCI_MAP_STATE=y
107CONFIG_CPU_LITTLE_ENDIAN=y 108CONFIG_CPU_LITTLE_ENDIAN=y
108CONFIG_MIPS_L1_CACHE_SHIFT=5 109CONFIG_MIPS_L1_CACHE_SHIFT=5
109 110
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index c38c4ed18fe7..fed6f2fab48b 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:01 2005 4# Wed Jan 26 02:49:01 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index ee81309ae3a5..178c0ad1af75 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:02 2005 4# Wed Jan 26 02:49:02 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
diff --git a/arch/mips/configs/ddb5476_defconfig b/arch/mips/configs/ddb5476_defconfig
index d43ed57c4b4e..70addc73f699 100644
--- a/arch/mips/configs/ddb5476_defconfig
+++ b/arch/mips/configs/ddb5476_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:02 2005 4# Wed Jan 26 02:49:02 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
82CONFIG_GENERIC_CALIBRATE_DELAY=y 82CONFIG_GENERIC_CALIBRATE_DELAY=y
83CONFIG_HAVE_DEC_LOCK=y 83CONFIG_HAVE_DEC_LOCK=y
84CONFIG_DMA_NONCOHERENT=y 84CONFIG_DMA_NONCOHERENT=y
85CONFIG_DMA_NEED_PCI_MAP_STATE=y
85CONFIG_I8259=y 86CONFIG_I8259=y
86CONFIG_CPU_LITTLE_ENDIAN=y 87CONFIG_CPU_LITTLE_ENDIAN=y
87CONFIG_IRQ_CPU=y 88CONFIG_IRQ_CPU=y
diff --git a/arch/mips/configs/ddb5477_defconfig b/arch/mips/configs/ddb5477_defconfig
index 5a032cdefd63..60292808b384 100644
--- a/arch/mips/configs/ddb5477_defconfig
+++ b/arch/mips/configs/ddb5477_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:02 2005 4# Wed Jan 26 02:49:02 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -83,6 +83,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
83CONFIG_GENERIC_CALIBRATE_DELAY=y 83CONFIG_GENERIC_CALIBRATE_DELAY=y
84CONFIG_HAVE_DEC_LOCK=y 84CONFIG_HAVE_DEC_LOCK=y
85CONFIG_DMA_NONCOHERENT=y 85CONFIG_DMA_NONCOHERENT=y
86CONFIG_DMA_NEED_PCI_MAP_STATE=y
86CONFIG_I8259=y 87CONFIG_I8259=y
87CONFIG_CPU_LITTLE_ENDIAN=y 88CONFIG_CPU_LITTLE_ENDIAN=y
88CONFIG_IRQ_CPU=y 89CONFIG_IRQ_CPU=y
diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig
index 32ada79da9d8..66ec1f41d122 100644
--- a/arch/mips/configs/decstation_defconfig
+++ b/arch/mips/configs/decstation_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:03 2005 4# Wed Jan 26 02:49:03 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
88CONFIG_GENERIC_CALIBRATE_DELAY=y 88CONFIG_GENERIC_CALIBRATE_DELAY=y
89CONFIG_HAVE_DEC_LOCK=y 89CONFIG_HAVE_DEC_LOCK=y
90CONFIG_DMA_NONCOHERENT=y 90CONFIG_DMA_NONCOHERENT=y
91CONFIG_DMA_NEED_PCI_MAP_STATE=y
91CONFIG_EARLY_PRINTK=y 92CONFIG_EARLY_PRINTK=y
92CONFIG_CPU_LITTLE_ENDIAN=y 93CONFIG_CPU_LITTLE_ENDIAN=y
93CONFIG_IRQ_CPU=y 94CONFIG_IRQ_CPU=y
diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig
index 52074a2085fb..ba2ec01defb1 100644
--- a/arch/mips/configs/e55_defconfig
+++ b/arch/mips/configs/e55_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:03 2005 4# Wed Jan 26 02:49:03 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -96,6 +96,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
96CONFIG_GENERIC_CALIBRATE_DELAY=y 96CONFIG_GENERIC_CALIBRATE_DELAY=y
97CONFIG_HAVE_DEC_LOCK=y 97CONFIG_HAVE_DEC_LOCK=y
98CONFIG_DMA_NONCOHERENT=y 98CONFIG_DMA_NONCOHERENT=y
99CONFIG_DMA_NEED_PCI_MAP_STATE=y
99CONFIG_CPU_LITTLE_ENDIAN=y 100CONFIG_CPU_LITTLE_ENDIAN=y
100CONFIG_IRQ_CPU=y 101CONFIG_IRQ_CPU=y
101CONFIG_MIPS_L1_CACHE_SHIFT=5 102CONFIG_MIPS_L1_CACHE_SHIFT=5
diff --git a/arch/mips/configs/ev64120_defconfig b/arch/mips/configs/ev64120_defconfig
index 360e842fd4be..17e87f70f602 100644
--- a/arch/mips/configs/ev64120_defconfig
+++ b/arch/mips/configs/ev64120_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:03 2005 4# Wed Jan 26 02:49:03 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -89,6 +89,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
89CONFIG_GENERIC_CALIBRATE_DELAY=y 89CONFIG_GENERIC_CALIBRATE_DELAY=y
90CONFIG_HAVE_DEC_LOCK=y 90CONFIG_HAVE_DEC_LOCK=y
91CONFIG_DMA_NONCOHERENT=y 91CONFIG_DMA_NONCOHERENT=y
92CONFIG_DMA_NEED_PCI_MAP_STATE=y
92# CONFIG_CPU_LITTLE_ENDIAN is not set 93# CONFIG_CPU_LITTLE_ENDIAN is not set
93CONFIG_MIPS_GT64120=y 94CONFIG_MIPS_GT64120=y
94# CONFIG_SYSCLK_75 is not set 95# CONFIG_SYSCLK_75 is not set
diff --git a/arch/mips/configs/ev96100_defconfig b/arch/mips/configs/ev96100_defconfig
index 657a9508d31a..9da4140eae00 100644
--- a/arch/mips/configs/ev96100_defconfig
+++ b/arch/mips/configs/ev96100_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:03 2005 4# Wed Jan 26 02:49:03 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
88CONFIG_GENERIC_CALIBRATE_DELAY=y 88CONFIG_GENERIC_CALIBRATE_DELAY=y
89CONFIG_HAVE_DEC_LOCK=y 89CONFIG_HAVE_DEC_LOCK=y
90CONFIG_DMA_NONCOHERENT=y 90CONFIG_DMA_NONCOHERENT=y
91CONFIG_DMA_NEED_PCI_MAP_STATE=y
91# CONFIG_CPU_LITTLE_ENDIAN is not set 92# CONFIG_CPU_LITTLE_ENDIAN is not set
92CONFIG_IRQ_CPU=y 93CONFIG_IRQ_CPU=y
93CONFIG_MIPS_GT64120=y 94CONFIG_MIPS_GT64120=y
diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig
index 3fb102e6a7f7..17fa5c4e3ad1 100644
--- a/arch/mips/configs/ip22_defconfig
+++ b/arch/mips/configs/ip22_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:04 2005 4# Wed Jan 26 02:49:04 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -90,6 +90,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y
90CONFIG_HAVE_DEC_LOCK=y 90CONFIG_HAVE_DEC_LOCK=y
91CONFIG_ARC=y 91CONFIG_ARC=y
92CONFIG_DMA_NONCOHERENT=y 92CONFIG_DMA_NONCOHERENT=y
93CONFIG_DMA_NEED_PCI_MAP_STATE=y
93# CONFIG_CPU_LITTLE_ENDIAN is not set 94# CONFIG_CPU_LITTLE_ENDIAN is not set
94CONFIG_IRQ_CPU=y 95CONFIG_IRQ_CPU=y
95CONFIG_SWAP_IO_SPACE=y 96CONFIG_SWAP_IO_SPACE=y
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index b5bab3a42fc4..b2a67da1e031 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -4,7 +4,7 @@
4# Wed Jan 26 02:49:04 2005 4# Wed Jan 26 02:49:04 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7CONFIG_MIPS64=y 7CONFIG_64BIT=y
8CONFIG_64BIT=y 8CONFIG_64BIT=y
9 9
10# 10#
diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig
index bdf1415475ff..b26e1173365d 100644
--- a/arch/mips/configs/ip32_defconfig
+++ b/arch/mips/configs/ip32_defconfig
@@ -4,7 +4,7 @@
4# Wed Jan 26 02:49:04 2005 4# Wed Jan 26 02:49:04 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7CONFIG_MIPS64=y 7CONFIG_64BIT=y
8CONFIG_64BIT=y 8CONFIG_64BIT=y
9 9
10# 10#
@@ -84,6 +84,7 @@ CONFIG_ARC=y
84CONFIG_DMA_IP32=y 84CONFIG_DMA_IP32=y
85CONFIG_OWN_DMA=y 85CONFIG_OWN_DMA=y
86CONFIG_DMA_NONCOHERENT=y 86CONFIG_DMA_NONCOHERENT=y
87CONFIG_DMA_NEED_PCI_MAP_STATE=y
87# CONFIG_CPU_LITTLE_ENDIAN is not set 88# CONFIG_CPU_LITTLE_ENDIAN is not set
88CONFIG_ARC32=y 89CONFIG_ARC32=y
89CONFIG_BOOT_ELF32=y 90CONFIG_BOOT_ELF32=y
diff --git a/arch/mips/configs/it8172_defconfig b/arch/mips/configs/it8172_defconfig
index 1ca7746388f0..08bd3ad64761 100644
--- a/arch/mips/configs/it8172_defconfig
+++ b/arch/mips/configs/it8172_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:05 2005 4# Wed Jan 26 02:49:05 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -90,6 +90,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
90CONFIG_GENERIC_CALIBRATE_DELAY=y 90CONFIG_GENERIC_CALIBRATE_DELAY=y
91CONFIG_HAVE_DEC_LOCK=y 91CONFIG_HAVE_DEC_LOCK=y
92CONFIG_DMA_NONCOHERENT=y 92CONFIG_DMA_NONCOHERENT=y
93CONFIG_DMA_NEED_PCI_MAP_STATE=y
93CONFIG_CPU_LITTLE_ENDIAN=y 94CONFIG_CPU_LITTLE_ENDIAN=y
94CONFIG_ITE_BOARD_GEN=y 95CONFIG_ITE_BOARD_GEN=y
95CONFIG_IT8172_CIR=y 96CONFIG_IT8172_CIR=y
diff --git a/arch/mips/configs/ivr_defconfig b/arch/mips/configs/ivr_defconfig
index c6eef708be1e..583ef5c5b1cd 100644
--- a/arch/mips/configs/ivr_defconfig
+++ b/arch/mips/configs/ivr_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:05 2005 4# Wed Jan 26 02:49:05 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -89,6 +89,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
89CONFIG_GENERIC_CALIBRATE_DELAY=y 89CONFIG_GENERIC_CALIBRATE_DELAY=y
90CONFIG_HAVE_DEC_LOCK=y 90CONFIG_HAVE_DEC_LOCK=y
91CONFIG_DMA_NONCOHERENT=y 91CONFIG_DMA_NONCOHERENT=y
92CONFIG_DMA_NEED_PCI_MAP_STATE=y
92CONFIG_CPU_LITTLE_ENDIAN=y 93CONFIG_CPU_LITTLE_ENDIAN=y
93CONFIG_ITE_BOARD_GEN=y 94CONFIG_ITE_BOARD_GEN=y
94CONFIG_IT8172_CIR=y 95CONFIG_IT8172_CIR=y
diff --git a/arch/mips/configs/jaguar-atx_defconfig b/arch/mips/configs/jaguar-atx_defconfig
index 757c4e88cc00..8abb5a0c6c12 100644
--- a/arch/mips/configs/jaguar-atx_defconfig
+++ b/arch/mips/configs/jaguar-atx_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:05 2005 4# Wed Jan 26 02:49:05 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -81,6 +81,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
81CONFIG_GENERIC_CALIBRATE_DELAY=y 81CONFIG_GENERIC_CALIBRATE_DELAY=y
82CONFIG_HAVE_DEC_LOCK=y 82CONFIG_HAVE_DEC_LOCK=y
83CONFIG_DMA_NONCOHERENT=y 83CONFIG_DMA_NONCOHERENT=y
84CONFIG_DMA_NEED_PCI_MAP_STATE=y
84CONFIG_LIMITED_DMA=y 85CONFIG_LIMITED_DMA=y
85# CONFIG_CPU_LITTLE_ENDIAN is not set 86# CONFIG_CPU_LITTLE_ENDIAN is not set
86CONFIG_IRQ_CPU=y 87CONFIG_IRQ_CPU=y
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig
index e5a613906554..da5d9ee2ecce 100644
--- a/arch/mips/configs/jmr3927_defconfig
+++ b/arch/mips/configs/jmr3927_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:06 2005 4# Wed Jan 26 02:49:06 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
82CONFIG_GENERIC_CALIBRATE_DELAY=y 82CONFIG_GENERIC_CALIBRATE_DELAY=y
83CONFIG_HAVE_DEC_LOCK=y 83CONFIG_HAVE_DEC_LOCK=y
84CONFIG_DMA_NONCOHERENT=y 84CONFIG_DMA_NONCOHERENT=y
85CONFIG_DMA_NEED_PCI_MAP_STATE=y
85# CONFIG_CPU_LITTLE_ENDIAN is not set 86# CONFIG_CPU_LITTLE_ENDIAN is not set
86CONFIG_MIPS_TX3927=y 87CONFIG_MIPS_TX3927=y
87CONFIG_SWAP_IO_SPACE=y 88CONFIG_SWAP_IO_SPACE=y
diff --git a/arch/mips/configs/lasat200_defconfig b/arch/mips/configs/lasat200_defconfig
index 1e7697834e90..8d600ae890f4 100644
--- a/arch/mips/configs/lasat200_defconfig
+++ b/arch/mips/configs/lasat200_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:06 2005 4# Wed Jan 26 02:49:06 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -92,6 +92,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
92CONFIG_GENERIC_CALIBRATE_DELAY=y 92CONFIG_GENERIC_CALIBRATE_DELAY=y
93CONFIG_HAVE_DEC_LOCK=y 93CONFIG_HAVE_DEC_LOCK=y
94CONFIG_DMA_NONCOHERENT=y 94CONFIG_DMA_NONCOHERENT=y
95CONFIG_DMA_NEED_PCI_MAP_STATE=y
95CONFIG_MIPS_NILE4=y 96CONFIG_MIPS_NILE4=y
96CONFIG_CPU_LITTLE_ENDIAN=y 97CONFIG_CPU_LITTLE_ENDIAN=y
97CONFIG_MIPS_GT64120=y 98CONFIG_MIPS_GT64120=y
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 61fb9fb97e6e..79519ac5af4a 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:53:14 2005 4# Wed Jan 26 02:53:14 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -88,6 +88,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
88CONFIG_GENERIC_CALIBRATE_DELAY=y 88CONFIG_GENERIC_CALIBRATE_DELAY=y
89CONFIG_HAVE_DEC_LOCK=y 89CONFIG_HAVE_DEC_LOCK=y
90CONFIG_DMA_NONCOHERENT=y 90CONFIG_DMA_NONCOHERENT=y
91CONFIG_DMA_NEED_PCI_MAP_STATE=y
91CONFIG_GENERIC_ISA_DMA=y 92CONFIG_GENERIC_ISA_DMA=y
92CONFIG_I8259=y 93CONFIG_I8259=y
93CONFIG_MIPS_BONITO64=y 94CONFIG_MIPS_BONITO64=y
diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig
index 31b8f2ad7338..0fea57ef18f2 100644
--- a/arch/mips/configs/mpc30x_defconfig
+++ b/arch/mips/configs/mpc30x_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:07 2005 4# Wed Jan 26 02:49:07 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -97,6 +97,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
97CONFIG_GENERIC_CALIBRATE_DELAY=y 97CONFIG_GENERIC_CALIBRATE_DELAY=y
98CONFIG_HAVE_DEC_LOCK=y 98CONFIG_HAVE_DEC_LOCK=y
99CONFIG_DMA_NONCOHERENT=y 99CONFIG_DMA_NONCOHERENT=y
100CONFIG_DMA_NEED_PCI_MAP_STATE=y
100CONFIG_CPU_LITTLE_ENDIAN=y 101CONFIG_CPU_LITTLE_ENDIAN=y
101CONFIG_IRQ_CPU=y 102CONFIG_IRQ_CPU=y
102CONFIG_MIPS_L1_CACHE_SHIFT=5 103CONFIG_MIPS_L1_CACHE_SHIFT=5
diff --git a/arch/mips/configs/ocelot_3_defconfig b/arch/mips/configs/ocelot_3_defconfig
index 2cce682fffcf..b4cf97a732bc 100644
--- a/arch/mips/configs/ocelot_3_defconfig
+++ b/arch/mips/configs/ocelot_3_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:07 2005 4# Wed Jan 26 02:49:07 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -89,6 +89,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
89CONFIG_GENERIC_CALIBRATE_DELAY=y 89CONFIG_GENERIC_CALIBRATE_DELAY=y
90CONFIG_HAVE_DEC_LOCK=y 90CONFIG_HAVE_DEC_LOCK=y
91CONFIG_DMA_NONCOHERENT=y 91CONFIG_DMA_NONCOHERENT=y
92CONFIG_DMA_NEED_PCI_MAP_STATE=y
92# CONFIG_CPU_LITTLE_ENDIAN is not set 93# CONFIG_CPU_LITTLE_ENDIAN is not set
93CONFIG_IRQ_CPU=y 94CONFIG_IRQ_CPU=y
94CONFIG_IRQ_CPU_RM7K=y 95CONFIG_IRQ_CPU_RM7K=y
diff --git a/arch/mips/configs/ocelot_c_defconfig b/arch/mips/configs/ocelot_c_defconfig
index 0cbf48a62e02..a38903db85a0 100644
--- a/arch/mips/configs/ocelot_c_defconfig
+++ b/arch/mips/configs/ocelot_c_defconfig
@@ -4,7 +4,7 @@
4# Wed Jan 26 02:49:07 2005 4# Wed Jan 26 02:49:07 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7CONFIG_MIPS64=y 7CONFIG_64BIT=y
8CONFIG_64BIT=y 8CONFIG_64BIT=y
9 9
10# 10#
@@ -80,6 +80,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
80CONFIG_GENERIC_CALIBRATE_DELAY=y 80CONFIG_GENERIC_CALIBRATE_DELAY=y
81CONFIG_HAVE_DEC_LOCK=y 81CONFIG_HAVE_DEC_LOCK=y
82CONFIG_DMA_NONCOHERENT=y 82CONFIG_DMA_NONCOHERENT=y
83CONFIG_DMA_NEED_PCI_MAP_STATE=y
83# CONFIG_CPU_LITTLE_ENDIAN is not set 84# CONFIG_CPU_LITTLE_ENDIAN is not set
84CONFIG_IRQ_CPU=y 85CONFIG_IRQ_CPU=y
85CONFIG_IRQ_MV64340=y 86CONFIG_IRQ_MV64340=y
diff --git a/arch/mips/configs/ocelot_defconfig b/arch/mips/configs/ocelot_defconfig
index 4043950d360a..920d59b56a4e 100644
--- a/arch/mips/configs/ocelot_defconfig
+++ b/arch/mips/configs/ocelot_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:08 2005 4# Wed Jan 26 02:49:08 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -82,6 +82,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
82CONFIG_GENERIC_CALIBRATE_DELAY=y 82CONFIG_GENERIC_CALIBRATE_DELAY=y
83CONFIG_HAVE_DEC_LOCK=y 83CONFIG_HAVE_DEC_LOCK=y
84CONFIG_DMA_NONCOHERENT=y 84CONFIG_DMA_NONCOHERENT=y
85CONFIG_DMA_NEED_PCI_MAP_STATE=y
85# CONFIG_CPU_LITTLE_ENDIAN is not set 86# CONFIG_CPU_LITTLE_ENDIAN is not set
86CONFIG_IRQ_CPU=y 87CONFIG_IRQ_CPU=y
87CONFIG_IRQ_CPU_RM7K=y 88CONFIG_IRQ_CPU_RM7K=y
diff --git a/arch/mips/configs/ocelot_g_defconfig b/arch/mips/configs/ocelot_g_defconfig
index 3870af4537ad..ef5ea50893d1 100644
--- a/arch/mips/configs/ocelot_g_defconfig
+++ b/arch/mips/configs/ocelot_g_defconfig
@@ -4,7 +4,7 @@
4# Wed Jan 26 02:49:08 2005 4# Wed Jan 26 02:49:08 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7CONFIG_MIPS64=y 7CONFIG_64BIT=y
8CONFIG_64BIT=y 8CONFIG_64BIT=y
9 9
10# 10#
@@ -80,6 +80,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
80CONFIG_GENERIC_CALIBRATE_DELAY=y 80CONFIG_GENERIC_CALIBRATE_DELAY=y
81CONFIG_HAVE_DEC_LOCK=y 81CONFIG_HAVE_DEC_LOCK=y
82CONFIG_DMA_NONCOHERENT=y 82CONFIG_DMA_NONCOHERENT=y
83CONFIG_DMA_NEED_PCI_MAP_STATE=y
83# CONFIG_CPU_LITTLE_ENDIAN is not set 84# CONFIG_CPU_LITTLE_ENDIAN is not set
84CONFIG_IRQ_CPU=y 85CONFIG_IRQ_CPU=y
85CONFIG_IRQ_CPU_RM7K=y 86CONFIG_IRQ_CPU_RM7K=y
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index 6cdabd550300..813e3a8b480b 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:08 2005 4# Wed Jan 26 02:49:08 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -104,6 +104,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
104CONFIG_GENERIC_CALIBRATE_DELAY=y 104CONFIG_GENERIC_CALIBRATE_DELAY=y
105CONFIG_HAVE_DEC_LOCK=y 105CONFIG_HAVE_DEC_LOCK=y
106CONFIG_DMA_NONCOHERENT=y 106CONFIG_DMA_NONCOHERENT=y
107CONFIG_DMA_NEED_PCI_MAP_STATE=y
107CONFIG_CPU_LITTLE_ENDIAN=y 108CONFIG_CPU_LITTLE_ENDIAN=y
108CONFIG_SWAP_IO_SPACE=y 109CONFIG_SWAP_IO_SPACE=y
109# CONFIG_AU1X00_USB_DEVICE is not set 110# CONFIG_AU1X00_USB_DEVICE is not set
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 2aebbd2e82b3..49e528340a39 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:09 2005 4# Wed Jan 26 02:49:09 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 9e21edc28280..8e426776c098 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:09 2005 4# Wed Jan 26 02:49:09 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
diff --git a/arch/mips/configs/osprey_defconfig b/arch/mips/configs/qemu_defconfig
index 989cb9e7ae83..b6568e421b99 100644
--- a/arch/mips/configs/osprey_defconfig
+++ b/arch/mips/configs/qemu_defconfig
@@ -1,108 +1,133 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.11-rc2 3# Linux kernel version: 2.6.13-rc6
4# Wed Jan 26 02:49:08 2005 4# Mon Aug 8 11:49:54 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set
9CONFIG_MIPS32=y
10 7
11# 8#
12# Code maturity level options 9# Code maturity level options
13# 10#
14CONFIG_EXPERIMENTAL=y 11# CONFIG_EXPERIMENTAL is not set
15CONFIG_CLEAN_COMPILE=y 12CONFIG_CLEAN_COMPILE=y
16CONFIG_BROKEN_ON_SMP=y 13CONFIG_BROKEN_ON_SMP=y
14CONFIG_INIT_ENV_ARG_LIMIT=32
17 15
18# 16#
19# General setup 17# General setup
20# 18#
21CONFIG_LOCALVERSION="" 19CONFIG_LOCALVERSION=""
22CONFIG_SWAP=y 20# CONFIG_SWAP is not set
23CONFIG_SYSVIPC=y 21# CONFIG_SYSVIPC is not set
24# CONFIG_POSIX_MQUEUE is not set
25# CONFIG_BSD_PROCESS_ACCT is not set 22# CONFIG_BSD_PROCESS_ACCT is not set
26CONFIG_SYSCTL=y 23# CONFIG_SYSCTL is not set
27# CONFIG_AUDIT is not set 24# CONFIG_AUDIT is not set
28CONFIG_LOG_BUF_SHIFT=14
29# CONFIG_HOTPLUG is not set 25# CONFIG_HOTPLUG is not set
30CONFIG_KOBJECT_UEVENT=y 26CONFIG_KOBJECT_UEVENT=y
31# CONFIG_IKCONFIG is not set 27# CONFIG_IKCONFIG is not set
32CONFIG_EMBEDDED=y 28CONFIG_EMBEDDED=y
33CONFIG_KALLSYMS=y 29CONFIG_KALLSYMS=y
34# CONFIG_KALLSYMS_EXTRA_PASS is not set 30# CONFIG_KALLSYMS_EXTRA_PASS is not set
35CONFIG_FUTEX=y 31CONFIG_PRINTK=y
36CONFIG_EPOLL=y 32# CONFIG_BUG is not set
33# CONFIG_BASE_FULL is not set
34# CONFIG_FUTEX is not set
35# CONFIG_EPOLL is not set
37# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 36# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
38CONFIG_SHMEM=y 37# CONFIG_SHMEM is not set
39CONFIG_CC_ALIGN_FUNCTIONS=0 38CONFIG_CC_ALIGN_FUNCTIONS=0
40CONFIG_CC_ALIGN_LABELS=0 39CONFIG_CC_ALIGN_LABELS=0
41CONFIG_CC_ALIGN_LOOPS=0 40CONFIG_CC_ALIGN_LOOPS=0
42CONFIG_CC_ALIGN_JUMPS=0 41CONFIG_CC_ALIGN_JUMPS=0
43# CONFIG_TINY_SHMEM is not set 42CONFIG_TINY_SHMEM=y
43CONFIG_BASE_SMALL=1
44 44
45# 45#
46# Loadable module support 46# Loadable module support
47# 47#
48CONFIG_MODULES=y 48# CONFIG_MODULES is not set
49CONFIG_MODULE_UNLOAD=y
50# CONFIG_MODULE_FORCE_UNLOAD is not set
51CONFIG_OBSOLETE_MODPARM=y
52CONFIG_MODVERSIONS=y
53CONFIG_MODULE_SRCVERSION_ALL=y
54CONFIG_KMOD=y
55 49
56# 50#
57# Machine selection 51# Machine selection
58# 52#
59# CONFIG_MACH_JAZZ is not set 53# CONFIG_MIPS_MTX1 is not set
60# CONFIG_MACH_VR41XX is not set 54# CONFIG_MIPS_BOSPORUS is not set
61# CONFIG_TOSHIBA_JMR3927 is not set 55# CONFIG_MIPS_PB1000 is not set
56# CONFIG_MIPS_PB1100 is not set
57# CONFIG_MIPS_PB1500 is not set
58# CONFIG_MIPS_PB1550 is not set
59# CONFIG_MIPS_PB1200 is not set
60# CONFIG_MIPS_DB1000 is not set
61# CONFIG_MIPS_DB1100 is not set
62# CONFIG_MIPS_DB1500 is not set
63# CONFIG_MIPS_DB1550 is not set
64# CONFIG_MIPS_DB1200 is not set
65# CONFIG_MIPS_MIRAGE is not set
62# CONFIG_MIPS_COBALT is not set 66# CONFIG_MIPS_COBALT is not set
63# CONFIG_MACH_DECSTATION is not set 67# CONFIG_MACH_DECSTATION is not set
64# CONFIG_MIPS_EV64120 is not set 68# CONFIG_MIPS_EV64120 is not set
65# CONFIG_MIPS_EV96100 is not set 69# CONFIG_MIPS_EV96100 is not set
66# CONFIG_MIPS_IVR is not set 70# CONFIG_MIPS_IVR is not set
67# CONFIG_LASAT is not set
68# CONFIG_MIPS_ITE8172 is not set 71# CONFIG_MIPS_ITE8172 is not set
72# CONFIG_MACH_JAZZ is not set
73# CONFIG_LASAT is not set
69# CONFIG_MIPS_ATLAS is not set 74# CONFIG_MIPS_ATLAS is not set
70# CONFIG_MIPS_MALTA is not set 75# CONFIG_MIPS_MALTA is not set
71# CONFIG_MIPS_SEAD is not set 76# CONFIG_MIPS_SEAD is not set
77# CONFIG_MOMENCO_JAGUAR_ATX is not set
72# CONFIG_MOMENCO_OCELOT is not set 78# CONFIG_MOMENCO_OCELOT is not set
73# CONFIG_MOMENCO_OCELOT_G is not set
74# CONFIG_MOMENCO_OCELOT_C is not set
75# CONFIG_MOMENCO_OCELOT_3 is not set 79# CONFIG_MOMENCO_OCELOT_3 is not set
76# CONFIG_MOMENCO_JAGUAR_ATX is not set 80# CONFIG_MOMENCO_OCELOT_C is not set
77# CONFIG_PMC_YOSEMITE is not set 81# CONFIG_MOMENCO_OCELOT_G is not set
82# CONFIG_MIPS_XXS1500 is not set
83# CONFIG_PNX8550_V2PCI is not set
84# CONFIG_PNX8550_JBS is not set
78# CONFIG_DDB5074 is not set 85# CONFIG_DDB5074 is not set
79# CONFIG_DDB5476 is not set 86# CONFIG_DDB5476 is not set
80# CONFIG_DDB5477 is not set 87# CONFIG_DDB5477 is not set
81CONFIG_NEC_OSPREY=y 88# CONFIG_MACH_VR41XX is not set
89# CONFIG_PMC_YOSEMITE is not set
90CONFIG_QEMU=y
82# CONFIG_SGI_IP22 is not set 91# CONFIG_SGI_IP22 is not set
83# CONFIG_SOC_AU1X00 is not set 92# CONFIG_SGI_IP27 is not set
84# CONFIG_SIBYTE_SB1xxx_SOC is not set 93# CONFIG_SGI_IP32 is not set
94# CONFIG_SIBYTE_SWARM is not set
95# CONFIG_SIBYTE_SENTOSA is not set
96# CONFIG_SIBYTE_RHONE is not set
97# CONFIG_SIBYTE_CARMEL is not set
98# CONFIG_SIBYTE_PTSWARM is not set
99# CONFIG_SIBYTE_LITTLESUR is not set
100# CONFIG_SIBYTE_CRHINE is not set
101# CONFIG_SIBYTE_CRHONE is not set
85# CONFIG_SNI_RM200_PCI is not set 102# CONFIG_SNI_RM200_PCI is not set
103# CONFIG_TOSHIBA_JMR3927 is not set
86# CONFIG_TOSHIBA_RBTX4927 is not set 104# CONFIG_TOSHIBA_RBTX4927 is not set
105# CONFIG_TOSHIBA_RBTX4938 is not set
87CONFIG_RWSEM_GENERIC_SPINLOCK=y 106CONFIG_RWSEM_GENERIC_SPINLOCK=y
88CONFIG_GENERIC_CALIBRATE_DELAY=y 107CONFIG_GENERIC_CALIBRATE_DELAY=y
89CONFIG_HAVE_DEC_LOCK=y 108CONFIG_HAVE_DEC_LOCK=y
90CONFIG_DMA_NONCOHERENT=y 109CONFIG_DMA_COHERENT=y
91CONFIG_CPU_LITTLE_ENDIAN=y 110CONFIG_GENERIC_ISA_DMA=y
92CONFIG_IRQ_CPU=y 111CONFIG_I8259=y
112CONFIG_CPU_BIG_ENDIAN=y
113# CONFIG_CPU_LITTLE_ENDIAN is not set
114CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
115CONFIG_SWAP_IO_SPACE=y
93CONFIG_MIPS_L1_CACHE_SHIFT=5 116CONFIG_MIPS_L1_CACHE_SHIFT=5
94CONFIG_VR4181=y 117CONFIG_HAVE_STD_PC_SERIAL_PORT=y
95 118
96# 119#
97# CPU selection 120# CPU selection
98# 121#
99# CONFIG_CPU_MIPS32 is not set 122# CONFIG_CPU_MIPS32_R1 is not set
100# CONFIG_CPU_MIPS64 is not set 123# CONFIG_CPU_MIPS32_R2 is not set
124# CONFIG_CPU_MIPS64_R1 is not set
125# CONFIG_CPU_MIPS64_R2 is not set
101# CONFIG_CPU_R3000 is not set 126# CONFIG_CPU_R3000 is not set
102# CONFIG_CPU_TX39XX is not set 127# CONFIG_CPU_TX39XX is not set
103CONFIG_CPU_VR41XX=y 128# CONFIG_CPU_VR41XX is not set
104# CONFIG_CPU_R4300 is not set 129# CONFIG_CPU_R4300 is not set
105# CONFIG_CPU_R4X00 is not set 130CONFIG_CPU_R4X00=y
106# CONFIG_CPU_TX49XX is not set 131# CONFIG_CPU_TX49XX is not set
107# CONFIG_CPU_R5000 is not set 132# CONFIG_CPU_R5000 is not set
108# CONFIG_CPU_R5432 is not set 133# CONFIG_CPU_R5432 is not set
@@ -113,17 +138,36 @@ CONFIG_CPU_VR41XX=y
113# CONFIG_CPU_RM7000 is not set 138# CONFIG_CPU_RM7000 is not set
114# CONFIG_CPU_RM9000 is not set 139# CONFIG_CPU_RM9000 is not set
115# CONFIG_CPU_SB1 is not set 140# CONFIG_CPU_SB1 is not set
141CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
142CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
143CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
144
145#
146# Kernel type
147#
148CONFIG_32BIT=y
149# CONFIG_64BIT is not set
116CONFIG_PAGE_SIZE_4KB=y 150CONFIG_PAGE_SIZE_4KB=y
117# CONFIG_PAGE_SIZE_8KB is not set 151# CONFIG_PAGE_SIZE_8KB is not set
118# CONFIG_PAGE_SIZE_16KB is not set 152# CONFIG_PAGE_SIZE_16KB is not set
119# CONFIG_PAGE_SIZE_64KB is not set 153# CONFIG_PAGE_SIZE_64KB is not set
154# CONFIG_MIPS_MT is not set
155# CONFIG_64BIT_PHYS_ADDR is not set
120# CONFIG_CPU_ADVANCED is not set 156# CONFIG_CPU_ADVANCED is not set
157CONFIG_CPU_HAS_LLSC=y
158CONFIG_CPU_HAS_LLDSCD=y
121CONFIG_CPU_HAS_SYNC=y 159CONFIG_CPU_HAS_SYNC=y
160CONFIG_ARCH_FLATMEM_ENABLE=y
161CONFIG_FLATMEM=y
162CONFIG_FLAT_NODE_MEM_MAP=y
163CONFIG_PREEMPT_NONE=y
164# CONFIG_PREEMPT_VOLUNTARY is not set
122# CONFIG_PREEMPT is not set 165# CONFIG_PREEMPT is not set
123 166
124# 167#
125# Bus options (PCI, PCMCIA, EISA, ISA, TC) 168# Bus options (PCI, PCMCIA, EISA, ISA, TC)
126# 169#
170CONFIG_ISA=y
127CONFIG_MMU=y 171CONFIG_MMU=y
128 172
129# 173#
@@ -132,10 +176,6 @@ CONFIG_MMU=y
132# CONFIG_PCCARD is not set 176# CONFIG_PCCARD is not set
133 177
134# 178#
135# PC-card bridges
136#
137
138#
139# PCI Hotplug Support 179# PCI Hotplug Support
140# 180#
141 181
@@ -147,6 +187,56 @@ CONFIG_BINFMT_ELF=y
147CONFIG_TRAD_SIGNALS=y 187CONFIG_TRAD_SIGNALS=y
148 188
149# 189#
190# Networking
191#
192CONFIG_NET=y
193
194#
195# Networking options
196#
197CONFIG_PACKET=y
198CONFIG_PACKET_MMAP=y
199CONFIG_UNIX=y
200# CONFIG_NET_KEY is not set
201CONFIG_INET=y
202CONFIG_IP_MULTICAST=y
203# CONFIG_IP_ADVANCED_ROUTER is not set
204CONFIG_IP_FIB_HASH=y
205CONFIG_IP_PNP=y
206CONFIG_IP_PNP_DHCP=y
207CONFIG_IP_PNP_BOOTP=y
208# CONFIG_IP_PNP_RARP is not set
209# CONFIG_NET_IPIP is not set
210# CONFIG_NET_IPGRE is not set
211# CONFIG_IP_MROUTE is not set
212# CONFIG_SYN_COOKIES is not set
213# CONFIG_INET_AH is not set
214# CONFIG_INET_ESP is not set
215# CONFIG_INET_IPCOMP is not set
216# CONFIG_INET_TUNNEL is not set
217CONFIG_IP_TCPDIAG=y
218# CONFIG_IP_TCPDIAG_IPV6 is not set
219# CONFIG_TCP_CONG_ADVANCED is not set
220CONFIG_TCP_CONG_BIC=y
221# CONFIG_IPV6 is not set
222# CONFIG_NETFILTER is not set
223# CONFIG_BRIDGE is not set
224# CONFIG_VLAN_8021Q is not set
225# CONFIG_DECNET is not set
226# CONFIG_LLC2 is not set
227# CONFIG_IPX is not set
228# CONFIG_ATALK is not set
229# CONFIG_NET_SCHED is not set
230# CONFIG_NET_CLS_ROUTE is not set
231
232#
233# Network testing
234#
235# CONFIG_HAMRADIO is not set
236# CONFIG_IRDA is not set
237# CONFIG_BT is not set
238
239#
150# Device Drivers 240# Device Drivers
151# 241#
152 242
@@ -154,7 +244,7 @@ CONFIG_TRAD_SIGNALS=y
154# Generic Driver Options 244# Generic Driver Options
155# 245#
156CONFIG_STANDALONE=y 246CONFIG_STANDALONE=y
157CONFIG_PREVENT_FIRMWARE_BUILD=y 247# CONFIG_PREVENT_FIRMWARE_BUILD is not set
158# CONFIG_FW_LOADER is not set 248# CONFIG_FW_LOADER is not set
159 249
160# 250#
@@ -170,6 +260,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
170# 260#
171# Plug and Play support 261# Plug and Play support
172# 262#
263# CONFIG_PNP is not set
173 264
174# 265#
175# Block devices 266# Block devices
@@ -181,19 +272,16 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
181# CONFIG_BLK_DEV_RAM is not set 272# CONFIG_BLK_DEV_RAM is not set
182CONFIG_BLK_DEV_RAM_COUNT=16 273CONFIG_BLK_DEV_RAM_COUNT=16
183CONFIG_INITRAMFS_SOURCE="" 274CONFIG_INITRAMFS_SOURCE=""
184# CONFIG_LBD is not set 275# CONFIG_CDROM_PKTCDVD is not set
185CONFIG_CDROM_PKTCDVD=m
186CONFIG_CDROM_PKTCDVD_BUFFERS=8
187# CONFIG_CDROM_PKTCDVD_WCACHE is not set
188 276
189# 277#
190# IO Schedulers 278# IO Schedulers
191# 279#
192CONFIG_IOSCHED_NOOP=y 280CONFIG_IOSCHED_NOOP=y
193CONFIG_IOSCHED_AS=y 281# CONFIG_IOSCHED_AS is not set
194CONFIG_IOSCHED_DEADLINE=y 282# CONFIG_IOSCHED_DEADLINE is not set
195CONFIG_IOSCHED_CFQ=y 283# CONFIG_IOSCHED_CFQ is not set
196CONFIG_ATA_OVER_ETH=m 284# CONFIG_ATA_OVER_ETH is not set
197 285
198# 286#
199# ATA/ATAPI/MFM/RLL support 287# ATA/ATAPI/MFM/RLL support
@@ -206,6 +294,11 @@ CONFIG_ATA_OVER_ETH=m
206# CONFIG_SCSI is not set 294# CONFIG_SCSI is not set
207 295
208# 296#
297# Old CD-ROM drivers (not SCSI, not IDE)
298#
299# CONFIG_CD_NO_IDESCSI is not set
300
301#
209# Multi-device support (RAID and LVM) 302# Multi-device support (RAID and LVM)
210# 303#
211# CONFIG_MD is not set 304# CONFIG_MD is not set
@@ -213,6 +306,7 @@ CONFIG_ATA_OVER_ETH=m
213# 306#
214# Fusion MPT device support 307# Fusion MPT device support
215# 308#
309# CONFIG_FUSION is not set
216 310
217# 311#
218# IEEE 1394 (FireWire) support 312# IEEE 1394 (FireWire) support
@@ -223,84 +317,41 @@ CONFIG_ATA_OVER_ETH=m
223# 317#
224 318
225# 319#
226# Networking support 320# Network device support
227#
228CONFIG_NET=y
229
230#
231# Networking options
232# 321#
233CONFIG_PACKET=y
234# CONFIG_PACKET_MMAP is not set
235CONFIG_NETLINK_DEV=y
236CONFIG_UNIX=y
237CONFIG_NET_KEY=y
238CONFIG_INET=y
239# CONFIG_IP_MULTICAST is not set
240# CONFIG_IP_ADVANCED_ROUTER is not set
241CONFIG_IP_PNP=y
242# CONFIG_IP_PNP_DHCP is not set
243CONFIG_IP_PNP_BOOTP=y
244# CONFIG_IP_PNP_RARP is not set
245# CONFIG_NET_IPIP is not set
246# CONFIG_NET_IPGRE is not set
247# CONFIG_ARPD is not set
248# CONFIG_SYN_COOKIES is not set
249# CONFIG_INET_AH is not set
250# CONFIG_INET_ESP is not set
251# CONFIG_INET_IPCOMP is not set
252CONFIG_INET_TUNNEL=m
253CONFIG_IP_TCPDIAG=m
254# CONFIG_IP_TCPDIAG_IPV6 is not set
255# CONFIG_IPV6 is not set
256# CONFIG_NETFILTER is not set
257CONFIG_XFRM=y
258CONFIG_XFRM_USER=m
259
260#
261# SCTP Configuration (EXPERIMENTAL)
262#
263# CONFIG_IP_SCTP is not set
264# CONFIG_ATM is not set
265# CONFIG_BRIDGE is not set
266# CONFIG_VLAN_8021Q is not set
267# CONFIG_DECNET is not set
268# CONFIG_LLC2 is not set
269# CONFIG_IPX is not set
270# CONFIG_ATALK is not set
271# CONFIG_X25 is not set
272# CONFIG_LAPB is not set
273# CONFIG_NET_DIVERT is not set
274# CONFIG_ECONET is not set
275# CONFIG_WAN_ROUTER is not set
276
277#
278# QoS and/or fair queueing
279#
280# CONFIG_NET_SCHED is not set
281# CONFIG_NET_CLS_ROUTE is not set
282
283#
284# Network testing
285#
286# CONFIG_NET_PKTGEN is not set
287# CONFIG_NETPOLL is not set
288# CONFIG_NET_POLL_CONTROLLER is not set
289# CONFIG_HAMRADIO is not set
290# CONFIG_IRDA is not set
291# CONFIG_BT is not set
292CONFIG_NETDEVICES=y 322CONFIG_NETDEVICES=y
293# CONFIG_DUMMY is not set 323# CONFIG_DUMMY is not set
294# CONFIG_BONDING is not set 324# CONFIG_BONDING is not set
295# CONFIG_EQUALIZER is not set 325# CONFIG_EQUALIZER is not set
296# CONFIG_TUN is not set 326# CONFIG_TUN is not set
297# CONFIG_ETHERTAP is not set 327
328#
329# ARCnet devices
330#
331# CONFIG_ARCNET is not set
298 332
299# 333#
300# Ethernet (10 or 100Mbit) 334# Ethernet (10 or 100Mbit)
301# 335#
302CONFIG_NET_ETHERNET=y 336CONFIG_NET_ETHERNET=y
303# CONFIG_MII is not set 337CONFIG_MII=y
338# CONFIG_NET_VENDOR_3COM is not set
339# CONFIG_NET_VENDOR_SMC is not set
340# CONFIG_NET_VENDOR_RACAL is not set
341# CONFIG_DEPCA is not set
342# CONFIG_HP100 is not set
343CONFIG_NET_ISA=y
344# CONFIG_E2100 is not set
345# CONFIG_EWRK3 is not set
346# CONFIG_EEXPRESS is not set
347# CONFIG_EEXPRESS_PRO is not set
348# CONFIG_HPLAN_PLUS is not set
349# CONFIG_HPLAN is not set
350# CONFIG_LP486E is not set
351# CONFIG_ETH16I is not set
352CONFIG_NE2000=y
353# CONFIG_NET_PCI is not set
354# CONFIG_NET_POCKET is not set
304 355
305# 356#
306# Ethernet (1000 Mbit) 357# Ethernet (1000 Mbit)
@@ -313,6 +364,7 @@ CONFIG_NET_ETHERNET=y
313# 364#
314# Token Ring devices 365# Token Ring devices
315# 366#
367# CONFIG_TR is not set
316 368
317# 369#
318# Wireless LAN (non-hamradio) 370# Wireless LAN (non-hamradio)
@@ -325,8 +377,8 @@ CONFIG_NET_ETHERNET=y
325# CONFIG_WAN is not set 377# CONFIG_WAN is not set
326# CONFIG_PPP is not set 378# CONFIG_PPP is not set
327# CONFIG_SLIP is not set 379# CONFIG_SLIP is not set
328# CONFIG_SHAPER is not set 380# CONFIG_NETPOLL is not set
329# CONFIG_NETCONSOLE is not set 381# CONFIG_NET_POLL_CONTROLLER is not set
330 382
331# 383#
332# ISDN subsystem 384# ISDN subsystem
@@ -346,28 +398,13 @@ CONFIG_INPUT=y
346# 398#
347# Userland interfaces 399# Userland interfaces
348# 400#
349CONFIG_INPUT_MOUSEDEV=y 401# CONFIG_INPUT_MOUSEDEV is not set
350CONFIG_INPUT_MOUSEDEV_PSAUX=y
351CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
352CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
353# CONFIG_INPUT_JOYDEV is not set 402# CONFIG_INPUT_JOYDEV is not set
354# CONFIG_INPUT_TSDEV is not set 403# CONFIG_INPUT_TSDEV is not set
355# CONFIG_INPUT_EVDEV is not set 404# CONFIG_INPUT_EVDEV is not set
356# CONFIG_INPUT_EVBUG is not set 405# CONFIG_INPUT_EVBUG is not set
357 406
358# 407#
359# Input I/O drivers
360#
361# CONFIG_GAMEPORT is not set
362CONFIG_SOUND_GAMEPORT=y
363CONFIG_SERIO=y
364# CONFIG_SERIO_I8042 is not set
365CONFIG_SERIO_SERPORT=y
366# CONFIG_SERIO_CT82C710 is not set
367# CONFIG_SERIO_LIBPS2 is not set
368CONFIG_SERIO_RAW=m
369
370#
371# Input Device Drivers 408# Input Device Drivers
372# 409#
373# CONFIG_INPUT_KEYBOARD is not set 410# CONFIG_INPUT_KEYBOARD is not set
@@ -377,6 +414,12 @@ CONFIG_SERIO_RAW=m
377# CONFIG_INPUT_MISC is not set 414# CONFIG_INPUT_MISC is not set
378 415
379# 416#
417# Hardware I/O ports
418#
419# CONFIG_SERIO is not set
420# CONFIG_GAMEPORT is not set
421
422#
380# Character devices 423# Character devices
381# 424#
382CONFIG_VT=y 425CONFIG_VT=y
@@ -397,9 +440,8 @@ CONFIG_SERIAL_8250_NR_UARTS=4
397# 440#
398CONFIG_SERIAL_CORE=y 441CONFIG_SERIAL_CORE=y
399CONFIG_SERIAL_CORE_CONSOLE=y 442CONFIG_SERIAL_CORE_CONSOLE=y
400CONFIG_UNIX98_PTYS=y 443# CONFIG_UNIX98_PTYS is not set
401CONFIG_LEGACY_PTYS=y 444# CONFIG_LEGACY_PTYS is not set
402CONFIG_LEGACY_PTY_COUNT=256
403 445
404# 446#
405# IPMI 447# IPMI
@@ -418,13 +460,17 @@ CONFIG_LEGACY_PTY_COUNT=256
418# 460#
419# Ftape, the floppy tape device driver 461# Ftape, the floppy tape device driver
420# 462#
421# CONFIG_DRM is not set
422# CONFIG_RAW_DRIVER is not set 463# CONFIG_RAW_DRIVER is not set
423 464
424# 465#
466# TPM devices
467#
468
469#
425# I2C support 470# I2C support
426# 471#
427# CONFIG_I2C is not set 472# CONFIG_I2C is not set
473# CONFIG_I2C_SENSOR is not set
428 474
429# 475#
430# Dallas's 1-wire bus 476# Dallas's 1-wire bus
@@ -432,6 +478,11 @@ CONFIG_LEGACY_PTY_COUNT=256
432# CONFIG_W1 is not set 478# CONFIG_W1 is not set
433 479
434# 480#
481# Hardware Monitoring support
482#
483# CONFIG_HWMON is not set
484
485#
435# Misc devices 486# Misc devices
436# 487#
437 488
@@ -453,9 +504,9 @@ CONFIG_LEGACY_PTY_COUNT=256
453# 504#
454# Console display driver support 505# Console display driver support
455# 506#
456# CONFIG_VGA_CONSOLE is not set 507CONFIG_VGA_CONSOLE=y
508# CONFIG_MDA_CONSOLE is not set
457CONFIG_DUMMY_CONSOLE=y 509CONFIG_DUMMY_CONSOLE=y
458# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
459 510
460# 511#
461# Sound 512# Sound
@@ -469,10 +520,6 @@ CONFIG_DUMMY_CONSOLE=y
469# CONFIG_USB_ARCH_HAS_OHCI is not set 520# CONFIG_USB_ARCH_HAS_OHCI is not set
470 521
471# 522#
472# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
473#
474
475#
476# USB Gadget Support 523# USB Gadget Support
477# 524#
478# CONFIG_USB_GADGET is not set 525# CONFIG_USB_GADGET is not set
@@ -488,19 +535,28 @@ CONFIG_DUMMY_CONSOLE=y
488# CONFIG_INFINIBAND is not set 535# CONFIG_INFINIBAND is not set
489 536
490# 537#
538# SN Devices
539#
540
541#
491# File systems 542# File systems
492# 543#
493CONFIG_EXT2_FS=y 544# CONFIG_EXT2_FS is not set
494# CONFIG_EXT2_FS_XATTR is not set
495# CONFIG_EXT3_FS is not set 545# CONFIG_EXT3_FS is not set
496# CONFIG_JBD is not set 546# CONFIG_JBD is not set
497# CONFIG_REISERFS_FS is not set 547# CONFIG_REISERFS_FS is not set
498# CONFIG_JFS_FS is not set 548# CONFIG_JFS_FS is not set
549# CONFIG_FS_POSIX_ACL is not set
550
551#
552# XFS support
553#
499# CONFIG_XFS_FS is not set 554# CONFIG_XFS_FS is not set
500# CONFIG_MINIX_FS is not set 555# CONFIG_MINIX_FS is not set
501# CONFIG_ROMFS_FS is not set 556# CONFIG_ROMFS_FS is not set
557CONFIG_INOTIFY=y
502# CONFIG_QUOTA is not set 558# CONFIG_QUOTA is not set
503CONFIG_DNOTIFY=y 559# CONFIG_DNOTIFY is not set
504# CONFIG_AUTOFS_FS is not set 560# CONFIG_AUTOFS_FS is not set
505# CONFIG_AUTOFS4_FS is not set 561# CONFIG_AUTOFS4_FS is not set
506 562
@@ -520,12 +576,8 @@ CONFIG_DNOTIFY=y
520# 576#
521# Pseudo filesystems 577# Pseudo filesystems
522# 578#
523CONFIG_PROC_FS=y 579# CONFIG_PROC_FS is not set
524CONFIG_PROC_KCORE=y 580# CONFIG_SYSFS is not set
525CONFIG_SYSFS=y
526# CONFIG_DEVFS_FS is not set
527CONFIG_DEVPTS_FS_XATTR=y
528CONFIG_DEVPTS_FS_SECURITY=y
529# CONFIG_TMPFS is not set 581# CONFIG_TMPFS is not set
530# CONFIG_HUGETLB_PAGE is not set 582# CONFIG_HUGETLB_PAGE is not set
531CONFIG_RAMFS=y 583CONFIG_RAMFS=y
@@ -533,13 +585,7 @@ CONFIG_RAMFS=y
533# 585#
534# Miscellaneous filesystems 586# Miscellaneous filesystems
535# 587#
536# CONFIG_ADFS_FS is not set
537# CONFIG_AFFS_FS is not set
538# CONFIG_HFS_FS is not set
539# CONFIG_HFSPLUS_FS is not set 588# CONFIG_HFSPLUS_FS is not set
540# CONFIG_BEFS_FS is not set
541# CONFIG_BFS_FS is not set
542# CONFIG_EFS_FS is not set
543# CONFIG_CRAMFS is not set 589# CONFIG_CRAMFS is not set
544# CONFIG_VXFS_FS is not set 590# CONFIG_VXFS_FS is not set
545# CONFIG_HPFS_FS is not set 591# CONFIG_HPFS_FS is not set
@@ -551,23 +597,18 @@ CONFIG_RAMFS=y
551# Network File Systems 597# Network File Systems
552# 598#
553CONFIG_NFS_FS=y 599CONFIG_NFS_FS=y
554# CONFIG_NFS_V3 is not set 600CONFIG_NFS_V3=y
555# CONFIG_NFS_V4 is not set 601# CONFIG_NFS_V3_ACL is not set
556# CONFIG_NFS_DIRECTIO is not set 602# CONFIG_NFSD is not set
557CONFIG_NFSD=y
558# CONFIG_NFSD_V3 is not set
559# CONFIG_NFSD_TCP is not set
560CONFIG_ROOT_NFS=y 603CONFIG_ROOT_NFS=y
561CONFIG_LOCKD=y 604CONFIG_LOCKD=y
562CONFIG_EXPORTFS=y 605CONFIG_LOCKD_V4=y
606CONFIG_NFS_COMMON=y
563CONFIG_SUNRPC=y 607CONFIG_SUNRPC=y
564# CONFIG_RPCSEC_GSS_KRB5 is not set
565# CONFIG_RPCSEC_GSS_SPKM3 is not set
566# CONFIG_SMB_FS is not set 608# CONFIG_SMB_FS is not set
567# CONFIG_CIFS is not set 609# CONFIG_CIFS is not set
568# CONFIG_NCP_FS is not set 610# CONFIG_NCP_FS is not set
569# CONFIG_CODA_FS is not set 611# CONFIG_CODA_FS is not set
570# CONFIG_AFS_FS is not set
571 612
572# 613#
573# Partition Types 614# Partition Types
@@ -581,22 +622,18 @@ CONFIG_MSDOS_PARTITION=y
581# CONFIG_NLS is not set 622# CONFIG_NLS is not set
582 623
583# 624#
584# Profiling support
585#
586# CONFIG_PROFILING is not set
587
588#
589# Kernel hacking 625# Kernel hacking
590# 626#
627# CONFIG_PRINTK_TIME is not set
591# CONFIG_DEBUG_KERNEL is not set 628# CONFIG_DEBUG_KERNEL is not set
629CONFIG_LOG_BUF_SHIFT=14
592CONFIG_CROSSCOMPILE=y 630CONFIG_CROSSCOMPILE=y
593CONFIG_CMDLINE="ip=bootp ether=46,0x03fe0300,eth0" 631CONFIG_CMDLINE="console=ttyS0 debug ip=172.20.0.2:172.20.0.1::255.255.0.0"
594 632
595# 633#
596# Security options 634# Security options
597# 635#
598CONFIG_KEYS=y 636# CONFIG_KEYS is not set
599CONFIG_KEYS_DEBUG_PROC_KEYS=y
600# CONFIG_SECURITY is not set 637# CONFIG_SECURITY is not set
601 638
602# 639#
@@ -612,7 +649,7 @@ CONFIG_KEYS_DEBUG_PROC_KEYS=y
612# Library routines 649# Library routines
613# 650#
614# CONFIG_CRC_CCITT is not set 651# CONFIG_CRC_CCITT is not set
615# CONFIG_CRC32 is not set 652CONFIG_CRC32=y
616CONFIG_LIBCRC32C=m 653# CONFIG_LIBCRC32C is not set
617CONFIG_GENERIC_HARDIRQS=y 654CONFIG_GENERIC_HARDIRQS=y
618CONFIG_GENERIC_IRQ_PROBE=y 655CONFIG_GENERIC_IRQ_PROBE=y
diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig
index d0c85a4009d6..17d4fce6c4c6 100644
--- a/arch/mips/configs/rm200_defconfig
+++ b/arch/mips/configs/rm200_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:09 2005 4# Wed Jan 26 02:49:09 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -91,6 +91,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y
91CONFIG_HAVE_DEC_LOCK=y 91CONFIG_HAVE_DEC_LOCK=y
92CONFIG_ARC=y 92CONFIG_ARC=y
93CONFIG_DMA_NONCOHERENT=y 93CONFIG_DMA_NONCOHERENT=y
94CONFIG_DMA_NEED_PCI_MAP_STATE=y
94CONFIG_GENERIC_ISA_DMA=y 95CONFIG_GENERIC_ISA_DMA=y
95CONFIG_I8259=y 96CONFIG_I8259=y
96CONFIG_CPU_LITTLE_ENDIAN=y 97CONFIG_CPU_LITTLE_ENDIAN=y
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 84978b70714b..1dc935f37582 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:10 2005 4# Wed Jan 26 02:49:10 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
diff --git a/arch/mips/configs/sead_defconfig b/arch/mips/configs/sead_defconfig
index 7c718a429b04..dd07e866b128 100644
--- a/arch/mips/configs/sead_defconfig
+++ b/arch/mips/configs/sead_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:10 2005 4# Wed Jan 26 02:49:10 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -80,6 +80,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
80CONFIG_GENERIC_CALIBRATE_DELAY=y 80CONFIG_GENERIC_CALIBRATE_DELAY=y
81CONFIG_HAVE_DEC_LOCK=y 81CONFIG_HAVE_DEC_LOCK=y
82CONFIG_DMA_NONCOHERENT=y 82CONFIG_DMA_NONCOHERENT=y
83CONFIG_DMA_NEED_PCI_MAP_STATE=y
83CONFIG_CPU_LITTLE_ENDIAN=y 84CONFIG_CPU_LITTLE_ENDIAN=y
84CONFIG_IRQ_CPU=y 85CONFIG_IRQ_CPU=y
85CONFIG_MIPS_BOARDS_GEN=y 86CONFIG_MIPS_BOARDS_GEN=y
diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig
index e01727cd0fe9..c9d3f83caf0f 100644
--- a/arch/mips/configs/tb0226_defconfig
+++ b/arch/mips/configs/tb0226_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:12 2005 4# Wed Jan 26 02:49:12 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -95,6 +95,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
95CONFIG_GENERIC_CALIBRATE_DELAY=y 95CONFIG_GENERIC_CALIBRATE_DELAY=y
96CONFIG_HAVE_DEC_LOCK=y 96CONFIG_HAVE_DEC_LOCK=y
97CONFIG_DMA_NONCOHERENT=y 97CONFIG_DMA_NONCOHERENT=y
98CONFIG_DMA_NEED_PCI_MAP_STATE=y
98CONFIG_CPU_LITTLE_ENDIAN=y 99CONFIG_CPU_LITTLE_ENDIAN=y
99CONFIG_IRQ_CPU=y 100CONFIG_IRQ_CPU=y
100CONFIG_MIPS_L1_CACHE_SHIFT=5 101CONFIG_MIPS_L1_CACHE_SHIFT=5
diff --git a/arch/mips/configs/tb0229_defconfig b/arch/mips/configs/tb0229_defconfig
index c6ba3de27614..2cb669188aa9 100644
--- a/arch/mips/configs/tb0229_defconfig
+++ b/arch/mips/configs/tb0229_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:12 2005 4# Wed Jan 26 02:49:12 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -98,6 +98,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
98CONFIG_GENERIC_CALIBRATE_DELAY=y 98CONFIG_GENERIC_CALIBRATE_DELAY=y
99CONFIG_HAVE_DEC_LOCK=y 99CONFIG_HAVE_DEC_LOCK=y
100CONFIG_DMA_NONCOHERENT=y 100CONFIG_DMA_NONCOHERENT=y
101CONFIG_DMA_NEED_PCI_MAP_STATE=y
101CONFIG_CPU_LITTLE_ENDIAN=y 102CONFIG_CPU_LITTLE_ENDIAN=y
102CONFIG_IRQ_CPU=y 103CONFIG_IRQ_CPU=y
103CONFIG_MIPS_L1_CACHE_SHIFT=5 104CONFIG_MIPS_L1_CACHE_SHIFT=5
diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig
index 915c43b6e2d9..16e07fca446f 100644
--- a/arch/mips/configs/workpad_defconfig
+++ b/arch/mips/configs/workpad_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:12 2005 4# Wed Jan 26 02:49:12 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -96,6 +96,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
96CONFIG_GENERIC_CALIBRATE_DELAY=y 96CONFIG_GENERIC_CALIBRATE_DELAY=y
97CONFIG_HAVE_DEC_LOCK=y 97CONFIG_HAVE_DEC_LOCK=y
98CONFIG_DMA_NONCOHERENT=y 98CONFIG_DMA_NONCOHERENT=y
99CONFIG_DMA_NEED_PCI_MAP_STATE=y
99CONFIG_CPU_LITTLE_ENDIAN=y 100CONFIG_CPU_LITTLE_ENDIAN=y
100CONFIG_IRQ_CPU=y 101CONFIG_IRQ_CPU=y
101CONFIG_MIPS_L1_CACHE_SHIFT=5 102CONFIG_MIPS_L1_CACHE_SHIFT=5
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
index 562f2b8043ac..6d2290777ad7 100644
--- a/arch/mips/configs/yosemite_defconfig
+++ b/arch/mips/configs/yosemite_defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:49:13 2005 4# Wed Jan 26 02:49:13 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
index 5f027bfa4af8..9ffe1a9142ca 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq.c
@@ -76,7 +76,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
76extern void vrc5477_irq_init(u32 base); 76extern void vrc5477_irq_init(u32 base);
77extern void mips_cpu_irq_init(u32 base); 77extern void mips_cpu_irq_init(u32 base);
78extern asmlinkage void ddb5477_handle_int(void); 78extern asmlinkage void ddb5477_handle_int(void);
79extern int setup_irq(unsigned int irq, struct irqaction *irqaction); 79extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
80static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; 80static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
81 81
82void __init arch_init_irq(void) 82void __init arch_init_irq(void)
@@ -94,7 +94,7 @@ void __init arch_init_irq(void)
94 /* setup PCI interrupt attributes */ 94 /* setup PCI interrupt attributes */
95 set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); 95 set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
96 set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); 96 set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
97 if (mips_machtype == MACH_NEC_ROCKHOPPERII) 97 if (mips_machtype == MACH_NEC_ROCKHOPPERII)
98 set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); 98 set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
99 else 99 else
100 set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); 100 set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
@@ -134,7 +134,7 @@ void __init arch_init_irq(void)
134 134
135 /* setup cascade interrupts */ 135 /* setup cascade interrupts */
136 setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); 136 setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
137 setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); 137 setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
138 138
139 /* hook up the first-level interrupt handler */ 139 /* hook up the first-level interrupt handler */
140 set_except_vector(0, ddb5477_handle_int); 140 set_except_vector(0, ddb5477_handle_int);
diff --git a/arch/mips/ddb5xxx/ddb5477/setup.c b/arch/mips/ddb5xxx/ddb5477/setup.c
index 15c6e543b56f..d62f5a789b05 100644
--- a/arch/mips/ddb5xxx/ddb5477/setup.c
+++ b/arch/mips/ddb5xxx/ddb5477/setup.c
@@ -141,7 +141,7 @@ static void __init ddb_time_init(void)
141 141
142 /* mips_hpt_frequency is 1/2 of the cpu core freq */ 142 /* mips_hpt_frequency is 1/2 of the cpu core freq */
143 i = (read_c0_config() >> 28 ) & 7; 143 i = (read_c0_config() >> 28 ) & 7;
144 if ((current_cpu_data.cputype == CPU_R5432) && (i == 3)) 144 if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
145 i = 4; 145 i = 4;
146 mips_hpt_frequency = bus_frequency*(i+4)/4; 146 mips_hpt_frequency = bus_frequency*(i+4)/4;
147} 147}
@@ -298,11 +298,11 @@ static void __init ddb5477_board_init(void)
298 298
299 if (mips_machtype == MACH_NEC_ROCKHOPPER 299 if (mips_machtype == MACH_NEC_ROCKHOPPER
300 || mips_machtype == MACH_NEC_ROCKHOPPERII) { 300 || mips_machtype == MACH_NEC_ROCKHOPPERII) {
301 /* Disable bus diagnostics. */ 301 /* Disable bus diagnostics. */
302 ddb_out32(DDB_PCICTL0_L, 0); 302 ddb_out32(DDB_PCICTL0_L, 0);
303 ddb_out32(DDB_PCICTL0_H, 0); 303 ddb_out32(DDB_PCICTL0_H, 0);
304 ddb_out32(DDB_PCICTL1_L, 0); 304 ddb_out32(DDB_PCICTL1_L, 0);
305 ddb_out32(DDB_PCICTL1_H, 0); 305 ddb_out32(DDB_PCICTL1_H, 0);
306 } 306 }
307 307
308 if (mips_machtype == MACH_NEC_ROCKHOPPER) { 308 if (mips_machtype == MACH_NEC_ROCKHOPPER) {
@@ -354,7 +354,7 @@ static void __init ddb5477_board_init(void)
354 */ 354 */
355 pci_write_config_byte(&dev_m1533, 0x58, 0x74); 355 pci_write_config_byte(&dev_m1533, 0x58, 0x74);
356 356
357 /* 357 /*
358 * positive decode (bit6 -0) 358 * positive decode (bit6 -0)
359 * enable IDE controler interrupt (bit 4 -1) 359 * enable IDE controler interrupt (bit 4 -1)
360 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101) 360 * setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
@@ -364,31 +364,31 @@ static void __init ddb5477_board_init(void)
364 /* Setup M5229 registers */ 364 /* Setup M5229 registers */
365 dev_m5229.bus = &bus; 365 dev_m5229.bus = &bus;
366 dev_m5229.sysdata = NULL; 366 dev_m5229.sysdata = NULL;
367 dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE 367 dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
368 368
369 /* 369 /*
370 * enable IDE in the M5229 config register 0x50 (bit 0 - 1) 370 * enable IDE in the M5229 config register 0x50 (bit 0 - 1)
371 * M5229 IDSEL is addr:15; see above setting 371 * M5229 IDSEL is addr:15; see above setting
372 */ 372 */
373 pci_read_config_byte(&dev_m5229, 0x50, &temp8); 373 pci_read_config_byte(&dev_m5229, 0x50, &temp8);
374 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1); 374 pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
375 375
376 /* 376 /*
377 * enable bus master (bit 2) and IO decoding (bit 0) 377 * enable bus master (bit 2) and IO decoding (bit 0)
378 */ 378 */
379 pci_read_config_byte(&dev_m5229, 0x04, &temp8); 379 pci_read_config_byte(&dev_m5229, 0x04, &temp8);
380 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5); 380 pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
381 381
382 /* 382 /*
383 * enable native, copied from arch/ppc/k2boot/head.S 383 * enable native, copied from arch/ppc/k2boot/head.S
384 * TODO - need volatile, need to be portable 384 * TODO - need volatile, need to be portable
385 */ 385 */
386 pci_write_config_byte(&dev_m5229, 0x09, 0xef); 386 pci_write_config_byte(&dev_m5229, 0x09, 0xef);
387 387
388 /* Set Primary Channel Command Block Timing */ 388 /* Set Primary Channel Command Block Timing */
389 pci_write_config_byte(&dev_m5229, 0x59, 0x31); 389 pci_write_config_byte(&dev_m5229, 0x59, 0x31);
390 390
391 /* 391 /*
392 * Enable primary channel 40-pin cable 392 * Enable primary channel 40-pin cable
393 * M5229 register 0x4a (bit 0) 393 * M5229 register 0x4a (bit 0)
394 */ 394 */
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 133fb7c48e6c..6dbce92eb068 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -253,7 +253,7 @@ static inline void dec_kn03_be_init(void)
253 253
254 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR); 254 kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR);
255 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN); 255 kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN);
256 256
257 /* 257 /*
258 * Set normal ECC detection and generation, enable ECC correction. 258 * Set normal ECC detection and generation, enable ECC correction.
259 * For KN05 we also need to make sure EE (?) is enabled in the MB. 259 * For KN05 we also need to make sure EE (?) is enabled in the MB.
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index 3b3790993219..c89768d5c4e5 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -133,7 +133,7 @@
133 */ 133 */
134 mfc0 t0,CP0_CAUSE # get pending interrupts 134 mfc0 t0,CP0_CAUSE # get pending interrupts
135 mfc0 t1,CP0_STATUS 135 mfc0 t1,CP0_STATUS
136#ifdef CONFIG_MIPS32 136#ifdef CONFIG_32BIT
137 lw t2,cpu_fpu_mask 137 lw t2,cpu_fpu_mask
138#endif 138#endif
139 andi t0,ST0_IM # CAUSE.CE may be non-zero! 139 andi t0,ST0_IM # CAUSE.CE may be non-zero!
@@ -141,7 +141,7 @@
141 141
142 beqz t0,spurious 142 beqz t0,spurious
143 143
144#ifdef CONFIG_MIPS32 144#ifdef CONFIG_32BIT
145 and t2,t0 145 and t2,t0
146 bnez t2,fpu # handle FPU immediately 146 bnez t2,fpu # handle FPU immediately
147#endif 147#endif
@@ -271,7 +271,7 @@ handle_it:
271 j ret_from_irq 271 j ret_from_irq
272 nop 272 nop
273 273
274#ifdef CONFIG_MIPS32 274#ifdef CONFIG_32BIT
275fpu: 275fpu:
276 j handle_fpe_int 276 j handle_fpe_int
277 nop 277 nop
diff --git a/arch/mips/dec/prom/Makefile b/arch/mips/dec/prom/Makefile
index 373822ec2d8c..bcd0247b3a66 100644
--- a/arch/mips/dec/prom/Makefile
+++ b/arch/mips/dec/prom/Makefile
@@ -5,7 +5,7 @@
5 5
6lib-y += init.o memory.o cmdline.o identify.o console.o 6lib-y += init.o memory.o cmdline.o identify.o console.o
7 7
8lib-$(CONFIG_MIPS32) += locore.o 8lib-$(CONFIG_32BIT) += locore.o
9lib-$(CONFIG_MIPS64) += call_o32.o 9lib-$(CONFIG_64BIT) += call_o32.o
10 10
11EXTRA_AFLAGS := $(CFLAGS) 11EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/defconfig b/arch/mips/defconfig
index d55fe665926f..20f84b119b4c 100644
--- a/arch/mips/defconfig
+++ b/arch/mips/defconfig
@@ -4,9 +4,9 @@
4# Wed Jan 26 02:48:59 2005 4# Wed Jan 26 02:48:59 2005
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7# CONFIG_MIPS64 is not set
8# CONFIG_64BIT is not set 7# CONFIG_64BIT is not set
9CONFIG_MIPS32=y 8# CONFIG_64BIT is not set
9CONFIG_32BIT=y
10 10
11# 11#
12# Code maturity level options 12# Code maturity level options
@@ -90,6 +90,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y
90CONFIG_HAVE_DEC_LOCK=y 90CONFIG_HAVE_DEC_LOCK=y
91CONFIG_ARC=y 91CONFIG_ARC=y
92CONFIG_DMA_NONCOHERENT=y 92CONFIG_DMA_NONCOHERENT=y
93CONFIG_DMA_NEED_PCI_MAP_STATE=y
93# CONFIG_CPU_LITTLE_ENDIAN is not set 94# CONFIG_CPU_LITTLE_ENDIAN is not set
94CONFIG_IRQ_CPU=y 95CONFIG_IRQ_CPU=y
95CONFIG_SWAP_IO_SPACE=y 96CONFIG_SWAP_IO_SPACE=y
diff --git a/arch/mips/ite-boards/generic/it8172_setup.c b/arch/mips/ite-boards/generic/it8172_setup.c
index d808a67294b8..a5f6d84bc181 100644
--- a/arch/mips/ite-boards/generic/it8172_setup.c
+++ b/arch/mips/ite-boards/generic/it8172_setup.c
@@ -129,7 +129,7 @@ static void __init it8172_setup(void)
129 129
130 /* 130 /*
131 * IO/MEM resources. 131 * IO/MEM resources.
132 * 132 *
133 * revisit this area. 133 * revisit this area.
134 */ 134 */
135 set_io_port_base(KSEG1); 135 set_io_port_base(KSEG1);
diff --git a/arch/mips/ite-boards/generic/time.c b/arch/mips/ite-boards/generic/time.c
index 30a6c0d5fc50..f5d67ee21ac6 100644
--- a/arch/mips/ite-boards/generic/time.c
+++ b/arch/mips/ite-boards/generic/time.c
@@ -72,7 +72,7 @@ static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; }
72static inline unsigned char 72static inline unsigned char
73bin_to_hw(unsigned char c) 73bin_to_hw(unsigned char c)
74{ 74{
75 if (rtc_dm_binary()) 75 if (rtc_dm_binary())
76 return c; 76 return c;
77 else 77 else
78 return ((c/10) << 4) + (c%10); 78 return ((c/10) << 4) + (c%10);
@@ -91,9 +91,9 @@ hw_to_bin(unsigned char c)
91static inline unsigned char 91static inline unsigned char
92hour_bin_to_hw(unsigned char c) 92hour_bin_to_hw(unsigned char c)
93{ 93{
94 if (rtc_24h()) 94 if (rtc_24h())
95 return bin_to_hw(c); 95 return bin_to_hw(c);
96 if (c >= 12) 96 if (c >= 12)
97 return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */ 97 return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */
98 else 98 else
99 return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */ 99 return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */
@@ -105,9 +105,9 @@ hour_hw_to_bin(unsigned char c)
105 unsigned char tmp = hw_to_bin(c&0x3f); 105 unsigned char tmp = hw_to_bin(c&0x3f);
106 if (rtc_24h()) 106 if (rtc_24h())
107 return tmp; 107 return tmp;
108 if (c & 0x80) 108 if (c & 0x80)
109 return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */ 109 return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */
110 else 110 else
111 return (tmp==12)?0:tmp; /* 12am is 0 */ 111 return (tmp==12)?0:tmp; /* 12am is 0 */
112} 112}
113 113
@@ -145,7 +145,7 @@ static unsigned long __init cal_r4koff(void)
145 return (mips_hpt_frequency / HZ); 145 return (mips_hpt_frequency / HZ);
146} 146}
147 147
148static unsigned long 148static unsigned long
149it8172_rtc_get_time(void) 149it8172_rtc_get_time(void)
150{ 150{
151 unsigned int year, mon, day, hour, min, sec; 151 unsigned int year, mon, day, hour, min, sec;
@@ -166,12 +166,12 @@ it8172_rtc_get_time(void)
166 hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS)); 166 hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS));
167 day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH)); 167 day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH));
168 mon = hw_to_bin(CMOS_READ(RTC_MONTH)); 168 mon = hw_to_bin(CMOS_READ(RTC_MONTH));
169 year = hw_to_bin(CMOS_READ(RTC_YEAR)) + 169 year = hw_to_bin(CMOS_READ(RTC_YEAR)) +
170 hw_to_bin(*rtc_century_reg) * 100; 170 hw_to_bin(*rtc_century_reg) * 100;
171 171
172 /* restore interrupts */ 172 /* restore interrupts */
173 local_irq_restore(flags); 173 local_irq_restore(flags);
174 174
175 return mktime(year, mon, day, hour, min, sec); 175 return mktime(year, mon, day, hour, min, sec);
176} 176}
177 177
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index a0230ee0f7f4..d3303584fbd1 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -13,8 +13,8 @@ binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
13 13
14ifdef CONFIG_MODULES 14ifdef CONFIG_MODULES
15obj-y += mips_ksyms.o module.o 15obj-y += mips_ksyms.o module.o
16obj-$(CONFIG_MIPS32) += module-elf32.o 16obj-$(CONFIG_32BIT) += module-elf32.o
17obj-$(CONFIG_MIPS64) += module-elf64.o 17obj-$(CONFIG_64BIT) += module-elf64.o
18endif 18endif
19 19
20obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o 20obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
@@ -45,8 +45,8 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
45obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o 45obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
46obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o 46obj-$(CONFIG_IRQ_MV64340) += irq-mv6434x.o
47 47
48obj-$(CONFIG_MIPS32) += scall32-o32.o 48obj-$(CONFIG_32BIT) += scall32-o32.o
49obj-$(CONFIG_MIPS64) += scall64-64.o 49obj-$(CONFIG_64BIT) += scall64-64.o
50obj-$(CONFIG_BINFMT_IRIX) += binfmt_irix.o 50obj-$(CONFIG_BINFMT_IRIX) += binfmt_irix.o
51obj-$(CONFIG_MIPS32_COMPAT) += ioctl32.o linux32.o signal32.o 51obj-$(CONFIG_MIPS32_COMPAT) += ioctl32.o linux32.o signal32.o
52obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o 52obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o
@@ -55,7 +55,7 @@ obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o ptrace32.o
55obj-$(CONFIG_KGDB) += gdb-low.o gdb-stub.o 55obj-$(CONFIG_KGDB) += gdb-low.o gdb-stub.o
56obj-$(CONFIG_PROC_FS) += proc.o 56obj-$(CONFIG_PROC_FS) += proc.o
57 57
58obj-$(CONFIG_MIPS64) += cpu-bugs64.o 58obj-$(CONFIG_64BIT) += cpu-bugs64.o
59 59
60obj-$(CONFIG_GEN_RTC) += genrtc.o 60obj-$(CONFIG_GEN_RTC) += genrtc.o
61 61
diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c
index ed47041f3030..6b645fbb1ddc 100644
--- a/arch/mips/kernel/binfmt_elfn32.c
+++ b/arch/mips/kernel/binfmt_elfn32.c
@@ -103,7 +103,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
103 * Convert jiffies to nanoseconds and seperate with 103 * Convert jiffies to nanoseconds and seperate with
104 * one divide. 104 * one divide.
105 */ 105 */
106 u64 nsec = (u64)jiffies * TICK_NSEC; 106 u64 nsec = (u64)jiffies * TICK_NSEC;
107 value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec); 107 value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec);
108 value->tv_usec /= NSEC_PER_USEC; 108 value->tv_usec /= NSEC_PER_USEC;
109} 109}
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index ee21b18c37a8..b4075e99c452 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -105,7 +105,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
105 * Convert jiffies to nanoseconds and seperate with 105 * Convert jiffies to nanoseconds and seperate with
106 * one divide. 106 * one divide.
107 */ 107 */
108 u64 nsec = (u64)jiffies * TICK_NSEC; 108 u64 nsec = (u64)jiffies * TICK_NSEC;
109 value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec); 109 value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec);
110 value->tv_usec /= NSEC_PER_USEC; 110 value->tv_usec /= NSEC_PER_USEC;
111} 111}
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 11ebe5d4c446..47a087b6c11b 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -137,7 +137,7 @@ static inline void check_mult_sh(void)
137 for (i = 0; i < 8; i++) 137 for (i = 0; i < 8; i++)
138 if (v1[i] != w[i]) 138 if (v1[i] != w[i])
139 bug = 1; 139 bug = 1;
140 140
141 if (bug == 0) { 141 if (bug == 0) {
142 printk("no.\n"); 142 printk("no.\n");
143 return; 143 return;
@@ -149,7 +149,7 @@ static inline void check_mult_sh(void)
149 for (i = 0; i < 8; i++) 149 for (i = 0; i < 8; i++)
150 if (v2[i] != w[i]) 150 if (v2[i] != w[i])
151 fix = 0; 151 fix = 0;
152 152
153 if (fix == 1) { 153 if (fix == 1) {
154 printk("yes.\n"); 154 printk("yes.\n");
155 return; 155 return;
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 4bb849582314..7685f8baf3f0 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -229,15 +229,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
229 break; 229 break;
230 case PRID_IMP_VR41XX: 230 case PRID_IMP_VR41XX:
231 switch (c->processor_id & 0xf0) { 231 switch (c->processor_id & 0xf0) {
232#ifndef CONFIG_VR4181
233 case PRID_REV_VR4111: 232 case PRID_REV_VR4111:
234 c->cputype = CPU_VR4111; 233 c->cputype = CPU_VR4111;
235 break; 234 break;
236#else
237 case PRID_REV_VR4181:
238 c->cputype = CPU_VR4181;
239 break;
240#endif
241 case PRID_REV_VR4121: 235 case PRID_REV_VR4121:
242 c->cputype = CPU_VR4121; 236 c->cputype = CPU_VR4121;
243 break; 237 break;
diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S
index ece6ddaf7011..512bedbfa7b9 100644
--- a/arch/mips/kernel/gdb-low.S
+++ b/arch/mips/kernel/gdb-low.S
@@ -13,13 +13,13 @@
13#include <asm/stackframe.h> 13#include <asm/stackframe.h>
14#include <asm/gdb-stub.h> 14#include <asm/gdb-stub.h>
15 15
16#ifdef CONFIG_MIPS32 16#ifdef CONFIG_32BIT
17#define DMFC0 mfc0 17#define DMFC0 mfc0
18#define DMTC0 mtc0 18#define DMTC0 mtc0
19#define LDC1 lwc1 19#define LDC1 lwc1
20#define SDC1 lwc1 20#define SDC1 lwc1
21#endif 21#endif
22#ifdef CONFIG_MIPS64 22#ifdef CONFIG_64BIT
23#define DMFC0 dmfc0 23#define DMFC0 dmfc0
24#define DMTC0 dmtc0 24#define DMTC0 dmtc0
25#define LDC1 ldc1 25#define LDC1 ldc1
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
index 269889302a27..d3fd1ab14274 100644
--- a/arch/mips/kernel/gdb-stub.c
+++ b/arch/mips/kernel/gdb-stub.c
@@ -687,8 +687,8 @@ void handle_exception (struct gdb_regs *regs)
687 * acquire the big kgdb spinlock 687 * acquire the big kgdb spinlock
688 */ 688 */
689 if (!spin_trylock(&kgdb_lock)) { 689 if (!spin_trylock(&kgdb_lock)) {
690 /* 690 /*
691 * some other CPU has the lock, we should go back to 691 * some other CPU has the lock, we should go back to
692 * receive the gdb_wait IPC 692 * receive the gdb_wait IPC
693 */ 693 */
694 return; 694 return;
@@ -703,7 +703,7 @@ void handle_exception (struct gdb_regs *regs)
703 async_bp.addr = 0; 703 async_bp.addr = 0;
704 } 704 }
705 705
706 /* 706 /*
707 * acquire the CPU spinlocks 707 * acquire the CPU spinlocks
708 */ 708 */
709 for (i = num_online_cpus()-1; i >= 0; i--) 709 for (i = num_online_cpus()-1; i >= 0; i--)
@@ -894,7 +894,7 @@ void handle_exception (struct gdb_regs *regs)
894 ptr = &input_buffer[1]; 894 ptr = &input_buffer[1];
895 if (hexToLong(&ptr, &addr)) 895 if (hexToLong(&ptr, &addr))
896 regs->cp0_epc = addr; 896 regs->cp0_epc = addr;
897 897
898 goto exit_kgdb_exception; 898 goto exit_kgdb_exception;
899 break; 899 break;
900 900
@@ -1001,7 +1001,7 @@ void breakpoint(void)
1001 return; 1001 return;
1002 1002
1003 __asm__ __volatile__( 1003 __asm__ __volatile__(
1004 ".globl breakinst\n\t" 1004 ".globl breakinst\n\t"
1005 ".set\tnoreorder\n\t" 1005 ".set\tnoreorder\n\t"
1006 "nop\n" 1006 "nop\n"
1007 "breakinst:\tbreak\n\t" 1007 "breakinst:\tbreak\n\t"
@@ -1014,7 +1014,7 @@ void breakpoint(void)
1014void async_breakpoint(void) 1014void async_breakpoint(void)
1015{ 1015{
1016 __asm__ __volatile__( 1016 __asm__ __volatile__(
1017 ".globl async_breakinst\n\t" 1017 ".globl async_breakinst\n\t"
1018 ".set\tnoreorder\n\t" 1018 ".set\tnoreorder\n\t"
1019 "nop\n" 1019 "nop\n"
1020 "async_breakinst:\tbreak\n\t" 1020 "async_breakinst:\tbreak\n\t"
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index a5b0a389b063..e7f6c1b90806 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -54,7 +54,7 @@ NESTED(except_vec3_generic, 0, sp)
54#endif 54#endif
55 mfc0 k1, CP0_CAUSE 55 mfc0 k1, CP0_CAUSE
56 andi k1, k1, 0x7c 56 andi k1, k1, 0x7c
57#ifdef CONFIG_MIPS64 57#ifdef CONFIG_64BIT
58 dsll k1, k1, 1 58 dsll k1, k1, 1
59#endif 59#endif
60 PTR_L k0, exception_handlers(k1) 60 PTR_L k0, exception_handlers(k1)
@@ -81,7 +81,7 @@ NESTED(except_vec3_r4000, 0, sp)
81 beq k1, k0, handle_vced 81 beq k1, k0, handle_vced
82 li k0, 14<<2 82 li k0, 14<<2
83 beq k1, k0, handle_vcei 83 beq k1, k0, handle_vcei
84#ifdef CONFIG_MIPS64 84#ifdef CONFIG_64BIT
85 dsll k1, k1, 1 85 dsll k1, k1, 1
86#endif 86#endif
87 .set pop 87 .set pop
@@ -244,12 +244,12 @@ NESTED(nmi_handler, PT_SIZE, sp)
244 start with an n and gas will believe \n is ok ... */ 244 start with an n and gas will believe \n is ok ... */
245 .macro __BUILD_verbose nexception 245 .macro __BUILD_verbose nexception
246 LONG_L a1, PT_EPC(sp) 246 LONG_L a1, PT_EPC(sp)
247#if CONFIG_MIPS32 247#ifdef CONFIG_32BIT
248 PRINT("Got \nexception at %08lx\012") 248 PRINT("Got \nexception at %08lx\012")
249#endif 249#endif
250#if CONFIG_MIPS64 250#ifdef CONFIG_64BIT
251 PRINT("Got \nexception at %016lx\012") 251 PRINT("Got \nexception at %016lx\012")
252#endif 252#endif
253 .endm 253 .endm
254 254
255 .macro __BUILD_count exception 255 .macro __BUILD_count exception
@@ -293,7 +293,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
293 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ 293 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
294 BUILD_HANDLER reserved reserved sti verbose /* others */ 294 BUILD_HANDLER reserved reserved sti verbose /* others */
295 295
296#ifdef CONFIG_MIPS64 296#ifdef CONFIG_64BIT
297/* A temporary overflow handler used by check_daddi(). */ 297/* A temporary overflow handler used by check_daddi(). */
298 298
299 __INIT 299 __INIT
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index a64e87d22014..2a1b45d66f04 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -107,7 +107,7 @@
107 .endm 107 .endm
108 108
109 .macro setup_c0_status_pri 109 .macro setup_c0_status_pri
110#ifdef CONFIG_MIPS64 110#ifdef CONFIG_64BIT
111 setup_c0_status ST0_KX 0 111 setup_c0_status ST0_KX 0
112#else 112#else
113 setup_c0_status 0 0 113 setup_c0_status 0 0
@@ -115,7 +115,7 @@
115 .endm 115 .endm
116 116
117 .macro setup_c0_status_sec 117 .macro setup_c0_status_sec
118#ifdef CONFIG_MIPS64 118#ifdef CONFIG_64BIT
119 setup_c0_status ST0_KX ST0_BEV 119 setup_c0_status ST0_KX ST0_BEV
120#else 120#else
121 setup_c0_status 0 ST0_BEV 121 setup_c0_status 0 ST0_BEV
@@ -215,7 +215,7 @@ NESTED(smp_bootstrap, 16, sp)
215 * slightly different layout ... 215 * slightly different layout ...
216 */ 216 */
217 page swapper_pg_dir, _PGD_ORDER 217 page swapper_pg_dir, _PGD_ORDER
218#ifdef CONFIG_MIPS64 218#ifdef CONFIG_64BIT
219 page invalid_pmd_table, _PMD_ORDER 219 page invalid_pmd_table, _PMD_ORDER
220#endif 220#endif
221 page invalid_pte_table, _PTE_ORDER 221 page invalid_pte_table, _PTE_ORDER
diff --git a/arch/mips/kernel/ioctl32.c b/arch/mips/kernel/ioctl32.c
index 519cd5d0aebb..c069719ff0d8 100644
--- a/arch/mips/kernel/ioctl32.c
+++ b/arch/mips/kernel/ioctl32.c
@@ -27,7 +27,7 @@ long sys_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg);
27#include "compat_ioctl.c" 27#include "compat_ioctl.c"
28 28
29typedef int (* ioctl32_handler_t)(unsigned int, unsigned int, unsigned long, struct file *); 29typedef int (* ioctl32_handler_t)(unsigned int, unsigned int, unsigned long, struct file *);
30 30
31#define COMPATIBLE_IOCTL(cmd) HANDLE_IOCTL((cmd),sys_ioctl) 31#define COMPATIBLE_IOCTL(cmd) HANDLE_IOCTL((cmd),sys_ioctl)
32#define HANDLE_IOCTL(cmd,handler) { (cmd), (ioctl32_handler_t)(handler), NULL }, 32#define HANDLE_IOCTL(cmd,handler) { (cmd), (ioctl32_handler_t)(handler), NULL },
33#define IOCTL_TABLE_START \ 33#define IOCTL_TABLE_START \
diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c
index 3f956f809fa4..4c114ae21793 100644
--- a/arch/mips/kernel/irixsig.c
+++ b/arch/mips/kernel/irixsig.c
@@ -155,13 +155,12 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info,
155 else 155 else
156 setup_irix_frame(ka, regs, sig, oldset); 156 setup_irix_frame(ka, regs, sig, oldset);
157 157
158 if (!(ka->sa.sa_flags & SA_NODEFER)) { 158 spin_lock_irq(&current->sighand->siglock);
159 spin_lock_irq(&current->sighand->siglock); 159 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
160 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 160 if (!(ka->sa.sa_flags & SA_NODEFER))
161 sigaddset(&current->blocked,sig); 161 sigaddset(&current->blocked,sig);
162 recalc_sigpending(); 162 recalc_sigpending();
163 spin_unlock_irq(&current->sighand->siglock); 163 spin_unlock_irq(&current->sighand->siglock);
164 }
165} 164}
166 165
167asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs) 166asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs)
@@ -178,7 +177,7 @@ asmlinkage int do_irix_signal(sigset_t *oldset, struct pt_regs *regs)
178 if (!user_mode(regs)) 177 if (!user_mode(regs))
179 return 1; 178 return 1;
180 179
181 if (try_to_freeze(0)) 180 if (try_to_freeze())
182 goto no_signal; 181 goto no_signal;
183 182
184 if (!oldset) 183 if (!oldset)
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 441157a1f994..7d93992e462c 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -77,7 +77,7 @@ int show_interrupts(struct seq_file *p, void *v)
77 if (i < NR_IRQS) { 77 if (i < NR_IRQS) {
78 spin_lock_irqsave(&irq_desc[i].lock, flags); 78 spin_lock_irqsave(&irq_desc[i].lock, flags);
79 action = irq_desc[i].action; 79 action = irq_desc[i].action;
80 if (!action) 80 if (!action)
81 goto skip; 81 goto skip;
82 seq_printf(p, "%3d: ",i); 82 seq_printf(p, "%3d: ",i);
83#ifndef CONFIG_SMP 83#ifndef CONFIG_SMP
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 993abc868e54..4613219dd73e 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -313,7 +313,7 @@ asmlinkage int sys32_sysinfo(struct sysinfo32 *info)
313 struct sysinfo s; 313 struct sysinfo s;
314 int ret, err; 314 int ret, err;
315 mm_segment_t old_fs = get_fs (); 315 mm_segment_t old_fs = get_fs ();
316 316
317 set_fs (KERNEL_DS); 317 set_fs (KERNEL_DS);
318 ret = sys_sysinfo(&s); 318 ret = sys_sysinfo(&s);
319 set_fs (old_fs); 319 set_fs (old_fs);
@@ -560,7 +560,7 @@ struct ipc64_perm32 {
560 compat_gid_t gid; 560 compat_gid_t gid;
561 compat_uid_t cuid; 561 compat_uid_t cuid;
562 compat_gid_t cgid; 562 compat_gid_t cgid;
563 compat_mode_t mode; 563 compat_mode_t mode;
564 unsigned short seq; 564 unsigned short seq;
565 unsigned short __pad1; 565 unsigned short __pad1;
566 unsigned int __unused1; 566 unsigned int __unused1;
@@ -1334,17 +1334,17 @@ asmlinkage int sys32_sendfile(int out_fd, int in_fd, compat_off_t *offset,
1334 mm_segment_t old_fs = get_fs(); 1334 mm_segment_t old_fs = get_fs();
1335 int ret; 1335 int ret;
1336 off_t of; 1336 off_t of;
1337 1337
1338 if (offset && get_user(of, offset)) 1338 if (offset && get_user(of, offset))
1339 return -EFAULT; 1339 return -EFAULT;
1340 1340
1341 set_fs(KERNEL_DS); 1341 set_fs(KERNEL_DS);
1342 ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count); 1342 ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count);
1343 set_fs(old_fs); 1343 set_fs(old_fs);
1344 1344
1345 if (offset && put_user(of, offset)) 1345 if (offset && put_user(of, offset))
1346 return -EFAULT; 1346 return -EFAULT;
1347 1347
1348 return ret; 1348 return ret;
1349} 1349}
1350 1350
@@ -1362,11 +1362,11 @@ static unsigned char socketcall_nargs[18]={AL(0),AL(3),AL(3),AL(3),AL(2),AL(3),
1362#undef AL 1362#undef AL
1363 1363
1364/* 1364/*
1365 * System call vectors. 1365 * System call vectors.
1366 * 1366 *
1367 * Argument checking cleaned up. Saved 20% in size. 1367 * Argument checking cleaned up. Saved 20% in size.
1368 * This function doesn't need to set the kernel lock because 1368 * This function doesn't need to set the kernel lock because
1369 * it is set by the callees. 1369 * it is set by the callees.
1370 */ 1370 */
1371 1371
1372asmlinkage long sys32_socketcall(int call, unsigned int *args32) 1372asmlinkage long sys32_socketcall(int call, unsigned int *args32)
@@ -1402,11 +1402,11 @@ asmlinkage long sys32_socketcall(int call, unsigned int *args32)
1402 /* copy_from_user should be SMP safe. */ 1402 /* copy_from_user should be SMP safe. */
1403 if (copy_from_user(a, args32, socketcall_nargs[call])) 1403 if (copy_from_user(a, args32, socketcall_nargs[call]))
1404 return -EFAULT; 1404 return -EFAULT;
1405 1405
1406 a0=a[0]; 1406 a0=a[0];
1407 a1=a[1]; 1407 a1=a[1];
1408 1408
1409 switch(call) 1409 switch(call)
1410 { 1410 {
1411 case SYS_SOCKET: 1411 case SYS_SOCKET:
1412 err = sys_socket(a0,a1,a[2]); 1412 err = sys_socket(a0,a1,a[2]);
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index eed29fc9dc82..86e42c633f73 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -35,7 +35,7 @@ EXPORT_SYMBOL(memcpy);
35EXPORT_SYMBOL(memmove); 35EXPORT_SYMBOL(memmove);
36EXPORT_SYMBOL(strcat); 36EXPORT_SYMBOL(strcat);
37EXPORT_SYMBOL(strchr); 37EXPORT_SYMBOL(strchr);
38#ifdef CONFIG_MIPS64 38#ifdef CONFIG_64BIT
39EXPORT_SYMBOL(strncmp); 39EXPORT_SYMBOL(strncmp);
40#endif 40#endif
41EXPORT_SYMBOL(strlen); 41EXPORT_SYMBOL(strlen);
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 6e70c42c2058..e4f2f8011387 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -70,7 +70,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
70 70
71 /* New thread loses kernel privileges. */ 71 /* New thread loses kernel privileges. */
72 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK); 72 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|KU_MASK);
73#ifdef CONFIG_MIPS64 73#ifdef CONFIG_64BIT
74 status &= ~ST0_FR; 74 status &= ~ST0_FR;
75 status |= (current->thread.mflags & MF_32BIT_REGS) ? 0 : ST0_FR; 75 status |= (current->thread.mflags & MF_32BIT_REGS) ? 0 : ST0_FR;
76#endif 76#endif
@@ -236,10 +236,10 @@ static int __init get_frame_info(struct mips_frame_info *info, void *func)
236 break; 236 break;
237 237
238 if ( 238 if (
239#ifdef CONFIG_MIPS32 239#ifdef CONFIG_32BIT
240 ip->i_format.opcode == sw_op && 240 ip->i_format.opcode == sw_op &&
241#endif 241#endif
242#ifdef CONFIG_MIPS64 242#ifdef CONFIG_64BIT
243 ip->i_format.opcode == sd_op && 243 ip->i_format.opcode == sd_op &&
244#endif 244#endif
245 ip->i_format.rs == 29) 245 ip->i_format.rs == 29)
@@ -353,7 +353,7 @@ schedule_timeout_caller:
353 353
354out: 354out:
355 355
356#ifdef CONFIG_MIPS64 356#ifdef CONFIG_64BIT
357 if (current->thread.mflags & MF_32BIT_REGS) /* Kludge for 32-bit ps */ 357 if (current->thread.mflags & MF_32BIT_REGS) /* Kludge for 32-bit ps */
358 pc &= 0xffffffffUL; 358 pc &= 0xffffffffUL;
359#endif 359#endif
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 92e70ca3bff9..0b571a5b4b83 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -124,7 +124,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
124 if (tsk_used_math(child)) { 124 if (tsk_used_math(child)) {
125 fpureg_t *fregs = get_fpu_regs(child); 125 fpureg_t *fregs = get_fpu_regs(child);
126 126
127#ifdef CONFIG_MIPS32 127#ifdef CONFIG_32BIT
128 /* 128 /*
129 * The odd registers are actually the high 129 * The odd registers are actually the high
130 * order bits of the values stored in the even 130 * order bits of the values stored in the even
@@ -135,7 +135,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
135 else 135 else
136 tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff); 136 tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
137#endif 137#endif
138#ifdef CONFIG_MIPS64 138#ifdef CONFIG_64BIT
139 tmp = fregs[addr - FPR_BASE]; 139 tmp = fregs[addr - FPR_BASE];
140#endif 140#endif
141 } else { 141 } else {
@@ -213,7 +213,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
213 sizeof(child->thread.fpu.hard)); 213 sizeof(child->thread.fpu.hard));
214 child->thread.fpu.hard.fcr31 = 0; 214 child->thread.fpu.hard.fcr31 = 0;
215 } 215 }
216#ifdef CONFIG_MIPS32 216#ifdef CONFIG_32BIT
217 /* 217 /*
218 * The odd registers are actually the high order bits 218 * The odd registers are actually the high order bits
219 * of the values stored in the even registers - unless 219 * of the values stored in the even registers - unless
@@ -227,7 +227,7 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
227 fregs[addr - FPR_BASE] |= data; 227 fregs[addr - FPR_BASE] |= data;
228 } 228 }
229#endif 229#endif
230#ifdef CONFIG_MIPS64 230#ifdef CONFIG_64BIT
231 fregs[addr - FPR_BASE] = data; 231 fregs[addr - FPR_BASE] = data;
232#endif 232#endif
233 break; 233 break;
@@ -304,14 +304,14 @@ out:
304static inline int audit_arch(void) 304static inline int audit_arch(void)
305{ 305{
306#ifdef CONFIG_CPU_LITTLE_ENDIAN 306#ifdef CONFIG_CPU_LITTLE_ENDIAN
307#ifdef CONFIG_MIPS64 307#ifdef CONFIG_64BIT
308 if (!(current->thread.mflags & MF_32BIT_REGS)) 308 if (!(current->thread.mflags & MF_32BIT_REGS))
309 return AUDIT_ARCH_MIPSEL64; 309 return AUDIT_ARCH_MIPSEL64;
310#endif /* MIPS64 */ 310#endif /* MIPS64 */
311 return AUDIT_ARCH_MIPSEL; 311 return AUDIT_ARCH_MIPSEL;
312 312
313#else /* big endian... */ 313#else /* big endian... */
314#ifdef CONFIG_MIPS64 314#ifdef CONFIG_64BIT
315 if (!(current->thread.mflags & MF_32BIT_REGS)) 315 if (!(current->thread.mflags & MF_32BIT_REGS))
316 return AUDIT_ARCH_MIPS64; 316 return AUDIT_ARCH_MIPS64;
317#endif /* MIPS64 */ 317#endif /* MIPS64 */
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 243e7b629af6..f10019640ee9 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -35,7 +35,7 @@
35/* 35/*
36 * FPU context is saved iff the process has used it's FPU in the current 36 * FPU context is saved iff the process has used it's FPU in the current
37 * time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user 37 * time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user
38 * space STATUS register should be 0, so that a process *always* starts its 38 * space STATUS register should be 0, so that a process *always* starts its
39 * userland with FPU disabled after each context switch. 39 * userland with FPU disabled after each context switch.
40 * 40 *
41 * FPU will be enabled as soon as the process accesses FPU again, through 41 * FPU will be enabled as soon as the process accesses FPU again, through
@@ -55,7 +55,7 @@ LEAF(resume)
55 cpu_save_nonscratch a0 55 cpu_save_nonscratch a0
56 sw ra, THREAD_REG31(a0) 56 sw ra, THREAD_REG31(a0)
57 57
58 /* 58 /*
59 * check if we need to save FPU registers 59 * check if we need to save FPU registers
60 */ 60 */
61 lw t3, TASK_THREAD_INFO(a0) 61 lw t3, TASK_THREAD_INFO(a0)
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index ebb643d8d14c..aba665bcb386 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -36,7 +36,7 @@
36LEAF(_save_fp_context) 36LEAF(_save_fp_context)
37 cfc1 t1, fcr31 37 cfc1 t1, fcr31
38 38
39#ifdef CONFIG_MIPS64 39#ifdef CONFIG_64BIT
40 /* Store the 16 odd double precision registers */ 40 /* Store the 16 odd double precision registers */
41 EX sdc1 $f1, SC_FPREGS+8(a0) 41 EX sdc1 $f1, SC_FPREGS+8(a0)
42 EX sdc1 $f3, SC_FPREGS+24(a0) 42 EX sdc1 $f3, SC_FPREGS+24(a0)
@@ -118,7 +118,7 @@ LEAF(_save_fp_context32)
118 */ 118 */
119LEAF(_restore_fp_context) 119LEAF(_restore_fp_context)
120 EX lw t0, SC_FPC_CSR(a0) 120 EX lw t0, SC_FPC_CSR(a0)
121#ifdef CONFIG_MIPS64 121#ifdef CONFIG_64BIT
122 EX ldc1 $f1, SC_FPREGS+8(a0) 122 EX ldc1 $f1, SC_FPREGS+8(a0)
123 EX ldc1 $f3, SC_FPREGS+24(a0) 123 EX ldc1 $f3, SC_FPREGS+24(a0)
124 EX ldc1 $f5, SC_FPREGS+40(a0) 124 EX ldc1 $f5, SC_FPREGS+40(a0)
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 1fc3b2eb12bd..e02b7722ccb8 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -33,7 +33,7 @@
33/* 33/*
34 * FPU context is saved iff the process has used it's FPU in the current 34 * FPU context is saved iff the process has used it's FPU in the current
35 * time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user 35 * time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user
36 * space STATUS register should be 0, so that a process *always* starts its 36 * space STATUS register should be 0, so that a process *always* starts its
37 * userland with FPU disabled after each context switch. 37 * userland with FPU disabled after each context switch.
38 * 38 *
39 * FPU will be enabled as soon as the process accesses FPU again, through 39 * FPU will be enabled as soon as the process accesses FPU again, through
@@ -105,7 +105,7 @@
105 * Save a thread's fp context. 105 * Save a thread's fp context.
106 */ 106 */
107LEAF(_save_fp) 107LEAF(_save_fp)
108#ifdef CONFIG_MIPS64 108#ifdef CONFIG_64BIT
109 mfc0 t1, CP0_STATUS 109 mfc0 t1, CP0_STATUS
110#endif 110#endif
111 fpu_save_double a0 t1 t0 t2 # clobbers t1 111 fpu_save_double a0 t1 t0 t2 # clobbers t1
@@ -142,7 +142,7 @@ LEAF(_init_fpu)
142 142
143 li t1, -1 # SNaN 143 li t1, -1 # SNaN
144 144
145#ifdef CONFIG_MIPS64 145#ifdef CONFIG_64BIT
146 sll t0, t0, 5 146 sll t0, t0, 5
147 bgez t0, 1f # 16 / 32 register mode? 147 bgez t0, 1f # 16 / 32 register mode?
148 148
@@ -164,7 +164,7 @@ LEAF(_init_fpu)
164 dmtc1 t1, $f31 164 dmtc1 t1, $f31
1651: 1651:
166#endif 166#endif
167 167
168#ifdef CONFIG_CPU_MIPS32 168#ifdef CONFIG_CPU_MIPS32
169 mtc1 t1, $f0 169 mtc1 t1, $f0
170 mtc1 t1, $f1 170 mtc1 t1, $f1
diff --git a/arch/mips/kernel/reset.c b/arch/mips/kernel/reset.c
index 7e0a9821931a..ae2ba67b7ef6 100644
--- a/arch/mips/kernel/reset.c
+++ b/arch/mips/kernel/reset.c
@@ -26,18 +26,13 @@ void machine_restart(char *command)
26 _machine_restart(command); 26 _machine_restart(command);
27} 27}
28 28
29EXPORT_SYMBOL(machine_restart);
30
31void machine_halt(void) 29void machine_halt(void)
32{ 30{
33 _machine_halt(); 31 _machine_halt();
34} 32}
35 33
36EXPORT_SYMBOL(machine_halt);
37
38void machine_power_off(void) 34void machine_power_off(void)
39{ 35{
40 _machine_power_off(); 36 _machine_power_off();
41} 37}
42 38
43EXPORT_SYMBOL(machine_power_off);
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 3a240e3e004c..12b531c295c4 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -241,7 +241,7 @@ static inline int parse_rd_cmdline(unsigned long* rd_start, unsigned long* rd_en
241 if (*tmp) 241 if (*tmp)
242 strcat(command_line, tmp); 242 strcat(command_line, tmp);
243 243
244#ifdef CONFIG_MIPS64 244#ifdef CONFIG_64BIT
245 /* HACK: Guess if the sign extension was forgotten */ 245 /* HACK: Guess if the sign extension was forgotten */
246 if (start > 0x0000000080000000 && start < 0x00000000ffffffff) 246 if (start > 0x0000000080000000 && start < 0x00000000ffffffff)
247 start |= 0xffffffff00000000; 247 start |= 0xffffffff00000000;
@@ -446,7 +446,7 @@ static inline void resource_init(void)
446{ 446{
447 int i; 447 int i;
448 448
449#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64) 449#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
450 /* 450 /*
451 * The 64bit code in 32bit object format trick can't represent 451 * The 64bit code in 32bit object format trick can't represent
452 * 64bit wide relocations for linker script symbols. 452 * 64bit wide relocations for linker script symbols.
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 65ee15396ffd..0209c1dd1429 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -425,13 +425,12 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info,
425 setup_frame(ka, regs, sig, oldset); 425 setup_frame(ka, regs, sig, oldset);
426#endif 426#endif
427 427
428 if (!(ka->sa.sa_flags & SA_NODEFER)) { 428 spin_lock_irq(&current->sighand->siglock);
429 spin_lock_irq(&current->sighand->siglock); 429 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
430 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 430 if (!(ka->sa.sa_flags & SA_NODEFER))
431 sigaddset(&current->blocked,sig); 431 sigaddset(&current->blocked,sig);
432 recalc_sigpending(); 432 recalc_sigpending();
433 spin_unlock_irq(&current->sighand->siglock); 433 spin_unlock_irq(&current->sighand->siglock);
434 }
435} 434}
436 435
437extern int do_signal32(sigset_t *oldset, struct pt_regs *regs); 436extern int do_signal32(sigset_t *oldset, struct pt_regs *regs);
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 1f3b19124c01..8ddfbd8d425a 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -558,7 +558,7 @@ static inline int setup_sigcontext32(struct pt_regs *regs,
558 if (!used_math()) 558 if (!used_math())
559 goto out; 559 goto out;
560 560
561 /* 561 /*
562 * Save FPU state to signal context. Signal handler will "inherit" 562 * Save FPU state to signal context. Signal handler will "inherit"
563 * current FPU state. 563 * current FPU state.
564 */ 564 */
@@ -751,13 +751,12 @@ static inline void handle_signal(unsigned long sig, siginfo_t *info,
751 else 751 else
752 setup_frame(ka, regs, sig, oldset); 752 setup_frame(ka, regs, sig, oldset);
753 753
754 if (!(ka->sa.sa_flags & SA_NODEFER)) { 754 spin_lock_irq(&current->sighand->siglock);
755 spin_lock_irq(&current->sighand->siglock); 755 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
756 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 756 if (!(ka->sa.sa_flags & SA_NODEFER))
757 sigaddset(&current->blocked,sig); 757 sigaddset(&current->blocked,sig);
758 recalc_sigpending(); 758 recalc_sigpending();
759 spin_unlock_irq(&current->sighand->siglock); 759 spin_unlock_irq(&current->sighand->siglock);
760 }
761} 760}
762 761
763int do_signal32(sigset_t *oldset, struct pt_regs *regs) 762int do_signal32(sigset_t *oldset, struct pt_regs *regs)
@@ -774,7 +773,7 @@ int do_signal32(sigset_t *oldset, struct pt_regs *regs)
774 if (!user_mode(regs)) 773 if (!user_mode(regs))
775 return 1; 774 return 1;
776 775
777 if (try_to_freeze(0)) 776 if (try_to_freeze())
778 goto no_signal; 777 goto no_signal;
779 778
780 if (!oldset) 779 if (!oldset)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 56c36e42e0a6..a53b1ed7b386 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -924,7 +924,7 @@ void __init per_cpu_trap_init(void)
924 * flag that some firmware may have left set and the TS bit (for 924 * flag that some firmware may have left set and the TS bit (for
925 * IP27). Set XX for ISA IV code to work. 925 * IP27). Set XX for ISA IV code to work.
926 */ 926 */
927#ifdef CONFIG_MIPS64 927#ifdef CONFIG_64BIT
928 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 928 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
929#endif 929#endif
930 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) 930 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 3f24a1d45865..36c5212e0928 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -240,7 +240,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
240 break; 240 break;
241 241
242 case lwu_op: 242 case lwu_op:
243#ifdef CONFIG_MIPS64 243#ifdef CONFIG_64BIT
244 /* 244 /*
245 * A 32-bit kernel might be running on a 64-bit processor. But 245 * A 32-bit kernel might be running on a 64-bit processor. But
246 * if we're on a 32-bit processor and an i-cache incoherency 246 * if we're on a 32-bit processor and an i-cache incoherency
@@ -278,13 +278,13 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
278 *newvalue = value; 278 *newvalue = value;
279 *regptr = &regs->regs[insn.i_format.rt]; 279 *regptr = &regs->regs[insn.i_format.rt];
280 break; 280 break;
281#endif /* CONFIG_MIPS64 */ 281#endif /* CONFIG_64BIT */
282 282
283 /* Cannot handle 64-bit instructions in 32-bit kernel */ 283 /* Cannot handle 64-bit instructions in 32-bit kernel */
284 goto sigill; 284 goto sigill;
285 285
286 case ld_op: 286 case ld_op:
287#ifdef CONFIG_MIPS64 287#ifdef CONFIG_64BIT
288 /* 288 /*
289 * A 32-bit kernel might be running on a 64-bit processor. But 289 * A 32-bit kernel might be running on a 64-bit processor. But
290 * if we're on a 32-bit processor and an i-cache incoherency 290 * if we're on a 32-bit processor and an i-cache incoherency
@@ -320,7 +320,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
320 *newvalue = value; 320 *newvalue = value;
321 *regptr = &regs->regs[insn.i_format.rt]; 321 *regptr = &regs->regs[insn.i_format.rt];
322 break; 322 break;
323#endif /* CONFIG_MIPS64 */ 323#endif /* CONFIG_64BIT */
324 324
325 /* Cannot handle 64-bit instructions in 32-bit kernel */ 325 /* Cannot handle 64-bit instructions in 32-bit kernel */
326 goto sigill; 326 goto sigill;
@@ -392,7 +392,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
392 break; 392 break;
393 393
394 case sd_op: 394 case sd_op:
395#ifdef CONFIG_MIPS64 395#ifdef CONFIG_64BIT
396 /* 396 /*
397 * A 32-bit kernel might be running on a 64-bit processor. But 397 * A 32-bit kernel might be running on a 64-bit processor. But
398 * if we're on a 32-bit processor and an i-cache incoherency 398 * if we're on a 32-bit processor and an i-cache incoherency
@@ -428,7 +428,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
428 if (res) 428 if (res)
429 goto fault; 429 goto fault;
430 break; 430 break;
431#endif /* CONFIG_MIPS64 */ 431#endif /* CONFIG_64BIT */
432 432
433 /* Cannot handle 64-bit instructions in 32-bit kernel */ 433 /* Cannot handle 64-bit instructions in 32-bit kernel */
434 goto sigill; 434 goto sigill;
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index e830d788c106..482ac310c937 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -15,7 +15,7 @@ SECTIONS
15 /* This is the value for an Origin kernel, taken from an IRIX kernel. */ 15 /* This is the value for an Origin kernel, taken from an IRIX kernel. */
16 /* . = 0xc00000000001c000; */ 16 /* . = 0xc00000000001c000; */
17 17
18 /* Set the vaddr for the text segment to a value 18 /* Set the vaddr for the text segment to a value
19 >= 0xa800 0000 0001 9000 if no symmon is going to configured 19 >= 0xa800 0000 0001 9000 if no symmon is going to configured
20 >= 0xa800 0000 0030 0000 otherwise */ 20 >= 0xa800 0000 0030 0000 otherwise */
21 21
diff --git a/arch/mips/lasat/at93c.c b/arch/mips/lasat/at93c.c
index f6add041ebec..ca26e554615e 100644
--- a/arch/mips/lasat/at93c.c
+++ b/arch/mips/lasat/at93c.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Atmel AT93C46 serial eeprom driver 2 * Atmel AT93C46 serial eeprom driver
3 * 3 *
4 * Brian Murphy <brian.murphy@eicon.com> 4 * Brian Murphy <brian.murphy@eicon.com>
5 * 5 *
6 */ 6 */
7#include <linux/kernel.h> 7#include <linux/kernel.h>
@@ -21,12 +21,12 @@
21 21
22struct at93c_defs *at93c; 22struct at93c_defs *at93c;
23 23
24static void at93c_reg_write(u32 val) 24static void at93c_reg_write(u32 val)
25{ 25{
26 *at93c->reg = val; 26 *at93c->reg = val;
27} 27}
28 28
29static u32 at93c_reg_read(void) 29static u32 at93c_reg_read(void)
30{ 30{
31 u32 tmp = *at93c->reg; 31 u32 tmp = *at93c->reg;
32 return tmp; 32 return tmp;
@@ -81,7 +81,7 @@ static u8 at93c_read_byte(void)
81} 81}
82 82
83static void at93c_write_bits(u32 data, int size) 83static void at93c_write_bits(u32 data, int size)
84{ 84{
85 int i; 85 int i;
86 int shift = size - 1; 86 int shift = size - 1;
87 u32 mask = (1 << shift); 87 u32 mask = (1 << shift);
@@ -90,7 +90,7 @@ static void at93c_write_bits(u32 data, int size)
90 at93c_write_databit((data & mask) >> shift); 90 at93c_write_databit((data & mask) >> shift);
91 data <<= 1; 91 data <<= 1;
92 } 92 }
93} 93}
94 94
95static void at93c_init_op(void) 95static void at93c_init_op(void)
96{ 96{
@@ -104,8 +104,8 @@ static void at93c_end_op(void)
104 lasat_ndelay(250); 104 lasat_ndelay(250);
105} 105}
106 106
107static void at93c_wait(void) 107static void at93c_wait(void)
108{ 108{
109 at93c_init_op(); 109 at93c_init_op();
110 while (!at93c_read_databit()) 110 while (!at93c_read_databit())
111 ; 111 ;
diff --git a/arch/mips/lasat/at93c.h b/arch/mips/lasat/at93c.h
index a912ac2171b0..cfe2f99b1d44 100644
--- a/arch/mips/lasat/at93c.h
+++ b/arch/mips/lasat/at93c.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Atmel AT93C46 serial eeprom driver 2 * Atmel AT93C46 serial eeprom driver
3 * 3 *
4 * Brian Murphy <brian.murphy@eicon.com> 4 * Brian Murphy <brian.murphy@eicon.com>
5 * 5 *
6 */ 6 */
7 7
diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c
index 7bbf6cf923c9..9d7812e03dcd 100644
--- a/arch/mips/lasat/ds1603.c
+++ b/arch/mips/lasat/ds1603.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Dallas Semiconductors 1603 RTC driver 2 * Dallas Semiconductors 1603 RTC driver
3 * 3 *
4 * Brian Murphy <brian@murphy.dk> 4 * Brian Murphy <brian@murphy.dk>
5 * 5 *
6 */ 6 */
7#include <linux/kernel.h> 7#include <linux/kernel.h>
@@ -20,12 +20,12 @@
20struct ds_defs *ds1603 = NULL; 20struct ds_defs *ds1603 = NULL;
21 21
22/* HW specific register functions */ 22/* HW specific register functions */
23static void rtc_reg_write(unsigned long val) 23static void rtc_reg_write(unsigned long val)
24{ 24{
25 *ds1603->reg = val; 25 *ds1603->reg = val;
26} 26}
27 27
28static unsigned long rtc_reg_read(void) 28static unsigned long rtc_reg_read(void)
29{ 29{
30 unsigned long tmp = *ds1603->reg; 30 unsigned long tmp = *ds1603->reg;
31 return tmp; 31 return tmp;
@@ -80,7 +80,7 @@ static unsigned int rtc_read_databit(void)
80{ 80{
81 unsigned int data; 81 unsigned int data;
82 82
83 data = (rtc_datareg_read() & (1 << ds1603->data_read_shift)) 83 data = (rtc_datareg_read() & (1 << ds1603->data_read_shift))
84 >> ds1603->data_read_shift; 84 >> ds1603->data_read_shift;
85 rtc_cycle_clock(rtc_reg_read()); 85 rtc_cycle_clock(rtc_reg_read());
86 return data; 86 return data;
diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h
index 55f3b0423c20..c2e5c76a379d 100644
--- a/arch/mips/lasat/ds1603.h
+++ b/arch/mips/lasat/ds1603.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Dallas Semiconductors 1603 RTC driver 2 * Dallas Semiconductors 1603 RTC driver
3 * 3 *
4 * Brian Murphy <brian@murphy.dk> 4 * Brian Murphy <brian@murphy.dk>
5 * 5 *
6 */ 6 */
7#ifndef __DS1603_H 7#ifndef __DS1603_H
diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile
index 18b6430f11be..35ecd6483ef6 100644
--- a/arch/mips/lasat/image/Makefile
+++ b/arch/mips/lasat/image/Makefile
@@ -21,7 +21,7 @@ LDSCRIPT= -L$(obj) -Tromscript.normal
21HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \ 21HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \
22 -D_kernel_entry=0x$(KERNEL_ENTRY) \ 22 -D_kernel_entry=0x$(KERNEL_ENTRY) \
23 -D VERSION="\"$(Version)\"" \ 23 -D VERSION="\"$(Version)\"" \
24 -D TIMESTAMP=$(shell date +%s) 24 -D TIMESTAMP=$(shell date +%s)
25 25
26$(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE) 26$(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE)
27 $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $< 27 $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $<
diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S
index 426bd7de17bb..efb95f2609c2 100644
--- a/arch/mips/lasat/image/head.S
+++ b/arch/mips/lasat/image/head.S
@@ -27,5 +27,5 @@ reldate:
27 .word TIMESTAMP 27 .word TIMESTAMP
28 28
29 .org 0x50 29 .org 0x50
30release: 30release:
31 .string VERSION 31 .string VERSION
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index 1148a2d20aa7..c90da1639440 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -15,7 +15,7 @@
15 * with this program; if not, write to the Free Software Foundation, Inc., 15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 * 17 *
18 * Routines for generic manipulation of the interrupts found on the 18 * Routines for generic manipulation of the interrupts found on the
19 * Lasat boards. 19 * Lasat boards.
20 */ 20 */
21#include <linux/init.h> 21#include <linux/init.h>
@@ -101,7 +101,7 @@ static unsigned long get_int_status_100(void)
101 return *lasat_int_status & *lasat_int_mask; 101 return *lasat_int_status & *lasat_int_mask;
102} 102}
103 103
104static unsigned long get_int_status_200(void) 104static unsigned long get_int_status_200(void)
105{ 105{
106 unsigned long int_status; 106 unsigned long int_status;
107 107
diff --git a/arch/mips/lasat/lasat_board.c b/arch/mips/lasat/lasat_board.c
index 8c784bcf1111..fc9b0e2a6be1 100644
--- a/arch/mips/lasat/lasat_board.c
+++ b/arch/mips/lasat/lasat_board.c
@@ -67,7 +67,7 @@ static void init_flash_sizes(void)
67 67
68 if (mips_machtype == MACH_LASAT_100) { 68 if (mips_machtype == MACH_LASAT_100) {
69 lasat_board_info.li_flash_base = 0x1e000000; 69 lasat_board_info.li_flash_base = 0x1e000000;
70 70
71 lb[LASAT_MTD_BOOTLOADER] = 0x1e400000; 71 lb[LASAT_MTD_BOOTLOADER] = 0x1e400000;
72 72
73 if (lasat_board_info.li_flash_size > 0x200000) { 73 if (lasat_board_info.li_flash_size > 0x200000) {
@@ -103,7 +103,7 @@ int lasat_init_board_info(void)
103 memset(&lasat_board_info, 0, sizeof(lasat_board_info)); 103 memset(&lasat_board_info, 0, sizeof(lasat_board_info));
104 104
105 /* First read the EEPROM info */ 105 /* First read the EEPROM info */
106 EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info, 106 EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
107 sizeof(struct lasat_eeprom_struct)); 107 sizeof(struct lasat_eeprom_struct));
108 108
109 /* Check the CRC */ 109 /* Check the CRC */
@@ -188,7 +188,7 @@ int lasat_init_board_info(void)
188 case 0x1: 188 case 0x1:
189 lasat_board_info.li_cpu_hz = 189 lasat_board_info.li_cpu_hz =
190 lasat_board_info.li_bus_hz + 190 lasat_board_info.li_bus_hz +
191 (lasat_board_info.li_bus_hz >> 1); 191 (lasat_board_info.li_bus_hz >> 1);
192 break; 192 break;
193 case 0x2: 193 case 0x2:
194 lasat_board_info.li_cpu_hz = 194 lasat_board_info.li_cpu_hz =
@@ -271,7 +271,7 @@ void lasat_write_eeprom_info(void)
271 lasat_board_info.li_eeprom_info.crc32 = crc; 271 lasat_board_info.li_eeprom_info.crc32 = crc;
272 272
273 /* Write the EEPROM info */ 273 /* Write the EEPROM info */
274 EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info, 274 EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
275 sizeof(struct lasat_eeprom_struct)); 275 sizeof(struct lasat_eeprom_struct));
276} 276}
277 277
diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c
index 5637cd153926..9ae82c3ffb07 100644
--- a/arch/mips/lasat/picvue.c
+++ b/arch/mips/lasat/picvue.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Picvue PVC160206 display driver 2 * Picvue PVC160206 display driver
3 * 3 *
4 * Brian Murphy <brian@murphy.dk> 4 * Brian Murphy <brian@murphy.dk>
5 * 5 *
6 */ 6 */
7#include <linux/kernel.h> 7#include <linux/kernel.h>
@@ -24,12 +24,12 @@ struct pvc_defs *picvue = NULL;
24 24
25DECLARE_MUTEX(pvc_sem); 25DECLARE_MUTEX(pvc_sem);
26 26
27static void pvc_reg_write(u32 val) 27static void pvc_reg_write(u32 val)
28{ 28{
29 *picvue->reg = val; 29 *picvue->reg = val;
30} 30}
31 31
32static u32 pvc_reg_read(void) 32static u32 pvc_reg_read(void)
33{ 33{
34 u32 tmp = *picvue->reg; 34 u32 tmp = *picvue->reg;
35 return tmp; 35 return tmp;
@@ -65,12 +65,12 @@ static u8 pvc_read_data(void)
65{ 65{
66 u32 data = pvc_reg_read(); 66 u32 data = pvc_reg_read();
67 u8 byte; 67 u8 byte;
68 data |= picvue->rw; 68 data |= picvue->rw;
69 data &= ~picvue->rs; 69 data &= ~picvue->rs;
70 pvc_reg_write(data); 70 pvc_reg_write(data);
71 ndelay(40); 71 ndelay(40);
72 byte = pvc_read_byte(data); 72 byte = pvc_read_byte(data);
73 data |= picvue->rs; 73 data |= picvue->rs;
74 pvc_reg_write(data); 74 pvc_reg_write(data);
75 return byte; 75 return byte;
76} 76}
diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h
index 74a39039135d..2a96bf971897 100644
--- a/arch/mips/lasat/picvue.h
+++ b/arch/mips/lasat/picvue.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Picvue PVC160206 display driver 2 * Picvue PVC160206 display driver
3 * 3 *
4 * Brian Murphy <brian.murphy@eicon.com> 4 * Brian Murphy <brian.murphy@eicon.com>
5 * 5 *
6 */ 6 */
7#include <asm/semaphore.h> 7#include <asm/semaphore.h>
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
index eaa2b4625124..cce7cddcdb08 100644
--- a/arch/mips/lasat/picvue_proc.c
+++ b/arch/mips/lasat/picvue_proc.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Picvue PVC160206 display driver 2 * Picvue PVC160206 display driver
3 * 3 *
4 * Brian Murphy <brian.murphy@eicon.com> 4 * Brian Murphy <brian.murphy@eicon.com>
5 * 5 *
6 */ 6 */
7#include <linux/kernel.h> 7#include <linux/kernel.h>
@@ -51,10 +51,10 @@ static int pvc_proc_read_line(char *page, char **start,
51 page += sprintf(page, "%s\n", pvc_lines[lineno]); 51 page += sprintf(page, "%s\n", pvc_lines[lineno]);
52 up(&pvc_sem); 52 up(&pvc_sem);
53 53
54 return page - origpage; 54 return page - origpage;
55} 55}
56 56
57static int pvc_proc_write_line(struct file *file, const char *buffer, 57static int pvc_proc_write_line(struct file *file, const char *buffer,
58 unsigned long count, void *data) 58 unsigned long count, void *data)
59{ 59{
60 int origcount = count; 60 int origcount = count;
@@ -119,7 +119,7 @@ static int pvc_proc_read_scroll(char *page, char **start,
119 page += sprintf(page, "%d\n", scroll_dir * scroll_interval); 119 page += sprintf(page, "%d\n", scroll_dir * scroll_interval);
120 up(&pvc_sem); 120 up(&pvc_sem);
121 121
122 return page - origpage; 122 return page - origpage;
123} 123}
124 124
125 125
diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c
index ca62881c9e52..88c7ab871ec4 100644
--- a/arch/mips/lasat/prom.c
+++ b/arch/mips/lasat/prom.c
@@ -42,7 +42,7 @@ static void null_prom_putc(char c)
42/* these are functions provided by the bootloader */ 42/* these are functions provided by the bootloader */
43static void (* prom_putc)(char c) = null_prom_putc; 43static void (* prom_putc)(char c) = null_prom_putc;
44void (* prom_printf)(const char * fmt, ...) = null_prom_printf; 44void (* prom_printf)(const char * fmt, ...) = null_prom_printf;
45void (* prom_display)(const char *string, int pos, int clear) = 45void (* prom_display)(const char *string, int pos, int clear) =
46 null_prom_display; 46 null_prom_display;
47void (* prom_monitor)(void) = null_prom_monitor; 47void (* prom_monitor)(void) = null_prom_monitor;
48 48
diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c
index 37e4912ee1c8..8d7d7a454f9a 100644
--- a/arch/mips/lasat/reset.c
+++ b/arch/mips/lasat/reset.c
@@ -1,4 +1,4 @@
1/* 1/*
2 * Thomas Horsten <thh@lasat.com> 2 * Thomas Horsten <thh@lasat.com>
3 * Copyright (C) 2000 LASAT Networks A/S. 3 * Copyright (C) 2000 LASAT Networks A/S.
4 * 4 *
diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c
index e371ed5cbe34..f2604fab9a99 100644
--- a/arch/mips/lasat/setup.c
+++ b/arch/mips/lasat/setup.c
@@ -105,7 +105,7 @@ static int lasat_panic_prom_monitor(struct notifier_block *this,
105 return NOTIFY_DONE; 105 return NOTIFY_DONE;
106} 106}
107 107
108static struct notifier_block lasat_panic_block[] = 108static struct notifier_block lasat_panic_block[] =
109{ 109{
110 { lasat_panic_display, NULL, INT_MAX }, 110 { lasat_panic_display, NULL, INT_MAX },
111 { lasat_panic_prom_monitor, NULL, INT_MIN } 111 { lasat_panic_prom_monitor, NULL, INT_MIN }
@@ -120,7 +120,7 @@ static void lasat_timer_setup(struct irqaction *irq)
120{ 120{
121 121
122 write_c0_compare( 122 write_c0_compare(
123 read_c0_count() + 123 read_c0_count() +
124 mips_hpt_frequency / HZ); 124 mips_hpt_frequency / HZ);
125 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); 125 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5);
126} 126}
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
index 1c0cc620a43f..8ff43a1c1e99 100644
--- a/arch/mips/lasat/sysctl.c
+++ b/arch/mips/lasat/sysctl.c
@@ -37,14 +37,14 @@
37 37
38static DECLARE_MUTEX(lasat_info_sem); 38static DECLARE_MUTEX(lasat_info_sem);
39 39
40/* Strategy function to write EEPROM after changing string entry */ 40/* Strategy function to write EEPROM after changing string entry */
41int sysctl_lasatstring(ctl_table *table, int *name, int nlen, 41int sysctl_lasatstring(ctl_table *table, int *name, int nlen,
42 void *oldval, size_t *oldlenp, 42 void *oldval, size_t *oldlenp,
43 void *newval, size_t newlen, void **context) 43 void *newval, size_t newlen, void **context)
44{ 44{
45 int r; 45 int r;
46 down(&lasat_info_sem); 46 down(&lasat_info_sem);
47 r = sysctl_string(table, name, 47 r = sysctl_string(table, name,
48 nlen, oldval, oldlenp, newval, newlen, context); 48 nlen, oldval, oldlenp, newval, newlen, context);
49 if (r < 0) { 49 if (r < 0) {
50 up(&lasat_info_sem); 50 up(&lasat_info_sem);
@@ -74,7 +74,7 @@ int proc_dolasatstring(ctl_table *table, int write, struct file *filp,
74 return 0; 74 return 0;
75} 75}
76 76
77/* proc function to write EEPROM after changing int entry */ 77/* proc function to write EEPROM after changing int entry */
78int proc_dolasatint(ctl_table *table, int write, struct file *filp, 78int proc_dolasatint(ctl_table *table, int write, struct file *filp,
79 void *buffer, size_t *lenp, loff_t *ppos) 79 void *buffer, size_t *lenp, loff_t *ppos)
80{ 80{
@@ -93,7 +93,7 @@ int proc_dolasatint(ctl_table *table, int write, struct file *filp,
93static int rtctmp; 93static int rtctmp;
94 94
95#ifdef CONFIG_DS1603 95#ifdef CONFIG_DS1603
96/* proc function to read/write RealTime Clock */ 96/* proc function to read/write RealTime Clock */
97int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, 97int proc_dolasatrtc(ctl_table *table, int write, struct file *filp,
98 void *buffer, size_t *lenp, loff_t *ppos) 98 void *buffer, size_t *lenp, loff_t *ppos)
99{ 99{
@@ -165,9 +165,9 @@ static char lasat_bcastaddr[16];
165void update_bcastaddr(void) 165void update_bcastaddr(void)
166{ 166{
167 unsigned int ip; 167 unsigned int ip;
168 168
169 ip = (lasat_board_info.li_eeprom_info.ipaddr & 169 ip = (lasat_board_info.li_eeprom_info.ipaddr &
170 lasat_board_info.li_eeprom_info.netmask) | 170 lasat_board_info.li_eeprom_info.netmask) |
171 ~lasat_board_info.li_eeprom_info.netmask; 171 ~lasat_board_info.li_eeprom_info.netmask;
172 172
173 sprintf(lasat_bcastaddr, "%d.%d.%d.%d", 173 sprintf(lasat_bcastaddr, "%d.%d.%d.%d",
@@ -205,7 +205,7 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp,
205 break; 205 break;
206 len++; 206 len++;
207 } 207 }
208 if (len >= sizeof(proc_lasat_ipbuf)-1) 208 if (len >= sizeof(proc_lasat_ipbuf)-1)
209 len = sizeof(proc_lasat_ipbuf) - 1; 209 len = sizeof(proc_lasat_ipbuf) - 1;
210 if (copy_from_user(proc_lasat_ipbuf, buffer, len)) 210 if (copy_from_user(proc_lasat_ipbuf, buffer, len))
211 { 211 {
@@ -249,8 +249,8 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp,
249} 249}
250#endif /* defined(CONFIG_INET) */ 250#endif /* defined(CONFIG_INET) */
251 251
252static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen, 252static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen,
253 void *oldval, size_t *oldlenp, 253 void *oldval, size_t *oldlenp,
254 void *newval, size_t newlen, 254 void *newval, size_t newlen,
255 void **context) 255 void **context)
256{ 256{
@@ -293,7 +293,7 @@ int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp,
293 if (!strcmp(filp->f_dentry->d_name.name, "debugaccess")) 293 if (!strcmp(filp->f_dentry->d_name.name, "debugaccess"))
294 lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess; 294 lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess;
295 } 295 }
296 lasat_write_eeprom_info(); 296 lasat_write_eeprom_info();
297 up(&lasat_info_sem); 297 up(&lasat_info_sem);
298 return 0; 298 return 0;
299} 299}
@@ -316,8 +316,8 @@ static ctl_table lasat_table[] = {
316 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, 316 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec},
317 {LASAT_NETMASK, "netmask", &lasat_board_info.li_eeprom_info.netmask, sizeof(int), 317 {LASAT_NETMASK, "netmask", &lasat_board_info.li_eeprom_info.netmask, sizeof(int),
318 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec}, 318 0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec},
319 {LASAT_BCAST, "bcastaddr", &lasat_bcastaddr, 319 {LASAT_BCAST, "bcastaddr", &lasat_bcastaddr,
320 sizeof(lasat_bcastaddr), 0600, NULL, 320 sizeof(lasat_bcastaddr), 0600, NULL,
321 &proc_dostring, &sysctl_string}, 321 &proc_dostring, &sysctl_string},
322#endif 322#endif
323 {LASAT_PASSWORD, "passwd_hash", &lasat_board_info.li_eeprom_info.passwd_hash, sizeof(lasat_board_info.li_eeprom_info.passwd_hash), 323 {LASAT_PASSWORD, "passwd_hash", &lasat_board_info.li_eeprom_info.passwd_hash, sizeof(lasat_board_info.li_eeprom_info.passwd_hash),
diff --git a/arch/mips/lib-32/Makefile b/arch/mips/lib-32/Makefile
index fd6a2bafdfcf..ad285786e74b 100644
--- a/arch/mips/lib-32/Makefile
+++ b/arch/mips/lib-32/Makefile
@@ -2,7 +2,7 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial.o memset.o watch.o 5lib-y += csum_partial.o memset.o watch.o
6 6
7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o 7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o 8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
diff --git a/arch/mips/lib-64/Makefile b/arch/mips/lib-64/Makefile
index fd6a2bafdfcf..ad285786e74b 100644
--- a/arch/mips/lib-64/Makefile
+++ b/arch/mips/lib-64/Makefile
@@ -2,7 +2,7 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial.o memset.o watch.o 5lib-y += csum_partial.o memset.o watch.o
6 6
7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o 7obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o 8obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index afa8eae18ff6..90ee8d43261f 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -79,7 +79,7 @@
79/* 79/*
80 * Only on the 64-bit kernel we can made use of 64-bit registers. 80 * Only on the 64-bit kernel we can made use of 64-bit registers.
81 */ 81 */
82#ifdef CONFIG_MIPS64 82#ifdef CONFIG_64BIT
83#define USE_DOUBLE 83#define USE_DOUBLE
84#endif 84#endif
85 85
@@ -101,7 +101,7 @@
101#define NBYTES 8 101#define NBYTES 8
102#define LOG_NBYTES 3 102#define LOG_NBYTES 3
103 103
104/* 104/*
105 * As we are sharing code base with the mips32 tree (which use the o32 ABI 105 * As we are sharing code base with the mips32 tree (which use the o32 ABI
106 * register definitions). We need to redefine the register definitions from 106 * register definitions). We need to redefine the register definitions from
107 * the n64 ABI register naming to the o32 ABI register naming. 107 * the n64 ABI register naming to the o32 ABI register naming.
@@ -118,7 +118,7 @@
118#define t5 $13 118#define t5 $13
119#define t6 $14 119#define t6 $14
120#define t7 $15 120#define t7 $15
121 121
122#else 122#else
123 123
124#define LOAD lw 124#define LOAD lw
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 20a552be02ee..99c550632d44 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -320,7 +320,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
320 case cop1_op: 320 case cop1_op:
321 switch (MIPSInst_RS(ir)) { 321 switch (MIPSInst_RS(ir)) {
322 322
323#if __mips64 && !defined(SINGLE_ONLY_FPU) 323#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
324 case dmfc_op: 324 case dmfc_op:
325 /* copregister fs -> gpr[rt] */ 325 /* copregister fs -> gpr[rt] */
326 if (MIPSInst_RT(ir) != 0) { 326 if (MIPSInst_RT(ir) != 0) {
@@ -805,7 +805,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
805 ieee754dp d; 805 ieee754dp d;
806 ieee754sp s; 806 ieee754sp s;
807 int w; 807 int w;
808#if __mips64 808#ifdef __mips64
809 s64 l; 809 s64 l;
810#endif 810#endif
811 } rv; /* resulting value */ 811 } rv; /* resulting value */
@@ -950,7 +950,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
950 } 950 }
951#endif /* __mips >= 2 */ 951#endif /* __mips >= 2 */
952 952
953#if __mips64 && !defined(SINGLE_ONLY_FPU) 953#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
954 case fcvtl_op:{ 954 case fcvtl_op:{
955 ieee754sp fs; 955 ieee754sp fs;
956 956
@@ -1125,7 +1125,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1125 } 1125 }
1126#endif 1126#endif
1127 1127
1128#if __mips64 && !defined(SINGLE_ONLY_FPU) 1128#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
1129 case fcvtl_op:{ 1129 case fcvtl_op:{
1130 ieee754dp fs; 1130 ieee754dp fs;
1131 1131
@@ -1203,7 +1203,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1203 break; 1203 break;
1204 } 1204 }
1205 1205
1206#if __mips64 && !defined(SINGLE_ONLY_FPU) 1206#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
1207 case l_fmt:{ 1207 case l_fmt:{
1208 switch (MIPSInst_FUNC(ir)) { 1208 switch (MIPSInst_FUNC(ir)) {
1209 case fcvts_op: 1209 case fcvts_op:
@@ -1267,7 +1267,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1267 case w_fmt: 1267 case w_fmt:
1268 SITOREG(rv.w, MIPSInst_FD(ir)); 1268 SITOREG(rv.w, MIPSInst_FD(ir));
1269 break; 1269 break;
1270#if __mips64 && !defined(SINGLE_ONLY_FPU) 1270#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
1271 case l_fmt: 1271 case l_fmt:
1272 DITOREG(rv.l, MIPSInst_FD(ir)); 1272 DITOREG(rv.l, MIPSInst_FD(ir));
1273 break; 1273 break;
diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c
index 04397fec30fc..4002f0cf79f3 100644
--- a/arch/mips/math-emu/kernel_linkage.c
+++ b/arch/mips/math-emu/kernel_linkage.c
@@ -86,7 +86,7 @@ int fpu_emulator_restore_context(struct sigcontext *sc)
86 return err; 86 return err;
87} 87}
88 88
89#ifdef CONFIG_MIPS64 89#ifdef CONFIG_64BIT
90/* 90/*
91 * This is the o32 version 91 * This is the o32 version
92 */ 92 */
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 8f1d875217a2..19d4b0792460 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -122,7 +122,7 @@ void __init arch_init_irq(void)
122 int i; 122 int i;
123 123
124 atlas_hw0_icregs = (struct atlas_ictrl_regs *)ioremap (ATLAS_ICTRL_REGS_BASE, sizeof(struct atlas_ictrl_regs *)); 124 atlas_hw0_icregs = (struct atlas_ictrl_regs *)ioremap (ATLAS_ICTRL_REGS_BASE, sizeof(struct atlas_ictrl_regs *));
125 125
126 /* 126 /*
127 * Mask out all interrupt by writing "1" to all bit position in 127 * Mask out all interrupt by writing "1" to all bit position in
128 * the interrupt reset reg. 128 * the interrupt reset reg.
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 31caf0603a3f..311155d1d3ed 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -200,7 +200,7 @@ void __init kgdb_config (void)
200 generic_putDebugChar = saa9730_putDebugChar; 200 generic_putDebugChar = saa9730_putDebugChar;
201 generic_getDebugChar = saa9730_getDebugChar; 201 generic_getDebugChar = saa9730_getDebugChar;
202 } 202 }
203 else 203 else
204#endif 204#endif
205 { 205 {
206 speed = rs_kgdb_hook(line, speed); 206 speed = rs_kgdb_hook(line, speed);
@@ -243,7 +243,7 @@ void __init prom_init(void)
243 mips_revision_corid = MIPS_REVISION_CORID; 243 mips_revision_corid = MIPS_REVISION_CORID;
244 244
245 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { 245 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
246 if (BONITO_PCIDID == 0x0001df53 || 246 if (BONITO_PCIDID == 0x0001df53 ||
247 BONITO_PCIDID == 0x0003df53) 247 BONITO_PCIDID == 0x0003df53)
248 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; 248 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
249 else 249 else
@@ -310,7 +310,7 @@ void __init prom_init(void)
310 case MIPS_REVISION_CORID_CORE_MSC: 310 case MIPS_REVISION_CORID_CORE_MSC:
311 case MIPS_REVISION_CORID_CORE_FPGA2: 311 case MIPS_REVISION_CORID_CORE_FPGA2:
312 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 312 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
313 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); 313 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
314 314
315#ifdef CONFIG_CPU_LITTLE_ENDIAN 315#ifdef CONFIG_CPU_LITTLE_ENDIAN
316 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); 316 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index fe7fc17305a6..16315444dd5a 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -89,7 +89,7 @@ static unsigned int __init estimate_cpu_frequency(void)
89 * really calculate the timer frequency 89 * really calculate the timer frequency
90 * For now we hardwire the SEAD board frequency to 12MHz. 90 * For now we hardwire the SEAD board frequency to 12MHz.
91 */ 91 */
92 92
93 if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) || 93 if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
94 (prid == (PRID_COMP_MIPS | PRID_IMP_25KF))) 94 (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
95 count = 12000000; 95 count = 12000000;
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index 3377e66de9eb..df6db6419ae9 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -149,15 +149,15 @@ static int __init malta_setup(void)
149 argptr = prom_getcmdline(); 149 argptr = prom_getcmdline();
150 if (strstr(argptr, "iobcuncached")) { 150 if (strstr(argptr, "iobcuncached")) {
151 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; 151 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
152 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & 152 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
153 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 153 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
154 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 154 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
155 printk("Disabled Bonito IOBC coherency\n"); 155 printk("Disabled Bonito IOBC coherency\n");
156 } 156 }
157 else { 157 else {
158 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; 158 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
159 BONITO_PCIMEMBASECFG |= 159 BONITO_PCIMEMBASECFG |=
160 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 160 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
161 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 161 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
162 printk("Disabled Bonito IOBC coherency\n"); 162 printk("Disabled Bonito IOBC coherency\n");
163 } 163 }
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index f61e038b4440..b56a0abdc3d4 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -5,8 +5,8 @@
5obj-y += cache.o extable.o fault.o init.o pgtable.o \ 5obj-y += cache.o extable.o fault.o init.o pgtable.o \
6 tlbex.o tlbex-fault.o 6 tlbex.o tlbex-fault.o
7 7
8obj-$(CONFIG_MIPS32) += ioremap.o pgtable-32.o 8obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o
9obj-$(CONFIG_MIPS64) += pgtable-64.o 9obj-$(CONFIG_64BIT) += pgtable-64.o
10obj-$(CONFIG_HIGHMEM) += highmem.o 10obj-$(CONFIG_HIGHMEM) += highmem.o
11 11
12obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 12obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a03ebb2cba67..5ea84bc98c6a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -126,13 +126,13 @@ static inline void tx49_blast_icache32(void)
126 126
127 CACHE32_UNROLL32_ALIGN2; 127 CACHE32_UNROLL32_ALIGN2;
128 /* I'm in even chunk. blast odd chunks */ 128 /* I'm in even chunk. blast odd chunks */
129 for (ws = 0; ws < ws_end; ws += ws_inc) 129 for (ws = 0; ws < ws_end; ws += ws_inc)
130 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 130 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
131 cache32_unroll32(addr|ws,Index_Invalidate_I); 131 cache32_unroll32(addr|ws,Index_Invalidate_I);
132 CACHE32_UNROLL32_ALIGN; 132 CACHE32_UNROLL32_ALIGN;
133 /* I'm in odd chunk. blast even chunks */ 133 /* I'm in odd chunk. blast even chunks */
134 for (ws = 0; ws < ws_end; ws += ws_inc) 134 for (ws = 0; ws < ws_end; ws += ws_inc)
135 for (addr = start; addr < end; addr += 0x400 * 2) 135 for (addr = start; addr < end; addr += 0x400 * 2)
136 cache32_unroll32(addr|ws,Index_Invalidate_I); 136 cache32_unroll32(addr|ws,Index_Invalidate_I);
137} 137}
138 138
@@ -156,13 +156,13 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page)
156 156
157 CACHE32_UNROLL32_ALIGN2; 157 CACHE32_UNROLL32_ALIGN2;
158 /* I'm in even chunk. blast odd chunks */ 158 /* I'm in even chunk. blast odd chunks */
159 for (ws = 0; ws < ws_end; ws += ws_inc) 159 for (ws = 0; ws < ws_end; ws += ws_inc)
160 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 160 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
161 cache32_unroll32(addr|ws,Index_Invalidate_I); 161 cache32_unroll32(addr|ws,Index_Invalidate_I);
162 CACHE32_UNROLL32_ALIGN; 162 CACHE32_UNROLL32_ALIGN;
163 /* I'm in odd chunk. blast even chunks */ 163 /* I'm in odd chunk. blast even chunks */
164 for (ws = 0; ws < ws_end; ws += ws_inc) 164 for (ws = 0; ws < ws_end; ws += ws_inc)
165 for (addr = start; addr < end; addr += 0x400 * 2) 165 for (addr = start; addr < end; addr += 0x400 * 2)
166 cache32_unroll32(addr|ws,Index_Invalidate_I); 166 cache32_unroll32(addr|ws,Index_Invalidate_I);
167} 167}
168 168
@@ -723,10 +723,10 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
723 ".set push\n\t" 723 ".set push\n\t"
724 ".set noat\n\t" 724 ".set noat\n\t"
725 ".set mips3\n\t" 725 ".set mips3\n\t"
726#ifdef CONFIG_MIPS32 726#ifdef CONFIG_32BIT
727 "la $at,1f\n\t" 727 "la $at,1f\n\t"
728#endif 728#endif
729#ifdef CONFIG_MIPS64 729#ifdef CONFIG_64BIT
730 "dla $at,1f\n\t" 730 "dla $at,1f\n\t"
731#endif 731#endif
732 "cache %0,($at)\n\t" 732 "cache %0,($at)\n\t"
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index ab30afd63b32..502f68c664b2 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -270,7 +270,7 @@ static void local_sb1_flush_icache_range(unsigned long start,
270 __sb1_writeback_inv_dcache_all(); 270 __sb1_writeback_inv_dcache_all();
271 else 271 else
272 __sb1_writeback_inv_dcache_range(start, end); 272 __sb1_writeback_inv_dcache_range(start, end);
273 273
274 /* Just flush the whole icache if the range is big enough */ 274 /* Just flush the whole icache if the range is big enough */
275 if ((end - start) > icache_range_cutoff) 275 if ((end - start) > icache_range_cutoff)
276 __sb1_flush_icache_all(); 276 __sb1_flush_icache_all();
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 13d96d62764e..7166ffe63502 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -25,7 +25,7 @@
25#include <asm/sibyte/sb1250_regs.h> 25#include <asm/sibyte/sb1250_regs.h>
26#include <asm/sibyte/sb1250_scd.h> 26#include <asm/sibyte/sb1250_scd.h>
27#endif 27#endif
28 28
29/* SB1 definitions */ 29/* SB1 definitions */
30 30
31/* XXX should come from config1 XXX */ 31/* XXX should come from config1 XXX */
@@ -136,14 +136,14 @@ static inline void breakout_cerrd(unsigned int val)
136 136
137#ifndef CONFIG_SIBYTE_BUS_WATCHER 137#ifndef CONFIG_SIBYTE_BUS_WATCHER
138 138
139static void check_bus_watcher(void) 139static void check_bus_watcher(void)
140{ 140{
141 uint32_t status, l2_err, memio_err; 141 uint32_t status, l2_err, memio_err;
142 142
143 /* Destructive read, clears register and interrupt */ 143 /* Destructive read, clears register and interrupt */
144 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); 144 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
145 /* Bit 31 is always on, but there's no #define for that */ 145 /* Bit 31 is always on, but there's no #define for that */
146 if (status & ~(1UL << 31)) { 146 if (status & ~(1UL << 31)) {
147 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); 147 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
148 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); 148 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
149 prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); 149 prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
@@ -153,14 +153,14 @@ static void check_bus_watcher(void)
153 (int)(G_SCD_BERR_TID(status) >> 6), 153 (int)(G_SCD_BERR_TID(status) >> 6),
154 (int)G_SCD_BERR_RID(status), 154 (int)G_SCD_BERR_RID(status),
155 (int)G_SCD_BERR_DCODE(status)); 155 (int)G_SCD_BERR_DCODE(status));
156 } else { 156 } else {
157 prom_printf("Bus watcher indicates no error\n"); 157 prom_printf("Bus watcher indicates no error\n");
158 } 158 }
159} 159}
160#else 160#else
161extern void check_bus_watcher(void); 161extern void check_bus_watcher(void);
162#endif 162#endif
163 163
164asmlinkage void sb1_cache_error(void) 164asmlinkage void sb1_cache_error(void)
165{ 165{
166 uint64_t cerr_dpa; 166 uint64_t cerr_dpa;
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 9895e32b0fce..59e54f12212e 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -162,7 +162,7 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
162 162
163 for (i = 0; i < nents; i++, sg++) { 163 for (i = 0; i < nents; i++, sg++) {
164 unsigned long addr; 164 unsigned long addr;
165 165
166 addr = (unsigned long) page_address(sg->page); 166 addr = (unsigned long) page_address(sg->page);
167 if (addr) 167 if (addr)
168 __dma_sync(addr + sg->offset, sg->length, direction); 168 __dma_sync(addr + sg->offset, sg->length, direction);
@@ -230,9 +230,9 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
230 size_t size, enum dma_data_direction direction) 230 size_t size, enum dma_data_direction direction)
231{ 231{
232 unsigned long addr; 232 unsigned long addr;
233 233
234 BUG_ON(direction == DMA_NONE); 234 BUG_ON(direction == DMA_NONE);
235 235
236 addr = dma_handle + PAGE_OFFSET; 236 addr = dma_handle + PAGE_OFFSET;
237 __dma_sync(addr, size, direction); 237 __dma_sync(addr, size, direction);
238} 238}
@@ -282,9 +282,9 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
282 enum dma_data_direction direction) 282 enum dma_data_direction direction)
283{ 283{
284 int i; 284 int i;
285 285
286 BUG_ON(direction == DMA_NONE); 286 BUG_ON(direction == DMA_NONE);
287 287
288 /* Make sure that gcc doesn't leave the empty loop body. */ 288 /* Make sure that gcc doesn't leave the empty loop body. */
289 for (i = 0; i < nelems; i++, sg++) 289 for (i = 0; i < nelems; i++, sg++)
290 __dma_sync((unsigned long)page_address(sg->page), 290 __dma_sync((unsigned long)page_address(sg->page),
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 9c9a271c8a3a..dc6830b10fab 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -96,7 +96,7 @@ static void __init kmap_init(void)
96 kmap_prot = PAGE_KERNEL; 96 kmap_prot = PAGE_KERNEL;
97} 97}
98 98
99#ifdef CONFIG_MIPS64 99#ifdef CONFIG_64BIT
100static void __init fixrange_init(unsigned long start, unsigned long end, 100static void __init fixrange_init(unsigned long start, unsigned long end,
101 pgd_t *pgd_base) 101 pgd_t *pgd_base)
102{ 102{
@@ -125,7 +125,7 @@ static void __init fixrange_init(unsigned long start, unsigned long end,
125 j = 0; 125 j = 0;
126 } 126 }
127} 127}
128#endif /* CONFIG_MIPS64 */ 128#endif /* CONFIG_64BIT */
129#endif /* CONFIG_HIGHMEM */ 129#endif /* CONFIG_HIGHMEM */
130 130
131#ifndef CONFIG_NEED_MULTIPLE_NODES 131#ifndef CONFIG_NEED_MULTIPLE_NODES
@@ -258,7 +258,7 @@ void __init mem_init(void)
258#ifdef CONFIG_BLK_DEV_INITRD 258#ifdef CONFIG_BLK_DEV_INITRD
259void free_initrd_mem(unsigned long start, unsigned long end) 259void free_initrd_mem(unsigned long start, unsigned long end)
260{ 260{
261#ifdef CONFIG_MIPS64 261#ifdef CONFIG_64BIT
262 /* Switch from KSEG0 to XKPHYS addresses */ 262 /* Switch from KSEG0 to XKPHYS addresses */
263 start = (unsigned long)phys_to_virt(CPHYSADDR(start)); 263 start = (unsigned long)phys_to_virt(CPHYSADDR(start));
264 end = (unsigned long)phys_to_virt(CPHYSADDR(end)); 264 end = (unsigned long)phys_to_virt(CPHYSADDR(end));
@@ -286,7 +286,7 @@ void free_initmem(void)
286 286
287 addr = (unsigned long) &__init_begin; 287 addr = (unsigned long) &__init_begin;
288 while (addr < (unsigned long) &__init_end) { 288 while (addr < (unsigned long) &__init_end) {
289#ifdef CONFIG_MIPS64 289#ifdef CONFIG_64BIT
290 page = PAGE_OFFSET | CPHYSADDR(addr); 290 page = PAGE_OFFSET | CPHYSADDR(addr);
291#else 291#else
292 page = addr; 292 page = addr;
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index 59d131b5e536..1b6df7133c1e 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -114,7 +114,7 @@ static inline void copy_page_cpu(void *to, void *from)
114 " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%1)\n" 114 " pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%1)\n"
115 " pref " SB1_PREF_LOAD_STREAMED_HINT ", -32(%0)\n" 115 " pref " SB1_PREF_LOAD_STREAMED_HINT ", -32(%0)\n"
116 "1: pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%1)\n" 116 "1: pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%1)\n"
117# ifdef CONFIG_MIPS64 117# ifdef CONFIG_64BIT
118 " ld $8, -128(%0) \n" /* Block copy a cacheline */ 118 " ld $8, -128(%0) \n" /* Block copy a cacheline */
119 " ld $9, -120(%0) \n" 119 " ld $9, -120(%0) \n"
120 " ld $10, -112(%0) \n" 120 " ld $10, -112(%0) \n"
@@ -148,7 +148,7 @@ static inline void copy_page_cpu(void *to, void *from)
148 " daddiu %0, %0, -128 \n" 148 " daddiu %0, %0, -128 \n"
149 " daddiu %1, %1, -128 \n" 149 " daddiu %1, %1, -128 \n"
150#endif 150#endif
151#ifdef CONFIG_MIPS64 151#ifdef CONFIG_64BIT
152 " ld $8, 0(%0) \n" /* Block copy a cacheline */ 152 " ld $8, 0(%0) \n" /* Block copy a cacheline */
153 "1: ld $9, 8(%0) \n" 153 "1: ld $9, 8(%0) \n"
154 " ld $10, 16(%0) \n" 154 " ld $10, 16(%0) \n"
@@ -178,7 +178,7 @@ static inline void copy_page_cpu(void *to, void *from)
178 " daddiu %0, %0, 32 \n" 178 " daddiu %0, %0, 32 \n"
179 " daddiu %1, %1, 32 \n" 179 " daddiu %1, %1, 32 \n"
180 " bnel %0, %2, 1b \n" 180 " bnel %0, %2, 1b \n"
181#ifdef CONFIG_MIPS64 181#ifdef CONFIG_64BIT
182 " ld $8, 0(%0) \n" 182 " ld $8, 0(%0) \n"
183#else 183#else
184 " lw $2, 0(%0) \n" 184 " lw $2, 0(%0) \n"
@@ -186,7 +186,7 @@ static inline void copy_page_cpu(void *to, void *from)
186 " .set pop \n" 186 " .set pop \n"
187 : "+r" (src), "+r" (dst) 187 : "+r" (src), "+r" (dst)
188 : "r" (end) 188 : "r" (end)
189#ifdef CONFIG_MIPS64 189#ifdef CONFIG_64BIT
190 : "$8","$9","$10","$11","memory"); 190 : "$8","$9","$10","$11","memory");
191#else 191#else
192 : "$2","$3","$6","$7","$8","$9","$10","$11","memory"); 192 : "$2","$3","$6","$7","$8","$9","$10","$11","memory");
@@ -198,7 +198,7 @@ static inline void copy_page_cpu(void *to, void *from)
198 198
199/* 199/*
200 * Pad descriptors to cacheline, since each is exclusively owned by a 200 * Pad descriptors to cacheline, since each is exclusively owned by a
201 * particular CPU. 201 * particular CPU.
202 */ 202 */
203typedef struct dmadscr_s { 203typedef struct dmadscr_s {
204 u64 dscr_a; 204 u64 dscr_a;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 87e229f4d3d5..6569be3983c7 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -448,7 +448,7 @@ L_LA(_r3000_write_probe_fail)
448L_LA(_r3000_write_probe_ok) 448L_LA(_r3000_write_probe_ok)
449 449
450/* convenience macros for instructions */ 450/* convenience macros for instructions */
451#ifdef CONFIG_MIPS64 451#ifdef CONFIG_64BIT
452# define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off) 452# define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off)
453# define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off) 453# define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off)
454# define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh) 454# define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh)
@@ -486,7 +486,7 @@ L_LA(_r3000_write_probe_ok)
486#define i_ssnop(buf) i_sll(buf, 0, 0, 1) 486#define i_ssnop(buf) i_sll(buf, 0, 0, 1)
487#define i_ehb(buf) i_sll(buf, 0, 0, 3) 487#define i_ehb(buf) i_sll(buf, 0, 0, 3)
488 488
489#ifdef CONFIG_MIPS64 489#ifdef CONFIG_64BIT
490static __init int __attribute__((unused)) in_compat_space_p(long addr) 490static __init int __attribute__((unused)) in_compat_space_p(long addr)
491{ 491{
492 /* Is this address in 32bit compat space? */ 492 /* Is this address in 32bit compat space? */
@@ -516,7 +516,7 @@ static __init int rel_lo(long val)
516 516
517static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) 517static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
518{ 518{
519#if CONFIG_MIPS64 519#ifdef CONFIG_64BIT
520 if (!in_compat_space_p(addr)) { 520 if (!in_compat_space_p(addr)) {
521 i_lui(buf, rs, rel_highest(addr)); 521 i_lui(buf, rs, rel_highest(addr));
522 if (rel_higher(addr)) 522 if (rel_higher(addr))
@@ -682,7 +682,7 @@ static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
682#define C0_EPC 14 682#define C0_EPC 14
683#define C0_XCONTEXT 20 683#define C0_XCONTEXT 20
684 684
685#ifdef CONFIG_MIPS64 685#ifdef CONFIG_64BIT
686# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT) 686# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT)
687#else 687#else
688# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT) 688# define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT)
@@ -923,7 +923,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
923 } 923 }
924} 924}
925 925
926#ifdef CONFIG_MIPS64 926#ifdef CONFIG_64BIT
927/* 927/*
928 * TMP and PTR are scratch. 928 * TMP and PTR are scratch.
929 * TMP will be clobbered, PTR will hold the pmd entry. 929 * TMP will be clobbered, PTR will hold the pmd entry.
@@ -1010,7 +1010,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1010 } 1010 }
1011} 1011}
1012 1012
1013#else /* !CONFIG_MIPS64 */ 1013#else /* !CONFIG_64BIT */
1014 1014
1015/* 1015/*
1016 * TMP and PTR are scratch. 1016 * TMP and PTR are scratch.
@@ -1038,7 +1038,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1038 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 1038 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
1039} 1039}
1040 1040
1041#endif /* !CONFIG_MIPS64 */ 1041#endif /* !CONFIG_64BIT */
1042 1042
1043static __init void build_adjust_context(u32 **p, unsigned int ctx) 1043static __init void build_adjust_context(u32 **p, unsigned int ctx)
1044{ 1044{
@@ -1159,7 +1159,7 @@ static void __init build_r4000_tlb_refill_handler(void)
1159 /* No need for i_nop */ 1159 /* No need for i_nop */
1160 } 1160 }
1161 1161
1162#ifdef CONFIG_MIPS64 1162#ifdef CONFIG_64BIT
1163 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1163 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1164#else 1164#else
1165 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1165 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
@@ -1171,7 +1171,7 @@ static void __init build_r4000_tlb_refill_handler(void)
1171 l_leave(&l, p); 1171 l_leave(&l, p);
1172 i_eret(&p); /* return from trap */ 1172 i_eret(&p); /* return from trap */
1173 1173
1174#ifdef CONFIG_MIPS64 1174#ifdef CONFIG_64BIT
1175 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); 1175 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
1176#endif 1176#endif
1177 1177
@@ -1182,7 +1182,7 @@ static void __init build_r4000_tlb_refill_handler(void)
1182 * need three, with the the second nop'ed and the third being 1182 * need three, with the the second nop'ed and the third being
1183 * unused. 1183 * unused.
1184 */ 1184 */
1185#ifdef CONFIG_MIPS32 1185#ifdef CONFIG_32BIT
1186 if ((p - tlb_handler) > 64) 1186 if ((p - tlb_handler) > 64)
1187 panic("TLB refill handler space exceeded"); 1187 panic("TLB refill handler space exceeded");
1188#else 1188#else
@@ -1195,12 +1195,12 @@ static void __init build_r4000_tlb_refill_handler(void)
1195 /* 1195 /*
1196 * Now fold the handler in the TLB refill handler space. 1196 * Now fold the handler in the TLB refill handler space.
1197 */ 1197 */
1198#ifdef CONFIG_MIPS32 1198#ifdef CONFIG_32BIT
1199 f = final_handler; 1199 f = final_handler;
1200 /* Simplest case, just copy the handler. */ 1200 /* Simplest case, just copy the handler. */
1201 copy_handler(relocs, labels, tlb_handler, p, f); 1201 copy_handler(relocs, labels, tlb_handler, p, f);
1202 final_len = p - tlb_handler; 1202 final_len = p - tlb_handler;
1203#else /* CONFIG_MIPS64 */ 1203#else /* CONFIG_64BIT */
1204 f = final_handler + 32; 1204 f = final_handler + 32;
1205 if ((p - tlb_handler) <= 32) { 1205 if ((p - tlb_handler) <= 32) {
1206 /* Just copy the handler. */ 1206 /* Just copy the handler. */
@@ -1235,7 +1235,7 @@ static void __init build_r4000_tlb_refill_handler(void)
1235 copy_handler(relocs, labels, split, p, final_handler); 1235 copy_handler(relocs, labels, split, p, final_handler);
1236 final_len = (f - (final_handler + 32)) + (p - split); 1236 final_len = (f - (final_handler + 32)) + (p - split);
1237 } 1237 }
1238#endif /* CONFIG_MIPS64 */ 1238#endif /* CONFIG_64BIT */
1239 1239
1240 resolve_relocs(relocs, labels); 1240 resolve_relocs(relocs, labels);
1241 printk("Synthesized TLB refill handler (%u instructions).\n", 1241 printk("Synthesized TLB refill handler (%u instructions).\n",
@@ -1605,7 +1605,7 @@ build_r4000_tlbchange_handler_head(u32 **p, struct label **l,
1605 struct reloc **r, unsigned int pte, 1605 struct reloc **r, unsigned int pte,
1606 unsigned int ptr) 1606 unsigned int ptr)
1607{ 1607{
1608#ifdef CONFIG_MIPS64 1608#ifdef CONFIG_64BIT
1609 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ 1609 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1610#else 1610#else
1611 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ 1611 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
@@ -1636,7 +1636,7 @@ build_r4000_tlbchange_handler_tail(u32 **p, struct label **l,
1636 l_leave(l, *p); 1636 l_leave(l, *p);
1637 i_eret(p); /* return from trap */ 1637 i_eret(p); /* return from trap */
1638 1638
1639#ifdef CONFIG_MIPS64 1639#ifdef CONFIG_64BIT
1640 build_get_pgd_vmalloc64(p, l, r, tmp, ptr); 1640 build_get_pgd_vmalloc64(p, l, r, tmp, ptr);
1641#endif 1641#endif
1642} 1642}
diff --git a/arch/mips/momentum/jaguar_atx/int-handler.S b/arch/mips/momentum/jaguar_atx/int-handler.S
index 43fd5a58077c..55bc789733f2 100644
--- a/arch/mips/momentum/jaguar_atx/int-handler.S
+++ b/arch/mips/momentum/jaguar_atx/int-handler.S
@@ -27,11 +27,11 @@
27 SAVE_ALL 27 SAVE_ALL
28 CLI 28 CLI
29 .set at 29 .set at
30 mfc0 t0, CP0_CAUSE 30 mfc0 t0, CP0_CAUSE
31 mfc0 t2, CP0_STATUS 31 mfc0 t2, CP0_STATUS
32 32
33 and t0, t2 33 and t0, t2
34 34
35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ 35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
36 bnez t1, ll_sw0_irq 36 bnez t1, ll_sw0_irq
37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ 37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
@@ -103,25 +103,25 @@ ll_pcia_irq:
103 move a1, sp 103 move a1, sp
104 jal do_IRQ 104 jal do_IRQ
105 j ret_from_irq 105 j ret_from_irq
106 106
107ll_pcib_irq: 107ll_pcib_irq:
108 li a0, 5 108 li a0, 5
109 move a1, sp 109 move a1, sp
110 jal do_IRQ 110 jal do_IRQ
111 j ret_from_irq 111 j ret_from_irq
112 112
113ll_uart_irq: 113ll_uart_irq:
114 li a0, 6 114 li a0, 6
115 move a1, sp 115 move a1, sp
116 jal do_IRQ 116 jal do_IRQ
117 j ret_from_irq 117 j ret_from_irq
118 118
119ll_cputimer_irq: 119ll_cputimer_irq:
120 li a0, 7 120 li a0, 7
121 move a1, sp 121 move a1, sp
122 jal ll_timer_interrupt 122 jal ll_timer_interrupt
123 j ret_from_irq 123 j ret_from_irq
124 124
125ll_mv64340_decode_irq: 125ll_mv64340_decode_irq:
126 move a0, sp 126 move a0, sp
127 jal ll_mv64340_irq 127 jal ll_mv64340_irq
diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c
index fa5982ac0ac6..14ae2e713585 100644
--- a/arch/mips/momentum/jaguar_atx/prom.c
+++ b/arch/mips/momentum/jaguar_atx/prom.c
@@ -64,7 +64,7 @@ static u8 exchange_bit(u8 val, u8 cs)
64 64
65 /* turn the clock off and read-strobe */ 65 /* turn the clock off and read-strobe */
66 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); 66 JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
67 67
68 /* return the data */ 68 /* return the data */
69 return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); 69 return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
70} 70}
@@ -90,7 +90,7 @@ void get_mac(char dest[6])
90} 90}
91#endif 91#endif
92 92
93#ifdef CONFIG_MIPS64 93#ifdef CONFIG_64BIT
94 94
95unsigned long signext(unsigned long addr) 95unsigned long signext(unsigned long addr)
96{ 96{
@@ -143,7 +143,7 @@ char *arg64(unsigned long addrin, int arg_index)
143 143
144 return p; 144 return p;
145} 145}
146#endif /* CONFIG_MIPS64 */ 146#endif /* CONFIG_64BIT */
147 147
148/* PMON passes arguments in C main() style */ 148/* PMON passes arguments in C main() style */
149void __init prom_init(void) 149void __init prom_init(void)
@@ -158,7 +158,7 @@ void __init prom_init(void)
158// ja_setup_console(); /* The very first thing. */ 158// ja_setup_console(); /* The very first thing. */
159#endif 159#endif
160 160
161#ifdef CONFIG_MIPS64 161#ifdef CONFIG_64BIT
162 char *ptr; 162 char *ptr;
163 163
164 printk("Mips64 Jaguar-ATX\n"); 164 printk("Mips64 Jaguar-ATX\n");
@@ -201,7 +201,7 @@ void __init prom_init(void)
201 } 201 }
202 printk("arcs_cmdline: %s\n", arcs_cmdline); 202 printk("arcs_cmdline: %s\n", arcs_cmdline);
203 203
204#else /* CONFIG_MIPS64 */ 204#else /* CONFIG_64BIT */
205 /* save the PROM vectors for debugging use */ 205 /* save the PROM vectors for debugging use */
206 debug_vectors = cv; 206 debug_vectors = cv;
207 207
@@ -226,7 +226,7 @@ void __init prom_init(void)
226 } 226 }
227 env++; 227 env++;
228 } 228 }
229#endif /* CONFIG_MIPS64 */ 229#endif /* CONFIG_64BIT */
230 mips_machgroup = MACH_GROUP_MOMENCO; 230 mips_machgroup = MACH_GROUP_MOMENCO;
231 mips_machtype = MACH_MOMENCO_JAGUAR_ATX; 231 mips_machtype = MACH_MOMENCO_JAGUAR_ATX;
232 232
diff --git a/arch/mips/momentum/jaguar_atx/reset.c b/arch/mips/momentum/jaguar_atx/reset.c
index 48039484cdf9..c4236b1e59fa 100644
--- a/arch/mips/momentum/jaguar_atx/reset.c
+++ b/arch/mips/momentum/jaguar_atx/reset.c
@@ -27,7 +27,7 @@
27void momenco_jaguar_restart(char *command) 27void momenco_jaguar_restart(char *command)
28{ 28{
29 /* base address of timekeeper portion of part */ 29 /* base address of timekeeper portion of part */
30#ifdef CONFIG_MIPS64 30#ifdef CONFIG_64BIT
31 void *nvram = (void*) 0xfffffffffc807000; 31 void *nvram = (void*) 0xfffffffffc807000;
32#else 32#else
33 void *nvram = (void*) 0xfc807000; 33 void *nvram = (void*) 0xfc807000;
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
index 30462e715066..90288cf2b1e0 100644
--- a/arch/mips/momentum/jaguar_atx/setup.c
+++ b/arch/mips/momentum/jaguar_atx/setup.c
@@ -105,7 +105,7 @@ void __init bus_error_init(void) { /* nothing */ }
105 105
106static __init void wire_stupidity_into_tlb(void) 106static __init void wire_stupidity_into_tlb(void)
107{ 107{
108#ifdef CONFIG_MIPS32 108#ifdef CONFIG_32BIT
109 write_c0_wired(0); 109 write_c0_wired(0);
110 local_flush_tlb_all(); 110 local_flush_tlb_all();
111 111
@@ -451,7 +451,7 @@ static int __init momenco_jaguar_atx_setup(void)
451#ifdef GEMDEBUG_TRACEBUFFER 451#ifdef GEMDEBUG_TRACEBUFFER
452 { 452 {
453 unsigned int tbControl; 453 unsigned int tbControl;
454 tbControl = 454 tbControl =
455 0 << 26 | /* post trigger delay 0 */ 455 0 << 26 | /* post trigger delay 0 */
456 0x2 << 16 | /* sequential trace mode */ 456 0x2 << 16 | /* sequential trace mode */
457 // 0x0 << 16 | /* non-sequential trace mode */ 457 // 0x0 << 16 | /* non-sequential trace mode */
diff --git a/arch/mips/momentum/ocelot_3/prom.c b/arch/mips/momentum/ocelot_3/prom.c
index 89c17a0c0bed..c4fa9c525faa 100644
--- a/arch/mips/momentum/ocelot_3/prom.c
+++ b/arch/mips/momentum/ocelot_3/prom.c
@@ -93,7 +93,7 @@ void get_mac(char dest[6])
93#endif 93#endif
94 94
95 95
96#ifdef CONFIG_MIPS64 96#ifdef CONFIG_64BIT
97 97
98unsigned long signext(unsigned long addr) 98unsigned long signext(unsigned long addr)
99{ 99{
@@ -145,7 +145,7 @@ char *arg64(unsigned long addrin, int arg_index)
145 145
146 return p; 146 return p;
147} 147}
148#endif /* CONFIG_MIPS64 */ 148#endif /* CONFIG_64BIT */
149 149
150void __init prom_init(void) 150void __init prom_init(void)
151{ 151{
@@ -155,7 +155,7 @@ void __init prom_init(void)
155 struct callvectors *cv = (struct callvectors *) fw_arg3; 155 struct callvectors *cv = (struct callvectors *) fw_arg3;
156 int i; 156 int i;
157 157
158#ifdef CONFIG_MIPS64 158#ifdef CONFIG_64BIT
159 char *ptr; 159 char *ptr;
160 printk("prom_init - MIPS64\n"); 160 printk("prom_init - MIPS64\n");
161 161
@@ -198,7 +198,7 @@ void __init prom_init(void)
198 } 198 }
199 printk("arcs_cmdline: %s\n", arcs_cmdline); 199 printk("arcs_cmdline: %s\n", arcs_cmdline);
200 200
201#else /* CONFIG_MIPS64 */ 201#else /* CONFIG_64BIT */
202 202
203 /* save the PROM vectors for debugging use */ 203 /* save the PROM vectors for debugging use */
204 debug_vectors = cv; 204 debug_vectors = cv;
@@ -224,7 +224,7 @@ void __init prom_init(void)
224 } 224 }
225 env++; 225 env++;
226 } 226 }
227#endif /* CONFIG_MIPS64 */ 227#endif /* CONFIG_64BIT */
228 228
229 mips_machgroup = MACH_GROUP_MOMENCO; 229 mips_machgroup = MACH_GROUP_MOMENCO;
230 mips_machtype = MACH_MOMENCO_OCELOT_3; 230 mips_machtype = MACH_MOMENCO_OCELOT_3;
@@ -234,7 +234,7 @@ void __init prom_init(void)
234 get_mac(prom_mac_addr_base); 234 get_mac(prom_mac_addr_base);
235#endif 235#endif
236 236
237#ifndef CONFIG_MIPS64 237#ifndef CONFIG_64BIT
238 debug_vectors->printf("Booting Linux kernel...\n"); 238 debug_vectors->printf("Booting Linux kernel...\n");
239#endif 239#endif
240} 240}
diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S
index 2f2430648abc..52349d9bf1be 100644
--- a/arch/mips/momentum/ocelot_c/int-handler.S
+++ b/arch/mips/momentum/ocelot_c/int-handler.S
@@ -27,11 +27,11 @@
27 SAVE_ALL 27 SAVE_ALL
28 CLI 28 CLI
29 .set at 29 .set at
30 mfc0 t0, CP0_CAUSE 30 mfc0 t0, CP0_CAUSE
31 mfc0 t2, CP0_STATUS 31 mfc0 t2, CP0_STATUS
32 32
33 and t0, t2 33 and t0, t2
34 34
35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */ 35 andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
36 bnez t1, ll_sw0_irq 36 bnez t1, ll_sw0_irq
37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */ 37 andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
@@ -83,7 +83,7 @@ ll_pmc_irq:
83 move a1, sp 83 move a1, sp
84 jal do_IRQ 84 jal do_IRQ
85 j ret_from_irq 85 j ret_from_irq
86 86
87ll_cpci_decode_irq: 87ll_cpci_decode_irq:
88 move a0, sp 88 move a0, sp
89 jal ll_cpci_irq 89 jal ll_cpci_irq
@@ -99,4 +99,4 @@ ll_cputimer_irq:
99 move a1, sp 99 move a1, sp
100 jal do_IRQ 100 jal do_IRQ
101 j ret_from_irq 101 j ret_from_irq
102 102
diff --git a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
index a6cf7a7959b3..97fb77dad723 100644
--- a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
+++ b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
@@ -32,7 +32,7 @@
32 32
33#include <linux/config.h> 33#include <linux/config.h>
34 34
35#ifdef CONFIG_MIPS64 35#ifdef CONFIG_64BIT
36#define OCELOT_C_CS0_ADDR (0xfffffffffc000000) 36#define OCELOT_C_CS0_ADDR (0xfffffffffc000000)
37#else 37#else
38#define OCELOT_C_CS0_ADDR (0xfc000000) 38#define OCELOT_C_CS0_ADDR (0xfc000000)
diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c
index 49ac302d8901..5b6809724b15 100644
--- a/arch/mips/momentum/ocelot_c/prom.c
+++ b/arch/mips/momentum/ocelot_c/prom.c
@@ -67,7 +67,7 @@ static u8 exchange_bit(u8 val, u8 cs)
67 67
68 /* turn the clock off and read-strobe */ 68 /* turn the clock off and read-strobe */
69 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE); 69 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
70 70
71 /* return the data */ 71 /* return the data */
72 return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1); 72 return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
73} 73}
@@ -94,7 +94,7 @@ void get_mac(char dest[6])
94#endif 94#endif
95 95
96 96
97#ifdef CONFIG_MIPS64 97#ifdef CONFIG_64BIT
98 98
99unsigned long signext(unsigned long addr) 99unsigned long signext(unsigned long addr)
100{ 100{
@@ -144,7 +144,7 @@ char *arg64(unsigned long addrin, int arg_index)
144 p = (char *)get_arg(args, arg_index); 144 p = (char *)get_arg(args, arg_index);
145 return p; 145 return p;
146} 146}
147#endif /* CONFIG_MIPS64 */ 147#endif /* CONFIG_64BIT */
148 148
149 149
150void __init prom_init(void) 150void __init prom_init(void)
@@ -155,7 +155,7 @@ void __init prom_init(void)
155 struct callvectors *cv = (struct callvectors *) fw_arg3; 155 struct callvectors *cv = (struct callvectors *) fw_arg3;
156 int i; 156 int i;
157 157
158#ifdef CONFIG_MIPS64 158#ifdef CONFIG_64BIT
159 char *ptr; 159 char *ptr;
160 160
161 printk("prom_init - MIPS64\n"); 161 printk("prom_init - MIPS64\n");
@@ -197,7 +197,7 @@ void __init prom_init(void)
197 } 197 }
198 printk("arcs_cmdline: %s\n", arcs_cmdline); 198 printk("arcs_cmdline: %s\n", arcs_cmdline);
199 199
200#else /* CONFIG_MIPS64 */ 200#else /* CONFIG_64BIT */
201 /* save the PROM vectors for debugging use */ 201 /* save the PROM vectors for debugging use */
202 debug_vectors = cv; 202 debug_vectors = cv;
203 203
@@ -222,7 +222,7 @@ void __init prom_init(void)
222 } 222 }
223 env++; 223 env++;
224 } 224 }
225#endif /* CONFIG_MIPS64 */ 225#endif /* CONFIG_64BIT */
226 226
227 mips_machgroup = MACH_GROUP_MOMENCO; 227 mips_machgroup = MACH_GROUP_MOMENCO;
228 mips_machtype = MACH_MOMENCO_OCELOT_C; 228 mips_machtype = MACH_MOMENCO_OCELOT_C;
@@ -232,7 +232,7 @@ void __init prom_init(void)
232 get_mac(prom_mac_addr_base); 232 get_mac(prom_mac_addr_base);
233#endif 233#endif
234 234
235#ifndef CONFIG_MIPS64 235#ifndef CONFIG_64BIT
236 debug_vectors->printf("Booting Linux kernel...\n"); 236 debug_vectors->printf("Booting Linux kernel...\n");
237#endif 237#endif
238} 238}
diff --git a/arch/mips/momentum/ocelot_c/reset.c b/arch/mips/momentum/ocelot_c/reset.c
index 1f2b4263cc8c..6a2489f3b9a0 100644
--- a/arch/mips/momentum/ocelot_c/reset.c
+++ b/arch/mips/momentum/ocelot_c/reset.c
@@ -28,7 +28,7 @@ void momenco_ocelot_restart(char *command)
28{ 28{
29 /* base address of timekeeper portion of part */ 29 /* base address of timekeeper portion of part */
30 void *nvram = (void *) 30 void *nvram = (void *)
31#ifdef CONFIG_MIPS64 31#ifdef CONFIG_64BIT
32 0xfffffffffc807000; 32 0xfffffffffc807000;
33#else 33#else
34 0xfc807000; 34 0xfc807000;
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c
index 021c00e3c07c..844ddd06349b 100644
--- a/arch/mips/momentum/ocelot_c/setup.c
+++ b/arch/mips/momentum/ocelot_c/setup.c
@@ -109,7 +109,7 @@ void PMON_v2_setup(void)
109 */ 109 */
110 printk("PMON_v2_setup\n"); 110 printk("PMON_v2_setup\n");
111 111
112#ifdef CONFIG_MIPS64 112#ifdef CONFIG_64BIT
113 /* marvell and extra space */ 113 /* marvell and extra space */
114 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K); 114 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xfffffffff4000000, PM_64K);
115 /* fpga, rtc, and uart */ 115 /* fpga, rtc, and uart */
@@ -134,7 +134,7 @@ void PMON_v2_setup(void)
134 134
135unsigned long m48t37y_get_time(void) 135unsigned long m48t37y_get_time(void)
136{ 136{
137#ifdef CONFIG_MIPS64 137#ifdef CONFIG_64BIT
138 unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000; 138 unsigned char *rtc_base = (unsigned char*)0xfffffffffc800000;
139#else 139#else
140 unsigned char* rtc_base = (unsigned char*)0xfc800000; 140 unsigned char* rtc_base = (unsigned char*)0xfc800000;
@@ -163,7 +163,7 @@ unsigned long m48t37y_get_time(void)
163 163
164int m48t37y_set_time(unsigned long sec) 164int m48t37y_set_time(unsigned long sec)
165{ 165{
166#ifdef CONFIG_MIPS64 166#ifdef CONFIG_64BIT
167 unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000; 167 unsigned char* rtc_base = (unsigned char*)0xfffffffffc800000;
168#else 168#else
169 unsigned char* rtc_base = (unsigned char*)0xfc800000; 169 unsigned char* rtc_base = (unsigned char*)0xfc800000;
@@ -342,7 +342,7 @@ static void __init momenco_ocelot_c_setup(void)
342 342
343early_initcall(momenco_ocelot_c_setup); 343early_initcall(momenco_ocelot_c_setup);
344 344
345#ifndef CONFIG_MIPS64 345#ifndef CONFIG_64BIT
346/* This needs to be one of the first initcalls, because no I/O port access 346/* This needs to be one of the first initcalls, because no I/O port access
347 can work before this */ 347 can work before this */
348static int io_base_ioremap(void) 348static int io_base_ioremap(void)
diff --git a/arch/mips/pci/fixup-ddb5074.c b/arch/mips/pci/fixup-ddb5074.c
index b345e528a53c..5a4a7c239c42 100644
--- a/arch/mips/pci/fixup-ddb5074.c
+++ b/arch/mips/pci/fixup-ddb5074.c
@@ -5,7 +5,7 @@ static void ddb5074_fixup(struct pci_dev *dev)
5{ 5{
6 extern struct pci_dev *pci_pmu; 6 extern struct pci_dev *pci_pmu;
7 u8 t8; 7 u8 t8;
8 8
9 pci_pmu = dev; /* for LEDs D2 and D3 */ 9 pci_pmu = dev; /* for LEDs D2 and D3 */
10 /* Program the lines for LEDs D2 and D3 to output */ 10 /* Program the lines for LEDs D2 and D3 to output */
11 pci_read_config_byte(dev, 0x7d, &t8); 11 pci_read_config_byte(dev, 0x7d, &t8);
diff --git a/arch/mips/pci/fixup-ddb5477.c b/arch/mips/pci/fixup-ddb5477.c
index 6abdc88bab1e..2f1444e60654 100644
--- a/arch/mips/pci/fixup-ddb5477.c
+++ b/arch/mips/pci/fixup-ddb5477.c
@@ -65,7 +65,7 @@ static void ddb5477_amd_lance_fixup(struct pci_dev *dev)
65 ioaddr = pci_resource_start(dev, 0); 65 ioaddr = pci_resource_start(dev, 0);
66 66
67 inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */ 67 inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */
68 68
69 /* bcr_18 |= 0x0800 */ 69 /* bcr_18 |= 0x0800 */
70 outw(18, ioaddr + PCNET32_WIO_RAP); 70 outw(18, ioaddr + PCNET32_WIO_RAP);
71 temp = inw(ioaddr + PCNET32_WIO_BDP); 71 temp = inw(ioaddr + PCNET32_WIO_BDP);
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index b9296d9942b3..bf2c41d1e9c5 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -56,7 +56,7 @@ static void __init malta_piix_func0_fixup(struct pci_dev *pdev)
56 0, 0, 0, 3, 56 0, 0, 0, 3,
57 4, 5, 6, 7, 57 4, 5, 6, 7,
58 0, 9, 10, 11, 58 0, 9, 10, 11,
59 12, 0, 14, 15 59 12, 0, 14, 15
60 }; 60 };
61 int i; 61 int i;
62 62
diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c
index de4e443da208..ceeb1860895a 100644
--- a/arch/mips/pci/fixup-rbtx4927.c
+++ b/arch/mips/pci/fixup-rbtx4927.c
@@ -7,7 +7,7 @@
7 * Author: MontaVista Software, Inc. 7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com 8 * ppopov@mvista.com or source@mvista.com
9 * 9 *
10 * Copyright (C) 2000-2001 Toshiba Corporation 10 * Copyright (C) 2000-2001 Toshiba Corporation
11 * 11 *
12 * Copyright (C) 2004 MontaVista Software Inc. 12 * Copyright (C) 2004 MontaVista Software Inc.
13 * Author: Manish Lachwani (mlachwani@mvista.com) 13 * Author: Manish Lachwani (mlachwani@mvista.com)
diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c
index c8ef01a017cc..a176f2ca8656 100644
--- a/arch/mips/pci/fixup-sni.c
+++ b/arch/mips/pci/fixup-sni.c
@@ -32,7 +32,7 @@
32 * Device 4: Unused 32 * Device 4: Unused
33 * Device 5: Slot 2 33 * Device 5: Slot 2
34 * Device 6: Slot 3 34 * Device 6: Slot 3
35 * Device 7: Slot 4 35 * Device 7: Slot 4
36 * 36 *
37 * Documentation says the VGA is device 5 and device 3 is unused but that 37 * Documentation says the VGA is device 5 and device 3 is unused but that
38 * seem to be a documentation error. At least on my RM200C the Cirrus 38 * seem to be a documentation error. At least on my RM200C the Cirrus
diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c
index 850a900f0eb4..bc55b06e1904 100644
--- a/arch/mips/pci/fixup-tb0219.c
+++ b/arch/mips/pci/fixup-tb0219.c
@@ -29,27 +29,12 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
29 29
30 switch (slot) { 30 switch (slot) {
31 case 12: 31 case 12:
32 vr41xx_set_irq_trigger(TB0219_PCI_SLOT1_PIN,
33 TRIGGER_LEVEL,
34 SIGNAL_THROUGH);
35 vr41xx_set_irq_level(TB0219_PCI_SLOT1_PIN,
36 LEVEL_LOW);
37 irq = TB0219_PCI_SLOT1_IRQ; 32 irq = TB0219_PCI_SLOT1_IRQ;
38 break; 33 break;
39 case 13: 34 case 13:
40 vr41xx_set_irq_trigger(TB0219_PCI_SLOT2_PIN,
41 TRIGGER_LEVEL,
42 SIGNAL_THROUGH);
43 vr41xx_set_irq_level(TB0219_PCI_SLOT2_PIN,
44 LEVEL_LOW);
45 irq = TB0219_PCI_SLOT2_IRQ; 35 irq = TB0219_PCI_SLOT2_IRQ;
46 break; 36 break;
47 case 14: 37 case 14:
48 vr41xx_set_irq_trigger(TB0219_PCI_SLOT3_PIN,
49 TRIGGER_LEVEL,
50 SIGNAL_THROUGH);
51 vr41xx_set_irq_level(TB0219_PCI_SLOT3_PIN,
52 LEVEL_LOW);
53 irq = TB0219_PCI_SLOT3_IRQ; 38 irq = TB0219_PCI_SLOT3_IRQ;
54 break; 39 break;
55 default: 40 default:
diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c
index e955443fedf9..0406b50a37d8 100644
--- a/arch/mips/pci/ops-ddb5477.c
+++ b/arch/mips/pci/ops-ddb5477.c
@@ -127,7 +127,7 @@ static inline void ddb_close_config_base(struct pci_config_swap *swap)
127} 127}
128 128
129static int read_config_dword(struct pci_config_swap *swap, 129static int read_config_dword(struct pci_config_swap *swap,
130 struct pci_bus *bus, u32 devfn, u32 where, 130 struct pci_bus *bus, u32 devfn, u32 where,
131 u32 * val) 131 u32 * val)
132{ 132{
133 u32 bus_num, slot_num, func_num; 133 u32 bus_num, slot_num, func_num;
@@ -153,7 +153,7 @@ static int read_config_dword(struct pci_config_swap *swap,
153} 153}
154 154
155static int read_config_word(struct pci_config_swap *swap, 155static int read_config_word(struct pci_config_swap *swap,
156 struct pci_bus *bus, u32 devfn, u32 where, 156 struct pci_bus *bus, u32 devfn, u32 where,
157 u16 * val) 157 u16 * val)
158{ 158{
159 int status; 159 int status;
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index 2a9d7227fe87..7688b7711329 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -1,16 +1,16 @@
1/* 1/*
2 * Copyright 2001 MontaVista Software Inc. 2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. 3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com 4 * ahennessy@mvista.com
5 * 5 *
6 * Copyright (C) 2000-2001 Toshiba Corporation 6 * Copyright (C) 2000-2001 Toshiba Corporation
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 * 8 *
9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c 9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
10 * 10 *
11 * Define the pci_ops for the Toshiba rbtx4927 11 * Define the pci_ops for the Toshiba rbtx4927
12 * 12 *
13 * Much of the code is derived from the original DDB5074 port by 13 * Much of the code is derived from the original DDB5074 port by
14 * Geert Uytterhoeven <geert@sonycom.com> 14 * Geert Uytterhoeven <geert@sonycom.com>
15 * 15 *
16 * Copyright 2004 MontaVista Software Inc. 16 * Copyright 2004 MontaVista Software Inc.
diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c
index 4ddd53eaf656..826d653184e5 100644
--- a/arch/mips/pci/pci-ddb5477.c
+++ b/arch/mips/pci/pci-ddb5477.c
@@ -76,7 +76,7 @@ struct pci_controller ddb5477_io_controller = {
76 */ 76 */
77 77
78/* 78/*
79 * irq mapping : device -> pci int # -> vrc4377 irq# , 79 * irq mapping : device -> pci int # -> vrc4377 irq# ,
80 * ddb5477 board manual page 4 and vrc5477 manual page 46 80 * ddb5477 board manual page 4 and vrc5477 manual page 46
81 */ 81 */
82 82
@@ -137,9 +137,9 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
137 unsigned char *slot_irq_map; 137 unsigned char *slot_irq_map;
138 unsigned char irq; 138 unsigned char irq;
139 139
140 /* 140 /*
141 * We ignore the swizzled slot and pin values. The original 141 * We ignore the swizzled slot and pin values. The original
142 * pci_fixup_irq() codes largely base irq number on the dev slot 142 * pci_fixup_irq() codes largely base irq number on the dev slot
143 * numbers because except for one case they are unique even 143 * numbers because except for one case they are unique even
144 * though there are multiple pci buses. 144 * though there are multiple pci buses.
145 */ 145 */
@@ -160,7 +160,7 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
160 160
161 if (mips_machtype == MACH_NEC_ROCKHOPPERII) { 161 if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
162 /* hack to distinquish overlapping slot 20s, one 162 /* hack to distinquish overlapping slot 20s, one
163 * on bus 0 (ALI USB on the M1535 on the backplane), 163 * on bus 0 (ALI USB on the M1535 on the backplane),
164 * and one on bus 2 (NEC USB controller on the CPU board) 164 * and one on bus 2 (NEC USB controller on the CPU board)
165 * Make the M1535 USB - ISA IRQ number 9. 165 * Make the M1535 USB - ISA IRQ number 9.
166 */ 166 */
diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c
index 1faeb034f06e..000dc6af6cd3 100644
--- a/arch/mips/pci/pci-ip32.c
+++ b/arch/mips/pci/pci-ip32.c
@@ -84,7 +84,7 @@ static irqreturn_t macepci_error(int irq, void *dev, struct pt_regs *regs)
84 84
85 85
86extern struct pci_ops mace_pci_ops; 86extern struct pci_ops mace_pci_ops;
87#ifdef CONFIG_MIPS64 87#ifdef CONFIG_64BIT
88static struct resource mace_pci_mem_resource = { 88static struct resource mace_pci_mem_resource = {
89 .name = "SGI O2 PCI MEM", 89 .name = "SGI O2 PCI MEM",
90 .start = MACEPCI_HI_MEMORY, 90 .start = MACEPCI_HI_MEMORY,
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 8141dffac241..a8d499b0a36f 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -132,7 +132,7 @@ static int __init pcibios_init(void)
132 hose->need_domain_info = need_domain_info; 132 hose->need_domain_info = need_domain_info;
133 next_busno = bus->subordinate + 1; 133 next_busno = bus->subordinate + 1;
134 /* Don't allow 8-bit bus number overflow inside the hose - 134 /* Don't allow 8-bit bus number overflow inside the hose -
135 reserve some space for bridges. */ 135 reserve some space for bridges. */
136 if (next_busno > 224) { 136 if (next_busno > 224) {
137 next_busno = 0; 137 next_busno = 0;
138 need_domain_info = 1; 138 need_domain_info = 1;
@@ -260,7 +260,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
260 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 260 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
261 pci_read_bridge_bases(bus); 261 pci_read_bridge_bases(bus);
262 pcibios_fixup_device_resources(dev, bus); 262 pcibios_fixup_device_resources(dev, bus);
263 } 263 }
264 264
265 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { 265 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
266 struct pci_dev *dev = pci_dev_b(ln); 266 struct pci_dev *dev = pci_dev_b(ln);
@@ -292,8 +292,25 @@ pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
292 region->end = res->end - offset; 292 region->end = res->end - offset;
293} 293}
294 294
295void __devinit
296pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
297 struct pci_bus_region *region)
298{
299 struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
300 unsigned long offset = 0;
301
302 if (res->flags & IORESOURCE_IO)
303 offset = hose->io_offset;
304 else if (res->flags & IORESOURCE_MEM)
305 offset = hose->mem_offset;
306
307 res->start = region->start + offset;
308 res->end = region->end + offset;
309}
310
295#ifdef CONFIG_HOTPLUG 311#ifdef CONFIG_HOTPLUG
296EXPORT_SYMBOL(pcibios_resource_to_bus); 312EXPORT_SYMBOL(pcibios_resource_to_bus);
313EXPORT_SYMBOL(pcibios_bus_to_resource);
297EXPORT_SYMBOL(PCIBIOS_MIN_IO); 314EXPORT_SYMBOL(PCIBIOS_MIN_IO);
298EXPORT_SYMBOL(PCIBIOS_MIN_MEM); 315EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
299#endif 316#endif
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
index b067988614c3..97862f45496d 100644
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
+++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
@@ -30,7 +30,7 @@
30 * 30 *
31 * This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL 31 * This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL
32 * 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program 32 * 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program
33 * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are 33 * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are
34 * expected to have a connectivity from the EEPROM to the serial port. This program does 34 * expected to have a connectivity from the EEPROM to the serial port. This program does
35 * __not__ communicate using the I2C protocol 35 * __not__ communicate using the I2C protocol
36 */ 36 */
@@ -64,14 +64,14 @@ static void send_ack(void)
64static void send_byte(unsigned char byte) 64static void send_byte(unsigned char byte)
65{ 65{
66 int i = 0; 66 int i = 0;
67 67
68 for (i = 7; i >= 0; i--) 68 for (i = 7; i >= 0; i--)
69 send_bit((byte >> i) & 0x01); 69 send_bit((byte >> i) & 0x01);
70} 70}
71 71
72static void send_start(void) 72static void send_start(void)
73{ 73{
74 sda_hi; 74 sda_hi;
75 delay(TXX); 75 delay(TXX);
76 scl_hi; 76 scl_hi;
77 delay(TXX); 77 delay(TXX);
@@ -114,9 +114,9 @@ static unsigned char recv_byte(void) {
114 int i; 114 int i;
115 unsigned char byte=0; 115 unsigned char byte=0;
116 116
117 for (i=7;i>=0;i--) 117 for (i=7;i>=0;i--)
118 byte |= (recv_bit() << i); 118 byte |= (recv_bit() << i);
119 119
120 return byte; 120 return byte;
121} 121}
122 122
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
index d27566d99ffc..c19f01a32045 100644
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
+++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
@@ -27,7 +27,7 @@
27 */ 27 */
28 28
29/* 29/*
30 * Header file for atmel_read_eeprom.c 30 * Header file for atmel_read_eeprom.c
31 */ 31 */
32 32
33#include <linux/types.h> 33#include <linux/types.h>
@@ -46,7 +46,7 @@
46#define DEFAULT_PORT "/dev/ttyS0" /* Port to open */ 46#define DEFAULT_PORT "/dev/ttyS0" /* Port to open */
47#define TXX 0 /* Dummy loop for spinning */ 47#define TXX 0 /* Dummy loop for spinning */
48 48
49#define BLOCK_SEL 0x00 49#define BLOCK_SEL 0x00
50#define SLAVE_ADDR 0xa0 50#define SLAVE_ADDR 0xa0
51#define READ_BIT 0x01 51#define READ_BIT 0x01
52#define WRITE_BIT 0x00 52#define WRITE_BIT 0x00
diff --git a/arch/mips/qemu/Makefile b/arch/mips/qemu/Makefile
new file mode 100644
index 000000000000..934944ab9e85
--- /dev/null
+++ b/arch/mips/qemu/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for Qemu specific kernel interface routines under Linux.
3#
4
5obj-y = q-firmware.o q-int.o q-irq.o q-mem.o q-setup.o
diff --git a/arch/mips/qemu/q-firmware.c b/arch/mips/qemu/q-firmware.c
new file mode 100644
index 000000000000..5980f02b2df9
--- /dev/null
+++ b/arch/mips/qemu/q-firmware.c
@@ -0,0 +1,7 @@
1#include <linux/init.h>
2#include <asm/bootinfo.h>
3
4void __init prom_init(void)
5{
6 add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM);
7}
diff --git a/arch/mips/qemu/q-int.S b/arch/mips/qemu/q-int.S
new file mode 100644
index 000000000000..6e3dfe5eb14b
--- /dev/null
+++ b/arch/mips/qemu/q-int.S
@@ -0,0 +1,17 @@
1/*
2 * Qemu interrupt handler code.
3 *
4 * Copyright (C) 2005 by Ralf Baechle
5 */
6#include <asm/asm.h>
7#include <asm/regdef.h>
8#include <asm/stackframe.h>
9
10 .align 5
11 NESTED(qemu_handle_int, PT_SIZE, sp)
12 SAVE_ALL
13 CLI
14 move a0, sp
15 PTR_LA ra, ret_from_irq
16 j do_qemu_int
17 END(qemu_handle_int)
diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c
new file mode 100644
index 000000000000..2c4e0704ff10
--- /dev/null
+++ b/arch/mips/qemu/q-irq.c
@@ -0,0 +1,37 @@
1#include <linux/init.h>
2#include <linux/linkage.h>
3
4#include <asm/i8259.h>
5#include <asm/mipsregs.h>
6#include <asm/qemu.h>
7#include <asm/system.h>
8#include <asm/time.h>
9
10extern asmlinkage void qemu_handle_int(void);
11
12asmlinkage void do_qemu_int(struct pt_regs *regs)
13{
14 unsigned int pending = read_c0_status() & read_c0_cause();
15
16 if (pending & 0x8000) {
17 ll_timer_interrupt(Q_COUNT_COMPARE_IRQ, regs);
18 return;
19 }
20 if (pending & 0x0400) {
21 int irq = i8259_irq();
22
23 if (likely(irq >= 0))
24 do_IRQ(irq, regs);
25
26 return;
27 }
28}
29
30void __init arch_init_irq(void)
31{
32 set_except_vector(0, qemu_handle_int);
33 mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */
34
35 init_i8259_irqs();
36 set_c0_status(0x8400);
37}
diff --git a/arch/mips/qemu/q-mem.c b/arch/mips/qemu/q-mem.c
new file mode 100644
index 000000000000..d174fac43031
--- /dev/null
+++ b/arch/mips/qemu/q-mem.c
@@ -0,0 +1,6 @@
1#include <linux/init.h>
2
3unsigned long __init prom_free_prom_memory(void)
4{
5 return 0UL;
6}
diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c
new file mode 100644
index 000000000000..1a80eee8cd35
--- /dev/null
+++ b/arch/mips/qemu/q-setup.c
@@ -0,0 +1,20 @@
1#include <linux/init.h>
2#include <asm/io.h>
3#include <asm/time.h>
4
5#define QEMU_PORT_BASE 0xb4000000
6
7static void __init qemu_timer_setup(struct irqaction *irq)
8{
9 /* set the clock to 100 Hz */
10 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
11 outb_p(LATCH & 0xff , 0x40); /* LSB */
12 outb(LATCH >> 8 , 0x40); /* MSB */
13 setup_irq(0, irq);
14}
15
16void __init plat_setup(void)
17{
18 set_io_port_base(QEMU_PORT_BASE);
19 board_timer_setup = qemu_timer_setup;
20}
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 0ab4abf65d58..fa0e719c5bd1 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -242,7 +242,7 @@ int __init ip22_eisa_init(void)
242 int i, c; 242 int i, c;
243 char *str; 243 char *str;
244 u8 *slot_addr; 244 u8 *slot_addr;
245 245
246 if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) { 246 if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) {
247 printk(KERN_INFO "EISA: bus not present.\n"); 247 printk(KERN_INFO "EISA: bus not present.\n");
248 return 1; 248 return 1;
diff --git a/arch/mips/sgi-ip22/ip22-hpc.c b/arch/mips/sgi-ip22/ip22-hpc.c
index c0afeccb08c4..5c00cdd20d8e 100644
--- a/arch/mips/sgi-ip22/ip22-hpc.c
+++ b/arch/mips/sgi-ip22/ip22-hpc.c
@@ -49,7 +49,7 @@ void __init sgihpc_init(void)
49 sgint = &sgioc->int3; 49 sgint = &sgioc->int3;
50 system_type = "SGI Indy"; 50 system_type = "SGI Indy";
51 } 51 }
52 52
53 sgi_ioc_reset = (SGIOC_RESET_PPORT | SGIOC_RESET_KBDMOUSE | 53 sgi_ioc_reset = (SGIOC_RESET_PPORT | SGIOC_RESET_KBDMOUSE |
54 SGIOC_RESET_EISA | SGIOC_RESET_ISDN | 54 SGIOC_RESET_EISA | SGIOC_RESET_ISDN |
55 SGIOC_RESET_LC0OFF); 55 SGIOC_RESET_LC0OFF);
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index ea2844d29e6e..d16fb43b1a93 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -28,7 +28,7 @@
28/* #define DEBUG_SGINT */ 28/* #define DEBUG_SGINT */
29 29
30/* So far nothing hangs here */ 30/* So far nothing hangs here */
31#undef USE_LIO3_IRQ 31#undef USE_LIO3_IRQ
32 32
33struct sgint_regs *sgint; 33struct sgint_regs *sgint;
34 34
@@ -272,32 +272,32 @@ void indy_buserror_irq(struct pt_regs *regs)
272 irq_exit(); 272 irq_exit();
273} 273}
274 274
275static struct irqaction local0_cascade = { 275static struct irqaction local0_cascade = {
276 .handler = no_action, 276 .handler = no_action,
277 .flags = SA_INTERRUPT, 277 .flags = SA_INTERRUPT,
278 .name = "local0 cascade", 278 .name = "local0 cascade",
279}; 279};
280 280
281static struct irqaction local1_cascade = { 281static struct irqaction local1_cascade = {
282 .handler = no_action, 282 .handler = no_action,
283 .flags = SA_INTERRUPT, 283 .flags = SA_INTERRUPT,
284 .name = "local1 cascade", 284 .name = "local1 cascade",
285}; 285};
286 286
287static struct irqaction buserr = { 287static struct irqaction buserr = {
288 .handler = no_action, 288 .handler = no_action,
289 .flags = SA_INTERRUPT, 289 .flags = SA_INTERRUPT,
290 .name = "Bus Error", 290 .name = "Bus Error",
291}; 291};
292 292
293static struct irqaction map0_cascade = { 293static struct irqaction map0_cascade = {
294 .handler = no_action, 294 .handler = no_action,
295 .flags = SA_INTERRUPT, 295 .flags = SA_INTERRUPT,
296 .name = "mapable0 cascade", 296 .name = "mapable0 cascade",
297}; 297};
298 298
299#ifdef USE_LIO3_IRQ 299#ifdef USE_LIO3_IRQ
300static struct irqaction map1_cascade = { 300static struct irqaction map1_cascade = {
301 .handler = no_action, 301 .handler = no_action,
302 .flags = SA_INTERRUPT, 302 .flags = SA_INTERRUPT,
303 .name = "mapable1 cascade", 303 .name = "mapable1 cascade",
diff --git a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c
index de43e86fa17c..fd29fd407ae8 100644
--- a/arch/mips/sgi-ip22/ip22-nvram.c
+++ b/arch/mips/sgi-ip22/ip22-nvram.c
@@ -39,7 +39,7 @@
39 *ptr |= EEPROM_CSEL; \ 39 *ptr |= EEPROM_CSEL; \
40 *ptr |= EEPROM_ECLK; }) 40 *ptr |= EEPROM_ECLK; })
41 41
42 42
43#define eeprom_cs_off(ptr) ({ \ 43#define eeprom_cs_off(ptr) ({ \
44 *ptr &= ~EEPROM_ECLK; \ 44 *ptr &= ~EEPROM_ECLK; \
45 *ptr &= ~EEPROM_CSEL; \ 45 *ptr &= ~EEPROM_CSEL; \
@@ -50,7 +50,7 @@
50/* 50/*
51 * clock in the nvram command and the register number. For the 51 * clock in the nvram command and the register number. For the
52 * national semiconductor nv ram chip the op code is 3 bits and 52 * national semiconductor nv ram chip the op code is 3 bits and
53 * the address is 6/8 bits. 53 * the address is 6/8 bits.
54 */ 54 */
55static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd, 55static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd,
56 unsigned reg) 56 unsigned reg)
@@ -90,7 +90,7 @@ unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg)
90 if (*ctrl & EEPROM_DATI) 90 if (*ctrl & EEPROM_DATI)
91 res |= 1; 91 res |= 1;
92 } 92 }
93 93
94 eeprom_cs_off(ctrl); 94 eeprom_cs_off(ctrl);
95 95
96 return res; 96 return res;
@@ -113,7 +113,7 @@ unsigned short ip22_nvram_read(int reg)
113 reg <<= 1; 113 reg <<= 1;
114 tmp = hpc3c0->bbram[reg++] & 0xff; 114 tmp = hpc3c0->bbram[reg++] & 0xff;
115 return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff); 115 return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff);
116 } 116 }
117} 117}
118 118
119EXPORT_SYMBOL(ip22_nvram_read); 119EXPORT_SYMBOL(ip22_nvram_read);
diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c
index ed5c60adce63..214ffd2e98a3 100644
--- a/arch/mips/sgi-ip22/ip22-reset.c
+++ b/arch/mips/sgi-ip22/ip22-reset.c
@@ -185,7 +185,7 @@ static irqreturn_t panel_int(int irq, void *dev_id, struct pt_regs *regs)
185 add_timer(&debounce_timer); 185 add_timer(&debounce_timer);
186 } 186 }
187 187
188 /* Power button was pressed 188 /* Power button was pressed
189 * ioc.ps page 22: "The Panel Register is called Power Control by Full 189 * ioc.ps page 22: "The Panel Register is called Power Control by Full
190 * House. Only lowest 2 bits are used. Guiness uses upper four bits 190 * House. Only lowest 2 bits are used. Guiness uses upper four bits
191 * for volume control". This is not true, all bits are pulled high 191 * for volume control". This is not true, all bits are pulled high
diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c
index 173f76805ea3..df9b5694328a 100644
--- a/arch/mips/sgi-ip22/ip22-time.c
+++ b/arch/mips/sgi-ip22/ip22-time.c
@@ -126,7 +126,7 @@ static __init void indy_time_init(void)
126 unsigned long r4k_ticks[3]; 126 unsigned long r4k_ticks[3];
127 unsigned long r4k_tick; 127 unsigned long r4k_tick;
128 128
129 /* 129 /*
130 * Figure out the r4k offset, the algorithm is very simple and works in 130 * Figure out the r4k offset, the algorithm is very simple and works in
131 * _all_ cases as long as the 8254 counter register itself works ok (as 131 * _all_ cases as long as the 8254 counter register itself works ok (as
132 * an interrupt driving timer it does not because of bug, this is why 132 * an interrupt driving timer it does not because of bug, this is why
diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c
index a160d04f7dbe..ef20d9ac0ba3 100644
--- a/arch/mips/sgi-ip27/ip27-memory.c
+++ b/arch/mips/sgi-ip27/ip27-memory.c
@@ -538,7 +538,7 @@ void __init mem_init(void)
538 for_each_online_node(node) { 538 for_each_online_node(node) {
539 unsigned slot, numslots; 539 unsigned slot, numslots;
540 struct page *end, *p; 540 struct page *end, *p;
541 541
542 /* 542 /*
543 * This will free up the bootmem, ie, slot 0 memory. 543 * This will free up the bootmem, ie, slot 0 memory.
544 */ 544 */
diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c
index 281f090e48a4..88e1f52059ff 100644
--- a/arch/mips/sgi-ip32/ip32-reset.c
+++ b/arch/mips/sgi-ip32/ip32-reset.c
@@ -140,7 +140,7 @@ static irqreturn_t ip32_rtc_int(int irq, void *dev_id, struct pt_regs *regs)
140 140
141 reg_c = CMOS_READ(RTC_INTR_FLAGS); 141 reg_c = CMOS_READ(RTC_INTR_FLAGS);
142 if (!(reg_c & RTC_IRQF)) { 142 if (!(reg_c & RTC_IRQF)) {
143 printk(KERN_WARNING 143 printk(KERN_WARNING
144 "%s: RTC IRQ without RTC_IRQF\n", __FUNCTION__); 144 "%s: RTC IRQ without RTC_IRQF\n", __FUNCTION__);
145 } 145 }
146 /* Wait until interrupt goes away */ 146 /* Wait until interrupt goes away */
diff --git a/arch/mips/sibyte/cfe/cfe_error.h b/arch/mips/sibyte/cfe/cfe_error.h
index 77eb4935bfb4..975f00002cbe 100644
--- a/arch/mips/sibyte/cfe/cfe_error.h
+++ b/arch/mips/sibyte/cfe/cfe_error.h
@@ -17,15 +17,15 @@
17 */ 17 */
18 18
19/* ********************************************************************* 19/* *********************************************************************
20 * 20 *
21 * Broadcom Common Firmware Environment (CFE) 21 * Broadcom Common Firmware Environment (CFE)
22 * 22 *
23 * Error codes File: cfe_error.h 23 * Error codes File: cfe_error.h
24 * 24 *
25 * CFE's global error code list is here. 25 * CFE's global error code list is here.
26 * 26 *
27 * Author: Mitch Lichtenberg 27 * Author: Mitch Lichtenberg
28 * 28 *
29 ********************************************************************* */ 29 ********************************************************************* */
30 30
31 31
diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c
index 53a5c1eb5611..7721100d0275 100644
--- a/arch/mips/sibyte/cfe/console.c
+++ b/arch/mips/sibyte/cfe/console.c
@@ -38,7 +38,7 @@ static void cfe_console_write(struct console *cons, const char *str,
38 last += written; 38 last += written;
39 } while (last < count); 39 } while (last < count);
40 } 40 }
41 41
42} 42}
43 43
44static int cfe_console_setup(struct console *cons, char *str) 44static int cfe_console_setup(struct console *cons, char *str)
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index d6d0364fa760..7a2c7a8510d4 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -33,7 +33,7 @@
33#include "cfe_error.h" 33#include "cfe_error.h"
34 34
35/* Max ram addressable in 32-bit segments */ 35/* Max ram addressable in 32-bit segments */
36#ifdef CONFIG_MIPS64 36#ifdef CONFIG_64BIT
37#define MAX_RAM_SIZE (~0ULL) 37#define MAX_RAM_SIZE (~0ULL)
38#else 38#else
39#ifdef CONFIG_HIGHMEM 39#ifdef CONFIG_HIGHMEM
@@ -285,7 +285,7 @@ void __init prom_init(void)
285 while (1) ; 285 while (1) ;
286 } 286 }
287 cfe_init(cfe_handle, cfe_ept); 287 cfe_init(cfe_handle, cfe_ept);
288 /* 288 /*
289 * Get the handle for (at least) prom_putchar, possibly for 289 * Get the handle for (at least) prom_putchar, possibly for
290 * boot console 290 * boot console
291 */ 291 */
diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c
index 73392190d2b1..e44ce1a9eea9 100644
--- a/arch/mips/sibyte/cfe/smp.c
+++ b/arch/mips/sibyte/cfe/smp.c
@@ -57,7 +57,7 @@ void __init prom_prepare_cpus(unsigned int max_cpus)
57void prom_boot_secondary(int cpu, struct task_struct *idle) 57void prom_boot_secondary(int cpu, struct task_struct *idle)
58{ 58{
59 int retval; 59 int retval;
60 60
61 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, 61 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
62 __KSTK_TOS(idle), 62 __KSTK_TOS(idle),
63 (unsigned long)idle->thread_info, 0); 63 (unsigned long)idle->thread_info, 0);
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c
index 182a16f42e2d..1a97e3127aeb 100644
--- a/arch/mips/sibyte/sb1250/bus_watcher.c
+++ b/arch/mips/sibyte/sb1250/bus_watcher.c
@@ -10,13 +10,13 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18 18
19/* 19/*
20 * The Bus Watcher monitors internal bus transactions and maintains 20 * The Bus Watcher monitors internal bus transactions and maintains
21 * counts of transactions with error status, logging details and 21 * counts of transactions with error status, logging details and
22 * causing one of several interrupts. This driver provides a handler 22 * causing one of several interrupts. This driver provides a handler
@@ -155,7 +155,7 @@ static int bw_read_proc(char *page, char **start, off_t off,
155static void create_proc_decoder(struct bw_stats_struct *stats) 155static void create_proc_decoder(struct bw_stats_struct *stats)
156{ 156{
157 struct proc_dir_entry *ent; 157 struct proc_dir_entry *ent;
158 158
159 ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL, 159 ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL,
160 bw_read_proc, stats); 160 bw_read_proc, stats);
161 if (!ent) { 161 if (!ent) {
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 2728abbc94d2..2725b263cced 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -377,7 +377,7 @@ void __init arch_init_irq(void)
377 377
378 /* 378 /*
379 * Note that the timer interrupts are also mapped, but this is 379 * Note that the timer interrupts are also mapped, but this is
380 * done in sb1250_time_init(). Also, the profiling driver 380 * done in sb1250_time_init(). Also, the profiling driver
381 * does its own management of IP7. 381 * does its own management of IP7.
382 */ 382 */
383 383
@@ -392,7 +392,7 @@ void __init arch_init_irq(void)
392 if (kgdb_flag) { 392 if (kgdb_flag) {
393 kgdb_irq = K_INT_UART_0 + kgdb_port; 393 kgdb_irq = K_INT_UART_0 + kgdb_port;
394 394
395#ifdef CONFIG_SIBYTE_SB1250_DUART 395#ifdef CONFIG_SIBYTE_SB1250_DUART
396 sb1250_duart_present[kgdb_port] = 0; 396 sb1250_duart_present[kgdb_port] = 0;
397#endif 397#endif
398 /* Setup uart 1 settings, mapper */ 398 /* Setup uart 1 settings, mapper */
diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c
index 0e633ee8d83c..a686bb716ec6 100644
--- a/arch/mips/sibyte/swarm/rtc_m41t81.c
+++ b/arch/mips/sibyte/swarm/rtc_m41t81.c
@@ -128,7 +128,7 @@ static int m41t81_write(uint8_t addr, int b)
128 /* Clear error bit by writing a 1 */ 128 /* Clear error bit by writing a 1 */
129 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); 129 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
130 return -1; 130 return -1;
131 } 131 }
132 132
133 /* read the same byte again to make sure it is written */ 133 /* read the same byte again to make sure it is written */
134 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, 134 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
@@ -136,7 +136,7 @@ static int m41t81_write(uint8_t addr, int b)
136 136
137 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) 137 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
138 ; 138 ;
139 139
140 return 0; 140 return 0;
141} 141}
142 142
@@ -148,13 +148,13 @@ int m41t81_set_time(unsigned long t)
148 148
149 /* 149 /*
150 * Note the write order matters as it ensures the correctness. 150 * Note the write order matters as it ensures the correctness.
151 * When we write sec, 10th sec is clear. It is reasonable to 151 * When we write sec, 10th sec is clear. It is reasonable to
152 * believe we should finish writing min within a second. 152 * believe we should finish writing min within a second.
153 */ 153 */
154 154
155 tm.tm_sec = BIN2BCD(tm.tm_sec); 155 tm.tm_sec = BIN2BCD(tm.tm_sec);
156 m41t81_write(M41T81REG_SC, tm.tm_sec); 156 m41t81_write(M41T81REG_SC, tm.tm_sec);
157 157
158 tm.tm_min = BIN2BCD(tm.tm_min); 158 tm.tm_min = BIN2BCD(tm.tm_min);
159 m41t81_write(M41T81REG_MN, tm.tm_min); 159 m41t81_write(M41T81REG_MN, tm.tm_min);
160 160
@@ -187,7 +187,7 @@ unsigned long m41t81_get_time(void)
187{ 187{
188 unsigned int year, mon, day, hour, min, sec; 188 unsigned int year, mon, day, hour, min, sec;
189 189
190 /* 190 /*
191 * min is valid if two reads of sec are the same. 191 * min is valid if two reads of sec are the same.
192 */ 192 */
193 for (;;) { 193 for (;;) {
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index 457aeb7be858..4daeaa413def 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -73,7 +73,7 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup)
73{ 73{
74 if (!is_fixup && (regs->cp0_cause & 4)) { 74 if (!is_fixup && (regs->cp0_cause & 4)) {
75 /* Data bus error - print PA */ 75 /* Data bus error - print PA */
76#ifdef CONFIG_MIPS64 76#ifdef CONFIG_64BIT
77 printk("DBE physical address: %010lx\n", 77 printk("DBE physical address: %010lx\n",
78 __read_64bit_c0_register($26, 1)); 78 __read_64bit_c0_register($26, 1));
79#else 79#else
@@ -98,7 +98,7 @@ static int __init swarm_setup(void)
98 rtc_get_time = xicor_get_time; 98 rtc_get_time = xicor_get_time;
99 rtc_set_time = xicor_set_time; 99 rtc_set_time = xicor_set_time;
100 } 100 }
101 101
102 if (m41t81_probe()) { 102 if (m41t81_probe()) {
103 printk("swarm setup: M41T81 RTC detected.\n"); 103 printk("swarm setup: M41T81 RTC detected.\n");
104 rtc_get_time = m41t81_get_time; 104 rtc_get_time = m41t81_get_time;
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 62c760f14674..141a310d74d8 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -103,7 +103,7 @@ static unsigned int ls1bit8(unsigned int x)
103 103
104/* 104/*
105 * hwint 1 deals with EISA and SCSI interrupts, 105 * hwint 1 deals with EISA and SCSI interrupts,
106 * 106 *
107 * The EISA_INT bit in CSITPEND is high active, all others are low active. 107 * The EISA_INT bit in CSITPEND is high active, all others are low active.
108 */ 108 */
109void pciasic_hwint1(struct pt_regs *regs) 109void pciasic_hwint1(struct pt_regs *regs)
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index 8f67cee4317b..1b3f8a0903e1 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -111,7 +111,7 @@ static struct resource sni_mem_resource = {
111 * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used 111 * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
112 * for other purposes. Be paranoid and allocate all of the before the PCI 112 * for other purposes. Be paranoid and allocate all of the before the PCI
113 * code gets a chance to to map anything else there ... 113 * code gets a chance to to map anything else there ...
114 * 114 *
115 * This leaves the following areas available: 115 * This leaves the following areas available:
116 * 116 *
117 * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory 117 * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
diff --git a/arch/mips/tx4927/common/tx4927_irq_handler.S b/arch/mips/tx4927/common/tx4927_irq_handler.S
index ca123e28d1ef..dd3ceda9d712 100644
--- a/arch/mips/tx4927/common/tx4927_irq_handler.S
+++ b/arch/mips/tx4927/common/tx4927_irq_handler.S
@@ -42,13 +42,13 @@
42 CLI 42 CLI
43 .set at 43 .set at
44 44
45 mfc0 t0, CP0_CAUSE 45 mfc0 t0, CP0_CAUSE
46 mfc0 t1, CP0_STATUS 46 mfc0 t1, CP0_STATUS
47 and t0, t1 47 and t0, t1
48 48
49 andi t1, t0, STATUSF_IP7 /* cpu timer */ 49 andi t1, t0, STATUSF_IP7 /* cpu timer */
50 bnez t1, ll_ip7 50 bnez t1, ll_ip7
51 51
52 /* IP6..IP3 multiplexed -- do not use */ 52 /* IP6..IP3 multiplexed -- do not use */
53 53
54 andi t1, t0, STATUSF_IP2 /* tx4927 pic */ 54 andi t1, t0, STATUSF_IP2 /* tx4927 pic */
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
index 16bcbdc6d1cc..26d7c53612a8 100644
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -152,7 +152,7 @@ dump_cp0(char *key)
152 print_cp0(key, 16, "CONFIG ", read_c0_config()); 152 print_cp0(key, 16, "CONFIG ", read_c0_config());
153 return; 153 return;
154} 154}
155 155
156void print_pic(char *key, u32 reg, char *name) 156void print_pic(char *key, u32 reg, char *name)
157{ 157{
158 printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name, 158 printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name,
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/Makefile b/arch/mips/tx4927/toshiba_rbtx4927/Makefile
index 86ca4cf2d587..c1a377a80a5d 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/Makefile
+++ b/arch/mips/tx4927/toshiba_rbtx4927/Makefile
@@ -1,5 +1,5 @@
1obj-y += toshiba_rbtx4927_prom.o 1obj-y += toshiba_rbtx4927_prom.o
2obj-y += toshiba_rbtx4927_setup.o 2obj-y += toshiba_rbtx4927_setup.o
3obj-y += toshiba_rbtx4927_irq.o 3obj-y += toshiba_rbtx4927_irq.o
4 4
5EXTRA_AFLAGS := $(CFLAGS) 5EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index fd5b433f83b7..aee07ff2212a 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -31,7 +31,7 @@
31 31
32 32
33/* 33/*
34IRQ Device 34IRQ Device
3500 RBTX4927-ISA/00 3500 RBTX4927-ISA/00
3601 RBTX4927-ISA/01 PS2/Keyboard 3601 RBTX4927-ISA/01 PS2/Keyboard
3702 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15) 3702 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
@@ -52,15 +52,15 @@ IRQ Device
5216 TX4927-CP0/00 Software 0 5216 TX4927-CP0/00 Software 0
5317 TX4927-CP0/01 Software 1 5317 TX4927-CP0/01 Software 1
5418 TX4927-CP0/02 Cascade TX4927-CP0 5418 TX4927-CP0/02 Cascade TX4927-CP0
5519 TX4927-CP0/03 Multiplexed -- do not use 5519 TX4927-CP0/03 Multiplexed -- do not use
5620 TX4927-CP0/04 Multiplexed -- do not use 5620 TX4927-CP0/04 Multiplexed -- do not use
5721 TX4927-CP0/05 Multiplexed -- do not use 5721 TX4927-CP0/05 Multiplexed -- do not use
5822 TX4927-CP0/06 Multiplexed -- do not use 5822 TX4927-CP0/06 Multiplexed -- do not use
5923 TX4927-CP0/07 CPU TIMER 5923 TX4927-CP0/07 CPU TIMER
60 60
6124 TX4927-PIC/00 6124 TX4927-PIC/00
6225 TX4927-PIC/01 6225 TX4927-PIC/01
6326 TX4927-PIC/02 6326 TX4927-PIC/02
6427 TX4927-PIC/03 Cascade RBTX4927-IOC 6427 TX4927-PIC/03 Cascade RBTX4927-IOC
6528 TX4927-PIC/04 6528 TX4927-PIC/04
6629 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet 6629 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
@@ -80,7 +80,7 @@ IRQ Device
8043 TX4927-PIC/19 8043 TX4927-PIC/19
8144 TX4927-PIC/20 8144 TX4927-PIC/20
8245 TX4927-PIC/21 8245 TX4927-PIC/21
8346 TX4927-PIC/22 TX4927 PCI PCI-ERR 8346 TX4927-PIC/22 TX4927 PCI PCI-ERR
8447 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used) 8447 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
8548 TX4927-PIC/24 8548 TX4927-PIC/24
8649 TX4927-PIC/25 8649 TX4927-PIC/25
@@ -100,7 +100,7 @@ IRQ Device
10062 RBTX4927-IOC/06 10062 RBTX4927-IOC/06
10163 RBTX4927-IOC/07 10163 RBTX4927-IOC/07
102 102
103NOTES: 103NOTES:
104SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58 104SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
105SouthBridge/ISA/pin=0 no pci irq used by this device 105SouthBridge/ISA/pin=0 no pci irq used by this device
106SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14 106SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
@@ -175,19 +175,19 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
175static const u32 toshiba_rbtx4927_irq_debug_flag = 175static const u32 toshiba_rbtx4927_irq_debug_flag =
176 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | 176 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
177 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR 177 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
178// | TOSHIBA_RBTX4927_IRQ_IOC_INIT 178// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
179// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP 179// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
180// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN 180// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
181// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE 181// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
182// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE 182// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
183// | TOSHIBA_RBTX4927_IRQ_IOC_MASK 183// | TOSHIBA_RBTX4927_IRQ_IOC_MASK
184// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ 184// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
185// | TOSHIBA_RBTX4927_IRQ_ISA_INIT 185// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
186// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP 186// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
187// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN 187// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
188// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE 188// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
189// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE 189// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
190// | TOSHIBA_RBTX4927_IRQ_ISA_MASK 190// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
191// | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ 191// | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
192 ); 192 );
193#endif 193#endif
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index 8724ea3ae04e..fc0720599fd9 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -395,7 +395,7 @@ static int __init tx4927_pcibios_init(void)
395 /* enable secondary ide */ 395 /* enable secondary ide */
396 v08_43 |= 0x80; 396 v08_43 |= 0x80;
397 397
398 /* 398 /*
399 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!! 399 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
400 * 400 *
401 * This line of code is intended to provide the user with a work 401 * This line of code is intended to provide the user with a work
diff --git a/arch/mips/vr4181/common/Makefile b/arch/mips/vr4181/common/Makefile
deleted file mode 100644
index f7587ca64ead..000000000000
--- a/arch/mips/vr4181/common/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for common code of NEC vr4181 based boards
3#
4
5obj-y := irq.o int_handler.o serial.o time.o
6
7EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/vr4181/common/int_handler.S b/arch/mips/vr4181/common/int_handler.S
deleted file mode 100644
index 2c041b8ee52b..000000000000
--- a/arch/mips/vr4181/common/int_handler.S
+++ /dev/null
@@ -1,206 +0,0 @@
1/*
2 * arch/mips/vr4181/common/int_handler.S
3 *
4 * Adapted to the VR4181 and almost entirely rewritten:
5 * Copyright (C) 1999 Bradley D. LaRonde and Michael Klar
6 *
7 * Clean up to conform to the new IRQ
8 * Copyright (C) 2001 MontaVista Software Inc.
9 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 *
15 */
16
17#include <asm/asm.h>
18#include <asm/regdef.h>
19#include <asm/mipsregs.h>
20#include <asm/stackframe.h>
21
22#include <asm/vr4181/vr4181.h>
23
24/*
25 * [jsun]
26 * See include/asm/vr4181/irq.h for IRQ assignment and strategy.
27 */
28
29 .text
30 .set noreorder
31
32 .align 5
33 NESTED(vr4181_handle_irq, PT_SIZE, ra)
34
35 .set noat
36 SAVE_ALL
37 CLI
38
39 .set at
40 .set noreorder
41
42 mfc0 t0, CP0_CAUSE
43 mfc0 t2, CP0_STATUS
44
45 and t0, t2
46
47 /* we check IP3 first; it happens most frequently */
48 andi t1, t0, STATUSF_IP3
49 bnez t1, ll_cpu_ip3
50 andi t1, t0, STATUSF_IP2
51 bnez t1, ll_cpu_ip2
52 andi t1, t0, STATUSF_IP7 /* cpu timer */
53 bnez t1, ll_cputimer_irq
54 andi t1, t0, STATUSF_IP4
55 bnez t1, ll_cpu_ip4
56 andi t1, t0, STATUSF_IP5
57 bnez t1, ll_cpu_ip5
58 andi t1, t0, STATUSF_IP6
59 bnez t1, ll_cpu_ip6
60 andi t1, t0, STATUSF_IP0 /* software int 0 */
61 bnez t1, ll_cpu_ip0
62 andi t1, t0, STATUSF_IP1 /* software int 1 */
63 bnez t1, ll_cpu_ip1
64 nop
65
66 .set reorder
67do_spurious:
68 j spurious_interrupt
69
70/*
71 * regular CPU irqs
72 */
73ll_cputimer_irq:
74 li a0, VR4181_IRQ_TIMER
75 move a1, sp
76 jal do_IRQ
77 j ret_from_irq
78
79
80ll_cpu_ip0:
81 li a0, VR4181_IRQ_SW1
82 move a1, sp
83 jal do_IRQ
84 j ret_from_irq
85
86ll_cpu_ip1:
87 li a0, VR4181_IRQ_SW2
88 move a1, sp
89 jal do_IRQ
90 j ret_from_irq
91
92ll_cpu_ip3:
93 li a0, VR4181_IRQ_INT1
94 move a1, sp
95 jal do_IRQ
96 j ret_from_irq
97
98ll_cpu_ip4:
99 li a0, VR4181_IRQ_INT2
100 move a1, sp
101 jal do_IRQ
102 j ret_from_irq
103
104ll_cpu_ip5:
105 li a0, VR4181_IRQ_INT3
106 move a1, sp
107 jal do_IRQ
108 j ret_from_irq
109
110ll_cpu_ip6:
111 li a0, VR4181_IRQ_INT4
112 move a1, sp
113 jal do_IRQ
114 j ret_from_irq
115
116/*
117 * One of the sys irq has happend.
118 *
119 * In the interest of speed, we first determine in the following order
120 * which 16-irq block have pending interrupts:
121 * sysint1 (16 sources, including cascading intrs from GPIO)
122 * sysint2
123 * gpio (16 intr sources)
124 *
125 * Then we do binary search to find the exact interrupt source.
126 */
127ll_cpu_ip2:
128
129 lui t3,%hi(VR4181_SYSINT1REG)
130 lhu t0,%lo(VR4181_SYSINT1REG)(t3)
131 lhu t2,%lo(VR4181_MSYSINT1REG)(t3)
132 and t0, 0xfffb /* hack - remove RTC Long 1 intr */
133 and t0, t2
134 beqz t0, check_sysint2
135
136 /* check for GPIO interrupts */
137 andi t1, t0, 0x0100
138 bnez t1, check_gpio_int
139
140 /* so we have an interrupt in sysint1 which is not gpio int */
141 li a0, VR4181_SYS_IRQ_BASE - 1
142 j check_16
143
144check_sysint2:
145
146 lhu t0,%lo(VR4181_SYSINT2REG)(t3)
147 lhu t2,%lo(VR4181_MSYSINT2REG)(t3)
148 and t0, 0xfffe /* hack - remove RTC Long 2 intr */
149 and t0, t2
150 li a0, VR4181_SYS_IRQ_BASE + 16 - 1
151 j check_16
152
153check_gpio_int:
154 lui t3,%hi(VR4181_GPINTMSK)
155 lhu t0,%lo(VR4181_GPINTMSK)(t3)
156 lhu t2,%lo(VR4181_GPINTSTAT)(t3)
157 xori t0, 0xffff /* why? reverse logic? */
158 and t0, t2
159 li a0, VR4181_GPIO_IRQ_BASE - 1
160 j check_16
161
162/*
163 * When we reach check_16, we have 16-bit status in t0 and base irq number
164 * in a0.
165 */
166check_16:
167 andi t1, t0, 0xff
168 bnez t1, check_8
169
170 srl t0, 8
171 addi a0, 8
172 j check_8
173
174/*
175 * When we reach check_8, we have 8-bit status in t0 and base irq number
176 * in a0.
177 */
178check_8:
179 andi t1, t0, 0xf
180 bnez t1, check_4
181
182 srl t0, 4
183 addi a0, 4
184 j check_4
185
186/*
187 * When we reach check_4, we have 4-bit status in t0 and base irq number
188 * in a0.
189 */
190check_4:
191 andi t0, t0, 0xf
192 beqz t0, do_spurious
193
194loop:
195 andi t2, t0, 0x1
196 srl t0, 1
197 addi a0, 1
198 beqz t2, loop
199
200found_it:
201 move a1, sp
202 jal do_IRQ
203
204 j ret_from_irq
205
206 END(vr4181_handle_irq)
diff --git a/arch/mips/vr4181/common/irq.c b/arch/mips/vr4181/common/irq.c
deleted file mode 100644
index 2cdf77c5cb3e..000000000000
--- a/arch/mips/vr4181/common/irq.c
+++ /dev/null
@@ -1,239 +0,0 @@
1/*
2 * Copyright (C) 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
5 *
6 * linux/arch/mips/vr4181/common/irq.c
7 * Completely re-written to use the new irq.c
8 *
9 * Credits to Bradley D. LaRonde and Michael Klar for writing the original
10 * irq.c file which was derived from the common irq.c file.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/kernel_stat.h>
19#include <linux/signal.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/slab.h>
23#include <linux/random.h>
24
25#include <asm/irq.h>
26#include <asm/mipsregs.h>
27#include <asm/gdb-stub.h>
28
29#include <asm/vr4181/vr4181.h>
30
31/*
32 * Strategy:
33 *
34 * We essentially have three irq controllers, CPU, system, and gpio.
35 *
36 * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and
37 * CONFIG_IRQ_CPU config option.
38 *
39 * We here provide sys_irq and gpio_irq controller code.
40 */
41
42static int sys_irq_base;
43static int gpio_irq_base;
44
45/* ---------------------- sys irq ------------------------ */
46static void
47sys_irq_enable(unsigned int irq)
48{
49 irq -= sys_irq_base;
50 if (irq < 16) {
51 *VR4181_MSYSINT1REG |= (u16)(1 << irq);
52 } else {
53 irq -= 16;
54 *VR4181_MSYSINT2REG |= (u16)(1 << irq);
55 }
56}
57
58static void
59sys_irq_disable(unsigned int irq)
60{
61 irq -= sys_irq_base;
62 if (irq < 16) {
63 *VR4181_MSYSINT1REG &= ~((u16)(1 << irq));
64 } else {
65 irq -= 16;
66 *VR4181_MSYSINT2REG &= ~((u16)(1 << irq));
67 }
68
69}
70
71static unsigned int
72sys_irq_startup(unsigned int irq)
73{
74 sys_irq_enable(irq);
75 return 0;
76}
77
78#define sys_irq_shutdown sys_irq_disable
79#define sys_irq_ack sys_irq_disable
80
81static void
82sys_irq_end(unsigned int irq)
83{
84 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
85 sys_irq_enable(irq);
86}
87
88static hw_irq_controller sys_irq_controller = {
89 "vr4181_sys_irq",
90 sys_irq_startup,
91 sys_irq_shutdown,
92 sys_irq_enable,
93 sys_irq_disable,
94 sys_irq_ack,
95 sys_irq_end,
96 NULL /* no affinity stuff for UP */
97};
98
99/* ---------------------- gpio irq ------------------------ */
100/* gpio irq lines use reverse logic */
101static void
102gpio_irq_enable(unsigned int irq)
103{
104 irq -= gpio_irq_base;
105 *VR4181_GPINTMSK &= ~((u16)(1 << irq));
106}
107
108static void
109gpio_irq_disable(unsigned int irq)
110{
111 irq -= gpio_irq_base;
112 *VR4181_GPINTMSK |= (u16)(1 << irq);
113}
114
115static unsigned int
116gpio_irq_startup(unsigned int irq)
117{
118 gpio_irq_enable(irq);
119
120 irq -= gpio_irq_base;
121 *VR4181_GPINTEN |= (u16)(1 << irq );
122
123 return 0;
124}
125
126static void
127gpio_irq_shutdown(unsigned int irq)
128{
129 gpio_irq_disable(irq);
130
131 irq -= gpio_irq_base;
132 *VR4181_GPINTEN &= ~((u16)(1 << irq ));
133}
134
135static void
136gpio_irq_ack(unsigned int irq)
137{
138 u16 irqtype;
139 u16 irqshift;
140
141 gpio_irq_disable(irq);
142
143 /* we clear interrupt if it is edge triggered */
144 irq -= gpio_irq_base;
145 if (irq < 8) {
146 irqtype = *VR4181_GPINTTYPL;
147 irqshift = 2 << (irq*2);
148 } else {
149 irqtype = *VR4181_GPINTTYPH;
150 irqshift = 2 << ((irq-8)*2);
151 }
152 if ( ! (irqtype & irqshift) ) {
153 *VR4181_GPINTSTAT = (u16) (1 << irq);
154 }
155}
156
157static void
158gpio_irq_end(unsigned int irq)
159{
160 if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
161 gpio_irq_enable(irq);
162}
163
164static hw_irq_controller gpio_irq_controller = {
165 "vr4181_gpio_irq",
166 gpio_irq_startup,
167 gpio_irq_shutdown,
168 gpio_irq_enable,
169 gpio_irq_disable,
170 gpio_irq_ack,
171 gpio_irq_end,
172 NULL /* no affinity stuff for UP */
173};
174
175/* --------------------- IRQ init stuff ---------------------- */
176
177extern asmlinkage void vr4181_handle_irq(void);
178extern void breakpoint(void);
179extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
180extern void mips_cpu_irq_init(u32 irq_base);
181
182static struct irqaction cascade =
183 { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL };
184static struct irqaction reserved =
185 { no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade", NULL, NULL };
186
187void __init arch_init_irq(void)
188{
189 int i;
190
191 set_except_vector(0, vr4181_handle_irq);
192
193 /* init CPU irqs */
194 mips_cpu_irq_init(VR4181_CPU_IRQ_BASE);
195
196 /* init sys irqs */
197 sys_irq_base = VR4181_SYS_IRQ_BASE;
198 for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) {
199 irq_desc[i].status = IRQ_DISABLED;
200 irq_desc[i].action = NULL;
201 irq_desc[i].depth = 1;
202 irq_desc[i].handler = &sys_irq_controller;
203 }
204
205 /* init gpio irqs */
206 gpio_irq_base = VR4181_GPIO_IRQ_BASE;
207 for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) {
208 irq_desc[i].status = IRQ_DISABLED;
209 irq_desc[i].action = NULL;
210 irq_desc[i].depth = 1;
211 irq_desc[i].handler = &gpio_irq_controller;
212 }
213
214 /* Default all ICU IRQs to off ... */
215 *VR4181_MSYSINT1REG = 0;
216 *VR4181_MSYSINT2REG = 0;
217
218 /* We initialize the level 2 ICU registers to all bits disabled. */
219 *VR4181_MPIUINTREG = 0;
220 *VR4181_MAIUINTREG = 0;
221 *VR4181_MKIUINTREG = 0;
222
223 /* disable all GPIO intrs */
224 *VR4181_GPINTMSK = 0xffff;
225
226 /* vector handler. What these do is register the IRQ as non-sharable */
227 setup_irq(VR4181_IRQ_INT0, &cascade);
228 setup_irq(VR4181_IRQ_GIU, &cascade);
229
230 /*
231 * RTC interrupts are interesting. They have two destinations.
232 * One is at sys irq controller, and the other is at CPU IP3 and IP4.
233 * RTC timer is used as system timer.
234 * We enable them here, but timer routine will register later
235 * with CPU IP3/IP4.
236 */
237 setup_irq(VR4181_IRQ_RTCL1, &reserved);
238 setup_irq(VR4181_IRQ_RTCL2, &reserved);
239}
diff --git a/arch/mips/vr4181/common/serial.c b/arch/mips/vr4181/common/serial.c
deleted file mode 100644
index 3f62c62b107f..000000000000
--- a/arch/mips/vr4181/common/serial.c
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/vr4181/common/serial.c
6 * initialize serial port on vr4181.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15/*
16 * [jsun, 010925]
17 * You need to make sure rs_table has at least one element in
18 * drivers/char/serial.c file. There is no good way to do it right
19 * now. A workaround is to include CONFIG_SERIAL_MANY_PORTS in your
20 * configure file, which would gives you 64 ports and wastes 11K ram.
21 */
22
23#include <linux/types.h>
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/serial.h>
27
28#include <asm/vr4181/vr4181.h>
29
30void __init vr4181_init_serial(void)
31{
32 struct serial_struct s;
33
34 /* turn on UART clock */
35 *VR4181_CMUCLKMSK |= VR4181_CMUCLKMSK_MSKSIU;
36
37 /* clear memory */
38 memset(&s, 0, sizeof(s));
39
40 s.line = 0; /* we set the first one */
41 s.baud_base = 1152000;
42 s.irq = VR4181_IRQ_SIU;
43 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */
44 s.iomem_base = (u8*)VR4181_SIURB;
45 s.iomem_reg_shift = 0;
46 s.io_type = SERIAL_IO_MEM;
47 if (early_serial_setup(&s) != 0) {
48 panic("vr4181_init_serial() failed!");
49 }
50}
51
diff --git a/arch/mips/vr4181/common/time.c b/arch/mips/vr4181/common/time.c
deleted file mode 100644
index 17814076b6f4..000000000000
--- a/arch/mips/vr4181/common/time.c
+++ /dev/null
@@ -1,145 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * rtc and time ops for vr4181. Part of code is drived from
6 * linux-vr, originally written by Bradley D. LaRonde & Michael Klar.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/spinlock.h>
17#include <linux/param.h> /* for HZ */
18#include <linux/time.h>
19#include <linux/interrupt.h>
20
21#include <asm/system.h>
22#include <asm/time.h>
23
24#include <asm/vr4181/vr4181.h>
25
26#define COUNTS_PER_JIFFY ((32768 + HZ/2) / HZ)
27
28/*
29 * RTC ops
30 */
31
32DEFINE_SPINLOCK(rtc_lock);
33
34/* per VR41xx docs, bad data can be read if between 2 counts */
35static inline unsigned short
36read_time_reg(volatile unsigned short *reg)
37{
38 unsigned short value;
39 do {
40 value = *reg;
41 barrier();
42 } while (value != *reg);
43 return value;
44}
45
46static unsigned long
47vr4181_rtc_get_time(void)
48{
49 unsigned short regh, regm, regl;
50
51 // why this crazy order, you ask? to guarantee that neither m
52 // nor l wrap before all 3 read
53 do {
54 regm = read_time_reg(VR4181_ETIMEMREG);
55 barrier();
56 regh = read_time_reg(VR4181_ETIMEHREG);
57 barrier();
58 regl = read_time_reg(VR4181_ETIMELREG);
59 } while (regm != read_time_reg(VR4181_ETIMEMREG));
60 return ((regh << 17) | (regm << 1) | (regl >> 15));
61}
62
63static int
64vr4181_rtc_set_time(unsigned long timeval)
65{
66 unsigned short intreg;
67 unsigned long flags;
68
69 spin_lock_irqsave(&rtc_lock, flags);
70 intreg = *VR4181_RTCINTREG & 0x05;
71 barrier();
72 *VR4181_ETIMELREG = timeval << 15;
73 *VR4181_ETIMEMREG = timeval >> 1;
74 *VR4181_ETIMEHREG = timeval >> 17;
75 barrier();
76 // assume that any ints that just triggered are invalid, since the
77 // time value is written non-atomically in 3 separate regs
78 *VR4181_RTCINTREG = 0x05 ^ intreg;
79 spin_unlock_irqrestore(&rtc_lock, flags);
80
81 return 0;
82}
83
84
85/*
86 * timer interrupt routine (wrapper)
87 *
88 * we need our own interrupt routine because we need to clear
89 * RTC1 interrupt.
90 */
91static void
92vr4181_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
93{
94 /* Clear the interrupt. */
95 *VR4181_RTCINTREG = 0x2;
96
97 /* call the generic one */
98 timer_interrupt(irq, dev_id, regs);
99}
100
101
102/*
103 * vr4181_time_init:
104 *
105 * We pick the following choices:
106 * . we use elapsed timer as the RTC. We set some reasonable init data since
107 * it does not persist across reset
108 * . we use RTC1 as the system timer interrupt source.
109 * . we use CPU counter for fast_gettimeoffset and we calivrate the cpu
110 * frequency. In other words, we use calibrate_div64_gettimeoffset().
111 * . we use our own timer interrupt routine which clears the interrupt
112 * and then calls the generic high-level timer interrupt routine.
113 *
114 */
115
116extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
117
118static void
119vr4181_timer_setup(struct irqaction *irq)
120{
121 /* over-write the handler to be our own one */
122 irq->handler = vr4181_timer_interrupt;
123
124 /* sets up the frequency */
125 *VR4181_RTCL1LREG = COUNTS_PER_JIFFY;
126 *VR4181_RTCL1HREG = 0;
127
128 /* and ack any pending ints */
129 *VR4181_RTCINTREG = 0x2;
130
131 /* setup irqaction */
132 setup_irq(VR4181_IRQ_INT1, irq);
133
134}
135
136void
137vr4181_init_time(void)
138{
139 /* setup hookup functions */
140 rtc_get_time = vr4181_rtc_get_time;
141 rtc_set_time = vr4181_rtc_set_time;
142
143 board_timer_setup = vr4181_timer_setup;
144}
145
diff --git a/arch/mips/vr4181/osprey/Makefile b/arch/mips/vr4181/osprey/Makefile
deleted file mode 100644
index 34be05790883..000000000000
--- a/arch/mips/vr4181/osprey/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for common code of NEC Osprey board
3#
4
5obj-y := setup.o prom.o reset.o
6
7obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/vr4181/osprey/dbg_io.c b/arch/mips/vr4181/osprey/dbg_io.c
deleted file mode 100644
index 5e8a84072d5b..000000000000
--- a/arch/mips/vr4181/osprey/dbg_io.c
+++ /dev/null
@@ -1,136 +0,0 @@
1/*
2 * kgdb io functions for osprey. We use the serial port on debug board.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/* ======================= CONFIG ======================== */
15
16/* [jsun] we use the second serial port for kdb */
17#define BASE 0xb7fffff0
18#define MAX_BAUD 115200
19
20/* distance in bytes between two serial registers */
21#define REG_OFFSET 1
22
23/*
24 * 0 - kgdb does serial init
25 * 1 - kgdb skip serial init
26 */
27static int remoteDebugInitialized = 1;
28
29/*
30 * the default baud rate *if* kgdb does serial init
31 */
32#define BAUD_DEFAULT UART16550_BAUD_38400
33
34/* ======================= END OF CONFIG ======================== */
35
36typedef unsigned char uint8;
37typedef unsigned int uint32;
38
39#define UART16550_BAUD_2400 2400
40#define UART16550_BAUD_4800 4800
41#define UART16550_BAUD_9600 9600
42#define UART16550_BAUD_19200 19200
43#define UART16550_BAUD_38400 38400
44#define UART16550_BAUD_57600 57600
45#define UART16550_BAUD_115200 115200
46
47#define UART16550_PARITY_NONE 0
48#define UART16550_PARITY_ODD 0x08
49#define UART16550_PARITY_EVEN 0x18
50#define UART16550_PARITY_MARK 0x28
51#define UART16550_PARITY_SPACE 0x38
52
53#define UART16550_DATA_5BIT 0x0
54#define UART16550_DATA_6BIT 0x1
55#define UART16550_DATA_7BIT 0x2
56#define UART16550_DATA_8BIT 0x3
57
58#define UART16550_STOP_1BIT 0x0
59#define UART16550_STOP_2BIT 0x4
60
61/* register offset */
62#define OFS_RCV_BUFFER 0
63#define OFS_TRANS_HOLD 0
64#define OFS_SEND_BUFFER 0
65#define OFS_INTR_ENABLE (1*REG_OFFSET)
66#define OFS_INTR_ID (2*REG_OFFSET)
67#define OFS_DATA_FORMAT (3*REG_OFFSET)
68#define OFS_LINE_CONTROL (3*REG_OFFSET)
69#define OFS_MODEM_CONTROL (4*REG_OFFSET)
70#define OFS_RS232_OUTPUT (4*REG_OFFSET)
71#define OFS_LINE_STATUS (5*REG_OFFSET)
72#define OFS_MODEM_STATUS (6*REG_OFFSET)
73#define OFS_RS232_INPUT (6*REG_OFFSET)
74#define OFS_SCRATCH_PAD (7*REG_OFFSET)
75
76#define OFS_DIVISOR_LSB (0*REG_OFFSET)
77#define OFS_DIVISOR_MSB (1*REG_OFFSET)
78
79
80/* memory-mapped read/write of the port */
81#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
82#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
83
84void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
85{
86 /* disable interrupts */
87 UART16550_WRITE(OFS_INTR_ENABLE, 0);
88
89 /* set up buad rate */
90 {
91 uint32 divisor;
92
93 /* set DIAB bit */
94 UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
95
96 /* set divisor */
97 divisor = MAX_BAUD / baud;
98 UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
99 UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
100
101 /* clear DIAB bit */
102 UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
103 }
104
105 /* set data format */
106 UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
107}
108
109
110uint8 getDebugChar(void)
111{
112 if (!remoteDebugInitialized) {
113 remoteDebugInitialized = 1;
114 debugInit(BAUD_DEFAULT,
115 UART16550_DATA_8BIT,
116 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
117 }
118
119 while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
120 return UART16550_READ(OFS_RCV_BUFFER);
121}
122
123
124int putDebugChar(uint8 byte)
125{
126 if (!remoteDebugInitialized) {
127 remoteDebugInitialized = 1;
128 debugInit(BAUD_DEFAULT,
129 UART16550_DATA_8BIT,
130 UART16550_PARITY_NONE, UART16550_STOP_1BIT);
131 }
132
133 while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
134 UART16550_WRITE(OFS_SEND_BUFFER, byte);
135 return 1;
136}
diff --git a/arch/mips/vr4181/osprey/prom.c b/arch/mips/vr4181/osprey/prom.c
deleted file mode 100644
index af0d14561619..000000000000
--- a/arch/mips/vr4181/osprey/prom.c
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/vr4181/osprey/prom.c
6 * prom code for osprey.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/string.h>
17#include <linux/mm.h>
18#include <linux/bootmem.h>
19#include <asm/bootinfo.h>
20#include <asm/addrspace.h>
21
22const char *get_system_type(void)
23{
24 return "NEC_Vr41xx Osprey";
25}
26
27/*
28 * [jsun] right now we assume it is the nec debug monitor, which does
29 * not pass any arguments.
30 */
31void __init prom_init(void)
32{
33 // cmdline is now set in default config
34 // strcpy(arcs_cmdline, "ip=bootp ");
35 // strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 ");
36 // strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
37 // strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 ");
38
39 mips_machgroup = MACH_GROUP_NEC_VR41XX;
40 mips_machtype = MACH_NEC_OSPREY;
41
42 /* 16MB fixed */
43 add_memory_region(0, 16 << 20, BOOT_MEM_RAM);
44}
45
46unsigned long __init prom_free_prom_memory(void)
47{
48 return 0;
49}
diff --git a/arch/mips/vr4181/osprey/reset.c b/arch/mips/vr4181/osprey/reset.c
deleted file mode 100644
index 036ae83d89d6..000000000000
--- a/arch/mips/vr4181/osprey/reset.c
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (C) 1997, 2001 Ralf Baechle
8 * Copyright 2001 MontaVista Software Inc.
9 * Author: jsun@mvista.com or jsun@junsun.net
10 */
11#include <linux/sched.h>
12#include <linux/mm.h>
13#include <asm/io.h>
14#include <asm/cacheflush.h>
15#include <asm/processor.h>
16#include <asm/reboot.h>
17#include <asm/system.h>
18
19void nec_osprey_restart(char *command)
20{
21 set_c0_status(ST0_ERL);
22 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
23 flush_cache_all();
24 write_c0_wired(0);
25 __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
26}
27
28void nec_osprey_halt(void)
29{
30 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
31 while (1)
32 __asm__(".set\tmips3\n\t"
33 "wait\n\t"
34 ".set\tmips0");
35}
36
37void nec_osprey_power_off(void)
38{
39 nec_osprey_halt();
40}
diff --git a/arch/mips/vr4181/osprey/setup.c b/arch/mips/vr4181/osprey/setup.c
deleted file mode 100644
index 2ff7140e7ed7..000000000000
--- a/arch/mips/vr4181/osprey/setup.c
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * linux/arch/mips/vr4181/setup.c
3 *
4 * VR41xx setup routines
5 *
6 * Copyright (C) 1999 Bradley D. LaRonde
7 * Copyright (C) 1999, 2000 Michael Klar
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 * Author: jsun@mvista.com or jsun@junsun.net
11 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 *
17 */
18
19#include <linux/ide.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <asm/reboot.h>
23#include <asm/vr4181/vr4181.h>
24#include <asm/io.h>
25
26
27extern void nec_osprey_restart(char* c);
28extern void nec_osprey_halt(void);
29extern void nec_osprey_power_off(void);
30
31extern void vr4181_init_serial(void);
32extern void vr4181_init_time(void);
33
34static void __init nec_osprey_setup(void)
35{
36 set_io_port_base(VR4181_PORT_BASE);
37 isa_slot_offset = VR4181_ISAMEM_BASE;
38
39 vr4181_init_serial();
40 vr4181_init_time();
41
42 _machine_restart = nec_osprey_restart;
43 _machine_halt = nec_osprey_halt;
44 _machine_power_off = nec_osprey_power_off;
45
46 /* setup resource limit */
47 ioport_resource.end = 0xffffffff;
48 iomem_resource.end = 0xffffffff;
49
50 /* [jsun] hack */
51 /*
52 printk("[jsun] hack to change external ISA control register, %x -> %x\n",
53 (*VR4181_XISACTL),
54 (*VR4181_XISACTL) | 0x2);
55 *VR4181_XISACTL |= 0x2;
56 */
57
58 // *VR4181_GPHIBSTH = 0x2000;
59 // *VR4181_GPMD0REG = 0x00c0;
60 // *VR4181_GPINTEN = 1<<6;
61
62 /* [jsun] I believe this will get the interrupt type right
63 * for the ether port.
64 */
65 *VR4181_GPINTTYPL = 0x3000;
66}
67
68early_initcall(nec_osprey_setup);
diff --git a/arch/mips/vr41xx/casio-e55/setup.c b/arch/mips/vr41xx/casio-e55/setup.c
index aa8605ab76ff..d29201acc4f3 100644
--- a/arch/mips/vr41xx/casio-e55/setup.c
+++ b/arch/mips/vr41xx/casio-e55/setup.c
@@ -23,11 +23,6 @@
23#include <asm/io.h> 23#include <asm/io.h>
24#include <asm/vr41xx/e55.h> 24#include <asm/vr41xx/e55.h>
25 25
26const char *get_system_type(void)
27{
28 return "CASIO CASSIOPEIA E-11/15/55/65";
29}
30
31static int __init casio_e55_setup(void) 26static int __init casio_e55_setup(void)
32{ 27{
33 set_io_port_base(IO_PORT_BASE); 28 set_io_port_base(IO_PORT_BASE);
diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile
index 92c11e9bbb3f..9096302a7ecc 100644
--- a/arch/mips/vr41xx/common/Makefile
+++ b/arch/mips/vr41xx/common/Makefile
@@ -2,7 +2,7 @@
2# Makefile for common code of the NEC VR4100 series. 2# Makefile for common code of the NEC VR4100 series.
3# 3#
4 4
5obj-y += bcu.o cmu.o giu.o icu.o init.o int-handler.o pmu.o 5obj-y += bcu.o cmu.o icu.o init.o int-handler.o irq.o pmu.o type.o
6obj-$(CONFIG_VRC4173) += vrc4173.o 6obj-$(CONFIG_VRC4173) += vrc4173.o
7 7
8EXTRA_AFLAGS := $(CFLAGS) 8EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/vr41xx/common/giu.c b/arch/mips/vr41xx/common/giu.c
deleted file mode 100644
index 9c6b21a79e8f..000000000000
--- a/arch/mips/vr41xx/common/giu.c
+++ /dev/null
@@ -1,455 +0,0 @@
1/*
2 * giu.c, General-purpose I/O Unit Interrupt routines for NEC VR4100 series.
3 *
4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6 * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23/*
24 * Changes:
25 * MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
26 * - New creation, NEC VR4111, VR4121, VR4122 and VR4131 are supported.
27 *
28 * Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
29 * - Added support for NEC VR4133.
30 * - Removed board_irq_init.
31 */
32#include <linux/errno.h>
33#include <linux/init.h>
34#include <linux/irq.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/smp.h>
38#include <linux/types.h>
39
40#include <asm/cpu.h>
41#include <asm/io.h>
42#include <asm/vr41xx/vr41xx.h>
43
44#define GIUIOSELL_TYPE1 KSEG1ADDR(0x0b000100)
45#define GIUIOSELL_TYPE2 KSEG1ADDR(0x0f000140)
46
47#define GIUIOSELL 0x00
48#define GIUIOSELH 0x02
49#define GIUINTSTATL 0x08
50#define GIUINTSTATH 0x0a
51#define GIUINTENL 0x0c
52#define GIUINTENH 0x0e
53#define GIUINTTYPL 0x10
54#define GIUINTTYPH 0x12
55#define GIUINTALSELL 0x14
56#define GIUINTALSELH 0x16
57#define GIUINTHTSELL 0x18
58#define GIUINTHTSELH 0x1a
59#define GIUFEDGEINHL 0x20
60#define GIUFEDGEINHH 0x22
61#define GIUREDGEINHL 0x24
62#define GIUREDGEINHH 0x26
63
64static uint32_t giu_base;
65
66static struct irqaction giu_cascade = {
67 .handler = no_action,
68 .mask = CPU_MASK_NONE,
69 .name = "cascade",
70};
71
72#define read_giuint(offset) readw(giu_base + (offset))
73#define write_giuint(val, offset) writew((val), giu_base + (offset))
74
75#define GIUINT_HIGH_OFFSET 16
76
77static inline uint16_t set_giuint(uint8_t offset, uint16_t set)
78{
79 uint16_t res;
80
81 res = read_giuint(offset);
82 res |= set;
83 write_giuint(res, offset);
84
85 return res;
86}
87
88static inline uint16_t clear_giuint(uint8_t offset, uint16_t clear)
89{
90 uint16_t res;
91
92 res = read_giuint(offset);
93 res &= ~clear;
94 write_giuint(res, offset);
95
96 return res;
97}
98
99static unsigned int startup_giuint_low_irq(unsigned int irq)
100{
101 unsigned int pin;
102
103 pin = GIU_IRQ_TO_PIN(irq);
104 write_giuint((uint16_t)1 << pin, GIUINTSTATL);
105 set_giuint(GIUINTENL, (uint16_t)1 << pin);
106
107 return 0;
108}
109
110static void shutdown_giuint_low_irq(unsigned int irq)
111{
112 clear_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
113}
114
115static void enable_giuint_low_irq(unsigned int irq)
116{
117 set_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
118}
119
120#define disable_giuint_low_irq shutdown_giuint_low_irq
121
122static void ack_giuint_low_irq(unsigned int irq)
123{
124 unsigned int pin;
125
126 pin = GIU_IRQ_TO_PIN(irq);
127 clear_giuint(GIUINTENL, (uint16_t)1 << pin);
128 write_giuint((uint16_t)1 << pin, GIUINTSTATL);
129}
130
131static void end_giuint_low_irq(unsigned int irq)
132{
133 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
134 set_giuint(GIUINTENL, (uint16_t)1 << GIU_IRQ_TO_PIN(irq));
135}
136
137static struct hw_interrupt_type giuint_low_irq_type = {
138 .typename = "GIUINTL",
139 .startup = startup_giuint_low_irq,
140 .shutdown = shutdown_giuint_low_irq,
141 .enable = enable_giuint_low_irq,
142 .disable = disable_giuint_low_irq,
143 .ack = ack_giuint_low_irq,
144 .end = end_giuint_low_irq,
145};
146
147static unsigned int startup_giuint_high_irq(unsigned int irq)
148{
149 unsigned int pin;
150
151 pin = GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET);
152 write_giuint((uint16_t)1 << pin, GIUINTSTATH);
153 set_giuint(GIUINTENH, (uint16_t)1 << pin);
154
155 return 0;
156}
157
158static void shutdown_giuint_high_irq(unsigned int irq)
159{
160 clear_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
161}
162
163static void enable_giuint_high_irq(unsigned int irq)
164{
165 set_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
166}
167
168#define disable_giuint_high_irq shutdown_giuint_high_irq
169
170static void ack_giuint_high_irq(unsigned int irq)
171{
172 unsigned int pin;
173
174 pin = GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET);
175 clear_giuint(GIUINTENH, (uint16_t)1 << pin);
176 write_giuint((uint16_t)1 << pin, GIUINTSTATH);
177}
178
179static void end_giuint_high_irq(unsigned int irq)
180{
181 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
182 set_giuint(GIUINTENH, (uint16_t)1 << GIU_IRQ_TO_PIN(irq - GIUINT_HIGH_OFFSET));
183}
184
185static struct hw_interrupt_type giuint_high_irq_type = {
186 .typename = "GIUINTH",
187 .startup = startup_giuint_high_irq,
188 .shutdown = shutdown_giuint_high_irq,
189 .enable = enable_giuint_high_irq,
190 .disable = disable_giuint_high_irq,
191 .ack = ack_giuint_high_irq,
192 .end = end_giuint_high_irq,
193};
194
195void __init init_vr41xx_giuint_irq(void)
196{
197 int i;
198
199 for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
200 if (i < (GIU_IRQ_BASE + GIUINT_HIGH_OFFSET))
201 irq_desc[i].handler = &giuint_low_irq_type;
202 else
203 irq_desc[i].handler = &giuint_high_irq_type;
204 }
205
206 setup_irq(GIUINT_CASCADE_IRQ, &giu_cascade);
207}
208
209void vr41xx_set_irq_trigger(int pin, int trigger, int hold)
210{
211 uint16_t mask;
212
213 if (pin < GIUINT_HIGH_OFFSET) {
214 mask = (uint16_t)1 << pin;
215 if (trigger != TRIGGER_LEVEL) {
216 set_giuint(GIUINTTYPL, mask);
217 if (hold == SIGNAL_HOLD)
218 set_giuint(GIUINTHTSELL, mask);
219 else
220 clear_giuint(GIUINTHTSELL, mask);
221 if (current_cpu_data.cputype == CPU_VR4133) {
222 switch (trigger) {
223 case TRIGGER_EDGE_FALLING:
224 set_giuint(GIUFEDGEINHL, mask);
225 clear_giuint(GIUREDGEINHL, mask);
226 break;
227 case TRIGGER_EDGE_RISING:
228 clear_giuint(GIUFEDGEINHL, mask);
229 set_giuint(GIUREDGEINHL, mask);
230 break;
231 default:
232 set_giuint(GIUFEDGEINHL, mask);
233 set_giuint(GIUREDGEINHL, mask);
234 break;
235 }
236 }
237 } else {
238 clear_giuint(GIUINTTYPL, mask);
239 clear_giuint(GIUINTHTSELL, mask);
240 }
241 write_giuint(mask, GIUINTSTATL);
242 } else {
243 mask = (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET);
244 if (trigger != TRIGGER_LEVEL) {
245 set_giuint(GIUINTTYPH, mask);
246 if (hold == SIGNAL_HOLD)
247 set_giuint(GIUINTHTSELH, mask);
248 else
249 clear_giuint(GIUINTHTSELH, mask);
250 if (current_cpu_data.cputype == CPU_VR4133) {
251 switch (trigger) {
252 case TRIGGER_EDGE_FALLING:
253 set_giuint(GIUFEDGEINHH, mask);
254 clear_giuint(GIUREDGEINHH, mask);
255 break;
256 case TRIGGER_EDGE_RISING:
257 clear_giuint(GIUFEDGEINHH, mask);
258 set_giuint(GIUREDGEINHH, mask);
259 break;
260 default:
261 set_giuint(GIUFEDGEINHH, mask);
262 set_giuint(GIUREDGEINHH, mask);
263 break;
264 }
265 }
266 } else {
267 clear_giuint(GIUINTTYPH, mask);
268 clear_giuint(GIUINTHTSELH, mask);
269 }
270 write_giuint(mask, GIUINTSTATH);
271 }
272}
273
274EXPORT_SYMBOL(vr41xx_set_irq_trigger);
275
276void vr41xx_set_irq_level(int pin, int level)
277{
278 uint16_t mask;
279
280 if (pin < GIUINT_HIGH_OFFSET) {
281 mask = (uint16_t)1 << pin;
282 if (level == LEVEL_HIGH)
283 set_giuint(GIUINTALSELL, mask);
284 else
285 clear_giuint(GIUINTALSELL, mask);
286 write_giuint(mask, GIUINTSTATL);
287 } else {
288 mask = (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET);
289 if (level == LEVEL_HIGH)
290 set_giuint(GIUINTALSELH, mask);
291 else
292 clear_giuint(GIUINTALSELH, mask);
293 write_giuint(mask, GIUINTSTATH);
294 }
295}
296
297EXPORT_SYMBOL(vr41xx_set_irq_level);
298
299#define GIUINT_NR_IRQS 32
300
301enum {
302 GIUINT_NO_CASCADE,
303 GIUINT_CASCADE
304};
305
306struct vr41xx_giuint_cascade {
307 unsigned int flag;
308 int (*get_irq_number)(int irq);
309};
310
311static struct vr41xx_giuint_cascade giuint_cascade[GIUINT_NR_IRQS];
312
313static int no_irq_number(int irq)
314{
315 return -EINVAL;
316}
317
318int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq))
319{
320 unsigned int pin;
321 int retval;
322
323 if (irq < GIU_IRQ(0) || irq > GIU_IRQ(31))
324 return -EINVAL;
325
326 if(!get_irq_number)
327 return -EINVAL;
328
329 pin = GIU_IRQ_TO_PIN(irq);
330 giuint_cascade[pin].flag = GIUINT_CASCADE;
331 giuint_cascade[pin].get_irq_number = get_irq_number;
332
333 retval = setup_irq(irq, &giu_cascade);
334 if (retval != 0) {
335 giuint_cascade[pin].flag = GIUINT_NO_CASCADE;
336 giuint_cascade[pin].get_irq_number = no_irq_number;
337 }
338
339 return retval;
340}
341
342EXPORT_SYMBOL(vr41xx_cascade_irq);
343
344static inline int get_irq_pin_number(void)
345{
346 uint16_t pendl, pendh, maskl, maskh;
347 int i;
348
349 pendl = read_giuint(GIUINTSTATL);
350 pendh = read_giuint(GIUINTSTATH);
351 maskl = read_giuint(GIUINTENL);
352 maskh = read_giuint(GIUINTENH);
353
354 maskl &= pendl;
355 maskh &= pendh;
356
357 if (maskl) {
358 for (i = 0; i < 16; i++) {
359 if (maskl & ((uint16_t)1 << i))
360 return i;
361 }
362 } else if (maskh) {
363 for (i = 0; i < 16; i++) {
364 if (maskh & ((uint16_t)1 << i))
365 return i + GIUINT_HIGH_OFFSET;
366 }
367 }
368
369 printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
370 maskl, pendl, maskh, pendh);
371
372 atomic_inc(&irq_err_count);
373
374 return -1;
375}
376
377static inline void ack_giuint_irq(int pin)
378{
379 if (pin < GIUINT_HIGH_OFFSET) {
380 clear_giuint(GIUINTENL, (uint16_t)1 << pin);
381 write_giuint((uint16_t)1 << pin, GIUINTSTATL);
382 } else {
383 pin -= GIUINT_HIGH_OFFSET;
384 clear_giuint(GIUINTENH, (uint16_t)1 << pin);
385 write_giuint((uint16_t)1 << pin, GIUINTSTATH);
386 }
387}
388
389static inline void end_giuint_irq(int pin)
390{
391 if (pin < GIUINT_HIGH_OFFSET)
392 set_giuint(GIUINTENL, (uint16_t)1 << pin);
393 else
394 set_giuint(GIUINTENH, (uint16_t)1 << (pin - GIUINT_HIGH_OFFSET));
395}
396
397void giuint_irq_dispatch(struct pt_regs *regs)
398{
399 struct vr41xx_giuint_cascade *cascade;
400 unsigned int giuint_irq;
401 int pin;
402
403 pin = get_irq_pin_number();
404 if (pin < 0)
405 return;
406
407 disable_irq(GIUINT_CASCADE_IRQ);
408
409 cascade = &giuint_cascade[pin];
410 giuint_irq = GIU_IRQ(pin);
411 if (cascade->flag == GIUINT_CASCADE) {
412 int irq = cascade->get_irq_number(giuint_irq);
413 ack_giuint_irq(pin);
414 if (irq >= 0)
415 do_IRQ(irq, regs);
416 end_giuint_irq(pin);
417 } else {
418 do_IRQ(giuint_irq, regs);
419 }
420
421 enable_irq(GIUINT_CASCADE_IRQ);
422}
423
424static int __init vr41xx_giu_init(void)
425{
426 int i;
427
428 switch (current_cpu_data.cputype) {
429 case CPU_VR4111:
430 case CPU_VR4121:
431 giu_base = GIUIOSELL_TYPE1;
432 break;
433 case CPU_VR4122:
434 case CPU_VR4131:
435 case CPU_VR4133:
436 giu_base = GIUIOSELL_TYPE2;
437 break;
438 default:
439 printk(KERN_ERR "GIU: Unexpected CPU of NEC VR4100 series\n");
440 return -EINVAL;
441 }
442
443 for (i = 0; i < GIUINT_NR_IRQS; i++) {
444 if (i < GIUINT_HIGH_OFFSET)
445 clear_giuint(GIUINTENL, (uint16_t)1 << i);
446 else
447 clear_giuint(GIUINTENH, (uint16_t)1 << (i - GIUINT_HIGH_OFFSET));
448 giuint_cascade[i].flag = GIUINT_NO_CASCADE;
449 giuint_cascade[i].get_irq_number = no_irq_number;
450 }
451
452 return 0;
453}
454
455early_initcall(vr41xx_giu_init);
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index c842661144cb..0b73c5ab3c0c 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -3,8 +3,7 @@
3 * 3 *
4 * Copyright (C) 2001-2002 MontaVista Software Inc. 4 * Copyright (C) 2001-2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com> 5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6 * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 6 * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8 * 7 *
9 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -31,7 +30,7 @@
31 */ 30 */
32#include <linux/errno.h> 31#include <linux/errno.h>
33#include <linux/init.h> 32#include <linux/init.h>
34#include <linux/interrupt.h> 33#include <linux/ioport.h>
35#include <linux/irq.h> 34#include <linux/irq.h>
36#include <linux/module.h> 35#include <linux/module.h>
37#include <linux/smp.h> 36#include <linux/smp.h>
@@ -39,34 +38,24 @@
39 38
40#include <asm/cpu.h> 39#include <asm/cpu.h>
41#include <asm/io.h> 40#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/irq_cpu.h>
44#include <asm/vr41xx/vr41xx.h> 41#include <asm/vr41xx/vr41xx.h>
45 42
46extern asmlinkage void vr41xx_handle_interrupt(void); 43static void __iomem *icu1_base;
47 44static void __iomem *icu2_base;
48extern void init_vr41xx_giuint_irq(void);
49extern void giuint_irq_dispatch(struct pt_regs *regs);
50
51static uint32_t icu1_base;
52static uint32_t icu2_base;
53
54static struct irqaction icu_cascade = {
55 .handler = no_action,
56 .mask = CPU_MASK_NONE,
57 .name = "cascade",
58};
59 45
60static unsigned char sysint1_assign[16] = { 46static unsigned char sysint1_assign[16] = {
61 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 47 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
62static unsigned char sysint2_assign[16] = { 48static unsigned char sysint2_assign[16] = {
63 2, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; 49 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
64 50
65#define SYSINT1REG_TYPE1 KSEG1ADDR(0x0b000080) 51#define ICU1_TYPE1_BASE 0x0b000080UL
66#define SYSINT2REG_TYPE1 KSEG1ADDR(0x0b000200) 52#define ICU2_TYPE1_BASE 0x0b000200UL
67 53
68#define SYSINT1REG_TYPE2 KSEG1ADDR(0x0f000080) 54#define ICU1_TYPE2_BASE 0x0f000080UL
69#define SYSINT2REG_TYPE2 KSEG1ADDR(0x0f0000a0) 55#define ICU2_TYPE2_BASE 0x0f0000a0UL
56
57#define ICU1_SIZE 0x20
58#define ICU2_SIZE 0x1c
70 59
71#define SYSINT1REG 0x00 60#define SYSINT1REG 0x00
72#define PIUINTREG 0x02 61#define PIUINTREG 0x02
@@ -106,61 +95,61 @@ static unsigned char sysint2_assign[16] = {
106#define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */ 95#define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */
107#define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */ 96#define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */
108 97
109#define read_icu1(offset) readw(icu1_base + (offset)) 98#define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */
110#define write_icu1(val, offset) writew((val), icu1_base + (offset)) 99
100#define icu1_read(offset) readw(icu1_base + (offset))
101#define icu1_write(offset, value) writew((value), icu1_base + (offset))
111 102
112#define read_icu2(offset) readw(icu2_base + (offset)) 103#define icu2_read(offset) readw(icu2_base + (offset))
113#define write_icu2(val, offset) writew((val), icu2_base + (offset)) 104#define icu2_write(offset, value) writew((value), icu2_base + (offset))
114 105
115#define INTASSIGN_MAX 4 106#define INTASSIGN_MAX 4
116#define INTASSIGN_MASK 0x0007 107#define INTASSIGN_MASK 0x0007
117 108
118static inline uint16_t set_icu1(uint8_t offset, uint16_t set) 109static inline uint16_t icu1_set(uint8_t offset, uint16_t set)
119{ 110{
120 uint16_t res; 111 uint16_t data;
121 112
122 res = read_icu1(offset); 113 data = icu1_read(offset);
123 res |= set; 114 data |= set;
124 write_icu1(res, offset); 115 icu1_write(offset, data);
125 116
126 return res; 117 return data;
127} 118}
128 119
129static inline uint16_t clear_icu1(uint8_t offset, uint16_t clear) 120static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear)
130{ 121{
131 uint16_t res; 122 uint16_t data;
132 123
133 res = read_icu1(offset); 124 data = icu1_read(offset);
134 res &= ~clear; 125 data &= ~clear;
135 write_icu1(res, offset); 126 icu1_write(offset, data);
136 127
137 return res; 128 return data;
138} 129}
139 130
140static inline uint16_t set_icu2(uint8_t offset, uint16_t set) 131static inline uint16_t icu2_set(uint8_t offset, uint16_t set)
141{ 132{
142 uint16_t res; 133 uint16_t data;
143 134
144 res = read_icu2(offset); 135 data = icu2_read(offset);
145 res |= set; 136 data |= set;
146 write_icu2(res, offset); 137 icu2_write(offset, data);
147 138
148 return res; 139 return data;
149} 140}
150 141
151static inline uint16_t clear_icu2(uint8_t offset, uint16_t clear) 142static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear)
152{ 143{
153 uint16_t res; 144 uint16_t data;
154 145
155 res = read_icu2(offset); 146 data = icu2_read(offset);
156 res &= ~clear; 147 data &= ~clear;
157 write_icu2(res, offset); 148 icu2_write(offset, data);
158 149
159 return res; 150 return data;
160} 151}
161 152
162/*=======================================================================*/
163
164void vr41xx_enable_piuint(uint16_t mask) 153void vr41xx_enable_piuint(uint16_t mask)
165{ 154{
166 irq_desc_t *desc = irq_desc + PIU_IRQ; 155 irq_desc_t *desc = irq_desc + PIU_IRQ;
@@ -169,7 +158,7 @@ void vr41xx_enable_piuint(uint16_t mask)
169 if (current_cpu_data.cputype == CPU_VR4111 || 158 if (current_cpu_data.cputype == CPU_VR4111 ||
170 current_cpu_data.cputype == CPU_VR4121) { 159 current_cpu_data.cputype == CPU_VR4121) {
171 spin_lock_irqsave(&desc->lock, flags); 160 spin_lock_irqsave(&desc->lock, flags);
172 set_icu1(MPIUINTREG, mask); 161 icu1_set(MPIUINTREG, mask);
173 spin_unlock_irqrestore(&desc->lock, flags); 162 spin_unlock_irqrestore(&desc->lock, flags);
174 } 163 }
175} 164}
@@ -184,7 +173,7 @@ void vr41xx_disable_piuint(uint16_t mask)
184 if (current_cpu_data.cputype == CPU_VR4111 || 173 if (current_cpu_data.cputype == CPU_VR4111 ||
185 current_cpu_data.cputype == CPU_VR4121) { 174 current_cpu_data.cputype == CPU_VR4121) {
186 spin_lock_irqsave(&desc->lock, flags); 175 spin_lock_irqsave(&desc->lock, flags);
187 clear_icu1(MPIUINTREG, mask); 176 icu1_clear(MPIUINTREG, mask);
188 spin_unlock_irqrestore(&desc->lock, flags); 177 spin_unlock_irqrestore(&desc->lock, flags);
189 } 178 }
190} 179}
@@ -199,7 +188,7 @@ void vr41xx_enable_aiuint(uint16_t mask)
199 if (current_cpu_data.cputype == CPU_VR4111 || 188 if (current_cpu_data.cputype == CPU_VR4111 ||
200 current_cpu_data.cputype == CPU_VR4121) { 189 current_cpu_data.cputype == CPU_VR4121) {
201 spin_lock_irqsave(&desc->lock, flags); 190 spin_lock_irqsave(&desc->lock, flags);
202 set_icu1(MAIUINTREG, mask); 191 icu1_set(MAIUINTREG, mask);
203 spin_unlock_irqrestore(&desc->lock, flags); 192 spin_unlock_irqrestore(&desc->lock, flags);
204 } 193 }
205} 194}
@@ -214,7 +203,7 @@ void vr41xx_disable_aiuint(uint16_t mask)
214 if (current_cpu_data.cputype == CPU_VR4111 || 203 if (current_cpu_data.cputype == CPU_VR4111 ||
215 current_cpu_data.cputype == CPU_VR4121) { 204 current_cpu_data.cputype == CPU_VR4121) {
216 spin_lock_irqsave(&desc->lock, flags); 205 spin_lock_irqsave(&desc->lock, flags);
217 clear_icu1(MAIUINTREG, mask); 206 icu1_clear(MAIUINTREG, mask);
218 spin_unlock_irqrestore(&desc->lock, flags); 207 spin_unlock_irqrestore(&desc->lock, flags);
219 } 208 }
220} 209}
@@ -229,7 +218,7 @@ void vr41xx_enable_kiuint(uint16_t mask)
229 if (current_cpu_data.cputype == CPU_VR4111 || 218 if (current_cpu_data.cputype == CPU_VR4111 ||
230 current_cpu_data.cputype == CPU_VR4121) { 219 current_cpu_data.cputype == CPU_VR4121) {
231 spin_lock_irqsave(&desc->lock, flags); 220 spin_lock_irqsave(&desc->lock, flags);
232 set_icu1(MKIUINTREG, mask); 221 icu1_set(MKIUINTREG, mask);
233 spin_unlock_irqrestore(&desc->lock, flags); 222 spin_unlock_irqrestore(&desc->lock, flags);
234 } 223 }
235} 224}
@@ -244,7 +233,7 @@ void vr41xx_disable_kiuint(uint16_t mask)
244 if (current_cpu_data.cputype == CPU_VR4111 || 233 if (current_cpu_data.cputype == CPU_VR4111 ||
245 current_cpu_data.cputype == CPU_VR4121) { 234 current_cpu_data.cputype == CPU_VR4121) {
246 spin_lock_irqsave(&desc->lock, flags); 235 spin_lock_irqsave(&desc->lock, flags);
247 clear_icu1(MKIUINTREG, mask); 236 icu1_clear(MKIUINTREG, mask);
248 spin_unlock_irqrestore(&desc->lock, flags); 237 spin_unlock_irqrestore(&desc->lock, flags);
249 } 238 }
250} 239}
@@ -257,7 +246,7 @@ void vr41xx_enable_dsiuint(uint16_t mask)
257 unsigned long flags; 246 unsigned long flags;
258 247
259 spin_lock_irqsave(&desc->lock, flags); 248 spin_lock_irqsave(&desc->lock, flags);
260 set_icu1(MDSIUINTREG, mask); 249 icu1_set(MDSIUINTREG, mask);
261 spin_unlock_irqrestore(&desc->lock, flags); 250 spin_unlock_irqrestore(&desc->lock, flags);
262} 251}
263 252
@@ -269,7 +258,7 @@ void vr41xx_disable_dsiuint(uint16_t mask)
269 unsigned long flags; 258 unsigned long flags;
270 259
271 spin_lock_irqsave(&desc->lock, flags); 260 spin_lock_irqsave(&desc->lock, flags);
272 clear_icu1(MDSIUINTREG, mask); 261 icu1_clear(MDSIUINTREG, mask);
273 spin_unlock_irqrestore(&desc->lock, flags); 262 spin_unlock_irqrestore(&desc->lock, flags);
274} 263}
275 264
@@ -281,7 +270,7 @@ void vr41xx_enable_firint(uint16_t mask)
281 unsigned long flags; 270 unsigned long flags;
282 271
283 spin_lock_irqsave(&desc->lock, flags); 272 spin_lock_irqsave(&desc->lock, flags);
284 set_icu2(MFIRINTREG, mask); 273 icu2_set(MFIRINTREG, mask);
285 spin_unlock_irqrestore(&desc->lock, flags); 274 spin_unlock_irqrestore(&desc->lock, flags);
286} 275}
287 276
@@ -293,7 +282,7 @@ void vr41xx_disable_firint(uint16_t mask)
293 unsigned long flags; 282 unsigned long flags;
294 283
295 spin_lock_irqsave(&desc->lock, flags); 284 spin_lock_irqsave(&desc->lock, flags);
296 clear_icu2(MFIRINTREG, mask); 285 icu2_clear(MFIRINTREG, mask);
297 spin_unlock_irqrestore(&desc->lock, flags); 286 spin_unlock_irqrestore(&desc->lock, flags);
298} 287}
299 288
@@ -308,7 +297,7 @@ void vr41xx_enable_pciint(void)
308 current_cpu_data.cputype == CPU_VR4131 || 297 current_cpu_data.cputype == CPU_VR4131 ||
309 current_cpu_data.cputype == CPU_VR4133) { 298 current_cpu_data.cputype == CPU_VR4133) {
310 spin_lock_irqsave(&desc->lock, flags); 299 spin_lock_irqsave(&desc->lock, flags);
311 write_icu2(PCIINT0, MPCIINTREG); 300 icu2_write(MPCIINTREG, PCIINT0);
312 spin_unlock_irqrestore(&desc->lock, flags); 301 spin_unlock_irqrestore(&desc->lock, flags);
313 } 302 }
314} 303}
@@ -324,7 +313,7 @@ void vr41xx_disable_pciint(void)
324 current_cpu_data.cputype == CPU_VR4131 || 313 current_cpu_data.cputype == CPU_VR4131 ||
325 current_cpu_data.cputype == CPU_VR4133) { 314 current_cpu_data.cputype == CPU_VR4133) {
326 spin_lock_irqsave(&desc->lock, flags); 315 spin_lock_irqsave(&desc->lock, flags);
327 write_icu2(0, MPCIINTREG); 316 icu2_write(MPCIINTREG, 0);
328 spin_unlock_irqrestore(&desc->lock, flags); 317 spin_unlock_irqrestore(&desc->lock, flags);
329 } 318 }
330} 319}
@@ -340,7 +329,7 @@ void vr41xx_enable_scuint(void)
340 current_cpu_data.cputype == CPU_VR4131 || 329 current_cpu_data.cputype == CPU_VR4131 ||
341 current_cpu_data.cputype == CPU_VR4133) { 330 current_cpu_data.cputype == CPU_VR4133) {
342 spin_lock_irqsave(&desc->lock, flags); 331 spin_lock_irqsave(&desc->lock, flags);
343 write_icu2(SCUINT0, MSCUINTREG); 332 icu2_write(MSCUINTREG, SCUINT0);
344 spin_unlock_irqrestore(&desc->lock, flags); 333 spin_unlock_irqrestore(&desc->lock, flags);
345 } 334 }
346} 335}
@@ -356,7 +345,7 @@ void vr41xx_disable_scuint(void)
356 current_cpu_data.cputype == CPU_VR4131 || 345 current_cpu_data.cputype == CPU_VR4131 ||
357 current_cpu_data.cputype == CPU_VR4133) { 346 current_cpu_data.cputype == CPU_VR4133) {
358 spin_lock_irqsave(&desc->lock, flags); 347 spin_lock_irqsave(&desc->lock, flags);
359 write_icu2(0, MSCUINTREG); 348 icu2_write(MSCUINTREG, 0);
360 spin_unlock_irqrestore(&desc->lock, flags); 349 spin_unlock_irqrestore(&desc->lock, flags);
361 } 350 }
362} 351}
@@ -372,7 +361,7 @@ void vr41xx_enable_csiint(uint16_t mask)
372 current_cpu_data.cputype == CPU_VR4131 || 361 current_cpu_data.cputype == CPU_VR4131 ||
373 current_cpu_data.cputype == CPU_VR4133) { 362 current_cpu_data.cputype == CPU_VR4133) {
374 spin_lock_irqsave(&desc->lock, flags); 363 spin_lock_irqsave(&desc->lock, flags);
375 set_icu2(MCSIINTREG, mask); 364 icu2_set(MCSIINTREG, mask);
376 spin_unlock_irqrestore(&desc->lock, flags); 365 spin_unlock_irqrestore(&desc->lock, flags);
377 } 366 }
378} 367}
@@ -388,7 +377,7 @@ void vr41xx_disable_csiint(uint16_t mask)
388 current_cpu_data.cputype == CPU_VR4131 || 377 current_cpu_data.cputype == CPU_VR4131 ||
389 current_cpu_data.cputype == CPU_VR4133) { 378 current_cpu_data.cputype == CPU_VR4133) {
390 spin_lock_irqsave(&desc->lock, flags); 379 spin_lock_irqsave(&desc->lock, flags);
391 clear_icu2(MCSIINTREG, mask); 380 icu2_clear(MCSIINTREG, mask);
392 spin_unlock_irqrestore(&desc->lock, flags); 381 spin_unlock_irqrestore(&desc->lock, flags);
393 } 382 }
394} 383}
@@ -404,7 +393,7 @@ void vr41xx_enable_bcuint(void)
404 current_cpu_data.cputype == CPU_VR4131 || 393 current_cpu_data.cputype == CPU_VR4131 ||
405 current_cpu_data.cputype == CPU_VR4133) { 394 current_cpu_data.cputype == CPU_VR4133) {
406 spin_lock_irqsave(&desc->lock, flags); 395 spin_lock_irqsave(&desc->lock, flags);
407 write_icu2(BCUINTR, MBCUINTREG); 396 icu2_write(MBCUINTREG, BCUINTR);
408 spin_unlock_irqrestore(&desc->lock, flags); 397 spin_unlock_irqrestore(&desc->lock, flags);
409 } 398 }
410} 399}
@@ -420,30 +409,28 @@ void vr41xx_disable_bcuint(void)
420 current_cpu_data.cputype == CPU_VR4131 || 409 current_cpu_data.cputype == CPU_VR4131 ||
421 current_cpu_data.cputype == CPU_VR4133) { 410 current_cpu_data.cputype == CPU_VR4133) {
422 spin_lock_irqsave(&desc->lock, flags); 411 spin_lock_irqsave(&desc->lock, flags);
423 write_icu2(0, MBCUINTREG); 412 icu2_write(MBCUINTREG, 0);
424 spin_unlock_irqrestore(&desc->lock, flags); 413 spin_unlock_irqrestore(&desc->lock, flags);
425 } 414 }
426} 415}
427 416
428EXPORT_SYMBOL(vr41xx_disable_bcuint); 417EXPORT_SYMBOL(vr41xx_disable_bcuint);
429 418
430/*=======================================================================*/
431
432static unsigned int startup_sysint1_irq(unsigned int irq) 419static unsigned int startup_sysint1_irq(unsigned int irq)
433{ 420{
434 set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); 421 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
435 422
436 return 0; /* never anything pending */ 423 return 0; /* never anything pending */
437} 424}
438 425
439static void shutdown_sysint1_irq(unsigned int irq) 426static void shutdown_sysint1_irq(unsigned int irq)
440{ 427{
441 clear_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); 428 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
442} 429}
443 430
444static void enable_sysint1_irq(unsigned int irq) 431static void enable_sysint1_irq(unsigned int irq)
445{ 432{
446 set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); 433 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
447} 434}
448 435
449#define disable_sysint1_irq shutdown_sysint1_irq 436#define disable_sysint1_irq shutdown_sysint1_irq
@@ -452,7 +439,7 @@ static void enable_sysint1_irq(unsigned int irq)
452static void end_sysint1_irq(unsigned int irq) 439static void end_sysint1_irq(unsigned int irq)
453{ 440{
454 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 441 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
455 set_icu1(MSYSINT1REG, (uint16_t)1 << SYSINT1_IRQ_TO_PIN(irq)); 442 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
456} 443}
457 444
458static struct hw_interrupt_type sysint1_irq_type = { 445static struct hw_interrupt_type sysint1_irq_type = {
@@ -465,23 +452,21 @@ static struct hw_interrupt_type sysint1_irq_type = {
465 .end = end_sysint1_irq, 452 .end = end_sysint1_irq,
466}; 453};
467 454
468/*=======================================================================*/
469
470static unsigned int startup_sysint2_irq(unsigned int irq) 455static unsigned int startup_sysint2_irq(unsigned int irq)
471{ 456{
472 set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); 457 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
473 458
474 return 0; /* never anything pending */ 459 return 0; /* never anything pending */
475} 460}
476 461
477static void shutdown_sysint2_irq(unsigned int irq) 462static void shutdown_sysint2_irq(unsigned int irq)
478{ 463{
479 clear_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); 464 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
480} 465}
481 466
482static void enable_sysint2_irq(unsigned int irq) 467static void enable_sysint2_irq(unsigned int irq)
483{ 468{
484 set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); 469 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
485} 470}
486 471
487#define disable_sysint2_irq shutdown_sysint2_irq 472#define disable_sysint2_irq shutdown_sysint2_irq
@@ -490,7 +475,7 @@ static void enable_sysint2_irq(unsigned int irq)
490static void end_sysint2_irq(unsigned int irq) 475static void end_sysint2_irq(unsigned int irq)
491{ 476{
492 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 477 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
493 set_icu2(MSYSINT2REG, (uint16_t)1 << SYSINT2_IRQ_TO_PIN(irq)); 478 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
494} 479}
495 480
496static struct hw_interrupt_type sysint2_irq_type = { 481static struct hw_interrupt_type sysint2_irq_type = {
@@ -503,8 +488,6 @@ static struct hw_interrupt_type sysint2_irq_type = {
503 .end = end_sysint2_irq, 488 .end = end_sysint2_irq,
504}; 489};
505 490
506/*=======================================================================*/
507
508static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) 491static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
509{ 492{
510 irq_desc_t *desc = irq_desc + irq; 493 irq_desc_t *desc = irq_desc + irq;
@@ -515,8 +498,8 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
515 498
516 spin_lock_irq(&desc->lock); 499 spin_lock_irq(&desc->lock);
517 500
518 intassign0 = read_icu1(INTASSIGN0); 501 intassign0 = icu1_read(INTASSIGN0);
519 intassign1 = read_icu1(INTASSIGN1); 502 intassign1 = icu1_read(INTASSIGN1);
520 503
521 switch (pin) { 504 switch (pin) {
522 case 0: 505 case 0:
@@ -556,8 +539,8 @@ static inline int set_sysint1_assign(unsigned int irq, unsigned char assign)
556 } 539 }
557 540
558 sysint1_assign[pin] = assign; 541 sysint1_assign[pin] = assign;
559 write_icu1(intassign0, INTASSIGN0); 542 icu1_write(INTASSIGN0, intassign0);
560 write_icu1(intassign1, INTASSIGN1); 543 icu1_write(INTASSIGN1, intassign1);
561 544
562 spin_unlock_irq(&desc->lock); 545 spin_unlock_irq(&desc->lock);
563 546
@@ -574,8 +557,8 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
574 557
575 spin_lock_irq(&desc->lock); 558 spin_lock_irq(&desc->lock);
576 559
577 intassign2 = read_icu1(INTASSIGN2); 560 intassign2 = icu1_read(INTASSIGN2);
578 intassign3 = read_icu1(INTASSIGN3); 561 intassign3 = icu1_read(INTASSIGN3);
579 562
580 switch (pin) { 563 switch (pin) {
581 case 0: 564 case 0:
@@ -623,8 +606,8 @@ static inline int set_sysint2_assign(unsigned int irq, unsigned char assign)
623 } 606 }
624 607
625 sysint2_assign[pin] = assign; 608 sysint2_assign[pin] = assign;
626 write_icu1(intassign2, INTASSIGN2); 609 icu1_write(INTASSIGN2, intassign2);
627 write_icu1(intassign3, INTASSIGN3); 610 icu1_write(INTASSIGN3, intassign3);
628 611
629 spin_unlock_irq(&desc->lock); 612 spin_unlock_irq(&desc->lock);
630 613
@@ -651,88 +634,92 @@ int vr41xx_set_intassign(unsigned int irq, unsigned char intassign)
651 634
652EXPORT_SYMBOL(vr41xx_set_intassign); 635EXPORT_SYMBOL(vr41xx_set_intassign);
653 636
654/*=======================================================================*/ 637static int icu_get_irq(unsigned int irq, struct pt_regs *regs)
655
656asmlinkage void irq_dispatch(unsigned char intnum, struct pt_regs *regs)
657{ 638{
658 uint16_t pend1, pend2; 639 uint16_t pend1, pend2;
659 uint16_t mask1, mask2; 640 uint16_t mask1, mask2;
660 int i; 641 int i;
661 642
662 pend1 = read_icu1(SYSINT1REG); 643 pend1 = icu1_read(SYSINT1REG);
663 mask1 = read_icu1(MSYSINT1REG); 644 mask1 = icu1_read(MSYSINT1REG);
664 645
665 pend2 = read_icu2(SYSINT2REG); 646 pend2 = icu2_read(SYSINT2REG);
666 mask2 = read_icu2(MSYSINT2REG); 647 mask2 = icu2_read(MSYSINT2REG);
667 648
668 mask1 &= pend1; 649 mask1 &= pend1;
669 mask2 &= pend2; 650 mask2 &= pend2;
670 651
671 if (mask1) { 652 if (mask1) {
672 for (i = 0; i < 16; i++) { 653 for (i = 0; i < 16; i++) {
673 if (intnum == sysint1_assign[i] && 654 if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i)))
674 (mask1 & ((uint16_t)1 << i))) { 655 return SYSINT1_IRQ(i);
675 if (i == 8)
676 giuint_irq_dispatch(regs);
677 else
678 do_IRQ(SYSINT1_IRQ(i), regs);
679 return;
680 }
681 } 656 }
682 } 657 }
683 658
684 if (mask2) { 659 if (mask2) {
685 for (i = 0; i < 16; i++) { 660 for (i = 0; i < 16; i++) {
686 if (intnum == sysint2_assign[i] && 661 if (irq == INT_TO_IRQ(sysint2_assign[i]) && (mask2 & (1 << i)))
687 (mask2 & ((uint16_t)1 << i))) { 662 return SYSINT2_IRQ(i);
688 do_IRQ(SYSINT2_IRQ(i), regs);
689 return;
690 }
691 } 663 }
692 } 664 }
693 665
694 printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2); 666 printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2);
695 667
696 atomic_inc(&irq_err_count); 668 atomic_inc(&irq_err_count);
697}
698 669
699/*=======================================================================*/ 670 return -1;
671}
700 672
701static int __init vr41xx_icu_init(void) 673static int __init vr41xx_icu_init(void)
702{ 674{
675 unsigned long icu1_start, icu2_start;
676 int i;
677
703 switch (current_cpu_data.cputype) { 678 switch (current_cpu_data.cputype) {
704 case CPU_VR4111: 679 case CPU_VR4111:
705 case CPU_VR4121: 680 case CPU_VR4121:
706 icu1_base = SYSINT1REG_TYPE1; 681 icu1_start = ICU1_TYPE1_BASE;
707 icu2_base = SYSINT2REG_TYPE1; 682 icu2_start = ICU2_TYPE1_BASE;
708 break; 683 break;
709 case CPU_VR4122: 684 case CPU_VR4122:
710 case CPU_VR4131: 685 case CPU_VR4131:
711 case CPU_VR4133: 686 case CPU_VR4133:
712 icu1_base = SYSINT1REG_TYPE2; 687 icu1_start = ICU1_TYPE2_BASE;
713 icu2_base = SYSINT2REG_TYPE2; 688 icu2_start = ICU2_TYPE2_BASE;
714 break; 689 break;
715 default: 690 default:
716 printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n"); 691 printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n");
717 return -EINVAL; 692 return -ENODEV;
718 } 693 }
719 694
720 write_icu1(0, MSYSINT1REG); 695 if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL)
721 write_icu1(0xffff, MGIUINTLREG); 696 return -EBUSY;
722 697
723 write_icu2(0, MSYSINT2REG); 698 if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) {
724 write_icu2(0xffff, MGIUINTHREG); 699 release_mem_region(icu1_start, ICU1_SIZE);
700 return -EBUSY;
701 }
725 702
726 return 0; 703 icu1_base = ioremap(icu1_start, ICU1_SIZE);
727} 704 if (icu1_base == NULL) {
705 release_mem_region(icu1_start, ICU1_SIZE);
706 release_mem_region(icu2_start, ICU2_SIZE);
707 return -ENOMEM;
708 }
728 709
729early_initcall(vr41xx_icu_init); 710 icu2_base = ioremap(icu2_start, ICU2_SIZE);
711 if (icu2_base == NULL) {
712 iounmap(icu1_base);
713 release_mem_region(icu1_start, ICU1_SIZE);
714 release_mem_region(icu2_start, ICU2_SIZE);
715 return -ENOMEM;
716 }
730 717
731/*=======================================================================*/ 718 icu1_write(MSYSINT1REG, 0);
719 icu1_write(MGIUINTLREG, 0xffff);
732 720
733static inline void init_vr41xx_icu_irq(void) 721 icu2_write(MSYSINT2REG, 0);
734{ 722 icu2_write(MGIUINTHREG, 0xffff);
735 int i;
736 723
737 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) 724 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
738 irq_desc[i].handler = &sysint1_irq_type; 725 irq_desc[i].handler = &sysint1_irq_type;
@@ -740,18 +727,13 @@ static inline void init_vr41xx_icu_irq(void)
740 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) 727 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
741 irq_desc[i].handler = &sysint2_irq_type; 728 irq_desc[i].handler = &sysint2_irq_type;
742 729
743 setup_irq(INT0_CASCADE_IRQ, &icu_cascade); 730 cascade_irq(INT0_IRQ, icu_get_irq);
744 setup_irq(INT1_CASCADE_IRQ, &icu_cascade); 731 cascade_irq(INT1_IRQ, icu_get_irq);
745 setup_irq(INT2_CASCADE_IRQ, &icu_cascade); 732 cascade_irq(INT2_IRQ, icu_get_irq);
746 setup_irq(INT3_CASCADE_IRQ, &icu_cascade); 733 cascade_irq(INT3_IRQ, icu_get_irq);
747 setup_irq(INT4_CASCADE_IRQ, &icu_cascade); 734 cascade_irq(INT4_IRQ, icu_get_irq);
748}
749 735
750void __init arch_init_irq(void) 736 return 0;
751{
752 mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
753 init_vr41xx_icu_irq();
754 init_vr41xx_giuint_irq();
755
756 set_except_vector(0, vr41xx_handle_interrupt);
757} 737}
738
739core_initcall(vr41xx_icu_init);
diff --git a/arch/mips/vr41xx/common/int-handler.S b/arch/mips/vr41xx/common/int-handler.S
index 38ff89b505f2..272c13aee4fd 100644
--- a/arch/mips/vr41xx/common/int-handler.S
+++ b/arch/mips/vr41xx/common/int-handler.S
@@ -71,24 +71,24 @@
71 71
72 andi t1, t0, CAUSEF_IP3 # check for Int1 72 andi t1, t0, CAUSEF_IP3 # check for Int1
73 bnez t1, handle_int 73 bnez t1, handle_int
74 li a0, 1 74 li a0, 3
75 75
76 andi t1, t0, CAUSEF_IP4 # check for Int2 76 andi t1, t0, CAUSEF_IP4 # check for Int2
77 bnez t1, handle_int 77 bnez t1, handle_int
78 li a0, 2 78 li a0, 4
79 79
80 andi t1, t0, CAUSEF_IP5 # check for Int3 80 andi t1, t0, CAUSEF_IP5 # check for Int3
81 bnez t1, handle_int 81 bnez t1, handle_int
82 li a0, 3 82 li a0, 5
83 83
84 andi t1, t0, CAUSEF_IP6 # check for Int4 84 andi t1, t0, CAUSEF_IP6 # check for Int4
85 bnez t1, handle_int 85 bnez t1, handle_int
86 li a0, 4 86 li a0, 6
87 87
881: 881:
89 andi t1, t0, CAUSEF_IP2 # check for Int0 89 andi t1, t0, CAUSEF_IP2 # check for Int0
90 bnez t1, handle_int 90 bnez t1, handle_int
91 li a0, 0 91 li a0, 2
92 92
93 andi t1, t0, CAUSEF_IP0 # check for IP0 93 andi t1, t0, CAUSEF_IP0 # check for IP0
94 bnez t1, handle_irq 94 bnez t1, handle_irq
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
new file mode 100644
index 000000000000..43b214d39438
--- /dev/null
+++ b/arch/mips/vr41xx/common/irq.c
@@ -0,0 +1,94 @@
1/*
2 * Interrupt handing routines for NEC VR4100 series.
3 *
4 * Copyright (C) 2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/interrupt.h>
21#include <linux/module.h>
22
23#include <asm/irq_cpu.h>
24#include <asm/system.h>
25#include <asm/vr41xx/vr41xx.h>
26
27typedef struct irq_cascade {
28 int (*get_irq)(unsigned int, struct pt_regs *);
29} irq_cascade_t;
30
31static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
32
33static struct irqaction cascade_irqaction = {
34 .handler = no_action,
35 .mask = CPU_MASK_NONE,
36 .name = "cascade",
37};
38
39int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *))
40{
41 int retval = 0;
42
43 if (irq >= NR_IRQS)
44 return -EINVAL;
45
46 if (irq_cascade[irq].get_irq != NULL)
47 free_irq(irq, NULL);
48
49 irq_cascade[irq].get_irq = get_irq;
50
51 if (get_irq != NULL) {
52 retval = setup_irq(irq, &cascade_irqaction);
53 if (retval < 0)
54 irq_cascade[irq].get_irq = NULL;
55 }
56
57 return retval;
58}
59
60EXPORT_SYMBOL_GPL(cascade_irq);
61
62asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs)
63{
64 irq_cascade_t *cascade;
65 irq_desc_t *desc;
66
67 if (irq >= NR_IRQS) {
68 atomic_inc(&irq_err_count);
69 return;
70 }
71
72 cascade = irq_cascade + irq;
73 if (cascade->get_irq != NULL) {
74 unsigned int source_irq = irq;
75 desc = irq_desc + source_irq;
76 desc->handler->ack(source_irq);
77 irq = cascade->get_irq(irq, regs);
78 if (irq < 0)
79 atomic_inc(&irq_err_count);
80 else
81 irq_dispatch(irq, regs);
82 desc->handler->end(source_irq);
83 } else
84 do_IRQ(irq, regs);
85}
86
87extern asmlinkage void vr41xx_handle_interrupt(void);
88
89void __init arch_init_irq(void)
90{
91 mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
92
93 set_except_vector(0, vr41xx_handle_interrupt);
94}
diff --git a/arch/mips/vr41xx/tanbac-tb0226/setup.c b/arch/mips/vr41xx/common/type.c
index 60027e5dea25..bcb5f71b5026 100644
--- a/arch/mips/vr41xx/tanbac-tb0226/setup.c
+++ b/arch/mips/vr41xx/common/type.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * setup.c, Setup for the TANBAC TB0226. 2 * type.c, System type for NEC VR4100 series.
3 * 3 *
4 * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 4 * Copyright (C) 2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -20,5 +20,5 @@
20 20
21const char *get_system_type(void) 21const char *get_system_type(void)
22{ 22{
23 return "TANBAC TB0226"; 23 return "NEC VR4100 series";
24} 24}
diff --git a/arch/mips/vr41xx/common/vrc4173.c b/arch/mips/vr41xx/common/vrc4173.c
index 5475dd72e264..ba58764ef8ea 100644
--- a/arch/mips/vr41xx/common/vrc4173.c
+++ b/arch/mips/vr41xx/common/vrc4173.c
@@ -476,7 +476,7 @@ static inline int vrc4173_icu_init(int cascade_irq)
476 476
477 if (cascade_irq < GIU_IRQ(0) || cascade_irq > GIU_IRQ(15)) 477 if (cascade_irq < GIU_IRQ(0) || cascade_irq > GIU_IRQ(15))
478 return -EINVAL; 478 return -EINVAL;
479 479
480 vrc4173_outw(0, VRC4173_MSYSINT1REG); 480 vrc4173_outw(0, VRC4173_MSYSINT1REG);
481 481
482 vr41xx_set_irq_trigger(GIU_IRQ_TO_PIN(cascade_irq), TRIGGER_LEVEL, SIGNAL_THROUGH); 482 vr41xx_set_irq_trigger(GIU_IRQ_TO_PIN(cascade_irq), TRIGGER_LEVEL, SIGNAL_THROUGH);
diff --git a/arch/mips/vr41xx/ibm-workpad/setup.c b/arch/mips/vr41xx/ibm-workpad/setup.c
index cff44602d3d4..e4b34ad6ea61 100644
--- a/arch/mips/vr41xx/ibm-workpad/setup.c
+++ b/arch/mips/vr41xx/ibm-workpad/setup.c
@@ -23,11 +23,6 @@
23#include <asm/io.h> 23#include <asm/io.h>
24#include <asm/vr41xx/workpad.h> 24#include <asm/vr41xx/workpad.h>
25 25
26const char *get_system_type(void)
27{
28 return "IBM WorkPad z50";
29}
30
31static int __init ibm_workpad_setup(void) 26static int __init ibm_workpad_setup(void)
32{ 27{
33 set_io_port_base(IO_PORT_BASE); 28 set_io_port_base(IO_PORT_BASE);
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/init.c b/arch/mips/vr41xx/nec-cmbvr4133/init.c
index 87f06b3f5a9c..be590edb0b83 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/init.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/init.c
@@ -16,11 +16,6 @@
16 * Manish Lachwani (mlachwani@mvista.com) 16 * Manish Lachwani (mlachwani@mvista.com)
17 */ 17 */
18#include <linux/config.h> 18#include <linux/config.h>
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/string.h>
22
23#include <asm/bootinfo.h>
24 19
25#ifdef CONFIG_ROCKHOPPER 20#ifdef CONFIG_ROCKHOPPER
26#include <asm/io.h> 21#include <asm/io.h>
@@ -28,14 +23,7 @@
28 23
29#define PCICONFDREG 0xaf000c14 24#define PCICONFDREG 0xaf000c14
30#define PCICONFAREG 0xaf000c18 25#define PCICONFAREG 0xaf000c18
31#endif
32
33const char *get_system_type(void)
34{
35 return "NEC CMB-VR4133";
36}
37 26
38#ifdef CONFIG_ROCKHOPPER
39void disable_pcnet(void) 27void disable_pcnet(void)
40{ 28{
41 u32 data; 29 u32 data;
diff --git a/arch/mips/vr41xx/tanbac-tb0226/Makefile b/arch/mips/vr41xx/tanbac-tb0226/Makefile
deleted file mode 100644
index 372f953d240b..000000000000
--- a/arch/mips/vr41xx/tanbac-tb0226/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for the TANBAC TB0226 specific parts of the kernel
3#
4
5obj-y += setup.o
diff --git a/arch/mips/vr41xx/tanbac-tb0229/Makefile b/arch/mips/vr41xx/tanbac-tb0229/Makefile
deleted file mode 100644
index 9c6b864ef2ef..000000000000
--- a/arch/mips/vr41xx/tanbac-tb0229/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for the TANBAC TB0229(VR4131DIMM) specific parts of the kernel
3#
4
5obj-y := setup.o
diff --git a/arch/mips/vr41xx/tanbac-tb0229/setup.c b/arch/mips/vr41xx/tanbac-tb0229/setup.c
deleted file mode 100644
index 5c1b757bfb0c..000000000000
--- a/arch/mips/vr41xx/tanbac-tb0229/setup.c
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * setup.c, Setup for the TANBAC TB0229 (VR4131DIMM)
3 *
4 * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
5 *
6 * Modified for TANBAC TB0229:
7 * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24const char *get_system_type(void)
25{
26 return "TANBAC TB0229";
27}
diff --git a/arch/mips/vr41xx/victor-mpc30x/Makefile b/arch/mips/vr41xx/victor-mpc30x/Makefile
deleted file mode 100644
index a2e8086a31a6..000000000000
--- a/arch/mips/vr41xx/victor-mpc30x/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for the Victor MP-C303/304 specific parts of the kernel
3#
4
5obj-y += setup.o
diff --git a/arch/mips/vr41xx/victor-mpc30x/setup.c b/arch/mips/vr41xx/victor-mpc30x/setup.c
deleted file mode 100644
index f591e36726e6..000000000000
--- a/arch/mips/vr41xx/victor-mpc30x/setup.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * setup.c, Setup for the Victor MP-C303/304.
3 *
4 * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21const char *get_system_type(void)
22{
23 return "Victor MP-C303/304";
24}
diff --git a/arch/mips/vr41xx/zao-capcella/Makefile b/arch/mips/vr41xx/zao-capcella/Makefile
deleted file mode 100644
index cf420197cd23..000000000000
--- a/arch/mips/vr41xx/zao-capcella/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for the ZAO Networks Capcella specific parts of the kernel
3#
4
5obj-y += setup.o
diff --git a/arch/mips/vr41xx/zao-capcella/setup.c b/arch/mips/vr41xx/zao-capcella/setup.c
deleted file mode 100644
index 17bade241fe2..000000000000
--- a/arch/mips/vr41xx/zao-capcella/setup.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * setup.c, Setup for the ZAO Networks Capcella.
3 *
4 * Copyright (C) 2002-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21const char *get_system_type(void)
22{
23 return "ZAO Networks Capcella";
24}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 21:30:05 -0500