150 files changed, 15110 insertions, 733 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 25f3b0a11ca8..8c4be1f301cf 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -601,6 +601,7 @@ config CAVIUM_OCTEON_SIMULATOR
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_SUPPORTS_HIGHMEM
+        select SYS_SUPPORTS_HOTPLUG_CPU
         select SYS_HAS_CPU_CAVIUM_OCTEON
         help
           The Octeon simulator is software performance model of the Cavium
@@ -615,9 +616,12 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
         select SYS_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_SUPPORTS_HIGHMEM
+        select SYS_SUPPORTS_HOTPLUG_CPU
         select SYS_HAS_EARLY_PRINTK
         select SYS_HAS_CPU_CAVIUM_OCTEON
         select SWAP_IO_SPACE
+        select HW_HAS_PCI
+        select ARCH_SUPPORTS_MSI
         help
           This option supports all of the Octeon reference boards from Cavium
           Networks. It builds a kernel that dynamically determines the Octeon
@@ -782,8 +786,17 @@ config SYS_HAS_EARLY_PRINTK
         bool
 
 config HOTPLUG_CPU
+        bool "Support for hot-pluggable CPUs"
+        depends on SMP && HOTPLUG && SYS_SUPPORTS_HOTPLUG_CPU
+        help
+          Say Y here to allow turning CPUs off and on. CPUs can be
+          controlled through /sys/devices/system/cpu.
+          (Note: power management support will enable this option
+            automatically on SMP systems. )
+          Say N if you want to disable CPU hotplug.
+
+config SYS_SUPPORTS_HOTPLUG_CPU
         bool
-        default n
 
 config I8259
         bool
@@ -851,6 +864,11 @@ config SYS_SUPPORTS_BIG_ENDIAN
 config SYS_SUPPORTS_LITTLE_ENDIAN
         bool
 
+config SYS_SUPPORTS_HUGETLBFS
+        bool
+        depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
+        default y
+
 config IRQ_CPU
         bool
 
@@ -1055,6 +1073,7 @@ config CPU_MIPS64_R1
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
+        select CPU_SUPPORTS_HUGEPAGES
         help
           Choose this option to build a kernel for release 1 or later of the
           MIPS64 architecture.  Many modern embedded systems with a 64-bit
@@ -1074,6 +1093,7 @@ config CPU_MIPS64_R2
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
+        select CPU_SUPPORTS_HUGEPAGES
         help
           Choose this option to build a kernel for release 2 or later of the
           MIPS64 architecture.  Many modern embedded systems with a 64-bit
@@ -1160,6 +1180,7 @@ config CPU_R5500
         select CPU_HAS_LLSC
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HUGEPAGES
         help
           NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
           instruction set.
@@ -1245,6 +1266,7 @@ config CPU_CAVIUM_OCTEON
         select WEAK_ORDERING
         select WEAK_REORDERING_BEYOND_LLSC
         select CPU_SUPPORTS_HIGHMEM
+        select CPU_SUPPORTS_HUGEPAGES
         help
           The Cavium Octeon processor is a highly integrated chip containing
           many ethernet hardware widgets for networking tasks. The processor
@@ -1364,6 +1386,8 @@ config CPU_SUPPORTS_32BIT_KERNEL
         bool
 config CPU_SUPPORTS_64BIT_KERNEL
         bool
+config CPU_SUPPORTS_HUGEPAGES
+        bool
 
 #
 # Set to y for ptrace access to watch registers.
@@ -2121,9 +2145,13 @@ endmenu
 
 menu "Power management options"
 
+config ARCH_HIBERNATION_POSSIBLE
+        def_bool y
+        depends on SYS_SUPPORTS_HOTPLUG_CPU
+
 config ARCH_SUSPEND_POSSIBLE
         def_bool y
-        depends on !SMP
+        depends on SYS_SUPPORTS_HOTPLUG_CPU
 
 source "kernel/power/Kconfig"
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index c4cae9e6b802..807572a6a4d2 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -167,7 +167,6 @@ libs-$(CONFIG_ARC)		+= arch/mips/fw/arc/
 libs-$(CONFIG_CFE)              += arch/mips/fw/cfe/
 libs-$(CONFIG_SNIPROM)          += arch/mips/fw/sni/
 libs-y                          += arch/mips/fw/lib/
-libs-$(CONFIG_SIBYTE_CFE)       += arch/mips/sibyte/cfe/
 
 #
 # Board-dependent options and extra files
@@ -184,7 +183,6 @@ load-$(CONFIG_MACH_JAZZ)	+= 0xffffffff80080000
 # Common Alchemy Au1x00 stuff
 #
 core-$(CONFIG_SOC_AU1X00)       += arch/mips/alchemy/common/
-cflags-$(CONFIG_SOC_AU1X00)     += -I$(srctree)/arch/mips/include/asm/mach-au1x00
 
 #
 # AMD Alchemy Pb1000 eval board
@@ -282,6 +280,10 @@ load-$(CONFIG_MIPS_MTX1)	+= 0xffffffff80100000
 libs-$(CONFIG_MIPS_XXS1500)     += arch/mips/alchemy/xxs1500/
 load-$(CONFIG_MIPS_XXS1500)     += 0xffffffff80100000
 
+# must be last for Alchemy systems for GPIO to work properly
+cflags-$(CONFIG_SOC_AU1X00)     += -I$(srctree)/arch/mips/include/asm/mach-au1x00
+
+
 #
 # Cobalt Server
 #
@@ -675,6 +677,9 @@ core-y			+= arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
 
 drivers-$(CONFIG_OPROFILE)      += arch/mips/oprofile/
 
+# suspend and hibernation support
+drivers-$(CONFIG_PM)    += arch/mips/power/
+
 ifdef CONFIG_LASAT
 rom.bin rom.sw: vmlinux
         $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 8128aebfb155..00b498e97c83 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -1,3 +1,14 @@
+# au1000-style gpio
+config ALCHEMY_GPIO_AU1000
+        bool
+
+# select this in your board config if you don't want to use the gpio
+# namespace as documented in the manuals.  In this case however you need
+# to create the necessary gpio_* functions in your board code/headers!
+# see arch/mips/include/asm/mach-au1x00/gpio.h   for more information.
+config ALCHEMY_GPIO_INDIRECT
+        def_bool n
+
 choice
         prompt "Machine type"
         depends on MACH_ALCHEMY
@@ -108,22 +119,27 @@ endchoice
 config SOC_AU1000
         bool
         select SOC_AU1X00
+        select ALCHEMY_GPIO_AU1000
 
 config SOC_AU1100
         bool
         select SOC_AU1X00
+        select ALCHEMY_GPIO_AU1000
 
 config SOC_AU1500
         bool
         select SOC_AU1X00
+        select ALCHEMY_GPIO_AU1000
 
 config SOC_AU1550
         bool
         select SOC_AU1X00
+        select ALCHEMY_GPIO_AU1000
 
 config SOC_AU1200
         bool
         select SOC_AU1X00
+        select ALCHEMY_GPIO_AU1000
 
 config SOC_AU1X00
         bool
@@ -134,4 +150,5 @@ config SOC_AU1X00
         select SYS_HAS_CPU_MIPS32_R1
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_APM_EMULATION
-        select ARCH_REQUIRE_GPIOLIB
+        select GENERIC_GPIO
+        select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index d50d4764eafe..b67fb512529d 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -7,7 +7,14 @@
 
 obj-y += prom.o irq.o puts.o time.o reset.o \
         clocks.o platform.o power.o setup.o \
-        sleeper.o dma.o dbdma.o gpio.o
+        sleeper.o dma.o dbdma.o
+
+# optional gpiolib support
+ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
+ ifeq ($(CONFIG_GPIOLIB),y)
+  obj-$(CONFIG_ALCHEMY_GPIO_AU1000) += gpiolib-au1000.o
+ endif
+endif
 
 obj-$(CONFIG_PCI)               += pci.o
 
diff --git a/arch/mips/alchemy/common/gpio.c b/arch/mips/alchemy/common/gpio.c
deleted file mode 100644
index 91a9c4436c39..000000000000
--- a/arch/mips/alchemy/common/gpio.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- *  Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
- *      Architecture specific GPIO support
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *  Notes :
- *      au1000 SoC have only one GPIO line : GPIO1
- *      others have a second one : GPIO2
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-au1x00/au1000.h>
-#include <asm/gpio.h>
-
-struct au1000_gpio_chip {
-        struct gpio_chip        chip;
-        void __iomem            *regbase;
-};
-
-#if !defined(CONFIG_SOC_AU1000)
-static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
-{
-        u32 mask = 1 << offset;
-        struct au1000_gpio_chip *gpch;
-
-        gpch = container_of(chip, struct au1000_gpio_chip, chip);
-        return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
-}
-
-static void au1000_gpio2_set(struct gpio_chip *chip,
-                                unsigned offset, int value)
-{
-        u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
-        struct au1000_gpio_chip *gpch;
-        unsigned long flags;
-
-        gpch = container_of(chip, struct au1000_gpio_chip, chip);
-
-        local_irq_save(flags);
-        writel(mask, gpch->regbase + AU1000_GPIO2_OUT);
-        local_irq_restore(flags);
-}
-
-static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        u32 mask = 1 << offset;
-        u32 tmp;
-        struct au1000_gpio_chip *gpch;
-        unsigned long flags;
-
-        gpch = container_of(chip, struct au1000_gpio_chip, chip);
-
-        local_irq_save(flags);
-        tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
-        tmp &= ~mask;
-        writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-static int au1000_gpio2_direction_output(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        u32 mask = 1 << offset;
-        u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
-        u32 tmp;
-        struct au1000_gpio_chip *gpch;
-        unsigned long flags;
-
-        gpch = container_of(chip, struct au1000_gpio_chip, chip);
-
-        local_irq_save(flags);
-        tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
-        tmp |= mask;
-        writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
-        writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT);
-        local_irq_restore(flags);
-
-        return 0;
-}
-#endif /* !defined(CONFIG_SOC_AU1000) */
-
-static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
-{
-        u32 mask = 1 << offset;
-        struct au1000_gpio_chip *gpch;
-
-        gpch = container_of(chip, struct au1000_gpio_chip, chip);
-        return readl(gpch->regbase + AU1000_GPIO1_ST) & mask;
-}
-
-static void au1000_gpio1_set(struct gpio_chip *chip,
-                                unsigned offset, int value)
-{
-        u32 mask = 1 << offset;
-        u32 reg_offset;
-        struct au1000_gpio_chip *gpch;
-        unsigned long flags;
-
-        gpch = container_of(chip, struct au1000_gpio_chip, chip);
-
-        if (value)
-                reg_offset = AU1000_GPIO1_OUT;
-        else
-                reg_offset = AU1000_GPIO1_CLR;
-
-        local_irq_save(flags);
-        writel(mask, gpch->regbase + reg_offset);
-        local_irq_restore(flags);
-}
-
-static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-        u32 mask = 1 << offset;
-        struct au1000_gpio_chip *gpch;
-
-        gpch = container_of(chip, struct au1000_gpio_chip, chip);
-        writel(mask, gpch->regbase + AU1000_GPIO1_ST);
-
-        return 0;
-}
-
-static int au1000_gpio1_direction_output(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        u32 mask = 1 << offset;
-        struct au1000_gpio_chip *gpch;
-
-        gpch = container_of(chip, struct au1000_gpio_chip, chip);
-
-        writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT);
-        au1000_gpio1_set(chip, offset, value);
-
-        return 0;
-}
-
-struct au1000_gpio_chip au1000_gpio_chip[] = {
-        [0] = {
-                .regbase                        = (void __iomem *)SYS_BASE,
-                .chip = {
-                        .label                  = "au1000-gpio1",
-                        .direction_input        = au1000_gpio1_direction_input,
-                        .direction_output       = au1000_gpio1_direction_output,
-                        .get                    = au1000_gpio1_get,
-                        .set                    = au1000_gpio1_set,
-                        .base                   = 0,
-                        .ngpio                  = 32,
-                },
-        },
-#if !defined(CONFIG_SOC_AU1000)
-        [1] = {
-                .regbase                        = (void __iomem *)GPIO2_BASE,
-                .chip = {
-                        .label                  = "au1000-gpio2",
-                        .direction_input        = au1000_gpio2_direction_input,
-                        .direction_output       = au1000_gpio2_direction_output,
-                        .get                    = au1000_gpio2_get,
-                        .set                    = au1000_gpio2_set,
-                        .base                   = AU1XXX_GPIO_BASE,
-                        .ngpio                  = 32,
-                },
-        },
-#endif
-};
-
-static int __init au1000_gpio_init(void)
-{
-        gpiochip_add(&au1000_gpio_chip[0].chip);
-#if !defined(CONFIG_SOC_AU1000)
-        gpiochip_add(&au1000_gpio_chip[1].chip);
-#endif
-
-        return 0;
-}
-arch_initcall(au1000_gpio_init);
-
diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib-au1000.c
new file mode 100644
index 000000000000..1bfa91f939f4
--- /dev/null
+++ b/arch/mips/alchemy/common/gpiolib-au1000.c
@@ -0,0 +1,130 @@
+/*
+ *  Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
+ *      GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *  Notes :
+ *      au1000 SoC have only one GPIO block : GPIO1
+ *      Au1100, Au15x0, Au12x0 have a second one : GPIO2
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/gpio.h>
+
+#if !defined(CONFIG_SOC_AU1000)
+static int gpio2_get(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
+}
+
+static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
+}
+
+static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
+}
+
+static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset,
+                                  int value)
+{
+        return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
+                                                value);
+}
+
+static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
+}
+#endif /* !defined(CONFIG_SOC_AU1000) */
+
+static int gpio1_get(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
+}
+
+static void gpio1_set(struct gpio_chip *chip,
+                                unsigned offset, int value)
+{
+        alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
+}
+
+static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
+}
+
+static int gpio1_direction_output(struct gpio_chip *chip,
+                                        unsigned offset, int value)
+{
+        return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
+                                             value);
+}
+
+static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
+}
+
+struct gpio_chip alchemy_gpio_chip[] = {
+        [0] = {
+                .label                  = "alchemy-gpio1",
+                .direction_input        = gpio1_direction_input,
+                .direction_output       = gpio1_direction_output,
+                .get                    = gpio1_get,
+                .set                    = gpio1_set,
+                .to_irq                 = gpio1_to_irq,
+                .base                   = ALCHEMY_GPIO1_BASE,
+                .ngpio                  = ALCHEMY_GPIO1_NUM,
+        },
+#if !defined(CONFIG_SOC_AU1000)
+        [1] = {
+                .label                  = "alchemy-gpio2",
+                .direction_input        = gpio2_direction_input,
+                .direction_output       = gpio2_direction_output,
+                .get                    = gpio2_get,
+                .set                    = gpio2_set,
+                .to_irq                 = gpio2_to_irq,
+                .base                   = ALCHEMY_GPIO2_BASE,
+                .ngpio                  = ALCHEMY_GPIO2_NUM,
+        },
+#endif
+};
+
+static int __init alchemy_gpiolib_init(void)
+{
+        gpiochip_add(&alchemy_gpio_chip[0]);
+#if !defined(CONFIG_SOC_AU1000)
+        gpiochip_add(&alchemy_gpio_chip[1]);
+#endif
+
+        return 0;
+}
+arch_initcall(alchemy_gpiolib_init);
diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c
index 0191c936cb5e..4791011e8f92 100644
--- a/arch/mips/alchemy/common/reset.c
+++ b/arch/mips/alchemy/common/reset.c
@@ -27,8 +27,9 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <asm/cacheflush.h>
+#include <linux/gpio.h>
 
+#include <asm/cacheflush.h>
 #include <asm/mach-au1x00/au1000.h>
 
 void au1000_restart(char *command)
@@ -161,7 +162,7 @@ void au1000_halt(void)
 #else
         printk(KERN_NOTICE "\n** You can safely turn off the power\n");
 #ifdef CONFIG_MIPS_MIRAGE
-        au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
+        gpio_direction_output(210, 1);
 #endif
 #ifdef CONFIG_MIPS_DB1200
         au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index a75ffbf99f25..de30d8ea7176 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -27,6 +27,7 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/gpio.h>
 #include <linux/init.h>
 
 #include <asm/mach-au1x00/au1000.h>
@@ -94,12 +95,12 @@ void __init board_setup(void)
 #endif
         bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */
 
-#ifdef CONFIG_MIPS_MIRAGE
         /* Enable GPIO[31:0] inputs */
-        au_writel(0, SYS_PININPUTEN);
+        alchemy_gpio1_input_enable();
 
-        /* GPIO[20] is output, tristate the other input primary GPIOs */
-        au_writel(~(1 << 20), SYS_TRIOUTCLR);
+#ifdef CONFIG_MIPS_MIRAGE
+        /* GPIO[20] is output */
+        alchemy_gpio_direction_output(20, 0);
 
         /* Set GPIO[210:208] instead of SSI_0 */
         pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
@@ -118,8 +119,7 @@ void __init board_setup(void)
          * Enable speaker amplifier.  This should
          * be part of the audio driver.
          */
-        au_writel(au_readl(GPIO2_DIR) | 0x200, GPIO2_DIR);
-        au_writel(0x02000200, GPIO2_OUTPUT);
+        alchemy_gpio_direction_output(209, 1);
 #endif
 
         au_sync();
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index aed2fdecc709..cd273545e810 100644
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -24,6 +24,7 @@
  */
 
 #include <linux/delay.h>
+#include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <asm/mach-au1x00/au1000.h>
@@ -130,8 +131,11 @@ void __init board_setup(void)
         pin_func |= SYS_PF_USB;
 
         au_writel(pin_func, SYS_PINFUNC);
-        au_writel(0x2800, SYS_TRIOUTCLR);
-        au_writel(0x0030, SYS_OUTPUTCLR);
+
+        alchemy_gpio_direction_input(11);
+        alchemy_gpio_direction_input(13);
+        alchemy_gpio_direction_output(4, 0);
+        alchemy_gpio_direction_output(5, 0);
 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
 
         /* Make GPIO 15 an input (for interrupt line) */
@@ -140,7 +144,7 @@ void __init board_setup(void)
         pin_func |= SYS_PF_I2S;
         au_writel(pin_func, SYS_PINFUNC);
 
-        au_writel(0x8000, SYS_TRIOUTCLR);
+        alchemy_gpio_direction_input(15);
 
         static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
         au_writel(static_cfg0, MEM_STCFG0);
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
index 4df57fae15d4..61263081ef58 100644
--- a/arch/mips/alchemy/devboards/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -23,6 +23,7 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
@@ -88,7 +89,7 @@ void __init board_setup(void)
 
         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
         au_writel(8, SYS_AUXPLL);
-        au_writel(0, SYS_PININPUTEN);
+        alchemy_gpio1_input_enable();
         udelay(100);
 
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index fed3b093156a..d7a56569e7ed 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -23,8 +23,9 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
-#include <linux/init.h>
 #include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
 #include <linux/interrupt.h>
 
 #include <asm/mach-au1x00/au1000.h>
@@ -90,11 +91,12 @@ void __init board_setup(void)
         au_writel(0, SYS_PINSTATERD);
         udelay(100);
 
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-
         /* GPIO201 is input for PCMCIA card detect */
         /* GPIO203 is input for PCMCIA interrupt request */
-        au_writel(au_readl(GPIO2_DIR) & ~((1 << 1) | (1 << 3)), GPIO2_DIR);
+        alchemy_gpio_direction_input(201);
+        alchemy_gpio_direction_input(203);
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
 
         /* Zero and disable FREQ2 */
         sys_freqctrl = au_readl(SYS_FREQCTRL0);
diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c
index d5eb9c325ed0..632f9862a0fb 100644
--- a/arch/mips/alchemy/devboards/pm.c
+++ b/arch/mips/alchemy/devboards/pm.c
@@ -9,6 +9,7 @@
 #include <linux/suspend.h>
 #include <linux/sysfs.h>
 #include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/gpio.h>
 
 /*
  * Generic suspend userspace interface for Alchemy development boards.
@@ -26,7 +27,7 @@ static unsigned long db1x_pm_last_wakesrc;
 static int db1x_pm_enter(suspend_state_t state)
 {
         /* enable GPIO based wakeup */
-        au_writel(1, SYS_PININPUTEN);
+        alchemy_gpio1_input_enable();
 
         /* clear and setup wake cause and source */
         au_writel(0, SYS_WAKEMSK);
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 8ed1ae12bc55..cc32c69a74ad 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -28,6 +28,7 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/gpio.h>
 #include <linux/init.h>
 
 #include <asm/mach-au1x00/au1000.h>
@@ -55,10 +56,11 @@ void __init board_setup(void)
         }
 #endif
 
+        alchemy_gpio2_enable();
+
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
         /* Enable USB power switch */
-        au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR);
-        au_writel(0x100000, GPIO2_OUTPUT);
+        alchemy_gpio_direction_output(204, 0);
 #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
 
 #ifdef CONFIG_PCI
@@ -74,14 +76,14 @@ void __init board_setup(void)
 
         /* Initialize GPIO */
         au_writel(0xFFFFFFFF, SYS_TRIOUTCLR);
-        au_writel(0x00000001, SYS_OUTPUTCLR); /* set M66EN (PCI 66MHz) to OFF */
-        au_writel(0x00000008, SYS_OUTPUTSET); /* set PCI CLKRUN# to OFF */
-        au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */
-        au_writel(0x00000020, SYS_OUTPUTCLR); /* set eth PHY TX_ER to OFF */
+        alchemy_gpio_direction_output(0, 0);    /* Disable M66EN (PCI 66MHz) */
+        alchemy_gpio_direction_output(3, 1);    /* Disable PCI CLKRUN# */
+        alchemy_gpio_direction_output(1, 1);    /* Enable EXT_IO3 */
+        alchemy_gpio_direction_output(5, 0);    /* Disable eth PHY TX_ER */
 
         /* Enable LED and set it to green */
-        au_writel(au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR);
-        au_writel(0x18000800, GPIO2_OUTPUT);
+        alchemy_gpio_direction_output(211, 1);  /* green on */
+        alchemy_gpio_direction_output(212, 0);  /* red off */
 
         board_pci_idsel = mtx1_pci_idsel;
 
@@ -101,10 +103,10 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
 
         if (assert && devsel != 0)
                 /* Suppress signal to Cardbus */
-                au_writel(0x00000002, SYS_OUTPUTCLR); /* set EXT_IO3 OFF */
+                gpio_set_value(1, 0);   /* set EXT_IO3 OFF */
         else
-                au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */
+                gpio_set_value(1, 1);   /* set EXT_IO3 ON */
+
         au_sync_udelay(1);
         return 1;
 }
-
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index a2634fabc50d..4de2d48caed8 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -23,6 +23,7 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/delay.h>
 
@@ -50,6 +51,9 @@ void __init board_setup(void)
         }
 #endif
 
+        alchemy_gpio1_input_enable();
+        alchemy_gpio2_enable();
+
         /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
         pin_func  = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
         pin_func |= SYS_PF_UR3;
@@ -65,20 +69,19 @@ void __init board_setup(void)
         au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
 
 #ifdef CONFIG_PCMCIA_XXS1500
-        /* Setup PCMCIA signals */
-        au_writel(0, SYS_PININPUTEN);
-
         /* GPIO 0, 1, and 4 are inputs */
-        au_writel(1 | (1 << 1) | (1 << 4), SYS_TRIOUTCLR);
+        alchemy_gpio_direction_input(0);
+        alchemy_gpio_direction_input(1);
+        alchemy_gpio_direction_input(4);
 
-        /* Enable GPIO2 if not already enabled */
-        au_writel(1, GPIO2_ENABLE);
         /* GPIO2 208/9/10/11 are inputs */
-        au_writel((1 << 8) | (1 << 9) | (1 << 10) | (1 << 11), GPIO2_DIR);
+        alchemy_gpio_direction_input(208);
+        alchemy_gpio_direction_input(209);
+        alchemy_gpio_direction_input(210);
+        alchemy_gpio_direction_input(211);
 
         /* Turn off power */
-        au_writel((au_readl(GPIO2_PINSTATE) & ~(1 << 14)) | (1 << 30),
-                  GPIO2_OUTPUT);
+        alchemy_gpio_direction_output(214, 0);
 #endif
 
 #ifdef CONFIG_PCI
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index d6903c3f3d51..7c0528b0e34c 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -14,5 +14,9 @@ obj-y += dma-octeon.o flash_setup.o
 obj-y += octeon-memcpy.o
 
 obj-$(CONFIG_SMP)                     += smp.o
+obj-$(CONFIG_PCI)                     += pci-common.o
+obj-$(CONFIG_PCI)                     += pci.o
+obj-$(CONFIG_PCI)                     += pcie.o
+obj-$(CONFIG_PCI_MSI)                 += msi.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index 01b1ef94b361..627c162a6159 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -13,20 +13,327 @@
  */
 #include <linux/types.h>
 #include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/scatterlist.h>
+
+#include <linux/cache.h>
+#include <linux/io.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-npi-defs.h>
+#include <asm/octeon/cvmx-pci-defs.h>
 
 #include <dma-coherence.h>
 
+#ifdef CONFIG_PCI
+#include "pci-common.h"
+#endif
+
+#define BAR2_PCI_ADDRESS 0x8000000000ul
+
+struct bar1_index_state {
+        int16_t ref_count;      /* Number of PCI mappings using this index */
+        uint16_t address_bits;  /* Upper bits of physical address. This is
+                                   shifted 22 bits */
+};
+
+#ifdef CONFIG_PCI
+static DEFINE_SPINLOCK(bar1_lock);
+static struct bar1_index_state bar1_state[32];
+#endif
+
 dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
 {
+#ifndef CONFIG_PCI
         /* Without PCI/PCIe this function can be called for Octeon internal
            devices such as USB. These devices all support 64bit addressing */
         mb();
         return virt_to_phys(ptr);
+#else
+        unsigned long flags;
+        uint64_t dma_mask;
+        int64_t start_index;
+        dma_addr_t result = -1;
+        uint64_t physical = virt_to_phys(ptr);
+        int64_t index;
+
+        mb();
+        /*
+         * Use the DMA masks to determine the allowed memory
+         * region. For us it doesn't limit the actual memory, just the
+         * address visible over PCI.  Devices with limits need to use
+         * lower indexed Bar1 entries.
+         */
+        if (dev) {
+                dma_mask = dev->coherent_dma_mask;
+                if (dev->dma_mask)
+                        dma_mask = *dev->dma_mask;
+        } else {
+                dma_mask = 0xfffffffful;
+        }
+
+        /*
+         * Platform devices, such as the internal USB, skip all
+         * translation and use Octeon physical addresses directly.
+         */
+        if (!dev || dev->bus == &platform_bus_type)
+                return physical;
+
+        switch (octeon_dma_bar_type) {
+        case OCTEON_DMA_BAR_TYPE_PCIE:
+                if (unlikely(physical < (16ul << 10)))
+                        panic("dma_map_single: Not allowed to map first 16KB."
+                              " It interferes with BAR0 special area\n");
+                else if ((physical + size >= (256ul << 20)) &&
+                         (physical < (512ul << 20)))
+                        panic("dma_map_single: Not allowed to map bootbus\n");
+                else if ((physical + size >= 0x400000000ull) &&
+                         physical < 0x410000000ull)
+                        panic("dma_map_single: "
+                              "Attempt to map illegal memory address 0x%llx\n",
+                              physical);
+                else if (physical >= 0x420000000ull)
+                        panic("dma_map_single: "
+                              "Attempt to map illegal memory address 0x%llx\n",
+                              physical);
+                else if ((physical + size >=
+                          (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20))
+                         && physical < (4ull<<30))
+                        pr_warning("dma_map_single: Warning: "
+                                   "Mapping memory address that might "
+                                   "conflict with devices 0x%llx-0x%llx\n",
+                                   physical, physical+size-1);
+                /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
+                if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
+                        result = physical - 0x400000000ull;
+                else
+                        result = physical;
+                if (((result+size-1) & dma_mask) != result+size-1)
+                        panic("dma_map_single: Attempt to map address "
+                              "0x%llx-0x%llx, which can't be accessed "
+                              "according to the dma mask 0x%llx\n",
+                              physical, physical+size-1, dma_mask);
+                goto done;
+
+        case OCTEON_DMA_BAR_TYPE_BIG:
+#ifdef CONFIG_64BIT
+                /* If the device supports 64bit addressing, then use BAR2 */
+                if (dma_mask > BAR2_PCI_ADDRESS) {
+                        result = physical + BAR2_PCI_ADDRESS;
+                        goto done;
+                }
+#endif
+                if (unlikely(physical < (4ul << 10))) {
+                        panic("dma_map_single: Not allowed to map first 4KB. "
+                              "It interferes with BAR0 special area\n");
+                } else if (physical < (256ul << 20)) {
+                        if (unlikely(physical + size > (256ul << 20)))
+                                panic("dma_map_single: Requested memory spans "
+                                      "Bar0 0:256MB and bootbus\n");
+                        result = physical;
+                        goto done;
+                } else if (unlikely(physical < (512ul << 20))) {
+                        panic("dma_map_single: Not allowed to map bootbus\n");
+                } else if (physical < (2ul << 30)) {
+                        if (unlikely(physical + size > (2ul << 30)))
+                                panic("dma_map_single: Requested memory spans "
+                                      "Bar0 512MB:2GB and BAR1\n");
+                        result = physical;
+                        goto done;
+                } else if (physical < (2ul << 30) + (128 << 20)) {
+                        /* Fall through */
+                } else if (physical <
+                           (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) {
+                        if (unlikely
+                            (physical + size >
+                             (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)))
+                                panic("dma_map_single: Requested memory "
+                                      "extends past Bar1 (4GB-%luMB)\n",
+                                      OCTEON_PCI_BAR1_HOLE_SIZE);
+                        result = physical;
+                        goto done;
+                } else if ((physical >= 0x410000000ull) &&
+                           (physical < 0x420000000ull)) {
+                        if (unlikely(physical + size > 0x420000000ull))
+                                panic("dma_map_single: Requested memory spans "
+                                      "non existant memory\n");
+                        /* BAR0 fixed mapping 256MB:512MB ->
+                         * 16GB+256MB:16GB+512MB */
+                        result = physical - 0x400000000ull;
+                        goto done;
+                } else {
+                        /* Continued below switch statement */
+                }
+                break;
+
+        case OCTEON_DMA_BAR_TYPE_SMALL:
+#ifdef CONFIG_64BIT
+                /* If the device supports 64bit addressing, then use BAR2 */
+                if (dma_mask > BAR2_PCI_ADDRESS) {
+                        result = physical + BAR2_PCI_ADDRESS;
+                        goto done;
+                }
+#endif
+                /* Continued below switch statement */
+                break;
+
+        default:
+                panic("dma_map_single: Invalid octeon_dma_bar_type\n");
+        }
+
+        /* Don't allow mapping to span multiple Bar entries. The hardware guys
+           won't guarantee that DMA across boards work */
+        if (unlikely((physical >> 22) != ((physical + size - 1) >> 22)))
+                panic("dma_map_single: "
+                      "Requested memory spans more than one Bar1 entry\n");
+
+        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
+                start_index = 31;
+        else if (unlikely(dma_mask < (1ul << 27)))
+                start_index = (dma_mask >> 22);
+        else
+                start_index = 31;
+
+        /* Only one processor can access the Bar register at once */
+        spin_lock_irqsave(&bar1_lock, flags);
+
+        /* Look through Bar1 for existing mapping that will work */
+        for (index = start_index; index >= 0; index--) {
+                if ((bar1_state[index].address_bits == physical >> 22) &&
+                    (bar1_state[index].ref_count)) {
+                        /* An existing mapping will work, use it */
+                        bar1_state[index].ref_count++;
+                        if (unlikely(bar1_state[index].ref_count < 0))
+                                panic("dma_map_single: "
+                                      "Bar1[%d] reference count overflowed\n",
+                                      (int) index);
+                        result = (index << 22) | (physical & ((1 << 22) - 1));
+                        /* Large BAR1 is offset at 2GB */
+                        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
+                                result += 2ul << 30;
+                        goto done_unlock;
+                }
+        }
+
+        /* No existing mappings, look for a free entry */
+        for (index = start_index; index >= 0; index--) {
+                if (unlikely(bar1_state[index].ref_count == 0)) {
+                        union cvmx_pci_bar1_indexx bar1_index;
+                        /* We have a free entry, use it */
+                        bar1_state[index].ref_count = 1;
+                        bar1_state[index].address_bits = physical >> 22;
+                        bar1_index.u32 = 0;
+                        /* Address bits[35:22] sent to L2C */
+                        bar1_index.s.addr_idx = physical >> 22;
+                        /* Don't put PCI accesses in L2. */
+                        bar1_index.s.ca = 1;
+                        /* Endian Swap Mode */
+                        bar1_index.s.end_swp = 1;
+                        /* Set '1' when the selected address range is valid. */
+                        bar1_index.s.addr_v = 1;
+                        octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
+                                           bar1_index.u32);
+                        /* An existing mapping will work, use it */
+                        result = (index << 22) | (physical & ((1 << 22) - 1));
+                        /* Large BAR1 is offset at 2GB */
+                        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
+                                result += 2ul << 30;
+                        goto done_unlock;
+                }
+        }
+
+        pr_err("dma_map_single: "
+               "Can't find empty BAR1 index for physical mapping 0x%llx\n",
+               (unsigned long long) physical);
+
+done_unlock:
+        spin_unlock_irqrestore(&bar1_lock, flags);
+done:
+        pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result);
+        return result;
+#endif
 }
 
 void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
 {
-        /* Without PCI/PCIe this function can be called for Octeon internal
-         * devices such as USB. These devices all support 64bit addressing */
+#ifndef CONFIG_PCI
+        /*
+         * Without PCI/PCIe this function can be called for Octeon internal
+         * devices such as USB. These devices all support 64bit addressing.
+         */
+        return;
+#else
+        unsigned long flags;
+        uint64_t index;
+
+        /*
+         * Platform devices, such as the internal USB, skip all
+         * translation and use Octeon physical addresses directly.
+         */
+        if (dev->bus == &platform_bus_type)
+                return;
+
+        switch (octeon_dma_bar_type) {
+        case OCTEON_DMA_BAR_TYPE_PCIE:
+                /* Nothing to do, all mappings are static */
+                goto done;
+
+        case OCTEON_DMA_BAR_TYPE_BIG:
+#ifdef CONFIG_64BIT
+                /* Nothing to do for addresses using BAR2 */
+                if (dma_addr >= BAR2_PCI_ADDRESS)
+                        goto done;
+#endif
+                if (unlikely(dma_addr < (4ul << 10)))
+                        panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
+                              dma_addr);
+                else if (dma_addr < (2ul << 30))
+                        /* Nothing to do for addresses using BAR0 */
+                        goto done;
+                else if (dma_addr < (2ul << 30) + (128ul << 20))
+                        /* Need to unmap, fall through */
+                        index = (dma_addr - (2ul << 30)) >> 22;
+                else if (dma_addr <
+                         (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))
+                        goto done;      /* Nothing to do for the rest of BAR1 */
+                else
+                        panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
+                              dma_addr);
+                /* Continued below switch statement */
+                break;
+
+        case OCTEON_DMA_BAR_TYPE_SMALL:
+#ifdef CONFIG_64BIT
+                /* Nothing to do for addresses using BAR2 */
+                if (dma_addr >= BAR2_PCI_ADDRESS)
+                        goto done;
+#endif
+                index = dma_addr >> 22;
+                /* Continued below switch statement */
+                break;
+
+        default:
+                panic("dma_unmap_single: Invalid octeon_dma_bar_type\n");
+        }
+
+        if (unlikely(index > 31))
+                panic("dma_unmap_single: "
+                      "Attempt to unmap an invalid address (0x%llx)\n",
+                      dma_addr);
+
+        spin_lock_irqsave(&bar1_lock, flags);
+        bar1_state[index].ref_count--;
+        if (bar1_state[index].ref_count == 0)
+                octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
+        else if (unlikely(bar1_state[index].ref_count < 0))
+                panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
+                      (int) index);
+        spin_unlock_irqrestore(&bar1_lock, flags);
+done:
+        pr_debug("dma_unmap_single 0x%llx\n", dma_addr);
         return;
+#endif
 }
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
index 80d6cb26766b..2fd66db6939e 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -11,3 +11,4 @@
 
 obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
 
+obj-$(CONFIG_PCI) += cvmx-helper-errata.o cvmx-helper-jtag.o
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
index 4f5a08b37ccd..25666da17b22 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -31,6 +31,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/module.h>
 
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-spinlock.h>
@@ -97,6 +98,33 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
         return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
 }
 
+void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
+                                     uint64_t max_addr, uint64_t align,
+                                     char *name)
+{
+        int64_t addr;
+
+        addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr,
+                                                  align, name, 0);
+        if (addr >= 0)
+                return cvmx_phys_to_ptr(addr);
+        else
+                return NULL;
+}
+
+void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
+                                       char *name)
+{
+    return cvmx_bootmem_alloc_named_range(size, address, address + size,
+                                          0, name);
+}
+
+void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *name)
+{
+    return cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name);
+}
+EXPORT_SYMBOL(cvmx_bootmem_alloc_named);
+
 int cvmx_bootmem_free_named(char *name)
 {
         return cvmx_bootmem_phy_named_block_free(name, 0);
@@ -106,6 +134,7 @@ struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name)
 {
         return cvmx_bootmem_phy_named_block_find(name, 0);
 }
+EXPORT_SYMBOL(cvmx_bootmem_find_named_block);
 
 void cvmx_bootmem_lock(void)
 {
@@ -584,3 +613,78 @@ int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags)
         cvmx_bootmem_unlock();
         return named_block_ptr != NULL; /* 0 on failure, 1 on success */
 }
+
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
+                                           uint64_t max_addr,
+                                           uint64_t alignment,
+                                           char *name,
+                                           uint32_t flags)
+{
+        int64_t addr_allocated;
+        struct cvmx_bootmem_named_block_desc *named_block_desc_ptr;
+
+#ifdef DEBUG
+        cvmx_dprintf("cvmx_bootmem_phy_named_block_alloc: size: 0x%llx, min: "
+                     "0x%llx, max: 0x%llx, align: 0x%llx, name: %s\n",
+                     (unsigned long long)size,
+                     (unsigned long long)min_addr,
+                     (unsigned long long)max_addr,
+                     (unsigned long long)alignment,
+                     name);
+#endif
+        if (cvmx_bootmem_desc->major_version != 3) {
+                cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: "
+                             "%d.%d at addr: %p\n",
+                             (int)cvmx_bootmem_desc->major_version,
+                             (int)cvmx_bootmem_desc->minor_version,
+                             cvmx_bootmem_desc);
+                return -1;
+        }
+
+        /*
+         * Take lock here, as name lookup/block alloc/name add need to
+         * be atomic.
+         */
+        if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+                cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+
+        /* Get pointer to first available named block descriptor */
+        named_block_desc_ptr =
+                cvmx_bootmem_phy_named_block_find(NULL,
+                                                  flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+        /*
+         * Check to see if name already in use, return error if name
+         * not available or no more room for blocks.
+         */
+        if (cvmx_bootmem_phy_named_block_find(name,
+                                              flags | CVMX_BOOTMEM_FLAG_NO_LOCKING) || !named_block_desc_ptr) {
+                if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+                        cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+                return -1;
+        }
+
+
+        /*
+         * Round size up to mult of minimum alignment bytes We need
+         * the actual size allocated to allow for blocks to be
+         * coallesced when they are freed.  The alloc routine does the
+         * same rounding up on all allocations.
+         */
+        size = __ALIGN_MASK(size, (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1));
+
+        addr_allocated = cvmx_bootmem_phy_alloc(size, min_addr, max_addr,
+                                                alignment,
+                                                flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
+        if (addr_allocated >= 0) {
+                named_block_desc_ptr->base_addr = addr_allocated;
+                named_block_desc_ptr->size = size;
+                strncpy(named_block_desc_ptr->name, name,
+                        cvmx_bootmem_desc->named_block_name_len);
+                named_block_desc_ptr->name[cvmx_bootmem_desc->named_block_name_len - 1] = 0;
+        }
+
+        if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
+                cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
+        return addr_allocated;
+}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
new file mode 100644
index 000000000000..868659e64d4a
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
@@ -0,0 +1,73 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * Fixes and workaround for Octeon chip errata. This file
+ * contains functions called by cvmx-helper to workaround known
+ * chip errata. For the most part, code doesn't need to call
+ * these functions directly.
+ *
+ */
+#include <linux/module.h>
+
+#include <asm/octeon/octeon.h>
+
+#include <asm/octeon/cvmx-helper-jtag.h>
+
+/**
+ * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
+ * 1 doesn't work properly. The following code disables 2nd order
+ * CDR for the specified QLM.
+ *
+ * @qlm:    QLM to disable 2nd order CDR for.
+ */
+void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
+{
+        int lane;
+        cvmx_helper_qlm_jtag_init();
+        /* We need to load all four lanes of the QLM, a total of 1072 bits */
+        for (lane = 0; lane < 4; lane++) {
+                /*
+                 * Each lane has 268 bits. We need to set
+                 * cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> =
+                 * 1. All other bits are zero. Bits go in LSB first,
+                 * so start off with the zeros for bits <63:0>.
+                 */
+                cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
+                /* cfg_cdr_incx<67:64>=3 */
+                cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
+                /* Zeros for bits <76:68> */
+                cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
+                /* cfg_cdr_secord<77>=1 */
+                cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
+                /* Zeros for bits <267:78> */
+                cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
+        }
+        cvmx_helper_qlm_jtag_update(qlm);
+}
+EXPORT_SYMBOL(__cvmx_helper_errata_qlm_disable_2nd_order_cdr);
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
new file mode 100644
index 000000000000..c1c54890bae0
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
@@ -0,0 +1,144 @@
+
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * Helper utilities for qlm_jtag.
+ *
+ */
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-helper-jtag.h>
+
+
+/**
+ * Initialize the internal QLM JTAG logic to allow programming
+ * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
+ * These functions should only be used at the direction of Cavium
+ * Networks. Programming incorrect values into the JTAG chain
+ * can cause chip damage.
+ */
+void cvmx_helper_qlm_jtag_init(void)
+{
+        union cvmx_ciu_qlm_jtgc jtgc;
+        uint32_t clock_div = 0;
+        uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000);
+        divisor = (divisor - 1) >> 2;
+        /* Convert the divisor into a power of 2 shift */
+        while (divisor) {
+                clock_div++;
+                divisor = divisor >> 1;
+        }
+
+        /*
+         * Clock divider for QLM JTAG operations.  eclk is divided by
+         * 2^(CLK_DIV + 2)
+         */
+        jtgc.u64 = 0;
+        jtgc.s.clk_div = clock_div;
+        jtgc.s.mux_sel = 0;
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+                jtgc.s.bypass = 0x3;
+        else
+                jtgc.s.bypass = 0xf;
+        cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
+        cvmx_read_csr(CVMX_CIU_QLM_JTGC);
+}
+
+/**
+ * Write up to 32bits into the QLM jtag chain. Bits are shifted
+ * into the MSB and out the LSB, so you should shift in the low
+ * order bits followed by the high order bits. The JTAG chain is
+ * 4 * 268 bits long, or 1072.
+ *
+ * @qlm:    QLM to shift value into
+ * @bits:   Number of bits to shift in (1-32).
+ * @data:   Data to shift in. Bit 0 enters the chain first, followed by
+ *               bit 1, etc.
+ *
+ * Returns The low order bits of the JTAG chain that shifted out of the
+ *         circle.
+ */
+uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
+{
+        union cvmx_ciu_qlm_jtgd jtgd;
+        jtgd.u64 = 0;
+        jtgd.s.shift = 1;
+        jtgd.s.shft_cnt = bits - 1;
+        jtgd.s.shft_reg = data;
+        if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+                jtgd.s.select = 1 << qlm;
+        cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
+        do {
+                jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
+        } while (jtgd.s.shift);
+        return jtgd.s.shft_reg >> (32 - bits);
+}
+
+/**
+ * Shift long sequences of zeros into the QLM JTAG chain. It is
+ * common to need to shift more than 32 bits of zeros into the
+ * chain. This function is a convience wrapper around
+ * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
+ * zeros at a time.
+ *
+ * @qlm:    QLM to shift zeros into
+ * @bits:
+ */
+void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
+{
+        while (bits > 0) {
+                int n = bits;
+                if (n > 32)
+                        n = 32;
+                cvmx_helper_qlm_jtag_shift(qlm, n, 0);
+                bits -= n;
+        }
+}
+
+/**
+ * Program the QLM JTAG chain into all lanes of the QLM. You must
+ * have already shifted in 268*4, or 1072 bits into the JTAG
+ * chain. Updating invalid values can possibly cause chip damage.
+ *
+ * @qlm:    QLM to program
+ */
+void cvmx_helper_qlm_jtag_update(int qlm)
+{
+        union cvmx_ciu_qlm_jtgd jtgd;
+
+        /* Update the new data */
+        jtgd.u64 = 0;
+        jtgd.s.update = 1;
+        if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+                jtgd.s.select = 1 << qlm;
+        cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
+        do {
+                jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
+        } while (jtgd.s.update);
+}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
index 4812370706a1..e5838890cba5 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
@@ -29,6 +29,7 @@
  * This module provides system/board/application information obtained
  * by the bootloader.
  */
+#include <linux/module.h>
 
 #include <asm/octeon/cvmx.h>
 #include <asm/octeon/cvmx-spinlock.h>
@@ -69,6 +70,7 @@ struct cvmx_sysinfo *cvmx_sysinfo_get(void)
 {
         return &(state.sysinfo);
 }
+EXPORT_SYMBOL(cvmx_sysinfo_get);
 
 /**
  * This function is used in non-simple executive environments (such as
diff --git a/arch/mips/cavium-octeon/msi.c b/arch/mips/cavium-octeon/msi.c
new file mode 100644
index 000000000000..964b03b75a8f
--- /dev/null
+++ b/arch/mips/cavium-octeon/msi.c
@@ -0,0 +1,288 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2007 Cavium Networks
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/msi.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-npi-defs.h>
+#include <asm/octeon/cvmx-pci-defs.h>
+#include <asm/octeon/cvmx-npei-defs.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+
+#include "pci-common.h"
+
+/*
+ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
+ * in use.
+ */
+static uint64_t msi_free_irq_bitmask;
+
+/*
+ * Each bit in msi_multiple_irq_bitmask tells that the device using
+ * this bit in msi_free_irq_bitmask is also using the next bit. This
+ * is used so we can disable all of the MSI interrupts when a device
+ * uses multiple.
+ */
+static uint64_t msi_multiple_irq_bitmask;
+
+/*
+ * This lock controls updates to msi_free_irq_bitmask and
+ * msi_multiple_irq_bitmask.
+ */
+static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
+
+
+/**
+ * Called when a driver request MSI interrupts instead of the
+ * legacy INT A-D. This routine will allocate multiple interrupts
+ * for MSI devices that support them. A device can override this by
+ * programming the MSI control bits [6:4] before calling
+ * pci_enable_msi().
+ *
+ * @param dev    Device requesting MSI interrupts
+ * @param desc   MSI descriptor
+ *
+ * Returns 0 on success.
+ */
+int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
+{
+        struct msi_msg msg;
+        uint16_t control;
+        int configured_private_bits;
+        int request_private_bits;
+        int irq;
+        int irq_step;
+        uint64_t search_mask;
+
+        /*
+         * Read the MSI config to figure out how many IRQs this device
+         * wants.  Most devices only want 1, which will give
+         * configured_private_bits and request_private_bits equal 0.
+         */
+        pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
+                             &control);
+
+        /*
+         * If the number of private bits has been configured then use
+         * that value instead of the requested number. This gives the
+         * driver the chance to override the number of interrupts
+         * before calling pci_enable_msi().
+         */
+        configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
+        if (configured_private_bits == 0) {
+                /* Nothing is configured, so use the hardware requested size */
+                request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
+        } else {
+                /*
+                 * Use the number of configured bits, assuming the
+                 * driver wanted to override the hardware request
+                 * value.
+                 */
+                request_private_bits = configured_private_bits;
+        }
+
+        /*
+         * The PCI 2.3 spec mandates that there are at most 32
+         * interrupts. If this device asks for more, only give it one.
+         */
+        if (request_private_bits > 5)
+                request_private_bits = 0;
+
+try_only_one:
+        /*
+         * The IRQs have to be aligned on a power of two based on the
+         * number being requested.
+         */
+        irq_step = 1 << request_private_bits;
+
+        /* Mask with one bit for each IRQ */
+        search_mask = (1 << irq_step) - 1;
+
+        /*
+         * We're going to search msi_free_irq_bitmask_lock for zero
+         * bits. This represents an MSI interrupt number that isn't in
+         * use.
+         */
+        spin_lock(&msi_free_irq_bitmask_lock);
+        for (irq = 0; irq < 64; irq += irq_step) {
+                if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
+                        msi_free_irq_bitmask |= search_mask << irq;
+                        msi_multiple_irq_bitmask |= (search_mask >> 1) << irq;
+                        break;
+                }
+        }
+        spin_unlock(&msi_free_irq_bitmask_lock);
+
+        /* Make sure the search for available interrupts didn't fail */
+        if (irq >= 64) {
+                if (request_private_bits) {
+                        pr_err("arch_setup_msi_irq: Unable to find %d free "
+                               "interrupts, trying just one",
+                               1 << request_private_bits);
+                        request_private_bits = 0;
+                        goto try_only_one;
+                } else
+                        panic("arch_setup_msi_irq: Unable to find a free MSI "
+                              "interrupt");
+        }
+
+        /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
+        irq += OCTEON_IRQ_MSI_BIT0;
+
+        switch (octeon_dma_bar_type) {
+        case OCTEON_DMA_BAR_TYPE_SMALL:
+                /* When not using big bar, Bar 0 is based at 128MB */
+                msg.address_lo =
+                        ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
+                msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
+        case OCTEON_DMA_BAR_TYPE_BIG:
+                /* When using big bar, Bar 0 is based at 0 */
+                msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
+                msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
+                break;
+        case OCTEON_DMA_BAR_TYPE_PCIE:
+                /* When using PCIe, Bar 0 is based at 0 */
+                /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
+                msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
+                msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
+                break;
+        default:
+                panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
+        }
+        msg.data = irq - OCTEON_IRQ_MSI_BIT0;
+
+        /* Update the number of IRQs the device has available to it */
+        control &= ~PCI_MSI_FLAGS_QSIZE;
+        control |= request_private_bits << 4;
+        pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
+                              control);
+
+        set_irq_msi(irq, desc);
+        write_msi_msg(irq, &msg);
+        return 0;
+}
+
+
+/**
+ * Called when a device no longer needs its MSI interrupts. All
+ * MSI interrupts for the device are freed.
+ *
+ * @irq:    The devices first irq number. There may be multple in sequence.
+ */
+void arch_teardown_msi_irq(unsigned int irq)
+{
+        int number_irqs;
+        uint64_t bitmask;
+
+        if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63))
+                panic("arch_teardown_msi_irq: Attempted to teardown illegal "
+                      "MSI interrupt (%d)", irq);
+        irq -= OCTEON_IRQ_MSI_BIT0;
+
+        /*
+         * Count the number of IRQs we need to free by looking at the
+         * msi_multiple_irq_bitmask. Each bit set means that the next
+         * IRQ is also owned by this device.
+         */
+        number_irqs = 0;
+        while ((irq+number_irqs < 64) &&
+               (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
+                number_irqs++;
+        number_irqs++;
+        /* Mask with one bit for each IRQ */
+        bitmask = (1 << number_irqs) - 1;
+        /* Shift the mask to the correct bit location */
+        bitmask <<= irq;
+        if ((msi_free_irq_bitmask & bitmask) != bitmask)
+                panic("arch_teardown_msi_irq: Attempted to teardown MSI "
+                      "interrupt (%d) not in use", irq);
+
+        /* Checks are done, update the in use bitmask */
+        spin_lock(&msi_free_irq_bitmask_lock);
+        msi_free_irq_bitmask &= ~bitmask;
+        msi_multiple_irq_bitmask &= ~bitmask;
+        spin_unlock(&msi_free_irq_bitmask_lock);
+}
+
+
+/**
+ * Called by the interrupt handling code when an MSI interrupt
+ * occurs.
+ *
+ * @param cpl
+ * @param dev_id
+ *
+ * @return
+ */
+static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
+{
+        uint64_t msi_bits;
+        int irq;
+
+        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
+                msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
+        else
+                msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
+        irq = fls64(msi_bits);
+        if (irq) {
+                irq += OCTEON_IRQ_MSI_BIT0 - 1;
+                if (irq_desc[irq].action) {
+                        do_IRQ(irq);
+                        return IRQ_HANDLED;
+                } else {
+                        pr_err("Spurious MSI interrupt %d\n", irq);
+                        if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
+                                /* These chips have PCIe */
+                                cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
+                                               1ull << (irq -
+                                                        OCTEON_IRQ_MSI_BIT0));
+                        } else {
+                                /* These chips have PCI */
+                                cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
+                                               1ull << (irq -
+                                                        OCTEON_IRQ_MSI_BIT0));
+                        }
+                }
+        }
+        return IRQ_NONE;
+}
+
+
+/**
+ * Initializes the MSI interrupt handling code
+ *
+ * @return
+ */
+int octeon_msi_initialize(void)
+{
+        int r;
+        if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
+                r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
+                                IRQF_SHARED,
+                                "MSI[0:63]", octeon_msi_interrupt);
+        } else if (octeon_is_pci_host()) {
+                r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
+                                IRQF_SHARED,
+                                "MSI[0:15]", octeon_msi_interrupt);
+                r += request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
+                                 IRQF_SHARED,
+                                 "MSI[16:31]", octeon_msi_interrupt);
+                r += request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
+                                 IRQF_SHARED,
+                                 "MSI[32:47]", octeon_msi_interrupt);
+                r += request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
+                                 IRQF_SHARED,
+                                 "MSI[48:63]", octeon_msi_interrupt);
+        }
+        return 0;
+}
+
+subsys_initcall(octeon_msi_initialize);
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index d3a0c8154bec..384f1842bfb1 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -7,9 +7,11 @@
  */
 #include <linux/irq.h>
 #include <linux/interrupt.h>
-#include <linux/hardirq.h>
+#include <linux/smp.h>
 
 #include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-npi-defs.h>
 
 DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
 DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
@@ -499,3 +501,62 @@ asmlinkage void plat_irq_dispatch(void)
                 }
         }
 }
+
+#ifdef CONFIG_HOTPLUG_CPU
+static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu)
+{
+       unsigned int isset;
+#ifdef CONFIG_SMP
+       int coreid = cpu_logical_map(cpu);
+#else
+        int coreid = cvmx_get_core_num();
+#endif
+        int bit = (irq < OCTEON_IRQ_WDOG0) ?
+                irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0;
+       if (irq < 64) {
+                isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) &
+                        (1ull << bit)) >> bit;
+       } else {
+               isset = (cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)) &
+                        (1ull << bit)) >> bit;
+       }
+       return isset;
+}
+
+void fixup_irqs(void)
+{
+       int irq;
+
+        for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
+                octeon_irq_core_disable_local(irq);
+
+        for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_GPIO15; irq++) {
+                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
+                        /* ciu irq migrates to next cpu */
+                        octeon_irq_chip_ciu0.disable(irq);
+                        octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
+                }
+        }
+
+#if 0
+        for (irq = OCTEON_IRQ_MBOX0; irq <= OCTEON_IRQ_MBOX1; irq++)
+                octeon_irq_mailbox_mask(irq);
+#endif
+        for (irq = OCTEON_IRQ_UART0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
+                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
+                        /* ciu irq migrates to next cpu */
+                        octeon_irq_chip_ciu0.disable(irq);
+                        octeon_irq_ciu0_set_affinity(irq, &cpu_online_map);
+                }
+        }
+
+        for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED135; irq++) {
+                if (is_irq_enabled_on_cpu(irq, smp_processor_id())) {
+                        /* ciu irq migrates to next cpu */
+                        octeon_irq_chip_ciu1.disable(irq);
+                        octeon_irq_ciu1_set_affinity(irq, &cpu_online_map);
+                }
+        }
+}
+
+#endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h
new file mode 100644
index 000000000000..0f7f84accf9a
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon_boot.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2004, 2005 Cavium Networks
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __OCTEON_BOOT_H__
+#define __OCTEON_BOOT_H__
+
+#include <linux/types.h>
+
+struct boot_init_vector {
+        uint32_t stack_addr;
+        uint32_t code_addr;
+        uint32_t app_start_func_addr;
+        uint32_t k0_val;
+        uint32_t flags;
+        uint32_t boot_info_addr;
+        uint32_t pad;
+        uint32_t pad2;
+};
+
+/* similar to bootloader's linux_app_boot_info but without global data */
+struct linux_app_boot_info {
+        uint32_t labi_signature;
+        uint32_t start_core0_addr;
+        uint32_t avail_coremask;
+        uint32_t pci_console_active;
+        uint32_t icache_prefetch_disable;
+        uint32_t InitTLBStart_addr;
+        uint32_t start_app_addr;
+        uint32_t cur_exception_base;
+        uint32_t no_mark_private_data;
+        uint32_t compact_flash_common_base_addr;
+        uint32_t compact_flash_attribute_base_addr;
+        uint32_t led_display_base_addr;
+};
+
+/* If not to copy a lot of bootloader's structures
+   here is only offset of requested member */
+#define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK    0x765c
+
+/* hardcoded in bootloader */
+#define  LABI_ADDR_IN_BOOTLOADER                         0x700
+
+#define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
+
+#define LABI_SIGNATURE 0xAABBCCDD
+
+/*  from uboot-headers/octeon_mem_map.h */
+#define EXCEPTION_BASE_INCR     (4 * 1024)
+                               /* Increment size for exception base addresses (4k minimum) */
+#define EXCEPTION_BASE_BASE     0
+#define BOOTLOADER_PRIV_DATA_BASE       (EXCEPTION_BASE_BASE + 0x800)
+#define BOOTLOADER_BOOT_VECTOR          (BOOTLOADER_PRIV_DATA_BASE)
+
+#endif /* __OCTEON_BOOT_H__ */
diff --git a/arch/mips/cavium-octeon/pci-common.c b/arch/mips/cavium-octeon/pci-common.c
new file mode 100644
index 000000000000..cd029f88da7f
--- /dev/null
+++ b/arch/mips/cavium-octeon/pci-common.c
@@ -0,0 +1,137 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2007 Cavium Networks
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include "pci-common.h"
+
+typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
+enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
+
+/**
+ * Map a PCI device to the appropriate interrupt line
+ *
+ * @param dev    The Linux PCI device structure for the device to map
+ * @param slot   The slot number for this device on __BUS 0__. Linux
+ *               enumerates through all the bridges and figures out the
+ *               slot on Bus 0 where this device eventually hooks to.
+ * @param pin    The PCI interrupt pin read from the device, then swizzled
+ *               as it goes through each bridge.
+ * @return Interrupt number for the device
+ */
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        if (octeon_pcibios_map_irq)
+                return octeon_pcibios_map_irq(dev, slot, pin);
+        else
+                panic("octeon_pcibios_map_irq doesn't point to a "
+                      "pcibios_map_irq() function");
+}
+
+
+/**
+ * Called to perform platform specific PCI setup
+ *
+ * @param dev
+ * @return
+ */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        uint16_t config;
+        uint32_t dconfig;
+        int pos;
+        /*
+         * Force the Cache line setting to 64 bytes. The standard
+         * Linux bus scan doesn't seem to set it. Octeon really has
+         * 128 byte lines, but Intel bridges get really upset if you
+         * try and set values above 64 bytes. Value is specified in
+         * 32bit words.
+         */
+        pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
+        /* Set latency timers for all devices */
+        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
+
+        /* Enable reporting System errors and parity errors on all devices */
+        /* Enable parity checking and error reporting */
+        pci_read_config_word(dev, PCI_COMMAND, &config);
+        config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
+        pci_write_config_word(dev, PCI_COMMAND, config);
+
+        if (dev->subordinate) {
+                /* Set latency timers on sub bridges */
+                pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
+                /* More bridge error detection */
+                pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
+                config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
+                pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
+        }
+
+        /* Enable the PCIe normal error reporting */
+        pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
+        if (pos) {
+                /* Update Device Control */
+                pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
+                /* Correctable Error Reporting */
+                config |= PCI_EXP_DEVCTL_CERE;
+                /* Non-Fatal Error Reporting */
+                config |= PCI_EXP_DEVCTL_NFERE;
+                /* Fatal Error Reporting */
+                config |= PCI_EXP_DEVCTL_FERE;
+                /* Unsupported Request */
+                config |= PCI_EXP_DEVCTL_URRE;
+                pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
+        }
+
+        /* Find the Advanced Error Reporting capability */
+        pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
+        if (pos) {
+                /* Clear Uncorrectable Error Status */
+                pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
+                                      &dconfig);
+                pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
+                                       dconfig);
+                /* Enable reporting of all uncorrectable errors */
+                /* Uncorrectable Error Mask - turned on bits disable errors */
+                pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
+                /*
+                 * Leave severity at HW default. This only controls if
+                 * errors are reported as uncorrectable or
+                 * correctable, not if the error is reported.
+                 */
+                /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
+                /* Clear Correctable Error Status */
+                pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
+                pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
+                /* Enable reporting of all correctable errors */
+                /* Correctable Error Mask - turned on bits disable errors */
+                pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
+                /* Advanced Error Capabilities */
+                pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
+                /* ECRC Generation Enable */
+                if (config & PCI_ERR_CAP_ECRC_GENC)
+                        config |= PCI_ERR_CAP_ECRC_GENE;
+                /* ECRC Check Enable */
+                if (config & PCI_ERR_CAP_ECRC_CHKC)
+                        config |= PCI_ERR_CAP_ECRC_CHKE;
+                pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
+                /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
+                /* Report all errors to the root complex */
+                pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
+                                       PCI_ERR_ROOT_CMD_COR_EN |
+                                       PCI_ERR_ROOT_CMD_NONFATAL_EN |
+                                       PCI_ERR_ROOT_CMD_FATAL_EN);
+                /* Clear the Root status register */
+                pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
+                pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
+        }
+
+        return 0;
+}
diff --git a/arch/mips/cavium-octeon/pci-common.h b/arch/mips/cavium-octeon/pci-common.h
new file mode 100644
index 000000000000..74ae79991e45
--- /dev/null
+++ b/arch/mips/cavium-octeon/pci-common.h
@@ -0,0 +1,39 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2007 Cavium Networks
+ */
+#ifndef __OCTEON_PCI_COMMON_H__
+#define __OCTEON_PCI_COMMON_H__
+
+#include <linux/pci.h>
+
+/* Some PCI cards require delays when accessing config space. */
+#define PCI_CONFIG_SPACE_DELAY 10000
+
+/* pcibios_map_irq() is defined inside pci-common.c. All it does is call the
+   Octeon specific version pointed to by this variable. This function needs to
+   change for PCI or PCIe based hosts */
+extern typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
+
+/* The following defines are only used when octeon_dma_bar_type =
+   OCTEON_DMA_BAR_TYPE_BIG */
+#define OCTEON_PCI_BAR1_HOLE_BITS 5
+#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
+
+enum octeon_dma_bar_type {
+        OCTEON_DMA_BAR_TYPE_INVALID,
+        OCTEON_DMA_BAR_TYPE_SMALL,
+        OCTEON_DMA_BAR_TYPE_BIG,
+        OCTEON_DMA_BAR_TYPE_PCIE
+};
+
+/**
+ * This is a variable to tell the DMA mapping system in dma-octeon.c
+ * how to map PCI DMA addresses.
+ */
+extern enum octeon_dma_bar_type octeon_dma_bar_type;
+
+#endif
diff --git a/arch/mips/cavium-octeon/pci.c b/arch/mips/cavium-octeon/pci.c
new file mode 100644
index 000000000000..67c0ff5e92f1
--- /dev/null
+++ b/arch/mips/cavium-octeon/pci.c
@@ -0,0 +1,568 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005-2007 Cavium Networks
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+
+#include <asm/time.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-npi-defs.h>
+#include <asm/octeon/cvmx-pci-defs.h>
+
+#include "pci-common.h"
+
+#define USE_OCTEON_INTERNAL_ARBITER
+
+/*
+ * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
+ * addresses. Use PCI endian swapping 1 so no address swapping is
+ * necessary. The Linux io routines will endian swap the data.
+ */
+#define OCTEON_PCI_IOSPACE_BASE     0x80011a0400000000ull
+#define OCTEON_PCI_IOSPACE_SIZE     (1ull<<32)
+
+/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
+#define OCTEON_PCI_MEMSPACE_OFFSET  (0x00011b0000000000ull)
+
+/**
+ * This is the bit decoding used for the Octeon PCI controller addresses
+ */
+union octeon_pci_address {
+        uint64_t u64;
+        struct {
+                uint64_t upper:2;
+                uint64_t reserved:13;
+                uint64_t io:1;
+                uint64_t did:5;
+                uint64_t subdid:3;
+                uint64_t reserved2:4;
+                uint64_t endian_swap:2;
+                uint64_t reserved3:10;
+                uint64_t bus:8;
+                uint64_t dev:5;
+                uint64_t func:3;
+                uint64_t reg:8;
+        } s;
+};
+
+/**
+ * Return the mapping of PCI device number to IRQ line. Each
+ * character in the return string represents the interrupt
+ * line for the device at that position. Device 1 maps to the
+ * first character, etc. The characters A-D are used for PCI
+ * interrupts.
+ *
+ * Returns PCI interrupt mapping
+ */
+const char *octeon_get_pci_interrupts(void)
+{
+        /*
+         * Returning an empty string causes the interrupts to be
+         * routed based on the PCI specification. From the PCI spec:
+         *
+         * INTA# of Device Number 0 is connected to IRQW on the system
+         * board.  (Device Number has no significance regarding being
+         * located on the system board or in a connector.) INTA# of
+         * Device Number 1 is connected to IRQX on the system
+         * board. INTA# of Device Number 2 is connected to IRQY on the
+         * system board. INTA# of Device Number 3 is connected to IRQZ
+         * on the system board. The table below describes how each
+         * agent's INTx# lines are connected to the system board
+         * interrupt lines. The following equation can be used to
+         * determine to which INTx# signal on the system board a given
+         * device's INTx# line(s) is connected.
+         *
+         * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0,
+         * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I =
+         * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
+         * INTD# = 3)
+         */
+        switch (octeon_bootinfo->board_type) {
+        case CVMX_BOARD_TYPE_NAO38:
+                /* This is really the NAC38 */
+                return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
+        case CVMX_BOARD_TYPE_THUNDER:
+                return "";
+        case CVMX_BOARD_TYPE_EBH3000:
+                return "";
+        case CVMX_BOARD_TYPE_EBH3100:
+        case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+        case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+                return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
+        case CVMX_BOARD_TYPE_BBGW_REF:
+                return "AABCD";
+        default:
+                return "";
+        }
+}
+
+/**
+ * Map a PCI device to the appropriate interrupt line
+ *
+ * @dev:    The Linux PCI device structure for the device to map
+ * @slot:   The slot number for this device on __BUS 0__. Linux
+ *               enumerates through all the bridges and figures out the
+ *               slot on Bus 0 where this device eventually hooks to.
+ * @pin:    The PCI interrupt pin read from the device, then swizzled
+ *               as it goes through each bridge.
+ * Returns Interrupt number for the device
+ */
+int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
+                                      u8 slot, u8 pin)
+{
+        int irq_num;
+        const char *interrupts;
+        int dev_num;
+
+        /* Get the board specific interrupt mapping */
+        interrupts = octeon_get_pci_interrupts();
+
+        dev_num = dev->devfn >> 3;
+        if (dev_num < strlen(interrupts))
+                irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
+                        OCTEON_IRQ_PCI_INT0;
+        else
+                irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
+        return irq_num;
+}
+
+
+/**
+ * Read a value from configuration space
+ *
+ */
+static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
+                              int reg, int size, u32 *val)
+{
+        union octeon_pci_address pci_addr;
+
+        pci_addr.u64 = 0;
+        pci_addr.s.upper = 2;
+        pci_addr.s.io = 1;
+        pci_addr.s.did = 3;
+        pci_addr.s.subdid = 1;
+        pci_addr.s.endian_swap = 1;
+        pci_addr.s.bus = bus->number;
+        pci_addr.s.dev = devfn >> 3;
+        pci_addr.s.func = devfn & 0x7;
+        pci_addr.s.reg = reg;
+
+#if PCI_CONFIG_SPACE_DELAY
+        udelay(PCI_CONFIG_SPACE_DELAY);
+#endif
+        switch (size) {
+        case 4:
+                *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
+                return PCIBIOS_SUCCESSFUL;
+        case 2:
+                *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
+                return PCIBIOS_SUCCESSFUL;
+        case 1:
+                *val = cvmx_read64_uint8(pci_addr.u64);
+                return PCIBIOS_SUCCESSFUL;
+        }
+        return PCIBIOS_FUNC_NOT_SUPPORTED;
+}
+
+
+/**
+ * Write a value to PCI configuration space
+ *
+ * @bus:
+ * @devfn:
+ * @reg:
+ * @size:
+ * @val:
+ * Returns
+ */
+static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
+                               int reg, int size, u32 val)
+{
+        union octeon_pci_address pci_addr;
+
+        pci_addr.u64 = 0;
+        pci_addr.s.upper = 2;
+        pci_addr.s.io = 1;
+        pci_addr.s.did = 3;
+        pci_addr.s.subdid = 1;
+        pci_addr.s.endian_swap = 1;
+        pci_addr.s.bus = bus->number;
+        pci_addr.s.dev = devfn >> 3;
+        pci_addr.s.func = devfn & 0x7;
+        pci_addr.s.reg = reg;
+
+#if PCI_CONFIG_SPACE_DELAY
+        udelay(PCI_CONFIG_SPACE_DELAY);
+#endif
+        switch (size) {
+        case 4:
+                cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
+                return PCIBIOS_SUCCESSFUL;
+        case 2:
+                cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
+                return PCIBIOS_SUCCESSFUL;
+        case 1:
+                cvmx_write64_uint8(pci_addr.u64, val);
+                return PCIBIOS_SUCCESSFUL;
+        }
+        return PCIBIOS_FUNC_NOT_SUPPORTED;
+}
+
+
+static struct pci_ops octeon_pci_ops = {
+        octeon_read_config,
+        octeon_write_config,
+};
+
+static struct resource octeon_pci_mem_resource = {
+        .start = 0,
+        .end = 0,
+        .name = "Octeon PCI MEM",
+        .flags = IORESOURCE_MEM,
+};
+
+/*
+ * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
+ * bridge
+ */
+static struct resource octeon_pci_io_resource = {
+        .start = 0x4000,
+        .end = OCTEON_PCI_IOSPACE_SIZE - 1,
+        .name = "Octeon PCI IO",
+        .flags = IORESOURCE_IO,
+};
+
+static struct pci_controller octeon_pci_controller = {
+        .pci_ops = &octeon_pci_ops,
+        .mem_resource = &octeon_pci_mem_resource,
+        .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
+        .io_resource = &octeon_pci_io_resource,
+        .io_offset = 0,
+        .io_map_base = OCTEON_PCI_IOSPACE_BASE,
+};
+
+
+/**
+ * Low level initialize the Octeon PCI controller
+ *
+ * Returns
+ */
+static void octeon_pci_initialize(void)
+{
+        union cvmx_pci_cfg01 cfg01;
+        union cvmx_npi_ctl_status ctl_status;
+        union cvmx_pci_ctl_status_2 ctl_status_2;
+        union cvmx_pci_cfg19 cfg19;
+        union cvmx_pci_cfg16 cfg16;
+        union cvmx_pci_cfg22 cfg22;
+        union cvmx_pci_cfg56 cfg56;
+
+        /* Reset the PCI Bus */
+        cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
+        cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+
+        udelay(2000);           /* Hold PCI reset for 2 ms */
+
+        ctl_status.u64 = 0;     /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
+        ctl_status.s.max_word = 1;
+        ctl_status.s.timer = 1;
+        cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
+
+        /* Deassert PCI reset and advertize PCX Host Mode Device Capability
+           (64b) */
+        cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
+        cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+
+        udelay(2000);           /* Wait 2 ms after deasserting PCI reset */
+
+        ctl_status_2.u32 = 0;
+        ctl_status_2.s.tsr_hwm = 1;     /* Initializes to 0.  Must be set
+                                           before any PCI reads. */
+        ctl_status_2.s.bar2pres = 1;    /* Enable BAR2 */
+        ctl_status_2.s.bar2_enb = 1;
+        ctl_status_2.s.bar2_cax = 1;    /* Don't use L2 */
+        ctl_status_2.s.bar2_esx = 1;
+        ctl_status_2.s.pmo_amod = 1;    /* Round robin priority */
+        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
+                /* BAR1 hole */
+                ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
+                ctl_status_2.s.bb1_siz = 1;  /* BAR1 is 2GB */
+                ctl_status_2.s.bb_ca = 1;    /* Don't use L2 with big bars */
+                ctl_status_2.s.bb_es = 1;    /* Big bar in byte swap mode */
+                ctl_status_2.s.bb1 = 1;      /* BAR1 is big */
+                ctl_status_2.s.bb0 = 1;      /* BAR0 is big */
+        }
+
+        octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
+        udelay(2000);           /* Wait 2 ms before doing PCI reads */
+
+        ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
+        pr_notice("PCI Status: %s %s-bit\n",
+                  ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
+                  ctl_status_2.s.ap_64ad ? "64" : "32");
+
+        if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                union cvmx_pci_cnt_reg cnt_reg_start;
+                union cvmx_pci_cnt_reg cnt_reg_end;
+                unsigned long cycles, pci_clock;
+
+                cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
+                cycles = read_c0_cvmcount();
+                udelay(1000);
+                cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
+                cycles = read_c0_cvmcount() - cycles;
+                pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
+                            (cycles / (mips_hpt_frequency / 1000000));
+                pr_notice("PCI Clock: %lu MHz\n", pci_clock);
+        }
+
+        /*
+         * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
+         * in PCI-X mode to allow four oustanding splits. Otherwise,
+         * should not change from its reset value. Don't write PCI_CFG19
+         * in PCI mode (0x82000001 reset value), write it to 0x82000004
+         * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
+         * MRBCM -> must be one.
+         */
+        if (ctl_status_2.s.ap_pcix) {
+                cfg19.u32 = 0;
+                /*
+                 * Target Delayed/Split request outstanding maximum
+                 * count. [1..31] and 0=32.  NOTE: If the user
+                 * programs these bits beyond the Designed Maximum
+                 * outstanding count, then the designed maximum table
+                 * depth will be used instead.  No additional
+                 * Deferred/Split transactions will be accepted if
+                 * this outstanding maximum count is
+                 * reached. Furthermore, no additional deferred/split
+                 * transactions will be accepted if the I/O delay/ I/O
+                 * Split Request outstanding maximum is reached.
+                 */
+                cfg19.s.tdomc = 4;
+                /*
+                 * Master Deferred Read Request Outstanding Max Count
+                 * (PCI only).  CR4C[26:24] Max SAC cycles MAX DAC
+                 * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
+                 * 5 2 110 6 3 111 7 3 For example, if these bits are
+                 * programmed to 100, the core can support 2 DAC
+                 * cycles, 4 SAC cycles or a combination of 1 DAC and
+                 * 2 SAC cycles. NOTE: For the PCI-X maximum
+                 * outstanding split transactions, refer to
+                 * CRE0[22:20].
+                 */
+                cfg19.s.mdrrmc = 2;
+                /*
+                 * Master Request (Memory Read) Byte Count/Byte Enable
+                 * select. 0 = Byte Enables valid. In PCI mode, a
+                 * burst transaction cannot be performed using Memory
+                 * Read command=4?h6. 1 = DWORD Byte Count valid
+                 * (default). In PCI Mode, the memory read byte
+                 * enables are automatically generated by the
+                 * core. Note: N3 Master Request transaction sizes are
+                 * always determined through the
+                 * am_attr[<35:32>|<7:0>] field.
+                 */
+                cfg19.s.mrbcm = 1;
+                octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
+        }
+
+
+        cfg01.u32 = 0;
+        cfg01.s.msae = 1;       /* Memory Space Access Enable */
+        cfg01.s.me = 1;         /* Master Enable */
+        cfg01.s.pee = 1;        /* PERR# Enable */
+        cfg01.s.see = 1;        /* System Error Enable */
+        cfg01.s.fbbe = 1;       /* Fast Back to Back Transaction Enable */
+
+        octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
+
+#ifdef USE_OCTEON_INTERNAL_ARBITER
+        /*
+         * When OCTEON is a PCI host, most systems will use OCTEON's
+         * internal arbiter, so must enable it before any PCI/PCI-X
+         * traffic can occur.
+         */
+        {
+                union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
+
+                pci_int_arb_cfg.u64 = 0;
+                pci_int_arb_cfg.s.en = 1;       /* Internal arbiter enable */
+                cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
+        }
+#endif                          /* USE_OCTEON_INTERNAL_ARBITER */
+
+        /*
+         * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE,
+         * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
+         * 1..7.
+         */
+        cfg16.u32 = 0;
+        cfg16.s.mltd = 1;       /* Master Latency Timer Disable */
+        octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
+
+        /*
+         * Should be written to 0x4ff00. MTTV -> must be zero.
+         * FLUSH -> must be 1. MRV -> should be 0xFF.
+         */
+        cfg22.u32 = 0;
+        /* Master Retry Value [1..255] and 0=infinite */
+        cfg22.s.mrv = 0xff;
+        /*
+         * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
+         * N3K operation.
+         */
+        cfg22.s.flush = 1;
+        octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
+
+        /*
+         * MOST Indicates the maximum number of outstanding splits (in -1
+         * notation) when OCTEON is in PCI-X mode.  PCI-X performance is
+         * affected by the MOST selection.  Should generally be written
+         * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
+         * depending on the desired MOST of 3, 2, 1, or 0, respectively.
+         */
+        cfg56.u32 = 0;
+        cfg56.s.pxcid = 7;      /* RO - PCI-X Capability ID */
+        cfg56.s.ncp = 0xe8;     /* RO - Next Capability Pointer */
+        cfg56.s.dpere = 1;      /* Data Parity Error Recovery Enable */
+        cfg56.s.roe = 1;        /* Relaxed Ordering Enable */
+        cfg56.s.mmbc = 1;       /* Maximum Memory Byte Count
+                                   [0=512B,1=1024B,2=2048B,3=4096B] */
+        cfg56.s.most = 3;       /* Maximum outstanding Split transactions [0=1
+                                   .. 7=32] */
+
+        octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
+
+        /*
+         * Affects PCI performance when OCTEON services reads to its
+         * BAR1/BAR2. Refer to Section 10.6.1.  The recommended values are
+         * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
+         * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
+         * these values need to be changed so they won't possibly prefetch off
+         * of the end of memory if PCI is DMAing a buffer at the end of
+         * memory. Note that these values differ from their reset values.
+         */
+        octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
+        octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
+        octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
+}
+
+
+/**
+ * Initialize the Octeon PCI controller
+ *
+ * Returns
+ */
+static int __init octeon_pci_setup(void)
+{
+        union cvmx_npi_mem_access_subidx mem_access;
+        int index;
+
+        /* Only these chips have PCI */
+        if (octeon_has_feature(OCTEON_FEATURE_PCIE))
+                return 0;
+
+        /* Point pcibios_map_irq() to the PCI version of it */
+        octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
+
+        /* Only use the big bars on chips that support it */
+        if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
+            OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
+            OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
+                octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
+        else
+                octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
+
+        /* PCI I/O and PCI MEM values */
+        set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
+        ioport_resource.start = 0;
+        ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
+        if (!octeon_is_pci_host()) {
+                pr_notice("Not in host mode, PCI Controller not initialized\n");
+                return 0;
+        }
+
+        pr_notice("%s Octeon big bar support\n",
+                  (octeon_dma_bar_type ==
+                  OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
+
+        octeon_pci_initialize();
+
+        mem_access.u64 = 0;
+        mem_access.s.esr = 1;   /* Endian-Swap on read. */
+        mem_access.s.esw = 1;   /* Endian-Swap on write. */
+        mem_access.s.nsr = 0;   /* No-Snoop on read. */
+        mem_access.s.nsw = 0;   /* No-Snoop on write. */
+        mem_access.s.ror = 0;   /* Relax Read on read. */
+        mem_access.s.row = 0;   /* Relax Order on write. */
+        mem_access.s.ba = 0;    /* PCI Address bits [63:36]. */
+        cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
+
+        /*
+         * Remap the Octeon BAR 2 above all 32 bit devices
+         * (0x8000000000ul).  This is done here so it is remapped
+         * before the readl()'s below. We don't want BAR2 overlapping
+         * with BAR0/BAR1 during these reads.
+         */
+        octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0);
+        octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80);
+
+        /* Disable the BAR1 movable mappings */
+        for (index = 0; index < 32; index++)
+                octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
+
+        if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
+                /* Remap the Octeon BAR 0 to 0-2GB */
+                octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
+                octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
+
+                /*
+                 * Remap the Octeon BAR 1 to map 2GB-4GB (minus the
+                 * BAR 1 hole).
+                 */
+                octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
+                octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
+
+                /* Devices go after BAR1 */
+                octeon_pci_mem_resource.start =
+                        OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
+                        (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
+                octeon_pci_mem_resource.end =
+                        octeon_pci_mem_resource.start + (1ul << 30);
+        } else {
+                /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */
+                octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
+                octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
+
+                /* Remap the Octeon BAR 1 to map 0-128MB */
+                octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
+                octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
+
+                /* Devices go after BAR0 */
+                octeon_pci_mem_resource.start =
+                        OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
+                        (4ul << 10);
+                octeon_pci_mem_resource.end =
+                        octeon_pci_mem_resource.start + (1ul << 30);
+        }
+
+        register_pci_controller(&octeon_pci_controller);
+
+        /*
+         * Clear any errors that might be pending from before the bus
+         * was setup properly.
+         */
+        cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
+        return 0;
+}
+
+arch_initcall(octeon_pci_setup);
diff --git a/arch/mips/cavium-octeon/pcie.c b/arch/mips/cavium-octeon/pcie.c
new file mode 100644
index 000000000000..49d14081b3b5
--- /dev/null
+++ b/arch/mips/cavium-octeon/pcie.c
@@ -0,0 +1,1370 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007, 2008 Cavium Networks
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-npei-defs.h>
+#include <asm/octeon/cvmx-pciercx-defs.h>
+#include <asm/octeon/cvmx-pescx-defs.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-helper-errata.h>
+
+#include "pci-common.h"
+
+union cvmx_pcie_address {
+        uint64_t u64;
+        struct {
+                uint64_t upper:2;       /* Normally 2 for XKPHYS */
+                uint64_t reserved_49_61:13;     /* Must be zero */
+                uint64_t io:1;  /* 1 for IO space access */
+                uint64_t did:5; /* PCIe DID = 3 */
+                uint64_t subdid:3;      /* PCIe SubDID = 1 */
+                uint64_t reserved_36_39:4;      /* Must be zero */
+                uint64_t es:2;  /* Endian swap = 1 */
+                uint64_t port:2;        /* PCIe port 0,1 */
+                uint64_t reserved_29_31:3;      /* Must be zero */
+                /*
+                 * Selects the type of the configuration request (0 = type 0,
+                 * 1 = type 1).
+                 */
+                uint64_t ty:1;
+                /* Target bus number sent in the ID in the request. */
+                uint64_t bus:8;
+                /*
+                 * Target device number sent in the ID in the
+                 * request. Note that Dev must be zero for type 0
+                 * configuration requests.
+                 */
+                uint64_t dev:5;
+                /* Target function number sent in the ID in the request. */
+                uint64_t func:3;
+                /*
+                 * Selects a register in the configuration space of
+                 * the target.
+                 */
+                uint64_t reg:12;
+        } config;
+        struct {
+                uint64_t upper:2;       /* Normally 2 for XKPHYS */
+                uint64_t reserved_49_61:13;     /* Must be zero */
+                uint64_t io:1;  /* 1 for IO space access */
+                uint64_t did:5; /* PCIe DID = 3 */
+                uint64_t subdid:3;      /* PCIe SubDID = 2 */
+                uint64_t reserved_36_39:4;      /* Must be zero */
+                uint64_t es:2;  /* Endian swap = 1 */
+                uint64_t port:2;        /* PCIe port 0,1 */
+                uint64_t address:32;    /* PCIe IO address */
+        } io;
+        struct {
+                uint64_t upper:2;       /* Normally 2 for XKPHYS */
+                uint64_t reserved_49_61:13;     /* Must be zero */
+                uint64_t io:1;  /* 1 for IO space access */
+                uint64_t did:5; /* PCIe DID = 3 */
+                uint64_t subdid:3;      /* PCIe SubDID = 3-6 */
+                uint64_t reserved_36_39:4;      /* Must be zero */
+                uint64_t address:36;    /* PCIe Mem address */
+        } mem;
+};
+
+/**
+ * Return the Core virtual base address for PCIe IO access. IOs are
+ * read/written as an offset from this address.
+ *
+ * @pcie_port: PCIe port the IO is for
+ *
+ * Returns 64bit Octeon IO base address for read/write
+ */
+static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
+{
+        union cvmx_pcie_address pcie_addr;
+        pcie_addr.u64 = 0;
+        pcie_addr.io.upper = 0;
+        pcie_addr.io.io = 1;
+        pcie_addr.io.did = 3;
+        pcie_addr.io.subdid = 2;
+        pcie_addr.io.es = 1;
+        pcie_addr.io.port = pcie_port;
+        return pcie_addr.u64;
+}
+
+/**
+ * Size of the IO address region returned at address
+ * cvmx_pcie_get_io_base_address()
+ *
+ * @pcie_port: PCIe port the IO is for
+ *
+ * Returns Size of the IO window
+ */
+static inline uint64_t cvmx_pcie_get_io_size(int pcie_port)
+{
+        return 1ull << 32;
+}
+
+/**
+ * Return the Core virtual base address for PCIe MEM access. Memory is
+ * read/written as an offset from this address.
+ *
+ * @pcie_port: PCIe port the IO is for
+ *
+ * Returns 64bit Octeon IO base address for read/write
+ */
+static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
+{
+        union cvmx_pcie_address pcie_addr;
+        pcie_addr.u64 = 0;
+        pcie_addr.mem.upper = 0;
+        pcie_addr.mem.io = 1;
+        pcie_addr.mem.did = 3;
+        pcie_addr.mem.subdid = 3 + pcie_port;
+        return pcie_addr.u64;
+}
+
+/**
+ * Size of the Mem address region returned at address
+ * cvmx_pcie_get_mem_base_address()
+ *
+ * @pcie_port: PCIe port the IO is for
+ *
+ * Returns Size of the Mem window
+ */
+static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
+{
+        return 1ull << 36;
+}
+
+/**
+ * Read a PCIe config space register indirectly. This is used for
+ * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
+ *
+ * @pcie_port:  PCIe port to read from
+ * @cfg_offset: Address to read
+ *
+ * Returns Value read
+ */
+static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
+{
+        union cvmx_pescx_cfg_rd pescx_cfg_rd;
+        pescx_cfg_rd.u64 = 0;
+        pescx_cfg_rd.s.addr = cfg_offset;
+        cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
+        pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
+        return pescx_cfg_rd.s.data;
+}
+
+/**
+ * Write a PCIe config space register indirectly. This is used for
+ * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
+ *
+ * @pcie_port:  PCIe port to write to
+ * @cfg_offset: Address to write
+ * @val:        Value to write
+ */
+static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
+                                 uint32_t val)
+{
+        union cvmx_pescx_cfg_wr pescx_cfg_wr;
+        pescx_cfg_wr.u64 = 0;
+        pescx_cfg_wr.s.addr = cfg_offset;
+        pescx_cfg_wr.s.data = val;
+        cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
+}
+
+/**
+ * Build a PCIe config space request address for a device
+ *
+ * @pcie_port: PCIe port to access
+ * @bus:       Sub bus
+ * @dev:       Device ID
+ * @fn:        Device sub function
+ * @reg:       Register to access
+ *
+ * Returns 64bit Octeon IO address
+ */
+static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
+                                                     int dev, int fn, int reg)
+{
+        union cvmx_pcie_address pcie_addr;
+        union cvmx_pciercx_cfg006 pciercx_cfg006;
+
+        pciercx_cfg006.u32 =
+            cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
+        if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
+                return 0;
+
+        pcie_addr.u64 = 0;
+        pcie_addr.config.upper = 2;
+        pcie_addr.config.io = 1;
+        pcie_addr.config.did = 3;
+        pcie_addr.config.subdid = 1;
+        pcie_addr.config.es = 1;
+        pcie_addr.config.port = pcie_port;
+        pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
+        pcie_addr.config.bus = bus;
+        pcie_addr.config.dev = dev;
+        pcie_addr.config.func = fn;
+        pcie_addr.config.reg = reg;
+        return pcie_addr.u64;
+}
+
+/**
+ * Read 8bits from a Device's config space
+ *
+ * @pcie_port: PCIe port the device is on
+ * @bus:       Sub bus
+ * @dev:       Device ID
+ * @fn:        Device sub function
+ * @reg:       Register to access
+ *
+ * Returns Result of the read
+ */
+static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
+                                      int fn, int reg)
+{
+        uint64_t address =
+            __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+        if (address)
+                return cvmx_read64_uint8(address);
+        else
+                return 0xff;
+}
+
+/**
+ * Read 16bits from a Device's config space
+ *
+ * @pcie_port: PCIe port the device is on
+ * @bus:       Sub bus
+ * @dev:       Device ID
+ * @fn:        Device sub function
+ * @reg:       Register to access
+ *
+ * Returns Result of the read
+ */
+static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
+                                        int fn, int reg)
+{
+        uint64_t address =
+            __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+        if (address)
+                return le16_to_cpu(cvmx_read64_uint16(address));
+        else
+                return 0xffff;
+}
+
+/**
+ * Read 32bits from a Device's config space
+ *
+ * @pcie_port: PCIe port the device is on
+ * @bus:       Sub bus
+ * @dev:       Device ID
+ * @fn:        Device sub function
+ * @reg:       Register to access
+ *
+ * Returns Result of the read
+ */
+static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
+                                        int fn, int reg)
+{
+        uint64_t address =
+            __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+        if (address)
+                return le32_to_cpu(cvmx_read64_uint32(address));
+        else
+                return 0xffffffff;
+}
+
+/**
+ * Write 8bits to a Device's config space
+ *
+ * @pcie_port: PCIe port the device is on
+ * @bus:       Sub bus
+ * @dev:       Device ID
+ * @fn:        Device sub function
+ * @reg:       Register to access
+ * @val:       Value to write
+ */
+static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
+                                    int reg, uint8_t val)
+{
+        uint64_t address =
+            __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+        if (address)
+                cvmx_write64_uint8(address, val);
+}
+
+/**
+ * Write 16bits to a Device's config space
+ *
+ * @pcie_port: PCIe port the device is on
+ * @bus:       Sub bus
+ * @dev:       Device ID
+ * @fn:        Device sub function
+ * @reg:       Register to access
+ * @val:       Value to write
+ */
+static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
+                                     int reg, uint16_t val)
+{
+        uint64_t address =
+            __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+        if (address)
+                cvmx_write64_uint16(address, cpu_to_le16(val));
+}
+
+/**
+ * Write 32bits to a Device's config space
+ *
+ * @pcie_port: PCIe port the device is on
+ * @bus:       Sub bus
+ * @dev:       Device ID
+ * @fn:        Device sub function
+ * @reg:       Register to access
+ * @val:       Value to write
+ */
+static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
+                                     int reg, uint32_t val)
+{
+        uint64_t address =
+            __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
+        if (address)
+                cvmx_write64_uint32(address, cpu_to_le32(val));
+}
+
+/**
+ * Initialize the RC config space CSRs
+ *
+ * @pcie_port: PCIe port to initialize
+ */
+static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
+{
+        union cvmx_pciercx_cfg030 pciercx_cfg030;
+        union cvmx_npei_ctl_status2 npei_ctl_status2;
+        union cvmx_pciercx_cfg070 pciercx_cfg070;
+        union cvmx_pciercx_cfg001 pciercx_cfg001;
+        union cvmx_pciercx_cfg032 pciercx_cfg032;
+        union cvmx_pciercx_cfg006 pciercx_cfg006;
+        union cvmx_pciercx_cfg008 pciercx_cfg008;
+        union cvmx_pciercx_cfg009 pciercx_cfg009;
+        union cvmx_pciercx_cfg010 pciercx_cfg010;
+        union cvmx_pciercx_cfg011 pciercx_cfg011;
+        union cvmx_pciercx_cfg035 pciercx_cfg035;
+        union cvmx_pciercx_cfg075 pciercx_cfg075;
+        union cvmx_pciercx_cfg034 pciercx_cfg034;
+
+        /* Max Payload Size (PCIE*_CFG030[MPS]) */
+        /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
+        /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
+        /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
+        pciercx_cfg030.u32 =
+                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
+        /*
+         * Max payload size = 128 bytes for best Octeon DMA
+         * performance.
+         */
+        pciercx_cfg030.s.mps = 0;
+        /*
+         * Max read request size = 128 bytes for best Octeon DMA
+         * performance.
+         */
+        pciercx_cfg030.s.mrrs = 0;
+        /* Enable relaxed ordering. */
+        pciercx_cfg030.s.ro_en = 1;
+        /* Enable no snoop. */
+        pciercx_cfg030.s.ns_en = 1;
+        /* Correctable error reporting enable. */
+        pciercx_cfg030.s.ce_en = 1;
+        /* Non-fatal error reporting enable. */
+        pciercx_cfg030.s.nfe_en = 1;
+        /* Fatal error reporting enable. */
+        pciercx_cfg030.s.fe_en = 1;
+        /* Unsupported request reporting enable. */
+        pciercx_cfg030.s.ur_en = 1;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
+                             pciercx_cfg030.u32);
+
+        /*
+         * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
+         * PCIE*_CFG030[MPS]
+         *
+         * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
+         * exceed PCIE*_CFG030[MRRS].
+         */
+        npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
+        /* Max payload size = 128 bytes for best Octeon DMA performance */
+        npei_ctl_status2.s.mps = 0;
+        /* Max read request size = 128 bytes for best Octeon DMA performance */
+        npei_ctl_status2.s.mrrs = 0;
+        cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
+
+        /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
+        pciercx_cfg070.u32 =
+                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
+        pciercx_cfg070.s.ge = 1;        /* ECRC generation enable. */
+        pciercx_cfg070.s.ce = 1;        /* ECRC check enable. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
+                             pciercx_cfg070.u32);
+
+        /*
+         * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
+         * always be set.
+         *
+         * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
+         * Message Enable (PCIE*_CFG001[SEE])
+         */
+        pciercx_cfg001.u32 =
+                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
+        pciercx_cfg001.s.msae = 1;      /* Memory space enable. */
+        pciercx_cfg001.s.me = 1;        /* Bus master enable. */
+        pciercx_cfg001.s.i_dis = 1;     /* INTx assertion disable. */
+        pciercx_cfg001.s.see = 1;       /* SERR# enable */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
+                        pciercx_cfg001.u32);
+
+        /* Advanced Error Recovery Message Enables */
+        /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
+        /* Use CVMX_PCIERCX_CFG067 hardware default */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
+
+        /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
+        pciercx_cfg032.u32 =
+                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+        pciercx_cfg032.s.aslpc = 0;     /* Active state Link PM control. */
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
+                             pciercx_cfg032.u32);
+
+        /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
+
+        /*
+         * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
+         * cvmx_pcie_rc_initialize_link()
+         *
+         * Primary Bus Number (PCIERCn_CFG006[PBNUM])
+         *
+         * We set the primary bus number to 1 so IDT bridges are
+         * happy. They don't like zero.
+         */
+        pciercx_cfg006.u32 = 0;
+        pciercx_cfg006.s.pbnum = 1;
+        pciercx_cfg006.s.sbnum = 1;
+        pciercx_cfg006.s.subbnum = 1;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
+                             pciercx_cfg006.u32);
+
+        /*
+         * Memory-mapped I/O BAR (PCIERCn_CFG008)
+         * Most applications should disable the memory-mapped I/O BAR by
+         * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
+         */
+        pciercx_cfg008.u32 = 0;
+        pciercx_cfg008.s.mb_addr = 0x100;
+        pciercx_cfg008.s.ml_addr = 0;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
+                             pciercx_cfg008.u32);
+
+        /*
+         * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
+         * Most applications should disable the prefetchable BAR by setting
+         * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
+         * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
+         */
+        pciercx_cfg009.u32 =
+                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
+        pciercx_cfg010.u32 =
+                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
+        pciercx_cfg011.u32 =
+                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
+        pciercx_cfg009.s.lmem_base = 0x100;
+        pciercx_cfg009.s.lmem_limit = 0;
+        pciercx_cfg010.s.umem_base = 0x100;
+        pciercx_cfg011.s.umem_limit = 0;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
+                             pciercx_cfg009.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
+                             pciercx_cfg010.u32);
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
+                             pciercx_cfg011.u32);
+
+        /*
+         * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
+         * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
+         */
+        pciercx_cfg035.u32 =
+                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
+        /* System error on correctable error enable. */
+        pciercx_cfg035.s.secee = 1;
+        /* System error on fatal error enable. */
+        pciercx_cfg035.s.sefee = 1;
+        /* System error on non-fatal error enable. */
+        pciercx_cfg035.s.senfee = 1;
+        /* PME interrupt enable. */
+        pciercx_cfg035.s.pmeie = 1;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
+                             pciercx_cfg035.u32);
+
+        /*
+         * Advanced Error Recovery Interrupt Enables
+         * (PCIERCn_CFG075[CERE,NFERE,FERE])
+         */
+        pciercx_cfg075.u32 =
+                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
+        /* Correctable error reporting enable. */
+        pciercx_cfg075.s.cere = 1;
+        /* Non-fatal error reporting enable. */
+        pciercx_cfg075.s.nfere = 1;
+        /* Fatal error reporting enable. */
+        pciercx_cfg075.s.fere = 1;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
+                             pciercx_cfg075.u32);
+
+        /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
+         * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
+         */
+        pciercx_cfg034.u32 =
+                cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
+        /* Hot-plug interrupt enable. */
+        pciercx_cfg034.s.hpint_en = 1;
+        /* Data Link Layer state changed enable */
+        pciercx_cfg034.s.dlls_en = 1;
+        /* Command completed interrupt enable. */
+        pciercx_cfg034.s.ccint_en = 1;
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
+                             pciercx_cfg034.u32);
+}
+
+/**
+ * Initialize a host mode PCIe link. This function takes a PCIe
+ * port from reset to a link up state. Software can then begin
+ * configuring the rest of the link.
+ *
+ * @pcie_port: PCIe port to initialize
+ *
+ * Returns Zero on success
+ */
+static int __cvmx_pcie_rc_initialize_link(int pcie_port)
+{
+        uint64_t start_cycle;
+        union cvmx_pescx_ctl_status pescx_ctl_status;
+        union cvmx_pciercx_cfg452 pciercx_cfg452;
+        union cvmx_pciercx_cfg032 pciercx_cfg032;
+        union cvmx_pciercx_cfg448 pciercx_cfg448;
+
+        /* Set the lane width */
+        pciercx_cfg452.u32 =
+            cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
+        pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
+        if (pescx_ctl_status.s.qlm_cfg == 0) {
+                /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
+                pciercx_cfg452.s.lme = 0xf;
+        } else {
+                /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
+                pciercx_cfg452.s.lme = 0x7;
+        }
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
+                             pciercx_cfg452.u32);
+
+        /*
+         * CN52XX pass 1.x has an errata where length mismatches on UR
+         * responses can cause bus errors on 64bit memory
+         * reads. Turning off length error checking fixes this.
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
+                union cvmx_pciercx_cfg455 pciercx_cfg455;
+                pciercx_cfg455.u32 =
+                    cvmx_pcie_cfgx_read(pcie_port,
+                                        CVMX_PCIERCX_CFG455(pcie_port));
+                pciercx_cfg455.s.m_cpl_len_err = 1;
+                cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
+                                     pciercx_cfg455.u32);
+        }
+
+        /* Lane swap needs to be manually enabled for CN52XX */
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
+                pescx_ctl_status.s.lane_swp = 1;
+                cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
+                               pescx_ctl_status.u64);
+        }
+
+        /* Bring up the link */
+        pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
+        pescx_ctl_status.s.lnk_enb = 1;
+        cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
+
+        /*
+         * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
+         * be disabled.
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
+                __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
+
+        /* Wait for the link to come up */
+        cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
+        start_cycle = cvmx_get_cycle();
+        do {
+                if (cvmx_get_cycle() - start_cycle >
+                    2 * cvmx_sysinfo_get()->cpu_clock_hz) {
+                        cvmx_dprintf("PCIe: Port %d link timeout\n",
+                                     pcie_port);
+                        return -1;
+                }
+                cvmx_wait(10000);
+                pciercx_cfg032.u32 =
+                    cvmx_pcie_cfgx_read(pcie_port,
+                                        CVMX_PCIERCX_CFG032(pcie_port));
+        } while (pciercx_cfg032.s.dlla == 0);
+
+        /* Display the link status */
+        cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
+                     pciercx_cfg032.s.nlw);
+
+        /*
+         * Update the Replay Time Limit. Empirically, some PCIe
+         * devices take a little longer to respond than expected under
+         * load. As a workaround for this we configure the Replay Time
+         * Limit to the value expected for a 512 byte MPS instead of
+         * our actual 256 byte MPS. The numbers below are directly
+         * from the PCIe spec table 3-4.
+         */
+        pciercx_cfg448.u32 =
+            cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
+        switch (pciercx_cfg032.s.nlw) {
+        case 1:         /* 1 lane */
+                pciercx_cfg448.s.rtl = 1677;
+                break;
+        case 2:         /* 2 lanes */
+                pciercx_cfg448.s.rtl = 867;
+                break;
+        case 4:         /* 4 lanes */
+                pciercx_cfg448.s.rtl = 462;
+                break;
+        case 8:         /* 8 lanes */
+                pciercx_cfg448.s.rtl = 258;
+                break;
+        }
+        cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
+                             pciercx_cfg448.u32);
+
+        return 0;
+}
+
+/**
+ * Initialize a PCIe port for use in host(RC) mode. It doesn't
+ * enumerate the bus.
+ *
+ * @pcie_port: PCIe port to initialize
+ *
+ * Returns Zero on success
+ */
+static int cvmx_pcie_rc_initialize(int pcie_port)
+{
+        int i;
+        union cvmx_ciu_soft_prst ciu_soft_prst;
+        union cvmx_pescx_bist_status pescx_bist_status;
+        union cvmx_pescx_bist_status2 pescx_bist_status2;
+        union cvmx_npei_ctl_status npei_ctl_status;
+        union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
+        union cvmx_npei_mem_access_subidx mem_access_subid;
+        union cvmx_npei_dbg_data npei_dbg_data;
+        union cvmx_pescx_ctl_status2 pescx_ctl_status2;
+
+        /*
+         * Make sure we aren't trying to setup a target mode interface
+         * in host mode.
+         */
+        npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
+        if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
+                cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
+                             "on port0, but port0 is not in host mode\n");
+                return -1;
+        }
+
+        /*
+         * Make sure a CN52XX isn't trying to bring up port 1 when it
+         * is disabled.
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+                if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
+                        cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
+                                     "called on port1, but port1 is "
+                                     "disabled\n");
+                        return -1;
+                }
+        }
+
+        /*
+         * PCIe switch arbitration mode. '0' == fixed priority NPEI,
+         * PCIe0, then PCIe1. '1' == round robin.
+         */
+        npei_ctl_status.s.arb = 1;
+        /* Allow up to 0x20 config retries */
+        npei_ctl_status.s.cfg_rtry = 0x20;
+        /*
+         * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
+         * don't reset.
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
+                npei_ctl_status.s.p0_ntags = 0x20;
+                npei_ctl_status.s.p1_ntags = 0x20;
+        }
+        cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
+
+        /* Bring the PCIe out of reset */
+        if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
+                /*
+                 * The EBH5200 board swapped the PCIe reset lines on
+                 * the board. As a workaround for this bug, we bring
+                 * both PCIe ports out of reset at the same time
+                 * instead of on separate calls. So for port 0, we
+                 * bring both out of reset and do nothing on port 1.
+                 */
+                if (pcie_port == 0) {
+                        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+                        /*
+                         * After a chip reset the PCIe will also be in
+                         * reset. If it isn't, most likely someone is
+                         * trying to init it again without a proper
+                         * PCIe reset.
+                         */
+                        if (ciu_soft_prst.s.soft_prst == 0) {
+                                /* Reset the ports */
+                                ciu_soft_prst.s.soft_prst = 1;
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST,
+                                               ciu_soft_prst.u64);
+                                ciu_soft_prst.u64 =
+                                    cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+                                ciu_soft_prst.s.soft_prst = 1;
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
+                                               ciu_soft_prst.u64);
+                                /* Wait until pcie resets the ports. */
+                                udelay(2000);
+                        }
+                        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+                        ciu_soft_prst.s.soft_prst = 0;
+                        cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+                        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+                        ciu_soft_prst.s.soft_prst = 0;
+                        cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+                }
+        } else {
+                /*
+                 * The normal case: The PCIe ports are completely
+                 * separate and can be brought out of reset
+                 * independently.
+                 */
+                if (pcie_port)
+                        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+                else
+                        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+                /*
+                 * After a chip reset the PCIe will also be in
+                 * reset. If it isn't, most likely someone is trying
+                 * to init it again without a proper PCIe reset.
+                 */
+                if (ciu_soft_prst.s.soft_prst == 0) {
+                        /* Reset the port */
+                        ciu_soft_prst.s.soft_prst = 1;
+                        if (pcie_port)
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
+                                               ciu_soft_prst.u64);
+                        else
+                                cvmx_write_csr(CVMX_CIU_SOFT_PRST,
+                                               ciu_soft_prst.u64);
+                        /* Wait until pcie resets the ports. */
+                        udelay(2000);
+                }
+                if (pcie_port) {
+                        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+                        ciu_soft_prst.s.soft_prst = 0;
+                        cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+                } else {
+                        ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+                        ciu_soft_prst.s.soft_prst = 0;
+                        cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+                }
+        }
+
+        /*
+         * Wait for PCIe reset to complete. Due to errata PCIE-700, we
+         * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
+         * fixed number of cycles.
+         */
+        cvmx_wait(400000);
+
+        /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
+           CN52XX, so we only probe it on newer chips */
+        if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
+            && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
+                /* Clear PCLK_RUN so we can check if the clock is running */
+                pescx_ctl_status2.u64 =
+                    cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
+                pescx_ctl_status2.s.pclk_run = 1;
+                cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
+                               pescx_ctl_status2.u64);
+                /*
+                 * Now that we cleared PCLK_RUN, wait for it to be set
+                 * again telling us the clock is running.
+                 */
+                if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
+                                          union cvmx_pescx_ctl_status2,
+                                          pclk_run, ==, 1, 10000)) {
+                        cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
+                                     pcie_port);
+                        return -1;
+                }
+        }
+
+        /*
+         * Check and make sure PCIe came out of reset. If it doesn't
+         * the board probably hasn't wired the clocks up and the
+         * interface should be skipped.
+         */
+        pescx_ctl_status2.u64 =
+            cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
+        if (pescx_ctl_status2.s.pcierst) {
+                cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
+                             pcie_port);
+                return -1;
+        }
+
+        /*
+         * Check BIST2 status. If any bits are set skip this interface. This
+         * is an attempt to catch PCIE-813 on pass 1 parts.
+         */
+        pescx_bist_status2.u64 =
+            cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
+        if (pescx_bist_status2.u64) {
+                cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
+                             "port isn't hooked up, skipping.\n",
+                             pcie_port);
+                return -1;
+        }
+
+        /* Check BIST status */
+        pescx_bist_status.u64 =
+            cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
+        if (pescx_bist_status.u64)
+                cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
+                             pcie_port, CAST64(pescx_bist_status.u64));
+
+        /* Initialize the config space CSRs */
+        __cvmx_pcie_rc_initialize_config_space(pcie_port);
+
+        /* Bring the link up */
+        if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
+                cvmx_dprintf
+                    ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
+                return -1;
+        }
+
+        /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
+        npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
+        /* Allow 16 words to combine */
+        npei_mem_access_ctl.s.max_word = 0;
+        /* Wait up to 127 cycles for more data */
+        npei_mem_access_ctl.s.timer = 127;
+        cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
+
+        /* Setup Mem access SubDIDs */
+        mem_access_subid.u64 = 0;
+        /* Port the request is sent to. */
+        mem_access_subid.s.port = pcie_port;
+        /* Due to an errata on pass 1 chips, no merging is allowed. */
+        mem_access_subid.s.nmerge = 1;
+        /* Endian-swap for Reads. */
+        mem_access_subid.s.esr = 1;
+        /* Endian-swap for Writes. */
+        mem_access_subid.s.esw = 1;
+        /* No Snoop for Reads. */
+        mem_access_subid.s.nsr = 1;
+        /* No Snoop for Writes. */
+        mem_access_subid.s.nsw = 1;
+        /* Disable Relaxed Ordering for Reads. */
+        mem_access_subid.s.ror = 0;
+        /* Disable Relaxed Ordering for Writes. */
+        mem_access_subid.s.row = 0;
+        /* PCIe Adddress Bits <63:34>. */
+        mem_access_subid.s.ba = 0;
+
+        /*
+         * Setup mem access 12-15 for port 0, 16-19 for port 1,
+         * supplying 36 bits of address space.
+         */
+        for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
+                cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
+                               mem_access_subid.u64);
+                /* Set each SUBID to extend the addressable range */
+                mem_access_subid.s.ba += 1;
+        }
+
+        /*
+         * Disable the peer to peer forwarding register. This must be
+         * setup by the OS after it enumerates the bus and assigns
+         * addresses to the PCIe busses.
+         */
+        for (i = 0; i < 4; i++) {
+                cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
+                cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
+        }
+
+        /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
+        cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
+
+        /*
+         * Disable Octeon's BAR1. It isn't needed in RC mode since
+         * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into
+         * the 2nd 256MB of memory.
+         */
+        cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1);
+
+        /*
+         * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
+         * precedence where they overlap. It also overlaps with the
+         * device addresses, so make sure the peer to peer forwarding
+         * is set right.
+         */
+        cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
+
+        /*
+         * Setup BAR2 attributes
+         *
+         * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
+         * - PTLP_RO,CTLP_RO should normally be set (except for debug).
+         * - WAIT_COM=0 will likely work for all applications.
+         *
+         * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
+         */
+        if (pcie_port) {
+                union cvmx_npei_ctl_port1 npei_ctl_port;
+                npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
+                npei_ctl_port.s.bar2_enb = 1;
+                npei_ctl_port.s.bar2_esx = 1;
+                npei_ctl_port.s.bar2_cax = 0;
+                npei_ctl_port.s.ptlp_ro = 1;
+                npei_ctl_port.s.ctlp_ro = 1;
+                npei_ctl_port.s.wait_com = 0;
+                npei_ctl_port.s.waitl_com = 0;
+                cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
+        } else {
+                union cvmx_npei_ctl_port0 npei_ctl_port;
+                npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
+                npei_ctl_port.s.bar2_enb = 1;
+                npei_ctl_port.s.bar2_esx = 1;
+                npei_ctl_port.s.bar2_cax = 0;
+                npei_ctl_port.s.ptlp_ro = 1;
+                npei_ctl_port.s.ctlp_ro = 1;
+                npei_ctl_port.s.wait_com = 0;
+                npei_ctl_port.s.waitl_com = 0;
+                cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
+        }
+        return 0;
+}
+
+
+/* Above was cvmx-pcie.c, below original pcie.c */
+
+
+/**
+ * Map a PCI device to the appropriate interrupt line
+ *
+ * @param dev    The Linux PCI device structure for the device to map
+ * @param slot   The slot number for this device on __BUS 0__. Linux
+ *               enumerates through all the bridges and figures out the
+ *               slot on Bus 0 where this device eventually hooks to.
+ * @param pin    The PCI interrupt pin read from the device, then swizzled
+ *               as it goes through each bridge.
+ * @return Interrupt number for the device
+ */
+int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
+                                       u8 slot, u8 pin)
+{
+        /*
+         * The EBH5600 board with the PCI to PCIe bridge mistakenly
+         * wires the first slot for both device id 2 and interrupt
+         * A. According to the PCI spec, device id 2 should be C. The
+         * following kludge attempts to fix this.
+         */
+        if (strstr(octeon_board_type_string(), "EBH5600") &&
+            dev->bus && dev->bus->parent) {
+                /*
+                 * Iterate all the way up the device chain and find
+                 * the root bus.
+                 */
+                while (dev->bus && dev->bus->parent)
+                        dev = to_pci_dev(dev->bus->bridge);
+                /* If the root bus is number 0 and the PEX 8114 is the
+                 * root, assume we are behind the miswired bus. We
+                 * need to correct the swizzle level by two. Yuck.
+                 */
+                if ((dev->bus->number == 0) &&
+                    (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
+                        /*
+                         * The pin field is one based, not zero. We
+                         * need to swizzle it by minus two.
+                         */
+                        pin = ((pin - 3) & 3) + 1;
+                }
+        }
+        /*
+         * The -1 is because pin starts with one, not zero. It might
+         * be that this equation needs to include the slot number, but
+         * I don't have hardware to check that against.
+         */
+        return pin - 1 + OCTEON_IRQ_PCI_INT0;
+}
+
+/**
+ * Read a value from configuration space
+ *
+ * @param bus
+ * @param devfn
+ * @param reg
+ * @param size
+ * @param val
+ * @return
+ */
+static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
+                                          unsigned int devfn, int reg, int size,
+                                          u32 *val)
+{
+        union octeon_cvmemctl cvmmemctl;
+        union octeon_cvmemctl cvmmemctl_save;
+        int bus_number = bus->number;
+
+        /*
+         * We need to force the bus number to be zero on the root
+         * bus. Linux numbers the 2nd root bus to start after all
+         * buses on root 0.
+         */
+        if (bus->parent == NULL)
+                bus_number = 0;
+
+        /*
+         * PCIe only has a single device connected to Octeon. It is
+         * always device ID 0. Don't bother doing reads for other
+         * device IDs on the first segment.
+         */
+        if ((bus_number == 0) && (devfn >> 3 != 0))
+                return PCIBIOS_FUNC_NOT_SUPPORTED;
+
+        /*
+         * The following is a workaround for the CN57XX, CN56XX,
+         * CN55XX, and CN54XX errata with PCIe config reads from non
+         * existent devices.  These chips will hang the PCIe link if a
+         * config read is performed that causes a UR response.
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
+            OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
+                /*
+                 * For our EBH5600 board, port 0 has a bridge with two
+                 * PCI-X slots. We need a new special checks to make
+                 * sure we only probe valid stuff.  The PCIe->PCI-X
+                 * bridge only respondes to device ID 0, function
+                 * 0-1
+                 */
+                if ((bus_number == 0) && (devfn >= 2))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+                /*
+                 * The PCI-X slots are device ID 2,3. Choose one of
+                 * the below "if" blocks based on what is plugged into
+                 * the board.
+                 */
+#if 1
+                /* Use this option if you aren't using either slot */
+                if (bus_number == 1)
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+#elif 0
+                /*
+                 * Use this option if you are using the first slot but
+                 * not the second.
+                 */
+                if ((bus_number == 1) && (devfn >> 3 != 2))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+#elif 0
+                /*
+                 * Use this option if you are using the second slot
+                 * but not the first.
+                 */
+                if ((bus_number == 1) && (devfn >> 3 != 3))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+#elif 0
+                /* Use this opion if you are using both slots */
+                if ((bus_number == 1) &&
+                    !((devfn == (2 << 3)) || (devfn == (3 << 3))))
+                        return PCIBIOS_FUNC_NOT_SUPPORTED;
+#endif
+
+                /*
+                 * Shorten the DID timeout so bus errors for PCIe
+                 * config reads from non existent devices happen
+                 * faster. This allows us to continue booting even if
+                 * the above "if" checks are wrong.  Once one of these
+                 * errors happens, the PCIe port is dead.
+                 */
+                cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
+                cvmmemctl.u64 = cvmmemctl_save.u64;
+                cvmmemctl.s.didtto = 2;
+                __write_64bit_c0_register($11, 7, cvmmemctl.u64);
+        }
+
+        switch (size) {
+        case 4:
+                *val = cvmx_pcie_config_read32(pcie_port, bus_number,
+                                               devfn >> 3, devfn & 0x7, reg);
+                break;
+        case 2:
+                *val = cvmx_pcie_config_read16(pcie_port, bus_number,
+                                               devfn >> 3, devfn & 0x7, reg);
+                break;
+        case 1:
+                *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
+                                              devfn & 0x7, reg);
+                break;
+        default:
+                return PCIBIOS_FUNC_NOT_SUPPORTED;
+        }
+
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
+            OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
+                __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
+                                    int reg, int size, u32 *val)
+{
+        return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
+}
+
+static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
+                                    int reg, int size, u32 *val)
+{
+        return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
+}
+
+
+
+/**
+ * Write a value to PCI configuration space
+ *
+ * @param bus
+ * @param devfn
+ * @param reg
+ * @param size
+ * @param val
+ * @return
+ */
+static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
+                                           unsigned int devfn, int reg,
+                                           int size, u32 val)
+{
+        int bus_number = bus->number;
+        /*
+         * We need to force the bus number to be zero on the root
+         * bus. Linux numbers the 2nd root bus to start after all
+         * busses on root 0.
+         */
+        if (bus->parent == NULL)
+                bus_number = 0;
+
+        switch (size) {
+        case 4:
+                cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
+                                         devfn & 0x7, reg, val);
+                return PCIBIOS_SUCCESSFUL;
+        case 2:
+                cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
+                                         devfn & 0x7, reg, val);
+                return PCIBIOS_SUCCESSFUL;
+        case 1:
+                cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
+                                        devfn & 0x7, reg, val);
+                return PCIBIOS_SUCCESSFUL;
+        }
+#if PCI_CONFIG_SPACE_DELAY
+        udelay(PCI_CONFIG_SPACE_DELAY);
+#endif
+        return PCIBIOS_FUNC_NOT_SUPPORTED;
+}
+
+static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
+                                     int reg, int size, u32 val)
+{
+        return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
+}
+
+static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
+                                     int reg, int size, u32 val)
+{
+        return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
+}
+
+static struct pci_ops octeon_pcie0_ops = {
+        octeon_pcie0_read_config,
+        octeon_pcie0_write_config,
+};
+
+static struct resource octeon_pcie0_mem_resource = {
+        .name = "Octeon PCIe0 MEM",
+        .flags = IORESOURCE_MEM,
+};
+
+static struct resource octeon_pcie0_io_resource = {
+        .name = "Octeon PCIe0 IO",
+        .flags = IORESOURCE_IO,
+};
+
+static struct pci_controller octeon_pcie0_controller = {
+        .pci_ops = &octeon_pcie0_ops,
+        .mem_resource = &octeon_pcie0_mem_resource,
+        .io_resource = &octeon_pcie0_io_resource,
+};
+
+static struct pci_ops octeon_pcie1_ops = {
+        octeon_pcie1_read_config,
+        octeon_pcie1_write_config,
+};
+
+static struct resource octeon_pcie1_mem_resource = {
+        .name = "Octeon PCIe1 MEM",
+        .flags = IORESOURCE_MEM,
+};
+
+static struct resource octeon_pcie1_io_resource = {
+        .name = "Octeon PCIe1 IO",
+        .flags = IORESOURCE_IO,
+};
+
+static struct pci_controller octeon_pcie1_controller = {
+        .pci_ops = &octeon_pcie1_ops,
+        .mem_resource = &octeon_pcie1_mem_resource,
+        .io_resource = &octeon_pcie1_io_resource,
+};
+
+
+/**
+ * Initialize the Octeon PCIe controllers
+ *
+ * @return
+ */
+static int __init octeon_pcie_setup(void)
+{
+        union cvmx_npei_ctl_status npei_ctl_status;
+        int result;
+
+        /* These chips don't have PCIe */
+        if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
+                return 0;
+
+        /* Point pcibios_map_irq() to the PCIe version of it */
+        octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
+
+        /* Use the PCIe based DMA mappings */
+        octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
+
+        /*
+         * PCIe I/O range. It is based on port 0 but includes up until
+         * port 1's end.
+         */
+        set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
+        ioport_resource.start = 0;
+        ioport_resource.end =
+                cvmx_pcie_get_io_base_address(1) -
+                cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
+
+        npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
+        if (npei_ctl_status.s.host_mode) {
+                pr_notice("PCIe: Initializing port 0\n");
+                result = cvmx_pcie_rc_initialize(0);
+                if (result == 0) {
+                        /* Memory offsets are physical addresses */
+                        octeon_pcie0_controller.mem_offset =
+                                cvmx_pcie_get_mem_base_address(0);
+                        /* IO offsets are Mips virtual addresses */
+                        octeon_pcie0_controller.io_map_base =
+                                CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
+                                                (0));
+                        octeon_pcie0_controller.io_offset = 0;
+                        /*
+                         * To keep things similar to PCI, we start
+                         * device addresses at the same place as PCI
+                         * uisng big bar support. This normally
+                         * translates to 4GB-256MB, which is the same
+                         * as most x86 PCs.
+                         */
+                        octeon_pcie0_controller.mem_resource->start =
+                                cvmx_pcie_get_mem_base_address(0) +
+                                (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
+                        octeon_pcie0_controller.mem_resource->end =
+                                cvmx_pcie_get_mem_base_address(0) +
+                                cvmx_pcie_get_mem_size(0) - 1;
+                        /*
+                         * Ports must be above 16KB for the ISA bus
+                         * filtering in the PCI-X to PCI bridge.
+                         */
+                        octeon_pcie0_controller.io_resource->start = 4 << 10;
+                        octeon_pcie0_controller.io_resource->end =
+                                cvmx_pcie_get_io_size(0) - 1;
+                        register_pci_controller(&octeon_pcie0_controller);
+                }
+        } else {
+                pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
+        }
+
+        /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                union cvmx_npei_dbg_data npei_dbg_data;
+                npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+                if (npei_dbg_data.cn52xx.qlm0_link_width)
+                        return 0;
+        }
+
+        pr_notice("PCIe: Initializing port 1\n");
+        result = cvmx_pcie_rc_initialize(1);
+        if (result == 0) {
+                /* Memory offsets are physical addresses */
+                octeon_pcie1_controller.mem_offset =
+                        cvmx_pcie_get_mem_base_address(1);
+                /* IO offsets are Mips virtual addresses */
+                octeon_pcie1_controller.io_map_base =
+                        CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
+                octeon_pcie1_controller.io_offset =
+                        cvmx_pcie_get_io_base_address(1) -
+                        cvmx_pcie_get_io_base_address(0);
+                /*
+                 * To keep things similar to PCI, we start device
+                 * addresses at the same place as PCI uisng big bar
+                 * support. This normally translates to 4GB-256MB,
+                 * which is the same as most x86 PCs.
+                 */
+                octeon_pcie1_controller.mem_resource->start =
+                        cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
+                        (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
+                octeon_pcie1_controller.mem_resource->end =
+                        cvmx_pcie_get_mem_base_address(1) +
+                        cvmx_pcie_get_mem_size(1) - 1;
+                /*
+                 * Ports must be above 16KB for the ISA bus filtering
+                 * in the PCI-X to PCI bridge.
+                 */
+                octeon_pcie1_controller.io_resource->start =
+                        cvmx_pcie_get_io_base_address(1) -
+                        cvmx_pcie_get_io_base_address(0);
+                octeon_pcie1_controller.io_resource->end =
+                        octeon_pcie1_controller.io_resource->start +
+                        cvmx_pcie_get_io_size(1) - 1;
+                register_pci_controller(&octeon_pcie1_controller);
+        }
+        return 0;
+}
+
+arch_initcall(octeon_pcie_setup);
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 5f4e49ba4713..da559249cc2f 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/serial.h>
+#include <linux/smp.h>
 #include <linux/types.h>
 #include <linux/string.h>       /* for memset */
 #include <linux/tty.h>
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 24e0ad63980a..0b891a9c6253 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -5,6 +5,7 @@
  *
  * Copyright (C) 2004-2008 Cavium Networks
  */
+#include <linux/cpu.h>
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/smp.h>
@@ -19,10 +20,16 @@
 
 #include <asm/octeon/octeon.h>
 
+#include "octeon_boot.h"
+
 volatile unsigned long octeon_processor_boot = 0xff;
 volatile unsigned long octeon_processor_sp;
 volatile unsigned long octeon_processor_gp;
 
+#ifdef CONFIG_HOTPLUG_CPU
+static unsigned int InitTLBStart_addr;
+#endif
+
 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
 {
         const int coreid = cvmx_get_core_num();
@@ -67,8 +74,28 @@ static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action)
 }
 
 /**
- * Detect available CPUs, populate phys_cpu_present_map
+ * Detect available CPUs, populate cpu_possible_map
  */
+static void octeon_smp_hotplug_setup(void)
+{
+#ifdef CONFIG_HOTPLUG_CPU
+        uint32_t labi_signature;
+
+        labi_signature =
+                cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                        LABI_ADDR_IN_BOOTLOADER +
+                                        offsetof(struct linux_app_boot_info,
+                                                    labi_signature)));
+        if (labi_signature != LABI_SIGNATURE)
+                pr_err("The bootloader version on this board is incorrect\n");
+        InitTLBStart_addr =
+                cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                   LABI_ADDR_IN_BOOTLOADER +
+                                           offsetof(struct linux_app_boot_info,
+                                                    InitTLBStart_addr)));
+#endif
+}
+
 static void octeon_smp_setup(void)
 {
         const int coreid = cvmx_get_core_num();
@@ -91,6 +118,9 @@ static void octeon_smp_setup(void)
                         cpus++;
                 }
         }
+        cpu_present_map = cpu_possible_map;
+
+        octeon_smp_hotplug_setup();
 }
 
 /**
@@ -128,6 +158,17 @@ static void octeon_init_secondary(void)
         const int coreid = cvmx_get_core_num();
         union cvmx_ciu_intx_sum0 interrupt_enable;
 
+#ifdef CONFIG_HOTPLUG_CPU
+        unsigned int cur_exception_base;
+
+        cur_exception_base = cvmx_read64_uint32(
+                CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                             LABI_ADDR_IN_BOOTLOADER +
+                             offsetof(struct linux_app_boot_info,
+                                      cur_exception_base)));
+        /* cur_exception_base is incremented in bootloader after setting */
+        write_c0_ebase((unsigned int)(cur_exception_base - EXCEPTION_BASE_INCR));
+#endif
         octeon_check_cpu_bist();
         octeon_init_cvmcount();
         /*
@@ -199,6 +240,193 @@ static void octeon_cpus_done(void)
 #endif
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+
+/* State of each CPU. */
+DEFINE_PER_CPU(int, cpu_state);
+
+extern void fixup_irqs(void);
+
+static DEFINE_SPINLOCK(smp_reserve_lock);
+
+static int octeon_cpu_disable(void)
+{
+        unsigned int cpu = smp_processor_id();
+
+        if (cpu == 0)
+                return -EBUSY;
+
+        spin_lock(&smp_reserve_lock);
+
+        cpu_clear(cpu, cpu_online_map);
+        cpu_clear(cpu, cpu_callin_map);
+        local_irq_disable();
+        fixup_irqs();
+        local_irq_enable();
+
+        flush_cache_all();
+        local_flush_tlb_all();
+
+        spin_unlock(&smp_reserve_lock);
+
+        return 0;
+}
+
+static void octeon_cpu_die(unsigned int cpu)
+{
+        int coreid = cpu_logical_map(cpu);
+        uint32_t avail_coremask;
+        struct cvmx_bootmem_named_block_desc *block_desc;
+
+#ifdef CONFIG_CAVIUM_OCTEON_WATCHDOG
+        /* Disable the watchdog */
+        cvmx_ciu_wdogx_t ciu_wdog;
+        ciu_wdog.u64 = cvmx_read_csr(CVMX_CIU_WDOGX(cpu));
+        ciu_wdog.s.mode = 0;
+        cvmx_write_csr(CVMX_CIU_WDOGX(cpu), ciu_wdog.u64);
+#endif
+
+        while (per_cpu(cpu_state, cpu) != CPU_DEAD)
+                cpu_relax();
+
+        /*
+         * This is a bit complicated strategics of getting/settig available
+         * cores mask, copied from bootloader
+         */
+        /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
+        block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
+
+        if (!block_desc) {
+                avail_coremask =
+                        cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                                   LABI_ADDR_IN_BOOTLOADER +
+                                                   offsetof
+                                                   (struct linux_app_boot_info,
+                                                    avail_coremask)));
+        } else {                       /* alternative, already initialized */
+               avail_coremask =
+                   cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                                   block_desc->base_addr +
+                                                  AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
+        }
+
+        avail_coremask |= 1 << coreid;
+
+        /* Setting avail_coremask for bootoct binary */
+        if (!block_desc) {
+                cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                                LABI_ADDR_IN_BOOTLOADER +
+                                                offsetof(struct linux_app_boot_info,
+                                                         avail_coremask)),
+                                   avail_coremask);
+        } else {
+                cvmx_write64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                                block_desc->base_addr +
+                                                AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK),
+                                   avail_coremask);
+        }
+
+        pr_info("Reset core %d. Available Coremask = %x \n", coreid,
+                avail_coremask);
+        cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
+        cvmx_write_csr(CVMX_CIU_PP_RST, 0);
+}
+
+void play_dead(void)
+{
+        int coreid = cvmx_get_core_num();
+
+        idle_task_exit();
+        octeon_processor_boot = 0xff;
+        per_cpu(cpu_state, coreid) = CPU_DEAD;
+
+        while (1)       /* core will be reset here */
+                ;
+}
+
+extern void kernel_entry(unsigned long arg1, ...);
+
+static void start_after_reset(void)
+{
+        kernel_entry(0, 0, 0);  /* set a2 = 0 for secondary core */
+}
+
+int octeon_update_boot_vector(unsigned int cpu)
+{
+
+        int coreid = cpu_logical_map(cpu);
+        unsigned int avail_coremask;
+        struct cvmx_bootmem_named_block_desc *block_desc;
+        struct boot_init_vector *boot_vect =
+                (struct boot_init_vector *) cvmx_phys_to_ptr(0x0 +
+                                                  BOOTLOADER_BOOT_VECTOR);
+
+        block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
+
+        if (!block_desc) {
+                avail_coremask =
+                        cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                           LABI_ADDR_IN_BOOTLOADER +
+                                                offsetof(struct linux_app_boot_info,
+                                                avail_coremask)));
+        } else {                       /* alternative, already initialized */
+               avail_coremask =
+                   cvmx_read64_uint32(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
+                                                   block_desc->base_addr +
+                                                   AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK));
+        }
+
+        if (!(avail_coremask & (1 << coreid))) {
+                /* core not available, assume, that catched by simple-executive */
+                cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
+                cvmx_write_csr(CVMX_CIU_PP_RST, 0);
+        }
+
+        boot_vect[coreid].app_start_func_addr =
+                (uint32_t) (unsigned long) start_after_reset;
+        boot_vect[coreid].code_addr = InitTLBStart_addr;
+
+        CVMX_SYNC;
+
+        cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
+
+        return 0;
+}
+
+static int __cpuinit octeon_cpu_callback(struct notifier_block *nfb,
+        unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (unsigned long)hcpu;
+
+        switch (action) {
+        case CPU_UP_PREPARE:
+                octeon_update_boot_vector(cpu);
+                break;
+        case CPU_ONLINE:
+                pr_info("Cpu %d online\n", cpu);
+                break;
+        case CPU_DEAD:
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata octeon_cpu_notifier = {
+        .notifier_call = octeon_cpu_callback,
+};
+
+static int __cpuinit register_cavium_notifier(void)
+{
+        register_hotcpu_notifier(&octeon_cpu_notifier);
+
+        return 0;
+}
+
+late_initcall(register_cavium_notifier);
+
+#endif  /* CONFIG_HOTPLUG_CPU */
+
 struct plat_smp_ops octeon_smp_ops = {
         .send_ipi_single        = octeon_send_ipi_single,
         .send_ipi_mask          = octeon_send_ipi_mask,
@@ -208,4 +436,8 @@ struct plat_smp_ops octeon_smp_ops = {
         .boot_secondary         = octeon_boot_secondary,
         .smp_setup              = octeon_smp_setup,
         .prepare_cpus           = octeon_prepare_cpus,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_disable            = octeon_cpu_disable,
+        .cpu_die                = octeon_cpu_die,
+#endif
 };
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 783da855a2e3..d6d35b2e5fe8 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -963,7 +963,7 @@ CONFIG_EEPROM_LEGACY=y
 CONFIG_SENSORS_PCF8574=y
 # CONFIG_PCF8575 is not set
 CONFIG_SENSORS_PCF8591=y
-CONFIG_SENSORS_MAX6875=y
+CONFIG_EEPROM_MAX6875=y
 # CONFIG_SENSORS_TSL2550 is not set
 CONFIG_I2C_DEBUG_CORE=y
 CONFIG_I2C_DEBUG_ALGO=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 8426d3b9501c..fadb351d249b 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -1849,7 +1849,7 @@ CONFIG_EEPROM_LEGACY=m
 CONFIG_SENSORS_PCF8574=m
 CONFIG_SENSORS_PCA9539=m
 CONFIG_SENSORS_PCF8591=m
-CONFIG_SENSORS_MAX6875=m
+CONFIG_EEPROM_MAX6875=m
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
diff --git a/arch/mips/include/asm/bug.h b/arch/mips/include/asm/bug.h
index 08ea46863fe5..6cf29c26e873 100644
--- a/arch/mips/include/asm/bug.h
+++ b/arch/mips/include/asm/bug.h
@@ -1,6 +1,7 @@
 #ifndef __ASM_BUG_H
 #define __ASM_BUG_H
 
+#include <linux/compiler.h>
 #include <asm/sgidefs.h>
 
 #ifdef CONFIG_BUG
diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h
index 9dc10df32078..b160a706795d 100644
--- a/arch/mips/include/asm/bugs.h
+++ b/arch/mips/include/asm/bugs.h
@@ -11,6 +11,7 @@
 
 #include <linux/bug.h>
 #include <linux/delay.h>
+#include <linux/smp.h>
 
 #include <asm/cpu.h>
 #include <asm/cpu-info.h>
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c0047f861337..8ab1d12ba7f4 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -147,6 +147,10 @@
 #define cpu_has_mips_r  (cpu_has_mips32r1 | cpu_has_mips32r2 | \
                          cpu_has_mips64r1 | cpu_has_mips64r2)
 
+#ifndef cpu_has_mips_r2_exec_hazard
+#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
+#endif
+
 /*
  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
  * pre-MIPS32/MIPS53 processors have CLO, CLZ.  For 64-bit kernels
@@ -230,4 +234,8 @@
 #define cpu_scache_line_size()  cpu_data[0].scache.linesz
 #endif
 
+#ifndef cpu_hwrena_impl_bits
+#define cpu_hwrena_impl_bits            0
+#endif
+
 #endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/delay.h b/arch/mips/include/asm/delay.h
index a07e51b2be13..d2d8949be6b7 100644
--- a/arch/mips/include/asm/delay.h
+++ b/arch/mips/include/asm/delay.h
@@ -15,7 +15,7 @@ extern void __delay(unsigned int loops);
 extern void __ndelay(unsigned int ns);
 extern void __udelay(unsigned int us);
 
-#define ndelay(ns) __udelay(ns)
+#define ndelay(ns) __ndelay(ns)
 #define udelay(us) __udelay(us)
 
 /* make sure "usecs *= ..." in udelay do not overflow. */
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
new file mode 100644
index 000000000000..f5e856015329
--- /dev/null
+++ b/arch/mips/include/asm/hugetlb.h
@@ -0,0 +1,114 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008, 2009 Cavium Networks, Inc.
+ */
+
+#ifndef __ASM_HUGETLB_H
+#define __ASM_HUGETLB_H
+
+#include <asm/page.h>
+
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+                                         unsigned long addr,
+                                         unsigned long len)
+{
+        return 0;
+}
+
+static inline int prepare_hugepage_range(struct file *file,
+                                         unsigned long addr,
+                                         unsigned long len)
+{
+        unsigned long task_size = STACK_TOP;
+        struct hstate *h = hstate_file(file);
+
+        if (len & ~huge_page_mask(h))
+                return -EINVAL;
+        if (addr & ~huge_page_mask(h))
+                return -EINVAL;
+        if (len > task_size)
+                return -ENOMEM;
+        if (task_size - len < addr)
+                return -EINVAL;
+        return 0;
+}
+
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
+{
+}
+
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+                                          unsigned long addr,
+                                          unsigned long end,
+                                          unsigned long floor,
+                                          unsigned long ceiling)
+{
+        free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                                   pte_t *ptep, pte_t pte)
+{
+        set_pte_at(mm, addr, ptep, pte);
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+                                            unsigned long addr, pte_t *ptep)
+{
+        pte_t clear;
+        pte_t pte = *ptep;
+
+        pte_val(clear) = (unsigned long)invalid_pte_table;
+        set_pte_at(mm, addr, ptep, clear);
+        return pte;
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long addr, pte_t *ptep)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+        unsigned long val = pte_val(pte) & ~_PAGE_GLOBAL;
+        return !val || (val == (unsigned long)invalid_pte_table);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+        return pte_wrprotect(pte);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+                                             unsigned long addr,
+                                             pte_t *ptep, pte_t pte,
+                                             int dirty)
+{
+        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+        return *ptep;
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+        return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+#endif /* __ASM_HUGETLB_H */
diff --git a/arch/mips/include/asm/i8253.h b/arch/mips/include/asm/i8253.h
index 5dabc870b322..032ca73f181b 100644
--- a/arch/mips/include/asm/i8253.h
+++ b/arch/mips/include/asm/i8253.h
@@ -12,8 +12,6 @@
 #define PIT_CH0                 0x40
 #define PIT_CH2                 0x42
 
-#define PIT_TICK_RATE           1193182UL
-
 extern spinlock_t i8253_lock;
 
 extern void setup_pit_timer(void);
diff --git a/arch/mips/include/asm/ioctl.h b/arch/mips/include/asm/ioctl.h
index 916163401b2c..c515a1a4c47c 100644
--- a/arch/mips/include/asm/ioctl.h
+++ b/arch/mips/include/asm/ioctl.h
@@ -3,40 +3,16 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle
+ * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2009 Wind River Systems
+ * Written by Ralf Baechle <ralf@linux-mips.org>
  */
-#ifndef _ASM_IOCTL_H
-#define _ASM_IOCTL_H
+#ifndef __ASM_IOCTL_H
+#define __ASM_IOCTL_H
 
-/*
- * The original linux ioctl numbering scheme was just a general
- * "anything goes" setup, where more or less random numbers were
- * assigned.  Sorry, I was clueless when I started out on this.
- *
- * On the alpha, we'll try to clean it up a bit, using a more sane
- * ioctl numbering, and also trying to be compatible with OSF/1 in
- * the process. I'd like to clean it up for the i386 as well, but
- * it's so painful recognizing both the new and the old numbers..
- *
- * The same applies for for the MIPS ABI; in fact even the macros
- * from Linux/Alpha fit almost perfectly.
- */
-
-#define _IOC_NRBITS     8
-#define _IOC_TYPEBITS   8
 #define _IOC_SIZEBITS   13
 #define _IOC_DIRBITS    3
 
-#define _IOC_NRMASK     ((1 << _IOC_NRBITS)-1)
-#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
-#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
-#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
-
-#define _IOC_NRSHIFT    0
-#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
-#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
-#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
-
 /*
  * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
  * And this turns out useful to catch old ioctl numbers in header
@@ -46,53 +22,6 @@
 #define _IOC_READ       2U
 #define _IOC_WRITE      4U
 
-/*
- * The following are included for compatibility
- */
-#define _IOC_VOID       0x20000000
-#define _IOC_OUT        0x40000000
-#define _IOC_IN         0x80000000
-#define _IOC_INOUT      (IOC_IN|IOC_OUT)
-
-#define _IOC(dir, type, nr, size) \
-        (((dir)  << _IOC_DIRSHIFT) | \
-         ((type) << _IOC_TYPESHIFT) | \
-         ((nr)   << _IOC_NRSHIFT) | \
-         ((size) << _IOC_SIZESHIFT))
-
-#ifdef __KERNEL__
-/* provoke compile error for invalid uses of size argument */
-extern unsigned int __invalid_size_argument_for_IOC;
-#define _IOC_TYPECHECK(t) \
-        ((sizeof(t) == sizeof(t[1]) && \
-          sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
-          sizeof(t) : __invalid_size_argument_for_IOC)
-#else
-#define _IOC_TYPECHECK(t)       (sizeof(t))
-#endif
-
-/* used to create numbers */
-#define _IO(type, nr)           _IOC(_IOC_NONE, (type), (nr), 0)
-#define _IOR(type, nr, size)    _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
-#define _IOW(type, nr, size)    _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
-#define _IOWR(type, nr, size)   _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
-#define _IOR_BAD(type, nr, size)        _IOC(_IOC_READ, (type), (nr), sizeof(size))
-#define _IOW_BAD(type, nr, size)        _IOC(_IOC_WRITE, (type), (nr), sizeof(size))
-#define _IOWR_BAD(type, nr, size)       _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size))
-
-
-/* used to decode them.. */
-#define _IOC_DIR(nr)            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
-#define _IOC_TYPE(nr)           (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
-#define _IOC_NR(nr)             (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
-#define _IOC_SIZE(nr)           (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
-
-/* ...and for the drivers/sound files... */
-
-#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
-#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
-#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
-#define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
-#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
+#include <asm-generic/ioctl.h>
 
-#endif /* _ASM_IOCTL_H */
+#endif /* __ASM_IOCTL_H */
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 4f1eed107b08..09b08d05ff72 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -10,6 +10,7 @@
 #define _ASM_IRQ_H
 
 #include <linux/linkage.h>
+#include <linux/smp.h>
 
 #include <asm/mipsmtregs.h>
 
diff --git a/arch/mips/include/asm/kmap_types.h b/arch/mips/include/asm/kmap_types.h
index 806aae3c5338..58e91ed0388f 100644
--- a/arch/mips/include/asm/kmap_types.h
+++ b/arch/mips/include/asm/kmap_types.h
@@ -1,30 +1,12 @@
 #ifndef _ASM_KMAP_TYPES_H
 #define _ASM_KMAP_TYPES_H
 
-
 #ifdef CONFIG_DEBUG_HIGHMEM
-# define D(n) __KM_FENCE_##n ,
-#else
-# define D(n)
+#define  __WITH_KM_FENCE
 #endif
 
-enum km_type {
-D(0)    KM_BOUNCE_READ,
-D(1)    KM_SKB_SUNRPC_DATA,
-D(2)    KM_SKB_DATA_SOFTIRQ,
-D(3)    KM_USER0,
-D(4)    KM_USER1,
-D(5)    KM_BIO_SRC_IRQ,
-D(6)    KM_BIO_DST_IRQ,
-D(7)    KM_PTE0,
-D(8)    KM_PTE1,
-D(9)    KM_IRQ0,
-D(10)   KM_IRQ1,
-D(11)   KM_SOFTIRQ0,
-D(12)   KM_SOFTIRQ1,
-D(13)   KM_TYPE_NR
-};
+#include <asm-generic/kmap_types.h>
 
-#undef D
+#undef __WITH_KM_FENCE
 
 #endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_gpio.h b/arch/mips/include/asm/mach-au1x00/au1000_gpio.h
deleted file mode 100644
index d8c96fda5549..000000000000
--- a/arch/mips/include/asm/mach-au1x00/au1000_gpio.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * FILE NAME au1000_gpio.h
- *
- * BRIEF MODULE DESCRIPTION
- *      API to Alchemy Au1xx0 GPIO device.
- *
- *  Author: MontaVista Software, Inc.  <source@mvista.com>
- *          Steve Longerbeam
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __AU1000_GPIO_H
-#define __AU1000_GPIO_H
-
-#include <linux/ioctl.h>
-
-#define AU1000GPIO_IOC_MAGIC 'A'
-
-#define AU1000GPIO_IN           _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
-#define AU1000GPIO_SET          _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
-#define AU1000GPIO_CLEAR        _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
-#define AU1000GPIO_OUT          _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
-#define AU1000GPIO_TRISTATE     _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
-#define AU1000GPIO_AVAIL_MASK   _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
-
-#ifdef __KERNEL__
-extern u32 get_au1000_avail_gpio_mask(void);
-extern int au1000gpio_tristate(u32 data);
-extern int au1000gpio_in(u32 *data);
-extern int au1000gpio_set(u32 data);
-extern int au1000gpio_clear(u32 data);
-extern int au1000gpio_out(u32 data);
-#endif
-
-#endif
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
new file mode 100644
index 000000000000..127d4ed9f073
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -0,0 +1,604 @@
+/*
+ * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
+ *
+ * Copyright (c) 2009 Manuel Lauss.
+ *
+ * Licensed under the terms outlined in the file COPYING.
+ */
+
+#ifndef _ALCHEMY_GPIO_AU1000_H_
+#define _ALCHEMY_GPIO_AU1000_H_
+
+#include <asm/mach-au1x00/au1000.h>
+
+/* The default GPIO numberspace as documented in the Alchemy manuals.
+ * GPIO0-31 from GPIO1 block,   GPIO200-215 from GPIO2 block.
+ */
+#define ALCHEMY_GPIO1_BASE      0
+#define ALCHEMY_GPIO2_BASE      200
+
+#define ALCHEMY_GPIO1_NUM       32
+#define ALCHEMY_GPIO2_NUM       16
+#define ALCHEMY_GPIO1_MAX       (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
+#define ALCHEMY_GPIO2_MAX       (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
+
+#define MAKE_IRQ(intc, off)     (AU1000_INTC##intc##_INT_BASE + (off))
+
+
+static inline int au1000_gpio1_to_irq(int gpio)
+{
+        return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
+}
+
+static inline int au1000_gpio2_to_irq(int gpio)
+{
+        return -ENXIO;
+}
+
+#ifdef CONFIG_SOC_AU1000
+static inline int au1000_irq_to_gpio(int irq)
+{
+        if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31))
+                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
+
+        return -ENXIO;
+}
+#endif
+
+static inline int au1500_gpio1_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO1_BASE;
+
+        switch (gpio) {
+        case 0 ... 15:
+        case 20:
+        case 23 ... 28: return MAKE_IRQ(1, gpio);
+        }
+
+        return -ENXIO;
+}
+
+static inline int au1500_gpio2_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO2_BASE;
+
+        switch (gpio) {
+        case 0 ... 3:   return MAKE_IRQ(1, 16 + gpio - 0);
+        case 4 ... 5:   return MAKE_IRQ(1, 21 + gpio - 4);
+        case 6 ... 7:   return MAKE_IRQ(1, 29 + gpio - 6);
+        }
+
+        return -ENXIO;
+}
+
+#ifdef CONFIG_SOC_AU1500
+static inline int au1500_irq_to_gpio(int irq)
+{
+        switch (irq) {
+        case AU1000_GPIO_0 ... AU1000_GPIO_15:
+        case AU1500_GPIO_20:
+        case AU1500_GPIO_23 ... AU1500_GPIO_28:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
+        case AU1500_GPIO_200 ... AU1500_GPIO_203:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0;
+        case AU1500_GPIO_204 ... AU1500_GPIO_205:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4;
+        case AU1500_GPIO_206 ... AU1500_GPIO_207:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
+        case AU1500_GPIO_208_215:
+                return ALCHEMY_GPIO2_BASE + 8;
+        }
+
+        return -ENXIO;
+}
+#endif
+
+static inline int au1100_gpio1_to_irq(int gpio)
+{
+        return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
+}
+
+static inline int au1100_gpio2_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO2_BASE;
+
+        if ((gpio >= 8) && (gpio <= 15))
+                return MAKE_IRQ(0, 29);         /* shared GPIO208_215 */
+}
+
+#ifdef CONFIG_SOC_AU1100
+static inline int au1100_irq_to_gpio(int irq)
+{
+        switch (irq) {
+        case AU1000_GPIO_0 ... AU1000_GPIO_31:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
+        case AU1100_GPIO_208_215:
+                return ALCHEMY_GPIO2_BASE + 8;
+        }
+
+        return -ENXIO;
+}
+#endif
+
+static inline int au1550_gpio1_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO1_BASE;
+
+        switch (gpio) {
+        case 0 ... 15:
+        case 20 ... 28: return MAKE_IRQ(1, gpio);
+        case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
+        }
+
+        return -ENXIO;
+}
+
+static inline int au1550_gpio2_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO2_BASE;
+
+        switch (gpio) {
+        case 0:         return MAKE_IRQ(1, 16);
+        case 1 ... 5:   return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
+        case 6 ... 7:   return MAKE_IRQ(1, 29 + gpio - 6);
+        case 8 ... 15:  return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
+        }
+
+        return -ENXIO;
+}
+
+#ifdef CONFIG_SOC_AU1550
+static inline int au1550_irq_to_gpio(int irq)
+{
+        switch (irq) {
+        case AU1000_GPIO_0 ... AU1000_GPIO_15:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
+        case AU1550_GPIO_200:
+        case AU1500_GPIO_201_205:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0;
+        case AU1500_GPIO_16 ... AU1500_GPIO_28:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16;
+        case AU1500_GPIO_206 ... AU1500_GPIO_208_218:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
+        }
+
+        return -ENXIO;
+}
+#endif
+
+static inline int au1200_gpio1_to_irq(int gpio)
+{
+        return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
+}
+
+static inline int au1200_gpio2_to_irq(int gpio)
+{
+        gpio -= ALCHEMY_GPIO2_BASE;
+
+        switch (gpio) {
+        case 0 ... 2:   return MAKE_IRQ(0, 5 + gpio - 0);
+        case 3:         return MAKE_IRQ(0, 22);
+        case 4 ... 7:   return MAKE_IRQ(0, 24 + gpio - 4);
+        case 8 ... 15:  return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
+        }
+
+        return -ENXIO;
+}
+
+#ifdef CONFIG_SOC_AU1200
+static inline int au1200_irq_to_gpio(int irq)
+{
+        switch (irq) {
+        case AU1000_GPIO_0 ... AU1000_GPIO_31:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
+        case AU1200_GPIO_200 ... AU1200_GPIO_202:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0;
+        case AU1200_GPIO_203:
+                return ALCHEMY_GPIO2_BASE + 3;
+        case AU1200_GPIO_204 ... AU1200_GPIO_208_215:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4;
+        }
+
+        return -ENXIO;
+}
+#endif
+
+/*
+ * GPIO1 block macros for common linux gpio functions.
+ */
+static inline void alchemy_gpio1_set_value(int gpio, int v)
+{
+        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
+        unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
+        au_writel(mask, r);
+        au_sync();
+}
+
+static inline int alchemy_gpio1_get_value(int gpio)
+{
+        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
+        return au_readl(SYS_PINSTATERD) & mask;
+}
+
+static inline int alchemy_gpio1_direction_input(int gpio)
+{
+        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
+        au_writel(mask, SYS_TRIOUTCLR);
+        au_sync();
+        return 0;
+}
+
+static inline int alchemy_gpio1_direction_output(int gpio, int v)
+{
+        /* hardware switches to "output" mode when one of the two
+         * "set_value" registers is accessed.
+         */
+        alchemy_gpio1_set_value(gpio, v);
+        return 0;
+}
+
+static inline int alchemy_gpio1_is_valid(int gpio)
+{
+        return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
+}
+
+static inline int alchemy_gpio1_to_irq(int gpio)
+{
+#if defined(CONFIG_SOC_AU1000)
+        return au1000_gpio1_to_irq(gpio);
+#elif defined(CONFIG_SOC_AU1100)
+        return au1100_gpio1_to_irq(gpio);
+#elif defined(CONFIG_SOC_AU1500)
+        return au1500_gpio1_to_irq(gpio);
+#elif defined(CONFIG_SOC_AU1550)
+        return au1550_gpio1_to_irq(gpio);
+#elif defined(CONFIG_SOC_AU1200)
+        return au1200_gpio1_to_irq(gpio);
+#else
+        return -ENXIO;
+#endif
+}
+
+/*
+ * GPIO2 block macros for common linux GPIO functions. The 'gpio'
+ * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
+ */
+static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
+{
+        unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
+        unsigned long d = au_readl(GPIO2_DIR);
+        if (to_out)
+                d |= mask;
+        else
+                d &= ~mask;
+        au_writel(d, GPIO2_DIR);
+        au_sync();
+}
+
+static inline void alchemy_gpio2_set_value(int gpio, int v)
+{
+        unsigned long mask;
+        mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
+        au_writel(mask, GPIO2_OUTPUT);
+        au_sync();
+}
+
+static inline int alchemy_gpio2_get_value(int gpio)
+{
+        return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
+}
+
+static inline int alchemy_gpio2_direction_input(int gpio)
+{
+        unsigned long flags;
+        local_irq_save(flags);
+        __alchemy_gpio2_mod_dir(gpio, 0);
+        local_irq_restore(flags);
+        return 0;
+}
+
+static inline int alchemy_gpio2_direction_output(int gpio, int v)
+{
+        unsigned long flags;
+        alchemy_gpio2_set_value(gpio, v);
+        local_irq_save(flags);
+        __alchemy_gpio2_mod_dir(gpio, 1);
+        local_irq_restore(flags);
+        return 0;
+}
+
+static inline int alchemy_gpio2_is_valid(int gpio)
+{
+        return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
+}
+
+static inline int alchemy_gpio2_to_irq(int gpio)
+{
+#if defined(CONFIG_SOC_AU1000)
+        return au1000_gpio2_to_irq(gpio);
+#elif defined(CONFIG_SOC_AU1100)
+        return au1100_gpio2_to_irq(gpio);
+#elif defined(CONFIG_SOC_AU1500)
+        return au1500_gpio2_to_irq(gpio);
+#elif defined(CONFIG_SOC_AU1550)
+        return au1550_gpio2_to_irq(gpio);
+#elif defined(CONFIG_SOC_AU1200)
+        return au1200_gpio2_to_irq(gpio);
+#else
+        return -ENXIO;
+#endif
+}
+
+/**********************************************************************/
+
+/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
+ * SYS_PININPUTEN is written to at least once.  On Au1550/Au1200 this
+ * register enables use of GPIOs as wake source.
+ */
+static inline void alchemy_gpio1_input_enable(void)
+{
+        au_writel(0, SYS_PININPUTEN);   /* the write op is key */
+        au_sync();
+}
+
+/* GPIO2 shared interrupts and control */
+
+static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
+{
+        unsigned long r = au_readl(GPIO2_INTENABLE);
+        if (en)
+                r |= 1 << gpio2;
+        else
+                r &= ~(1 << gpio2);
+        au_writel(r, GPIO2_INTENABLE);
+        au_sync();
+}
+
+/**
+ * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
+ * @gpio2:      The GPIO2 pin to activate (200...215).
+ *
+ * GPIO208-215 have one shared interrupt line to the INTC.  They are
+ * and'ed with a per-pin enable bit and finally or'ed together to form
+ * a single irq request (useful for active-high sources).
+ * With this function, a pins' individual contribution to the int request
+ * can be enabled.  As with all other GPIO-based interrupts, the INTC
+ * must be programmed to accept the GPIO208_215 interrupt as well.
+ *
+ * NOTE: Calling this macro is only necessary for GPIO208-215; all other
+ * GPIO2-based interrupts have their own request to the INTC.  Please
+ * consult your Alchemy databook for more information!
+ *
+ * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
+ * line to the INTC, GPIO201_205.  This function can be used for those
+ * as well.
+ *
+ * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
+ * (200-215 by default). No sanity checks are made,
+ */
+static inline void alchemy_gpio2_enable_int(int gpio2)
+{
+        unsigned long flags;
+
+        gpio2 -= ALCHEMY_GPIO2_BASE;
+
+#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
+        /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
+        gpio2 -= 8;
+#endif
+        local_irq_save(flags);
+        __alchemy_gpio2_mod_int(gpio2, 1);
+        local_irq_restore(flags);
+}
+
+/**
+ * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
+ * @gpio2:      The GPIO2 pin to activate (200...215).
+ *
+ * see function alchemy_gpio2_enable_int() for more information.
+ */
+static inline void alchemy_gpio2_disable_int(int gpio2)
+{
+        unsigned long flags;
+
+        gpio2 -= ALCHEMY_GPIO2_BASE;
+
+#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
+        /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
+        gpio2 -= 8;
+#endif
+        local_irq_save(flags);
+        __alchemy_gpio2_mod_int(gpio2, 0);
+        local_irq_restore(flags);
+}
+
+/**
+ * alchemy_gpio2_enable -  Activate GPIO2 block.
+ *
+ * The GPIO2 block must be enabled excplicitly to work.  On systems
+ * where this isn't done by the bootloader, this macro can be used.
+ */
+static inline void alchemy_gpio2_enable(void)
+{
+        au_writel(3, GPIO2_ENABLE);     /* reset, clock enabled */
+        au_sync();
+        au_writel(1, GPIO2_ENABLE);     /* clock enabled */
+        au_sync();
+}
+
+/**
+ * alchemy_gpio2_disable - disable GPIO2 block.
+ *
+ * Disable and put GPIO2 block in low-power mode.
+ */
+static inline void alchemy_gpio2_disable(void)
+{
+        au_writel(2, GPIO2_ENABLE);     /* reset, clock disabled */
+        au_sync();
+}
+
+/**********************************************************************/
+
+/* wrappers for on-chip gpios; can be used before gpio chips have been
+ * registered with gpiolib.
+ */
+static inline int alchemy_gpio_direction_input(int gpio)
+{
+        return (gpio >= ALCHEMY_GPIO2_BASE) ?
+                alchemy_gpio2_direction_input(gpio) :
+                alchemy_gpio1_direction_input(gpio);
+}
+
+static inline int alchemy_gpio_direction_output(int gpio, int v)
+{
+        return (gpio >= ALCHEMY_GPIO2_BASE) ?
+                alchemy_gpio2_direction_output(gpio, v) :
+                alchemy_gpio1_direction_output(gpio, v);
+}
+
+static inline int alchemy_gpio_get_value(int gpio)
+{
+        return (gpio >= ALCHEMY_GPIO2_BASE) ?
+                alchemy_gpio2_get_value(gpio) :
+                alchemy_gpio1_get_value(gpio);
+}
+
+static inline void alchemy_gpio_set_value(int gpio, int v)
+{
+        if (gpio >= ALCHEMY_GPIO2_BASE)
+                alchemy_gpio2_set_value(gpio, v);
+        else
+                alchemy_gpio1_set_value(gpio, v);
+}
+
+static inline int alchemy_gpio_is_valid(int gpio)
+{
+        return (gpio >= ALCHEMY_GPIO2_BASE) ?
+                alchemy_gpio2_is_valid(gpio) :
+                alchemy_gpio1_is_valid(gpio);
+}
+
+static inline int alchemy_gpio_cansleep(int gpio)
+{
+        return 0;       /* Alchemy never gets tired */
+}
+
+static inline int alchemy_gpio_to_irq(int gpio)
+{
+        return (gpio >= ALCHEMY_GPIO2_BASE) ?
+                alchemy_gpio2_to_irq(gpio) :
+                alchemy_gpio1_to_irq(gpio);
+}
+
+static inline int alchemy_irq_to_gpio(int irq)
+{
+#if defined(CONFIG_SOC_AU1000)
+        return au1000_irq_to_gpio(irq);
+#elif defined(CONFIG_SOC_AU1100)
+        return au1100_irq_to_gpio(irq);
+#elif defined(CONFIG_SOC_AU1500)
+        return au1500_irq_to_gpio(irq);
+#elif defined(CONFIG_SOC_AU1550)
+        return au1550_irq_to_gpio(irq);
+#elif defined(CONFIG_SOC_AU1200)
+        return au1200_irq_to_gpio(irq);
+#else
+        return -ENXIO;
+#endif
+}
+
+/**********************************************************************/
+
+/* Linux gpio framework integration.
+ *
+ * 4 use cases of Au1000-Au1200 GPIOS:
+ *(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
+ *      Board must register gpiochips.
+ *(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
+ *      2 (1 for Au1000) gpio_chips are registered.
+ *
+ *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
+ *      the boards' gpio.h must provide the linux gpio wrapper functions,
+ *
+ *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
+ *      inlinable gpio functions are provided which enable access to the
+ *      Au1000 gpios only by using the numbers straight out of the data-
+ *      sheets.
+
+ * Cases 1 and 3 are intended for boards which want to provide their own
+ * GPIO namespace and -operations (i.e. for example you have 8 GPIOs
+ * which are in part provided by spare Au1000 GPIO pins and in part by
+ * an external FPGA but you still want them to be accssible in linux
+ * as gpio0-7. The board can of course use the alchemy_gpioX_* functions
+ * as required).
+ */
+
+#ifndef CONFIG_GPIOLIB
+
+
+#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT    /* case (4) */
+
+static inline int gpio_direction_input(int gpio)
+{
+        return alchemy_gpio_direction_input(gpio);
+}
+
+static inline int gpio_direction_output(int gpio, int v)
+{
+        return alchemy_gpio_direction_output(gpio, v);
+}
+
+static inline int gpio_get_value(int gpio)
+{
+        return alchemy_gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(int gpio, int v)
+{
+        alchemy_gpio_set_value(gpio, v);
+}
+
+static inline int gpio_is_valid(int gpio)
+{
+        return alchemy_gpio_is_valid(gpio);
+}
+
+static inline int gpio_cansleep(int gpio)
+{
+        return alchemy_gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(int gpio)
+{
+        return alchemy_gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(int irq)
+{
+        return alchemy_irq_to_gpio(irq);
+}
+
+#endif  /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
+
+
+#else   /* CONFIG GPIOLIB */
+
+
+ /* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
+#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT    /* case (2) */
+
+/* get everything through gpiolib */
+#define gpio_to_irq     __gpio_to_irq
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define irq_to_gpio     alchemy_irq_to_gpio
+
+#include <asm-generic/gpio.h>
+
+#endif  /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
+
+
+#endif  /* !CONFIG_GPIOLIB */
+
+#endif /* _ALCHEMY_GPIO_AU1000_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index 34d9b7279024..f9b7d41c659a 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -1,33 +1,10 @@
-#ifndef _AU1XXX_GPIO_H_
-#define _AU1XXX_GPIO_H_
+#ifndef _ALCHEMY_GPIO_H_
+#define _ALCHEMY_GPIO_H_
 
-#include <linux/types.h>
+#if defined(CONFIG_ALCHEMY_GPIO_AU1000)
 
-#define AU1XXX_GPIO_BASE        200
+#include <asm/mach-au1x00/gpio-au1000.h>
 
-/* GPIO bank 1 offsets */
-#define AU1000_GPIO1_TRI_OUT    0x0100
-#define AU1000_GPIO1_OUT        0x0108
-#define AU1000_GPIO1_ST         0x0110
-#define AU1000_GPIO1_CLR        0x010C
+#endif
 
-/* GPIO bank 2 offsets */
-#define AU1000_GPIO2_DIR        0x00
-#define AU1000_GPIO2_RSVD       0x04
-#define AU1000_GPIO2_OUT        0x08
-#define AU1000_GPIO2_ST         0x0C
-#define AU1000_GPIO2_INT        0x10
-#define AU1000_GPIO2_EN         0x14
-
-#define GPIO2_OUT_EN_MASK       0x00010000
-
-#define gpio_to_irq(gpio)       NULL
-
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
-
-#define gpio_cansleep __gpio_cansleep
-
-#include <asm-generic/gpio.h>
-
-#endif /* _AU1XXX_GPIO_H_ */
+#endif  /* _ALCHEMY_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h
index 1784fde2e28f..98504142124e 100644
--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
@@ -37,6 +37,9 @@ static inline int gpio_direction_input(unsigned gpio)
 
 static inline int gpio_direction_output(unsigned gpio, int value)
 {
+        /* first set the gpio out value */
+        ssb_gpio_out(&ssb_bcm47xx, 1 << gpio, value ? 1 << gpio : 0);
+        /* then set the gpio mode */
         ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio);
         return 0;
 }
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 04ce6e6569da..3d830756b13a 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -47,11 +47,13 @@
 #define cpu_has_mips32r2        0
 #define cpu_has_mips64r1        0
 #define cpu_has_mips64r2        1
+#define cpu_has_mips_r2_exec_hazard 0
 #define cpu_has_dsp             0
 #define cpu_has_mipsmt          0
 #define cpu_has_userlocal       0
 #define cpu_has_vint            0
 #define cpu_has_veic            0
+#define cpu_hwrena_impl_bits    0xc0000000
 #define ARCH_HAS_READ_CURRENT_TIMER 1
 #define ARCH_HAS_IRQ_PER_CPU    1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index f30fce92aabb..17d579471ec4 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -30,12 +30,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
         return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
 }
 
-static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
+        dma_addr_t dma_addr)
 {
         return dma_addr;
 }
 
-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction)
 {
         octeon_unmap_dma_mem(dev, dma_addr);
 }
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 36c611b6c597..8da98073e952 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -23,12 +23,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
         return page_to_phys(page);
 }
 
-static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
+        dma_addr_t dma_addr)
 {
         return dma_addr;
 }
 
-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction)
 {
 }
 
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index 4c21bfca10c3..d3d04018a858 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -33,12 +33,14 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
         return pa;
 }
 
-static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static unsigned long plat_dma_addr_to_phys(struct device *dev,
+        dma_addr_t dma_addr)
 {
         return dma_addr & ~(0xffUL << 56);
 }
 
-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction)
 {
 }
 
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 7ae40f4b1c80..37855955b313 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -50,7 +50,8 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
 }
 
 /* This is almost certainly wrong but it's what dma-ip32.c used to use  */
-static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static unsigned long plat_dma_addr_to_phys(struct device *dev,
+        dma_addr_t dma_addr)
 {
         unsigned long addr = dma_addr & RAM_OFFSET_MASK;
 
@@ -60,7 +61,8 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
         return addr;
 }
 
-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction)
 {
 }
 
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index 1c7cd27efa7b..f93aee59454a 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -22,12 +22,14 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
         return vdma_alloc(page_to_phys(page), PAGE_SIZE);
 }
 
-static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static unsigned long plat_dma_addr_to_phys(struct device *dev,
+        dma_addr_t dma_addr)
 {
         return vdma_log2phys(dma_addr);
 }
 
-static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction)
 {
         vdma_free(dma_addr);
 }
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h
index 38fad7dfe7da..c8de5e750777 100644
--- a/arch/mips/include/asm/mach-lemote/dma-coherence.h
+++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h
@@ -25,12 +25,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
         return page_to_phys(page) | 0x80000000;
 }
 
-static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
+        dma_addr_t dma_addr)
 {
         return dma_addr & 0x7fffffff;
 }
 
-static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+        size_t size, enum dma_data_direction direction)
 {
 }
 
diff --git a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
index f3bc7efa2608..c3e4d3a4c95d 100644
--- a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
@@ -53,11 +53,6 @@
 #define cpu_has_smartmips               0
 
 #define cpu_has_vtag_icache             0
-/* #define cpu_has_dc_aliases           ? */
-/* #define cpu_has_ic_fills_f_dc        ? */
-/* #define cpu_has_pindexed_dcache      ? */
-
-/* #define cpu_icache_snoops_remote_store       ? */
 
 #define cpu_has_mips32r1                1
 #define cpu_has_mips32r2                0
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 32ef8bec5c85..a581d60cbcc2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -220,6 +220,22 @@
 #error Bad page size configuration!
 #endif
 
+/*
+ * Default huge tlb size for a given kernel configuration
+ */
+#ifdef CONFIG_PAGE_SIZE_4KB
+#define PM_HUGE_MASK    PM_1M
+#elif defined(CONFIG_PAGE_SIZE_8KB)
+#define PM_HUGE_MASK    PM_4M
+#elif defined(CONFIG_PAGE_SIZE_16KB)
+#define PM_HUGE_MASK    PM_16M
+#elif defined(CONFIG_PAGE_SIZE_32KB)
+#define PM_HUGE_MASK    PM_64M
+#elif defined(CONFIG_PAGE_SIZE_64KB)
+#define PM_HUGE_MASK    PM_256M
+#elif defined(CONFIG_HUGETLB_PAGE)
+#error Bad page size configuration for hugetlbfs!
+#endif
 
 /*
  * Values used for computation of new tlb entries
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index d7f3eb03ad12..d3bea88d8744 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -13,6 +13,7 @@
 
 #include <linux/errno.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/slab.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 692989acd8a9..f3c23a43f845 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -157,6 +157,13 @@ enum cvmx_board_types_enum {
         CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
         CVMX_BOARD_TYPE_EBT5600 = 22,
         CVMX_BOARD_TYPE_EBH5201 = 23,
+        CVMX_BOARD_TYPE_EBT5200 = 24,
+        CVMX_BOARD_TYPE_CB5600  = 25,
+        CVMX_BOARD_TYPE_CB5601  = 26,
+        CVMX_BOARD_TYPE_CB5200  = 27,
+        /* Special 'generic' board type, supports many boards */
+        CVMX_BOARD_TYPE_GENERIC = 28,
+        CVMX_BOARD_TYPE_EBH5610 = 29,
         CVMX_BOARD_TYPE_MAX,
 
         /*
@@ -228,6 +235,12 @@ static inline const char *cvmx_board_type_to_string(enum
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
+                ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
                 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
 
                         /* Customer boards listed here */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 1cbe4b55889d..8e708bdb43f7 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -183,6 +183,64 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
  * Returns 0 on failure,
  *         !0 on success
  */
+
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table.  (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @size:      Size in bytes of block to allocate
+ * @alignment: Alignment required - must be power of 2
+ * @name:      name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * Returns a pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment,
+                                      char *name);
+
+
+
+/**
+ * Allocate a block of memory from the free list that was passed
+ * to the application by the bootloader, and assign it a name in the
+ * global named block table.  (part of the cvmx_bootmem_descriptor_t structure)
+ * Named blocks can later be freed.
+ *
+ * @size:     Size in bytes of block to allocate
+ * @address:  Physical address to allocate memory at.  If this
+ *            memory is not available, the allocation fails.
+ * @name:     name of block - must be less than CVMX_BOOTMEM_NAME_LEN
+ *            bytes
+ *
+ * Returns a pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
+                                              char *name);
+
+
+
+/**
+ * Allocate a block of memory from a specific range of the free list
+ * that was passed to the application by the bootloader, and assign it
+ * a name in the global named block table.  (part of the
+ * cvmx_bootmem_descriptor_t structure) Named blocks can later be
+ * freed.  If request cannot be satisfied within the address range
+ * specified, NULL is returned
+ *
+ * @size:      Size in bytes of block to allocate
+ * @min_addr:  minimum address of range
+ * @max_addr:  maximum address of range
+ * @align:     Alignment of memory to be allocated. (must be a power of 2)
+ * @name:      name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ *
+ * Returns a pointer to block of memory, NULL on error
+ */
+extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
+                                            uint64_t max_addr, uint64_t align,
+                                            char *name);
+
 extern int cvmx_bootmem_free_named(char *name);
 
 /**
@@ -224,6 +282,33 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
                                uint32_t flags);
 
 /**
+ * Allocates a named block of physical memory from the free list, at
+ * (optional) requested address and alignment.
+ *
+ * @param size      size of region to allocate.  All requests are rounded
+ *                  up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE
+ *                  bytes size
+ * @param min_addr Minimum address that block can occupy.
+ * @param max_addr  Specifies the maximum address_min (inclusive) that
+ *                  the allocation can use.
+ * @param alignment Requested alignment of the block.  If this
+ *                  alignment cannot be met, the allocation fails.
+ *                  This must be a power of 2.  (Note: Alignment of
+ *                  CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
+ *                  internally enforced.  Requested alignments of less
+ *                  than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
+ *                  CVMX_BOOTMEM_ALIGNMENT_SIZE.)
+ * @param name      name to assign to named block
+ * @param flags     Flags to control options for the allocation.
+ *
+ * @return physical address of block allocated, or -1 on failure
+ */
+int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
+                                           uint64_t max_addr,
+                                           uint64_t alignment,
+                                           char *name, uint32_t flags);
+
+/**
  * Finds a named memory block by name.
  * Also used for finding an unused entry in the named block table.
  *
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-errata.h b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
new file mode 100644
index 000000000000..5fc99189ff58
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
@@ -0,0 +1,33 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_HELPER_ERRATA_H__
+#define __CVMX_HELPER_ERRATA_H__
+
+extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-jtag.h b/arch/mips/include/asm/octeon/cvmx-helper-jtag.h
new file mode 100644
index 000000000000..29f016ddb895
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-jtag.h
@@ -0,0 +1,43 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ *  Helper utilities for qlm_jtag.
+ *
+ */
+
+#ifndef __CVMX_HELPER_JTAG_H__
+#define __CVMX_HELPER_JTAG_H__
+
+extern void cvmx_helper_qlm_jtag_init(void);
+extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data);
+extern void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);
+extern void cvmx_helper_qlm_jtag_update(int qlm);
+
+#endif /* __CVMX_HELPER_JTAG_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
new file mode 100644
index 000000000000..4b347bb8ce80
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -0,0 +1,2560 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_NPEI_DEFS_H__
+#define __CVMX_NPEI_DEFS_H__
+
+#define CVMX_NPEI_BAR1_INDEXX(offset) \
+         (0x0000000000000000ull + (((offset) & 31) * 16))
+#define CVMX_NPEI_BIST_STATUS \
+         (0x0000000000000580ull)
+#define CVMX_NPEI_BIST_STATUS2 \
+         (0x0000000000000680ull)
+#define CVMX_NPEI_CTL_PORT0 \
+         (0x0000000000000250ull)
+#define CVMX_NPEI_CTL_PORT1 \
+         (0x0000000000000260ull)
+#define CVMX_NPEI_CTL_STATUS \
+         (0x0000000000000570ull)
+#define CVMX_NPEI_CTL_STATUS2 \
+         (0x0000000000003C00ull)
+#define CVMX_NPEI_DATA_OUT_CNT \
+         (0x00000000000005F0ull)
+#define CVMX_NPEI_DBG_DATA \
+         (0x0000000000000510ull)
+#define CVMX_NPEI_DBG_SELECT \
+         (0x0000000000000500ull)
+#define CVMX_NPEI_DMA0_INT_LEVEL \
+         (0x00000000000005C0ull)
+#define CVMX_NPEI_DMA1_INT_LEVEL \
+         (0x00000000000005D0ull)
+#define CVMX_NPEI_DMAX_COUNTS(offset) \
+         (0x0000000000000450ull + (((offset) & 7) * 16))
+#define CVMX_NPEI_DMAX_DBELL(offset) \
+         (0x00000000000003B0ull + (((offset) & 7) * 16))
+#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
+         (0x0000000000000400ull + (((offset) & 7) * 16))
+#define CVMX_NPEI_DMAX_NADDR(offset) \
+         (0x00000000000004A0ull + (((offset) & 7) * 16))
+#define CVMX_NPEI_DMA_CNTS \
+         (0x00000000000005E0ull)
+#define CVMX_NPEI_DMA_CONTROL \
+         (0x00000000000003A0ull)
+#define CVMX_NPEI_INT_A_ENB \
+         (0x0000000000000560ull)
+#define CVMX_NPEI_INT_A_ENB2 \
+         (0x0000000000003CE0ull)
+#define CVMX_NPEI_INT_A_SUM \
+         (0x0000000000000550ull)
+#define CVMX_NPEI_INT_ENB \
+         (0x0000000000000540ull)
+#define CVMX_NPEI_INT_ENB2 \
+         (0x0000000000003CD0ull)
+#define CVMX_NPEI_INT_INFO \
+         (0x0000000000000590ull)
+#define CVMX_NPEI_INT_SUM \
+         (0x0000000000000530ull)
+#define CVMX_NPEI_INT_SUM2 \
+         (0x0000000000003CC0ull)
+#define CVMX_NPEI_LAST_WIN_RDATA0 \
+         (0x0000000000000600ull)
+#define CVMX_NPEI_LAST_WIN_RDATA1 \
+         (0x0000000000000610ull)
+#define CVMX_NPEI_MEM_ACCESS_CTL \
+         (0x00000000000004F0ull)
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
+         (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
+#define CVMX_NPEI_MSI_ENB0 \
+         (0x0000000000003C50ull)
+#define CVMX_NPEI_MSI_ENB1 \
+         (0x0000000000003C60ull)
+#define CVMX_NPEI_MSI_ENB2 \
+         (0x0000000000003C70ull)
+#define CVMX_NPEI_MSI_ENB3 \
+         (0x0000000000003C80ull)
+#define CVMX_NPEI_MSI_RCV0 \
+         (0x0000000000003C10ull)
+#define CVMX_NPEI_MSI_RCV1 \
+         (0x0000000000003C20ull)
+#define CVMX_NPEI_MSI_RCV2 \
+         (0x0000000000003C30ull)
+#define CVMX_NPEI_MSI_RCV3 \
+         (0x0000000000003C40ull)
+#define CVMX_NPEI_MSI_RD_MAP \
+         (0x0000000000003CA0ull)
+#define CVMX_NPEI_MSI_W1C_ENB0 \
+         (0x0000000000003CF0ull)
+#define CVMX_NPEI_MSI_W1C_ENB1 \
+         (0x0000000000003D00ull)
+#define CVMX_NPEI_MSI_W1C_ENB2 \
+         (0x0000000000003D10ull)
+#define CVMX_NPEI_MSI_W1C_ENB3 \
+         (0x0000000000003D20ull)
+#define CVMX_NPEI_MSI_W1S_ENB0 \
+         (0x0000000000003D30ull)
+#define CVMX_NPEI_MSI_W1S_ENB1 \
+         (0x0000000000003D40ull)
+#define CVMX_NPEI_MSI_W1S_ENB2 \
+         (0x0000000000003D50ull)
+#define CVMX_NPEI_MSI_W1S_ENB3 \
+         (0x0000000000003D60ull)
+#define CVMX_NPEI_MSI_WR_MAP \
+         (0x0000000000003C90ull)
+#define CVMX_NPEI_PCIE_CREDIT_CNT \
+         (0x0000000000003D70ull)
+#define CVMX_NPEI_PCIE_MSI_RCV \
+         (0x0000000000003CB0ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B1 \
+         (0x0000000000000650ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B2 \
+         (0x0000000000000660ull)
+#define CVMX_NPEI_PCIE_MSI_RCV_B3 \
+         (0x0000000000000670ull)
+#define CVMX_NPEI_PKTX_CNTS(offset) \
+         (0x0000000000002400ull + (((offset) & 31) * 16))
+#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
+         (0x0000000000002800ull + (((offset) & 31) * 16))
+#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
+         (0x0000000000002C00ull + (((offset) & 31) * 16))
+#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
+         (0x0000000000003000ull + (((offset) & 31) * 16))
+#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
+         (0x0000000000003400ull + (((offset) & 31) * 16))
+#define CVMX_NPEI_PKTX_IN_BP(offset) \
+         (0x0000000000003800ull + (((offset) & 31) * 16))
+#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
+         (0x0000000000001400ull + (((offset) & 31) * 16))
+#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
+         (0x0000000000001800ull + (((offset) & 31) * 16))
+#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
+         (0x0000000000001C00ull + (((offset) & 31) * 16))
+#define CVMX_NPEI_PKT_CNT_INT \
+         (0x0000000000001110ull)
+#define CVMX_NPEI_PKT_CNT_INT_ENB \
+         (0x0000000000001130ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ES \
+         (0x00000000000010B0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_NS \
+         (0x00000000000010A0ull)
+#define CVMX_NPEI_PKT_DATA_OUT_ROR \
+         (0x0000000000001090ull)
+#define CVMX_NPEI_PKT_DPADDR \
+         (0x0000000000001080ull)
+#define CVMX_NPEI_PKT_INPUT_CONTROL \
+         (0x0000000000001150ull)
+#define CVMX_NPEI_PKT_INSTR_ENB \
+         (0x0000000000001000ull)
+#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
+         (0x0000000000001190ull)
+#define CVMX_NPEI_PKT_INSTR_SIZE \
+         (0x0000000000001020ull)
+#define CVMX_NPEI_PKT_INT_LEVELS \
+         (0x0000000000001100ull)
+#define CVMX_NPEI_PKT_IN_BP \
+         (0x00000000000006B0ull)
+#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
+         (0x0000000000002000ull + (((offset) & 31) * 16))
+#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
+         (0x00000000000006A0ull)
+#define CVMX_NPEI_PKT_IN_PCIE_PORT \
+         (0x00000000000011A0ull)
+#define CVMX_NPEI_PKT_IPTR \
+         (0x0000000000001070ull)
+#define CVMX_NPEI_PKT_OUTPUT_WMARK \
+         (0x0000000000001160ull)
+#define CVMX_NPEI_PKT_OUT_BMODE \
+         (0x00000000000010D0ull)
+#define CVMX_NPEI_PKT_OUT_ENB \
+         (0x0000000000001010ull)
+#define CVMX_NPEI_PKT_PCIE_PORT \
+         (0x00000000000010E0ull)
+#define CVMX_NPEI_PKT_PORT_IN_RST \
+         (0x0000000000000690ull)
+#define CVMX_NPEI_PKT_SLIST_ES \
+         (0x0000000000001050ull)
+#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
+         (0x0000000000001180ull)
+#define CVMX_NPEI_PKT_SLIST_NS \
+         (0x0000000000001040ull)
+#define CVMX_NPEI_PKT_SLIST_ROR \
+         (0x0000000000001030ull)
+#define CVMX_NPEI_PKT_TIME_INT \
+         (0x0000000000001120ull)
+#define CVMX_NPEI_PKT_TIME_INT_ENB \
+         (0x0000000000001140ull)
+#define CVMX_NPEI_RSL_INT_BLOCKS \
+         (0x0000000000000520ull)
+#define CVMX_NPEI_SCRATCH_1 \
+         (0x0000000000000270ull)
+#define CVMX_NPEI_STATE1 \
+         (0x0000000000000620ull)
+#define CVMX_NPEI_STATE2 \
+         (0x0000000000000630ull)
+#define CVMX_NPEI_STATE3 \
+         (0x0000000000000640ull)
+#define CVMX_NPEI_WINDOW_CTL \
+         (0x0000000000000380ull)
+#define CVMX_NPEI_WIN_RD_ADDR \
+         (0x0000000000000210ull)
+#define CVMX_NPEI_WIN_RD_DATA \
+         (0x0000000000000240ull)
+#define CVMX_NPEI_WIN_WR_ADDR \
+         (0x0000000000000200ull)
+#define CVMX_NPEI_WIN_WR_DATA \
+         (0x0000000000000220ull)
+#define CVMX_NPEI_WIN_WR_MASK \
+         (0x0000000000000230ull)
+
+union cvmx_npei_bar1_indexx {
+        uint32_t u32;
+        struct cvmx_npei_bar1_indexx_s {
+                uint32_t reserved_18_31:14;
+                uint32_t addr_idx:14;
+                uint32_t ca:1;
+                uint32_t end_swp:2;
+                uint32_t addr_v:1;
+        } s;
+        struct cvmx_npei_bar1_indexx_s cn52xx;
+        struct cvmx_npei_bar1_indexx_s cn52xxp1;
+        struct cvmx_npei_bar1_indexx_s cn56xx;
+        struct cvmx_npei_bar1_indexx_s cn56xxp1;
+};
+
+union cvmx_npei_bist_status {
+        uint64_t u64;
+        struct cvmx_npei_bist_status_s {
+                uint64_t pkt_rdf:1;
+                uint64_t pkt_pmem:1;
+                uint64_t pkt_p1:1;
+                uint64_t reserved_60_60:1;
+                uint64_t pcr_gim:1;
+                uint64_t pkt_pif:1;
+                uint64_t pcsr_int:1;
+                uint64_t pcsr_im:1;
+                uint64_t pcsr_cnt:1;
+                uint64_t pcsr_id:1;
+                uint64_t pcsr_sl:1;
+                uint64_t reserved_50_52:3;
+                uint64_t pkt_ind:1;
+                uint64_t pkt_slm:1;
+                uint64_t reserved_36_47:12;
+                uint64_t d0_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d3_pst:1;
+                uint64_t reserved_31_31:1;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t p2n1_po:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t csm0:1;
+                uint64_t csm1:1;
+                uint64_t dif0:1;
+                uint64_t dif1:1;
+                uint64_t dif2:1;
+                uint64_t dif3:1;
+                uint64_t reserved_2_2:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+        } s;
+        struct cvmx_npei_bist_status_cn52xx {
+                uint64_t pkt_rdf:1;
+                uint64_t pkt_pmem:1;
+                uint64_t pkt_p1:1;
+                uint64_t reserved_60_60:1;
+                uint64_t pcr_gim:1;
+                uint64_t pkt_pif:1;
+                uint64_t pcsr_int:1;
+                uint64_t pcsr_im:1;
+                uint64_t pcsr_cnt:1;
+                uint64_t pcsr_id:1;
+                uint64_t pcsr_sl:1;
+                uint64_t pkt_imem:1;
+                uint64_t pkt_pfm:1;
+                uint64_t pkt_pof:1;
+                uint64_t reserved_48_49:2;
+                uint64_t pkt_pop0:1;
+                uint64_t pkt_pop1:1;
+                uint64_t d0_mem:1;
+                uint64_t d1_mem:1;
+                uint64_t d2_mem:1;
+                uint64_t d3_mem:1;
+                uint64_t d4_mem:1;
+                uint64_t ds_mem:1;
+                uint64_t reserved_36_39:4;
+                uint64_t d0_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d3_pst:1;
+                uint64_t d4_pst:1;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t p2n1_po:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t csm0:1;
+                uint64_t csm1:1;
+                uint64_t dif0:1;
+                uint64_t dif1:1;
+                uint64_t dif2:1;
+                uint64_t dif3:1;
+                uint64_t dif4:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+        } cn52xx;
+        struct cvmx_npei_bist_status_cn52xxp1 {
+                uint64_t reserved_46_63:18;
+                uint64_t d0_mem0:1;
+                uint64_t d1_mem1:1;
+                uint64_t d2_mem2:1;
+                uint64_t d3_mem3:1;
+                uint64_t dr0_mem:1;
+                uint64_t d0_mem:1;
+                uint64_t d1_mem:1;
+                uint64_t d2_mem:1;
+                uint64_t d3_mem:1;
+                uint64_t dr1_mem:1;
+                uint64_t d0_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d3_pst:1;
+                uint64_t dr2_mem:1;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t p2n1_po:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t csm0:1;
+                uint64_t csm1:1;
+                uint64_t dif0:1;
+                uint64_t dif1:1;
+                uint64_t dif2:1;
+                uint64_t dif3:1;
+                uint64_t dr3_mem:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+        } cn52xxp1;
+        struct cvmx_npei_bist_status_cn56xx {
+                uint64_t pkt_rdf:1;
+                uint64_t reserved_60_62:3;
+                uint64_t pcr_gim:1;
+                uint64_t pkt_pif:1;
+                uint64_t pcsr_int:1;
+                uint64_t pcsr_im:1;
+                uint64_t pcsr_cnt:1;
+                uint64_t pcsr_id:1;
+                uint64_t pcsr_sl:1;
+                uint64_t pkt_imem:1;
+                uint64_t pkt_pfm:1;
+                uint64_t pkt_pof:1;
+                uint64_t reserved_48_49:2;
+                uint64_t pkt_pop0:1;
+                uint64_t pkt_pop1:1;
+                uint64_t d0_mem:1;
+                uint64_t d1_mem:1;
+                uint64_t d2_mem:1;
+                uint64_t d3_mem:1;
+                uint64_t d4_mem:1;
+                uint64_t ds_mem:1;
+                uint64_t reserved_36_39:4;
+                uint64_t d0_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d3_pst:1;
+                uint64_t d4_pst:1;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t p2n1_po:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t csm0:1;
+                uint64_t csm1:1;
+                uint64_t dif0:1;
+                uint64_t dif1:1;
+                uint64_t dif2:1;
+                uint64_t dif3:1;
+                uint64_t dif4:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+        } cn56xx;
+        struct cvmx_npei_bist_status_cn56xxp1 {
+                uint64_t reserved_58_63:6;
+                uint64_t pcsr_int:1;
+                uint64_t pcsr_im:1;
+                uint64_t pcsr_cnt:1;
+                uint64_t pcsr_id:1;
+                uint64_t pcsr_sl:1;
+                uint64_t pkt_pout:1;
+                uint64_t pkt_imem:1;
+                uint64_t pkt_cntm:1;
+                uint64_t pkt_ind:1;
+                uint64_t pkt_slm:1;
+                uint64_t pkt_odf:1;
+                uint64_t pkt_oif:1;
+                uint64_t pkt_out:1;
+                uint64_t pkt_i0:1;
+                uint64_t pkt_i1:1;
+                uint64_t pkt_s0:1;
+                uint64_t pkt_s1:1;
+                uint64_t d0_mem:1;
+                uint64_t d1_mem:1;
+                uint64_t d2_mem:1;
+                uint64_t d3_mem:1;
+                uint64_t d4_mem:1;
+                uint64_t d0_pst:1;
+                uint64_t d1_pst:1;
+                uint64_t d2_pst:1;
+                uint64_t d3_pst:1;
+                uint64_t d4_pst:1;
+                uint64_t n2p0_c:1;
+                uint64_t n2p0_o:1;
+                uint64_t n2p1_c:1;
+                uint64_t n2p1_o:1;
+                uint64_t cpl_p0:1;
+                uint64_t cpl_p1:1;
+                uint64_t p2n1_po:1;
+                uint64_t p2n1_no:1;
+                uint64_t p2n1_co:1;
+                uint64_t p2n0_po:1;
+                uint64_t p2n0_no:1;
+                uint64_t p2n0_co:1;
+                uint64_t p2n0_c0:1;
+                uint64_t p2n0_c1:1;
+                uint64_t p2n0_n:1;
+                uint64_t p2n0_p0:1;
+                uint64_t p2n0_p1:1;
+                uint64_t p2n1_c0:1;
+                uint64_t p2n1_c1:1;
+                uint64_t p2n1_n:1;
+                uint64_t p2n1_p0:1;
+                uint64_t p2n1_p1:1;
+                uint64_t csm0:1;
+                uint64_t csm1:1;
+                uint64_t dif0:1;
+                uint64_t dif1:1;
+                uint64_t dif2:1;
+                uint64_t dif3:1;
+                uint64_t dif4:1;
+                uint64_t msi:1;
+                uint64_t ncb_cmd:1;
+        } cn56xxp1;
+};
+
+union cvmx_npei_bist_status2 {
+        uint64_t u64;
+        struct cvmx_npei_bist_status2_s {
+                uint64_t reserved_5_63:59;
+                uint64_t psc_p0:1;
+                uint64_t psc_p1:1;
+                uint64_t pkt_gd:1;
+                uint64_t pkt_gl:1;
+                uint64_t pkt_blk:1;
+        } s;
+        struct cvmx_npei_bist_status2_s cn52xx;
+        struct cvmx_npei_bist_status2_s cn56xx;
+};
+
+union cvmx_npei_ctl_port0 {
+        uint64_t u64;
+        struct cvmx_npei_ctl_port0_s {
+                uint64_t reserved_21_63:43;
+                uint64_t waitl_com:1;
+                uint64_t intd:1;
+                uint64_t intc:1;
+                uint64_t intb:1;
+                uint64_t inta:1;
+                uint64_t intd_map:2;
+                uint64_t intc_map:2;
+                uint64_t intb_map:2;
+                uint64_t inta_map:2;
+                uint64_t ctlp_ro:1;
+                uint64_t reserved_6_6:1;
+                uint64_t ptlp_ro:1;
+                uint64_t bar2_enb:1;
+                uint64_t bar2_esx:2;
+                uint64_t bar2_cax:1;
+                uint64_t wait_com:1;
+        } s;
+        struct cvmx_npei_ctl_port0_s cn52xx;
+        struct cvmx_npei_ctl_port0_s cn52xxp1;
+        struct cvmx_npei_ctl_port0_s cn56xx;
+        struct cvmx_npei_ctl_port0_s cn56xxp1;
+};
+
+union cvmx_npei_ctl_port1 {
+        uint64_t u64;
+        struct cvmx_npei_ctl_port1_s {
+                uint64_t reserved_21_63:43;
+                uint64_t waitl_com:1;
+                uint64_t intd:1;
+                uint64_t intc:1;
+                uint64_t intb:1;
+                uint64_t inta:1;
+                uint64_t intd_map:2;
+                uint64_t intc_map:2;
+                uint64_t intb_map:2;
+                uint64_t inta_map:2;
+                uint64_t ctlp_ro:1;
+                uint64_t reserved_6_6:1;
+                uint64_t ptlp_ro:1;
+                uint64_t bar2_enb:1;
+                uint64_t bar2_esx:2;
+                uint64_t bar2_cax:1;
+                uint64_t wait_com:1;
+        } s;
+        struct cvmx_npei_ctl_port1_s cn52xx;
+        struct cvmx_npei_ctl_port1_s cn52xxp1;
+        struct cvmx_npei_ctl_port1_s cn56xx;
+        struct cvmx_npei_ctl_port1_s cn56xxp1;
+};
+
+union cvmx_npei_ctl_status {
+        uint64_t u64;
+        struct cvmx_npei_ctl_status_s {
+                uint64_t reserved_44_63:20;
+                uint64_t p1_ntags:6;
+                uint64_t p0_ntags:6;
+                uint64_t cfg_rtry:16;
+                uint64_t ring_en:1;
+                uint64_t lnk_rst:1;
+                uint64_t arb:1;
+                uint64_t pkt_bp:4;
+                uint64_t host_mode:1;
+                uint64_t chip_rev:8;
+        } s;
+        struct cvmx_npei_ctl_status_s cn52xx;
+        struct cvmx_npei_ctl_status_cn52xxp1 {
+                uint64_t reserved_44_63:20;
+                uint64_t p1_ntags:6;
+                uint64_t p0_ntags:6;
+                uint64_t cfg_rtry:16;
+                uint64_t reserved_15_15:1;
+                uint64_t lnk_rst:1;
+                uint64_t arb:1;
+                uint64_t reserved_9_12:4;
+                uint64_t host_mode:1;
+                uint64_t chip_rev:8;
+        } cn52xxp1;
+        struct cvmx_npei_ctl_status_s cn56xx;
+        struct cvmx_npei_ctl_status_cn56xxp1 {
+                uint64_t reserved_16_63:48;
+                uint64_t ring_en:1;
+                uint64_t lnk_rst:1;
+                uint64_t arb:1;
+                uint64_t pkt_bp:4;
+                uint64_t host_mode:1;
+                uint64_t chip_rev:8;
+        } cn56xxp1;
+};
+
+union cvmx_npei_ctl_status2 {
+        uint64_t u64;
+        struct cvmx_npei_ctl_status2_s {
+                uint64_t reserved_16_63:48;
+                uint64_t mps:1;
+                uint64_t mrrs:3;
+                uint64_t c1_w_flt:1;
+                uint64_t c0_w_flt:1;
+                uint64_t c1_b1_s:3;
+                uint64_t c0_b1_s:3;
+                uint64_t c1_wi_d:1;
+                uint64_t c1_b0_d:1;
+                uint64_t c0_wi_d:1;
+                uint64_t c0_b0_d:1;
+        } s;
+        struct cvmx_npei_ctl_status2_s cn52xx;
+        struct cvmx_npei_ctl_status2_s cn52xxp1;
+        struct cvmx_npei_ctl_status2_s cn56xx;
+        struct cvmx_npei_ctl_status2_s cn56xxp1;
+};
+
+union cvmx_npei_data_out_cnt {
+        uint64_t u64;
+        struct cvmx_npei_data_out_cnt_s {
+                uint64_t reserved_44_63:20;
+                uint64_t p1_ucnt:16;
+                uint64_t p1_fcnt:6;
+                uint64_t p0_ucnt:16;
+                uint64_t p0_fcnt:6;
+        } s;
+        struct cvmx_npei_data_out_cnt_s cn52xx;
+        struct cvmx_npei_data_out_cnt_s cn52xxp1;
+        struct cvmx_npei_data_out_cnt_s cn56xx;
+        struct cvmx_npei_data_out_cnt_s cn56xxp1;
+};
+
+union cvmx_npei_dbg_data {
+        uint64_t u64;
+        struct cvmx_npei_dbg_data_s {
+                uint64_t reserved_28_63:36;
+                uint64_t qlm0_rev_lanes:1;
+                uint64_t reserved_25_26:2;
+                uint64_t qlm1_spd:2;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+        } s;
+        struct cvmx_npei_dbg_data_cn52xx {
+                uint64_t reserved_29_63:35;
+                uint64_t qlm0_link_width:1;
+                uint64_t qlm0_rev_lanes:1;
+                uint64_t qlm1_mode:2;
+                uint64_t qlm1_spd:2;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+        } cn52xx;
+        struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
+        struct cvmx_npei_dbg_data_cn56xx {
+                uint64_t reserved_29_63:35;
+                uint64_t qlm2_rev_lanes:1;
+                uint64_t qlm0_rev_lanes:1;
+                uint64_t qlm3_spd:2;
+                uint64_t qlm1_spd:2;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+        } cn56xx;
+        struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
+};
+
+union cvmx_npei_dbg_select {
+        uint64_t u64;
+        struct cvmx_npei_dbg_select_s {
+                uint64_t reserved_16_63:48;
+                uint64_t dbg_sel:16;
+        } s;
+        struct cvmx_npei_dbg_select_s cn52xx;
+        struct cvmx_npei_dbg_select_s cn52xxp1;
+        struct cvmx_npei_dbg_select_s cn56xx;
+        struct cvmx_npei_dbg_select_s cn56xxp1;
+};
+
+union cvmx_npei_dmax_counts {
+        uint64_t u64;
+        struct cvmx_npei_dmax_counts_s {
+                uint64_t reserved_39_63:25;
+                uint64_t fcnt:7;
+                uint64_t dbell:32;
+        } s;
+        struct cvmx_npei_dmax_counts_s cn52xx;
+        struct cvmx_npei_dmax_counts_s cn52xxp1;
+        struct cvmx_npei_dmax_counts_s cn56xx;
+        struct cvmx_npei_dmax_counts_s cn56xxp1;
+};
+
+union cvmx_npei_dmax_dbell {
+        uint32_t u32;
+        struct cvmx_npei_dmax_dbell_s {
+                uint32_t reserved_16_31:16;
+                uint32_t dbell:16;
+        } s;
+        struct cvmx_npei_dmax_dbell_s cn52xx;
+        struct cvmx_npei_dmax_dbell_s cn52xxp1;
+        struct cvmx_npei_dmax_dbell_s cn56xx;
+        struct cvmx_npei_dmax_dbell_s cn56xxp1;
+};
+
+union cvmx_npei_dmax_ibuff_saddr {
+        uint64_t u64;
+        struct cvmx_npei_dmax_ibuff_saddr_s {
+                uint64_t reserved_37_63:27;
+                uint64_t idle:1;
+                uint64_t saddr:29;
+                uint64_t reserved_0_6:7;
+        } s;
+        struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
+                uint64_t reserved_36_63:28;
+                uint64_t saddr:29;
+                uint64_t reserved_0_6:7;
+        } cn52xx;
+        struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
+        struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
+        struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
+};
+
+union cvmx_npei_dmax_naddr {
+        uint64_t u64;
+        struct cvmx_npei_dmax_naddr_s {
+                uint64_t reserved_36_63:28;
+                uint64_t addr:36;
+        } s;
+        struct cvmx_npei_dmax_naddr_s cn52xx;
+        struct cvmx_npei_dmax_naddr_s cn52xxp1;
+        struct cvmx_npei_dmax_naddr_s cn56xx;
+        struct cvmx_npei_dmax_naddr_s cn56xxp1;
+};
+
+union cvmx_npei_dma0_int_level {
+        uint64_t u64;
+        struct cvmx_npei_dma0_int_level_s {
+                uint64_t time:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_npei_dma0_int_level_s cn52xx;
+        struct cvmx_npei_dma0_int_level_s cn52xxp1;
+        struct cvmx_npei_dma0_int_level_s cn56xx;
+        struct cvmx_npei_dma0_int_level_s cn56xxp1;
+};
+
+union cvmx_npei_dma1_int_level {
+        uint64_t u64;
+        struct cvmx_npei_dma1_int_level_s {
+                uint64_t time:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_npei_dma1_int_level_s cn52xx;
+        struct cvmx_npei_dma1_int_level_s cn52xxp1;
+        struct cvmx_npei_dma1_int_level_s cn56xx;
+        struct cvmx_npei_dma1_int_level_s cn56xxp1;
+};
+
+union cvmx_npei_dma_cnts {
+        uint64_t u64;
+        struct cvmx_npei_dma_cnts_s {
+                uint64_t dma1:32;
+                uint64_t dma0:32;
+        } s;
+        struct cvmx_npei_dma_cnts_s cn52xx;
+        struct cvmx_npei_dma_cnts_s cn52xxp1;
+        struct cvmx_npei_dma_cnts_s cn56xx;
+        struct cvmx_npei_dma_cnts_s cn56xxp1;
+};
+
+union cvmx_npei_dma_control {
+        uint64_t u64;
+        struct cvmx_npei_dma_control_s {
+                uint64_t reserved_39_63:25;
+                uint64_t dma4_enb:1;
+                uint64_t dma3_enb:1;
+                uint64_t dma2_enb:1;
+                uint64_t dma1_enb:1;
+                uint64_t dma0_enb:1;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t csize:14;
+        } s;
+        struct cvmx_npei_dma_control_s cn52xx;
+        struct cvmx_npei_dma_control_cn52xxp1 {
+                uint64_t reserved_38_63:26;
+                uint64_t dma3_enb:1;
+                uint64_t dma2_enb:1;
+                uint64_t dma1_enb:1;
+                uint64_t dma0_enb:1;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t csize:14;
+        } cn52xxp1;
+        struct cvmx_npei_dma_control_s cn56xx;
+        struct cvmx_npei_dma_control_s cn56xxp1;
+};
+
+union cvmx_npei_int_a_enb {
+        uint64_t u64;
+        struct cvmx_npei_int_a_enb_s {
+                uint64_t reserved_10_63:54;
+                uint64_t pout_err:1;
+                uint64_t pin_bp:1;
+                uint64_t p1_rdlk:1;
+                uint64_t p0_rdlk:1;
+                uint64_t pgl_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pop_err:1;
+                uint64_t pins_err:1;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+        } s;
+        struct cvmx_npei_int_a_enb_cn52xx {
+                uint64_t reserved_8_63:56;
+                uint64_t p1_rdlk:1;
+                uint64_t p0_rdlk:1;
+                uint64_t pgl_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pop_err:1;
+                uint64_t pins_err:1;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+        } cn52xx;
+        struct cvmx_npei_int_a_enb_cn52xxp1 {
+                uint64_t reserved_2_63:62;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+        } cn52xxp1;
+        struct cvmx_npei_int_a_enb_s cn56xx;
+};
+
+union cvmx_npei_int_a_enb2 {
+        uint64_t u64;
+        struct cvmx_npei_int_a_enb2_s {
+                uint64_t reserved_10_63:54;
+                uint64_t pout_err:1;
+                uint64_t pin_bp:1;
+                uint64_t p1_rdlk:1;
+                uint64_t p0_rdlk:1;
+                uint64_t pgl_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pop_err:1;
+                uint64_t pins_err:1;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+        } s;
+        struct cvmx_npei_int_a_enb2_cn52xx {
+                uint64_t reserved_8_63:56;
+                uint64_t p1_rdlk:1;
+                uint64_t p0_rdlk:1;
+                uint64_t pgl_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pop_err:1;
+                uint64_t pins_err:1;
+                uint64_t reserved_0_1:2;
+        } cn52xx;
+        struct cvmx_npei_int_a_enb2_cn52xxp1 {
+                uint64_t reserved_2_63:62;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+        } cn52xxp1;
+        struct cvmx_npei_int_a_enb2_s cn56xx;
+};
+
+union cvmx_npei_int_a_sum {
+        uint64_t u64;
+        struct cvmx_npei_int_a_sum_s {
+                uint64_t reserved_10_63:54;
+                uint64_t pout_err:1;
+                uint64_t pin_bp:1;
+                uint64_t p1_rdlk:1;
+                uint64_t p0_rdlk:1;
+                uint64_t pgl_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pop_err:1;
+                uint64_t pins_err:1;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+        } s;
+        struct cvmx_npei_int_a_sum_cn52xx {
+                uint64_t reserved_8_63:56;
+                uint64_t p1_rdlk:1;
+                uint64_t p0_rdlk:1;
+                uint64_t pgl_err:1;
+                uint64_t pdi_err:1;
+                uint64_t pop_err:1;
+                uint64_t pins_err:1;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+        } cn52xx;
+        struct cvmx_npei_int_a_sum_cn52xxp1 {
+                uint64_t reserved_2_63:62;
+                uint64_t dma1_cpl:1;
+                uint64_t dma0_cpl:1;
+        } cn52xxp1;
+        struct cvmx_npei_int_a_sum_s cn56xx;
+};
+
+union cvmx_npei_int_enb {
+        uint64_t u64;
+        struct cvmx_npei_int_enb_s {
+                uint64_t mio_inta:1;
+                uint64_t reserved_62_62:1;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } s;
+        struct cvmx_npei_int_enb_s cn52xx;
+        struct cvmx_npei_int_enb_cn52xxp1 {
+                uint64_t mio_inta:1;
+                uint64_t reserved_62_62:1;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn52xxp1;
+        struct cvmx_npei_int_enb_s cn56xx;
+        struct cvmx_npei_int_enb_cn56xxp1 {
+                uint64_t mio_inta:1;
+                uint64_t reserved_61_62:2;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t reserved_29_29:1;
+                uint64_t c1_se:1;
+                uint64_t reserved_27_27:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t reserved_22_22:1;
+                uint64_t c0_se:1;
+                uint64_t reserved_20_20:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn56xxp1;
+};
+
+union cvmx_npei_int_enb2 {
+        uint64_t u64;
+        struct cvmx_npei_int_enb2_s {
+                uint64_t reserved_62_63:2;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } s;
+        struct cvmx_npei_int_enb2_s cn52xx;
+        struct cvmx_npei_int_enb2_cn52xxp1 {
+                uint64_t reserved_62_63:2;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn52xxp1;
+        struct cvmx_npei_int_enb2_s cn56xx;
+        struct cvmx_npei_int_enb2_cn56xxp1 {
+                uint64_t reserved_61_63:3;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t reserved_29_29:1;
+                uint64_t c1_se:1;
+                uint64_t reserved_27_27:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t reserved_22_22:1;
+                uint64_t c0_se:1;
+                uint64_t reserved_20_20:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn56xxp1;
+};
+
+union cvmx_npei_int_info {
+        uint64_t u64;
+        struct cvmx_npei_int_info_s {
+                uint64_t reserved_12_63:52;
+                uint64_t pidbof:6;
+                uint64_t psldbof:6;
+        } s;
+        struct cvmx_npei_int_info_s cn52xx;
+        struct cvmx_npei_int_info_s cn56xx;
+        struct cvmx_npei_int_info_s cn56xxp1;
+};
+
+union cvmx_npei_int_sum {
+        uint64_t u64;
+        struct cvmx_npei_int_sum_s {
+                uint64_t mio_inta:1;
+                uint64_t reserved_62_62:1;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } s;
+        struct cvmx_npei_int_sum_s cn52xx;
+        struct cvmx_npei_int_sum_cn52xxp1 {
+                uint64_t mio_inta:1;
+                uint64_t reserved_62_62:1;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t reserved_15_18:4;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn52xxp1;
+        struct cvmx_npei_int_sum_s cn56xx;
+        struct cvmx_npei_int_sum_cn56xxp1 {
+                uint64_t mio_inta:1;
+                uint64_t reserved_61_62:2;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t reserved_29_29:1;
+                uint64_t c1_se:1;
+                uint64_t reserved_27_27:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t reserved_22_22:1;
+                uint64_t c0_se:1;
+                uint64_t reserved_20_20:1;
+                uint64_t c0_aeri:1;
+                uint64_t ptime:1;
+                uint64_t pcnt:1;
+                uint64_t pidbof:1;
+                uint64_t psldbof:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t dma4dbo:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn56xxp1;
+};
+
+union cvmx_npei_int_sum2 {
+        uint64_t u64;
+        struct cvmx_npei_int_sum2_s {
+                uint64_t mio_inta:1;
+                uint64_t reserved_62_62:1;
+                uint64_t int_a:1;
+                uint64_t c1_ldwn:1;
+                uint64_t c0_ldwn:1;
+                uint64_t c1_exc:1;
+                uint64_t c0_exc:1;
+                uint64_t c1_up_wf:1;
+                uint64_t c0_up_wf:1;
+                uint64_t c1_un_wf:1;
+                uint64_t c0_un_wf:1;
+                uint64_t c1_un_bx:1;
+                uint64_t c1_un_wi:1;
+                uint64_t c1_un_b2:1;
+                uint64_t c1_un_b1:1;
+                uint64_t c1_un_b0:1;
+                uint64_t c1_up_bx:1;
+                uint64_t c1_up_wi:1;
+                uint64_t c1_up_b2:1;
+                uint64_t c1_up_b1:1;
+                uint64_t c1_up_b0:1;
+                uint64_t c0_un_bx:1;
+                uint64_t c0_un_wi:1;
+                uint64_t c0_un_b2:1;
+                uint64_t c0_un_b1:1;
+                uint64_t c0_un_b0:1;
+                uint64_t c0_up_bx:1;
+                uint64_t c0_up_wi:1;
+                uint64_t c0_up_b2:1;
+                uint64_t c0_up_b1:1;
+                uint64_t c0_up_b0:1;
+                uint64_t c1_hpint:1;
+                uint64_t c1_pmei:1;
+                uint64_t c1_wake:1;
+                uint64_t crs1_dr:1;
+                uint64_t c1_se:1;
+                uint64_t crs1_er:1;
+                uint64_t c1_aeri:1;
+                uint64_t c0_hpint:1;
+                uint64_t c0_pmei:1;
+                uint64_t c0_wake:1;
+                uint64_t crs0_dr:1;
+                uint64_t c0_se:1;
+                uint64_t crs0_er:1;
+                uint64_t c0_aeri:1;
+                uint64_t reserved_15_18:4;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t dma1fi:1;
+                uint64_t dma0fi:1;
+                uint64_t reserved_8_8:1;
+                uint64_t dma3dbo:1;
+                uint64_t dma2dbo:1;
+                uint64_t dma1dbo:1;
+                uint64_t dma0dbo:1;
+                uint64_t iob2big:1;
+                uint64_t bar0_to:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } s;
+        struct cvmx_npei_int_sum2_s cn52xx;
+        struct cvmx_npei_int_sum2_s cn52xxp1;
+        struct cvmx_npei_int_sum2_s cn56xx;
+};
+
+union cvmx_npei_last_win_rdata0 {
+        uint64_t u64;
+        struct cvmx_npei_last_win_rdata0_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_npei_last_win_rdata0_s cn52xx;
+        struct cvmx_npei_last_win_rdata0_s cn52xxp1;
+        struct cvmx_npei_last_win_rdata0_s cn56xx;
+        struct cvmx_npei_last_win_rdata0_s cn56xxp1;
+};
+
+union cvmx_npei_last_win_rdata1 {
+        uint64_t u64;
+        struct cvmx_npei_last_win_rdata1_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_npei_last_win_rdata1_s cn52xx;
+        struct cvmx_npei_last_win_rdata1_s cn52xxp1;
+        struct cvmx_npei_last_win_rdata1_s cn56xx;
+        struct cvmx_npei_last_win_rdata1_s cn56xxp1;
+};
+
+union cvmx_npei_mem_access_ctl {
+        uint64_t u64;
+        struct cvmx_npei_mem_access_ctl_s {
+                uint64_t reserved_14_63:50;
+                uint64_t max_word:4;
+                uint64_t timer:10;
+        } s;
+        struct cvmx_npei_mem_access_ctl_s cn52xx;
+        struct cvmx_npei_mem_access_ctl_s cn52xxp1;
+        struct cvmx_npei_mem_access_ctl_s cn56xx;
+        struct cvmx_npei_mem_access_ctl_s cn56xxp1;
+};
+
+union cvmx_npei_mem_access_subidx {
+        uint64_t u64;
+        struct cvmx_npei_mem_access_subidx_s {
+                uint64_t reserved_42_63:22;
+                uint64_t zero:1;
+                uint64_t port:2;
+                uint64_t nmerge:1;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t nsr:1;
+                uint64_t nsw:1;
+                uint64_t ror:1;
+                uint64_t row:1;
+                uint64_t ba:30;
+        } s;
+        struct cvmx_npei_mem_access_subidx_s cn52xx;
+        struct cvmx_npei_mem_access_subidx_s cn52xxp1;
+        struct cvmx_npei_mem_access_subidx_s cn56xx;
+        struct cvmx_npei_mem_access_subidx_s cn56xxp1;
+};
+
+union cvmx_npei_msi_enb0 {
+        uint64_t u64;
+        struct cvmx_npei_msi_enb0_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_npei_msi_enb0_s cn52xx;
+        struct cvmx_npei_msi_enb0_s cn52xxp1;
+        struct cvmx_npei_msi_enb0_s cn56xx;
+        struct cvmx_npei_msi_enb0_s cn56xxp1;
+};
+
+union cvmx_npei_msi_enb1 {
+        uint64_t u64;
+        struct cvmx_npei_msi_enb1_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_npei_msi_enb1_s cn52xx;
+        struct cvmx_npei_msi_enb1_s cn52xxp1;
+        struct cvmx_npei_msi_enb1_s cn56xx;
+        struct cvmx_npei_msi_enb1_s cn56xxp1;
+};
+
+union cvmx_npei_msi_enb2 {
+        uint64_t u64;
+        struct cvmx_npei_msi_enb2_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_npei_msi_enb2_s cn52xx;
+        struct cvmx_npei_msi_enb2_s cn52xxp1;
+        struct cvmx_npei_msi_enb2_s cn56xx;
+        struct cvmx_npei_msi_enb2_s cn56xxp1;
+};
+
+union cvmx_npei_msi_enb3 {
+        uint64_t u64;
+        struct cvmx_npei_msi_enb3_s {
+                uint64_t enb:64;
+        } s;
+        struct cvmx_npei_msi_enb3_s cn52xx;
+        struct cvmx_npei_msi_enb3_s cn52xxp1;
+        struct cvmx_npei_msi_enb3_s cn56xx;
+        struct cvmx_npei_msi_enb3_s cn56xxp1;
+};
+
+union cvmx_npei_msi_rcv0 {
+        uint64_t u64;
+        struct cvmx_npei_msi_rcv0_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_npei_msi_rcv0_s cn52xx;
+        struct cvmx_npei_msi_rcv0_s cn52xxp1;
+        struct cvmx_npei_msi_rcv0_s cn56xx;
+        struct cvmx_npei_msi_rcv0_s cn56xxp1;
+};
+
+union cvmx_npei_msi_rcv1 {
+        uint64_t u64;
+        struct cvmx_npei_msi_rcv1_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_npei_msi_rcv1_s cn52xx;
+        struct cvmx_npei_msi_rcv1_s cn52xxp1;
+        struct cvmx_npei_msi_rcv1_s cn56xx;
+        struct cvmx_npei_msi_rcv1_s cn56xxp1;
+};
+
+union cvmx_npei_msi_rcv2 {
+        uint64_t u64;
+        struct cvmx_npei_msi_rcv2_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_npei_msi_rcv2_s cn52xx;
+        struct cvmx_npei_msi_rcv2_s cn52xxp1;
+        struct cvmx_npei_msi_rcv2_s cn56xx;
+        struct cvmx_npei_msi_rcv2_s cn56xxp1;
+};
+
+union cvmx_npei_msi_rcv3 {
+        uint64_t u64;
+        struct cvmx_npei_msi_rcv3_s {
+                uint64_t intr:64;
+        } s;
+        struct cvmx_npei_msi_rcv3_s cn52xx;
+        struct cvmx_npei_msi_rcv3_s cn52xxp1;
+        struct cvmx_npei_msi_rcv3_s cn56xx;
+        struct cvmx_npei_msi_rcv3_s cn56xxp1;
+};
+
+union cvmx_npei_msi_rd_map {
+        uint64_t u64;
+        struct cvmx_npei_msi_rd_map_s {
+                uint64_t reserved_16_63:48;
+                uint64_t rd_int:8;
+                uint64_t msi_int:8;
+        } s;
+        struct cvmx_npei_msi_rd_map_s cn52xx;
+        struct cvmx_npei_msi_rd_map_s cn52xxp1;
+        struct cvmx_npei_msi_rd_map_s cn56xx;
+        struct cvmx_npei_msi_rd_map_s cn56xxp1;
+};
+
+union cvmx_npei_msi_w1c_enb0 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1c_enb0_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_npei_msi_w1c_enb0_s cn52xx;
+        struct cvmx_npei_msi_w1c_enb0_s cn56xx;
+};
+
+union cvmx_npei_msi_w1c_enb1 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1c_enb1_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_npei_msi_w1c_enb1_s cn52xx;
+        struct cvmx_npei_msi_w1c_enb1_s cn56xx;
+};
+
+union cvmx_npei_msi_w1c_enb2 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1c_enb2_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_npei_msi_w1c_enb2_s cn52xx;
+        struct cvmx_npei_msi_w1c_enb2_s cn56xx;
+};
+
+union cvmx_npei_msi_w1c_enb3 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1c_enb3_s {
+                uint64_t clr:64;
+        } s;
+        struct cvmx_npei_msi_w1c_enb3_s cn52xx;
+        struct cvmx_npei_msi_w1c_enb3_s cn56xx;
+};
+
+union cvmx_npei_msi_w1s_enb0 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1s_enb0_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_npei_msi_w1s_enb0_s cn52xx;
+        struct cvmx_npei_msi_w1s_enb0_s cn56xx;
+};
+
+union cvmx_npei_msi_w1s_enb1 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1s_enb1_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_npei_msi_w1s_enb1_s cn52xx;
+        struct cvmx_npei_msi_w1s_enb1_s cn56xx;
+};
+
+union cvmx_npei_msi_w1s_enb2 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1s_enb2_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_npei_msi_w1s_enb2_s cn52xx;
+        struct cvmx_npei_msi_w1s_enb2_s cn56xx;
+};
+
+union cvmx_npei_msi_w1s_enb3 {
+        uint64_t u64;
+        struct cvmx_npei_msi_w1s_enb3_s {
+                uint64_t set:64;
+        } s;
+        struct cvmx_npei_msi_w1s_enb3_s cn52xx;
+        struct cvmx_npei_msi_w1s_enb3_s cn56xx;
+};
+
+union cvmx_npei_msi_wr_map {
+        uint64_t u64;
+        struct cvmx_npei_msi_wr_map_s {
+                uint64_t reserved_16_63:48;
+                uint64_t ciu_int:8;
+                uint64_t msi_int:8;
+        } s;
+        struct cvmx_npei_msi_wr_map_s cn52xx;
+        struct cvmx_npei_msi_wr_map_s cn52xxp1;
+        struct cvmx_npei_msi_wr_map_s cn56xx;
+        struct cvmx_npei_msi_wr_map_s cn56xxp1;
+};
+
+union cvmx_npei_pcie_credit_cnt {
+        uint64_t u64;
+        struct cvmx_npei_pcie_credit_cnt_s {
+                uint64_t reserved_48_63:16;
+                uint64_t p1_ccnt:8;
+                uint64_t p1_ncnt:8;
+                uint64_t p1_pcnt:8;
+                uint64_t p0_ccnt:8;
+                uint64_t p0_ncnt:8;
+                uint64_t p0_pcnt:8;
+        } s;
+        struct cvmx_npei_pcie_credit_cnt_s cn52xx;
+        struct cvmx_npei_pcie_credit_cnt_s cn56xx;
+};
+
+union cvmx_npei_pcie_msi_rcv {
+        uint64_t u64;
+        struct cvmx_npei_pcie_msi_rcv_s {
+                uint64_t reserved_8_63:56;
+                uint64_t intr:8;
+        } s;
+        struct cvmx_npei_pcie_msi_rcv_s cn52xx;
+        struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
+        struct cvmx_npei_pcie_msi_rcv_s cn56xx;
+        struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
+};
+
+union cvmx_npei_pcie_msi_rcv_b1 {
+        uint64_t u64;
+        struct cvmx_npei_pcie_msi_rcv_b1_s {
+                uint64_t reserved_16_63:48;
+                uint64_t intr:8;
+                uint64_t reserved_0_7:8;
+        } s;
+        struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
+        struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
+        struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
+        struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
+};
+
+union cvmx_npei_pcie_msi_rcv_b2 {
+        uint64_t u64;
+        struct cvmx_npei_pcie_msi_rcv_b2_s {
+                uint64_t reserved_24_63:40;
+                uint64_t intr:8;
+                uint64_t reserved_0_15:16;
+        } s;
+        struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
+        struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
+        struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
+        struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
+};
+
+union cvmx_npei_pcie_msi_rcv_b3 {
+        uint64_t u64;
+        struct cvmx_npei_pcie_msi_rcv_b3_s {
+                uint64_t reserved_32_63:32;
+                uint64_t intr:8;
+                uint64_t reserved_0_23:24;
+        } s;
+        struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
+        struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
+        struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
+        struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
+};
+
+union cvmx_npei_pktx_cnts {
+        uint64_t u64;
+        struct cvmx_npei_pktx_cnts_s {
+                uint64_t reserved_54_63:10;
+                uint64_t timer:22;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_npei_pktx_cnts_s cn52xx;
+        struct cvmx_npei_pktx_cnts_s cn56xx;
+        struct cvmx_npei_pktx_cnts_s cn56xxp1;
+};
+
+union cvmx_npei_pktx_in_bp {
+        uint64_t u64;
+        struct cvmx_npei_pktx_in_bp_s {
+                uint64_t wmark:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_npei_pktx_in_bp_s cn52xx;
+        struct cvmx_npei_pktx_in_bp_s cn56xx;
+        struct cvmx_npei_pktx_in_bp_s cn56xxp1;
+};
+
+union cvmx_npei_pktx_instr_baddr {
+        uint64_t u64;
+        struct cvmx_npei_pktx_instr_baddr_s {
+                uint64_t addr:61;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_npei_pktx_instr_baddr_s cn52xx;
+        struct cvmx_npei_pktx_instr_baddr_s cn56xx;
+        struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
+};
+
+union cvmx_npei_pktx_instr_baoff_dbell {
+        uint64_t u64;
+        struct cvmx_npei_pktx_instr_baoff_dbell_s {
+                uint64_t aoff:32;
+                uint64_t dbell:32;
+        } s;
+        struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
+        struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
+        struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
+};
+
+union cvmx_npei_pktx_instr_fifo_rsize {
+        uint64_t u64;
+        struct cvmx_npei_pktx_instr_fifo_rsize_s {
+                uint64_t max:9;
+                uint64_t rrp:9;
+                uint64_t wrp:9;
+                uint64_t fcnt:5;
+                uint64_t rsize:32;
+        } s;
+        struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
+        struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
+        struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
+};
+
+union cvmx_npei_pktx_instr_header {
+        uint64_t u64;
+        struct cvmx_npei_pktx_instr_header_s {
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t rsv_f:5;
+                uint64_t rparmode:2;
+                uint64_t rsv_e:1;
+                uint64_t rskp_len:7;
+                uint64_t rsv_d:6;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_c:5;
+                uint64_t par_mode:2;
+                uint64_t rsv_b:1;
+                uint64_t skp_len:7;
+                uint64_t rsv_a:6;
+        } s;
+        struct cvmx_npei_pktx_instr_header_s cn52xx;
+        struct cvmx_npei_pktx_instr_header_s cn56xx;
+        struct cvmx_npei_pktx_instr_header_s cn56xxp1;
+};
+
+union cvmx_npei_pktx_slist_baddr {
+        uint64_t u64;
+        struct cvmx_npei_pktx_slist_baddr_s {
+                uint64_t addr:60;
+                uint64_t reserved_0_3:4;
+        } s;
+        struct cvmx_npei_pktx_slist_baddr_s cn52xx;
+        struct cvmx_npei_pktx_slist_baddr_s cn56xx;
+        struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
+};
+
+union cvmx_npei_pktx_slist_baoff_dbell {
+        uint64_t u64;
+        struct cvmx_npei_pktx_slist_baoff_dbell_s {
+                uint64_t aoff:32;
+                uint64_t dbell:32;
+        } s;
+        struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
+        struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
+        struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
+};
+
+union cvmx_npei_pktx_slist_fifo_rsize {
+        uint64_t u64;
+        struct cvmx_npei_pktx_slist_fifo_rsize_s {
+                uint64_t reserved_32_63:32;
+                uint64_t rsize:32;
+        } s;
+        struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
+        struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
+        struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_cnt_int {
+        uint64_t u64;
+        struct cvmx_npei_pkt_cnt_int_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_npei_pkt_cnt_int_s cn52xx;
+        struct cvmx_npei_pkt_cnt_int_s cn56xx;
+        struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_cnt_int_enb {
+        uint64_t u64;
+        struct cvmx_npei_pkt_cnt_int_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
+        struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
+        struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_data_out_es {
+        uint64_t u64;
+        struct cvmx_npei_pkt_data_out_es_s {
+                uint64_t es:64;
+        } s;
+        struct cvmx_npei_pkt_data_out_es_s cn52xx;
+        struct cvmx_npei_pkt_data_out_es_s cn56xx;
+        struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_data_out_ns {
+        uint64_t u64;
+        struct cvmx_npei_pkt_data_out_ns_s {
+                uint64_t reserved_32_63:32;
+                uint64_t nsr:32;
+        } s;
+        struct cvmx_npei_pkt_data_out_ns_s cn52xx;
+        struct cvmx_npei_pkt_data_out_ns_s cn56xx;
+        struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_data_out_ror {
+        uint64_t u64;
+        struct cvmx_npei_pkt_data_out_ror_s {
+                uint64_t reserved_32_63:32;
+                uint64_t ror:32;
+        } s;
+        struct cvmx_npei_pkt_data_out_ror_s cn52xx;
+        struct cvmx_npei_pkt_data_out_ror_s cn56xx;
+        struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_dpaddr {
+        uint64_t u64;
+        struct cvmx_npei_pkt_dpaddr_s {
+                uint64_t reserved_32_63:32;
+                uint64_t dptr:32;
+        } s;
+        struct cvmx_npei_pkt_dpaddr_s cn52xx;
+        struct cvmx_npei_pkt_dpaddr_s cn56xx;
+        struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_in_bp {
+        uint64_t u64;
+        struct cvmx_npei_pkt_in_bp_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bp:32;
+        } s;
+        struct cvmx_npei_pkt_in_bp_s cn56xx;
+};
+
+union cvmx_npei_pkt_in_donex_cnts {
+        uint64_t u64;
+        struct cvmx_npei_pkt_in_donex_cnts_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
+        struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
+        struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_in_instr_counts {
+        uint64_t u64;
+        struct cvmx_npei_pkt_in_instr_counts_s {
+                uint64_t wr_cnt:32;
+                uint64_t rd_cnt:32;
+        } s;
+        struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
+        struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
+};
+
+union cvmx_npei_pkt_in_pcie_port {
+        uint64_t u64;
+        struct cvmx_npei_pkt_in_pcie_port_s {
+                uint64_t pp:64;
+        } s;
+        struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
+        struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
+};
+
+union cvmx_npei_pkt_input_control {
+        uint64_t u64;
+        struct cvmx_npei_pkt_input_control_s {
+                uint64_t reserved_23_63:41;
+                uint64_t pkt_rr:1;
+                uint64_t pbp_dhi:13;
+                uint64_t d_nsr:1;
+                uint64_t d_esr:2;
+                uint64_t d_ror:1;
+                uint64_t use_csr:1;
+                uint64_t nsr:1;
+                uint64_t esr:2;
+                uint64_t ror:1;
+        } s;
+        struct cvmx_npei_pkt_input_control_s cn52xx;
+        struct cvmx_npei_pkt_input_control_s cn56xx;
+        struct cvmx_npei_pkt_input_control_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_instr_enb {
+        uint64_t u64;
+        struct cvmx_npei_pkt_instr_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t enb:32;
+        } s;
+        struct cvmx_npei_pkt_instr_enb_s cn52xx;
+        struct cvmx_npei_pkt_instr_enb_s cn56xx;
+        struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_instr_rd_size {
+        uint64_t u64;
+        struct cvmx_npei_pkt_instr_rd_size_s {
+                uint64_t rdsize:64;
+        } s;
+        struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
+        struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
+};
+
+union cvmx_npei_pkt_instr_size {
+        uint64_t u64;
+        struct cvmx_npei_pkt_instr_size_s {
+                uint64_t reserved_32_63:32;
+                uint64_t is_64b:32;
+        } s;
+        struct cvmx_npei_pkt_instr_size_s cn52xx;
+        struct cvmx_npei_pkt_instr_size_s cn56xx;
+        struct cvmx_npei_pkt_instr_size_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_int_levels {
+        uint64_t u64;
+        struct cvmx_npei_pkt_int_levels_s {
+                uint64_t reserved_54_63:10;
+                uint64_t time:22;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_npei_pkt_int_levels_s cn52xx;
+        struct cvmx_npei_pkt_int_levels_s cn56xx;
+        struct cvmx_npei_pkt_int_levels_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_iptr {
+        uint64_t u64;
+        struct cvmx_npei_pkt_iptr_s {
+                uint64_t reserved_32_63:32;
+                uint64_t iptr:32;
+        } s;
+        struct cvmx_npei_pkt_iptr_s cn52xx;
+        struct cvmx_npei_pkt_iptr_s cn56xx;
+        struct cvmx_npei_pkt_iptr_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_out_bmode {
+        uint64_t u64;
+        struct cvmx_npei_pkt_out_bmode_s {
+                uint64_t reserved_32_63:32;
+                uint64_t bmode:32;
+        } s;
+        struct cvmx_npei_pkt_out_bmode_s cn52xx;
+        struct cvmx_npei_pkt_out_bmode_s cn56xx;
+        struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_out_enb {
+        uint64_t u64;
+        struct cvmx_npei_pkt_out_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t enb:32;
+        } s;
+        struct cvmx_npei_pkt_out_enb_s cn52xx;
+        struct cvmx_npei_pkt_out_enb_s cn56xx;
+        struct cvmx_npei_pkt_out_enb_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_output_wmark {
+        uint64_t u64;
+        struct cvmx_npei_pkt_output_wmark_s {
+                uint64_t reserved_32_63:32;
+                uint64_t wmark:32;
+        } s;
+        struct cvmx_npei_pkt_output_wmark_s cn52xx;
+        struct cvmx_npei_pkt_output_wmark_s cn56xx;
+};
+
+union cvmx_npei_pkt_pcie_port {
+        uint64_t u64;
+        struct cvmx_npei_pkt_pcie_port_s {
+                uint64_t pp:64;
+        } s;
+        struct cvmx_npei_pkt_pcie_port_s cn52xx;
+        struct cvmx_npei_pkt_pcie_port_s cn56xx;
+        struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_port_in_rst {
+        uint64_t u64;
+        struct cvmx_npei_pkt_port_in_rst_s {
+                uint64_t in_rst:32;
+                uint64_t out_rst:32;
+        } s;
+        struct cvmx_npei_pkt_port_in_rst_s cn52xx;
+        struct cvmx_npei_pkt_port_in_rst_s cn56xx;
+};
+
+union cvmx_npei_pkt_slist_es {
+        uint64_t u64;
+        struct cvmx_npei_pkt_slist_es_s {
+                uint64_t es:64;
+        } s;
+        struct cvmx_npei_pkt_slist_es_s cn52xx;
+        struct cvmx_npei_pkt_slist_es_s cn56xx;
+        struct cvmx_npei_pkt_slist_es_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_slist_id_size {
+        uint64_t u64;
+        struct cvmx_npei_pkt_slist_id_size_s {
+                uint64_t reserved_23_63:41;
+                uint64_t isize:7;
+                uint64_t bsize:16;
+        } s;
+        struct cvmx_npei_pkt_slist_id_size_s cn52xx;
+        struct cvmx_npei_pkt_slist_id_size_s cn56xx;
+        struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_slist_ns {
+        uint64_t u64;
+        struct cvmx_npei_pkt_slist_ns_s {
+                uint64_t reserved_32_63:32;
+                uint64_t nsr:32;
+        } s;
+        struct cvmx_npei_pkt_slist_ns_s cn52xx;
+        struct cvmx_npei_pkt_slist_ns_s cn56xx;
+        struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_slist_ror {
+        uint64_t u64;
+        struct cvmx_npei_pkt_slist_ror_s {
+                uint64_t reserved_32_63:32;
+                uint64_t ror:32;
+        } s;
+        struct cvmx_npei_pkt_slist_ror_s cn52xx;
+        struct cvmx_npei_pkt_slist_ror_s cn56xx;
+        struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_time_int {
+        uint64_t u64;
+        struct cvmx_npei_pkt_time_int_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_npei_pkt_time_int_s cn52xx;
+        struct cvmx_npei_pkt_time_int_s cn56xx;
+        struct cvmx_npei_pkt_time_int_s cn56xxp1;
+};
+
+union cvmx_npei_pkt_time_int_enb {
+        uint64_t u64;
+        struct cvmx_npei_pkt_time_int_enb_s {
+                uint64_t reserved_32_63:32;
+                uint64_t port:32;
+        } s;
+        struct cvmx_npei_pkt_time_int_enb_s cn52xx;
+        struct cvmx_npei_pkt_time_int_enb_s cn56xx;
+        struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
+};
+
+union cvmx_npei_rsl_int_blocks {
+        uint64_t u64;
+        struct cvmx_npei_rsl_int_blocks_s {
+                uint64_t reserved_31_63:33;
+                uint64_t iob:1;
+                uint64_t lmc1:1;
+                uint64_t agl:1;
+                uint64_t reserved_24_27:4;
+                uint64_t asxpcs1:1;
+                uint64_t asxpcs0:1;
+                uint64_t reserved_21_21:1;
+                uint64_t pip:1;
+                uint64_t reserved_18_19:2;
+                uint64_t lmc0:1;
+                uint64_t l2c:1;
+                uint64_t usb1:1;
+                uint64_t rad:1;
+                uint64_t usb:1;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t reserved_8_8:1;
+                uint64_t zip:1;
+                uint64_t reserved_6_6:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t npei:1;
+                uint64_t gmx1:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+        } s;
+        struct cvmx_npei_rsl_int_blocks_s cn52xx;
+        struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
+        struct cvmx_npei_rsl_int_blocks_cn56xx {
+                uint64_t reserved_31_63:33;
+                uint64_t iob:1;
+                uint64_t lmc1:1;
+                uint64_t agl:1;
+                uint64_t reserved_24_27:4;
+                uint64_t asxpcs1:1;
+                uint64_t asxpcs0:1;
+                uint64_t reserved_21_21:1;
+                uint64_t pip:1;
+                uint64_t reserved_18_19:2;
+                uint64_t lmc0:1;
+                uint64_t l2c:1;
+                uint64_t reserved_15_15:1;
+                uint64_t rad:1;
+                uint64_t usb:1;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t reserved_8_8:1;
+                uint64_t zip:1;
+                uint64_t reserved_6_6:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t npei:1;
+                uint64_t gmx1:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+        } cn56xx;
+        struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
+};
+
+union cvmx_npei_scratch_1 {
+        uint64_t u64;
+        struct cvmx_npei_scratch_1_s {
+                uint64_t data:64;
+        } s;
+        struct cvmx_npei_scratch_1_s cn52xx;
+        struct cvmx_npei_scratch_1_s cn52xxp1;
+        struct cvmx_npei_scratch_1_s cn56xx;
+        struct cvmx_npei_scratch_1_s cn56xxp1;
+};
+
+union cvmx_npei_state1 {
+        uint64_t u64;
+        struct cvmx_npei_state1_s {
+                uint64_t cpl1:12;
+                uint64_t cpl0:12;
+                uint64_t arb:1;
+                uint64_t csr:39;
+        } s;
+        struct cvmx_npei_state1_s cn52xx;
+        struct cvmx_npei_state1_s cn52xxp1;
+        struct cvmx_npei_state1_s cn56xx;
+        struct cvmx_npei_state1_s cn56xxp1;
+};
+
+union cvmx_npei_state2 {
+        uint64_t u64;
+        struct cvmx_npei_state2_s {
+                uint64_t reserved_48_63:16;
+                uint64_t npei:1;
+                uint64_t rac:1;
+                uint64_t csm1:15;
+                uint64_t csm0:15;
+                uint64_t nnp0:8;
+                uint64_t nnd:8;
+        } s;
+        struct cvmx_npei_state2_s cn52xx;
+        struct cvmx_npei_state2_s cn52xxp1;
+        struct cvmx_npei_state2_s cn56xx;
+        struct cvmx_npei_state2_s cn56xxp1;
+};
+
+union cvmx_npei_state3 {
+        uint64_t u64;
+        struct cvmx_npei_state3_s {
+                uint64_t reserved_56_63:8;
+                uint64_t psm1:15;
+                uint64_t psm0:15;
+                uint64_t nsm1:13;
+                uint64_t nsm0:13;
+        } s;
+        struct cvmx_npei_state3_s cn52xx;
+        struct cvmx_npei_state3_s cn52xxp1;
+        struct cvmx_npei_state3_s cn56xx;
+        struct cvmx_npei_state3_s cn56xxp1;
+};
+
+union cvmx_npei_win_rd_addr {
+        uint64_t u64;
+        struct cvmx_npei_win_rd_addr_s {
+                uint64_t reserved_51_63:13;
+                uint64_t ld_cmd:2;
+                uint64_t iobit:1;
+                uint64_t rd_addr:48;
+        } s;
+        struct cvmx_npei_win_rd_addr_s cn52xx;
+        struct cvmx_npei_win_rd_addr_s cn52xxp1;
+        struct cvmx_npei_win_rd_addr_s cn56xx;
+        struct cvmx_npei_win_rd_addr_s cn56xxp1;
+};
+
+union cvmx_npei_win_rd_data {
+        uint64_t u64;
+        struct cvmx_npei_win_rd_data_s {
+                uint64_t rd_data:64;
+        } s;
+        struct cvmx_npei_win_rd_data_s cn52xx;
+        struct cvmx_npei_win_rd_data_s cn52xxp1;
+        struct cvmx_npei_win_rd_data_s cn56xx;
+        struct cvmx_npei_win_rd_data_s cn56xxp1;
+};
+
+union cvmx_npei_win_wr_addr {
+        uint64_t u64;
+        struct cvmx_npei_win_wr_addr_s {
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t wr_addr:46;
+                uint64_t reserved_0_1:2;
+        } s;
+        struct cvmx_npei_win_wr_addr_s cn52xx;
+        struct cvmx_npei_win_wr_addr_s cn52xxp1;
+        struct cvmx_npei_win_wr_addr_s cn56xx;
+        struct cvmx_npei_win_wr_addr_s cn56xxp1;
+};
+
+union cvmx_npei_win_wr_data {
+        uint64_t u64;
+        struct cvmx_npei_win_wr_data_s {
+                uint64_t wr_data:64;
+        } s;
+        struct cvmx_npei_win_wr_data_s cn52xx;
+        struct cvmx_npei_win_wr_data_s cn52xxp1;
+        struct cvmx_npei_win_wr_data_s cn56xx;
+        struct cvmx_npei_win_wr_data_s cn56xxp1;
+};
+
+union cvmx_npei_win_wr_mask {
+        uint64_t u64;
+        struct cvmx_npei_win_wr_mask_s {
+                uint64_t reserved_8_63:56;
+                uint64_t wr_mask:8;
+        } s;
+        struct cvmx_npei_win_wr_mask_s cn52xx;
+        struct cvmx_npei_win_wr_mask_s cn52xxp1;
+        struct cvmx_npei_win_wr_mask_s cn56xx;
+        struct cvmx_npei_win_wr_mask_s cn56xxp1;
+};
+
+union cvmx_npei_window_ctl {
+        uint64_t u64;
+        struct cvmx_npei_window_ctl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t time:32;
+        } s;
+        struct cvmx_npei_window_ctl_s cn52xx;
+        struct cvmx_npei_window_ctl_s cn52xxp1;
+        struct cvmx_npei_window_ctl_s cn56xx;
+        struct cvmx_npei_window_ctl_s cn56xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
new file mode 100644
index 000000000000..4e03cd8561e3
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -0,0 +1,1735 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_NPI_DEFS_H__
+#define __CVMX_NPI_DEFS_H__
+
+#define CVMX_NPI_BASE_ADDR_INPUT0 \
+         CVMX_ADD_IO_SEG(0x00011F0000000070ull)
+#define CVMX_NPI_BASE_ADDR_INPUT1 \
+         CVMX_ADD_IO_SEG(0x00011F0000000080ull)
+#define CVMX_NPI_BASE_ADDR_INPUT2 \
+         CVMX_ADD_IO_SEG(0x00011F0000000090ull)
+#define CVMX_NPI_BASE_ADDR_INPUT3 \
+         CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
+#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
+#define CVMX_NPI_BASE_ADDR_OUTPUT0 \
+         CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
+#define CVMX_NPI_BASE_ADDR_OUTPUT1 \
+         CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
+#define CVMX_NPI_BASE_ADDR_OUTPUT2 \
+         CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
+#define CVMX_NPI_BASE_ADDR_OUTPUT3 \
+         CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
+#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
+#define CVMX_NPI_BIST_STATUS \
+         CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
+         CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
+         CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
+         CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
+#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
+         CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
+#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
+#define CVMX_NPI_COMP_CTL \
+         CVMX_ADD_IO_SEG(0x00011F0000000218ull)
+#define CVMX_NPI_CTL_STATUS \
+         CVMX_ADD_IO_SEG(0x00011F0000000010ull)
+#define CVMX_NPI_DBG_SELECT \
+         CVMX_ADD_IO_SEG(0x00011F0000000008ull)
+#define CVMX_NPI_DMA_CONTROL \
+         CVMX_ADD_IO_SEG(0x00011F0000000128ull)
+#define CVMX_NPI_DMA_HIGHP_COUNTS \
+         CVMX_ADD_IO_SEG(0x00011F0000000148ull)
+#define CVMX_NPI_DMA_HIGHP_NADDR \
+         CVMX_ADD_IO_SEG(0x00011F0000000158ull)
+#define CVMX_NPI_DMA_LOWP_COUNTS \
+         CVMX_ADD_IO_SEG(0x00011F0000000140ull)
+#define CVMX_NPI_DMA_LOWP_NADDR \
+         CVMX_ADD_IO_SEG(0x00011F0000000150ull)
+#define CVMX_NPI_HIGHP_DBELL \
+         CVMX_ADD_IO_SEG(0x00011F0000000120ull)
+#define CVMX_NPI_HIGHP_IBUFF_SADDR \
+         CVMX_ADD_IO_SEG(0x00011F0000000110ull)
+#define CVMX_NPI_INPUT_CONTROL \
+         CVMX_ADD_IO_SEG(0x00011F0000000138ull)
+#define CVMX_NPI_INT_ENB \
+         CVMX_ADD_IO_SEG(0x00011F0000000020ull)
+#define CVMX_NPI_INT_SUM \
+         CVMX_ADD_IO_SEG(0x00011F0000000018ull)
+#define CVMX_NPI_LOWP_DBELL \
+         CVMX_ADD_IO_SEG(0x00011F0000000118ull)
+#define CVMX_NPI_LOWP_IBUFF_SADDR \
+         CVMX_ADD_IO_SEG(0x00011F0000000108ull)
+#define CVMX_NPI_MEM_ACCESS_SUBID3 \
+         CVMX_ADD_IO_SEG(0x00011F0000000028ull)
+#define CVMX_NPI_MEM_ACCESS_SUBID4 \
+         CVMX_ADD_IO_SEG(0x00011F0000000030ull)
+#define CVMX_NPI_MEM_ACCESS_SUBID5 \
+         CVMX_ADD_IO_SEG(0x00011F0000000038ull)
+#define CVMX_NPI_MEM_ACCESS_SUBID6 \
+         CVMX_ADD_IO_SEG(0x00011F0000000040ull)
+#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
+#define CVMX_NPI_MSI_RCV \
+         (0x0000000000000190ull)
+#define CVMX_NPI_NPI_MSI_RCV \
+         CVMX_ADD_IO_SEG(0x00011F0000001190ull)
+#define CVMX_NPI_NUM_DESC_OUTPUT0 \
+         CVMX_ADD_IO_SEG(0x00011F0000000050ull)
+#define CVMX_NPI_NUM_DESC_OUTPUT1 \
+         CVMX_ADD_IO_SEG(0x00011F0000000058ull)
+#define CVMX_NPI_NUM_DESC_OUTPUT2 \
+         CVMX_ADD_IO_SEG(0x00011F0000000060ull)
+#define CVMX_NPI_NUM_DESC_OUTPUT3 \
+         CVMX_ADD_IO_SEG(0x00011F0000000068ull)
+#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
+#define CVMX_NPI_OUTPUT_CONTROL \
+         CVMX_ADD_IO_SEG(0x00011F0000000100ull)
+#define CVMX_NPI_P0_DBPAIR_ADDR \
+         CVMX_ADD_IO_SEG(0x00011F0000000180ull)
+#define CVMX_NPI_P0_INSTR_ADDR \
+         CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
+#define CVMX_NPI_P0_INSTR_CNTS \
+         CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
+#define CVMX_NPI_P0_PAIR_CNTS \
+         CVMX_ADD_IO_SEG(0x00011F0000000160ull)
+#define CVMX_NPI_P1_DBPAIR_ADDR \
+         CVMX_ADD_IO_SEG(0x00011F0000000188ull)
+#define CVMX_NPI_P1_INSTR_ADDR \
+         CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
+#define CVMX_NPI_P1_INSTR_CNTS \
+         CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
+#define CVMX_NPI_P1_PAIR_CNTS \
+         CVMX_ADD_IO_SEG(0x00011F0000000168ull)
+#define CVMX_NPI_P2_DBPAIR_ADDR \
+         CVMX_ADD_IO_SEG(0x00011F0000000190ull)
+#define CVMX_NPI_P2_INSTR_ADDR \
+         CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
+#define CVMX_NPI_P2_INSTR_CNTS \
+         CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
+#define CVMX_NPI_P2_PAIR_CNTS \
+         CVMX_ADD_IO_SEG(0x00011F0000000170ull)
+#define CVMX_NPI_P3_DBPAIR_ADDR \
+         CVMX_ADD_IO_SEG(0x00011F0000000198ull)
+#define CVMX_NPI_P3_INSTR_ADDR \
+         CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
+#define CVMX_NPI_P3_INSTR_CNTS \
+         CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
+#define CVMX_NPI_P3_PAIR_CNTS \
+         CVMX_ADD_IO_SEG(0x00011F0000000178ull)
+#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
+#define CVMX_NPI_PCI_BIST_REG \
+         CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
+#define CVMX_NPI_PCI_BURST_SIZE \
+         CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
+#define CVMX_NPI_PCI_CFG00 \
+         CVMX_ADD_IO_SEG(0x00011F0000001800ull)
+#define CVMX_NPI_PCI_CFG01 \
+         CVMX_ADD_IO_SEG(0x00011F0000001804ull)
+#define CVMX_NPI_PCI_CFG02 \
+         CVMX_ADD_IO_SEG(0x00011F0000001808ull)
+#define CVMX_NPI_PCI_CFG03 \
+         CVMX_ADD_IO_SEG(0x00011F000000180Cull)
+#define CVMX_NPI_PCI_CFG04 \
+         CVMX_ADD_IO_SEG(0x00011F0000001810ull)
+#define CVMX_NPI_PCI_CFG05 \
+         CVMX_ADD_IO_SEG(0x00011F0000001814ull)
+#define CVMX_NPI_PCI_CFG06 \
+         CVMX_ADD_IO_SEG(0x00011F0000001818ull)
+#define CVMX_NPI_PCI_CFG07 \
+         CVMX_ADD_IO_SEG(0x00011F000000181Cull)
+#define CVMX_NPI_PCI_CFG08 \
+         CVMX_ADD_IO_SEG(0x00011F0000001820ull)
+#define CVMX_NPI_PCI_CFG09 \
+         CVMX_ADD_IO_SEG(0x00011F0000001824ull)
+#define CVMX_NPI_PCI_CFG10 \
+         CVMX_ADD_IO_SEG(0x00011F0000001828ull)
+#define CVMX_NPI_PCI_CFG11 \
+         CVMX_ADD_IO_SEG(0x00011F000000182Cull)
+#define CVMX_NPI_PCI_CFG12 \
+         CVMX_ADD_IO_SEG(0x00011F0000001830ull)
+#define CVMX_NPI_PCI_CFG13 \
+         CVMX_ADD_IO_SEG(0x00011F0000001834ull)
+#define CVMX_NPI_PCI_CFG15 \
+         CVMX_ADD_IO_SEG(0x00011F000000183Cull)
+#define CVMX_NPI_PCI_CFG16 \
+         CVMX_ADD_IO_SEG(0x00011F0000001840ull)
+#define CVMX_NPI_PCI_CFG17 \
+         CVMX_ADD_IO_SEG(0x00011F0000001844ull)
+#define CVMX_NPI_PCI_CFG18 \
+         CVMX_ADD_IO_SEG(0x00011F0000001848ull)
+#define CVMX_NPI_PCI_CFG19 \
+         CVMX_ADD_IO_SEG(0x00011F000000184Cull)
+#define CVMX_NPI_PCI_CFG20 \
+         CVMX_ADD_IO_SEG(0x00011F0000001850ull)
+#define CVMX_NPI_PCI_CFG21 \
+         CVMX_ADD_IO_SEG(0x00011F0000001854ull)
+#define CVMX_NPI_PCI_CFG22 \
+         CVMX_ADD_IO_SEG(0x00011F0000001858ull)
+#define CVMX_NPI_PCI_CFG56 \
+         CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
+#define CVMX_NPI_PCI_CFG57 \
+         CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
+#define CVMX_NPI_PCI_CFG58 \
+         CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
+#define CVMX_NPI_PCI_CFG59 \
+         CVMX_ADD_IO_SEG(0x00011F00000018ECull)
+#define CVMX_NPI_PCI_CFG60 \
+         CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
+#define CVMX_NPI_PCI_CFG61 \
+         CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
+#define CVMX_NPI_PCI_CFG62 \
+         CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
+#define CVMX_NPI_PCI_CFG63 \
+         CVMX_ADD_IO_SEG(0x00011F00000018FCull)
+#define CVMX_NPI_PCI_CNT_REG \
+         CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
+#define CVMX_NPI_PCI_CTL_STATUS_2 \
+         CVMX_ADD_IO_SEG(0x00011F000000118Cull)
+#define CVMX_NPI_PCI_INT_ARB_CFG \
+         CVMX_ADD_IO_SEG(0x00011F0000000130ull)
+#define CVMX_NPI_PCI_INT_ENB2 \
+         CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
+#define CVMX_NPI_PCI_INT_SUM2 \
+         CVMX_ADD_IO_SEG(0x00011F0000001198ull)
+#define CVMX_NPI_PCI_READ_CMD \
+         CVMX_ADD_IO_SEG(0x00011F0000000048ull)
+#define CVMX_NPI_PCI_READ_CMD_6 \
+         CVMX_ADD_IO_SEG(0x00011F0000001180ull)
+#define CVMX_NPI_PCI_READ_CMD_C \
+         CVMX_ADD_IO_SEG(0x00011F0000001184ull)
+#define CVMX_NPI_PCI_READ_CMD_E \
+         CVMX_ADD_IO_SEG(0x00011F0000001188ull)
+#define CVMX_NPI_PCI_SCM_REG \
+         CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
+#define CVMX_NPI_PCI_TSR_REG \
+         CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
+#define CVMX_NPI_PORT32_INSTR_HDR \
+         CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
+#define CVMX_NPI_PORT33_INSTR_HDR \
+         CVMX_ADD_IO_SEG(0x00011F0000000200ull)
+#define CVMX_NPI_PORT34_INSTR_HDR \
+         CVMX_ADD_IO_SEG(0x00011F0000000208ull)
+#define CVMX_NPI_PORT35_INSTR_HDR \
+         CVMX_ADD_IO_SEG(0x00011F0000000210ull)
+#define CVMX_NPI_PORT_BP_CONTROL \
+         CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
+#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
+#define CVMX_NPI_PX_INSTR_ADDR(offset) \
+         CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
+#define CVMX_NPI_PX_INSTR_CNTS(offset) \
+         CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
+#define CVMX_NPI_PX_PAIR_CNTS(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
+#define CVMX_NPI_RSL_INT_BLOCKS \
+         CVMX_ADD_IO_SEG(0x00011F0000000000ull)
+#define CVMX_NPI_SIZE_INPUT0 \
+         CVMX_ADD_IO_SEG(0x00011F0000000078ull)
+#define CVMX_NPI_SIZE_INPUT1 \
+         CVMX_ADD_IO_SEG(0x00011F0000000088ull)
+#define CVMX_NPI_SIZE_INPUT2 \
+         CVMX_ADD_IO_SEG(0x00011F0000000098ull)
+#define CVMX_NPI_SIZE_INPUT3 \
+         CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
+#define CVMX_NPI_SIZE_INPUTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
+#define CVMX_NPI_WIN_READ_TO \
+         CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
+
+union cvmx_npi_base_addr_inputx {
+        uint64_t u64;
+        struct cvmx_npi_base_addr_inputx_s {
+                uint64_t baddr:61;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_npi_base_addr_inputx_s cn30xx;
+        struct cvmx_npi_base_addr_inputx_s cn31xx;
+        struct cvmx_npi_base_addr_inputx_s cn38xx;
+        struct cvmx_npi_base_addr_inputx_s cn38xxp2;
+        struct cvmx_npi_base_addr_inputx_s cn50xx;
+        struct cvmx_npi_base_addr_inputx_s cn58xx;
+        struct cvmx_npi_base_addr_inputx_s cn58xxp1;
+};
+
+union cvmx_npi_base_addr_outputx {
+        uint64_t u64;
+        struct cvmx_npi_base_addr_outputx_s {
+                uint64_t baddr:61;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_npi_base_addr_outputx_s cn30xx;
+        struct cvmx_npi_base_addr_outputx_s cn31xx;
+        struct cvmx_npi_base_addr_outputx_s cn38xx;
+        struct cvmx_npi_base_addr_outputx_s cn38xxp2;
+        struct cvmx_npi_base_addr_outputx_s cn50xx;
+        struct cvmx_npi_base_addr_outputx_s cn58xx;
+        struct cvmx_npi_base_addr_outputx_s cn58xxp1;
+};
+
+union cvmx_npi_bist_status {
+        uint64_t u64;
+        struct cvmx_npi_bist_status_s {
+                uint64_t reserved_20_63:44;
+                uint64_t csr_bs:1;
+                uint64_t dif_bs:1;
+                uint64_t rdp_bs:1;
+                uint64_t pcnc_bs:1;
+                uint64_t pcn_bs:1;
+                uint64_t rdn_bs:1;
+                uint64_t pcac_bs:1;
+                uint64_t pcad_bs:1;
+                uint64_t rdnl_bs:1;
+                uint64_t pgf_bs:1;
+                uint64_t pig_bs:1;
+                uint64_t pof0_bs:1;
+                uint64_t pof1_bs:1;
+                uint64_t pof2_bs:1;
+                uint64_t pof3_bs:1;
+                uint64_t pos_bs:1;
+                uint64_t nus_bs:1;
+                uint64_t dob_bs:1;
+                uint64_t pdf_bs:1;
+                uint64_t dpi_bs:1;
+        } s;
+        struct cvmx_npi_bist_status_cn30xx {
+                uint64_t reserved_20_63:44;
+                uint64_t csr_bs:1;
+                uint64_t dif_bs:1;
+                uint64_t rdp_bs:1;
+                uint64_t pcnc_bs:1;
+                uint64_t pcn_bs:1;
+                uint64_t rdn_bs:1;
+                uint64_t pcac_bs:1;
+                uint64_t pcad_bs:1;
+                uint64_t rdnl_bs:1;
+                uint64_t pgf_bs:1;
+                uint64_t pig_bs:1;
+                uint64_t pof0_bs:1;
+                uint64_t reserved_5_7:3;
+                uint64_t pos_bs:1;
+                uint64_t nus_bs:1;
+                uint64_t dob_bs:1;
+                uint64_t pdf_bs:1;
+                uint64_t dpi_bs:1;
+        } cn30xx;
+        struct cvmx_npi_bist_status_s cn31xx;
+        struct cvmx_npi_bist_status_s cn38xx;
+        struct cvmx_npi_bist_status_s cn38xxp2;
+        struct cvmx_npi_bist_status_cn50xx {
+                uint64_t reserved_20_63:44;
+                uint64_t csr_bs:1;
+                uint64_t dif_bs:1;
+                uint64_t rdp_bs:1;
+                uint64_t pcnc_bs:1;
+                uint64_t pcn_bs:1;
+                uint64_t rdn_bs:1;
+                uint64_t pcac_bs:1;
+                uint64_t pcad_bs:1;
+                uint64_t rdnl_bs:1;
+                uint64_t pgf_bs:1;
+                uint64_t pig_bs:1;
+                uint64_t pof0_bs:1;
+                uint64_t pof1_bs:1;
+                uint64_t reserved_5_6:2;
+                uint64_t pos_bs:1;
+                uint64_t nus_bs:1;
+                uint64_t dob_bs:1;
+                uint64_t pdf_bs:1;
+                uint64_t dpi_bs:1;
+        } cn50xx;
+        struct cvmx_npi_bist_status_s cn58xx;
+        struct cvmx_npi_bist_status_s cn58xxp1;
+};
+
+union cvmx_npi_buff_size_outputx {
+        uint64_t u64;
+        struct cvmx_npi_buff_size_outputx_s {
+                uint64_t reserved_23_63:41;
+                uint64_t isize:7;
+                uint64_t bsize:16;
+        } s;
+        struct cvmx_npi_buff_size_outputx_s cn30xx;
+        struct cvmx_npi_buff_size_outputx_s cn31xx;
+        struct cvmx_npi_buff_size_outputx_s cn38xx;
+        struct cvmx_npi_buff_size_outputx_s cn38xxp2;
+        struct cvmx_npi_buff_size_outputx_s cn50xx;
+        struct cvmx_npi_buff_size_outputx_s cn58xx;
+        struct cvmx_npi_buff_size_outputx_s cn58xxp1;
+};
+
+union cvmx_npi_comp_ctl {
+        uint64_t u64;
+        struct cvmx_npi_comp_ctl_s {
+                uint64_t reserved_10_63:54;
+                uint64_t pctl:5;
+                uint64_t nctl:5;
+        } s;
+        struct cvmx_npi_comp_ctl_s cn50xx;
+        struct cvmx_npi_comp_ctl_s cn58xx;
+        struct cvmx_npi_comp_ctl_s cn58xxp1;
+};
+
+union cvmx_npi_ctl_status {
+        uint64_t u64;
+        struct cvmx_npi_ctl_status_s {
+                uint64_t reserved_63_63:1;
+                uint64_t chip_rev:8;
+                uint64_t dis_pniw:1;
+                uint64_t out3_enb:1;
+                uint64_t out2_enb:1;
+                uint64_t out1_enb:1;
+                uint64_t out0_enb:1;
+                uint64_t ins3_enb:1;
+                uint64_t ins2_enb:1;
+                uint64_t ins1_enb:1;
+                uint64_t ins0_enb:1;
+                uint64_t ins3_64b:1;
+                uint64_t ins2_64b:1;
+                uint64_t ins1_64b:1;
+                uint64_t ins0_64b:1;
+                uint64_t pci_wdis:1;
+                uint64_t wait_com:1;
+                uint64_t reserved_37_39:3;
+                uint64_t max_word:5;
+                uint64_t reserved_10_31:22;
+                uint64_t timer:10;
+        } s;
+        struct cvmx_npi_ctl_status_cn30xx {
+                uint64_t reserved_63_63:1;
+                uint64_t chip_rev:8;
+                uint64_t dis_pniw:1;
+                uint64_t reserved_51_53:3;
+                uint64_t out0_enb:1;
+                uint64_t reserved_47_49:3;
+                uint64_t ins0_enb:1;
+                uint64_t reserved_43_45:3;
+                uint64_t ins0_64b:1;
+                uint64_t pci_wdis:1;
+                uint64_t wait_com:1;
+                uint64_t reserved_37_39:3;
+                uint64_t max_word:5;
+                uint64_t reserved_10_31:22;
+                uint64_t timer:10;
+        } cn30xx;
+        struct cvmx_npi_ctl_status_cn31xx {
+                uint64_t reserved_63_63:1;
+                uint64_t chip_rev:8;
+                uint64_t dis_pniw:1;
+                uint64_t reserved_52_53:2;
+                uint64_t out1_enb:1;
+                uint64_t out0_enb:1;
+                uint64_t reserved_48_49:2;
+                uint64_t ins1_enb:1;
+                uint64_t ins0_enb:1;
+                uint64_t reserved_44_45:2;
+                uint64_t ins1_64b:1;
+                uint64_t ins0_64b:1;
+                uint64_t pci_wdis:1;
+                uint64_t wait_com:1;
+                uint64_t reserved_37_39:3;
+                uint64_t max_word:5;
+                uint64_t reserved_10_31:22;
+                uint64_t timer:10;
+        } cn31xx;
+        struct cvmx_npi_ctl_status_s cn38xx;
+        struct cvmx_npi_ctl_status_s cn38xxp2;
+        struct cvmx_npi_ctl_status_cn31xx cn50xx;
+        struct cvmx_npi_ctl_status_s cn58xx;
+        struct cvmx_npi_ctl_status_s cn58xxp1;
+};
+
+union cvmx_npi_dbg_select {
+        uint64_t u64;
+        struct cvmx_npi_dbg_select_s {
+                uint64_t reserved_16_63:48;
+                uint64_t dbg_sel:16;
+        } s;
+        struct cvmx_npi_dbg_select_s cn30xx;
+        struct cvmx_npi_dbg_select_s cn31xx;
+        struct cvmx_npi_dbg_select_s cn38xx;
+        struct cvmx_npi_dbg_select_s cn38xxp2;
+        struct cvmx_npi_dbg_select_s cn50xx;
+        struct cvmx_npi_dbg_select_s cn58xx;
+        struct cvmx_npi_dbg_select_s cn58xxp1;
+};
+
+union cvmx_npi_dma_control {
+        uint64_t u64;
+        struct cvmx_npi_dma_control_s {
+                uint64_t reserved_36_63:28;
+                uint64_t b0_lend:1;
+                uint64_t dwb_denb:1;
+                uint64_t dwb_ichk:9;
+                uint64_t fpa_que:3;
+                uint64_t o_add1:1;
+                uint64_t o_ro:1;
+                uint64_t o_ns:1;
+                uint64_t o_es:2;
+                uint64_t o_mode:1;
+                uint64_t hp_enb:1;
+                uint64_t lp_enb:1;
+                uint64_t csize:14;
+        } s;
+        struct cvmx_npi_dma_control_s cn30xx;
+        struct cvmx_npi_dma_control_s cn31xx;
+        struct cvmx_npi_dma_control_s cn38xx;
+        struct cvmx_npi_dma_control_s cn38xxp2;
+        struct cvmx_npi_dma_control_s cn50xx;
+        struct cvmx_npi_dma_control_s cn58xx;
+        struct cvmx_npi_dma_control_s cn58xxp1;
+};
+
+union cvmx_npi_dma_highp_counts {
+        uint64_t u64;
+        struct cvmx_npi_dma_highp_counts_s {
+                uint64_t reserved_39_63:25;
+                uint64_t fcnt:7;
+                uint64_t dbell:32;
+        } s;
+        struct cvmx_npi_dma_highp_counts_s cn30xx;
+        struct cvmx_npi_dma_highp_counts_s cn31xx;
+        struct cvmx_npi_dma_highp_counts_s cn38xx;
+        struct cvmx_npi_dma_highp_counts_s cn38xxp2;
+        struct cvmx_npi_dma_highp_counts_s cn50xx;
+        struct cvmx_npi_dma_highp_counts_s cn58xx;
+        struct cvmx_npi_dma_highp_counts_s cn58xxp1;
+};
+
+union cvmx_npi_dma_highp_naddr {
+        uint64_t u64;
+        struct cvmx_npi_dma_highp_naddr_s {
+                uint64_t reserved_40_63:24;
+                uint64_t state:4;
+                uint64_t addr:36;
+        } s;
+        struct cvmx_npi_dma_highp_naddr_s cn30xx;
+        struct cvmx_npi_dma_highp_naddr_s cn31xx;
+        struct cvmx_npi_dma_highp_naddr_s cn38xx;
+        struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
+        struct cvmx_npi_dma_highp_naddr_s cn50xx;
+        struct cvmx_npi_dma_highp_naddr_s cn58xx;
+        struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
+};
+
+union cvmx_npi_dma_lowp_counts {
+        uint64_t u64;
+        struct cvmx_npi_dma_lowp_counts_s {
+                uint64_t reserved_39_63:25;
+                uint64_t fcnt:7;
+                uint64_t dbell:32;
+        } s;
+        struct cvmx_npi_dma_lowp_counts_s cn30xx;
+        struct cvmx_npi_dma_lowp_counts_s cn31xx;
+        struct cvmx_npi_dma_lowp_counts_s cn38xx;
+        struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
+        struct cvmx_npi_dma_lowp_counts_s cn50xx;
+        struct cvmx_npi_dma_lowp_counts_s cn58xx;
+        struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
+};
+
+union cvmx_npi_dma_lowp_naddr {
+        uint64_t u64;
+        struct cvmx_npi_dma_lowp_naddr_s {
+                uint64_t reserved_40_63:24;
+                uint64_t state:4;
+                uint64_t addr:36;
+        } s;
+        struct cvmx_npi_dma_lowp_naddr_s cn30xx;
+        struct cvmx_npi_dma_lowp_naddr_s cn31xx;
+        struct cvmx_npi_dma_lowp_naddr_s cn38xx;
+        struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
+        struct cvmx_npi_dma_lowp_naddr_s cn50xx;
+        struct cvmx_npi_dma_lowp_naddr_s cn58xx;
+        struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
+};
+
+union cvmx_npi_highp_dbell {
+        uint64_t u64;
+        struct cvmx_npi_highp_dbell_s {
+                uint64_t reserved_16_63:48;
+                uint64_t dbell:16;
+        } s;
+        struct cvmx_npi_highp_dbell_s cn30xx;
+        struct cvmx_npi_highp_dbell_s cn31xx;
+        struct cvmx_npi_highp_dbell_s cn38xx;
+        struct cvmx_npi_highp_dbell_s cn38xxp2;
+        struct cvmx_npi_highp_dbell_s cn50xx;
+        struct cvmx_npi_highp_dbell_s cn58xx;
+        struct cvmx_npi_highp_dbell_s cn58xxp1;
+};
+
+union cvmx_npi_highp_ibuff_saddr {
+        uint64_t u64;
+        struct cvmx_npi_highp_ibuff_saddr_s {
+                uint64_t reserved_36_63:28;
+                uint64_t saddr:36;
+        } s;
+        struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
+        struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
+        struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
+        struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
+        struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
+        struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
+        struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
+};
+
+union cvmx_npi_input_control {
+        uint64_t u64;
+        struct cvmx_npi_input_control_s {
+                uint64_t reserved_23_63:41;
+                uint64_t pkt_rr:1;
+                uint64_t pbp_dhi:13;
+                uint64_t d_nsr:1;
+                uint64_t d_esr:2;
+                uint64_t d_ror:1;
+                uint64_t use_csr:1;
+                uint64_t nsr:1;
+                uint64_t esr:2;
+                uint64_t ror:1;
+        } s;
+        struct cvmx_npi_input_control_cn30xx {
+                uint64_t reserved_22_63:42;
+                uint64_t pbp_dhi:13;
+                uint64_t d_nsr:1;
+                uint64_t d_esr:2;
+                uint64_t d_ror:1;
+                uint64_t use_csr:1;
+                uint64_t nsr:1;
+                uint64_t esr:2;
+                uint64_t ror:1;
+        } cn30xx;
+        struct cvmx_npi_input_control_cn30xx cn31xx;
+        struct cvmx_npi_input_control_s cn38xx;
+        struct cvmx_npi_input_control_cn30xx cn38xxp2;
+        struct cvmx_npi_input_control_s cn50xx;
+        struct cvmx_npi_input_control_s cn58xx;
+        struct cvmx_npi_input_control_s cn58xxp1;
+};
+
+union cvmx_npi_int_enb {
+        uint64_t u64;
+        struct cvmx_npi_int_enb_s {
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t i3_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t p3_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t p3_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t g3_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t p3_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t p3_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t i3_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t i3_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t po3_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } s;
+        struct cvmx_npi_int_enb_cn30xx {
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t reserved_36_38:3;
+                uint64_t i0_pperr:1;
+                uint64_t reserved_32_34:3;
+                uint64_t p0_ptout:1;
+                uint64_t reserved_28_30:3;
+                uint64_t p0_pperr:1;
+                uint64_t reserved_24_26:3;
+                uint64_t g0_rtout:1;
+                uint64_t reserved_20_22:3;
+                uint64_t p0_perr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t p0_rtout:1;
+                uint64_t reserved_12_14:3;
+                uint64_t i0_overf:1;
+                uint64_t reserved_8_10:3;
+                uint64_t i0_rtout:1;
+                uint64_t reserved_4_6:3;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn30xx;
+        struct cvmx_npi_int_enb_cn31xx {
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t reserved_37_38:2;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t reserved_33_34:2;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t reserved_29_30:2;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t reserved_25_26:2;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t reserved_21_22:2;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t reserved_17_18:2;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t reserved_13_14:2;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t reserved_9_10:2;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t reserved_5_6:2;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn31xx;
+        struct cvmx_npi_int_enb_s cn38xx;
+        struct cvmx_npi_int_enb_cn38xxp2 {
+                uint64_t reserved_42_63:22;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t i3_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t p3_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t p3_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t g3_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t p3_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t p3_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t i3_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t i3_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t po3_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn38xxp2;
+        struct cvmx_npi_int_enb_cn31xx cn50xx;
+        struct cvmx_npi_int_enb_s cn58xx;
+        struct cvmx_npi_int_enb_s cn58xxp1;
+};
+
+union cvmx_npi_int_sum {
+        uint64_t u64;
+        struct cvmx_npi_int_sum_s {
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t i3_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t p3_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t p3_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t g3_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t p3_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t p3_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t i3_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t i3_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t po3_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } s;
+        struct cvmx_npi_int_sum_cn30xx {
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t reserved_36_38:3;
+                uint64_t i0_pperr:1;
+                uint64_t reserved_32_34:3;
+                uint64_t p0_ptout:1;
+                uint64_t reserved_28_30:3;
+                uint64_t p0_pperr:1;
+                uint64_t reserved_24_26:3;
+                uint64_t g0_rtout:1;
+                uint64_t reserved_20_22:3;
+                uint64_t p0_perr:1;
+                uint64_t reserved_16_18:3;
+                uint64_t p0_rtout:1;
+                uint64_t reserved_12_14:3;
+                uint64_t i0_overf:1;
+                uint64_t reserved_8_10:3;
+                uint64_t i0_rtout:1;
+                uint64_t reserved_4_6:3;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn30xx;
+        struct cvmx_npi_int_sum_cn31xx {
+                uint64_t reserved_62_63:2;
+                uint64_t q1_a_f:1;
+                uint64_t q1_s_e:1;
+                uint64_t pdf_p_f:1;
+                uint64_t pdf_p_e:1;
+                uint64_t pcf_p_f:1;
+                uint64_t pcf_p_e:1;
+                uint64_t rdx_s_e:1;
+                uint64_t rwx_s_e:1;
+                uint64_t pnc_a_f:1;
+                uint64_t pnc_s_e:1;
+                uint64_t com_a_f:1;
+                uint64_t com_s_e:1;
+                uint64_t q3_a_f:1;
+                uint64_t q3_s_e:1;
+                uint64_t q2_a_f:1;
+                uint64_t q2_s_e:1;
+                uint64_t pcr_a_f:1;
+                uint64_t pcr_s_e:1;
+                uint64_t fcr_a_f:1;
+                uint64_t fcr_s_e:1;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t reserved_37_38:2;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t reserved_33_34:2;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t reserved_29_30:2;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t reserved_25_26:2;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t reserved_21_22:2;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t reserved_17_18:2;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t reserved_13_14:2;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t reserved_9_10:2;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t reserved_5_6:2;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn31xx;
+        struct cvmx_npi_int_sum_s cn38xx;
+        struct cvmx_npi_int_sum_cn38xxp2 {
+                uint64_t reserved_42_63:22;
+                uint64_t iobdma:1;
+                uint64_t p_dperr:1;
+                uint64_t win_rto:1;
+                uint64_t i3_pperr:1;
+                uint64_t i2_pperr:1;
+                uint64_t i1_pperr:1;
+                uint64_t i0_pperr:1;
+                uint64_t p3_ptout:1;
+                uint64_t p2_ptout:1;
+                uint64_t p1_ptout:1;
+                uint64_t p0_ptout:1;
+                uint64_t p3_pperr:1;
+                uint64_t p2_pperr:1;
+                uint64_t p1_pperr:1;
+                uint64_t p0_pperr:1;
+                uint64_t g3_rtout:1;
+                uint64_t g2_rtout:1;
+                uint64_t g1_rtout:1;
+                uint64_t g0_rtout:1;
+                uint64_t p3_perr:1;
+                uint64_t p2_perr:1;
+                uint64_t p1_perr:1;
+                uint64_t p0_perr:1;
+                uint64_t p3_rtout:1;
+                uint64_t p2_rtout:1;
+                uint64_t p1_rtout:1;
+                uint64_t p0_rtout:1;
+                uint64_t i3_overf:1;
+                uint64_t i2_overf:1;
+                uint64_t i1_overf:1;
+                uint64_t i0_overf:1;
+                uint64_t i3_rtout:1;
+                uint64_t i2_rtout:1;
+                uint64_t i1_rtout:1;
+                uint64_t i0_rtout:1;
+                uint64_t po3_2sml:1;
+                uint64_t po2_2sml:1;
+                uint64_t po1_2sml:1;
+                uint64_t po0_2sml:1;
+                uint64_t pci_rsl:1;
+                uint64_t rml_wto:1;
+                uint64_t rml_rto:1;
+        } cn38xxp2;
+        struct cvmx_npi_int_sum_cn31xx cn50xx;
+        struct cvmx_npi_int_sum_s cn58xx;
+        struct cvmx_npi_int_sum_s cn58xxp1;
+};
+
+union cvmx_npi_lowp_dbell {
+        uint64_t u64;
+        struct cvmx_npi_lowp_dbell_s {
+                uint64_t reserved_16_63:48;
+                uint64_t dbell:16;
+        } s;
+        struct cvmx_npi_lowp_dbell_s cn30xx;
+        struct cvmx_npi_lowp_dbell_s cn31xx;
+        struct cvmx_npi_lowp_dbell_s cn38xx;
+        struct cvmx_npi_lowp_dbell_s cn38xxp2;
+        struct cvmx_npi_lowp_dbell_s cn50xx;
+        struct cvmx_npi_lowp_dbell_s cn58xx;
+        struct cvmx_npi_lowp_dbell_s cn58xxp1;
+};
+
+union cvmx_npi_lowp_ibuff_saddr {
+        uint64_t u64;
+        struct cvmx_npi_lowp_ibuff_saddr_s {
+                uint64_t reserved_36_63:28;
+                uint64_t saddr:36;
+        } s;
+        struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
+        struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
+        struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
+        struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
+        struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
+        struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
+        struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
+};
+
+union cvmx_npi_mem_access_subidx {
+        uint64_t u64;
+        struct cvmx_npi_mem_access_subidx_s {
+                uint64_t reserved_38_63:26;
+                uint64_t shortl:1;
+                uint64_t nmerge:1;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t nsr:1;
+                uint64_t nsw:1;
+                uint64_t ror:1;
+                uint64_t row:1;
+                uint64_t ba:28;
+        } s;
+        struct cvmx_npi_mem_access_subidx_s cn30xx;
+        struct cvmx_npi_mem_access_subidx_cn31xx {
+                uint64_t reserved_36_63:28;
+                uint64_t esr:2;
+                uint64_t esw:2;
+                uint64_t nsr:1;
+                uint64_t nsw:1;
+                uint64_t ror:1;
+                uint64_t row:1;
+                uint64_t ba:28;
+        } cn31xx;
+        struct cvmx_npi_mem_access_subidx_s cn38xx;
+        struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
+        struct cvmx_npi_mem_access_subidx_s cn50xx;
+        struct cvmx_npi_mem_access_subidx_s cn58xx;
+        struct cvmx_npi_mem_access_subidx_s cn58xxp1;
+};
+
+union cvmx_npi_msi_rcv {
+        uint64_t u64;
+        struct cvmx_npi_msi_rcv_s {
+                uint64_t int_vec:64;
+        } s;
+        struct cvmx_npi_msi_rcv_s cn30xx;
+        struct cvmx_npi_msi_rcv_s cn31xx;
+        struct cvmx_npi_msi_rcv_s cn38xx;
+        struct cvmx_npi_msi_rcv_s cn38xxp2;
+        struct cvmx_npi_msi_rcv_s cn50xx;
+        struct cvmx_npi_msi_rcv_s cn58xx;
+        struct cvmx_npi_msi_rcv_s cn58xxp1;
+};
+
+union cvmx_npi_num_desc_outputx {
+        uint64_t u64;
+        struct cvmx_npi_num_desc_outputx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t size:32;
+        } s;
+        struct cvmx_npi_num_desc_outputx_s cn30xx;
+        struct cvmx_npi_num_desc_outputx_s cn31xx;
+        struct cvmx_npi_num_desc_outputx_s cn38xx;
+        struct cvmx_npi_num_desc_outputx_s cn38xxp2;
+        struct cvmx_npi_num_desc_outputx_s cn50xx;
+        struct cvmx_npi_num_desc_outputx_s cn58xx;
+        struct cvmx_npi_num_desc_outputx_s cn58xxp1;
+};
+
+union cvmx_npi_output_control {
+        uint64_t u64;
+        struct cvmx_npi_output_control_s {
+                uint64_t reserved_49_63:15;
+                uint64_t pkt_rr:1;
+                uint64_t p3_bmode:1;
+                uint64_t p2_bmode:1;
+                uint64_t p1_bmode:1;
+                uint64_t p0_bmode:1;
+                uint64_t o3_es:2;
+                uint64_t o3_ns:1;
+                uint64_t o3_ro:1;
+                uint64_t o2_es:2;
+                uint64_t o2_ns:1;
+                uint64_t o2_ro:1;
+                uint64_t o1_es:2;
+                uint64_t o1_ns:1;
+                uint64_t o1_ro:1;
+                uint64_t o0_es:2;
+                uint64_t o0_ns:1;
+                uint64_t o0_ro:1;
+                uint64_t o3_csrm:1;
+                uint64_t o2_csrm:1;
+                uint64_t o1_csrm:1;
+                uint64_t o0_csrm:1;
+                uint64_t reserved_20_23:4;
+                uint64_t iptr_o3:1;
+                uint64_t iptr_o2:1;
+                uint64_t iptr_o1:1;
+                uint64_t iptr_o0:1;
+                uint64_t esr_sl3:2;
+                uint64_t nsr_sl3:1;
+                uint64_t ror_sl3:1;
+                uint64_t esr_sl2:2;
+                uint64_t nsr_sl2:1;
+                uint64_t ror_sl2:1;
+                uint64_t esr_sl1:2;
+                uint64_t nsr_sl1:1;
+                uint64_t ror_sl1:1;
+                uint64_t esr_sl0:2;
+                uint64_t nsr_sl0:1;
+                uint64_t ror_sl0:1;
+        } s;
+        struct cvmx_npi_output_control_cn30xx {
+                uint64_t reserved_45_63:19;
+                uint64_t p0_bmode:1;
+                uint64_t reserved_32_43:12;
+                uint64_t o0_es:2;
+                uint64_t o0_ns:1;
+                uint64_t o0_ro:1;
+                uint64_t reserved_25_27:3;
+                uint64_t o0_csrm:1;
+                uint64_t reserved_17_23:7;
+                uint64_t iptr_o0:1;
+                uint64_t reserved_4_15:12;
+                uint64_t esr_sl0:2;
+                uint64_t nsr_sl0:1;
+                uint64_t ror_sl0:1;
+        } cn30xx;
+        struct cvmx_npi_output_control_cn31xx {
+                uint64_t reserved_46_63:18;
+                uint64_t p1_bmode:1;
+                uint64_t p0_bmode:1;
+                uint64_t reserved_36_43:8;
+                uint64_t o1_es:2;
+                uint64_t o1_ns:1;
+                uint64_t o1_ro:1;
+                uint64_t o0_es:2;
+                uint64_t o0_ns:1;
+                uint64_t o0_ro:1;
+                uint64_t reserved_26_27:2;
+                uint64_t o1_csrm:1;
+                uint64_t o0_csrm:1;
+                uint64_t reserved_18_23:6;
+                uint64_t iptr_o1:1;
+                uint64_t iptr_o0:1;
+                uint64_t reserved_8_15:8;
+                uint64_t esr_sl1:2;
+                uint64_t nsr_sl1:1;
+                uint64_t ror_sl1:1;
+                uint64_t esr_sl0:2;
+                uint64_t nsr_sl0:1;
+                uint64_t ror_sl0:1;
+        } cn31xx;
+        struct cvmx_npi_output_control_s cn38xx;
+        struct cvmx_npi_output_control_cn38xxp2 {
+                uint64_t reserved_48_63:16;
+                uint64_t p3_bmode:1;
+                uint64_t p2_bmode:1;
+                uint64_t p1_bmode:1;
+                uint64_t p0_bmode:1;
+                uint64_t o3_es:2;
+                uint64_t o3_ns:1;
+                uint64_t o3_ro:1;
+                uint64_t o2_es:2;
+                uint64_t o2_ns:1;
+                uint64_t o2_ro:1;
+                uint64_t o1_es:2;
+                uint64_t o1_ns:1;
+                uint64_t o1_ro:1;
+                uint64_t o0_es:2;
+                uint64_t o0_ns:1;
+                uint64_t o0_ro:1;
+                uint64_t o3_csrm:1;
+                uint64_t o2_csrm:1;
+                uint64_t o1_csrm:1;
+                uint64_t o0_csrm:1;
+                uint64_t reserved_20_23:4;
+                uint64_t iptr_o3:1;
+                uint64_t iptr_o2:1;
+                uint64_t iptr_o1:1;
+                uint64_t iptr_o0:1;
+                uint64_t esr_sl3:2;
+                uint64_t nsr_sl3:1;
+                uint64_t ror_sl3:1;
+                uint64_t esr_sl2:2;
+                uint64_t nsr_sl2:1;
+                uint64_t ror_sl2:1;
+                uint64_t esr_sl1:2;
+                uint64_t nsr_sl1:1;
+                uint64_t ror_sl1:1;
+                uint64_t esr_sl0:2;
+                uint64_t nsr_sl0:1;
+                uint64_t ror_sl0:1;
+        } cn38xxp2;
+        struct cvmx_npi_output_control_cn50xx {
+                uint64_t reserved_49_63:15;
+                uint64_t pkt_rr:1;
+                uint64_t reserved_46_47:2;
+                uint64_t p1_bmode:1;
+                uint64_t p0_bmode:1;
+                uint64_t reserved_36_43:8;
+                uint64_t o1_es:2;
+                uint64_t o1_ns:1;
+                uint64_t o1_ro:1;
+                uint64_t o0_es:2;
+                uint64_t o0_ns:1;
+                uint64_t o0_ro:1;
+                uint64_t reserved_26_27:2;
+                uint64_t o1_csrm:1;
+                uint64_t o0_csrm:1;
+                uint64_t reserved_18_23:6;
+                uint64_t iptr_o1:1;
+                uint64_t iptr_o0:1;
+                uint64_t reserved_8_15:8;
+                uint64_t esr_sl1:2;
+                uint64_t nsr_sl1:1;
+                uint64_t ror_sl1:1;
+                uint64_t esr_sl0:2;
+                uint64_t nsr_sl0:1;
+                uint64_t ror_sl0:1;
+        } cn50xx;
+        struct cvmx_npi_output_control_s cn58xx;
+        struct cvmx_npi_output_control_s cn58xxp1;
+};
+
+union cvmx_npi_px_dbpair_addr {
+        uint64_t u64;
+        struct cvmx_npi_px_dbpair_addr_s {
+                uint64_t reserved_63_63:1;
+                uint64_t state:2;
+                uint64_t naddr:61;
+        } s;
+        struct cvmx_npi_px_dbpair_addr_s cn30xx;
+        struct cvmx_npi_px_dbpair_addr_s cn31xx;
+        struct cvmx_npi_px_dbpair_addr_s cn38xx;
+        struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
+        struct cvmx_npi_px_dbpair_addr_s cn50xx;
+        struct cvmx_npi_px_dbpair_addr_s cn58xx;
+        struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
+};
+
+union cvmx_npi_px_instr_addr {
+        uint64_t u64;
+        struct cvmx_npi_px_instr_addr_s {
+                uint64_t state:3;
+                uint64_t naddr:61;
+        } s;
+        struct cvmx_npi_px_instr_addr_s cn30xx;
+        struct cvmx_npi_px_instr_addr_s cn31xx;
+        struct cvmx_npi_px_instr_addr_s cn38xx;
+        struct cvmx_npi_px_instr_addr_s cn38xxp2;
+        struct cvmx_npi_px_instr_addr_s cn50xx;
+        struct cvmx_npi_px_instr_addr_s cn58xx;
+        struct cvmx_npi_px_instr_addr_s cn58xxp1;
+};
+
+union cvmx_npi_px_instr_cnts {
+        uint64_t u64;
+        struct cvmx_npi_px_instr_cnts_s {
+                uint64_t reserved_38_63:26;
+                uint64_t fcnt:6;
+                uint64_t avail:32;
+        } s;
+        struct cvmx_npi_px_instr_cnts_s cn30xx;
+        struct cvmx_npi_px_instr_cnts_s cn31xx;
+        struct cvmx_npi_px_instr_cnts_s cn38xx;
+        struct cvmx_npi_px_instr_cnts_s cn38xxp2;
+        struct cvmx_npi_px_instr_cnts_s cn50xx;
+        struct cvmx_npi_px_instr_cnts_s cn58xx;
+        struct cvmx_npi_px_instr_cnts_s cn58xxp1;
+};
+
+union cvmx_npi_px_pair_cnts {
+        uint64_t u64;
+        struct cvmx_npi_px_pair_cnts_s {
+                uint64_t reserved_37_63:27;
+                uint64_t fcnt:5;
+                uint64_t avail:32;
+        } s;
+        struct cvmx_npi_px_pair_cnts_s cn30xx;
+        struct cvmx_npi_px_pair_cnts_s cn31xx;
+        struct cvmx_npi_px_pair_cnts_s cn38xx;
+        struct cvmx_npi_px_pair_cnts_s cn38xxp2;
+        struct cvmx_npi_px_pair_cnts_s cn50xx;
+        struct cvmx_npi_px_pair_cnts_s cn58xx;
+        struct cvmx_npi_px_pair_cnts_s cn58xxp1;
+};
+
+union cvmx_npi_pci_burst_size {
+        uint64_t u64;
+        struct cvmx_npi_pci_burst_size_s {
+                uint64_t reserved_14_63:50;
+                uint64_t wr_brst:7;
+                uint64_t rd_brst:7;
+        } s;
+        struct cvmx_npi_pci_burst_size_s cn30xx;
+        struct cvmx_npi_pci_burst_size_s cn31xx;
+        struct cvmx_npi_pci_burst_size_s cn38xx;
+        struct cvmx_npi_pci_burst_size_s cn38xxp2;
+        struct cvmx_npi_pci_burst_size_s cn50xx;
+        struct cvmx_npi_pci_burst_size_s cn58xx;
+        struct cvmx_npi_pci_burst_size_s cn58xxp1;
+};
+
+union cvmx_npi_pci_int_arb_cfg {
+        uint64_t u64;
+        struct cvmx_npi_pci_int_arb_cfg_s {
+                uint64_t reserved_13_63:51;
+                uint64_t hostmode:1;
+                uint64_t pci_ovr:4;
+                uint64_t reserved_5_7:3;
+                uint64_t en:1;
+                uint64_t park_mod:1;
+                uint64_t park_dev:3;
+        } s;
+        struct cvmx_npi_pci_int_arb_cfg_cn30xx {
+                uint64_t reserved_5_63:59;
+                uint64_t en:1;
+                uint64_t park_mod:1;
+                uint64_t park_dev:3;
+        } cn30xx;
+        struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
+        struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
+        struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
+        struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
+        struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
+        struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
+};
+
+union cvmx_npi_pci_read_cmd {
+        uint64_t u64;
+        struct cvmx_npi_pci_read_cmd_s {
+                uint64_t reserved_11_63:53;
+                uint64_t cmd_size:11;
+        } s;
+        struct cvmx_npi_pci_read_cmd_s cn30xx;
+        struct cvmx_npi_pci_read_cmd_s cn31xx;
+        struct cvmx_npi_pci_read_cmd_s cn38xx;
+        struct cvmx_npi_pci_read_cmd_s cn38xxp2;
+        struct cvmx_npi_pci_read_cmd_s cn50xx;
+        struct cvmx_npi_pci_read_cmd_s cn58xx;
+        struct cvmx_npi_pci_read_cmd_s cn58xxp1;
+};
+
+union cvmx_npi_port32_instr_hdr {
+        uint64_t u64;
+        struct cvmx_npi_port32_instr_hdr_s {
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t rsv_f:5;
+                uint64_t rparmode:2;
+                uint64_t rsv_e:1;
+                uint64_t rskp_len:7;
+                uint64_t rsv_d:6;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_c:5;
+                uint64_t par_mode:2;
+                uint64_t rsv_b:1;
+                uint64_t skp_len:7;
+                uint64_t rsv_a:6;
+        } s;
+        struct cvmx_npi_port32_instr_hdr_s cn30xx;
+        struct cvmx_npi_port32_instr_hdr_s cn31xx;
+        struct cvmx_npi_port32_instr_hdr_s cn38xx;
+        struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
+        struct cvmx_npi_port32_instr_hdr_s cn50xx;
+        struct cvmx_npi_port32_instr_hdr_s cn58xx;
+        struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
+};
+
+union cvmx_npi_port33_instr_hdr {
+        uint64_t u64;
+        struct cvmx_npi_port33_instr_hdr_s {
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t rsv_f:5;
+                uint64_t rparmode:2;
+                uint64_t rsv_e:1;
+                uint64_t rskp_len:7;
+                uint64_t rsv_d:6;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_c:5;
+                uint64_t par_mode:2;
+                uint64_t rsv_b:1;
+                uint64_t skp_len:7;
+                uint64_t rsv_a:6;
+        } s;
+        struct cvmx_npi_port33_instr_hdr_s cn31xx;
+        struct cvmx_npi_port33_instr_hdr_s cn38xx;
+        struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
+        struct cvmx_npi_port33_instr_hdr_s cn50xx;
+        struct cvmx_npi_port33_instr_hdr_s cn58xx;
+        struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
+};
+
+union cvmx_npi_port34_instr_hdr {
+        uint64_t u64;
+        struct cvmx_npi_port34_instr_hdr_s {
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t rsv_f:5;
+                uint64_t rparmode:2;
+                uint64_t rsv_e:1;
+                uint64_t rskp_len:7;
+                uint64_t rsv_d:6;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_c:5;
+                uint64_t par_mode:2;
+                uint64_t rsv_b:1;
+                uint64_t skp_len:7;
+                uint64_t rsv_a:6;
+        } s;
+        struct cvmx_npi_port34_instr_hdr_s cn38xx;
+        struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
+        struct cvmx_npi_port34_instr_hdr_s cn58xx;
+        struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
+};
+
+union cvmx_npi_port35_instr_hdr {
+        uint64_t u64;
+        struct cvmx_npi_port35_instr_hdr_s {
+                uint64_t reserved_44_63:20;
+                uint64_t pbp:1;
+                uint64_t rsv_f:5;
+                uint64_t rparmode:2;
+                uint64_t rsv_e:1;
+                uint64_t rskp_len:7;
+                uint64_t rsv_d:6;
+                uint64_t use_ihdr:1;
+                uint64_t rsv_c:5;
+                uint64_t par_mode:2;
+                uint64_t rsv_b:1;
+                uint64_t skp_len:7;
+                uint64_t rsv_a:6;
+        } s;
+        struct cvmx_npi_port35_instr_hdr_s cn38xx;
+        struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
+        struct cvmx_npi_port35_instr_hdr_s cn58xx;
+        struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
+};
+
+union cvmx_npi_port_bp_control {
+        uint64_t u64;
+        struct cvmx_npi_port_bp_control_s {
+                uint64_t reserved_8_63:56;
+                uint64_t bp_on:4;
+                uint64_t enb:4;
+        } s;
+        struct cvmx_npi_port_bp_control_s cn30xx;
+        struct cvmx_npi_port_bp_control_s cn31xx;
+        struct cvmx_npi_port_bp_control_s cn38xx;
+        struct cvmx_npi_port_bp_control_s cn38xxp2;
+        struct cvmx_npi_port_bp_control_s cn50xx;
+        struct cvmx_npi_port_bp_control_s cn58xx;
+        struct cvmx_npi_port_bp_control_s cn58xxp1;
+};
+
+union cvmx_npi_rsl_int_blocks {
+        uint64_t u64;
+        struct cvmx_npi_rsl_int_blocks_s {
+                uint64_t reserved_32_63:32;
+                uint64_t rint_31:1;
+                uint64_t iob:1;
+                uint64_t reserved_28_29:2;
+                uint64_t rint_27:1;
+                uint64_t rint_26:1;
+                uint64_t rint_25:1;
+                uint64_t rint_24:1;
+                uint64_t asx1:1;
+                uint64_t asx0:1;
+                uint64_t rint_21:1;
+                uint64_t pip:1;
+                uint64_t spx1:1;
+                uint64_t spx0:1;
+                uint64_t lmc:1;
+                uint64_t l2c:1;
+                uint64_t rint_15:1;
+                uint64_t reserved_13_14:2;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t rint_8:1;
+                uint64_t zip:1;
+                uint64_t dfa:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t npi:1;
+                uint64_t gmx1:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+        } s;
+        struct cvmx_npi_rsl_int_blocks_cn30xx {
+                uint64_t reserved_32_63:32;
+                uint64_t rint_31:1;
+                uint64_t iob:1;
+                uint64_t rint_29:1;
+                uint64_t rint_28:1;
+                uint64_t rint_27:1;
+                uint64_t rint_26:1;
+                uint64_t rint_25:1;
+                uint64_t rint_24:1;
+                uint64_t asx1:1;
+                uint64_t asx0:1;
+                uint64_t rint_21:1;
+                uint64_t pip:1;
+                uint64_t spx1:1;
+                uint64_t spx0:1;
+                uint64_t lmc:1;
+                uint64_t l2c:1;
+                uint64_t rint_15:1;
+                uint64_t rint_14:1;
+                uint64_t usb:1;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t rint_8:1;
+                uint64_t zip:1;
+                uint64_t dfa:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t npi:1;
+                uint64_t gmx1:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+        } cn30xx;
+        struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
+        struct cvmx_npi_rsl_int_blocks_cn38xx {
+                uint64_t reserved_32_63:32;
+                uint64_t rint_31:1;
+                uint64_t iob:1;
+                uint64_t rint_29:1;
+                uint64_t rint_28:1;
+                uint64_t rint_27:1;
+                uint64_t rint_26:1;
+                uint64_t rint_25:1;
+                uint64_t rint_24:1;
+                uint64_t asx1:1;
+                uint64_t asx0:1;
+                uint64_t rint_21:1;
+                uint64_t pip:1;
+                uint64_t spx1:1;
+                uint64_t spx0:1;
+                uint64_t lmc:1;
+                uint64_t l2c:1;
+                uint64_t rint_15:1;
+                uint64_t rint_14:1;
+                uint64_t rint_13:1;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t rint_8:1;
+                uint64_t zip:1;
+                uint64_t dfa:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t npi:1;
+                uint64_t gmx1:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+        } cn38xx;
+        struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
+        struct cvmx_npi_rsl_int_blocks_cn50xx {
+                uint64_t reserved_31_63:33;
+                uint64_t iob:1;
+                uint64_t lmc1:1;
+                uint64_t agl:1;
+                uint64_t reserved_24_27:4;
+                uint64_t asx1:1;
+                uint64_t asx0:1;
+                uint64_t reserved_21_21:1;
+                uint64_t pip:1;
+                uint64_t spx1:1;
+                uint64_t spx0:1;
+                uint64_t lmc:1;
+                uint64_t l2c:1;
+                uint64_t reserved_15_15:1;
+                uint64_t rad:1;
+                uint64_t usb:1;
+                uint64_t pow:1;
+                uint64_t tim:1;
+                uint64_t pko:1;
+                uint64_t ipd:1;
+                uint64_t reserved_8_8:1;
+                uint64_t zip:1;
+                uint64_t dfa:1;
+                uint64_t fpa:1;
+                uint64_t key:1;
+                uint64_t npi:1;
+                uint64_t gmx1:1;
+                uint64_t gmx0:1;
+                uint64_t mio:1;
+        } cn50xx;
+        struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
+        struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
+};
+
+union cvmx_npi_size_inputx {
+        uint64_t u64;
+        struct cvmx_npi_size_inputx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t size:32;
+        } s;
+        struct cvmx_npi_size_inputx_s cn30xx;
+        struct cvmx_npi_size_inputx_s cn31xx;
+        struct cvmx_npi_size_inputx_s cn38xx;
+        struct cvmx_npi_size_inputx_s cn38xxp2;
+        struct cvmx_npi_size_inputx_s cn50xx;
+        struct cvmx_npi_size_inputx_s cn58xx;
+        struct cvmx_npi_size_inputx_s cn58xxp1;
+};
+
+union cvmx_npi_win_read_to {
+        uint64_t u64;
+        struct cvmx_npi_win_read_to_s {
+                uint64_t reserved_32_63:32;
+                uint64_t time:32;
+        } s;
+        struct cvmx_npi_win_read_to_s cn30xx;
+        struct cvmx_npi_win_read_to_s cn31xx;
+        struct cvmx_npi_win_read_to_s cn38xx;
+        struct cvmx_npi_win_read_to_s cn38xxp2;
+        struct cvmx_npi_win_read_to_s cn50xx;
+        struct cvmx_npi_win_read_to_s cn58xx;
+        struct cvmx_npi_win_read_to_s cn58xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
new file mode 100644
index 000000000000..90f8d6535753
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
@@ -0,0 +1,1645 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PCI_DEFS_H__
+#define __CVMX_PCI_DEFS_H__
+
+#define CVMX_PCI_BAR1_INDEXX(offset) \
+         (0x0000000000000100ull + (((offset) & 31) * 4))
+#define CVMX_PCI_BIST_REG \
+         (0x00000000000001C0ull)
+#define CVMX_PCI_CFG00 \
+         (0x0000000000000000ull)
+#define CVMX_PCI_CFG01 \
+         (0x0000000000000004ull)
+#define CVMX_PCI_CFG02 \
+         (0x0000000000000008ull)
+#define CVMX_PCI_CFG03 \
+         (0x000000000000000Cull)
+#define CVMX_PCI_CFG04 \
+         (0x0000000000000010ull)
+#define CVMX_PCI_CFG05 \
+         (0x0000000000000014ull)
+#define CVMX_PCI_CFG06 \
+         (0x0000000000000018ull)
+#define CVMX_PCI_CFG07 \
+         (0x000000000000001Cull)
+#define CVMX_PCI_CFG08 \
+         (0x0000000000000020ull)
+#define CVMX_PCI_CFG09 \
+         (0x0000000000000024ull)
+#define CVMX_PCI_CFG10 \
+         (0x0000000000000028ull)
+#define CVMX_PCI_CFG11 \
+         (0x000000000000002Cull)
+#define CVMX_PCI_CFG12 \
+         (0x0000000000000030ull)
+#define CVMX_PCI_CFG13 \
+         (0x0000000000000034ull)
+#define CVMX_PCI_CFG15 \
+         (0x000000000000003Cull)
+#define CVMX_PCI_CFG16 \
+         (0x0000000000000040ull)
+#define CVMX_PCI_CFG17 \
+         (0x0000000000000044ull)
+#define CVMX_PCI_CFG18 \
+         (0x0000000000000048ull)
+#define CVMX_PCI_CFG19 \
+         (0x000000000000004Cull)
+#define CVMX_PCI_CFG20 \
+         (0x0000000000000050ull)
+#define CVMX_PCI_CFG21 \
+         (0x0000000000000054ull)
+#define CVMX_PCI_CFG22 \
+         (0x0000000000000058ull)
+#define CVMX_PCI_CFG56 \
+         (0x00000000000000E0ull)
+#define CVMX_PCI_CFG57 \
+         (0x00000000000000E4ull)
+#define CVMX_PCI_CFG58 \
+         (0x00000000000000E8ull)
+#define CVMX_PCI_CFG59 \
+         (0x00000000000000ECull)
+#define CVMX_PCI_CFG60 \
+         (0x00000000000000F0ull)
+#define CVMX_PCI_CFG61 \
+         (0x00000000000000F4ull)
+#define CVMX_PCI_CFG62 \
+         (0x00000000000000F8ull)
+#define CVMX_PCI_CFG63 \
+         (0x00000000000000FCull)
+#define CVMX_PCI_CNT_REG \
+         (0x00000000000001B8ull)
+#define CVMX_PCI_CTL_STATUS_2 \
+         (0x000000000000018Cull)
+#define CVMX_PCI_DBELL_0 \
+         (0x0000000000000080ull)
+#define CVMX_PCI_DBELL_1 \
+         (0x0000000000000088ull)
+#define CVMX_PCI_DBELL_2 \
+         (0x0000000000000090ull)
+#define CVMX_PCI_DBELL_3 \
+         (0x0000000000000098ull)
+#define CVMX_PCI_DBELL_X(offset) \
+         (0x0000000000000080ull + (((offset) & 3) * 8))
+#define CVMX_PCI_DMA_CNT0 \
+         (0x00000000000000A0ull)
+#define CVMX_PCI_DMA_CNT1 \
+         (0x00000000000000A8ull)
+#define CVMX_PCI_DMA_CNTX(offset) \
+         (0x00000000000000A0ull + (((offset) & 1) * 8))
+#define CVMX_PCI_DMA_INT_LEV0 \
+         (0x00000000000000A4ull)
+#define CVMX_PCI_DMA_INT_LEV1 \
+         (0x00000000000000ACull)
+#define CVMX_PCI_DMA_INT_LEVX(offset) \
+         (0x00000000000000A4ull + (((offset) & 1) * 8))
+#define CVMX_PCI_DMA_TIME0 \
+         (0x00000000000000B0ull)
+#define CVMX_PCI_DMA_TIME1 \
+         (0x00000000000000B4ull)
+#define CVMX_PCI_DMA_TIMEX(offset) \
+         (0x00000000000000B0ull + (((offset) & 1) * 4))
+#define CVMX_PCI_INSTR_COUNT0 \
+         (0x0000000000000084ull)
+#define CVMX_PCI_INSTR_COUNT1 \
+         (0x000000000000008Cull)
+#define CVMX_PCI_INSTR_COUNT2 \
+         (0x0000000000000094ull)
+#define CVMX_PCI_INSTR_COUNT3 \
+         (0x000000000000009Cull)
+#define CVMX_PCI_INSTR_COUNTX(offset) \
+         (0x0000000000000084ull + (((offset) & 3) * 8))
+#define CVMX_PCI_INT_ENB \
+         (0x0000000000000038ull)
+#define CVMX_PCI_INT_ENB2 \
+         (0x00000000000001A0ull)
+#define CVMX_PCI_INT_SUM \
+         (0x0000000000000030ull)
+#define CVMX_PCI_INT_SUM2 \
+         (0x0000000000000198ull)
+#define CVMX_PCI_MSI_RCV \
+         (0x00000000000000F0ull)
+#define CVMX_PCI_PKTS_SENT0 \
+         (0x0000000000000040ull)
+#define CVMX_PCI_PKTS_SENT1 \
+         (0x0000000000000050ull)
+#define CVMX_PCI_PKTS_SENT2 \
+         (0x0000000000000060ull)
+#define CVMX_PCI_PKTS_SENT3 \
+         (0x0000000000000070ull)
+#define CVMX_PCI_PKTS_SENTX(offset) \
+         (0x0000000000000040ull + (((offset) & 3) * 16))
+#define CVMX_PCI_PKTS_SENT_INT_LEV0 \
+         (0x0000000000000048ull)
+#define CVMX_PCI_PKTS_SENT_INT_LEV1 \
+         (0x0000000000000058ull)
+#define CVMX_PCI_PKTS_SENT_INT_LEV2 \
+         (0x0000000000000068ull)
+#define CVMX_PCI_PKTS_SENT_INT_LEV3 \
+         (0x0000000000000078ull)
+#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \
+         (0x0000000000000048ull + (((offset) & 3) * 16))
+#define CVMX_PCI_PKTS_SENT_TIME0 \
+         (0x000000000000004Cull)
+#define CVMX_PCI_PKTS_SENT_TIME1 \
+         (0x000000000000005Cull)
+#define CVMX_PCI_PKTS_SENT_TIME2 \
+         (0x000000000000006Cull)
+#define CVMX_PCI_PKTS_SENT_TIME3 \
+         (0x000000000000007Cull)
+#define CVMX_PCI_PKTS_SENT_TIMEX(offset) \
+         (0x000000000000004Cull + (((offset) & 3) * 16))
+#define CVMX_PCI_PKT_CREDITS0 \
+         (0x0000000000000044ull)
+#define CVMX_PCI_PKT_CREDITS1 \
+         (0x0000000000000054ull)
+#define CVMX_PCI_PKT_CREDITS2 \
+         (0x0000000000000064ull)
+#define CVMX_PCI_PKT_CREDITS3 \
+         (0x0000000000000074ull)
+#define CVMX_PCI_PKT_CREDITSX(offset) \
+         (0x0000000000000044ull + (((offset) & 3) * 16))
+#define CVMX_PCI_READ_CMD_6 \
+         (0x0000000000000180ull)
+#define CVMX_PCI_READ_CMD_C \
+         (0x0000000000000184ull)
+#define CVMX_PCI_READ_CMD_E \
+         (0x0000000000000188ull)
+#define CVMX_PCI_READ_TIMEOUT \
+         CVMX_ADD_IO_SEG(0x00011F00000000B0ull)
+#define CVMX_PCI_SCM_REG \
+         (0x00000000000001A8ull)
+#define CVMX_PCI_TSR_REG \
+         (0x00000000000001B0ull)
+#define CVMX_PCI_WIN_RD_ADDR \
+         (0x0000000000000008ull)
+#define CVMX_PCI_WIN_RD_DATA \
+         (0x0000000000000020ull)
+#define CVMX_PCI_WIN_WR_ADDR \
+         (0x0000000000000000ull)
+#define CVMX_PCI_WIN_WR_DATA \
+         (0x0000000000000010ull)
+#define CVMX_PCI_WIN_WR_MASK \
+         (0x0000000000000018ull)
+
+union cvmx_pci_bar1_indexx {
+        uint32_t u32;
+        struct cvmx_pci_bar1_indexx_s {
+                uint32_t reserved_18_31:14;
+                uint32_t addr_idx:14;
+                uint32_t ca:1;
+                uint32_t end_swp:2;
+                uint32_t addr_v:1;
+        } s;
+        struct cvmx_pci_bar1_indexx_s cn30xx;
+        struct cvmx_pci_bar1_indexx_s cn31xx;
+        struct cvmx_pci_bar1_indexx_s cn38xx;
+        struct cvmx_pci_bar1_indexx_s cn38xxp2;
+        struct cvmx_pci_bar1_indexx_s cn50xx;
+        struct cvmx_pci_bar1_indexx_s cn58xx;
+        struct cvmx_pci_bar1_indexx_s cn58xxp1;
+};
+
+union cvmx_pci_bist_reg {
+        uint64_t u64;
+        struct cvmx_pci_bist_reg_s {
+                uint64_t reserved_10_63:54;
+                uint64_t rsp_bs:1;
+                uint64_t dma0_bs:1;
+                uint64_t cmd0_bs:1;
+                uint64_t cmd_bs:1;
+                uint64_t csr2p_bs:1;
+                uint64_t csrr_bs:1;
+                uint64_t rsp2p_bs:1;
+                uint64_t csr2n_bs:1;
+                uint64_t dat2n_bs:1;
+                uint64_t dbg2n_bs:1;
+        } s;
+        struct cvmx_pci_bist_reg_s cn50xx;
+};
+
+union cvmx_pci_cfg00 {
+        uint32_t u32;
+        struct cvmx_pci_cfg00_s {
+                uint32_t devid:16;
+                uint32_t vendid:16;
+        } s;
+        struct cvmx_pci_cfg00_s cn30xx;
+        struct cvmx_pci_cfg00_s cn31xx;
+        struct cvmx_pci_cfg00_s cn38xx;
+        struct cvmx_pci_cfg00_s cn38xxp2;
+        struct cvmx_pci_cfg00_s cn50xx;
+        struct cvmx_pci_cfg00_s cn58xx;
+        struct cvmx_pci_cfg00_s cn58xxp1;
+};
+
+union cvmx_pci_cfg01 {
+        uint32_t u32;
+        struct cvmx_pci_cfg01_s {
+                uint32_t dpe:1;
+                uint32_t sse:1;
+                uint32_t rma:1;
+                uint32_t rta:1;
+                uint32_t sta:1;
+                uint32_t devt:2;
+                uint32_t mdpe:1;
+                uint32_t fbb:1;
+                uint32_t reserved_22_22:1;
+                uint32_t m66:1;
+                uint32_t cle:1;
+                uint32_t i_stat:1;
+                uint32_t reserved_11_18:8;
+                uint32_t i_dis:1;
+                uint32_t fbbe:1;
+                uint32_t see:1;
+                uint32_t ads:1;
+                uint32_t pee:1;
+                uint32_t vps:1;
+                uint32_t mwice:1;
+                uint32_t scse:1;
+                uint32_t me:1;
+                uint32_t msae:1;
+                uint32_t isae:1;
+        } s;
+        struct cvmx_pci_cfg01_s cn30xx;
+        struct cvmx_pci_cfg01_s cn31xx;
+        struct cvmx_pci_cfg01_s cn38xx;
+        struct cvmx_pci_cfg01_s cn38xxp2;
+        struct cvmx_pci_cfg01_s cn50xx;
+        struct cvmx_pci_cfg01_s cn58xx;
+        struct cvmx_pci_cfg01_s cn58xxp1;
+};
+
+union cvmx_pci_cfg02 {
+        uint32_t u32;
+        struct cvmx_pci_cfg02_s {
+                uint32_t cc:24;
+                uint32_t rid:8;
+        } s;
+        struct cvmx_pci_cfg02_s cn30xx;
+        struct cvmx_pci_cfg02_s cn31xx;
+        struct cvmx_pci_cfg02_s cn38xx;
+        struct cvmx_pci_cfg02_s cn38xxp2;
+        struct cvmx_pci_cfg02_s cn50xx;
+        struct cvmx_pci_cfg02_s cn58xx;
+        struct cvmx_pci_cfg02_s cn58xxp1;
+};
+
+union cvmx_pci_cfg03 {
+        uint32_t u32;
+        struct cvmx_pci_cfg03_s {
+                uint32_t bcap:1;
+                uint32_t brb:1;
+                uint32_t reserved_28_29:2;
+                uint32_t bcod:4;
+                uint32_t ht:8;
+                uint32_t lt:8;
+                uint32_t cls:8;
+        } s;
+        struct cvmx_pci_cfg03_s cn30xx;
+        struct cvmx_pci_cfg03_s cn31xx;
+        struct cvmx_pci_cfg03_s cn38xx;
+        struct cvmx_pci_cfg03_s cn38xxp2;
+        struct cvmx_pci_cfg03_s cn50xx;
+        struct cvmx_pci_cfg03_s cn58xx;
+        struct cvmx_pci_cfg03_s cn58xxp1;
+};
+
+union cvmx_pci_cfg04 {
+        uint32_t u32;
+        struct cvmx_pci_cfg04_s {
+                uint32_t lbase:20;
+                uint32_t lbasez:8;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+        } s;
+        struct cvmx_pci_cfg04_s cn30xx;
+        struct cvmx_pci_cfg04_s cn31xx;
+        struct cvmx_pci_cfg04_s cn38xx;
+        struct cvmx_pci_cfg04_s cn38xxp2;
+        struct cvmx_pci_cfg04_s cn50xx;
+        struct cvmx_pci_cfg04_s cn58xx;
+        struct cvmx_pci_cfg04_s cn58xxp1;
+};
+
+union cvmx_pci_cfg05 {
+        uint32_t u32;
+        struct cvmx_pci_cfg05_s {
+                uint32_t hbase:32;
+        } s;
+        struct cvmx_pci_cfg05_s cn30xx;
+        struct cvmx_pci_cfg05_s cn31xx;
+        struct cvmx_pci_cfg05_s cn38xx;
+        struct cvmx_pci_cfg05_s cn38xxp2;
+        struct cvmx_pci_cfg05_s cn50xx;
+        struct cvmx_pci_cfg05_s cn58xx;
+        struct cvmx_pci_cfg05_s cn58xxp1;
+};
+
+union cvmx_pci_cfg06 {
+        uint32_t u32;
+        struct cvmx_pci_cfg06_s {
+                uint32_t lbase:5;
+                uint32_t lbasez:23;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+        } s;
+        struct cvmx_pci_cfg06_s cn30xx;
+        struct cvmx_pci_cfg06_s cn31xx;
+        struct cvmx_pci_cfg06_s cn38xx;
+        struct cvmx_pci_cfg06_s cn38xxp2;
+        struct cvmx_pci_cfg06_s cn50xx;
+        struct cvmx_pci_cfg06_s cn58xx;
+        struct cvmx_pci_cfg06_s cn58xxp1;
+};
+
+union cvmx_pci_cfg07 {
+        uint32_t u32;
+        struct cvmx_pci_cfg07_s {
+                uint32_t hbase:32;
+        } s;
+        struct cvmx_pci_cfg07_s cn30xx;
+        struct cvmx_pci_cfg07_s cn31xx;
+        struct cvmx_pci_cfg07_s cn38xx;
+        struct cvmx_pci_cfg07_s cn38xxp2;
+        struct cvmx_pci_cfg07_s cn50xx;
+        struct cvmx_pci_cfg07_s cn58xx;
+        struct cvmx_pci_cfg07_s cn58xxp1;
+};
+
+union cvmx_pci_cfg08 {
+        uint32_t u32;
+        struct cvmx_pci_cfg08_s {
+                uint32_t lbasez:28;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+        } s;
+        struct cvmx_pci_cfg08_s cn30xx;
+        struct cvmx_pci_cfg08_s cn31xx;
+        struct cvmx_pci_cfg08_s cn38xx;
+        struct cvmx_pci_cfg08_s cn38xxp2;
+        struct cvmx_pci_cfg08_s cn50xx;
+        struct cvmx_pci_cfg08_s cn58xx;
+        struct cvmx_pci_cfg08_s cn58xxp1;
+};
+
+union cvmx_pci_cfg09 {
+        uint32_t u32;
+        struct cvmx_pci_cfg09_s {
+                uint32_t hbase:25;
+                uint32_t hbasez:7;
+        } s;
+        struct cvmx_pci_cfg09_s cn30xx;
+        struct cvmx_pci_cfg09_s cn31xx;
+        struct cvmx_pci_cfg09_s cn38xx;
+        struct cvmx_pci_cfg09_s cn38xxp2;
+        struct cvmx_pci_cfg09_s cn50xx;
+        struct cvmx_pci_cfg09_s cn58xx;
+        struct cvmx_pci_cfg09_s cn58xxp1;
+};
+
+union cvmx_pci_cfg10 {
+        uint32_t u32;
+        struct cvmx_pci_cfg10_s {
+                uint32_t cisp:32;
+        } s;
+        struct cvmx_pci_cfg10_s cn30xx;
+        struct cvmx_pci_cfg10_s cn31xx;
+        struct cvmx_pci_cfg10_s cn38xx;
+        struct cvmx_pci_cfg10_s cn38xxp2;
+        struct cvmx_pci_cfg10_s cn50xx;
+        struct cvmx_pci_cfg10_s cn58xx;
+        struct cvmx_pci_cfg10_s cn58xxp1;
+};
+
+union cvmx_pci_cfg11 {
+        uint32_t u32;
+        struct cvmx_pci_cfg11_s {
+                uint32_t ssid:16;
+                uint32_t ssvid:16;
+        } s;
+        struct cvmx_pci_cfg11_s cn30xx;
+        struct cvmx_pci_cfg11_s cn31xx;
+        struct cvmx_pci_cfg11_s cn38xx;
+        struct cvmx_pci_cfg11_s cn38xxp2;
+        struct cvmx_pci_cfg11_s cn50xx;
+        struct cvmx_pci_cfg11_s cn58xx;
+        struct cvmx_pci_cfg11_s cn58xxp1;
+};
+
+union cvmx_pci_cfg12 {
+        uint32_t u32;
+        struct cvmx_pci_cfg12_s {
+                uint32_t erbar:16;
+                uint32_t erbarz:5;
+                uint32_t reserved_1_10:10;
+                uint32_t erbar_en:1;
+        } s;
+        struct cvmx_pci_cfg12_s cn30xx;
+        struct cvmx_pci_cfg12_s cn31xx;
+        struct cvmx_pci_cfg12_s cn38xx;
+        struct cvmx_pci_cfg12_s cn38xxp2;
+        struct cvmx_pci_cfg12_s cn50xx;
+        struct cvmx_pci_cfg12_s cn58xx;
+        struct cvmx_pci_cfg12_s cn58xxp1;
+};
+
+union cvmx_pci_cfg13 {
+        uint32_t u32;
+        struct cvmx_pci_cfg13_s {
+                uint32_t reserved_8_31:24;
+                uint32_t cp:8;
+        } s;
+        struct cvmx_pci_cfg13_s cn30xx;
+        struct cvmx_pci_cfg13_s cn31xx;
+        struct cvmx_pci_cfg13_s cn38xx;
+        struct cvmx_pci_cfg13_s cn38xxp2;
+        struct cvmx_pci_cfg13_s cn50xx;
+        struct cvmx_pci_cfg13_s cn58xx;
+        struct cvmx_pci_cfg13_s cn58xxp1;
+};
+
+union cvmx_pci_cfg15 {
+        uint32_t u32;
+        struct cvmx_pci_cfg15_s {
+                uint32_t ml:8;
+                uint32_t mg:8;
+                uint32_t inta:8;
+                uint32_t il:8;
+        } s;
+        struct cvmx_pci_cfg15_s cn30xx;
+        struct cvmx_pci_cfg15_s cn31xx;
+        struct cvmx_pci_cfg15_s cn38xx;
+        struct cvmx_pci_cfg15_s cn38xxp2;
+        struct cvmx_pci_cfg15_s cn50xx;
+        struct cvmx_pci_cfg15_s cn58xx;
+        struct cvmx_pci_cfg15_s cn58xxp1;
+};
+
+union cvmx_pci_cfg16 {
+        uint32_t u32;
+        struct cvmx_pci_cfg16_s {
+                uint32_t trdnpr:1;
+                uint32_t trdard:1;
+                uint32_t rdsati:1;
+                uint32_t trdrs:1;
+                uint32_t trtae:1;
+                uint32_t twsei:1;
+                uint32_t twsen:1;
+                uint32_t twtae:1;
+                uint32_t tmae:1;
+                uint32_t tslte:3;
+                uint32_t tilt:4;
+                uint32_t pbe:12;
+                uint32_t dppmr:1;
+                uint32_t reserved_2_2:1;
+                uint32_t tswc:1;
+                uint32_t mltd:1;
+        } s;
+        struct cvmx_pci_cfg16_s cn30xx;
+        struct cvmx_pci_cfg16_s cn31xx;
+        struct cvmx_pci_cfg16_s cn38xx;
+        struct cvmx_pci_cfg16_s cn38xxp2;
+        struct cvmx_pci_cfg16_s cn50xx;
+        struct cvmx_pci_cfg16_s cn58xx;
+        struct cvmx_pci_cfg16_s cn58xxp1;
+};
+
+union cvmx_pci_cfg17 {
+        uint32_t u32;
+        struct cvmx_pci_cfg17_s {
+                uint32_t tscme:32;
+        } s;
+        struct cvmx_pci_cfg17_s cn30xx;
+        struct cvmx_pci_cfg17_s cn31xx;
+        struct cvmx_pci_cfg17_s cn38xx;
+        struct cvmx_pci_cfg17_s cn38xxp2;
+        struct cvmx_pci_cfg17_s cn50xx;
+        struct cvmx_pci_cfg17_s cn58xx;
+        struct cvmx_pci_cfg17_s cn58xxp1;
+};
+
+union cvmx_pci_cfg18 {
+        uint32_t u32;
+        struct cvmx_pci_cfg18_s {
+                uint32_t tdsrps:32;
+        } s;
+        struct cvmx_pci_cfg18_s cn30xx;
+        struct cvmx_pci_cfg18_s cn31xx;
+        struct cvmx_pci_cfg18_s cn38xx;
+        struct cvmx_pci_cfg18_s cn38xxp2;
+        struct cvmx_pci_cfg18_s cn50xx;
+        struct cvmx_pci_cfg18_s cn58xx;
+        struct cvmx_pci_cfg18_s cn58xxp1;
+};
+
+union cvmx_pci_cfg19 {
+        uint32_t u32;
+        struct cvmx_pci_cfg19_s {
+                uint32_t mrbcm:1;
+                uint32_t mrbci:1;
+                uint32_t mdwe:1;
+                uint32_t mdre:1;
+                uint32_t mdrimc:1;
+                uint32_t mdrrmc:3;
+                uint32_t tmes:8;
+                uint32_t teci:1;
+                uint32_t tmei:1;
+                uint32_t tmse:1;
+                uint32_t tmdpes:1;
+                uint32_t tmapes:1;
+                uint32_t reserved_9_10:2;
+                uint32_t tibcd:1;
+                uint32_t tibde:1;
+                uint32_t reserved_6_6:1;
+                uint32_t tidomc:1;
+                uint32_t tdomc:5;
+        } s;
+        struct cvmx_pci_cfg19_s cn30xx;
+        struct cvmx_pci_cfg19_s cn31xx;
+        struct cvmx_pci_cfg19_s cn38xx;
+        struct cvmx_pci_cfg19_s cn38xxp2;
+        struct cvmx_pci_cfg19_s cn50xx;
+        struct cvmx_pci_cfg19_s cn58xx;
+        struct cvmx_pci_cfg19_s cn58xxp1;
+};
+
+union cvmx_pci_cfg20 {
+        uint32_t u32;
+        struct cvmx_pci_cfg20_s {
+                uint32_t mdsp:32;
+        } s;
+        struct cvmx_pci_cfg20_s cn30xx;
+        struct cvmx_pci_cfg20_s cn31xx;
+        struct cvmx_pci_cfg20_s cn38xx;
+        struct cvmx_pci_cfg20_s cn38xxp2;
+        struct cvmx_pci_cfg20_s cn50xx;
+        struct cvmx_pci_cfg20_s cn58xx;
+        struct cvmx_pci_cfg20_s cn58xxp1;
+};
+
+union cvmx_pci_cfg21 {
+        uint32_t u32;
+        struct cvmx_pci_cfg21_s {
+                uint32_t scmre:32;
+        } s;
+        struct cvmx_pci_cfg21_s cn30xx;
+        struct cvmx_pci_cfg21_s cn31xx;
+        struct cvmx_pci_cfg21_s cn38xx;
+        struct cvmx_pci_cfg21_s cn38xxp2;
+        struct cvmx_pci_cfg21_s cn50xx;
+        struct cvmx_pci_cfg21_s cn58xx;
+        struct cvmx_pci_cfg21_s cn58xxp1;
+};
+
+union cvmx_pci_cfg22 {
+        uint32_t u32;
+        struct cvmx_pci_cfg22_s {
+                uint32_t mac:7;
+                uint32_t reserved_19_24:6;
+                uint32_t flush:1;
+                uint32_t mra:1;
+                uint32_t mtta:1;
+                uint32_t mrv:8;
+                uint32_t mttv:8;
+        } s;
+        struct cvmx_pci_cfg22_s cn30xx;
+        struct cvmx_pci_cfg22_s cn31xx;
+        struct cvmx_pci_cfg22_s cn38xx;
+        struct cvmx_pci_cfg22_s cn38xxp2;
+        struct cvmx_pci_cfg22_s cn50xx;
+        struct cvmx_pci_cfg22_s cn58xx;
+        struct cvmx_pci_cfg22_s cn58xxp1;
+};
+
+union cvmx_pci_cfg56 {
+        uint32_t u32;
+        struct cvmx_pci_cfg56_s {
+                uint32_t reserved_23_31:9;
+                uint32_t most:3;
+                uint32_t mmbc:2;
+                uint32_t roe:1;
+                uint32_t dpere:1;
+                uint32_t ncp:8;
+                uint32_t pxcid:8;
+        } s;
+        struct cvmx_pci_cfg56_s cn30xx;
+        struct cvmx_pci_cfg56_s cn31xx;
+        struct cvmx_pci_cfg56_s cn38xx;
+        struct cvmx_pci_cfg56_s cn38xxp2;
+        struct cvmx_pci_cfg56_s cn50xx;
+        struct cvmx_pci_cfg56_s cn58xx;
+        struct cvmx_pci_cfg56_s cn58xxp1;
+};
+
+union cvmx_pci_cfg57 {
+        uint32_t u32;
+        struct cvmx_pci_cfg57_s {
+                uint32_t reserved_30_31:2;
+                uint32_t scemr:1;
+                uint32_t mcrsd:3;
+                uint32_t mostd:3;
+                uint32_t mmrbcd:2;
+                uint32_t dc:1;
+                uint32_t usc:1;
+                uint32_t scd:1;
+                uint32_t m133:1;
+                uint32_t w64:1;
+                uint32_t bn:8;
+                uint32_t dn:5;
+                uint32_t fn:3;
+        } s;
+        struct cvmx_pci_cfg57_s cn30xx;
+        struct cvmx_pci_cfg57_s cn31xx;
+        struct cvmx_pci_cfg57_s cn38xx;
+        struct cvmx_pci_cfg57_s cn38xxp2;
+        struct cvmx_pci_cfg57_s cn50xx;
+        struct cvmx_pci_cfg57_s cn58xx;
+        struct cvmx_pci_cfg57_s cn58xxp1;
+};
+
+union cvmx_pci_cfg58 {
+        uint32_t u32;
+        struct cvmx_pci_cfg58_s {
+                uint32_t pmes:5;
+                uint32_t d2s:1;
+                uint32_t d1s:1;
+                uint32_t auxc:3;
+                uint32_t dsi:1;
+                uint32_t reserved_20_20:1;
+                uint32_t pmec:1;
+                uint32_t pcimiv:3;
+                uint32_t ncp:8;
+                uint32_t pmcid:8;
+        } s;
+        struct cvmx_pci_cfg58_s cn30xx;
+        struct cvmx_pci_cfg58_s cn31xx;
+        struct cvmx_pci_cfg58_s cn38xx;
+        struct cvmx_pci_cfg58_s cn38xxp2;
+        struct cvmx_pci_cfg58_s cn50xx;
+        struct cvmx_pci_cfg58_s cn58xx;
+        struct cvmx_pci_cfg58_s cn58xxp1;
+};
+
+union cvmx_pci_cfg59 {
+        uint32_t u32;
+        struct cvmx_pci_cfg59_s {
+                uint32_t pmdia:8;
+                uint32_t bpccen:1;
+                uint32_t bd3h:1;
+                uint32_t reserved_16_21:6;
+                uint32_t pmess:1;
+                uint32_t pmedsia:2;
+                uint32_t pmds:4;
+                uint32_t pmeens:1;
+                uint32_t reserved_2_7:6;
+                uint32_t ps:2;
+        } s;
+        struct cvmx_pci_cfg59_s cn30xx;
+        struct cvmx_pci_cfg59_s cn31xx;
+        struct cvmx_pci_cfg59_s cn38xx;
+        struct cvmx_pci_cfg59_s cn38xxp2;
+        struct cvmx_pci_cfg59_s cn50xx;
+        struct cvmx_pci_cfg59_s cn58xx;
+        struct cvmx_pci_cfg59_s cn58xxp1;
+};
+
+union cvmx_pci_cfg60 {
+        uint32_t u32;
+        struct cvmx_pci_cfg60_s {
+                uint32_t reserved_24_31:8;
+                uint32_t m64:1;
+                uint32_t mme:3;
+                uint32_t mmc:3;
+                uint32_t msien:1;
+                uint32_t ncp:8;
+                uint32_t msicid:8;
+        } s;
+        struct cvmx_pci_cfg60_s cn30xx;
+        struct cvmx_pci_cfg60_s cn31xx;
+        struct cvmx_pci_cfg60_s cn38xx;
+        struct cvmx_pci_cfg60_s cn38xxp2;
+        struct cvmx_pci_cfg60_s cn50xx;
+        struct cvmx_pci_cfg60_s cn58xx;
+        struct cvmx_pci_cfg60_s cn58xxp1;
+};
+
+union cvmx_pci_cfg61 {
+        uint32_t u32;
+        struct cvmx_pci_cfg61_s {
+                uint32_t msi31t2:30;
+                uint32_t reserved_0_1:2;
+        } s;
+        struct cvmx_pci_cfg61_s cn30xx;
+        struct cvmx_pci_cfg61_s cn31xx;
+        struct cvmx_pci_cfg61_s cn38xx;
+        struct cvmx_pci_cfg61_s cn38xxp2;
+        struct cvmx_pci_cfg61_s cn50xx;
+        struct cvmx_pci_cfg61_s cn58xx;
+        struct cvmx_pci_cfg61_s cn58xxp1;
+};
+
+union cvmx_pci_cfg62 {
+        uint32_t u32;
+        struct cvmx_pci_cfg62_s {
+                uint32_t msi:32;
+        } s;
+        struct cvmx_pci_cfg62_s cn30xx;
+        struct cvmx_pci_cfg62_s cn31xx;
+        struct cvmx_pci_cfg62_s cn38xx;
+        struct cvmx_pci_cfg62_s cn38xxp2;
+        struct cvmx_pci_cfg62_s cn50xx;
+        struct cvmx_pci_cfg62_s cn58xx;
+        struct cvmx_pci_cfg62_s cn58xxp1;
+};
+
+union cvmx_pci_cfg63 {
+        uint32_t u32;
+        struct cvmx_pci_cfg63_s {
+                uint32_t reserved_16_31:16;
+                uint32_t msimd:16;
+        } s;
+        struct cvmx_pci_cfg63_s cn30xx;
+        struct cvmx_pci_cfg63_s cn31xx;
+        struct cvmx_pci_cfg63_s cn38xx;
+        struct cvmx_pci_cfg63_s cn38xxp2;
+        struct cvmx_pci_cfg63_s cn50xx;
+        struct cvmx_pci_cfg63_s cn58xx;
+        struct cvmx_pci_cfg63_s cn58xxp1;
+};
+
+union cvmx_pci_cnt_reg {
+        uint64_t u64;
+        struct cvmx_pci_cnt_reg_s {
+                uint64_t reserved_38_63:26;
+                uint64_t hm_pcix:1;
+                uint64_t hm_speed:2;
+                uint64_t ap_pcix:1;
+                uint64_t ap_speed:2;
+                uint64_t pcicnt:32;
+        } s;
+        struct cvmx_pci_cnt_reg_s cn50xx;
+        struct cvmx_pci_cnt_reg_s cn58xx;
+        struct cvmx_pci_cnt_reg_s cn58xxp1;
+};
+
+union cvmx_pci_ctl_status_2 {
+        uint32_t u32;
+        struct cvmx_pci_ctl_status_2_s {
+                uint32_t reserved_29_31:3;
+                uint32_t bb1_hole:3;
+                uint32_t bb1_siz:1;
+                uint32_t bb_ca:1;
+                uint32_t bb_es:2;
+                uint32_t bb1:1;
+                uint32_t bb0:1;
+                uint32_t erst_n:1;
+                uint32_t bar2pres:1;
+                uint32_t scmtyp:1;
+                uint32_t scm:1;
+                uint32_t en_wfilt:1;
+                uint32_t reserved_14_14:1;
+                uint32_t ap_pcix:1;
+                uint32_t ap_64ad:1;
+                uint32_t b12_bist:1;
+                uint32_t pmo_amod:1;
+                uint32_t pmo_fpc:3;
+                uint32_t tsr_hwm:3;
+                uint32_t bar2_enb:1;
+                uint32_t bar2_esx:2;
+                uint32_t bar2_cax:1;
+        } s;
+        struct cvmx_pci_ctl_status_2_s cn30xx;
+        struct cvmx_pci_ctl_status_2_cn31xx {
+                uint32_t reserved_20_31:12;
+                uint32_t erst_n:1;
+                uint32_t bar2pres:1;
+                uint32_t scmtyp:1;
+                uint32_t scm:1;
+                uint32_t en_wfilt:1;
+                uint32_t reserved_14_14:1;
+                uint32_t ap_pcix:1;
+                uint32_t ap_64ad:1;
+                uint32_t b12_bist:1;
+                uint32_t pmo_amod:1;
+                uint32_t pmo_fpc:3;
+                uint32_t tsr_hwm:3;
+                uint32_t bar2_enb:1;
+                uint32_t bar2_esx:2;
+                uint32_t bar2_cax:1;
+        } cn31xx;
+        struct cvmx_pci_ctl_status_2_s cn38xx;
+        struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2;
+        struct cvmx_pci_ctl_status_2_s cn50xx;
+        struct cvmx_pci_ctl_status_2_s cn58xx;
+        struct cvmx_pci_ctl_status_2_s cn58xxp1;
+};
+
+union cvmx_pci_dbellx {
+        uint32_t u32;
+        struct cvmx_pci_dbellx_s {
+                uint32_t reserved_16_31:16;
+                uint32_t inc_val:16;
+        } s;
+        struct cvmx_pci_dbellx_s cn30xx;
+        struct cvmx_pci_dbellx_s cn31xx;
+        struct cvmx_pci_dbellx_s cn38xx;
+        struct cvmx_pci_dbellx_s cn38xxp2;
+        struct cvmx_pci_dbellx_s cn50xx;
+        struct cvmx_pci_dbellx_s cn58xx;
+        struct cvmx_pci_dbellx_s cn58xxp1;
+};
+
+union cvmx_pci_dma_cntx {
+        uint32_t u32;
+        struct cvmx_pci_dma_cntx_s {
+                uint32_t dma_cnt:32;
+        } s;
+        struct cvmx_pci_dma_cntx_s cn30xx;
+        struct cvmx_pci_dma_cntx_s cn31xx;
+        struct cvmx_pci_dma_cntx_s cn38xx;
+        struct cvmx_pci_dma_cntx_s cn38xxp2;
+        struct cvmx_pci_dma_cntx_s cn50xx;
+        struct cvmx_pci_dma_cntx_s cn58xx;
+        struct cvmx_pci_dma_cntx_s cn58xxp1;
+};
+
+union cvmx_pci_dma_int_levx {
+        uint32_t u32;
+        struct cvmx_pci_dma_int_levx_s {
+                uint32_t pkt_cnt:32;
+        } s;
+        struct cvmx_pci_dma_int_levx_s cn30xx;
+        struct cvmx_pci_dma_int_levx_s cn31xx;
+        struct cvmx_pci_dma_int_levx_s cn38xx;
+        struct cvmx_pci_dma_int_levx_s cn38xxp2;
+        struct cvmx_pci_dma_int_levx_s cn50xx;
+        struct cvmx_pci_dma_int_levx_s cn58xx;
+        struct cvmx_pci_dma_int_levx_s cn58xxp1;
+};
+
+union cvmx_pci_dma_timex {
+        uint32_t u32;
+        struct cvmx_pci_dma_timex_s {
+                uint32_t dma_time:32;
+        } s;
+        struct cvmx_pci_dma_timex_s cn30xx;
+        struct cvmx_pci_dma_timex_s cn31xx;
+        struct cvmx_pci_dma_timex_s cn38xx;
+        struct cvmx_pci_dma_timex_s cn38xxp2;
+        struct cvmx_pci_dma_timex_s cn50xx;
+        struct cvmx_pci_dma_timex_s cn58xx;
+        struct cvmx_pci_dma_timex_s cn58xxp1;
+};
+
+union cvmx_pci_instr_countx {
+        uint32_t u32;
+        struct cvmx_pci_instr_countx_s {
+                uint32_t icnt:32;
+        } s;
+        struct cvmx_pci_instr_countx_s cn30xx;
+        struct cvmx_pci_instr_countx_s cn31xx;
+        struct cvmx_pci_instr_countx_s cn38xx;
+        struct cvmx_pci_instr_countx_s cn38xxp2;
+        struct cvmx_pci_instr_countx_s cn50xx;
+        struct cvmx_pci_instr_countx_s cn58xx;
+        struct cvmx_pci_instr_countx_s cn58xxp1;
+};
+
+union cvmx_pci_int_enb {
+        uint64_t u64;
+        struct cvmx_pci_int_enb_s {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t idtime1:1;
+                uint64_t idtime0:1;
+                uint64_t idcnt1:1;
+                uint64_t idcnt0:1;
+                uint64_t iptime3:1;
+                uint64_t iptime2:1;
+                uint64_t iptime1:1;
+                uint64_t iptime0:1;
+                uint64_t ipcnt3:1;
+                uint64_t ipcnt2:1;
+                uint64_t ipcnt1:1;
+                uint64_t ipcnt0:1;
+                uint64_t irsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t idperr:1;
+                uint64_t iaperr:1;
+                uint64_t iserr:1;
+                uint64_t itsr_abt:1;
+                uint64_t imsc_msg:1;
+                uint64_t imsi_mabt:1;
+                uint64_t imsi_tabt:1;
+                uint64_t imsi_per:1;
+                uint64_t imr_tto:1;
+                uint64_t imr_abt:1;
+                uint64_t itr_abt:1;
+                uint64_t imr_wtto:1;
+                uint64_t imr_wabt:1;
+                uint64_t itr_wabt:1;
+        } s;
+        struct cvmx_pci_int_enb_cn30xx {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t idtime1:1;
+                uint64_t idtime0:1;
+                uint64_t idcnt1:1;
+                uint64_t idcnt0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t iptime0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t ipcnt0:1;
+                uint64_t irsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t idperr:1;
+                uint64_t iaperr:1;
+                uint64_t iserr:1;
+                uint64_t itsr_abt:1;
+                uint64_t imsc_msg:1;
+                uint64_t imsi_mabt:1;
+                uint64_t imsi_tabt:1;
+                uint64_t imsi_per:1;
+                uint64_t imr_tto:1;
+                uint64_t imr_abt:1;
+                uint64_t itr_abt:1;
+                uint64_t imr_wtto:1;
+                uint64_t imr_wabt:1;
+                uint64_t itr_wabt:1;
+        } cn30xx;
+        struct cvmx_pci_int_enb_cn31xx {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t idtime1:1;
+                uint64_t idtime0:1;
+                uint64_t idcnt1:1;
+                uint64_t idcnt0:1;
+                uint64_t reserved_23_24:2;
+                uint64_t iptime1:1;
+                uint64_t iptime0:1;
+                uint64_t reserved_19_20:2;
+                uint64_t ipcnt1:1;
+                uint64_t ipcnt0:1;
+                uint64_t irsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t idperr:1;
+                uint64_t iaperr:1;
+                uint64_t iserr:1;
+                uint64_t itsr_abt:1;
+                uint64_t imsc_msg:1;
+                uint64_t imsi_mabt:1;
+                uint64_t imsi_tabt:1;
+                uint64_t imsi_per:1;
+                uint64_t imr_tto:1;
+                uint64_t imr_abt:1;
+                uint64_t itr_abt:1;
+                uint64_t imr_wtto:1;
+                uint64_t imr_wabt:1;
+                uint64_t itr_wabt:1;
+        } cn31xx;
+        struct cvmx_pci_int_enb_s cn38xx;
+        struct cvmx_pci_int_enb_s cn38xxp2;
+        struct cvmx_pci_int_enb_cn31xx cn50xx;
+        struct cvmx_pci_int_enb_s cn58xx;
+        struct cvmx_pci_int_enb_s cn58xxp1;
+};
+
+union cvmx_pci_int_enb2 {
+        uint64_t u64;
+        struct cvmx_pci_int_enb2_s {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t rdtime1:1;
+                uint64_t rdtime0:1;
+                uint64_t rdcnt1:1;
+                uint64_t rdcnt0:1;
+                uint64_t rptime3:1;
+                uint64_t rptime2:1;
+                uint64_t rptime1:1;
+                uint64_t rptime0:1;
+                uint64_t rpcnt3:1;
+                uint64_t rpcnt2:1;
+                uint64_t rpcnt1:1;
+                uint64_t rpcnt0:1;
+                uint64_t rrsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t rdperr:1;
+                uint64_t raperr:1;
+                uint64_t rserr:1;
+                uint64_t rtsr_abt:1;
+                uint64_t rmsc_msg:1;
+                uint64_t rmsi_mabt:1;
+                uint64_t rmsi_tabt:1;
+                uint64_t rmsi_per:1;
+                uint64_t rmr_tto:1;
+                uint64_t rmr_abt:1;
+                uint64_t rtr_abt:1;
+                uint64_t rmr_wtto:1;
+                uint64_t rmr_wabt:1;
+                uint64_t rtr_wabt:1;
+        } s;
+        struct cvmx_pci_int_enb2_cn30xx {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t rdtime1:1;
+                uint64_t rdtime0:1;
+                uint64_t rdcnt1:1;
+                uint64_t rdcnt0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t rptime0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t rpcnt0:1;
+                uint64_t rrsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t rdperr:1;
+                uint64_t raperr:1;
+                uint64_t rserr:1;
+                uint64_t rtsr_abt:1;
+                uint64_t rmsc_msg:1;
+                uint64_t rmsi_mabt:1;
+                uint64_t rmsi_tabt:1;
+                uint64_t rmsi_per:1;
+                uint64_t rmr_tto:1;
+                uint64_t rmr_abt:1;
+                uint64_t rtr_abt:1;
+                uint64_t rmr_wtto:1;
+                uint64_t rmr_wabt:1;
+                uint64_t rtr_wabt:1;
+        } cn30xx;
+        struct cvmx_pci_int_enb2_cn31xx {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t rdtime1:1;
+                uint64_t rdtime0:1;
+                uint64_t rdcnt1:1;
+                uint64_t rdcnt0:1;
+                uint64_t reserved_23_24:2;
+                uint64_t rptime1:1;
+                uint64_t rptime0:1;
+                uint64_t reserved_19_20:2;
+                uint64_t rpcnt1:1;
+                uint64_t rpcnt0:1;
+                uint64_t rrsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t rdperr:1;
+                uint64_t raperr:1;
+                uint64_t rserr:1;
+                uint64_t rtsr_abt:1;
+                uint64_t rmsc_msg:1;
+                uint64_t rmsi_mabt:1;
+                uint64_t rmsi_tabt:1;
+                uint64_t rmsi_per:1;
+                uint64_t rmr_tto:1;
+                uint64_t rmr_abt:1;
+                uint64_t rtr_abt:1;
+                uint64_t rmr_wtto:1;
+                uint64_t rmr_wabt:1;
+                uint64_t rtr_wabt:1;
+        } cn31xx;
+        struct cvmx_pci_int_enb2_s cn38xx;
+        struct cvmx_pci_int_enb2_s cn38xxp2;
+        struct cvmx_pci_int_enb2_cn31xx cn50xx;
+        struct cvmx_pci_int_enb2_s cn58xx;
+        struct cvmx_pci_int_enb2_s cn58xxp1;
+};
+
+union cvmx_pci_int_sum {
+        uint64_t u64;
+        struct cvmx_pci_int_sum_s {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t ptime3:1;
+                uint64_t ptime2:1;
+                uint64_t ptime1:1;
+                uint64_t ptime0:1;
+                uint64_t pcnt3:1;
+                uint64_t pcnt2:1;
+                uint64_t pcnt1:1;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+        } s;
+        struct cvmx_pci_int_sum_cn30xx {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t ptime0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+        } cn30xx;
+        struct cvmx_pci_int_sum_cn31xx {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t reserved_23_24:2;
+                uint64_t ptime1:1;
+                uint64_t ptime0:1;
+                uint64_t reserved_19_20:2;
+                uint64_t pcnt1:1;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+        } cn31xx;
+        struct cvmx_pci_int_sum_s cn38xx;
+        struct cvmx_pci_int_sum_s cn38xxp2;
+        struct cvmx_pci_int_sum_cn31xx cn50xx;
+        struct cvmx_pci_int_sum_s cn58xx;
+        struct cvmx_pci_int_sum_s cn58xxp1;
+};
+
+union cvmx_pci_int_sum2 {
+        uint64_t u64;
+        struct cvmx_pci_int_sum2_s {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t ptime3:1;
+                uint64_t ptime2:1;
+                uint64_t ptime1:1;
+                uint64_t ptime0:1;
+                uint64_t pcnt3:1;
+                uint64_t pcnt2:1;
+                uint64_t pcnt1:1;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+        } s;
+        struct cvmx_pci_int_sum2_cn30xx {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t reserved_22_24:3;
+                uint64_t ptime0:1;
+                uint64_t reserved_18_20:3;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+        } cn30xx;
+        struct cvmx_pci_int_sum2_cn31xx {
+                uint64_t reserved_34_63:30;
+                uint64_t ill_rd:1;
+                uint64_t ill_wr:1;
+                uint64_t win_wr:1;
+                uint64_t dma1_fi:1;
+                uint64_t dma0_fi:1;
+                uint64_t dtime1:1;
+                uint64_t dtime0:1;
+                uint64_t dcnt1:1;
+                uint64_t dcnt0:1;
+                uint64_t reserved_23_24:2;
+                uint64_t ptime1:1;
+                uint64_t ptime0:1;
+                uint64_t reserved_19_20:2;
+                uint64_t pcnt1:1;
+                uint64_t pcnt0:1;
+                uint64_t rsl_int:1;
+                uint64_t ill_rrd:1;
+                uint64_t ill_rwr:1;
+                uint64_t dperr:1;
+                uint64_t aperr:1;
+                uint64_t serr:1;
+                uint64_t tsr_abt:1;
+                uint64_t msc_msg:1;
+                uint64_t msi_mabt:1;
+                uint64_t msi_tabt:1;
+                uint64_t msi_per:1;
+                uint64_t mr_tto:1;
+                uint64_t mr_abt:1;
+                uint64_t tr_abt:1;
+                uint64_t mr_wtto:1;
+                uint64_t mr_wabt:1;
+                uint64_t tr_wabt:1;
+        } cn31xx;
+        struct cvmx_pci_int_sum2_s cn38xx;
+        struct cvmx_pci_int_sum2_s cn38xxp2;
+        struct cvmx_pci_int_sum2_cn31xx cn50xx;
+        struct cvmx_pci_int_sum2_s cn58xx;
+        struct cvmx_pci_int_sum2_s cn58xxp1;
+};
+
+union cvmx_pci_msi_rcv {
+        uint32_t u32;
+        struct cvmx_pci_msi_rcv_s {
+                uint32_t reserved_6_31:26;
+                uint32_t intr:6;
+        } s;
+        struct cvmx_pci_msi_rcv_s cn30xx;
+        struct cvmx_pci_msi_rcv_s cn31xx;
+        struct cvmx_pci_msi_rcv_s cn38xx;
+        struct cvmx_pci_msi_rcv_s cn38xxp2;
+        struct cvmx_pci_msi_rcv_s cn50xx;
+        struct cvmx_pci_msi_rcv_s cn58xx;
+        struct cvmx_pci_msi_rcv_s cn58xxp1;
+};
+
+union cvmx_pci_pkt_creditsx {
+        uint32_t u32;
+        struct cvmx_pci_pkt_creditsx_s {
+                uint32_t pkt_cnt:16;
+                uint32_t ptr_cnt:16;
+        } s;
+        struct cvmx_pci_pkt_creditsx_s cn30xx;
+        struct cvmx_pci_pkt_creditsx_s cn31xx;
+        struct cvmx_pci_pkt_creditsx_s cn38xx;
+        struct cvmx_pci_pkt_creditsx_s cn38xxp2;
+        struct cvmx_pci_pkt_creditsx_s cn50xx;
+        struct cvmx_pci_pkt_creditsx_s cn58xx;
+        struct cvmx_pci_pkt_creditsx_s cn58xxp1;
+};
+
+union cvmx_pci_pkts_sentx {
+        uint32_t u32;
+        struct cvmx_pci_pkts_sentx_s {
+                uint32_t pkt_cnt:32;
+        } s;
+        struct cvmx_pci_pkts_sentx_s cn30xx;
+        struct cvmx_pci_pkts_sentx_s cn31xx;
+        struct cvmx_pci_pkts_sentx_s cn38xx;
+        struct cvmx_pci_pkts_sentx_s cn38xxp2;
+        struct cvmx_pci_pkts_sentx_s cn50xx;
+        struct cvmx_pci_pkts_sentx_s cn58xx;
+        struct cvmx_pci_pkts_sentx_s cn58xxp1;
+};
+
+union cvmx_pci_pkts_sent_int_levx {
+        uint32_t u32;
+        struct cvmx_pci_pkts_sent_int_levx_s {
+                uint32_t pkt_cnt:32;
+        } s;
+        struct cvmx_pci_pkts_sent_int_levx_s cn30xx;
+        struct cvmx_pci_pkts_sent_int_levx_s cn31xx;
+        struct cvmx_pci_pkts_sent_int_levx_s cn38xx;
+        struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2;
+        struct cvmx_pci_pkts_sent_int_levx_s cn50xx;
+        struct cvmx_pci_pkts_sent_int_levx_s cn58xx;
+        struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1;
+};
+
+union cvmx_pci_pkts_sent_timex {
+        uint32_t u32;
+        struct cvmx_pci_pkts_sent_timex_s {
+                uint32_t pkt_time:32;
+        } s;
+        struct cvmx_pci_pkts_sent_timex_s cn30xx;
+        struct cvmx_pci_pkts_sent_timex_s cn31xx;
+        struct cvmx_pci_pkts_sent_timex_s cn38xx;
+        struct cvmx_pci_pkts_sent_timex_s cn38xxp2;
+        struct cvmx_pci_pkts_sent_timex_s cn50xx;
+        struct cvmx_pci_pkts_sent_timex_s cn58xx;
+        struct cvmx_pci_pkts_sent_timex_s cn58xxp1;
+};
+
+union cvmx_pci_read_cmd_6 {
+        uint32_t u32;
+        struct cvmx_pci_read_cmd_6_s {
+                uint32_t reserved_9_31:23;
+                uint32_t min_data:6;
+                uint32_t prefetch:3;
+        } s;
+        struct cvmx_pci_read_cmd_6_s cn30xx;
+        struct cvmx_pci_read_cmd_6_s cn31xx;
+        struct cvmx_pci_read_cmd_6_s cn38xx;
+        struct cvmx_pci_read_cmd_6_s cn38xxp2;
+        struct cvmx_pci_read_cmd_6_s cn50xx;
+        struct cvmx_pci_read_cmd_6_s cn58xx;
+        struct cvmx_pci_read_cmd_6_s cn58xxp1;
+};
+
+union cvmx_pci_read_cmd_c {
+        uint32_t u32;
+        struct cvmx_pci_read_cmd_c_s {
+                uint32_t reserved_9_31:23;
+                uint32_t min_data:6;
+                uint32_t prefetch:3;
+        } s;
+        struct cvmx_pci_read_cmd_c_s cn30xx;
+        struct cvmx_pci_read_cmd_c_s cn31xx;
+        struct cvmx_pci_read_cmd_c_s cn38xx;
+        struct cvmx_pci_read_cmd_c_s cn38xxp2;
+        struct cvmx_pci_read_cmd_c_s cn50xx;
+        struct cvmx_pci_read_cmd_c_s cn58xx;
+        struct cvmx_pci_read_cmd_c_s cn58xxp1;
+};
+
+union cvmx_pci_read_cmd_e {
+        uint32_t u32;
+        struct cvmx_pci_read_cmd_e_s {
+                uint32_t reserved_9_31:23;
+                uint32_t min_data:6;
+                uint32_t prefetch:3;
+        } s;
+        struct cvmx_pci_read_cmd_e_s cn30xx;
+        struct cvmx_pci_read_cmd_e_s cn31xx;
+        struct cvmx_pci_read_cmd_e_s cn38xx;
+        struct cvmx_pci_read_cmd_e_s cn38xxp2;
+        struct cvmx_pci_read_cmd_e_s cn50xx;
+        struct cvmx_pci_read_cmd_e_s cn58xx;
+        struct cvmx_pci_read_cmd_e_s cn58xxp1;
+};
+
+union cvmx_pci_read_timeout {
+        uint64_t u64;
+        struct cvmx_pci_read_timeout_s {
+                uint64_t reserved_32_63:32;
+                uint64_t enb:1;
+                uint64_t cnt:31;
+        } s;
+        struct cvmx_pci_read_timeout_s cn30xx;
+        struct cvmx_pci_read_timeout_s cn31xx;
+        struct cvmx_pci_read_timeout_s cn38xx;
+        struct cvmx_pci_read_timeout_s cn38xxp2;
+        struct cvmx_pci_read_timeout_s cn50xx;
+        struct cvmx_pci_read_timeout_s cn58xx;
+        struct cvmx_pci_read_timeout_s cn58xxp1;
+};
+
+union cvmx_pci_scm_reg {
+        uint64_t u64;
+        struct cvmx_pci_scm_reg_s {
+                uint64_t reserved_32_63:32;
+                uint64_t scm:32;
+        } s;
+        struct cvmx_pci_scm_reg_s cn30xx;
+        struct cvmx_pci_scm_reg_s cn31xx;
+        struct cvmx_pci_scm_reg_s cn38xx;
+        struct cvmx_pci_scm_reg_s cn38xxp2;
+        struct cvmx_pci_scm_reg_s cn50xx;
+        struct cvmx_pci_scm_reg_s cn58xx;
+        struct cvmx_pci_scm_reg_s cn58xxp1;
+};
+
+union cvmx_pci_tsr_reg {
+        uint64_t u64;
+        struct cvmx_pci_tsr_reg_s {
+                uint64_t reserved_36_63:28;
+                uint64_t tsr:36;
+        } s;
+        struct cvmx_pci_tsr_reg_s cn30xx;
+        struct cvmx_pci_tsr_reg_s cn31xx;
+        struct cvmx_pci_tsr_reg_s cn38xx;
+        struct cvmx_pci_tsr_reg_s cn38xxp2;
+        struct cvmx_pci_tsr_reg_s cn50xx;
+        struct cvmx_pci_tsr_reg_s cn58xx;
+        struct cvmx_pci_tsr_reg_s cn58xxp1;
+};
+
+union cvmx_pci_win_rd_addr {
+        uint64_t u64;
+        struct cvmx_pci_win_rd_addr_s {
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t reserved_0_47:48;
+        } s;
+        struct cvmx_pci_win_rd_addr_cn30xx {
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t rd_addr:46;
+                uint64_t reserved_0_1:2;
+        } cn30xx;
+        struct cvmx_pci_win_rd_addr_cn30xx cn31xx;
+        struct cvmx_pci_win_rd_addr_cn38xx {
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t rd_addr:45;
+                uint64_t reserved_0_2:3;
+        } cn38xx;
+        struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2;
+        struct cvmx_pci_win_rd_addr_cn30xx cn50xx;
+        struct cvmx_pci_win_rd_addr_cn38xx cn58xx;
+        struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1;
+};
+
+union cvmx_pci_win_rd_data {
+        uint64_t u64;
+        struct cvmx_pci_win_rd_data_s {
+                uint64_t rd_data:64;
+        } s;
+        struct cvmx_pci_win_rd_data_s cn30xx;
+        struct cvmx_pci_win_rd_data_s cn31xx;
+        struct cvmx_pci_win_rd_data_s cn38xx;
+        struct cvmx_pci_win_rd_data_s cn38xxp2;
+        struct cvmx_pci_win_rd_data_s cn50xx;
+        struct cvmx_pci_win_rd_data_s cn58xx;
+        struct cvmx_pci_win_rd_data_s cn58xxp1;
+};
+
+union cvmx_pci_win_wr_addr {
+        uint64_t u64;
+        struct cvmx_pci_win_wr_addr_s {
+                uint64_t reserved_49_63:15;
+                uint64_t iobit:1;
+                uint64_t wr_addr:45;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_pci_win_wr_addr_s cn30xx;
+        struct cvmx_pci_win_wr_addr_s cn31xx;
+        struct cvmx_pci_win_wr_addr_s cn38xx;
+        struct cvmx_pci_win_wr_addr_s cn38xxp2;
+        struct cvmx_pci_win_wr_addr_s cn50xx;
+        struct cvmx_pci_win_wr_addr_s cn58xx;
+        struct cvmx_pci_win_wr_addr_s cn58xxp1;
+};
+
+union cvmx_pci_win_wr_data {
+        uint64_t u64;
+        struct cvmx_pci_win_wr_data_s {
+                uint64_t wr_data:64;
+        } s;
+        struct cvmx_pci_win_wr_data_s cn30xx;
+        struct cvmx_pci_win_wr_data_s cn31xx;
+        struct cvmx_pci_win_wr_data_s cn38xx;
+        struct cvmx_pci_win_wr_data_s cn38xxp2;
+        struct cvmx_pci_win_wr_data_s cn50xx;
+        struct cvmx_pci_win_wr_data_s cn58xx;
+        struct cvmx_pci_win_wr_data_s cn58xxp1;
+};
+
+union cvmx_pci_win_wr_mask {
+        uint64_t u64;
+        struct cvmx_pci_win_wr_mask_s {
+                uint64_t reserved_8_63:56;
+                uint64_t wr_mask:8;
+        } s;
+        struct cvmx_pci_win_wr_mask_s cn30xx;
+        struct cvmx_pci_win_wr_mask_s cn31xx;
+        struct cvmx_pci_win_wr_mask_s cn38xx;
+        struct cvmx_pci_win_wr_mask_s cn38xxp2;
+        struct cvmx_pci_win_wr_mask_s cn50xx;
+        struct cvmx_pci_win_wr_mask_s cn58xx;
+        struct cvmx_pci_win_wr_mask_s cn58xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
new file mode 100644
index 000000000000..d553f8e88df6
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
@@ -0,0 +1,1365 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PCIEEP_DEFS_H__
+#define __CVMX_PCIEEP_DEFS_H__
+
+#define CVMX_PCIEEP_CFG000 \
+         (0x0000000000000000ull)
+#define CVMX_PCIEEP_CFG001 \
+         (0x0000000000000004ull)
+#define CVMX_PCIEEP_CFG002 \
+         (0x0000000000000008ull)
+#define CVMX_PCIEEP_CFG003 \
+         (0x000000000000000Cull)
+#define CVMX_PCIEEP_CFG004 \
+         (0x0000000000000010ull)
+#define CVMX_PCIEEP_CFG004_MASK \
+         (0x0000000080000010ull)
+#define CVMX_PCIEEP_CFG005 \
+         (0x0000000000000014ull)
+#define CVMX_PCIEEP_CFG005_MASK \
+         (0x0000000080000014ull)
+#define CVMX_PCIEEP_CFG006 \
+         (0x0000000000000018ull)
+#define CVMX_PCIEEP_CFG006_MASK \
+         (0x0000000080000018ull)
+#define CVMX_PCIEEP_CFG007 \
+         (0x000000000000001Cull)
+#define CVMX_PCIEEP_CFG007_MASK \
+         (0x000000008000001Cull)
+#define CVMX_PCIEEP_CFG008 \
+         (0x0000000000000020ull)
+#define CVMX_PCIEEP_CFG008_MASK \
+         (0x0000000080000020ull)
+#define CVMX_PCIEEP_CFG009 \
+         (0x0000000000000024ull)
+#define CVMX_PCIEEP_CFG009_MASK \
+         (0x0000000080000024ull)
+#define CVMX_PCIEEP_CFG010 \
+         (0x0000000000000028ull)
+#define CVMX_PCIEEP_CFG011 \
+         (0x000000000000002Cull)
+#define CVMX_PCIEEP_CFG012 \
+         (0x0000000000000030ull)
+#define CVMX_PCIEEP_CFG012_MASK \
+         (0x0000000080000030ull)
+#define CVMX_PCIEEP_CFG013 \
+         (0x0000000000000034ull)
+#define CVMX_PCIEEP_CFG015 \
+         (0x000000000000003Cull)
+#define CVMX_PCIEEP_CFG016 \
+         (0x0000000000000040ull)
+#define CVMX_PCIEEP_CFG017 \
+         (0x0000000000000044ull)
+#define CVMX_PCIEEP_CFG020 \
+         (0x0000000000000050ull)
+#define CVMX_PCIEEP_CFG021 \
+         (0x0000000000000054ull)
+#define CVMX_PCIEEP_CFG022 \
+         (0x0000000000000058ull)
+#define CVMX_PCIEEP_CFG023 \
+         (0x000000000000005Cull)
+#define CVMX_PCIEEP_CFG028 \
+         (0x0000000000000070ull)
+#define CVMX_PCIEEP_CFG029 \
+         (0x0000000000000074ull)
+#define CVMX_PCIEEP_CFG030 \
+         (0x0000000000000078ull)
+#define CVMX_PCIEEP_CFG031 \
+         (0x000000000000007Cull)
+#define CVMX_PCIEEP_CFG032 \
+         (0x0000000000000080ull)
+#define CVMX_PCIEEP_CFG033 \
+         (0x0000000000000084ull)
+#define CVMX_PCIEEP_CFG034 \
+         (0x0000000000000088ull)
+#define CVMX_PCIEEP_CFG037 \
+         (0x0000000000000094ull)
+#define CVMX_PCIEEP_CFG038 \
+         (0x0000000000000098ull)
+#define CVMX_PCIEEP_CFG039 \
+         (0x000000000000009Cull)
+#define CVMX_PCIEEP_CFG040 \
+         (0x00000000000000A0ull)
+#define CVMX_PCIEEP_CFG041 \
+         (0x00000000000000A4ull)
+#define CVMX_PCIEEP_CFG042 \
+         (0x00000000000000A8ull)
+#define CVMX_PCIEEP_CFG064 \
+         (0x0000000000000100ull)
+#define CVMX_PCIEEP_CFG065 \
+         (0x0000000000000104ull)
+#define CVMX_PCIEEP_CFG066 \
+         (0x0000000000000108ull)
+#define CVMX_PCIEEP_CFG067 \
+         (0x000000000000010Cull)
+#define CVMX_PCIEEP_CFG068 \
+         (0x0000000000000110ull)
+#define CVMX_PCIEEP_CFG069 \
+         (0x0000000000000114ull)
+#define CVMX_PCIEEP_CFG070 \
+         (0x0000000000000118ull)
+#define CVMX_PCIEEP_CFG071 \
+         (0x000000000000011Cull)
+#define CVMX_PCIEEP_CFG072 \
+         (0x0000000000000120ull)
+#define CVMX_PCIEEP_CFG073 \
+         (0x0000000000000124ull)
+#define CVMX_PCIEEP_CFG074 \
+         (0x0000000000000128ull)
+#define CVMX_PCIEEP_CFG448 \
+         (0x0000000000000700ull)
+#define CVMX_PCIEEP_CFG449 \
+         (0x0000000000000704ull)
+#define CVMX_PCIEEP_CFG450 \
+         (0x0000000000000708ull)
+#define CVMX_PCIEEP_CFG451 \
+         (0x000000000000070Cull)
+#define CVMX_PCIEEP_CFG452 \
+         (0x0000000000000710ull)
+#define CVMX_PCIEEP_CFG453 \
+         (0x0000000000000714ull)
+#define CVMX_PCIEEP_CFG454 \
+         (0x0000000000000718ull)
+#define CVMX_PCIEEP_CFG455 \
+         (0x000000000000071Cull)
+#define CVMX_PCIEEP_CFG456 \
+         (0x0000000000000720ull)
+#define CVMX_PCIEEP_CFG458 \
+         (0x0000000000000728ull)
+#define CVMX_PCIEEP_CFG459 \
+         (0x000000000000072Cull)
+#define CVMX_PCIEEP_CFG460 \
+         (0x0000000000000730ull)
+#define CVMX_PCIEEP_CFG461 \
+         (0x0000000000000734ull)
+#define CVMX_PCIEEP_CFG462 \
+         (0x0000000000000738ull)
+#define CVMX_PCIEEP_CFG463 \
+         (0x000000000000073Cull)
+#define CVMX_PCIEEP_CFG464 \
+         (0x0000000000000740ull)
+#define CVMX_PCIEEP_CFG465 \
+         (0x0000000000000744ull)
+#define CVMX_PCIEEP_CFG466 \
+         (0x0000000000000748ull)
+#define CVMX_PCIEEP_CFG467 \
+         (0x000000000000074Cull)
+#define CVMX_PCIEEP_CFG468 \
+         (0x0000000000000750ull)
+#define CVMX_PCIEEP_CFG490 \
+         (0x00000000000007A8ull)
+#define CVMX_PCIEEP_CFG491 \
+         (0x00000000000007ACull)
+#define CVMX_PCIEEP_CFG492 \
+         (0x00000000000007B0ull)
+#define CVMX_PCIEEP_CFG516 \
+         (0x0000000000000810ull)
+#define CVMX_PCIEEP_CFG517 \
+         (0x0000000000000814ull)
+
+union cvmx_pcieep_cfg000 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg000_s {
+                uint32_t devid:16;
+                uint32_t vendid:16;
+        } s;
+        struct cvmx_pcieep_cfg000_s cn52xx;
+        struct cvmx_pcieep_cfg000_s cn52xxp1;
+        struct cvmx_pcieep_cfg000_s cn56xx;
+        struct cvmx_pcieep_cfg000_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg001 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg001_s {
+                uint32_t dpe:1;
+                uint32_t sse:1;
+                uint32_t rma:1;
+                uint32_t rta:1;
+                uint32_t sta:1;
+                uint32_t devt:2;
+                uint32_t mdpe:1;
+                uint32_t fbb:1;
+                uint32_t reserved_22_22:1;
+                uint32_t m66:1;
+                uint32_t cl:1;
+                uint32_t i_stat:1;
+                uint32_t reserved_11_18:8;
+                uint32_t i_dis:1;
+                uint32_t fbbe:1;
+                uint32_t see:1;
+                uint32_t ids_wcc:1;
+                uint32_t per:1;
+                uint32_t vps:1;
+                uint32_t mwice:1;
+                uint32_t scse:1;
+                uint32_t me:1;
+                uint32_t msae:1;
+                uint32_t isae:1;
+        } s;
+        struct cvmx_pcieep_cfg001_s cn52xx;
+        struct cvmx_pcieep_cfg001_s cn52xxp1;
+        struct cvmx_pcieep_cfg001_s cn56xx;
+        struct cvmx_pcieep_cfg001_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg002 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg002_s {
+                uint32_t bcc:8;
+                uint32_t sc:8;
+                uint32_t pi:8;
+                uint32_t rid:8;
+        } s;
+        struct cvmx_pcieep_cfg002_s cn52xx;
+        struct cvmx_pcieep_cfg002_s cn52xxp1;
+        struct cvmx_pcieep_cfg002_s cn56xx;
+        struct cvmx_pcieep_cfg002_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg003 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg003_s {
+                uint32_t bist:8;
+                uint32_t mfd:1;
+                uint32_t chf:7;
+                uint32_t lt:8;
+                uint32_t cls:8;
+        } s;
+        struct cvmx_pcieep_cfg003_s cn52xx;
+        struct cvmx_pcieep_cfg003_s cn52xxp1;
+        struct cvmx_pcieep_cfg003_s cn56xx;
+        struct cvmx_pcieep_cfg003_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg004 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg004_s {
+                uint32_t lbab:18;
+                uint32_t reserved_4_13:10;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+        } s;
+        struct cvmx_pcieep_cfg004_s cn52xx;
+        struct cvmx_pcieep_cfg004_s cn52xxp1;
+        struct cvmx_pcieep_cfg004_s cn56xx;
+        struct cvmx_pcieep_cfg004_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg004_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg004_mask_s {
+                uint32_t lmask:31;
+                uint32_t enb:1;
+        } s;
+        struct cvmx_pcieep_cfg004_mask_s cn52xx;
+        struct cvmx_pcieep_cfg004_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg004_mask_s cn56xx;
+        struct cvmx_pcieep_cfg004_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg005 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg005_s {
+                uint32_t ubab:32;
+        } s;
+        struct cvmx_pcieep_cfg005_s cn52xx;
+        struct cvmx_pcieep_cfg005_s cn52xxp1;
+        struct cvmx_pcieep_cfg005_s cn56xx;
+        struct cvmx_pcieep_cfg005_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg005_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg005_mask_s {
+                uint32_t umask:32;
+        } s;
+        struct cvmx_pcieep_cfg005_mask_s cn52xx;
+        struct cvmx_pcieep_cfg005_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg005_mask_s cn56xx;
+        struct cvmx_pcieep_cfg005_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg006 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg006_s {
+                uint32_t lbab:6;
+                uint32_t reserved_4_25:22;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+        } s;
+        struct cvmx_pcieep_cfg006_s cn52xx;
+        struct cvmx_pcieep_cfg006_s cn52xxp1;
+        struct cvmx_pcieep_cfg006_s cn56xx;
+        struct cvmx_pcieep_cfg006_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg006_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg006_mask_s {
+                uint32_t lmask:31;
+                uint32_t enb:1;
+        } s;
+        struct cvmx_pcieep_cfg006_mask_s cn52xx;
+        struct cvmx_pcieep_cfg006_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg006_mask_s cn56xx;
+        struct cvmx_pcieep_cfg006_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg007 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg007_s {
+                uint32_t ubab:32;
+        } s;
+        struct cvmx_pcieep_cfg007_s cn52xx;
+        struct cvmx_pcieep_cfg007_s cn52xxp1;
+        struct cvmx_pcieep_cfg007_s cn56xx;
+        struct cvmx_pcieep_cfg007_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg007_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg007_mask_s {
+                uint32_t umask:32;
+        } s;
+        struct cvmx_pcieep_cfg007_mask_s cn52xx;
+        struct cvmx_pcieep_cfg007_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg007_mask_s cn56xx;
+        struct cvmx_pcieep_cfg007_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg008 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg008_s {
+                uint32_t reserved_4_31:28;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+        } s;
+        struct cvmx_pcieep_cfg008_s cn52xx;
+        struct cvmx_pcieep_cfg008_s cn52xxp1;
+        struct cvmx_pcieep_cfg008_s cn56xx;
+        struct cvmx_pcieep_cfg008_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg008_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg008_mask_s {
+                uint32_t lmask:31;
+                uint32_t enb:1;
+        } s;
+        struct cvmx_pcieep_cfg008_mask_s cn52xx;
+        struct cvmx_pcieep_cfg008_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg008_mask_s cn56xx;
+        struct cvmx_pcieep_cfg008_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg009 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg009_s {
+                uint32_t ubab:25;
+                uint32_t reserved_0_6:7;
+        } s;
+        struct cvmx_pcieep_cfg009_s cn52xx;
+        struct cvmx_pcieep_cfg009_s cn52xxp1;
+        struct cvmx_pcieep_cfg009_s cn56xx;
+        struct cvmx_pcieep_cfg009_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg009_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg009_mask_s {
+                uint32_t umask:32;
+        } s;
+        struct cvmx_pcieep_cfg009_mask_s cn52xx;
+        struct cvmx_pcieep_cfg009_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg009_mask_s cn56xx;
+        struct cvmx_pcieep_cfg009_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg010 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg010_s {
+                uint32_t cisp:32;
+        } s;
+        struct cvmx_pcieep_cfg010_s cn52xx;
+        struct cvmx_pcieep_cfg010_s cn52xxp1;
+        struct cvmx_pcieep_cfg010_s cn56xx;
+        struct cvmx_pcieep_cfg010_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg011 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg011_s {
+                uint32_t ssid:16;
+                uint32_t ssvid:16;
+        } s;
+        struct cvmx_pcieep_cfg011_s cn52xx;
+        struct cvmx_pcieep_cfg011_s cn52xxp1;
+        struct cvmx_pcieep_cfg011_s cn56xx;
+        struct cvmx_pcieep_cfg011_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg012 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg012_s {
+                uint32_t eraddr:16;
+                uint32_t reserved_1_15:15;
+                uint32_t er_en:1;
+        } s;
+        struct cvmx_pcieep_cfg012_s cn52xx;
+        struct cvmx_pcieep_cfg012_s cn52xxp1;
+        struct cvmx_pcieep_cfg012_s cn56xx;
+        struct cvmx_pcieep_cfg012_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg012_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg012_mask_s {
+                uint32_t mask:31;
+                uint32_t enb:1;
+        } s;
+        struct cvmx_pcieep_cfg012_mask_s cn52xx;
+        struct cvmx_pcieep_cfg012_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg012_mask_s cn56xx;
+        struct cvmx_pcieep_cfg012_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg013 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg013_s {
+                uint32_t reserved_8_31:24;
+                uint32_t cp:8;
+        } s;
+        struct cvmx_pcieep_cfg013_s cn52xx;
+        struct cvmx_pcieep_cfg013_s cn52xxp1;
+        struct cvmx_pcieep_cfg013_s cn56xx;
+        struct cvmx_pcieep_cfg013_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg015 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg015_s {
+                uint32_t ml:8;
+                uint32_t mg:8;
+                uint32_t inta:8;
+                uint32_t il:8;
+        } s;
+        struct cvmx_pcieep_cfg015_s cn52xx;
+        struct cvmx_pcieep_cfg015_s cn52xxp1;
+        struct cvmx_pcieep_cfg015_s cn56xx;
+        struct cvmx_pcieep_cfg015_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg016 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg016_s {
+                uint32_t pmes:5;
+                uint32_t d2s:1;
+                uint32_t d1s:1;
+                uint32_t auxc:3;
+                uint32_t dsi:1;
+                uint32_t reserved_20_20:1;
+                uint32_t pme_clock:1;
+                uint32_t pmsv:3;
+                uint32_t ncp:8;
+                uint32_t pmcid:8;
+        } s;
+        struct cvmx_pcieep_cfg016_s cn52xx;
+        struct cvmx_pcieep_cfg016_s cn52xxp1;
+        struct cvmx_pcieep_cfg016_s cn56xx;
+        struct cvmx_pcieep_cfg016_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg017 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg017_s {
+                uint32_t pmdia:8;
+                uint32_t bpccee:1;
+                uint32_t bd3h:1;
+                uint32_t reserved_16_21:6;
+                uint32_t pmess:1;
+                uint32_t pmedsia:2;
+                uint32_t pmds:4;
+                uint32_t pmeens:1;
+                uint32_t reserved_4_7:4;
+                uint32_t nsr:1;
+                uint32_t reserved_2_2:1;
+                uint32_t ps:2;
+        } s;
+        struct cvmx_pcieep_cfg017_s cn52xx;
+        struct cvmx_pcieep_cfg017_s cn52xxp1;
+        struct cvmx_pcieep_cfg017_s cn56xx;
+        struct cvmx_pcieep_cfg017_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg020 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg020_s {
+                uint32_t reserved_24_31:8;
+                uint32_t m64:1;
+                uint32_t mme:3;
+                uint32_t mmc:3;
+                uint32_t msien:1;
+                uint32_t ncp:8;
+                uint32_t msicid:8;
+        } s;
+        struct cvmx_pcieep_cfg020_s cn52xx;
+        struct cvmx_pcieep_cfg020_s cn52xxp1;
+        struct cvmx_pcieep_cfg020_s cn56xx;
+        struct cvmx_pcieep_cfg020_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg021 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg021_s {
+                uint32_t lmsi:30;
+                uint32_t reserved_0_1:2;
+        } s;
+        struct cvmx_pcieep_cfg021_s cn52xx;
+        struct cvmx_pcieep_cfg021_s cn52xxp1;
+        struct cvmx_pcieep_cfg021_s cn56xx;
+        struct cvmx_pcieep_cfg021_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg022 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg022_s {
+                uint32_t umsi:32;
+        } s;
+        struct cvmx_pcieep_cfg022_s cn52xx;
+        struct cvmx_pcieep_cfg022_s cn52xxp1;
+        struct cvmx_pcieep_cfg022_s cn56xx;
+        struct cvmx_pcieep_cfg022_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg023 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg023_s {
+                uint32_t reserved_16_31:16;
+                uint32_t msimd:16;
+        } s;
+        struct cvmx_pcieep_cfg023_s cn52xx;
+        struct cvmx_pcieep_cfg023_s cn52xxp1;
+        struct cvmx_pcieep_cfg023_s cn56xx;
+        struct cvmx_pcieep_cfg023_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg028 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg028_s {
+                uint32_t reserved_30_31:2;
+                uint32_t imn:5;
+                uint32_t si:1;
+                uint32_t dpt:4;
+                uint32_t pciecv:4;
+                uint32_t ncp:8;
+                uint32_t pcieid:8;
+        } s;
+        struct cvmx_pcieep_cfg028_s cn52xx;
+        struct cvmx_pcieep_cfg028_s cn52xxp1;
+        struct cvmx_pcieep_cfg028_s cn56xx;
+        struct cvmx_pcieep_cfg028_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg029 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg029_s {
+                uint32_t reserved_28_31:4;
+                uint32_t cspls:2;
+                uint32_t csplv:8;
+                uint32_t reserved_16_17:2;
+                uint32_t rber:1;
+                uint32_t reserved_12_14:3;
+                uint32_t el1al:3;
+                uint32_t el0al:3;
+                uint32_t etfs:1;
+                uint32_t pfs:2;
+                uint32_t mpss:3;
+        } s;
+        struct cvmx_pcieep_cfg029_s cn52xx;
+        struct cvmx_pcieep_cfg029_s cn52xxp1;
+        struct cvmx_pcieep_cfg029_s cn56xx;
+        struct cvmx_pcieep_cfg029_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg030 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg030_s {
+                uint32_t reserved_22_31:10;
+                uint32_t tp:1;
+                uint32_t ap_d:1;
+                uint32_t ur_d:1;
+                uint32_t fe_d:1;
+                uint32_t nfe_d:1;
+                uint32_t ce_d:1;
+                uint32_t reserved_15_15:1;
+                uint32_t mrrs:3;
+                uint32_t ns_en:1;
+                uint32_t ap_en:1;
+                uint32_t pf_en:1;
+                uint32_t etf_en:1;
+                uint32_t mps:3;
+                uint32_t ro_en:1;
+                uint32_t ur_en:1;
+                uint32_t fe_en:1;
+                uint32_t nfe_en:1;
+                uint32_t ce_en:1;
+        } s;
+        struct cvmx_pcieep_cfg030_s cn52xx;
+        struct cvmx_pcieep_cfg030_s cn52xxp1;
+        struct cvmx_pcieep_cfg030_s cn56xx;
+        struct cvmx_pcieep_cfg030_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg031 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg031_s {
+                uint32_t pnum:8;
+                uint32_t reserved_22_23:2;
+                uint32_t lbnc:1;
+                uint32_t dllarc:1;
+                uint32_t sderc:1;
+                uint32_t cpm:1;
+                uint32_t l1el:3;
+                uint32_t l0el:3;
+                uint32_t aslpms:2;
+                uint32_t mlw:6;
+                uint32_t mls:4;
+        } s;
+        struct cvmx_pcieep_cfg031_s cn52xx;
+        struct cvmx_pcieep_cfg031_s cn52xxp1;
+        struct cvmx_pcieep_cfg031_s cn56xx;
+        struct cvmx_pcieep_cfg031_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg032 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg032_s {
+                uint32_t reserved_30_31:2;
+                uint32_t dlla:1;
+                uint32_t scc:1;
+                uint32_t lt:1;
+                uint32_t reserved_26_26:1;
+                uint32_t nlw:6;
+                uint32_t ls:4;
+                uint32_t reserved_10_15:6;
+                uint32_t hawd:1;
+                uint32_t ecpm:1;
+                uint32_t es:1;
+                uint32_t ccc:1;
+                uint32_t rl:1;
+                uint32_t ld:1;
+                uint32_t rcb:1;
+                uint32_t reserved_2_2:1;
+                uint32_t aslpc:2;
+        } s;
+        struct cvmx_pcieep_cfg032_s cn52xx;
+        struct cvmx_pcieep_cfg032_s cn52xxp1;
+        struct cvmx_pcieep_cfg032_s cn56xx;
+        struct cvmx_pcieep_cfg032_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg033 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg033_s {
+                uint32_t ps_num:13;
+                uint32_t nccs:1;
+                uint32_t emip:1;
+                uint32_t sp_ls:2;
+                uint32_t sp_lv:8;
+                uint32_t hp_c:1;
+                uint32_t hp_s:1;
+                uint32_t pip:1;
+                uint32_t aip:1;
+                uint32_t mrlsp:1;
+                uint32_t pcp:1;
+                uint32_t abp:1;
+        } s;
+        struct cvmx_pcieep_cfg033_s cn52xx;
+        struct cvmx_pcieep_cfg033_s cn52xxp1;
+        struct cvmx_pcieep_cfg033_s cn56xx;
+        struct cvmx_pcieep_cfg033_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg034 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg034_s {
+                uint32_t reserved_25_31:7;
+                uint32_t dlls_c:1;
+                uint32_t emis:1;
+                uint32_t pds:1;
+                uint32_t mrlss:1;
+                uint32_t ccint_d:1;
+                uint32_t pd_c:1;
+                uint32_t mrls_c:1;
+                uint32_t pf_d:1;
+                uint32_t abp_d:1;
+                uint32_t reserved_13_15:3;
+                uint32_t dlls_en:1;
+                uint32_t emic:1;
+                uint32_t pcc:1;
+                uint32_t pic:2;
+                uint32_t aic:2;
+                uint32_t hpint_en:1;
+                uint32_t ccint_en:1;
+                uint32_t pd_en:1;
+                uint32_t mrls_en:1;
+                uint32_t pf_en:1;
+                uint32_t abp_en:1;
+        } s;
+        struct cvmx_pcieep_cfg034_s cn52xx;
+        struct cvmx_pcieep_cfg034_s cn52xxp1;
+        struct cvmx_pcieep_cfg034_s cn56xx;
+        struct cvmx_pcieep_cfg034_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg037 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg037_s {
+                uint32_t reserved_5_31:27;
+                uint32_t ctds:1;
+                uint32_t ctrs:4;
+        } s;
+        struct cvmx_pcieep_cfg037_s cn52xx;
+        struct cvmx_pcieep_cfg037_s cn52xxp1;
+        struct cvmx_pcieep_cfg037_s cn56xx;
+        struct cvmx_pcieep_cfg037_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg038 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg038_s {
+                uint32_t reserved_5_31:27;
+                uint32_t ctd:1;
+                uint32_t ctv:4;
+        } s;
+        struct cvmx_pcieep_cfg038_s cn52xx;
+        struct cvmx_pcieep_cfg038_s cn52xxp1;
+        struct cvmx_pcieep_cfg038_s cn56xx;
+        struct cvmx_pcieep_cfg038_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg039 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg039_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pcieep_cfg039_s cn52xx;
+        struct cvmx_pcieep_cfg039_s cn52xxp1;
+        struct cvmx_pcieep_cfg039_s cn56xx;
+        struct cvmx_pcieep_cfg039_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg040 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg040_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pcieep_cfg040_s cn52xx;
+        struct cvmx_pcieep_cfg040_s cn52xxp1;
+        struct cvmx_pcieep_cfg040_s cn56xx;
+        struct cvmx_pcieep_cfg040_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg041 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg041_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pcieep_cfg041_s cn52xx;
+        struct cvmx_pcieep_cfg041_s cn52xxp1;
+        struct cvmx_pcieep_cfg041_s cn56xx;
+        struct cvmx_pcieep_cfg041_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg042 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg042_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pcieep_cfg042_s cn52xx;
+        struct cvmx_pcieep_cfg042_s cn52xxp1;
+        struct cvmx_pcieep_cfg042_s cn56xx;
+        struct cvmx_pcieep_cfg042_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg064 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg064_s {
+                uint32_t nco:12;
+                uint32_t cv:4;
+                uint32_t pcieec:16;
+        } s;
+        struct cvmx_pcieep_cfg064_s cn52xx;
+        struct cvmx_pcieep_cfg064_s cn52xxp1;
+        struct cvmx_pcieep_cfg064_s cn56xx;
+        struct cvmx_pcieep_cfg064_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg065 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg065_s {
+                uint32_t reserved_21_31:11;
+                uint32_t ures:1;
+                uint32_t ecrces:1;
+                uint32_t mtlps:1;
+                uint32_t ros:1;
+                uint32_t ucs:1;
+                uint32_t cas:1;
+                uint32_t cts:1;
+                uint32_t fcpes:1;
+                uint32_t ptlps:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdes:1;
+                uint32_t dlpes:1;
+                uint32_t reserved_0_3:4;
+        } s;
+        struct cvmx_pcieep_cfg065_s cn52xx;
+        struct cvmx_pcieep_cfg065_s cn52xxp1;
+        struct cvmx_pcieep_cfg065_s cn56xx;
+        struct cvmx_pcieep_cfg065_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg066 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg066_s {
+                uint32_t reserved_21_31:11;
+                uint32_t urem:1;
+                uint32_t ecrcem:1;
+                uint32_t mtlpm:1;
+                uint32_t rom:1;
+                uint32_t ucm:1;
+                uint32_t cam:1;
+                uint32_t ctm:1;
+                uint32_t fcpem:1;
+                uint32_t ptlpm:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdem:1;
+                uint32_t dlpem:1;
+                uint32_t reserved_0_3:4;
+        } s;
+        struct cvmx_pcieep_cfg066_s cn52xx;
+        struct cvmx_pcieep_cfg066_s cn52xxp1;
+        struct cvmx_pcieep_cfg066_s cn56xx;
+        struct cvmx_pcieep_cfg066_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg067 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg067_s {
+                uint32_t reserved_21_31:11;
+                uint32_t ures:1;
+                uint32_t ecrces:1;
+                uint32_t mtlps:1;
+                uint32_t ros:1;
+                uint32_t ucs:1;
+                uint32_t cas:1;
+                uint32_t cts:1;
+                uint32_t fcpes:1;
+                uint32_t ptlps:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdes:1;
+                uint32_t dlpes:1;
+                uint32_t reserved_0_3:4;
+        } s;
+        struct cvmx_pcieep_cfg067_s cn52xx;
+        struct cvmx_pcieep_cfg067_s cn52xxp1;
+        struct cvmx_pcieep_cfg067_s cn56xx;
+        struct cvmx_pcieep_cfg067_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg068 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg068_s {
+                uint32_t reserved_14_31:18;
+                uint32_t anfes:1;
+                uint32_t rtts:1;
+                uint32_t reserved_9_11:3;
+                uint32_t rnrs:1;
+                uint32_t bdllps:1;
+                uint32_t btlps:1;
+                uint32_t reserved_1_5:5;
+                uint32_t res:1;
+        } s;
+        struct cvmx_pcieep_cfg068_s cn52xx;
+        struct cvmx_pcieep_cfg068_s cn52xxp1;
+        struct cvmx_pcieep_cfg068_s cn56xx;
+        struct cvmx_pcieep_cfg068_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg069 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg069_s {
+                uint32_t reserved_14_31:18;
+                uint32_t anfem:1;
+                uint32_t rttm:1;
+                uint32_t reserved_9_11:3;
+                uint32_t rnrm:1;
+                uint32_t bdllpm:1;
+                uint32_t btlpm:1;
+                uint32_t reserved_1_5:5;
+                uint32_t rem:1;
+        } s;
+        struct cvmx_pcieep_cfg069_s cn52xx;
+        struct cvmx_pcieep_cfg069_s cn52xxp1;
+        struct cvmx_pcieep_cfg069_s cn56xx;
+        struct cvmx_pcieep_cfg069_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg070 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg070_s {
+                uint32_t reserved_9_31:23;
+                uint32_t ce:1;
+                uint32_t cc:1;
+                uint32_t ge:1;
+                uint32_t gc:1;
+                uint32_t fep:5;
+        } s;
+        struct cvmx_pcieep_cfg070_s cn52xx;
+        struct cvmx_pcieep_cfg070_s cn52xxp1;
+        struct cvmx_pcieep_cfg070_s cn56xx;
+        struct cvmx_pcieep_cfg070_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg071 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg071_s {
+                uint32_t dword1:32;
+        } s;
+        struct cvmx_pcieep_cfg071_s cn52xx;
+        struct cvmx_pcieep_cfg071_s cn52xxp1;
+        struct cvmx_pcieep_cfg071_s cn56xx;
+        struct cvmx_pcieep_cfg071_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg072 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg072_s {
+                uint32_t dword2:32;
+        } s;
+        struct cvmx_pcieep_cfg072_s cn52xx;
+        struct cvmx_pcieep_cfg072_s cn52xxp1;
+        struct cvmx_pcieep_cfg072_s cn56xx;
+        struct cvmx_pcieep_cfg072_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg073 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg073_s {
+                uint32_t dword3:32;
+        } s;
+        struct cvmx_pcieep_cfg073_s cn52xx;
+        struct cvmx_pcieep_cfg073_s cn52xxp1;
+        struct cvmx_pcieep_cfg073_s cn56xx;
+        struct cvmx_pcieep_cfg073_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg074 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg074_s {
+                uint32_t dword4:32;
+        } s;
+        struct cvmx_pcieep_cfg074_s cn52xx;
+        struct cvmx_pcieep_cfg074_s cn52xxp1;
+        struct cvmx_pcieep_cfg074_s cn56xx;
+        struct cvmx_pcieep_cfg074_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg448 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg448_s {
+                uint32_t rtl:16;
+                uint32_t rtltl:16;
+        } s;
+        struct cvmx_pcieep_cfg448_s cn52xx;
+        struct cvmx_pcieep_cfg448_s cn52xxp1;
+        struct cvmx_pcieep_cfg448_s cn56xx;
+        struct cvmx_pcieep_cfg448_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg449 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg449_s {
+                uint32_t omr:32;
+        } s;
+        struct cvmx_pcieep_cfg449_s cn52xx;
+        struct cvmx_pcieep_cfg449_s cn52xxp1;
+        struct cvmx_pcieep_cfg449_s cn56xx;
+        struct cvmx_pcieep_cfg449_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg450 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg450_s {
+                uint32_t lpec:8;
+                uint32_t reserved_22_23:2;
+                uint32_t link_state:6;
+                uint32_t force_link:1;
+                uint32_t reserved_8_14:7;
+                uint32_t link_num:8;
+        } s;
+        struct cvmx_pcieep_cfg450_s cn52xx;
+        struct cvmx_pcieep_cfg450_s cn52xxp1;
+        struct cvmx_pcieep_cfg450_s cn56xx;
+        struct cvmx_pcieep_cfg450_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg451 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg451_s {
+                uint32_t reserved_30_31:2;
+                uint32_t l1el:3;
+                uint32_t l0el:3;
+                uint32_t n_fts_cc:8;
+                uint32_t n_fts:8;
+                uint32_t ack_freq:8;
+        } s;
+        struct cvmx_pcieep_cfg451_s cn52xx;
+        struct cvmx_pcieep_cfg451_s cn52xxp1;
+        struct cvmx_pcieep_cfg451_s cn56xx;
+        struct cvmx_pcieep_cfg451_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg452 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg452_s {
+                uint32_t reserved_26_31:6;
+                uint32_t eccrc:1;
+                uint32_t reserved_22_24:3;
+                uint32_t lme:6;
+                uint32_t reserved_8_15:8;
+                uint32_t flm:1;
+                uint32_t reserved_6_6:1;
+                uint32_t dllle:1;
+                uint32_t reserved_4_4:1;
+                uint32_t ra:1;
+                uint32_t le:1;
+                uint32_t sd:1;
+                uint32_t omr:1;
+        } s;
+        struct cvmx_pcieep_cfg452_s cn52xx;
+        struct cvmx_pcieep_cfg452_s cn52xxp1;
+        struct cvmx_pcieep_cfg452_s cn56xx;
+        struct cvmx_pcieep_cfg452_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg453 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg453_s {
+                uint32_t dlld:1;
+                uint32_t reserved_26_30:5;
+                uint32_t ack_nak:1;
+                uint32_t fcd:1;
+                uint32_t ilst:24;
+        } s;
+        struct cvmx_pcieep_cfg453_s cn52xx;
+        struct cvmx_pcieep_cfg453_s cn52xxp1;
+        struct cvmx_pcieep_cfg453_s cn56xx;
+        struct cvmx_pcieep_cfg453_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg454 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg454_s {
+                uint32_t reserved_29_31:3;
+                uint32_t tmfcwt:5;
+                uint32_t tmanlt:5;
+                uint32_t tmrt:5;
+                uint32_t reserved_11_13:3;
+                uint32_t nskps:3;
+                uint32_t reserved_4_7:4;
+                uint32_t ntss:4;
+        } s;
+        struct cvmx_pcieep_cfg454_s cn52xx;
+        struct cvmx_pcieep_cfg454_s cn52xxp1;
+        struct cvmx_pcieep_cfg454_s cn56xx;
+        struct cvmx_pcieep_cfg454_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg455 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg455_s {
+                uint32_t m_cfg0_filt:1;
+                uint32_t m_io_filt:1;
+                uint32_t msg_ctrl:1;
+                uint32_t m_cpl_ecrc_filt:1;
+                uint32_t m_ecrc_filt:1;
+                uint32_t m_cpl_len_err:1;
+                uint32_t m_cpl_attr_err:1;
+                uint32_t m_cpl_tc_err:1;
+                uint32_t m_cpl_fun_err:1;
+                uint32_t m_cpl_rid_err:1;
+                uint32_t m_cpl_tag_err:1;
+                uint32_t m_lk_filt:1;
+                uint32_t m_cfg1_filt:1;
+                uint32_t m_bar_match:1;
+                uint32_t m_pois_filt:1;
+                uint32_t m_fun:1;
+                uint32_t dfcwt:1;
+                uint32_t reserved_11_14:4;
+                uint32_t skpiv:11;
+        } s;
+        struct cvmx_pcieep_cfg455_s cn52xx;
+        struct cvmx_pcieep_cfg455_s cn52xxp1;
+        struct cvmx_pcieep_cfg455_s cn56xx;
+        struct cvmx_pcieep_cfg455_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg456 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg456_s {
+                uint32_t reserved_2_31:30;
+                uint32_t m_vend1_drp:1;
+                uint32_t m_vend0_drp:1;
+        } s;
+        struct cvmx_pcieep_cfg456_s cn52xx;
+        struct cvmx_pcieep_cfg456_s cn52xxp1;
+        struct cvmx_pcieep_cfg456_s cn56xx;
+        struct cvmx_pcieep_cfg456_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg458 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg458_s {
+                uint32_t dbg_info_l32:32;
+        } s;
+        struct cvmx_pcieep_cfg458_s cn52xx;
+        struct cvmx_pcieep_cfg458_s cn52xxp1;
+        struct cvmx_pcieep_cfg458_s cn56xx;
+        struct cvmx_pcieep_cfg458_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg459 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg459_s {
+                uint32_t dbg_info_u32:32;
+        } s;
+        struct cvmx_pcieep_cfg459_s cn52xx;
+        struct cvmx_pcieep_cfg459_s cn52xxp1;
+        struct cvmx_pcieep_cfg459_s cn56xx;
+        struct cvmx_pcieep_cfg459_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg460 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg460_s {
+                uint32_t reserved_20_31:12;
+                uint32_t tphfcc:8;
+                uint32_t tpdfcc:12;
+        } s;
+        struct cvmx_pcieep_cfg460_s cn52xx;
+        struct cvmx_pcieep_cfg460_s cn52xxp1;
+        struct cvmx_pcieep_cfg460_s cn56xx;
+        struct cvmx_pcieep_cfg460_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg461 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg461_s {
+                uint32_t reserved_20_31:12;
+                uint32_t tchfcc:8;
+                uint32_t tcdfcc:12;
+        } s;
+        struct cvmx_pcieep_cfg461_s cn52xx;
+        struct cvmx_pcieep_cfg461_s cn52xxp1;
+        struct cvmx_pcieep_cfg461_s cn56xx;
+        struct cvmx_pcieep_cfg461_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg462 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg462_s {
+                uint32_t reserved_20_31:12;
+                uint32_t tchfcc:8;
+                uint32_t tcdfcc:12;
+        } s;
+        struct cvmx_pcieep_cfg462_s cn52xx;
+        struct cvmx_pcieep_cfg462_s cn52xxp1;
+        struct cvmx_pcieep_cfg462_s cn56xx;
+        struct cvmx_pcieep_cfg462_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg463 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg463_s {
+                uint32_t reserved_3_31:29;
+                uint32_t rqne:1;
+                uint32_t trbne:1;
+                uint32_t rtlpfccnr:1;
+        } s;
+        struct cvmx_pcieep_cfg463_s cn52xx;
+        struct cvmx_pcieep_cfg463_s cn52xxp1;
+        struct cvmx_pcieep_cfg463_s cn56xx;
+        struct cvmx_pcieep_cfg463_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg464 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg464_s {
+                uint32_t wrr_vc3:8;
+                uint32_t wrr_vc2:8;
+                uint32_t wrr_vc1:8;
+                uint32_t wrr_vc0:8;
+        } s;
+        struct cvmx_pcieep_cfg464_s cn52xx;
+        struct cvmx_pcieep_cfg464_s cn52xxp1;
+        struct cvmx_pcieep_cfg464_s cn56xx;
+        struct cvmx_pcieep_cfg464_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg465 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg465_s {
+                uint32_t wrr_vc7:8;
+                uint32_t wrr_vc6:8;
+                uint32_t wrr_vc5:8;
+                uint32_t wrr_vc4:8;
+        } s;
+        struct cvmx_pcieep_cfg465_s cn52xx;
+        struct cvmx_pcieep_cfg465_s cn52xxp1;
+        struct cvmx_pcieep_cfg465_s cn56xx;
+        struct cvmx_pcieep_cfg465_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg466 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg466_s {
+                uint32_t rx_queue_order:1;
+                uint32_t type_ordering:1;
+                uint32_t reserved_24_29:6;
+                uint32_t queue_mode:3;
+                uint32_t reserved_20_20:1;
+                uint32_t header_credits:8;
+                uint32_t data_credits:12;
+        } s;
+        struct cvmx_pcieep_cfg466_s cn52xx;
+        struct cvmx_pcieep_cfg466_s cn52xxp1;
+        struct cvmx_pcieep_cfg466_s cn56xx;
+        struct cvmx_pcieep_cfg466_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg467 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg467_s {
+                uint32_t reserved_24_31:8;
+                uint32_t queue_mode:3;
+                uint32_t reserved_20_20:1;
+                uint32_t header_credits:8;
+                uint32_t data_credits:12;
+        } s;
+        struct cvmx_pcieep_cfg467_s cn52xx;
+        struct cvmx_pcieep_cfg467_s cn52xxp1;
+        struct cvmx_pcieep_cfg467_s cn56xx;
+        struct cvmx_pcieep_cfg467_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg468 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg468_s {
+                uint32_t reserved_24_31:8;
+                uint32_t queue_mode:3;
+                uint32_t reserved_20_20:1;
+                uint32_t header_credits:8;
+                uint32_t data_credits:12;
+        } s;
+        struct cvmx_pcieep_cfg468_s cn52xx;
+        struct cvmx_pcieep_cfg468_s cn52xxp1;
+        struct cvmx_pcieep_cfg468_s cn56xx;
+        struct cvmx_pcieep_cfg468_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg490 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg490_s {
+                uint32_t reserved_26_31:6;
+                uint32_t header_depth:10;
+                uint32_t reserved_14_15:2;
+                uint32_t data_depth:14;
+        } s;
+        struct cvmx_pcieep_cfg490_s cn52xx;
+        struct cvmx_pcieep_cfg490_s cn52xxp1;
+        struct cvmx_pcieep_cfg490_s cn56xx;
+        struct cvmx_pcieep_cfg490_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg491 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg491_s {
+                uint32_t reserved_26_31:6;
+                uint32_t header_depth:10;
+                uint32_t reserved_14_15:2;
+                uint32_t data_depth:14;
+        } s;
+        struct cvmx_pcieep_cfg491_s cn52xx;
+        struct cvmx_pcieep_cfg491_s cn52xxp1;
+        struct cvmx_pcieep_cfg491_s cn56xx;
+        struct cvmx_pcieep_cfg491_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg492 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg492_s {
+                uint32_t reserved_26_31:6;
+                uint32_t header_depth:10;
+                uint32_t reserved_14_15:2;
+                uint32_t data_depth:14;
+        } s;
+        struct cvmx_pcieep_cfg492_s cn52xx;
+        struct cvmx_pcieep_cfg492_s cn52xxp1;
+        struct cvmx_pcieep_cfg492_s cn56xx;
+        struct cvmx_pcieep_cfg492_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg516 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg516_s {
+                uint32_t phy_stat:32;
+        } s;
+        struct cvmx_pcieep_cfg516_s cn52xx;
+        struct cvmx_pcieep_cfg516_s cn52xxp1;
+        struct cvmx_pcieep_cfg516_s cn56xx;
+        struct cvmx_pcieep_cfg516_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg517 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg517_s {
+                uint32_t phy_ctrl:32;
+        } s;
+        struct cvmx_pcieep_cfg517_s cn52xx;
+        struct cvmx_pcieep_cfg517_s cn52xxp1;
+        struct cvmx_pcieep_cfg517_s cn56xx;
+        struct cvmx_pcieep_cfg517_s cn56xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
new file mode 100644
index 000000000000..75574c918942
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -0,0 +1,1397 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PCIERCX_DEFS_H__
+#define __CVMX_PCIERCX_DEFS_H__
+
+#define CVMX_PCIERCX_CFG000(offset) \
+         (0x0000000000000000ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG001(offset) \
+         (0x0000000000000004ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG002(offset) \
+         (0x0000000000000008ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG003(offset) \
+         (0x000000000000000Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG004(offset) \
+         (0x0000000000000010ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG005(offset) \
+         (0x0000000000000014ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG006(offset) \
+         (0x0000000000000018ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG007(offset) \
+         (0x000000000000001Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG008(offset) \
+         (0x0000000000000020ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG009(offset) \
+         (0x0000000000000024ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG010(offset) \
+         (0x0000000000000028ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG011(offset) \
+         (0x000000000000002Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG012(offset) \
+         (0x0000000000000030ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG013(offset) \
+         (0x0000000000000034ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG014(offset) \
+         (0x0000000000000038ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG015(offset) \
+         (0x000000000000003Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG016(offset) \
+         (0x0000000000000040ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG017(offset) \
+         (0x0000000000000044ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG020(offset) \
+         (0x0000000000000050ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG021(offset) \
+         (0x0000000000000054ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG022(offset) \
+         (0x0000000000000058ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG023(offset) \
+         (0x000000000000005Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG028(offset) \
+         (0x0000000000000070ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG029(offset) \
+         (0x0000000000000074ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG030(offset) \
+         (0x0000000000000078ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG031(offset) \
+         (0x000000000000007Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG032(offset) \
+         (0x0000000000000080ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG033(offset) \
+         (0x0000000000000084ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG034(offset) \
+         (0x0000000000000088ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG035(offset) \
+         (0x000000000000008Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG036(offset) \
+         (0x0000000000000090ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG037(offset) \
+         (0x0000000000000094ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG038(offset) \
+         (0x0000000000000098ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG039(offset) \
+         (0x000000000000009Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG040(offset) \
+         (0x00000000000000A0ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG041(offset) \
+         (0x00000000000000A4ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG042(offset) \
+         (0x00000000000000A8ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG064(offset) \
+         (0x0000000000000100ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG065(offset) \
+         (0x0000000000000104ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG066(offset) \
+         (0x0000000000000108ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG067(offset) \
+         (0x000000000000010Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG068(offset) \
+         (0x0000000000000110ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG069(offset) \
+         (0x0000000000000114ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG070(offset) \
+         (0x0000000000000118ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG071(offset) \
+         (0x000000000000011Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG072(offset) \
+         (0x0000000000000120ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG073(offset) \
+         (0x0000000000000124ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG074(offset) \
+         (0x0000000000000128ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG075(offset) \
+         (0x000000000000012Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG076(offset) \
+         (0x0000000000000130ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG077(offset) \
+         (0x0000000000000134ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG448(offset) \
+         (0x0000000000000700ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG449(offset) \
+         (0x0000000000000704ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG450(offset) \
+         (0x0000000000000708ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG451(offset) \
+         (0x000000000000070Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG452(offset) \
+         (0x0000000000000710ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG453(offset) \
+         (0x0000000000000714ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG454(offset) \
+         (0x0000000000000718ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG455(offset) \
+         (0x000000000000071Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG456(offset) \
+         (0x0000000000000720ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG458(offset) \
+         (0x0000000000000728ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG459(offset) \
+         (0x000000000000072Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG460(offset) \
+         (0x0000000000000730ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG461(offset) \
+         (0x0000000000000734ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG462(offset) \
+         (0x0000000000000738ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG463(offset) \
+         (0x000000000000073Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG464(offset) \
+         (0x0000000000000740ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG465(offset) \
+         (0x0000000000000744ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG466(offset) \
+         (0x0000000000000748ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG467(offset) \
+         (0x000000000000074Cull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG468(offset) \
+         (0x0000000000000750ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG490(offset) \
+         (0x00000000000007A8ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG491(offset) \
+         (0x00000000000007ACull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG492(offset) \
+         (0x00000000000007B0ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG516(offset) \
+         (0x0000000000000810ull + (((offset) & 1) * 0))
+#define CVMX_PCIERCX_CFG517(offset) \
+         (0x0000000000000814ull + (((offset) & 1) * 0))
+
+union cvmx_pciercx_cfg000 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg000_s {
+                uint32_t devid:16;
+                uint32_t vendid:16;
+        } s;
+        struct cvmx_pciercx_cfg000_s cn52xx;
+        struct cvmx_pciercx_cfg000_s cn52xxp1;
+        struct cvmx_pciercx_cfg000_s cn56xx;
+        struct cvmx_pciercx_cfg000_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg001 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg001_s {
+                uint32_t dpe:1;
+                uint32_t sse:1;
+                uint32_t rma:1;
+                uint32_t rta:1;
+                uint32_t sta:1;
+                uint32_t devt:2;
+                uint32_t mdpe:1;
+                uint32_t fbb:1;
+                uint32_t reserved_22_22:1;
+                uint32_t m66:1;
+                uint32_t cl:1;
+                uint32_t i_stat:1;
+                uint32_t reserved_11_18:8;
+                uint32_t i_dis:1;
+                uint32_t fbbe:1;
+                uint32_t see:1;
+                uint32_t ids_wcc:1;
+                uint32_t per:1;
+                uint32_t vps:1;
+                uint32_t mwice:1;
+                uint32_t scse:1;
+                uint32_t me:1;
+                uint32_t msae:1;
+                uint32_t isae:1;
+        } s;
+        struct cvmx_pciercx_cfg001_s cn52xx;
+        struct cvmx_pciercx_cfg001_s cn52xxp1;
+        struct cvmx_pciercx_cfg001_s cn56xx;
+        struct cvmx_pciercx_cfg001_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg002 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg002_s {
+                uint32_t bcc:8;
+                uint32_t sc:8;
+                uint32_t pi:8;
+                uint32_t rid:8;
+        } s;
+        struct cvmx_pciercx_cfg002_s cn52xx;
+        struct cvmx_pciercx_cfg002_s cn52xxp1;
+        struct cvmx_pciercx_cfg002_s cn56xx;
+        struct cvmx_pciercx_cfg002_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg003 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg003_s {
+                uint32_t bist:8;
+                uint32_t mfd:1;
+                uint32_t chf:7;
+                uint32_t lt:8;
+                uint32_t cls:8;
+        } s;
+        struct cvmx_pciercx_cfg003_s cn52xx;
+        struct cvmx_pciercx_cfg003_s cn52xxp1;
+        struct cvmx_pciercx_cfg003_s cn56xx;
+        struct cvmx_pciercx_cfg003_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg004 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg004_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pciercx_cfg004_s cn52xx;
+        struct cvmx_pciercx_cfg004_s cn52xxp1;
+        struct cvmx_pciercx_cfg004_s cn56xx;
+        struct cvmx_pciercx_cfg004_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg005 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg005_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pciercx_cfg005_s cn52xx;
+        struct cvmx_pciercx_cfg005_s cn52xxp1;
+        struct cvmx_pciercx_cfg005_s cn56xx;
+        struct cvmx_pciercx_cfg005_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg006 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg006_s {
+                uint32_t slt:8;
+                uint32_t subbnum:8;
+                uint32_t sbnum:8;
+                uint32_t pbnum:8;
+        } s;
+        struct cvmx_pciercx_cfg006_s cn52xx;
+        struct cvmx_pciercx_cfg006_s cn52xxp1;
+        struct cvmx_pciercx_cfg006_s cn56xx;
+        struct cvmx_pciercx_cfg006_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg007 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg007_s {
+                uint32_t dpe:1;
+                uint32_t sse:1;
+                uint32_t rma:1;
+                uint32_t rta:1;
+                uint32_t sta:1;
+                uint32_t devt:2;
+                uint32_t mdpe:1;
+                uint32_t fbb:1;
+                uint32_t reserved_22_22:1;
+                uint32_t m66:1;
+                uint32_t reserved_16_20:5;
+                uint32_t lio_limi:4;
+                uint32_t reserved_9_11:3;
+                uint32_t io32b:1;
+                uint32_t lio_base:4;
+                uint32_t reserved_1_3:3;
+                uint32_t io32a:1;
+        } s;
+        struct cvmx_pciercx_cfg007_s cn52xx;
+        struct cvmx_pciercx_cfg007_s cn52xxp1;
+        struct cvmx_pciercx_cfg007_s cn56xx;
+        struct cvmx_pciercx_cfg007_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg008 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg008_s {
+                uint32_t ml_addr:12;
+                uint32_t reserved_16_19:4;
+                uint32_t mb_addr:12;
+                uint32_t reserved_0_3:4;
+        } s;
+        struct cvmx_pciercx_cfg008_s cn52xx;
+        struct cvmx_pciercx_cfg008_s cn52xxp1;
+        struct cvmx_pciercx_cfg008_s cn56xx;
+        struct cvmx_pciercx_cfg008_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg009 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg009_s {
+                uint32_t lmem_limit:12;
+                uint32_t reserved_17_19:3;
+                uint32_t mem64b:1;
+                uint32_t lmem_base:12;
+                uint32_t reserved_1_3:3;
+                uint32_t mem64a:1;
+        } s;
+        struct cvmx_pciercx_cfg009_s cn52xx;
+        struct cvmx_pciercx_cfg009_s cn52xxp1;
+        struct cvmx_pciercx_cfg009_s cn56xx;
+        struct cvmx_pciercx_cfg009_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg010 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg010_s {
+                uint32_t umem_base:32;
+        } s;
+        struct cvmx_pciercx_cfg010_s cn52xx;
+        struct cvmx_pciercx_cfg010_s cn52xxp1;
+        struct cvmx_pciercx_cfg010_s cn56xx;
+        struct cvmx_pciercx_cfg010_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg011 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg011_s {
+                uint32_t umem_limit:32;
+        } s;
+        struct cvmx_pciercx_cfg011_s cn52xx;
+        struct cvmx_pciercx_cfg011_s cn52xxp1;
+        struct cvmx_pciercx_cfg011_s cn56xx;
+        struct cvmx_pciercx_cfg011_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg012 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg012_s {
+                uint32_t uio_limit:16;
+                uint32_t uio_base:16;
+        } s;
+        struct cvmx_pciercx_cfg012_s cn52xx;
+        struct cvmx_pciercx_cfg012_s cn52xxp1;
+        struct cvmx_pciercx_cfg012_s cn56xx;
+        struct cvmx_pciercx_cfg012_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg013 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg013_s {
+                uint32_t reserved_8_31:24;
+                uint32_t cp:8;
+        } s;
+        struct cvmx_pciercx_cfg013_s cn52xx;
+        struct cvmx_pciercx_cfg013_s cn52xxp1;
+        struct cvmx_pciercx_cfg013_s cn56xx;
+        struct cvmx_pciercx_cfg013_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg014 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg014_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pciercx_cfg014_s cn52xx;
+        struct cvmx_pciercx_cfg014_s cn52xxp1;
+        struct cvmx_pciercx_cfg014_s cn56xx;
+        struct cvmx_pciercx_cfg014_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg015 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg015_s {
+                uint32_t reserved_28_31:4;
+                uint32_t dtsees:1;
+                uint32_t dts:1;
+                uint32_t sdt:1;
+                uint32_t pdt:1;
+                uint32_t fbbe:1;
+                uint32_t sbrst:1;
+                uint32_t mam:1;
+                uint32_t vga16d:1;
+                uint32_t vgae:1;
+                uint32_t isae:1;
+                uint32_t see:1;
+                uint32_t pere:1;
+                uint32_t inta:8;
+                uint32_t il:8;
+        } s;
+        struct cvmx_pciercx_cfg015_s cn52xx;
+        struct cvmx_pciercx_cfg015_s cn52xxp1;
+        struct cvmx_pciercx_cfg015_s cn56xx;
+        struct cvmx_pciercx_cfg015_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg016 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg016_s {
+                uint32_t pmes:5;
+                uint32_t d2s:1;
+                uint32_t d1s:1;
+                uint32_t auxc:3;
+                uint32_t dsi:1;
+                uint32_t reserved_20_20:1;
+                uint32_t pme_clock:1;
+                uint32_t pmsv:3;
+                uint32_t ncp:8;
+                uint32_t pmcid:8;
+        } s;
+        struct cvmx_pciercx_cfg016_s cn52xx;
+        struct cvmx_pciercx_cfg016_s cn52xxp1;
+        struct cvmx_pciercx_cfg016_s cn56xx;
+        struct cvmx_pciercx_cfg016_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg017 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg017_s {
+                uint32_t pmdia:8;
+                uint32_t bpccee:1;
+                uint32_t bd3h:1;
+                uint32_t reserved_16_21:6;
+                uint32_t pmess:1;
+                uint32_t pmedsia:2;
+                uint32_t pmds:4;
+                uint32_t pmeens:1;
+                uint32_t reserved_4_7:4;
+                uint32_t nsr:1;
+                uint32_t reserved_2_2:1;
+                uint32_t ps:2;
+        } s;
+        struct cvmx_pciercx_cfg017_s cn52xx;
+        struct cvmx_pciercx_cfg017_s cn52xxp1;
+        struct cvmx_pciercx_cfg017_s cn56xx;
+        struct cvmx_pciercx_cfg017_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg020 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg020_s {
+                uint32_t reserved_24_31:8;
+                uint32_t m64:1;
+                uint32_t mme:3;
+                uint32_t mmc:3;
+                uint32_t msien:1;
+                uint32_t ncp:8;
+                uint32_t msicid:8;
+        } s;
+        struct cvmx_pciercx_cfg020_s cn52xx;
+        struct cvmx_pciercx_cfg020_s cn52xxp1;
+        struct cvmx_pciercx_cfg020_s cn56xx;
+        struct cvmx_pciercx_cfg020_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg021 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg021_s {
+                uint32_t lmsi:30;
+                uint32_t reserved_0_1:2;
+        } s;
+        struct cvmx_pciercx_cfg021_s cn52xx;
+        struct cvmx_pciercx_cfg021_s cn52xxp1;
+        struct cvmx_pciercx_cfg021_s cn56xx;
+        struct cvmx_pciercx_cfg021_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg022 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg022_s {
+                uint32_t umsi:32;
+        } s;
+        struct cvmx_pciercx_cfg022_s cn52xx;
+        struct cvmx_pciercx_cfg022_s cn52xxp1;
+        struct cvmx_pciercx_cfg022_s cn56xx;
+        struct cvmx_pciercx_cfg022_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg023 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg023_s {
+                uint32_t reserved_16_31:16;
+                uint32_t msimd:16;
+        } s;
+        struct cvmx_pciercx_cfg023_s cn52xx;
+        struct cvmx_pciercx_cfg023_s cn52xxp1;
+        struct cvmx_pciercx_cfg023_s cn56xx;
+        struct cvmx_pciercx_cfg023_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg028 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg028_s {
+                uint32_t reserved_30_31:2;
+                uint32_t imn:5;
+                uint32_t si:1;
+                uint32_t dpt:4;
+                uint32_t pciecv:4;
+                uint32_t ncp:8;
+                uint32_t pcieid:8;
+        } s;
+        struct cvmx_pciercx_cfg028_s cn52xx;
+        struct cvmx_pciercx_cfg028_s cn52xxp1;
+        struct cvmx_pciercx_cfg028_s cn56xx;
+        struct cvmx_pciercx_cfg028_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg029 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg029_s {
+                uint32_t reserved_28_31:4;
+                uint32_t cspls:2;
+                uint32_t csplv:8;
+                uint32_t reserved_16_17:2;
+                uint32_t rber:1;
+                uint32_t reserved_12_14:3;
+                uint32_t el1al:3;
+                uint32_t el0al:3;
+                uint32_t etfs:1;
+                uint32_t pfs:2;
+                uint32_t mpss:3;
+        } s;
+        struct cvmx_pciercx_cfg029_s cn52xx;
+        struct cvmx_pciercx_cfg029_s cn52xxp1;
+        struct cvmx_pciercx_cfg029_s cn56xx;
+        struct cvmx_pciercx_cfg029_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg030 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg030_s {
+                uint32_t reserved_22_31:10;
+                uint32_t tp:1;
+                uint32_t ap_d:1;
+                uint32_t ur_d:1;
+                uint32_t fe_d:1;
+                uint32_t nfe_d:1;
+                uint32_t ce_d:1;
+                uint32_t reserved_15_15:1;
+                uint32_t mrrs:3;
+                uint32_t ns_en:1;
+                uint32_t ap_en:1;
+                uint32_t pf_en:1;
+                uint32_t etf_en:1;
+                uint32_t mps:3;
+                uint32_t ro_en:1;
+                uint32_t ur_en:1;
+                uint32_t fe_en:1;
+                uint32_t nfe_en:1;
+                uint32_t ce_en:1;
+        } s;
+        struct cvmx_pciercx_cfg030_s cn52xx;
+        struct cvmx_pciercx_cfg030_s cn52xxp1;
+        struct cvmx_pciercx_cfg030_s cn56xx;
+        struct cvmx_pciercx_cfg030_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg031 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg031_s {
+                uint32_t pnum:8;
+                uint32_t reserved_22_23:2;
+                uint32_t lbnc:1;
+                uint32_t dllarc:1;
+                uint32_t sderc:1;
+                uint32_t cpm:1;
+                uint32_t l1el:3;
+                uint32_t l0el:3;
+                uint32_t aslpms:2;
+                uint32_t mlw:6;
+                uint32_t mls:4;
+        } s;
+        struct cvmx_pciercx_cfg031_s cn52xx;
+        struct cvmx_pciercx_cfg031_s cn52xxp1;
+        struct cvmx_pciercx_cfg031_s cn56xx;
+        struct cvmx_pciercx_cfg031_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg032 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg032_s {
+                uint32_t lab:1;
+                uint32_t lbm:1;
+                uint32_t dlla:1;
+                uint32_t scc:1;
+                uint32_t lt:1;
+                uint32_t reserved_26_26:1;
+                uint32_t nlw:6;
+                uint32_t ls:4;
+                uint32_t reserved_12_15:4;
+                uint32_t lab_int_enb:1;
+                uint32_t lbm_int_enb:1;
+                uint32_t hawd:1;
+                uint32_t ecpm:1;
+                uint32_t es:1;
+                uint32_t ccc:1;
+                uint32_t rl:1;
+                uint32_t ld:1;
+                uint32_t rcb:1;
+                uint32_t reserved_2_2:1;
+                uint32_t aslpc:2;
+        } s;
+        struct cvmx_pciercx_cfg032_s cn52xx;
+        struct cvmx_pciercx_cfg032_s cn52xxp1;
+        struct cvmx_pciercx_cfg032_s cn56xx;
+        struct cvmx_pciercx_cfg032_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg033 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg033_s {
+                uint32_t ps_num:13;
+                uint32_t nccs:1;
+                uint32_t emip:1;
+                uint32_t sp_ls:2;
+                uint32_t sp_lv:8;
+                uint32_t hp_c:1;
+                uint32_t hp_s:1;
+                uint32_t pip:1;
+                uint32_t aip:1;
+                uint32_t mrlsp:1;
+                uint32_t pcp:1;
+                uint32_t abp:1;
+        } s;
+        struct cvmx_pciercx_cfg033_s cn52xx;
+        struct cvmx_pciercx_cfg033_s cn52xxp1;
+        struct cvmx_pciercx_cfg033_s cn56xx;
+        struct cvmx_pciercx_cfg033_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg034 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg034_s {
+                uint32_t reserved_25_31:7;
+                uint32_t dlls_c:1;
+                uint32_t emis:1;
+                uint32_t pds:1;
+                uint32_t mrlss:1;
+                uint32_t ccint_d:1;
+                uint32_t pd_c:1;
+                uint32_t mrls_c:1;
+                uint32_t pf_d:1;
+                uint32_t abp_d:1;
+                uint32_t reserved_13_15:3;
+                uint32_t dlls_en:1;
+                uint32_t emic:1;
+                uint32_t pcc:1;
+                uint32_t pic:2;
+                uint32_t aic:2;
+                uint32_t hpint_en:1;
+                uint32_t ccint_en:1;
+                uint32_t pd_en:1;
+                uint32_t mrls_en:1;
+                uint32_t pf_en:1;
+                uint32_t abp_en:1;
+        } s;
+        struct cvmx_pciercx_cfg034_s cn52xx;
+        struct cvmx_pciercx_cfg034_s cn52xxp1;
+        struct cvmx_pciercx_cfg034_s cn56xx;
+        struct cvmx_pciercx_cfg034_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg035 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg035_s {
+                uint32_t reserved_17_31:15;
+                uint32_t crssv:1;
+                uint32_t reserved_5_15:11;
+                uint32_t crssve:1;
+                uint32_t pmeie:1;
+                uint32_t sefee:1;
+                uint32_t senfee:1;
+                uint32_t secee:1;
+        } s;
+        struct cvmx_pciercx_cfg035_s cn52xx;
+        struct cvmx_pciercx_cfg035_s cn52xxp1;
+        struct cvmx_pciercx_cfg035_s cn56xx;
+        struct cvmx_pciercx_cfg035_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg036 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg036_s {
+                uint32_t reserved_18_31:14;
+                uint32_t pme_pend:1;
+                uint32_t pme_stat:1;
+                uint32_t pme_rid:16;
+        } s;
+        struct cvmx_pciercx_cfg036_s cn52xx;
+        struct cvmx_pciercx_cfg036_s cn52xxp1;
+        struct cvmx_pciercx_cfg036_s cn56xx;
+        struct cvmx_pciercx_cfg036_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg037 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg037_s {
+                uint32_t reserved_5_31:27;
+                uint32_t ctds:1;
+                uint32_t ctrs:4;
+        } s;
+        struct cvmx_pciercx_cfg037_s cn52xx;
+        struct cvmx_pciercx_cfg037_s cn52xxp1;
+        struct cvmx_pciercx_cfg037_s cn56xx;
+        struct cvmx_pciercx_cfg037_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg038 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg038_s {
+                uint32_t reserved_5_31:27;
+                uint32_t ctd:1;
+                uint32_t ctv:4;
+        } s;
+        struct cvmx_pciercx_cfg038_s cn52xx;
+        struct cvmx_pciercx_cfg038_s cn52xxp1;
+        struct cvmx_pciercx_cfg038_s cn56xx;
+        struct cvmx_pciercx_cfg038_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg039 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg039_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pciercx_cfg039_s cn52xx;
+        struct cvmx_pciercx_cfg039_s cn52xxp1;
+        struct cvmx_pciercx_cfg039_s cn56xx;
+        struct cvmx_pciercx_cfg039_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg040 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg040_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pciercx_cfg040_s cn52xx;
+        struct cvmx_pciercx_cfg040_s cn52xxp1;
+        struct cvmx_pciercx_cfg040_s cn56xx;
+        struct cvmx_pciercx_cfg040_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg041 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg041_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pciercx_cfg041_s cn52xx;
+        struct cvmx_pciercx_cfg041_s cn52xxp1;
+        struct cvmx_pciercx_cfg041_s cn56xx;
+        struct cvmx_pciercx_cfg041_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg042 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg042_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pciercx_cfg042_s cn52xx;
+        struct cvmx_pciercx_cfg042_s cn52xxp1;
+        struct cvmx_pciercx_cfg042_s cn56xx;
+        struct cvmx_pciercx_cfg042_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg064 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg064_s {
+                uint32_t nco:12;
+                uint32_t cv:4;
+                uint32_t pcieec:16;
+        } s;
+        struct cvmx_pciercx_cfg064_s cn52xx;
+        struct cvmx_pciercx_cfg064_s cn52xxp1;
+        struct cvmx_pciercx_cfg064_s cn56xx;
+        struct cvmx_pciercx_cfg064_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg065 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg065_s {
+                uint32_t reserved_21_31:11;
+                uint32_t ures:1;
+                uint32_t ecrces:1;
+                uint32_t mtlps:1;
+                uint32_t ros:1;
+                uint32_t ucs:1;
+                uint32_t cas:1;
+                uint32_t cts:1;
+                uint32_t fcpes:1;
+                uint32_t ptlps:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdes:1;
+                uint32_t dlpes:1;
+                uint32_t reserved_0_3:4;
+        } s;
+        struct cvmx_pciercx_cfg065_s cn52xx;
+        struct cvmx_pciercx_cfg065_s cn52xxp1;
+        struct cvmx_pciercx_cfg065_s cn56xx;
+        struct cvmx_pciercx_cfg065_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg066 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg066_s {
+                uint32_t reserved_21_31:11;
+                uint32_t urem:1;
+                uint32_t ecrcem:1;
+                uint32_t mtlpm:1;
+                uint32_t rom:1;
+                uint32_t ucm:1;
+                uint32_t cam:1;
+                uint32_t ctm:1;
+                uint32_t fcpem:1;
+                uint32_t ptlpm:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdem:1;
+                uint32_t dlpem:1;
+                uint32_t reserved_0_3:4;
+        } s;
+        struct cvmx_pciercx_cfg066_s cn52xx;
+        struct cvmx_pciercx_cfg066_s cn52xxp1;
+        struct cvmx_pciercx_cfg066_s cn56xx;
+        struct cvmx_pciercx_cfg066_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg067 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg067_s {
+                uint32_t reserved_21_31:11;
+                uint32_t ures:1;
+                uint32_t ecrces:1;
+                uint32_t mtlps:1;
+                uint32_t ros:1;
+                uint32_t ucs:1;
+                uint32_t cas:1;
+                uint32_t cts:1;
+                uint32_t fcpes:1;
+                uint32_t ptlps:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdes:1;
+                uint32_t dlpes:1;
+                uint32_t reserved_0_3:4;
+        } s;
+        struct cvmx_pciercx_cfg067_s cn52xx;
+        struct cvmx_pciercx_cfg067_s cn52xxp1;
+        struct cvmx_pciercx_cfg067_s cn56xx;
+        struct cvmx_pciercx_cfg067_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg068 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg068_s {
+                uint32_t reserved_14_31:18;
+                uint32_t anfes:1;
+                uint32_t rtts:1;
+                uint32_t reserved_9_11:3;
+                uint32_t rnrs:1;
+                uint32_t bdllps:1;
+                uint32_t btlps:1;
+                uint32_t reserved_1_5:5;
+                uint32_t res:1;
+        } s;
+        struct cvmx_pciercx_cfg068_s cn52xx;
+        struct cvmx_pciercx_cfg068_s cn52xxp1;
+        struct cvmx_pciercx_cfg068_s cn56xx;
+        struct cvmx_pciercx_cfg068_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg069 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg069_s {
+                uint32_t reserved_14_31:18;
+                uint32_t anfem:1;
+                uint32_t rttm:1;
+                uint32_t reserved_9_11:3;
+                uint32_t rnrm:1;
+                uint32_t bdllpm:1;
+                uint32_t btlpm:1;
+                uint32_t reserved_1_5:5;
+                uint32_t rem:1;
+        } s;
+        struct cvmx_pciercx_cfg069_s cn52xx;
+        struct cvmx_pciercx_cfg069_s cn52xxp1;
+        struct cvmx_pciercx_cfg069_s cn56xx;
+        struct cvmx_pciercx_cfg069_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg070 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg070_s {
+                uint32_t reserved_9_31:23;
+                uint32_t ce:1;
+                uint32_t cc:1;
+                uint32_t ge:1;
+                uint32_t gc:1;
+                uint32_t fep:5;
+        } s;
+        struct cvmx_pciercx_cfg070_s cn52xx;
+        struct cvmx_pciercx_cfg070_s cn52xxp1;
+        struct cvmx_pciercx_cfg070_s cn56xx;
+        struct cvmx_pciercx_cfg070_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg071 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg071_s {
+                uint32_t dword1:32;
+        } s;
+        struct cvmx_pciercx_cfg071_s cn52xx;
+        struct cvmx_pciercx_cfg071_s cn52xxp1;
+        struct cvmx_pciercx_cfg071_s cn56xx;
+        struct cvmx_pciercx_cfg071_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg072 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg072_s {
+                uint32_t dword2:32;
+        } s;
+        struct cvmx_pciercx_cfg072_s cn52xx;
+        struct cvmx_pciercx_cfg072_s cn52xxp1;
+        struct cvmx_pciercx_cfg072_s cn56xx;
+        struct cvmx_pciercx_cfg072_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg073 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg073_s {
+                uint32_t dword3:32;
+        } s;
+        struct cvmx_pciercx_cfg073_s cn52xx;
+        struct cvmx_pciercx_cfg073_s cn52xxp1;
+        struct cvmx_pciercx_cfg073_s cn56xx;
+        struct cvmx_pciercx_cfg073_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg074 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg074_s {
+                uint32_t dword4:32;
+        } s;
+        struct cvmx_pciercx_cfg074_s cn52xx;
+        struct cvmx_pciercx_cfg074_s cn52xxp1;
+        struct cvmx_pciercx_cfg074_s cn56xx;
+        struct cvmx_pciercx_cfg074_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg075 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg075_s {
+                uint32_t reserved_3_31:29;
+                uint32_t fere:1;
+                uint32_t nfere:1;
+                uint32_t cere:1;
+        } s;
+        struct cvmx_pciercx_cfg075_s cn52xx;
+        struct cvmx_pciercx_cfg075_s cn52xxp1;
+        struct cvmx_pciercx_cfg075_s cn56xx;
+        struct cvmx_pciercx_cfg075_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg076 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg076_s {
+                uint32_t aeimn:5;
+                uint32_t reserved_7_26:20;
+                uint32_t femr:1;
+                uint32_t nfemr:1;
+                uint32_t fuf:1;
+                uint32_t multi_efnfr:1;
+                uint32_t efnfr:1;
+                uint32_t multi_ecr:1;
+                uint32_t ecr:1;
+        } s;
+        struct cvmx_pciercx_cfg076_s cn52xx;
+        struct cvmx_pciercx_cfg076_s cn52xxp1;
+        struct cvmx_pciercx_cfg076_s cn56xx;
+        struct cvmx_pciercx_cfg076_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg077 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg077_s {
+                uint32_t efnfsi:16;
+                uint32_t ecsi:16;
+        } s;
+        struct cvmx_pciercx_cfg077_s cn52xx;
+        struct cvmx_pciercx_cfg077_s cn52xxp1;
+        struct cvmx_pciercx_cfg077_s cn56xx;
+        struct cvmx_pciercx_cfg077_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg448 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg448_s {
+                uint32_t rtl:16;
+                uint32_t rtltl:16;
+        } s;
+        struct cvmx_pciercx_cfg448_s cn52xx;
+        struct cvmx_pciercx_cfg448_s cn52xxp1;
+        struct cvmx_pciercx_cfg448_s cn56xx;
+        struct cvmx_pciercx_cfg448_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg449 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg449_s {
+                uint32_t omr:32;
+        } s;
+        struct cvmx_pciercx_cfg449_s cn52xx;
+        struct cvmx_pciercx_cfg449_s cn52xxp1;
+        struct cvmx_pciercx_cfg449_s cn56xx;
+        struct cvmx_pciercx_cfg449_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg450 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg450_s {
+                uint32_t lpec:8;
+                uint32_t reserved_22_23:2;
+                uint32_t link_state:6;
+                uint32_t force_link:1;
+                uint32_t reserved_8_14:7;
+                uint32_t link_num:8;
+        } s;
+        struct cvmx_pciercx_cfg450_s cn52xx;
+        struct cvmx_pciercx_cfg450_s cn52xxp1;
+        struct cvmx_pciercx_cfg450_s cn56xx;
+        struct cvmx_pciercx_cfg450_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg451 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg451_s {
+                uint32_t reserved_30_31:2;
+                uint32_t l1el:3;
+                uint32_t l0el:3;
+                uint32_t n_fts_cc:8;
+                uint32_t n_fts:8;
+                uint32_t ack_freq:8;
+        } s;
+        struct cvmx_pciercx_cfg451_s cn52xx;
+        struct cvmx_pciercx_cfg451_s cn52xxp1;
+        struct cvmx_pciercx_cfg451_s cn56xx;
+        struct cvmx_pciercx_cfg451_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg452 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg452_s {
+                uint32_t reserved_26_31:6;
+                uint32_t eccrc:1;
+                uint32_t reserved_22_24:3;
+                uint32_t lme:6;
+                uint32_t reserved_8_15:8;
+                uint32_t flm:1;
+                uint32_t reserved_6_6:1;
+                uint32_t dllle:1;
+                uint32_t reserved_4_4:1;
+                uint32_t ra:1;
+                uint32_t le:1;
+                uint32_t sd:1;
+                uint32_t omr:1;
+        } s;
+        struct cvmx_pciercx_cfg452_s cn52xx;
+        struct cvmx_pciercx_cfg452_s cn52xxp1;
+        struct cvmx_pciercx_cfg452_s cn56xx;
+        struct cvmx_pciercx_cfg452_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg453 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg453_s {
+                uint32_t dlld:1;
+                uint32_t reserved_26_30:5;
+                uint32_t ack_nak:1;
+                uint32_t fcd:1;
+                uint32_t ilst:24;
+        } s;
+        struct cvmx_pciercx_cfg453_s cn52xx;
+        struct cvmx_pciercx_cfg453_s cn52xxp1;
+        struct cvmx_pciercx_cfg453_s cn56xx;
+        struct cvmx_pciercx_cfg453_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg454 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg454_s {
+                uint32_t reserved_29_31:3;
+                uint32_t tmfcwt:5;
+                uint32_t tmanlt:5;
+                uint32_t tmrt:5;
+                uint32_t reserved_11_13:3;
+                uint32_t nskps:3;
+                uint32_t reserved_4_7:4;
+                uint32_t ntss:4;
+        } s;
+        struct cvmx_pciercx_cfg454_s cn52xx;
+        struct cvmx_pciercx_cfg454_s cn52xxp1;
+        struct cvmx_pciercx_cfg454_s cn56xx;
+        struct cvmx_pciercx_cfg454_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg455 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg455_s {
+                uint32_t m_cfg0_filt:1;
+                uint32_t m_io_filt:1;
+                uint32_t msg_ctrl:1;
+                uint32_t m_cpl_ecrc_filt:1;
+                uint32_t m_ecrc_filt:1;
+                uint32_t m_cpl_len_err:1;
+                uint32_t m_cpl_attr_err:1;
+                uint32_t m_cpl_tc_err:1;
+                uint32_t m_cpl_fun_err:1;
+                uint32_t m_cpl_rid_err:1;
+                uint32_t m_cpl_tag_err:1;
+                uint32_t m_lk_filt:1;
+                uint32_t m_cfg1_filt:1;
+                uint32_t m_bar_match:1;
+                uint32_t m_pois_filt:1;
+                uint32_t m_fun:1;
+                uint32_t dfcwt:1;
+                uint32_t reserved_11_14:4;
+                uint32_t skpiv:11;
+        } s;
+        struct cvmx_pciercx_cfg455_s cn52xx;
+        struct cvmx_pciercx_cfg455_s cn52xxp1;
+        struct cvmx_pciercx_cfg455_s cn56xx;
+        struct cvmx_pciercx_cfg455_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg456 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg456_s {
+                uint32_t reserved_2_31:30;
+                uint32_t m_vend1_drp:1;
+                uint32_t m_vend0_drp:1;
+        } s;
+        struct cvmx_pciercx_cfg456_s cn52xx;
+        struct cvmx_pciercx_cfg456_s cn52xxp1;
+        struct cvmx_pciercx_cfg456_s cn56xx;
+        struct cvmx_pciercx_cfg456_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg458 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg458_s {
+                uint32_t dbg_info_l32:32;
+        } s;
+        struct cvmx_pciercx_cfg458_s cn52xx;
+        struct cvmx_pciercx_cfg458_s cn52xxp1;
+        struct cvmx_pciercx_cfg458_s cn56xx;
+        struct cvmx_pciercx_cfg458_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg459 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg459_s {
+                uint32_t dbg_info_u32:32;
+        } s;
+        struct cvmx_pciercx_cfg459_s cn52xx;
+        struct cvmx_pciercx_cfg459_s cn52xxp1;
+        struct cvmx_pciercx_cfg459_s cn56xx;
+        struct cvmx_pciercx_cfg459_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg460 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg460_s {
+                uint32_t reserved_20_31:12;
+                uint32_t tphfcc:8;
+                uint32_t tpdfcc:12;
+        } s;
+        struct cvmx_pciercx_cfg460_s cn52xx;
+        struct cvmx_pciercx_cfg460_s cn52xxp1;
+        struct cvmx_pciercx_cfg460_s cn56xx;
+        struct cvmx_pciercx_cfg460_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg461 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg461_s {
+                uint32_t reserved_20_31:12;
+                uint32_t tchfcc:8;
+                uint32_t tcdfcc:12;
+        } s;
+        struct cvmx_pciercx_cfg461_s cn52xx;
+        struct cvmx_pciercx_cfg461_s cn52xxp1;
+        struct cvmx_pciercx_cfg461_s cn56xx;
+        struct cvmx_pciercx_cfg461_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg462 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg462_s {
+                uint32_t reserved_20_31:12;
+                uint32_t tchfcc:8;
+                uint32_t tcdfcc:12;
+        } s;
+        struct cvmx_pciercx_cfg462_s cn52xx;
+        struct cvmx_pciercx_cfg462_s cn52xxp1;
+        struct cvmx_pciercx_cfg462_s cn56xx;
+        struct cvmx_pciercx_cfg462_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg463 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg463_s {
+                uint32_t reserved_3_31:29;
+                uint32_t rqne:1;
+                uint32_t trbne:1;
+                uint32_t rtlpfccnr:1;
+        } s;
+        struct cvmx_pciercx_cfg463_s cn52xx;
+        struct cvmx_pciercx_cfg463_s cn52xxp1;
+        struct cvmx_pciercx_cfg463_s cn56xx;
+        struct cvmx_pciercx_cfg463_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg464 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg464_s {
+                uint32_t wrr_vc3:8;
+                uint32_t wrr_vc2:8;
+                uint32_t wrr_vc1:8;
+                uint32_t wrr_vc0:8;
+        } s;
+        struct cvmx_pciercx_cfg464_s cn52xx;
+        struct cvmx_pciercx_cfg464_s cn52xxp1;
+        struct cvmx_pciercx_cfg464_s cn56xx;
+        struct cvmx_pciercx_cfg464_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg465 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg465_s {
+                uint32_t wrr_vc7:8;
+                uint32_t wrr_vc6:8;
+                uint32_t wrr_vc5:8;
+                uint32_t wrr_vc4:8;
+        } s;
+        struct cvmx_pciercx_cfg465_s cn52xx;
+        struct cvmx_pciercx_cfg465_s cn52xxp1;
+        struct cvmx_pciercx_cfg465_s cn56xx;
+        struct cvmx_pciercx_cfg465_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg466 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg466_s {
+                uint32_t rx_queue_order:1;
+                uint32_t type_ordering:1;
+                uint32_t reserved_24_29:6;
+                uint32_t queue_mode:3;
+                uint32_t reserved_20_20:1;
+                uint32_t header_credits:8;
+                uint32_t data_credits:12;
+        } s;
+        struct cvmx_pciercx_cfg466_s cn52xx;
+        struct cvmx_pciercx_cfg466_s cn52xxp1;
+        struct cvmx_pciercx_cfg466_s cn56xx;
+        struct cvmx_pciercx_cfg466_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg467 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg467_s {
+                uint32_t reserved_24_31:8;
+                uint32_t queue_mode:3;
+                uint32_t reserved_20_20:1;
+                uint32_t header_credits:8;
+                uint32_t data_credits:12;
+        } s;
+        struct cvmx_pciercx_cfg467_s cn52xx;
+        struct cvmx_pciercx_cfg467_s cn52xxp1;
+        struct cvmx_pciercx_cfg467_s cn56xx;
+        struct cvmx_pciercx_cfg467_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg468 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg468_s {
+                uint32_t reserved_24_31:8;
+                uint32_t queue_mode:3;
+                uint32_t reserved_20_20:1;
+                uint32_t header_credits:8;
+                uint32_t data_credits:12;
+        } s;
+        struct cvmx_pciercx_cfg468_s cn52xx;
+        struct cvmx_pciercx_cfg468_s cn52xxp1;
+        struct cvmx_pciercx_cfg468_s cn56xx;
+        struct cvmx_pciercx_cfg468_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg490 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg490_s {
+                uint32_t reserved_26_31:6;
+                uint32_t header_depth:10;
+                uint32_t reserved_14_15:2;
+                uint32_t data_depth:14;
+        } s;
+        struct cvmx_pciercx_cfg490_s cn52xx;
+        struct cvmx_pciercx_cfg490_s cn52xxp1;
+        struct cvmx_pciercx_cfg490_s cn56xx;
+        struct cvmx_pciercx_cfg490_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg491 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg491_s {
+                uint32_t reserved_26_31:6;
+                uint32_t header_depth:10;
+                uint32_t reserved_14_15:2;
+                uint32_t data_depth:14;
+        } s;
+        struct cvmx_pciercx_cfg491_s cn52xx;
+        struct cvmx_pciercx_cfg491_s cn52xxp1;
+        struct cvmx_pciercx_cfg491_s cn56xx;
+        struct cvmx_pciercx_cfg491_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg492 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg492_s {
+                uint32_t reserved_26_31:6;
+                uint32_t header_depth:10;
+                uint32_t reserved_14_15:2;
+                uint32_t data_depth:14;
+        } s;
+        struct cvmx_pciercx_cfg492_s cn52xx;
+        struct cvmx_pciercx_cfg492_s cn52xxp1;
+        struct cvmx_pciercx_cfg492_s cn56xx;
+        struct cvmx_pciercx_cfg492_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg516 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg516_s {
+                uint32_t phy_stat:32;
+        } s;
+        struct cvmx_pciercx_cfg516_s cn52xx;
+        struct cvmx_pciercx_cfg516_s cn52xxp1;
+        struct cvmx_pciercx_cfg516_s cn56xx;
+        struct cvmx_pciercx_cfg516_s cn56xxp1;
+};
+
+union cvmx_pciercx_cfg517 {
+        uint32_t u32;
+        struct cvmx_pciercx_cfg517_s {
+                uint32_t phy_ctrl:32;
+        } s;
+        struct cvmx_pciercx_cfg517_s cn52xx;
+        struct cvmx_pciercx_cfg517_s cn52xxp1;
+        struct cvmx_pciercx_cfg517_s cn56xx;
+        struct cvmx_pciercx_cfg517_s cn56xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
new file mode 100644
index 000000000000..f40cfaf84454
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
@@ -0,0 +1,410 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PESCX_DEFS_H__
+#define __CVMX_PESCX_DEFS_H__
+
+#define CVMX_PESCX_BIST_STATUS(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_BIST_STATUS2(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_CFG_RD(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_CFG_WR(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_CPL_LUT_VALID(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_CTL_STATUS(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_CTL_STATUS2(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_DBG_INFO(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_DBG_INFO_EN(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_DIAG_STATUS(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_P2N_BAR0_START(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_P2N_BAR1_START(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_P2N_BAR2_START(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_P2P_BARX_END(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_P2P_BARX_START(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PESCX_TLP_CREDITS(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull))
+
+union cvmx_pescx_bist_status {
+        uint64_t u64;
+        struct cvmx_pescx_bist_status_s {
+                uint64_t reserved_13_63:51;
+                uint64_t rqdata5:1;
+                uint64_t ctlp_or:1;
+                uint64_t ntlp_or:1;
+                uint64_t ptlp_or:1;
+                uint64_t retry:1;
+                uint64_t rqdata0:1;
+                uint64_t rqdata1:1;
+                uint64_t rqdata2:1;
+                uint64_t rqdata3:1;
+                uint64_t rqdata4:1;
+                uint64_t rqhdr1:1;
+                uint64_t rqhdr0:1;
+                uint64_t sot:1;
+        } s;
+        struct cvmx_pescx_bist_status_s cn52xx;
+        struct cvmx_pescx_bist_status_cn52xxp1 {
+                uint64_t reserved_12_63:52;
+                uint64_t ctlp_or:1;
+                uint64_t ntlp_or:1;
+                uint64_t ptlp_or:1;
+                uint64_t retry:1;
+                uint64_t rqdata0:1;
+                uint64_t rqdata1:1;
+                uint64_t rqdata2:1;
+                uint64_t rqdata3:1;
+                uint64_t rqdata4:1;
+                uint64_t rqhdr1:1;
+                uint64_t rqhdr0:1;
+                uint64_t sot:1;
+        } cn52xxp1;
+        struct cvmx_pescx_bist_status_s cn56xx;
+        struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
+};
+
+union cvmx_pescx_bist_status2 {
+        uint64_t u64;
+        struct cvmx_pescx_bist_status2_s {
+                uint64_t reserved_14_63:50;
+                uint64_t cto_p2e:1;
+                uint64_t e2p_cpl:1;
+                uint64_t e2p_n:1;
+                uint64_t e2p_p:1;
+                uint64_t e2p_rsl:1;
+                uint64_t dbg_p2e:1;
+                uint64_t peai_p2e:1;
+                uint64_t rsl_p2e:1;
+                uint64_t pef_tpf1:1;
+                uint64_t pef_tpf0:1;
+                uint64_t pef_tnf:1;
+                uint64_t pef_tcf1:1;
+                uint64_t pef_tc0:1;
+                uint64_t ppf:1;
+        } s;
+        struct cvmx_pescx_bist_status2_s cn52xx;
+        struct cvmx_pescx_bist_status2_s cn52xxp1;
+        struct cvmx_pescx_bist_status2_s cn56xx;
+        struct cvmx_pescx_bist_status2_s cn56xxp1;
+};
+
+union cvmx_pescx_cfg_rd {
+        uint64_t u64;
+        struct cvmx_pescx_cfg_rd_s {
+                uint64_t data:32;
+                uint64_t addr:32;
+        } s;
+        struct cvmx_pescx_cfg_rd_s cn52xx;
+        struct cvmx_pescx_cfg_rd_s cn52xxp1;
+        struct cvmx_pescx_cfg_rd_s cn56xx;
+        struct cvmx_pescx_cfg_rd_s cn56xxp1;
+};
+
+union cvmx_pescx_cfg_wr {
+        uint64_t u64;
+        struct cvmx_pescx_cfg_wr_s {
+                uint64_t data:32;
+                uint64_t addr:32;
+        } s;
+        struct cvmx_pescx_cfg_wr_s cn52xx;
+        struct cvmx_pescx_cfg_wr_s cn52xxp1;
+        struct cvmx_pescx_cfg_wr_s cn56xx;
+        struct cvmx_pescx_cfg_wr_s cn56xxp1;
+};
+
+union cvmx_pescx_cpl_lut_valid {
+        uint64_t u64;
+        struct cvmx_pescx_cpl_lut_valid_s {
+                uint64_t reserved_32_63:32;
+                uint64_t tag:32;
+        } s;
+        struct cvmx_pescx_cpl_lut_valid_s cn52xx;
+        struct cvmx_pescx_cpl_lut_valid_s cn52xxp1;
+        struct cvmx_pescx_cpl_lut_valid_s cn56xx;
+        struct cvmx_pescx_cpl_lut_valid_s cn56xxp1;
+};
+
+union cvmx_pescx_ctl_status {
+        uint64_t u64;
+        struct cvmx_pescx_ctl_status_s {
+                uint64_t reserved_28_63:36;
+                uint64_t dnum:5;
+                uint64_t pbus:8;
+                uint64_t qlm_cfg:2;
+                uint64_t lane_swp:1;
+                uint64_t pm_xtoff:1;
+                uint64_t pm_xpme:1;
+                uint64_t ob_p_cmd:1;
+                uint64_t reserved_7_8:2;
+                uint64_t nf_ecrc:1;
+                uint64_t dly_one:1;
+                uint64_t lnk_enb:1;
+                uint64_t ro_ctlp:1;
+                uint64_t reserved_2_2:1;
+                uint64_t inv_ecrc:1;
+                uint64_t inv_lcrc:1;
+        } s;
+        struct cvmx_pescx_ctl_status_s cn52xx;
+        struct cvmx_pescx_ctl_status_s cn52xxp1;
+        struct cvmx_pescx_ctl_status_cn56xx {
+                uint64_t reserved_28_63:36;
+                uint64_t dnum:5;
+                uint64_t pbus:8;
+                uint64_t qlm_cfg:2;
+                uint64_t reserved_12_12:1;
+                uint64_t pm_xtoff:1;
+                uint64_t pm_xpme:1;
+                uint64_t ob_p_cmd:1;
+                uint64_t reserved_7_8:2;
+                uint64_t nf_ecrc:1;
+                uint64_t dly_one:1;
+                uint64_t lnk_enb:1;
+                uint64_t ro_ctlp:1;
+                uint64_t reserved_2_2:1;
+                uint64_t inv_ecrc:1;
+                uint64_t inv_lcrc:1;
+        } cn56xx;
+        struct cvmx_pescx_ctl_status_cn56xx cn56xxp1;
+};
+
+union cvmx_pescx_ctl_status2 {
+        uint64_t u64;
+        struct cvmx_pescx_ctl_status2_s {
+                uint64_t reserved_2_63:62;
+                uint64_t pclk_run:1;
+                uint64_t pcierst:1;
+        } s;
+        struct cvmx_pescx_ctl_status2_s cn52xx;
+        struct cvmx_pescx_ctl_status2_cn52xxp1 {
+                uint64_t reserved_1_63:63;
+                uint64_t pcierst:1;
+        } cn52xxp1;
+        struct cvmx_pescx_ctl_status2_s cn56xx;
+        struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
+};
+
+union cvmx_pescx_dbg_info {
+        uint64_t u64;
+        struct cvmx_pescx_dbg_info_s {
+                uint64_t reserved_31_63:33;
+                uint64_t ecrc_e:1;
+                uint64_t rawwpp:1;
+                uint64_t racpp:1;
+                uint64_t ramtlp:1;
+                uint64_t rarwdns:1;
+                uint64_t caar:1;
+                uint64_t racca:1;
+                uint64_t racur:1;
+                uint64_t rauc:1;
+                uint64_t rqo:1;
+                uint64_t fcuv:1;
+                uint64_t rpe:1;
+                uint64_t fcpvwt:1;
+                uint64_t dpeoosd:1;
+                uint64_t rtwdle:1;
+                uint64_t rdwdle:1;
+                uint64_t mre:1;
+                uint64_t rte:1;
+                uint64_t acto:1;
+                uint64_t rvdm:1;
+                uint64_t rumep:1;
+                uint64_t rptamrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rfemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rcemrc:1;
+                uint64_t rpoison:1;
+                uint64_t recrce:1;
+                uint64_t rtlplle:1;
+                uint64_t rtlpmal:1;
+                uint64_t spoison:1;
+        } s;
+        struct cvmx_pescx_dbg_info_s cn52xx;
+        struct cvmx_pescx_dbg_info_s cn52xxp1;
+        struct cvmx_pescx_dbg_info_s cn56xx;
+        struct cvmx_pescx_dbg_info_s cn56xxp1;
+};
+
+union cvmx_pescx_dbg_info_en {
+        uint64_t u64;
+        struct cvmx_pescx_dbg_info_en_s {
+                uint64_t reserved_31_63:33;
+                uint64_t ecrc_e:1;
+                uint64_t rawwpp:1;
+                uint64_t racpp:1;
+                uint64_t ramtlp:1;
+                uint64_t rarwdns:1;
+                uint64_t caar:1;
+                uint64_t racca:1;
+                uint64_t racur:1;
+                uint64_t rauc:1;
+                uint64_t rqo:1;
+                uint64_t fcuv:1;
+                uint64_t rpe:1;
+                uint64_t fcpvwt:1;
+                uint64_t dpeoosd:1;
+                uint64_t rtwdle:1;
+                uint64_t rdwdle:1;
+                uint64_t mre:1;
+                uint64_t rte:1;
+                uint64_t acto:1;
+                uint64_t rvdm:1;
+                uint64_t rumep:1;
+                uint64_t rptamrc:1;
+                uint64_t rpmerc:1;
+                uint64_t rfemrc:1;
+                uint64_t rnfemrc:1;
+                uint64_t rcemrc:1;
+                uint64_t rpoison:1;
+                uint64_t recrce:1;
+                uint64_t rtlplle:1;
+                uint64_t rtlpmal:1;
+                uint64_t spoison:1;
+        } s;
+        struct cvmx_pescx_dbg_info_en_s cn52xx;
+        struct cvmx_pescx_dbg_info_en_s cn52xxp1;
+        struct cvmx_pescx_dbg_info_en_s cn56xx;
+        struct cvmx_pescx_dbg_info_en_s cn56xxp1;
+};
+
+union cvmx_pescx_diag_status {
+        uint64_t u64;
+        struct cvmx_pescx_diag_status_s {
+                uint64_t reserved_4_63:60;
+                uint64_t pm_dst:1;
+                uint64_t pm_stat:1;
+                uint64_t pm_en:1;
+                uint64_t aux_en:1;
+        } s;
+        struct cvmx_pescx_diag_status_s cn52xx;
+        struct cvmx_pescx_diag_status_s cn52xxp1;
+        struct cvmx_pescx_diag_status_s cn56xx;
+        struct cvmx_pescx_diag_status_s cn56xxp1;
+};
+
+union cvmx_pescx_p2n_bar0_start {
+        uint64_t u64;
+        struct cvmx_pescx_p2n_bar0_start_s {
+                uint64_t addr:50;
+                uint64_t reserved_0_13:14;
+        } s;
+        struct cvmx_pescx_p2n_bar0_start_s cn52xx;
+        struct cvmx_pescx_p2n_bar0_start_s cn52xxp1;
+        struct cvmx_pescx_p2n_bar0_start_s cn56xx;
+        struct cvmx_pescx_p2n_bar0_start_s cn56xxp1;
+};
+
+union cvmx_pescx_p2n_bar1_start {
+        uint64_t u64;
+        struct cvmx_pescx_p2n_bar1_start_s {
+                uint64_t addr:38;
+                uint64_t reserved_0_25:26;
+        } s;
+        struct cvmx_pescx_p2n_bar1_start_s cn52xx;
+        struct cvmx_pescx_p2n_bar1_start_s cn52xxp1;
+        struct cvmx_pescx_p2n_bar1_start_s cn56xx;
+        struct cvmx_pescx_p2n_bar1_start_s cn56xxp1;
+};
+
+union cvmx_pescx_p2n_bar2_start {
+        uint64_t u64;
+        struct cvmx_pescx_p2n_bar2_start_s {
+                uint64_t addr:25;
+                uint64_t reserved_0_38:39;
+        } s;
+        struct cvmx_pescx_p2n_bar2_start_s cn52xx;
+        struct cvmx_pescx_p2n_bar2_start_s cn52xxp1;
+        struct cvmx_pescx_p2n_bar2_start_s cn56xx;
+        struct cvmx_pescx_p2n_bar2_start_s cn56xxp1;
+};
+
+union cvmx_pescx_p2p_barx_end {
+        uint64_t u64;
+        struct cvmx_pescx_p2p_barx_end_s {
+                uint64_t addr:52;
+                uint64_t reserved_0_11:12;
+        } s;
+        struct cvmx_pescx_p2p_barx_end_s cn52xx;
+        struct cvmx_pescx_p2p_barx_end_s cn52xxp1;
+        struct cvmx_pescx_p2p_barx_end_s cn56xx;
+        struct cvmx_pescx_p2p_barx_end_s cn56xxp1;
+};
+
+union cvmx_pescx_p2p_barx_start {
+        uint64_t u64;
+        struct cvmx_pescx_p2p_barx_start_s {
+                uint64_t addr:52;
+                uint64_t reserved_0_11:12;
+        } s;
+        struct cvmx_pescx_p2p_barx_start_s cn52xx;
+        struct cvmx_pescx_p2p_barx_start_s cn52xxp1;
+        struct cvmx_pescx_p2p_barx_start_s cn56xx;
+        struct cvmx_pescx_p2p_barx_start_s cn56xxp1;
+};
+
+union cvmx_pescx_tlp_credits {
+        uint64_t u64;
+        struct cvmx_pescx_tlp_credits_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_pescx_tlp_credits_cn52xx {
+                uint64_t reserved_56_63:8;
+                uint64_t peai_ppf:8;
+                uint64_t pesc_cpl:8;
+                uint64_t pesc_np:8;
+                uint64_t pesc_p:8;
+                uint64_t npei_cpl:8;
+                uint64_t npei_np:8;
+                uint64_t npei_p:8;
+        } cn52xx;
+        struct cvmx_pescx_tlp_credits_cn52xxp1 {
+                uint64_t reserved_38_63:26;
+                uint64_t peai_ppf:8;
+                uint64_t pesc_cpl:5;
+                uint64_t pesc_np:5;
+                uint64_t pesc_p:5;
+                uint64_t npei_cpl:5;
+                uint64_t npei_np:5;
+                uint64_t npei_p:5;
+        } cn52xxp1;
+        struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
+        struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
new file mode 100644
index 000000000000..5ea5dc571b54
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -0,0 +1,229 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * cvmx-pexp-defs.h
+ *
+ * Configuration and status register (CSR) definitions for
+ * OCTEON PEXP.
+ *
+ */
+#ifndef __CVMX_PEXP_DEFS_H__
+#define __CVMX_PEXP_DEFS_H__
+
+#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16))
+#define CVMX_PEXP_NPEI_BIST_STATUS \
+         CVMX_ADD_IO_SEG(0x00011F0000008580ull)
+#define CVMX_PEXP_NPEI_BIST_STATUS2 \
+         CVMX_ADD_IO_SEG(0x00011F0000008680ull)
+#define CVMX_PEXP_NPEI_CTL_PORT0 \
+         CVMX_ADD_IO_SEG(0x00011F0000008250ull)
+#define CVMX_PEXP_NPEI_CTL_PORT1 \
+         CVMX_ADD_IO_SEG(0x00011F0000008260ull)
+#define CVMX_PEXP_NPEI_CTL_STATUS \
+         CVMX_ADD_IO_SEG(0x00011F0000008570ull)
+#define CVMX_PEXP_NPEI_CTL_STATUS2 \
+         CVMX_ADD_IO_SEG(0x00011F000000BC00ull)
+#define CVMX_PEXP_NPEI_DATA_OUT_CNT \
+         CVMX_ADD_IO_SEG(0x00011F00000085F0ull)
+#define CVMX_PEXP_NPEI_DBG_DATA \
+         CVMX_ADD_IO_SEG(0x00011F0000008510ull)
+#define CVMX_PEXP_NPEI_DBG_SELECT \
+         CVMX_ADD_IO_SEG(0x00011F0000008500ull)
+#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \
+         CVMX_ADD_IO_SEG(0x00011F00000085C0ull)
+#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \
+         CVMX_ADD_IO_SEG(0x00011F00000085D0ull)
+#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16))
+#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \
+         CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16))
+#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16))
+#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \
+         CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16))
+#define CVMX_PEXP_NPEI_DMA_CNTS \
+         CVMX_ADD_IO_SEG(0x00011F00000085E0ull)
+#define CVMX_PEXP_NPEI_DMA_CONTROL \
+         CVMX_ADD_IO_SEG(0x00011F00000083A0ull)
+#define CVMX_PEXP_NPEI_INT_A_ENB \
+         CVMX_ADD_IO_SEG(0x00011F0000008560ull)
+#define CVMX_PEXP_NPEI_INT_A_ENB2 \
+         CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)
+#define CVMX_PEXP_NPEI_INT_A_SUM \
+         CVMX_ADD_IO_SEG(0x00011F0000008550ull)
+#define CVMX_PEXP_NPEI_INT_ENB \
+         CVMX_ADD_IO_SEG(0x00011F0000008540ull)
+#define CVMX_PEXP_NPEI_INT_ENB2 \
+         CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)
+#define CVMX_PEXP_NPEI_INT_INFO \
+         CVMX_ADD_IO_SEG(0x00011F0000008590ull)
+#define CVMX_PEXP_NPEI_INT_SUM \
+         CVMX_ADD_IO_SEG(0x00011F0000008530ull)
+#define CVMX_PEXP_NPEI_INT_SUM2 \
+         CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \
+         CVMX_ADD_IO_SEG(0x00011F0000008600ull)
+#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \
+         CVMX_ADD_IO_SEG(0x00011F0000008610ull)
+#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \
+         CVMX_ADD_IO_SEG(0x00011F00000084F0ull)
+#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12)
+#define CVMX_PEXP_NPEI_MSI_ENB0 \
+         CVMX_ADD_IO_SEG(0x00011F000000BC50ull)
+#define CVMX_PEXP_NPEI_MSI_ENB1 \
+         CVMX_ADD_IO_SEG(0x00011F000000BC60ull)
+#define CVMX_PEXP_NPEI_MSI_ENB2 \
+         CVMX_ADD_IO_SEG(0x00011F000000BC70ull)
+#define CVMX_PEXP_NPEI_MSI_ENB3 \
+         CVMX_ADD_IO_SEG(0x00011F000000BC80ull)
+#define CVMX_PEXP_NPEI_MSI_RCV0 \
+         CVMX_ADD_IO_SEG(0x00011F000000BC10ull)
+#define CVMX_PEXP_NPEI_MSI_RCV1 \
+         CVMX_ADD_IO_SEG(0x00011F000000BC20ull)
+#define CVMX_PEXP_NPEI_MSI_RCV2 \
+         CVMX_ADD_IO_SEG(0x00011F000000BC30ull)
+#define CVMX_PEXP_NPEI_MSI_RCV3 \
+         CVMX_ADD_IO_SEG(0x00011F000000BC40ull)
+#define CVMX_PEXP_NPEI_MSI_RD_MAP \
+         CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \
+         CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \
+         CVMX_ADD_IO_SEG(0x00011F000000BD00ull)
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \
+         CVMX_ADD_IO_SEG(0x00011F000000BD10ull)
+#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \
+         CVMX_ADD_IO_SEG(0x00011F000000BD20ull)
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \
+         CVMX_ADD_IO_SEG(0x00011F000000BD30ull)
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \
+         CVMX_ADD_IO_SEG(0x00011F000000BD40ull)
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \
+         CVMX_ADD_IO_SEG(0x00011F000000BD50ull)
+#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \
+         CVMX_ADD_IO_SEG(0x00011F000000BD60ull)
+#define CVMX_PEXP_NPEI_MSI_WR_MAP \
+         CVMX_ADD_IO_SEG(0x00011F000000BC90ull)
+#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \
+         CVMX_ADD_IO_SEG(0x00011F000000BD70ull)
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \
+         CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \
+         CVMX_ADD_IO_SEG(0x00011F0000008650ull)
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \
+         CVMX_ADD_IO_SEG(0x00011F0000008660ull)
+#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \
+         CVMX_ADD_IO_SEG(0x00011F0000008670ull)
+#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \
+         CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16))
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \
+         CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16))
+#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
+         CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16))
+#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
+         CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16))
+#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \
+         CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16))
+#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \
+         CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16))
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16))
+#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16))
+#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
+         CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16))
+#define CVMX_PEXP_NPEI_PKT_CNT_INT \
+         CVMX_ADD_IO_SEG(0x00011F0000009110ull)
+#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \
+         CVMX_ADD_IO_SEG(0x00011F0000009130ull)
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \
+         CVMX_ADD_IO_SEG(0x00011F00000090B0ull)
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \
+         CVMX_ADD_IO_SEG(0x00011F00000090A0ull)
+#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \
+         CVMX_ADD_IO_SEG(0x00011F0000009090ull)
+#define CVMX_PEXP_NPEI_PKT_DPADDR \
+         CVMX_ADD_IO_SEG(0x00011F0000009080ull)
+#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \
+         CVMX_ADD_IO_SEG(0x00011F0000009150ull)
+#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \
+         CVMX_ADD_IO_SEG(0x00011F0000009000ull)
+#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \
+         CVMX_ADD_IO_SEG(0x00011F0000009190ull)
+#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \
+         CVMX_ADD_IO_SEG(0x00011F0000009020ull)
+#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \
+         CVMX_ADD_IO_SEG(0x00011F0000009100ull)
+#define CVMX_PEXP_NPEI_PKT_IN_BP \
+         CVMX_ADD_IO_SEG(0x00011F00000086B0ull)
+#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \
+         CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16))
+#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \
+         CVMX_ADD_IO_SEG(0x00011F00000086A0ull)
+#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \
+         CVMX_ADD_IO_SEG(0x00011F00000091A0ull)
+#define CVMX_PEXP_NPEI_PKT_IPTR \
+         CVMX_ADD_IO_SEG(0x00011F0000009070ull)
+#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \
+         CVMX_ADD_IO_SEG(0x00011F0000009160ull)
+#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \
+         CVMX_ADD_IO_SEG(0x00011F00000090D0ull)
+#define CVMX_PEXP_NPEI_PKT_OUT_ENB \
+         CVMX_ADD_IO_SEG(0x00011F0000009010ull)
+#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \
+         CVMX_ADD_IO_SEG(0x00011F00000090E0ull)
+#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \
+         CVMX_ADD_IO_SEG(0x00011F0000008690ull)
+#define CVMX_PEXP_NPEI_PKT_SLIST_ES \
+         CVMX_ADD_IO_SEG(0x00011F0000009050ull)
+#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \
+         CVMX_ADD_IO_SEG(0x00011F0000009180ull)
+#define CVMX_PEXP_NPEI_PKT_SLIST_NS \
+         CVMX_ADD_IO_SEG(0x00011F0000009040ull)
+#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \
+         CVMX_ADD_IO_SEG(0x00011F0000009030ull)
+#define CVMX_PEXP_NPEI_PKT_TIME_INT \
+         CVMX_ADD_IO_SEG(0x00011F0000009120ull)
+#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \
+         CVMX_ADD_IO_SEG(0x00011F0000009140ull)
+#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \
+         CVMX_ADD_IO_SEG(0x00011F0000008520ull)
+#define CVMX_PEXP_NPEI_SCRATCH_1 \
+         CVMX_ADD_IO_SEG(0x00011F0000008270ull)
+#define CVMX_PEXP_NPEI_STATE1 \
+         CVMX_ADD_IO_SEG(0x00011F0000008620ull)
+#define CVMX_PEXP_NPEI_STATE2 \
+         CVMX_ADD_IO_SEG(0x00011F0000008630ull)
+#define CVMX_PEXP_NPEI_STATE3 \
+         CVMX_ADD_IO_SEG(0x00011F0000008640ull)
+#define CVMX_PEXP_NPEI_WINDOW_CTL \
+         CVMX_ADD_IO_SEG(0x00011F0000008380ull)
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 03fddfa3e928..e31e3fe14f8a 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -376,6 +376,18 @@ static inline uint64_t cvmx_get_cycle(void)
 }
 
 /**
+ * Wait for the specified number of cycle
+ *
+ */
+static inline void cvmx_wait(uint64_t cycles)
+{
+        uint64_t done = cvmx_get_cycle() + cycles;
+
+        while (cvmx_get_cycle() < done)
+                ; /* Spin */
+}
+
+/**
  * Reads a chip global cycle counter.  This counts CPU cycles since
  * chip reset.  The counter is 64 bit.
  * This register does not exist on CN38XX pass 1 silicion
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index 04fac684069c..ef24a7b4ea57 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -57,6 +57,13 @@ enum octeon_feature {
         OCTEON_FEATURE_RAID,
         /* Octeon has a builtin USB */
         OCTEON_FEATURE_USB,
+        /* Octeon IPD can run without using work queue entries */
+        OCTEON_FEATURE_NO_WPTR,
+        /* Octeon has DFA state machines */
+        OCTEON_FEATURE_DFA,
+        /* Octeon MDIO block supports clause 45 transactions for 10
+         * Gig support */
+        OCTEON_FEATURE_MDIO_CLAUSE_45,
 };
 
 static inline int cvmx_fuse_read(int fuse);
@@ -112,6 +119,26 @@ static inline int octeon_has_feature(enum octeon_feature feature)
         case OCTEON_FEATURE_USB:
                 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
                          || OCTEON_IS_MODEL(OCTEON_CN58XX));
+        case OCTEON_FEATURE_NO_WPTR:
+                return (OCTEON_IS_MODEL(OCTEON_CN56XX)
+                         || OCTEON_IS_MODEL(OCTEON_CN52XX))
+                        && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
+                        && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
+        case OCTEON_FEATURE_DFA:
+                if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
+                    && !OCTEON_IS_MODEL(OCTEON_CN31XX)
+                    && !OCTEON_IS_MODEL(OCTEON_CN58XX))
+                        return 0;
+                else if (OCTEON_IS_MODEL(OCTEON_CN3020))
+                        return 0;
+                else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
+                        return 1;
+                else
+                        return !cvmx_fuse_read(120);
+        case OCTEON_FEATURE_MDIO_CLAUSE_45:
+                return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
+                         || OCTEON_IS_MODEL(OCTEON_CN58XX)
+                         || OCTEON_IS_MODEL(OCTEON_CN50XX));
         }
         return 0;
 }
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index edc676084cda..cac9b1a206fc 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -245,4 +245,6 @@ static inline uint32_t octeon_npi_read32(uint64_t address)
         return cvmx_read64_uint32(address ^ 4);
 }
 
+extern struct cvmx_bootinfo *octeon_bootinfo;
+
 #endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 72c80d2034c2..dc0eaa731281 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -32,6 +32,11 @@
 #define PAGE_SIZE       (1UL << PAGE_SHIFT)
 #define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
 
+#define HPAGE_SHIFT     (PAGE_SHIFT + PAGE_SHIFT - 3)
+#define HPAGE_SIZE      ((1UL) << HPAGE_SHIFT)
+#define HPAGE_MASK      (~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+
 #ifndef __ASSEMBLY__
 
 #include <linux/pfn.h>
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 053e4634acee..a68d111e55e9 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -142,19 +142,6 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev,
 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
                                     struct pci_bus_region *region);
 
-static inline struct resource *
-pcibios_select_root(struct pci_dev *pdev, struct resource *res)
-{
-        struct resource *root = NULL;
-
-        if (res->flags & IORESOURCE_IO)
-                root = &ioport_resource;
-        if (res->flags & IORESOURCE_MEM)
-                root = &iomem_resource;
-
-        return root;
-}
-
 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 
 static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 51b34a48c84a..1073e6df8621 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -72,6 +72,7 @@
 #else
 
 #define _PAGE_R4KBUG                (1<<5)  /* workaround for r4k bug  */
+#define _PAGE_HUGE                  (1<<5)  /* huge tlb page */
 #define _PAGE_GLOBAL                (1<<6)
 #define _PAGE_VALID                 (1<<7)
 #define _PAGE_SILENT_READ           (1<<7)  /* synonym                 */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 6a0edf72ffbc..1a9f9b257551 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -292,6 +292,16 @@ static inline pte_t pte_mkyoung(pte_t pte)
                 pte_val(pte) |= _PAGE_SILENT_READ;
         return pte;
 }
+
+#ifdef _PAGE_HUGE
+static inline int pte_huge(pte_t pte)   { return pte_val(pte) & _PAGE_HUGE; }
+
+static inline pte_t pte_mkhuge(pte_t pte)
+{
+        pte_val(pte) |= _PAGE_HUGE;
+        return pte;
+}
+#endif /* _PAGE_HUGE */
 #endif
 static inline int pte_special(pte_t pte)        { return 0; }
 static inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 4c140db36786..387bf59f1e37 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -399,6 +399,7 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
 __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
 __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index 64ffc0290b84..fd545547b8aa 100644
--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
@@ -26,6 +26,10 @@ struct plat_smp_ops {
         void (*boot_secondary)(int cpu, struct task_struct *idle);
         void (*smp_setup)(void);
         void (*prepare_cpus)(unsigned int max_cpus);
+#ifdef CONFIG_HOTPLUG_CPU
+        int (*cpu_disable)(void);
+        void (*cpu_die)(unsigned int cpu);
+#endif
 };
 
 extern void register_smp_ops(struct plat_smp_ops *ops);
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 40e5ef1d4d26..aaa2d4ab26dc 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -13,6 +13,7 @@
 
 #include <linux/bitops.h>
 #include <linux/linkage.h>
+#include <linux/smp.h>
 #include <linux/threads.h>
 #include <linux/cpumask.h>
 
@@ -40,6 +41,7 @@ extern int __cpu_logical_map[NR_CPUS];
 /* Octeon - Tell another core to flush its icache */
 #define SMP_ICACHE_FLUSH        0x4
 
+extern volatile cpumask_t cpu_callin_map;
 
 extern void asmlinkage smp_bootstrap(void);
 
@@ -55,6 +57,24 @@ static inline void smp_send_reschedule(int cpu)
         mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF);
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static inline int __cpu_disable(void)
+{
+        extern struct plat_smp_ops *mp_ops;     /* private */
+
+        return mp_ops->cpu_disable();
+}
+
+static inline void __cpu_die(unsigned int cpu)
+{
+        extern struct plat_smp_ops *mp_ops;     /* private */
+
+        mp_ops->cpu_die(cpu);
+}
+
+extern void play_dead(void);
+#endif
+
 extern asmlinkage void smp_call_function_interrupt(void);
 
 extern void arch_send_call_function_single_ipi(int cpu);
diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
index 3a56d90abfa6..2367b56dcdef 100644
--- a/arch/mips/include/asm/sn/addrs.h
+++ b/arch/mips/include/asm/sn/addrs.h
@@ -11,6 +11,7 @@
 
 
 #ifndef __ASSEMBLY__
+#include <linux/smp.h>
 #include <linux/types.h>
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h
new file mode 100644
index 000000000000..294cdb66c5fc
--- /dev/null
+++ b/arch/mips/include/asm/suspend.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_SUSPEND_H
+#define __ASM_SUSPEND_H
+
+static inline int arch_prepare_suspend(void) { return 0; }
+
+/* References to section boundaries */
+extern const void __nosave_begin, __nosave_end;
+
+#endif /* __ASM_SUSPEND_H */
diff --git a/arch/mips/include/asm/txx9/dmac.h b/arch/mips/include/asm/txx9/dmac.h
new file mode 100644
index 000000000000..5e9151fccbb4
--- /dev/null
+++ b/arch/mips/include/asm/txx9/dmac.h
@@ -0,0 +1,51 @@
+/*
+ * TXx9 SoC DMA Controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_TXX9_DMAC_H
+#define __ASM_TXX9_DMAC_H
+
+#include <linux/dmaengine.h>
+
+#define TXX9_DMA_MAX_NR_CHANNELS        4
+
+/**
+ * struct txx9dmac_platform_data - Controller configuration parameters
+ * @memcpy_chan: Channel used for DMA_MEMCPY
+ * @have_64bit_regs: DMAC have 64 bit registers
+ */
+struct txx9dmac_platform_data {
+        int     memcpy_chan;
+        bool    have_64bit_regs;
+};
+
+/**
+ * struct txx9dmac_chan_platform_data - Channel configuration parameters
+ * @dmac_dev: A platform device for DMAC
+ */
+struct txx9dmac_chan_platform_data {
+        struct platform_device *dmac_dev;
+};
+
+/**
+ * struct txx9dmac_slave - Controller-specific information about a slave
+ * @tx_reg: physical address of data register used for
+ *      memory-to-peripheral transfers
+ * @rx_reg: physical address of data register used for
+ *      peripheral-to-memory transfers
+ * @reg_width: peripheral register width
+ */
+struct txx9dmac_slave {
+        u64             tx_reg;
+        u64             rx_reg;
+        unsigned int    reg_width;
+};
+
+void txx9_dmac_init(int id, unsigned long baseaddr, int irq,
+                    const struct txx9dmac_platform_data *pdata);
+
+#endif /* __ASM_TXX9_DMAC_H */
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
index 9cde0090cbf6..827dc22be2ea 100644
--- a/arch/mips/include/asm/txx9/generic.h
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -91,4 +91,10 @@ void txx9_7segled_init(unsigned int num,
                        void (*putc)(unsigned int pos, unsigned char val));
 int txx9_7segled_putc(unsigned int pos, char c);
 
+void __init txx9_aclc_init(unsigned long baseaddr, int irq,
+                           unsigned int dmac_id,
+                           unsigned int dma_chan_out,
+                           unsigned int dma_chan_in);
+void __init txx9_sramc_init(struct resource *r);
+
 #endif /* __ASM_TXX9_GENERIC_H */
diff --git a/arch/mips/include/asm/txx9/tx4927.h b/arch/mips/include/asm/txx9/tx4927.h
index 7d813f1cb98d..18c98c52afdb 100644
--- a/arch/mips/include/asm/txx9/tx4927.h
+++ b/arch/mips/include/asm/txx9/tx4927.h
@@ -41,6 +41,7 @@
 
 #define TX4927_SDRAMC_REG       (TX4927_REG_BASE + 0x8000)
 #define TX4927_EBUSC_REG        (TX4927_REG_BASE + 0x9000)
+#define TX4927_DMA_REG          (TX4927_REG_BASE + 0xb000)
 #define TX4927_PCIC_REG         (TX4927_REG_BASE + 0xd000)
 #define TX4927_CCFG_REG         (TX4927_REG_BASE + 0xe000)
 #define TX4927_IRC_REG          (TX4927_REG_BASE + 0xf600)
@@ -49,6 +50,7 @@
 #define TX4927_NR_SIO   2
 #define TX4927_SIO_REG(ch)      (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
 #define TX4927_PIO_REG          (TX4927_REG_BASE + 0xf500)
+#define TX4927_ACLC_REG         (TX4927_REG_BASE + 0xf700)
 
 #define TX4927_IR_ECCERR        0
 #define TX4927_IR_WTOERR        1
@@ -265,5 +267,7 @@ int tx4927_pciclk66_setup(void);
 void tx4927_setup_pcierr_irq(void);
 void tx4927_irq_init(void);
 void tx4927_mtd_init(int ch);
+void tx4927_dmac_init(int memcpy_chan);
+void tx4927_aclc_init(unsigned int dma_chan_out, unsigned int dma_chan_in);
 
 #endif /* __ASM_TXX9_TX4927_H */
diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h
index cd8bc2021755..8a178f186f7d 100644
--- a/arch/mips/include/asm/txx9/tx4938.h
+++ b/arch/mips/include/asm/txx9/tx4938.h
@@ -305,5 +305,8 @@ struct tx4938ide_platform_info {
 };
 
 void tx4938_ata_init(unsigned int irq, unsigned int shift, int tune);
+void tx4938_dmac_init(int memcpy_chan0, int memcpy_chan1);
+void tx4938_aclc_init(void);
+void tx4938_sramc_init(void);
 
 #endif
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
index f02c50b3abfb..d4f342cd5939 100644
--- a/arch/mips/include/asm/txx9/tx4939.h
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -45,6 +45,8 @@
 #define TX4939_RTC_REG          (TX4939_REG_BASE + 0xfb00)
 #define TX4939_CIR_REG          (TX4939_REG_BASE + 0xfc00)
 
+#define TX4939_RNG_REG          (TX4939_CRYPTO_REG + 0xb0)
+
 struct tx4939_le_reg {
         __u32 r;
         __u32 unused;
@@ -544,5 +546,9 @@ void tx4939_ata_init(void);
 void tx4939_rtc_init(void);
 void tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
                        unsigned char ch_mask, unsigned char wide_mask);
+void tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1);
+void tx4939_aclc_init(void);
+void tx4939_sramc_init(void);
+void tx4939_rng_init(void);
 
 #endif /* __ASM_TXX9_TX4939_H */
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index d9b6a5b5399d..7fd170d007e7 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -10,6 +10,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
+#include <linux/smp.h>
 #include <linux/spinlock.h>
 
 #include <asm/irq_cpu.h>
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index c901c22d7ad0..8d006ec65677 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -14,6 +14,7 @@
 #include <linux/mm.h>
 #include <linux/interrupt.h>
 #include <linux/kbuild.h>
+#include <linux/suspend.h>
 #include <asm/ptrace.h>
 #include <asm/processor.h>
 
@@ -326,3 +327,15 @@ void output_octeon_cop2_state_defines(void)
         BLANK();
 }
 #endif
+
+#ifdef CONFIG_HIBERNATION
+void output_pbe_defines(void)
+{
+        COMMENT(" Linux struct pbe offsets. ");
+        OFFSET(PBE_ADDRESS, pbe, address);
+        OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
+        OFFSET(PBE_NEXT, pbe, next);
+        DEFINE(PBE_SIZE, sizeof(struct pbe));
+        BLANK();
+}
+#endif
diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c
index a5182a207696..e02f79b1eb51 100644
--- a/arch/mips/kernel/cevt-bcm1480.c
+++ b/arch/mips/kernel/cevt-bcm1480.c
@@ -18,6 +18,7 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/percpu.h>
+#include <linux/smp.h>
 
 #include <asm/addrspace.h>
 #include <asm/io.h>
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 0015e442572b..2652362ce047 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -9,6 +9,7 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/percpu.h>
+#include <linux/smp.h>
 
 #include <asm/smtc_ipi.h>
 #include <asm/time.h>
diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c
index 340f53e5c6b1..ac5903d1b20e 100644
--- a/arch/mips/kernel/cevt-sb1250.c
+++ b/arch/mips/kernel/cevt-sb1250.c
@@ -18,6 +18,7 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/percpu.h>
+#include <linux/smp.h>
 
 #include <asm/addrspace.h>
 #include <asm/io.h>
diff --git a/arch/mips/kernel/cevt-smtc.c b/arch/mips/kernel/cevt-smtc.c
index df6f5bc60572..98bd7de75778 100644
--- a/arch/mips/kernel/cevt-smtc.c
+++ b/arch/mips/kernel/cevt-smtc.c
@@ -10,6 +10,7 @@
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/percpu.h>
+#include <linux/smp.h>
 
 #include <asm/smtc_ipi.h>
 #include <asm/time.h>
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 2e911e3da8d3..0037f21baf0d 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -20,22 +20,29 @@
 #define TIMER_CCD       0       /* 1/2 */
 #define TIMER_CLK(imclk)        ((imclk) / (2 << TIMER_CCD))
 
-static struct txx9_tmr_reg __iomem *txx9_cs_tmrptr;
+struct txx9_clocksource {
+        struct clocksource cs;
+        struct txx9_tmr_reg __iomem *tmrptr;
+};
 
 static cycle_t txx9_cs_read(struct clocksource *cs)
 {
-        return __raw_readl(&txx9_cs_tmrptr->trr);
+        struct txx9_clocksource *txx9_cs =
+                container_of(cs, struct txx9_clocksource, cs);
+        return __raw_readl(&txx9_cs->tmrptr->trr);
 }
 
 /* Use 1 bit smaller width to use full bits in that width */
 #define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1)
 
-static struct clocksource txx9_clocksource = {
-        .name           = "TXx9",
-        .rating         = 200,
-        .read           = txx9_cs_read,
-        .mask           = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
-        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+static struct txx9_clocksource txx9_clocksource = {
+        .cs = {
+                .name           = "TXx9",
+                .rating         = 200,
+                .read           = txx9_cs_read,
+                .mask           = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
+                .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+        },
 };
 
 void __init txx9_clocksource_init(unsigned long baseaddr,
@@ -43,8 +50,8 @@ void __init txx9_clocksource_init(unsigned long baseaddr,
 {
         struct txx9_tmr_reg __iomem *tmrptr;
 
-        clocksource_set_clock(&txx9_clocksource, TIMER_CLK(imbusclk));
-        clocksource_register(&txx9_clocksource);
+        clocksource_set_clock(&txx9_clocksource.cs, TIMER_CLK(imbusclk));
+        clocksource_register(&txx9_clocksource.cs);
 
         tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
         __raw_writel(TCR_BASE, &tmrptr->tcr);
@@ -53,10 +60,13 @@ void __init txx9_clocksource_init(unsigned long baseaddr,
         __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
         __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
         __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
-        txx9_cs_tmrptr = tmrptr;
+        txx9_clocksource.tmrptr = tmrptr;
 }
 
-static struct txx9_tmr_reg __iomem *txx9_tmrptr;
+struct txx9_clock_event_device {
+        struct clock_event_device cd;
+        struct txx9_tmr_reg __iomem *tmrptr;
+};
 
 static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
 {
@@ -69,7 +79,9 @@ static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
 static void txx9tmr_set_mode(enum clock_event_mode mode,
                              struct clock_event_device *evt)
 {
-        struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
+        struct txx9_clock_event_device *txx9_cd =
+                container_of(evt, struct txx9_clock_event_device, cd);
+        struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
 
         txx9tmr_stop_and_clear(tmrptr);
         switch (mode) {
@@ -99,7 +111,9 @@ static void txx9tmr_set_mode(enum clock_event_mode mode,
 static int txx9tmr_set_next_event(unsigned long delta,
                                   struct clock_event_device *evt)
 {
-        struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
+        struct txx9_clock_event_device *txx9_cd =
+                container_of(evt, struct txx9_clock_event_device, cd);
+        struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
 
         txx9tmr_stop_and_clear(tmrptr);
         /* start timer */
@@ -108,18 +122,22 @@ static int txx9tmr_set_next_event(unsigned long delta,
         return 0;
 }
 
-static struct clock_event_device txx9tmr_clock_event_device = {
-        .name           = "TXx9",
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .rating         = 200,
-        .set_mode       = txx9tmr_set_mode,
-        .set_next_event = txx9tmr_set_next_event,
+static struct txx9_clock_event_device txx9_clock_event_device = {
+        .cd = {
+                .name           = "TXx9",
+                .features       = CLOCK_EVT_FEAT_PERIODIC |
+                                  CLOCK_EVT_FEAT_ONESHOT,
+                .rating         = 200,
+                .set_mode       = txx9tmr_set_mode,
+                .set_next_event = txx9tmr_set_next_event,
+        },
 };
 
 static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
 {
-        struct clock_event_device *cd = &txx9tmr_clock_event_device;
-        struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr;
+        struct txx9_clock_event_device *txx9_cd = dev_id;
+        struct clock_event_device *cd = &txx9_cd->cd;
+        struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
 
         __raw_writel(0, &tmrptr->tisr); /* ack interrupt */
         cd->event_handler(cd);
@@ -130,19 +148,20 @@ static struct irqaction txx9tmr_irq = {
         .handler        = txx9tmr_interrupt,
         .flags          = IRQF_DISABLED | IRQF_PERCPU,
         .name           = "txx9tmr",
+        .dev_id         = &txx9_clock_event_device,
 };
 
 void __init txx9_clockevent_init(unsigned long baseaddr, int irq,
                                  unsigned int imbusclk)
 {
-        struct clock_event_device *cd = &txx9tmr_clock_event_device;
+        struct clock_event_device *cd = &txx9_clock_event_device.cd;
         struct txx9_tmr_reg __iomem *tmrptr;
 
         tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
         txx9tmr_stop_and_clear(tmrptr);
         __raw_writel(TIMER_CCD, &tmrptr->ccdr);
         __raw_writel(0, &tmrptr->itmr);
-        txx9_tmrptr = tmrptr;
+        txx9_clock_event_device.tmrptr = tmrptr;
 
         clockevent_set_clock(cd, TIMER_CLK(imbusclk));
         cd->max_delta_ns =
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b13b8eb30596..1abe9905c9c1 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/ptrace.h>
+#include <linux/smp.h>
 #include <linux/stddef.h>
 
 #include <asm/bugs.h>
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
index ed20e7fe65e3..f7d8d5d0ddbf 100644
--- a/arch/mips/kernel/i8253.c
+++ b/arch/mips/kernel/i8253.c
@@ -7,6 +7,7 @@
 #include <linux/interrupt.h>
 #include <linux/jiffies.h>
 #include <linux/module.h>
+#include <linux/smp.h>
 #include <linux/spinlock.h>
 
 #include <asm/delay.h>
diff --git a/arch/mips/kernel/init_task.c b/arch/mips/kernel/init_task.c
index 149cd914526e..5b457a40c784 100644
--- a/arch/mips/kernel/init_task.c
+++ b/arch/mips/kernel/init_task.c
@@ -11,10 +11,6 @@
 
 static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
 static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct mm_struct init_mm = INIT_MM(init_mm);
-
-EXPORT_SYMBOL(init_mm);
-
 /*
  * Initial thread structure.
  *
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 3f43c2e3aa5a..39000f103f2c 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -2,6 +2,7 @@
 
 #include <linux/bitmap.h>
 #include <linux/init.h>
+#include <linux/smp.h>
 
 #include <asm/io.h>
 #include <asm/gic.h>
diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
index 6e152c80cd4a..50c9bb880667 100644
--- a/arch/mips/kernel/kgdb.c
+++ b/arch/mips/kernel/kgdb.c
@@ -26,6 +26,7 @@
 #include <linux/kgdb.h>
 #include <linux/kdebug.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <asm/inst.h>
 #include <asm/fpu.h>
 #include <asm/cacheflush.h>
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 1eaaa450e20c..c09d681b7181 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -50,10 +50,15 @@
  */
 void __noreturn cpu_idle(void)
 {
+        int cpu;
+
+        /* CPU is going idle. */
+        cpu = smp_processor_id();
+
         /* endless idle loop with no priority at all */
         while (1) {
                 tick_nohz_stop_sched_tick(1);
-                while (!need_resched()) {
+                while (!need_resched() && cpu_online(cpu)) {
 #ifdef CONFIG_MIPS_MT_SMTC
                         extern void smtc_idle_loop_hook(void);
 
@@ -62,6 +67,12 @@ void __noreturn cpu_idle(void)
                         if (cpu_wait)
                                 (*cpu_wait)();
                 }
+#ifdef CONFIG_HOTPLUG_CPU
+                if (!cpu_online(cpu) && !cpu_isset(cpu, cpu_callin_map) &&
+                    (system_state == SYSTEM_RUNNING ||
+                     system_state == SYSTEM_BOOTING))
+                        play_dead();
+#endif
                 tick_nohz_restart_sched_tick();
                 preempt_enable_no_resched();
                 schedule();
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index f27beca4b26d..653be061b9ec 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -20,6 +20,7 @@
 
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/cpumask.h>
 #include <linux/interrupt.h>
 #include <linux/compiler.h>
diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c
index 878e3733bbb2..2508d55d68fd 100644
--- a/arch/mips/kernel/smp-up.c
+++ b/arch/mips/kernel/smp-up.c
@@ -55,6 +55,18 @@ static void __init up_prepare_cpus(unsigned int max_cpus)
 {
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static int up_cpu_disable(void)
+{
+        return -ENOSYS;
+}
+
+static void up_cpu_die(unsigned int cpu)
+{
+        BUG();
+}
+#endif
+
 struct plat_smp_ops up_smp_ops = {
         .send_ipi_single        = up_send_ipi_single,
         .send_ipi_mask          = up_send_ipi_mask,
@@ -64,4 +76,8 @@ struct plat_smp_ops up_smp_ops = {
         .boot_secondary         = up_boot_secondary,
         .smp_setup              = up_smp_setup,
         .prepare_cpus           = up_prepare_cpus,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_disable            = up_cpu_disable,
+        .cpu_die                = up_cpu_die,
+#endif
 };
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index c937506a03aa..bc7d9b05e2f4 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -22,6 +22,7 @@
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/smp.h>
 #include <linux/spinlock.h>
 #include <linux/threads.h>
 #include <linux/module.h>
@@ -44,7 +45,7 @@
 #include <asm/mipsmtregs.h>
 #endif /* CONFIG_MIPS_MT_SMTC */
 
-static volatile cpumask_t cpu_callin_map;       /* Bitmask of started secondaries */
+volatile cpumask_t cpu_callin_map;      /* Bitmask of started secondaries */
 int __cpu_number_map[NR_CPUS];          /* Map physical to logical */
 int __cpu_logical_map[NR_CPUS];         /* Map logical to physical */
 
@@ -200,6 +201,8 @@ void __devinit smp_prepare_boot_cpu(void)
  * and keep control until "cpu_online(cpu)" is set.  Note: cpu is
  * physical, not logical.
  */
+static struct task_struct *cpu_idle_thread[NR_CPUS];
+
 int __cpuinit __cpu_up(unsigned int cpu)
 {
         struct task_struct *idle;
@@ -209,9 +212,16 @@ int __cpuinit __cpu_up(unsigned int cpu)
          * The following code is purely to make sure
          * Linux can schedule processes on this slave.
          */
-        idle = fork_idle(cpu);
-        if (IS_ERR(idle))
-                panic(KERN_ERR "Fork failed for CPU %d", cpu);
+        if (!cpu_idle_thread[cpu]) {
+                idle = fork_idle(cpu);
+                cpu_idle_thread[cpu] = idle;
+
+                if (IS_ERR(idle))
+                        panic(KERN_ERR "Fork failed for CPU %d", cpu);
+        } else {
+                idle = cpu_idle_thread[cpu];
+                init_idle(idle, cpu);
+        }
 
         mp_ops->boot_secondary(cpu, idle);
 
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 5f5af7d4c890..8a0626cbb108 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -20,6 +20,7 @@
 #include <linux/clockchips.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/cpumask.h>
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
@@ -924,6 +925,7 @@ void ipi_decode(struct smtc_ipi *pipi)
         int irq = MIPS_CPU_IRQ_BASE + 1;
 
         smtc_ipi_nq(&freeIPIq, pipi);
+
         switch (type_copy) {
         case SMTC_CLOCK_TICK:
                 irq_enter();
diff --git a/arch/mips/kernel/topology.c b/arch/mips/kernel/topology.c
index 660e44ed44d7..cf3eb61fad12 100644
--- a/arch/mips/kernel/topology.c
+++ b/arch/mips/kernel/topology.c
@@ -17,7 +17,10 @@ static int __init topology_init(void)
 #endif /* CONFIG_NUMA */
 
         for_each_present_cpu(i) {
-                ret = register_cpu(&per_cpu(cpu_devices, i), i);
+                struct cpu *c = &per_cpu(cpu_devices, i);
+
+                c->hotpluggable = 1;
+                ret = register_cpu(c, i);
                 if (ret)
                         printk(KERN_WARNING "topology_init: register_cpu %d "
                                "failed (%d)\n", i, ret);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index e83da174b533..08f1edf355e8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1502,7 +1502,7 @@ void __cpuinit per_cpu_trap_init(void)
                          status_set);
 
         if (cpu_has_mips_r2) {
-                unsigned int enable = 0x0000000f;
+                unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
 
                 if (!noulri && cpu_has_userlocal)
                         enable |= (1 << 29);
@@ -1510,10 +1510,6 @@ void __cpuinit per_cpu_trap_init(void)
                 write_c0_hwrena(enable);
         }
 
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-        write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
-#endif
-
 #ifdef CONFIG_MIPS_MT_SMTC
         if (!secondaryTC) {
 #endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c
index f69c6b569eb3..6b3b1de9dcae 100644
--- a/arch/mips/lib/delay.c
+++ b/arch/mips/lib/delay.c
@@ -43,7 +43,7 @@ void __udelay(unsigned long us)
 {
         unsigned int lpj = current_cpu_data.udelay_val;
 
-        __delay((us * 0x000010c7 * HZ * lpj) >> 32);
+        __delay((us * 0x000010c7ull * HZ * lpj) >> 32);
 }
 EXPORT_SYMBOL(__udelay);
 
@@ -51,6 +51,6 @@ void __ndelay(unsigned long ns)
 {
         unsigned int lpj = current_cpu_data.udelay_val;
 
-        __delay((us * 0x00000005 * HZ * lpj) >> 32);
+        __delay((ns * 0x00000005ull * HZ * lpj) >> 32);
 }
 EXPORT_SYMBOL(__ndelay);
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c
index 881ecbc1fa23..0cea932f1241 100644
--- a/arch/mips/mipssim/sim_time.c
+++ b/arch/mips/mipssim/sim_time.c
@@ -91,6 +91,7 @@ unsigned __cpuinit get_c0_compare_int(void)
                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
         } else {
 #endif
+               {
                 if (cpu_has_vint)
                         set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index d7ec95522292..f0e435599707 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -8,6 +8,7 @@ obj-y				+= cache.o dma-default.o extable.o fault.o \
 obj-$(CONFIG_32BIT)             += ioremap.o pgtable-32.o
 obj-$(CONFIG_64BIT)             += pgtable-64.o
 obj-$(CONFIG_HIGHMEM)           += highmem.o
+obj-$(CONFIG_HUGETLB_PAGE)      += hugetlbpage.o
 
 obj-$(CONFIG_CPU_LOONGSON2)     += c-r4k.o cex-gen.o tlb-r4k.o
 obj-$(CONFIG_CPU_MIPS32)        += c-r4k.o cex-gen.o tlb-r4k.o
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 44d01a0a8490..b165cdcb2818 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -8,6 +8,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/mm.h>
 #include <linux/bitops.h>
 #include <linux/cpu.h>
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 5500c20c79ae..54e5f7b9f440 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/mm.h>
 
 #include <asm/page.h>
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 171951d2305b..6721ee2b1e8b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/linkage.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/bitops.h>
@@ -100,6 +101,12 @@ static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
         blast_dcache32_page(addr);
 }
 
+static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
+{
+        R4600_HIT_CACHEOP_WAR_IMPL;
+        blast_dcache64_page(addr);
+}
+
 static void __cpuinit r4k_blast_dcache_page_setup(void)
 {
         unsigned long  dc_lsize = cpu_dcache_line_size();
@@ -110,6 +117,8 @@ static void __cpuinit r4k_blast_dcache_page_setup(void)
                 r4k_blast_dcache_page = blast_dcache16_page;
         else if (dc_lsize == 32)
                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
+        else if (dc_lsize == 64)
+                r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 }
 
 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
@@ -124,6 +133,8 @@ static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
         else if (dc_lsize == 32)
                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
+        else if (dc_lsize == 64)
+                r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 }
 
 static void (* r4k_blast_dcache)(void);
@@ -138,6 +149,8 @@ static void __cpuinit r4k_blast_dcache_setup(void)
                 r4k_blast_dcache = blast_dcache16;
         else if (dc_lsize == 32)
                 r4k_blast_dcache = blast_dcache32;
+        else if (dc_lsize == 64)
+                r4k_blast_dcache = blast_dcache64;
 }
 
 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index f7c8f9ce39c1..6515b4418714 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/mm.h>
 
 #include <asm/cacheops.h>
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 4fdb7f5216b9..7e48e76148aa 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -20,9 +20,10 @@
 
 #include <dma-coherence.h>
 
-static inline unsigned long dma_addr_to_virt(dma_addr_t dma_addr)
+static inline unsigned long dma_addr_to_virt(struct device *dev,
+        dma_addr_t dma_addr)
 {
-        unsigned long addr = plat_dma_addr_to_phys(dma_addr);
+        unsigned long addr = plat_dma_addr_to_phys(dev, dma_addr);
 
         return (unsigned long)phys_to_virt(addr);
 }
@@ -111,7 +112,7 @@ EXPORT_SYMBOL(dma_alloc_coherent);
 void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
         dma_addr_t dma_handle)
 {
-        plat_unmap_dma_mem(dev, dma_handle);
+        plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
         free_pages((unsigned long) vaddr, get_order(size));
 }
 
@@ -122,7 +123,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
 {
         unsigned long addr = (unsigned long) vaddr;
 
-        plat_unmap_dma_mem(dev, dma_handle);
+        plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
 
         if (!plat_device_is_coherent(dev))
                 addr = CAC_ADDR(addr);
@@ -170,10 +171,10 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
         enum dma_data_direction direction)
 {
         if (cpu_is_noncoherent_r10000(dev))
-                __dma_sync(dma_addr_to_virt(dma_addr), size,
+                __dma_sync(dma_addr_to_virt(dev, dma_addr), size,
                            direction);
 
-        plat_unmap_dma_mem(dev, dma_addr);
+        plat_unmap_dma_mem(dev, dma_addr, size, direction);
 }
 
 EXPORT_SYMBOL(dma_unmap_single);
@@ -232,7 +233,7 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
                         if (addr)
                                 __dma_sync(addr, sg->length, direction);
                 }
-                plat_unmap_dma_mem(dev, sg->dma_address);
+                plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction);
         }
 }
 
@@ -246,7 +247,7 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
         if (cpu_is_noncoherent_r10000(dev)) {
                 unsigned long addr;
 
-                addr = dma_addr_to_virt(dma_handle);
+                addr = dma_addr_to_virt(dev, dma_handle);
                 __dma_sync(addr, size, direction);
         }
 }
@@ -262,7 +263,7 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
         if (!plat_device_is_coherent(dev)) {
                 unsigned long addr;
 
-                addr = dma_addr_to_virt(dma_handle);
+                addr = dma_addr_to_virt(dev, dma_handle);
                 __dma_sync(addr, size, direction);
         }
 }
@@ -277,7 +278,7 @@ void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
         if (cpu_is_noncoherent_r10000(dev)) {
                 unsigned long addr;
 
-                addr = dma_addr_to_virt(dma_handle);
+                addr = dma_addr_to_virt(dev, dma_handle);
                 __dma_sync(addr + offset, size, direction);
         }
 }
@@ -293,7 +294,7 @@ void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
         if (!plat_device_is_coherent(dev)) {
                 unsigned long addr;
 
-                addr = dma_addr_to_virt(dma_handle);
+                addr = dma_addr_to_virt(dev, dma_handle);
                 __dma_sync(addr + offset, size, direction);
         }
 }
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 55767ad9f00e..6751ce9ede9e 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -102,7 +102,7 @@ good_area:
          * make sure we exit gracefully rather than endlessly redo
          * the fault.
          */
-        fault = handle_mm_fault(mm, vma, address, write);
+        fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
         if (unlikely(fault & VM_FAULT_ERROR)) {
                 if (fault & VM_FAULT_OOM)
                         goto out_of_memory;
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index 2b1309b2580a..e274fda329f4 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -1,5 +1,6 @@
 #include <linux/module.h>
 #include <linux/highmem.h>
+#include <linux/smp.h>
 #include <asm/fixmap.h>
 #include <asm/tlbflush.h>
 
diff --git a/arch/mips/mm/hugetlbpage.c b/arch/mips/mm/hugetlbpage.c
new file mode 100644
index 000000000000..471c09aa1614
--- /dev/null
+++ b/arch/mips/mm/hugetlbpage.c
@@ -0,0 +1,101 @@
+/*
+ * MIPS Huge TLB Page Support for Kernel.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>
+ * Copyright 2005, Embedded Alley Solutions, Inc.
+ * Matt Porter <mporter@embeddedalley.com>
+ * Copyright (C) 2008, 2009 Cavium Networks, Inc.
+ */
+
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/hugetlb.h>
+#include <linux/pagemap.h>
+#include <linux/smp_lock.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/sysctl.h>
+#include <asm/mman.h>
+#include <asm/tlb.h>
+#include <asm/tlbflush.h>
+
+pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr,
+                      unsigned long sz)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pte_t *pte = NULL;
+
+        pgd = pgd_offset(mm, addr);
+        pud = pud_alloc(mm, pgd, addr);
+        if (pud)
+                pte = (pte_t *)pmd_alloc(mm, pud, addr);
+
+        return pte;
+}
+
+pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd = NULL;
+
+        pgd = pgd_offset(mm, addr);
+        if (pgd_present(*pgd)) {
+                pud = pud_offset(pgd, addr);
+                if (pud_present(*pud))
+                        pmd = pmd_offset(pud, addr);
+        }
+        return (pte_t *) pmd;
+}
+
+int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
+{
+        return 0;
+}
+
+/*
+ * This function checks for proper alignment of input addr and len parameters.
+ */
+int is_aligned_hugepage_range(unsigned long addr, unsigned long len)
+{
+        if (len & ~HPAGE_MASK)
+                return -EINVAL;
+        if (addr & ~HPAGE_MASK)
+                return -EINVAL;
+        return 0;
+}
+
+struct page *
+follow_huge_addr(struct mm_struct *mm, unsigned long address, int write)
+{
+        return ERR_PTR(-EINVAL);
+}
+
+int pmd_huge(pmd_t pmd)
+{
+        return (pmd_val(pmd) & _PAGE_HUGE) != 0;
+}
+
+int pud_huge(pud_t pud)
+{
+        return (pud_val(pud) & _PAGE_HUGE) != 0;
+}
+
+struct page *
+follow_huge_pmd(struct mm_struct *mm, unsigned long address,
+                pmd_t *pmd, int write)
+{
+        struct page *page;
+
+        page = pte_page(*(pte_t *)pmd);
+        if (page)
+                page += ((address & ~HPAGE_MASK) >> PAGE_SHIFT);
+        return page;
+}
+
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index c5511294a9ee..0e820508ff23 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -13,6 +13,7 @@
 #include <linux/module.h>
 #include <linux/signal.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/string.h>
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 48060c635acd..f5c73754d664 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -10,6 +10,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/proc_fs.h>
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index 1c0048a6f5cf..0f5ab236ab69 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/mm.h>
 
 #include <asm/page.h>
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 892be426787c..cee502caf398 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -10,7 +10,9 @@
  */
 #include <linux/init.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/mm.h>
+#include <linux/hugetlb.h>
 
 #include <asm/cpu.h>
 #include <asm/bootinfo.h>
@@ -295,21 +297,41 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
         pudp = pud_offset(pgdp, address);
         pmdp = pmd_offset(pudp, address);
         idx = read_c0_index();
-        ptep = pte_offset_map(pmdp, address);
+#ifdef CONFIG_HUGETLB_PAGE
+        /* this could be a huge page  */
+        if (pmd_huge(*pmdp)) {
+                unsigned long lo;
+                write_c0_pagemask(PM_HUGE_MASK);
+                ptep = (pte_t *)pmdp;
+                lo = pte_val(*ptep) >> 6;
+                write_c0_entrylo0(lo);
+                write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
+
+                mtc0_tlbw_hazard();
+                if (idx < 0)
+                        tlb_write_random();
+                else
+                        tlb_write_indexed();
+                write_c0_pagemask(PM_DEFAULT_MASK);
+        } else
+#endif
+        {
+                ptep = pte_offset_map(pmdp, address);
 
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-        write_c0_entrylo0(ptep->pte_high);
-        ptep++;
-        write_c0_entrylo1(ptep->pte_high);
+                write_c0_entrylo0(ptep->pte_high);
+                ptep++;
+                write_c0_entrylo1(ptep->pte_high);
 #else
-        write_c0_entrylo0(pte_val(*ptep++) >> 6);
-        write_c0_entrylo1(pte_val(*ptep) >> 6);
+                write_c0_entrylo0(pte_val(*ptep++) >> 6);
+                write_c0_entrylo1(pte_val(*ptep) >> 6);
 #endif
-        mtc0_tlbw_hazard();
-        if (idx < 0)
-                tlb_write_random();
-        else
-                tlb_write_indexed();
+                mtc0_tlbw_hazard();
+                if (idx < 0)
+                        tlb_write_random();
+                else
+                        tlb_write_indexed();
+        }
         tlbw_use_hazard();
         FLUSH_ITLB_VM(vma);
         EXIT_CRITICAL(flags);
diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c
index 4ec95cc2df2f..2b82f23df1a1 100644
--- a/arch/mips/mm/tlb-r8k.c
+++ b/arch/mips/mm/tlb-r8k.c
@@ -10,6 +10,7 @@
  */
 #include <linux/init.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/mm.h>
 
 #include <asm/cpu.h>
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 0615b62efd6d..9a17bf8395df 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -6,8 +6,9 @@
  * Synthesize TLB refill handlers at runtime.
  *
  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
- * Copyright (C) 2005, 2007  Maciej W. Rozycki
+ * Copyright (C) 2005, 2007, 2008, 2009  Maciej W. Rozycki
  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2008, 2009 Cavium Networks, Inc.
  *
  * ... and the days got worse and worse and now you see
  * I've gone completly out of my mind.
@@ -19,8 +20,10 @@
  * (Condolences to Napoleon XIV)
  */
 
+#include <linux/bug.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/smp.h>
 #include <linux/string.h>
 #include <linux/init.h>
 
@@ -82,6 +85,9 @@ enum label_id {
         label_nopage_tlbm,
         label_smp_pgtable_change,
         label_r3000_write_probe_fail,
+#ifdef CONFIG_HUGETLB_PAGE
+        label_tlb_huge_update,
+#endif
 };
 
 UASM_L_LA(_second_part)
@@ -98,6 +104,9 @@ UASM_L_LA(_nopage_tlbs)
 UASM_L_LA(_nopage_tlbm)
 UASM_L_LA(_smp_pgtable_change)
 UASM_L_LA(_r3000_write_probe_fail)
+#ifdef CONFIG_HUGETLB_PAGE
+UASM_L_LA(_tlb_huge_update)
+#endif
 
 /*
  * For debug purposes.
@@ -125,6 +134,7 @@ static inline void dump_handler(const u32 *handler, int count)
 #define C0_TCBIND       2, 2
 #define C0_ENTRYLO1     3, 0
 #define C0_CONTEXT      4, 0
+#define C0_PAGEMASK     5, 0
 #define C0_BADVADDR     8, 0
 #define C0_ENTRYHI      10, 0
 #define C0_EPC          14, 0
@@ -258,7 +268,8 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         }
 
         if (cpu_has_mips_r2) {
-                uasm_i_ehb(p);
+                if (cpu_has_mips_r2_exec_hazard)
+                        uasm_i_ehb(p);
                 tlbw(p);
                 return;
         }
@@ -310,7 +321,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         case CPU_BCM3302:
         case CPU_BCM4710:
         case CPU_LOONGSON2:
-        case CPU_CAVIUM_OCTEON:
         case CPU_R5500:
                 if (m4kc_tlbp_war())
                         uasm_i_nop(p);
@@ -382,6 +392,98 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         }
 }
 
+#ifdef CONFIG_HUGETLB_PAGE
+static __cpuinit void build_huge_tlb_write_entry(u32 **p,
+                                                 struct uasm_label **l,
+                                                 struct uasm_reloc **r,
+                                                 unsigned int tmp,
+                                                 enum tlb_write_entry wmode)
+{
+        /* Set huge page tlb entry size */
+        uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
+        uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
+        uasm_i_mtc0(p, tmp, C0_PAGEMASK);
+
+        build_tlb_write_entry(p, l, r, wmode);
+
+        /* Reset default page size */
+        if (PM_DEFAULT_MASK >> 16) {
+                uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
+                uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
+                uasm_il_b(p, r, label_leave);
+                uasm_i_mtc0(p, tmp, C0_PAGEMASK);
+        } else if (PM_DEFAULT_MASK) {
+                uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
+                uasm_il_b(p, r, label_leave);
+                uasm_i_mtc0(p, tmp, C0_PAGEMASK);
+        } else {
+                uasm_il_b(p, r, label_leave);
+                uasm_i_mtc0(p, 0, C0_PAGEMASK);
+        }
+}
+
+/*
+ * Check if Huge PTE is present, if so then jump to LABEL.
+ */
+static void __cpuinit
+build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
+                unsigned int pmd, int lid)
+{
+        UASM_i_LW(p, tmp, 0, pmd);
+        uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
+        uasm_il_bnez(p, r, tmp, lid);
+}
+
+static __cpuinit void build_huge_update_entries(u32 **p,
+                                                unsigned int pte,
+                                                unsigned int tmp)
+{
+        int small_sequence;
+
+        /*
+         * A huge PTE describes an area the size of the
+         * configured huge page size. This is twice the
+         * of the large TLB entry size we intend to use.
+         * A TLB entry half the size of the configured
+         * huge page size is configured into entrylo0
+         * and entrylo1 to cover the contiguous huge PTE
+         * address space.
+         */
+        small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
+
+        /* We can clobber tmp.  It isn't used after this.*/
+        if (!small_sequence)
+                uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
+
+        UASM_i_SRL(p, pte, pte, 6); /* convert to entrylo */
+        uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* load it */
+        /* convert to entrylo1 */
+        if (small_sequence)
+                UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
+        else
+                UASM_i_ADDU(p, pte, pte, tmp);
+
+        uasm_i_mtc0(p, pte, C0_ENTRYLO1); /* load it */
+}
+
+static __cpuinit void build_huge_handler_tail(u32 **p,
+                                              struct uasm_reloc **r,
+                                              struct uasm_label **l,
+                                              unsigned int pte,
+                                              unsigned int ptr)
+{
+#ifdef CONFIG_SMP
+        UASM_i_SC(p, pte, 0, ptr);
+        uasm_il_beqz(p, r, pte, label_tlb_huge_update);
+        UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
+#else
+        UASM_i_SW(p, pte, 0, ptr);
+#endif
+        build_huge_update_entries(p, pte, ptr);
+        build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed);
+}
+#endif /* CONFIG_HUGETLB_PAGE */
+
 #ifdef CONFIG_64BIT
 /*
  * TMP and PTR are scratch.
@@ -649,6 +751,14 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
 #endif
 }
 
+/*
+ * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
+ * because EXL == 0.  If we wrap, we can also use the 32 instruction
+ * slots before the XTLB refill exception handler which belong to the
+ * unused TLB refill exception.
+ */
+#define MIPS64_REFILL_INSNS 32
+
 static void __cpuinit build_r4000_tlb_refill_handler(void)
 {
         u32 *p = tlb_handler;
@@ -680,12 +790,23 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
         build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
 #endif
 
+#ifdef CONFIG_HUGETLB_PAGE
+        build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
+#endif
+
         build_get_ptep(&p, K0, K1);
         build_update_entries(&p, K0, K1);
         build_tlb_write_entry(&p, &l, &r, tlb_random);
         uasm_l_leave(&l, p);
         uasm_i_eret(&p); /* return from trap */
 
+#ifdef CONFIG_HUGETLB_PAGE
+        uasm_l_tlb_huge_update(&l, p);
+        UASM_i_LW(&p, K0, 0, K1);
+        build_huge_update_entries(&p, K0, K1);
+        build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random);
+#endif
+
 #ifdef CONFIG_64BIT
         build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
 #endif
@@ -702,9 +823,10 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
         if ((p - tlb_handler) > 64)
                 panic("TLB refill handler space exceeded");
 #else
-        if (((p - tlb_handler) > 63)
-            || (((p - tlb_handler) > 61)
-                && uasm_insn_has_bdelay(relocs, tlb_handler + 29)))
+        if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
+            || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
+                && uasm_insn_has_bdelay(relocs,
+                                        tlb_handler + MIPS64_REFILL_INSNS - 3)))
                 panic("TLB refill handler space exceeded");
 #endif
 
@@ -717,39 +839,74 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
         uasm_copy_handler(relocs, labels, tlb_handler, p, f);
         final_len = p - tlb_handler;
 #else /* CONFIG_64BIT */
-        f = final_handler + 32;
-        if ((p - tlb_handler) <= 32) {
+        f = final_handler + MIPS64_REFILL_INSNS;
+        if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
                 /* Just copy the handler. */
                 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
                 final_len = p - tlb_handler;
         } else {
-                u32 *split = tlb_handler + 30;
+#if defined(CONFIG_HUGETLB_PAGE)
+                const enum label_id ls = label_tlb_huge_update;
+#elif defined(MODULE_START)
+                const enum label_id ls = label_module_alloc;
+#else
+                const enum label_id ls = label_vmalloc;
+#endif
+                u32 *split;
+                int ov = 0;
+                int i;
+
+                for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
+                        ;
+                BUG_ON(i == ARRAY_SIZE(labels));
+                split = labels[i].addr;
 
                 /*
-                 * Find the split point.
+                 * See if we have overflown one way or the other.
                  */
-                if (uasm_insn_has_bdelay(relocs, split - 1))
-                        split--;
-
+                if (split > tlb_handler + MIPS64_REFILL_INSNS ||
+                    split < p - MIPS64_REFILL_INSNS)
+                        ov = 1;
+
+                if (ov) {
+                        /*
+                         * Split two instructions before the end.  One
+                         * for the branch and one for the instruction
+                         * in the delay slot.
+                         */
+                        split = tlb_handler + MIPS64_REFILL_INSNS - 2;
+
+                        /*
+                         * If the branch would fall in a delay slot,
+                         * we must back up an additional instruction
+                         * so that it is no longer in a delay slot.
+                         */
+                        if (uasm_insn_has_bdelay(relocs, split - 1))
+                                split--;
+                }
                 /* Copy first part of the handler. */
                 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
                 f += split - tlb_handler;
 
-                /* Insert branch. */
-                uasm_l_split(&l, final_handler);
-                uasm_il_b(&f, &r, label_split);
-                if (uasm_insn_has_bdelay(relocs, split))
-                        uasm_i_nop(&f);
-                else {
-                        uasm_copy_handler(relocs, labels, split, split + 1, f);
-                        uasm_move_labels(labels, f, f + 1, -1);
-                        f++;
-                        split++;
+                if (ov) {
+                        /* Insert branch. */
+                        uasm_l_split(&l, final_handler);
+                        uasm_il_b(&f, &r, label_split);
+                        if (uasm_insn_has_bdelay(relocs, split))
+                                uasm_i_nop(&f);
+                        else {
+                                uasm_copy_handler(relocs, labels,
+                                                  split, split + 1, f);
+                                uasm_move_labels(labels, f, f + 1, -1);
+                                f++;
+                                split++;
+                        }
                 }
 
                 /* Copy the rest of the handler. */
                 uasm_copy_handler(relocs, labels, split, p, final_handler);
-                final_len = (f - (final_handler + 32)) + (p - split);
+                final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
+                            (p - split);
         }
 #endif /* CONFIG_64BIT */
 
@@ -782,7 +939,7 @@ u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
 u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
 
 static void __cpuinit
-iPTE_LW(u32 **p, struct uasm_label **l, unsigned int pte, unsigned int ptr)
+iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
 {
 #ifdef CONFIG_SMP
 # ifdef CONFIG_64BIT_PHYS_ADDR
@@ -862,13 +1019,13 @@ iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
  * with it's original value.
  */
 static void __cpuinit
-build_pte_present(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
+build_pte_present(u32 **p, struct uasm_reloc **r,
                   unsigned int pte, unsigned int ptr, enum label_id lid)
 {
         uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
         uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
         uasm_il_bnez(p, r, pte, lid);
-        iPTE_LW(p, l, pte, ptr);
+        iPTE_LW(p, pte, ptr);
 }
 
 /* Make PTE valid, store result in PTR. */
@@ -886,13 +1043,13 @@ build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
  * restore PTE with value from PTR when done.
  */
 static void __cpuinit
-build_pte_writable(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
+build_pte_writable(u32 **p, struct uasm_reloc **r,
                    unsigned int pte, unsigned int ptr, enum label_id lid)
 {
         uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
         uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
         uasm_il_bnez(p, r, pte, lid);
-        iPTE_LW(p, l, pte, ptr);
+        iPTE_LW(p, pte, ptr);
 }
 
 /* Make PTE writable, update software status bits as well, then store
@@ -913,12 +1070,12 @@ build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
  * restore PTE with value from PTR when done.
  */
 static void __cpuinit
-build_pte_modifiable(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
+build_pte_modifiable(u32 **p, struct uasm_reloc **r,
                      unsigned int pte, unsigned int ptr, enum label_id lid)
 {
         uasm_i_andi(p, pte, pte, _PAGE_WRITE);
         uasm_il_beqz(p, r, pte, lid);
-        iPTE_LW(p, l, pte, ptr);
+        iPTE_LW(p, pte, ptr);
 }
 
 /*
@@ -994,7 +1151,7 @@ static void __cpuinit build_r3000_tlb_load_handler(void)
         memset(relocs, 0, sizeof(relocs));
 
         build_r3000_tlbchange_handler_head(&p, K0, K1);
-        build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
+        build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
         uasm_i_nop(&p); /* load delay */
         build_make_valid(&p, &r, K0, K1);
         build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
@@ -1024,7 +1181,7 @@ static void __cpuinit build_r3000_tlb_store_handler(void)
         memset(relocs, 0, sizeof(relocs));
 
         build_r3000_tlbchange_handler_head(&p, K0, K1);
-        build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
+        build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
         uasm_i_nop(&p); /* load delay */
         build_make_write(&p, &r, K0, K1);
         build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
@@ -1054,7 +1211,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
         memset(relocs, 0, sizeof(relocs));
 
         build_r3000_tlbchange_handler_head(&p, K0, K1);
-        build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
+        build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
         uasm_i_nop(&p); /* load delay */
         build_make_write(&p, &r, K0, K1);
         build_r3000_pte_reload_tlbwi(&p, K0, K1);
@@ -1087,6 +1244,15 @@ build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
         build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
 #endif
 
+#ifdef CONFIG_HUGETLB_PAGE
+        /*
+         * For huge tlb entries, pmd doesn't contain an address but
+         * instead contains the tlb pte. Check the PAGE_HUGE bit and
+         * see if we need to jump to huge tlb processing.
+         */
+        build_is_huge_pte(p, r, pte, ptr, label_tlb_huge_update);
+#endif
+
         UASM_i_MFC0(p, pte, C0_BADVADDR);
         UASM_i_LW(p, ptr, 0, ptr);
         UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
@@ -1096,7 +1262,7 @@ build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
 #ifdef CONFIG_SMP
         uasm_l_smp_pgtable_change(l, *p);
 #endif
-        iPTE_LW(p, l, pte, ptr); /* get even pte */
+        iPTE_LW(p, pte, ptr); /* get even pte */
         if (!m4kc_tlbp_war())
                 build_tlb_probe_entry(p);
 }
@@ -1138,12 +1304,25 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
         }
 
         build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
-        build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
+        build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
         if (m4kc_tlbp_war())
                 build_tlb_probe_entry(&p);
         build_make_valid(&p, &r, K0, K1);
         build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
 
+#ifdef CONFIG_HUGETLB_PAGE
+        /*
+         * This is the entry point when build_r4000_tlbchange_handler_head
+         * spots a huge page.
+         */
+        uasm_l_tlb_huge_update(&l, p);
+        iPTE_LW(&p, K0, K1);
+        build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
+        build_tlb_probe_entry(&p);
+        uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID));
+        build_huge_handler_tail(&p, &r, &l, K0, K1);
+#endif
+
         uasm_l_nopage_tlbl(&l, p);
         uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
         uasm_i_nop(&p);
@@ -1169,12 +1348,26 @@ static void __cpuinit build_r4000_tlb_store_handler(void)
         memset(relocs, 0, sizeof(relocs));
 
         build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
-        build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
+        build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
         if (m4kc_tlbp_war())
                 build_tlb_probe_entry(&p);
         build_make_write(&p, &r, K0, K1);
         build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
 
+#ifdef CONFIG_HUGETLB_PAGE
+        /*
+         * This is the entry point when
+         * build_r4000_tlbchange_handler_head spots a huge page.
+         */
+        uasm_l_tlb_huge_update(&l, p);
+        iPTE_LW(&p, K0, K1);
+        build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
+        build_tlb_probe_entry(&p);
+        uasm_i_ori(&p, K0, K0,
+                   _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
+        build_huge_handler_tail(&p, &r, &l, K0, K1);
+#endif
+
         uasm_l_nopage_tlbs(&l, p);
         uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
         uasm_i_nop(&p);
@@ -1200,13 +1393,27 @@ static void __cpuinit build_r4000_tlb_modify_handler(void)
         memset(relocs, 0, sizeof(relocs));
 
         build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
-        build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
+        build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
         if (m4kc_tlbp_war())
                 build_tlb_probe_entry(&p);
         /* Present and writable bits set, set accessed and dirty bits. */
         build_make_write(&p, &r, K0, K1);
         build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
 
+#ifdef CONFIG_HUGETLB_PAGE
+        /*
+         * This is the entry point when
+         * build_r4000_tlbchange_handler_head spots a huge page.
+         */
+        uasm_l_tlb_huge_update(&l, p);
+        iPTE_LW(&p, K0, K1);
+        build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
+        build_tlb_probe_entry(&p);
+        uasm_i_ori(&p, K0, K0,
+                   _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
+        build_huge_handler_tail(&p, &r, &l, K0, K1);
+#endif
+
         uasm_l_nopage_tlbm(&l, p);
         uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
         uasm_i_nop(&p);
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index ea176113fea9..b4eaf137e4a7 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -24,6 +24,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index dda6f2058665..a0e726eb039a 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -10,6 +10,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/smp.h>
 #include <asm/sn/arch.h>
 #include <asm/pci/bridge.h>
 #include <asm/paccess.h>
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index f78c29b68d77..8ace27716232 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -1,5 +1,6 @@
 #include <linux/linkage.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 
 #include <asm/pmon.h>
 #include <asm/titan_dep.h>
diff --git a/arch/mips/power/Makefile b/arch/mips/power/Makefile
new file mode 100644
index 000000000000..73d56b87cb9b
--- /dev/null
+++ b/arch/mips/power/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_HIBERNATION) += cpu.o hibernate.o
diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c
new file mode 100644
index 000000000000..7995df45dc8d
--- /dev/null
+++ b/arch/mips/power/cpu.c
@@ -0,0 +1,43 @@
+/*
+ * Suspend support specific for mips.
+ *
+ * Licensed under the GPLv2
+ *
+ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Author: Hu Hongbing <huhb@lemote.com>
+ *         Wu Zhangjin <wuzj@lemote.com>
+ */
+#include <asm/suspend.h>
+#include <asm/fpu.h>
+#include <asm/dsp.h>
+
+static u32 saved_status;
+struct pt_regs saved_regs;
+
+void save_processor_state(void)
+{
+        saved_status = read_c0_status();
+
+        if (is_fpu_owner())
+                save_fp(current);
+        if (cpu_has_dsp)
+                save_dsp(current);
+}
+
+void restore_processor_state(void)
+{
+        write_c0_status(saved_status);
+
+        if (is_fpu_owner())
+                restore_fp(current);
+        if (cpu_has_dsp)
+                restore_dsp(current);
+}
+
+int pfn_is_nosave(unsigned long pfn)
+{
+        unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin));
+        unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end));
+
+        return  (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
+}
diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
new file mode 100644
index 000000000000..4b8174b382d7
--- /dev/null
+++ b/arch/mips/power/hibernate.S
@@ -0,0 +1,61 @@
+/*
+ * Hibernation support specific for mips - temporary page tables
+ *
+ * Licensed under the GPLv2
+ *
+ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Author: Hu Hongbing <huhb@lemote.com>
+ *         Wu Zhangjin <wuzj@lemote.com>
+ */
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+#include <asm/asm.h>
+
+.text
+LEAF(swsusp_arch_suspend)
+        PTR_LA t0, saved_regs
+        PTR_S ra, PT_R31(t0)
+        PTR_S sp, PT_R29(t0)
+        PTR_S fp, PT_R30(t0)
+        PTR_S gp, PT_R28(t0)
+        PTR_S s0, PT_R16(t0)
+        PTR_S s1, PT_R17(t0)
+        PTR_S s2, PT_R18(t0)
+        PTR_S s3, PT_R19(t0)
+        PTR_S s4, PT_R20(t0)
+        PTR_S s5, PT_R21(t0)
+        PTR_S s6, PT_R22(t0)
+        PTR_S s7, PT_R23(t0)
+        j swsusp_save
+END(swsusp_arch_suspend)
+
+LEAF(swsusp_arch_resume)
+        PTR_L t0, restore_pblist
+0:
+        PTR_L t1, PBE_ADDRESS(t0)   /* source */
+        PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */
+        PTR_ADDIU t3, t1, _PAGE_SIZE
+1:
+        REG_L t8, (t1)
+        REG_S t8, (t2)
+        PTR_ADDIU t1, t1, SZREG
+        PTR_ADDIU t2, t2, SZREG
+        bne t1, t3, 1b
+        PTR_L t0, PBE_NEXT(t0)
+        bnez t0, 0b
+        PTR_LA t0, saved_regs
+        PTR_L ra, PT_R31(t0)
+        PTR_L sp, PT_R29(t0)
+        PTR_L fp, PT_R30(t0)
+        PTR_L gp, PT_R28(t0)
+        PTR_L s0, PT_R16(t0)
+        PTR_L s1, PT_R17(t0)
+        PTR_L s2, PT_R18(t0)
+        PTR_L s3, PT_R19(t0)
+        PTR_L s4, PT_R20(t0)
+        PTR_L s5, PT_R21(t0)
+        PTR_L s6, PT_R22(t0)
+        PTR_L s7, PT_R23(t0)
+        PTR_LI v0, 0x0
+        jr ra
+END(swsusp_arch_resume)
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index 53eeb5e7bc5b..f07882029a90 100644
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -151,7 +151,8 @@ static void rb532_disable_irq(unsigned int irq_nr)
                 mask |= intr_bit;
                 WRITE_MASK(addr, mask);
 
-                if (group == GPIO_MAPPED_IRQ_GROUP)
+                /* There is a maximum of 14 GPIO interrupts */
+                if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13))
                         rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
 
                 /*
@@ -174,7 +175,7 @@ static int rb532_set_type(unsigned int irq_nr, unsigned type)
         int gpio = irq_nr - GPIO_MAPPED_IRQ_BASE;
         int group = irq_to_group(irq_nr);
 
-        if (group != GPIO_MAPPED_IRQ_GROUP)
+        if (group != GPIO_MAPPED_IRQ_GROUP || irq_nr > (GROUP4_IRQ_BASE + 13))
                 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
 
         switch (type) {
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index 4a500e8cd3cc..51d3a4f2d7e1 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -9,6 +9,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/cpumask.h>
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 1bb692a3b319..c1c8e40d65d6 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -18,6 +18,7 @@
 #include <linux/ioport.h>
 #include <linux/timex.h>
 #include <linux/slab.h>
+#include <linux/smp.h>
 #include <linux/random.h>
 #include <linux/kernel.h>
 #include <linux/kernel_stat.h>
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index f10a7cd64f7e..6d0e59ffba2e 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -10,6 +10,7 @@
 #include <linux/interrupt.h>
 #include <linux/kernel_stat.h>
 #include <linux/param.h>
+#include <linux/smp.h>
 #include <linux/time.h>
 #include <linux/timex.h>
 #include <linux/mm.h>
diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c
index 6ae64e8dfc40..5e871e75a8d9 100644
--- a/arch/mips/sgi-ip27/ip27-xtalk.c
+++ b/arch/mips/sgi-ip27/ip27-xtalk.c
@@ -9,6 +9,7 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/smp.h>
 #include <asm/sn/types.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/hub.h>
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index 366b19d33f77..3e639bda43f7 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -75,6 +75,8 @@ config SIBYTE_SB1xxx_SOC
         select SWAP_IO_SPACE
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_64BIT_KERNEL
+        select CFE
+        select SYS_HAS_EARLY_PRINTK
 
 choice
         prompt "SiByte SOC Stepping"
@@ -128,13 +130,6 @@ config SIBYTE_ENABLE_LDT_IF_PCI
         bool
         select SIBYTE_HAS_LDT if PCI
 
-config SIMULATION
-        bool "Running under simulation"
-        depends on SIBYTE_SB1xxx_SOC
-        help
-          Build a kernel suitable for running under the GDB simulator.
-          Primarily adjusts the kernel's notion of time.
-
 config SB1_CEX_ALWAYS_FATAL
         bool "All cache exceptions considered fatal (no recovery attempted)"
         depends on SIBYTE_SB1xxx_SOC
@@ -143,34 +138,14 @@ config SB1_CERR_STALL
         bool "Stall (rather than panic) on fatal cache error"
         depends on SIBYTE_SB1xxx_SOC
 
-config SIBYTE_CFE
-        bool "Booting from CFE"
-        depends on SIBYTE_SB1xxx_SOC
-        select CFE
-        select SYS_HAS_EARLY_PRINTK
-        help
-          Make use of the CFE API for enumerating available memory,
-          controlling secondary CPUs, and possibly console output.
-
 config SIBYTE_CFE_CONSOLE
         bool "Use firmware console"
-        depends on SIBYTE_CFE
+        depends on SIBYTE_SB1xxx_SOC
         help
           Use the CFE API's console write routines during boot.  Other console
           options (VT console, sb1250 duart console, etc.) should not be
           configured.
 
-config SIBYTE_STANDALONE
-        bool
-        depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
-        select SYS_HAS_EARLY_PRINTK
-        default y
-
-config SIBYTE_STANDALONE_RAM_SIZE
-        int "Memory size (in megabytes)"
-        depends on SIBYTE_STANDALONE
-        default "32"
-
 config SIBYTE_BUS_WATCHER
         bool "Support for Bus Watcher statistics"
         depends on SIBYTE_SB1xxx_SOC
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 690de06bde90..ba59839a021e 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/linkage.h>
 #include <linux/interrupt.h>
+#include <linux/smp.h>
 #include <linux/spinlock.h>
 #include <linux/mm.h>
 #include <linux/slab.h>
diff --git a/arch/mips/sibyte/cfe/Makefile b/arch/mips/sibyte/cfe/Makefile
deleted file mode 100644
index 02b32e142adf..000000000000
--- a/arch/mips/sibyte/cfe/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-lib-y                                   = setup.o
-lib-$(CONFIG_SIBYTE_CFE_CONSOLE)        += console.o
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile
index 48a91b9e5870..4f659837c7c6 100644
--- a/arch/mips/sibyte/common/Makefile
+++ b/arch/mips/sibyte/common/Makefile
@@ -1,5 +1,5 @@
-obj-y :=
-
+obj-y := cfe.o
+obj-$(CONFIG_SIBYTE_CFE_CONSOLE)        += cfe_console.o
 obj-$(CONFIG_SIBYTE_TBPROF)             += sb_tbprof.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/common/cfe.c
index eb5396cf81bb..eb5396cf81bb 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/common/cfe.c
diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/common/cfe_console.c
index 81e3d54376e9..1ad2da103fe9 100644
--- a/arch/mips/sibyte/cfe/console.c
+++ b/arch/mips/sibyte/common/cfe_console.c
@@ -51,12 +51,13 @@ static int cfe_console_setup(struct console *cons, char *str)
                         setleds("u0cn");
                 } else if (!strcmp(consdev, "uart1")) {
                         setleds("u1cn");
+                } else
 #endif
 #ifdef CONFIG_VGA_CONSOLE
-                } else if (!strcmp(consdev, "pcconsole0")) {
-                        setleds("pccn");
-#endif
+                       if (!strcmp(consdev, "pcconsole0")) {
+                                setleds("pccn");
                 } else
+#endif
                         return -ENODEV;
         }
         return 0;
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
index 697793783a25..1896f4e77a30 100644
--- a/arch/mips/sibyte/sb1250/Makefile
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -1,7 +1,6 @@
 obj-y := setup.o irq.o time.o
 
 obj-$(CONFIG_SMP)                       += smp.o
-obj-$(CONFIG_SIBYTE_STANDALONE)         += prom.o
 obj-$(CONFIG_SIBYTE_BUS_WATCHER)        += bus_watcher.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 409dec798863..5e7f2016cceb 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -111,11 +111,6 @@ static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
 
         i = cpumask_first(mask);
 
-        if (cpumask_weight(mask) > 1) {
-                printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
-                return -1;
-        }
-
         /* Convert logical CPU to physical CPU */
         cpu = cpu_logical_map(i);
 
diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c
deleted file mode 100644
index 65b1af66b674..000000000000
--- a/arch/mips/sibyte/sb1250/prom.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (C) 2000, 2001 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/blkdev.h>
-#include <linux/bootmem.h>
-#include <linux/smp.h>
-#include <linux/initrd.h>
-#include <linux/pm.h>
-
-#include <asm/bootinfo.h>
-#include <asm/reboot.h>
-
-#define MAX_RAM_SIZE ((CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - 1)
-
-static __init void prom_meminit(void)
-{
-#ifdef CONFIG_BLK_DEV_INITRD
-        unsigned long initrd_pstart;
-        unsigned long initrd_pend;
-
-        initrd_pstart = __pa(initrd_start);
-        initrd_pend = __pa(initrd_end);
-        if (initrd_start &&
-            ((initrd_pstart > MAX_RAM_SIZE)
-             || (initrd_pend > MAX_RAM_SIZE))) {
-                panic("initrd out of addressable memory");
-        }
-
-        add_memory_region(0, initrd_pstart,
-                          BOOT_MEM_RAM);
-        add_memory_region(initrd_pstart, initrd_pend - initrd_pstart,
-                          BOOT_MEM_RESERVED);
-        add_memory_region(initrd_pend,
-                          (CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - initrd_pend,
-                          BOOT_MEM_RAM);
-#else
-        add_memory_region(0, CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024,
-                          BOOT_MEM_RAM);
-#endif
-}
-
-void prom_cpu0_exit(void *unused)
-{
-        while (1) ;
-}
-
-static void prom_linux_exit(void)
-{
-#ifdef CONFIG_SMP
-        if (smp_processor_id()) {
-                smp_call_function(prom_cpu0_exit, NULL, 1);
-        }
-#endif
-        while(1);
-}
-
-/*
- * prom_init is called just after the cpu type is determined, from setup_arch()
- */
-void __init prom_init(void)
-{
-        _machine_restart   = (void (*)(char *))prom_linux_exit;
-        _machine_halt      = prom_linux_exit;
-        pm_power_off = prom_linux_exit;
-
-        strcpy(arcs_cmdline, "root=/dev/ram0 ");
-
-        prom_meminit();
-}
-
-void __init prom_free_prom_memory(void)
-{
-        /* Not sure what I'm supposed to do here.  Nothing, I think */
-}
-
-void prom_putchar(char c)
-{
-}
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index 080c966263b7..672e45d495a9 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -136,20 +136,6 @@ void __init plat_mem_setup(void)
         if (m41t81_probe())
                 swarm_rtc_type = RTC_M4LT81;
 
-        printk("This kernel optimized for "
-#ifdef CONFIG_SIMULATION
-               "simulation"
-#else
-               "board"
-#endif
-               " runs "
-#ifdef CONFIG_SIBYTE_CFE
-               "with"
-#else
-               "without"
-#endif
-               " CFE\n");
-
 #ifdef CONFIG_VT
         screen_info = (struct screen_info) {
                 0, 0,           /* orig-x, orig-y */
diff --git a/arch/mips/sni/eisa.c b/arch/mips/sni/eisa.c
index 7396cd719900..6827feb4de96 100644
--- a/arch/mips/sni/eisa.c
+++ b/arch/mips/sni/eisa.c
@@ -38,7 +38,7 @@ int __init sni_eisa_root_init(void)
         if (!r)
                 return r;
 
-        eisa_root_dev.dev.driver_data = &eisa_bus_root;
+        dev_set_drvdata(&eisa_root_dev.dev, &eisa_bus_root);
 
         if (eisa_root_register(&eisa_bus_root)) {
                 /* A real bridge may have been registered before
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 69f5f88711cc..0d9ec1a5c24a 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -1,5 +1,6 @@
 #include <linux/types.h>
 #include <linux/interrupt.h>
+#include <linux/smp.h>
 #include <linux/time.h>
 #include <linux/clockchips.h>
 
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 0db7cf38ed8b..852ae4bb7a85 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -69,6 +69,7 @@ config SOC_TX4927
         select IRQ_TXX9
         select PCI_TX4927
         select GPIO_TXX9
+        select HAS_TXX9_ACLC
 
 config SOC_TX4938
         bool
@@ -78,6 +79,7 @@ config SOC_TX4938
         select IRQ_TXX9
         select PCI_TX4927
         select GPIO_TXX9
+        select HAS_TXX9_ACLC
 
 config SOC_TX4939
         bool
@@ -85,6 +87,7 @@ config SOC_TX4939
         select HAS_TXX9_SERIAL
         select HW_HAS_PCI
         select PCI_TX4927
+        select HAS_TXX9_ACLC
 
 config TXX9_7SEGLED
         bool
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 8a266c6a3f58..3b7d77d61ce0 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -24,6 +24,7 @@
 #include <linux/serial_core.h>
 #include <linux/mtd/physmap.h>
 #include <linux/leds.h>
+#include <linux/sysdev.h>
 #include <asm/bootinfo.h>
 #include <asm/time.h>
 #include <asm/reboot.h>
@@ -33,6 +34,7 @@
 #include <asm/txx9/pci.h>
 #include <asm/txx9tmr.h>
 #include <asm/txx9/ndfmc.h>
+#include <asm/txx9/dmac.h>
 #ifdef CONFIG_CPU_TX49XX
 #include <asm/txx9/tx4938.h>
 #endif
@@ -821,3 +823,176 @@ void __init txx9_iocled_init(unsigned long baseaddr,
 {
 }
 #endif /* CONFIG_LEDS_GPIO */
+
+void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq,
+                           const struct txx9dmac_platform_data *pdata)
+{
+#if defined(CONFIG_TXX9_DMAC) || defined(CONFIG_TXX9_DMAC_MODULE)
+        struct resource res[] = {
+                {
+                        .start = baseaddr,
+                        .end = baseaddr + 0x800 - 1,
+                        .flags = IORESOURCE_MEM,
+#ifndef CONFIG_MACH_TX49XX
+                }, {
+                        .start = irq,
+                        .flags = IORESOURCE_IRQ,
+#endif
+                }
+        };
+#ifdef CONFIG_MACH_TX49XX
+        struct resource chan_res[] = {
+                {
+                        .flags = IORESOURCE_IRQ,
+                }
+        };
+#endif
+        struct platform_device *pdev = platform_device_alloc("txx9dmac", id);
+        struct txx9dmac_chan_platform_data cpdata;
+        int i;
+
+        if (!pdev ||
+            platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
+            platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
+            platform_device_add(pdev)) {
+                platform_device_put(pdev);
+                return;
+        }
+        memset(&cpdata, 0, sizeof(cpdata));
+        cpdata.dmac_dev = pdev;
+        for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
+#ifdef CONFIG_MACH_TX49XX
+                chan_res[0].start = irq + i;
+#endif
+                pdev = platform_device_alloc("txx9dmac-chan",
+                                             id * TXX9_DMA_MAX_NR_CHANNELS + i);
+                if (!pdev ||
+#ifdef CONFIG_MACH_TX49XX
+                    platform_device_add_resources(pdev, chan_res,
+                                                  ARRAY_SIZE(chan_res)) ||
+#endif
+                    platform_device_add_data(pdev, &cpdata, sizeof(cpdata)) ||
+                    platform_device_add(pdev))
+                        platform_device_put(pdev);
+        }
+#endif
+}
+
+void __init txx9_aclc_init(unsigned long baseaddr, int irq,
+                           unsigned int dmac_id,
+                           unsigned int dma_chan_out,
+                           unsigned int dma_chan_in)
+{
+#if defined(CONFIG_SND_SOC_TXX9ACLC) || \
+        defined(CONFIG_SND_SOC_TXX9ACLC_MODULE)
+        unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS;
+        struct resource res[] = {
+                {
+                        .start = baseaddr,
+                        .end = baseaddr + 0x100 - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .name = "txx9dmac-chan",
+                        .start = dma_base + dma_chan_out,
+                        .flags = IORESOURCE_DMA,
+                }, {
+                        .name = "txx9dmac-chan",
+                        .start = dma_base + dma_chan_in,
+                        .flags = IORESOURCE_DMA,
+                }
+        };
+        struct platform_device *pdev =
+                platform_device_alloc("txx9aclc-ac97", -1);
+
+        if (!pdev ||
+            platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
+            platform_device_add(pdev))
+                platform_device_put(pdev);
+#endif
+}
+
+static struct sysdev_class txx9_sramc_sysdev_class;
+
+struct txx9_sramc_sysdev {
+        struct sys_device dev;
+        struct bin_attribute bindata_attr;
+        void __iomem *base;
+};
+
+static ssize_t txx9_sram_read(struct kobject *kobj,
+                              struct bin_attribute *bin_attr,
+                              char *buf, loff_t pos, size_t size)
+{
+        struct txx9_sramc_sysdev *dev = bin_attr->private;
+        size_t ramsize = bin_attr->size;
+
+        if (pos >= ramsize)
+                return 0;
+        if (pos + size > ramsize)
+                size = ramsize - pos;
+        memcpy_fromio(buf, dev->base + pos, size);
+        return size;
+}
+
+static ssize_t txx9_sram_write(struct kobject *kobj,
+                               struct bin_attribute *bin_attr,
+                               char *buf, loff_t pos, size_t size)
+{
+        struct txx9_sramc_sysdev *dev = bin_attr->private;
+        size_t ramsize = bin_attr->size;
+
+        if (pos >= ramsize)
+                return 0;
+        if (pos + size > ramsize)
+                size = ramsize - pos;
+        memcpy_toio(dev->base + pos, buf, size);
+        return size;
+}
+
+void __init txx9_sramc_init(struct resource *r)
+{
+        struct txx9_sramc_sysdev *dev;
+        size_t size;
+        int err;
+
+        if (!txx9_sramc_sysdev_class.name) {
+                txx9_sramc_sysdev_class.name = "txx9_sram";
+                err = sysdev_class_register(&txx9_sramc_sysdev_class);
+                if (err) {
+                        txx9_sramc_sysdev_class.name = NULL;
+                        return;
+                }
+        }
+        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+        if (!dev)
+                return;
+        size = resource_size(r);
+        dev->base = ioremap(r->start, size);
+        if (!dev->base)
+                goto exit;
+        dev->dev.cls = &txx9_sramc_sysdev_class;
+        dev->bindata_attr.attr.name = "bindata";
+        dev->bindata_attr.attr.mode = S_IRUSR | S_IWUSR;
+        dev->bindata_attr.read = txx9_sram_read;
+        dev->bindata_attr.write = txx9_sram_write;
+        dev->bindata_attr.size = size;
+        dev->bindata_attr.private = dev;
+        err = sysdev_register(&dev->dev);
+        if (err)
+                goto exit;
+        err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr);
+        if (err) {
+                sysdev_unregister(&dev->dev);
+                goto exit;
+        }
+        return;
+exit:
+        if (dev) {
+                if (dev->base)
+                        iounmap(dev->base);
+                kfree(dev);
+        }
+}
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
index 1093549df1a8..3418b2a90f7e 100644
--- a/arch/mips/txx9/generic/setup_tx4927.c
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -22,6 +22,7 @@
 #include <asm/txx9tmr.h>
 #include <asm/txx9pio.h>
 #include <asm/txx9/generic.h>
+#include <asm/txx9/dmac.h>
 #include <asm/txx9/tx4927.h>
 
 static void __init tx4927_wdr_init(void)
@@ -253,6 +254,60 @@ void __init tx4927_mtd_init(int ch)
         txx9_physmap_flash_init(ch, start, size, &pdata);
 }
 
+void __init tx4927_dmac_init(int memcpy_chan)
+{
+        struct txx9dmac_platform_data plat_data = {
+                .memcpy_chan = memcpy_chan,
+                .have_64bit_regs = true,
+        };
+
+        txx9_dmac_init(0, TX4927_DMA_REG & 0xfffffffffULL,
+                       TXX9_IRQ_BASE + TX4927_IR_DMA(0), &plat_data);
+}
+
+void __init tx4927_aclc_init(unsigned int dma_chan_out,
+                             unsigned int dma_chan_in)
+{
+        u64 pcfg = __raw_readq(&tx4927_ccfgptr->pcfg);
+        __u64 dmasel_mask = 0, dmasel = 0;
+        unsigned long flags;
+
+        if (!(pcfg & TX4927_PCFG_SEL2))
+                return;
+        /* setup DMASEL (playback:ACLC ch0, capture:ACLC ch1) */
+        switch (dma_chan_out) {
+        case 0:
+                dmasel_mask |= TX4927_PCFG_DMASEL0_MASK;
+                dmasel |= TX4927_PCFG_DMASEL0_ACL0;
+                break;
+        case 2:
+                dmasel_mask |= TX4927_PCFG_DMASEL2_MASK;
+                dmasel |= TX4927_PCFG_DMASEL2_ACL0;
+                break;
+        default:
+                return;
+        }
+        switch (dma_chan_in) {
+        case 1:
+                dmasel_mask |= TX4927_PCFG_DMASEL1_MASK;
+                dmasel |= TX4927_PCFG_DMASEL1_ACL1;
+                break;
+        case 3:
+                dmasel_mask |= TX4927_PCFG_DMASEL3_MASK;
+                dmasel |= TX4927_PCFG_DMASEL3_ACL1;
+                break;
+        default:
+                return;
+        }
+        local_irq_save(flags);
+        txx9_clear64(&tx4927_ccfgptr->pcfg, dmasel_mask);
+        txx9_set64(&tx4927_ccfgptr->pcfg, dmasel);
+        local_irq_restore(flags);
+        txx9_aclc_init(TX4927_ACLC_REG & 0xfffffffffULL,
+                       TXX9_IRQ_BASE + TX4927_IR_ACLC,
+                       0, dma_chan_out, dma_chan_in);
+}
+
 static void __init tx4927_stop_unused_modules(void)
 {
         __u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index 3925219b8973..eb2080110239 100644
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -24,6 +24,7 @@
 #include <asm/txx9pio.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/ndfmc.h>
+#include <asm/txx9/dmac.h>
 #include <asm/txx9/tx4938.h>
 
 static void __init tx4938_wdr_init(void)
@@ -239,11 +240,6 @@ void __init tx4938_setup(void)
         for (i = 0; i < TX4938_NR_TMR; i++)
                 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
 
-        /* DMA */
-        for (i = 0; i < 2; i++)
-                ____raw_writeq(TX4938_DMA_MCR_MSTEN,
-                               (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
-
         /* PIO */
         txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
         __raw_writel(0, &tx4938_pioptr->maskcpu);
@@ -403,6 +399,38 @@ void __init tx4938_ndfmc_init(unsigned int hold, unsigned int spw)
                 txx9_ndfmc_init(baseaddr, &plat_data);
 }
 
+void __init tx4938_dmac_init(int memcpy_chan0, int memcpy_chan1)
+{
+        struct txx9dmac_platform_data plat_data = {
+                .have_64bit_regs = true,
+        };
+        int i;
+
+        for (i = 0; i < 2; i++) {
+                plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
+                txx9_dmac_init(i, TX4938_DMA_REG(i) & 0xfffffffffULL,
+                               TXX9_IRQ_BASE + TX4938_IR_DMA(i, 0),
+                               &plat_data);
+        }
+}
+
+void __init tx4938_aclc_init(void)
+{
+        u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
+
+        if ((pcfg & TX4938_PCFG_SEL2) &&
+            !(pcfg & TX4938_PCFG_ETH0_SEL))
+                txx9_aclc_init(TX4938_ACLC_REG & 0xfffffffffULL,
+                               TXX9_IRQ_BASE + TX4938_IR_ACLC,
+                               1, 0, 1);
+}
+
+void __init tx4938_sramc_init(void)
+{
+        if (tx4938_sram_resource.start)
+                txx9_sramc_init(&tx4938_sram_resource);
+}
+
 static void __init tx4938_stop_unused_modules(void)
 {
         __u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
index c2bf150c8838..3dc19f482959 100644
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -28,6 +28,7 @@
 #include <asm/txx9tmr.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/ndfmc.h>
+#include <asm/txx9/dmac.h>
 #include <asm/txx9/tx4939.h>
 
 static void __init tx4939_wdr_init(void)
@@ -259,11 +260,6 @@ void __init tx4939_setup(void)
         for (i = 0; i < TX4939_NR_TMR; i++)
                 txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
 
-        /* DMA */
-        for (i = 0; i < 2; i++)
-                ____raw_writeq(TX4938_DMA_MCR_MSTEN,
-                               (void __iomem *)(TX4939_DMA_REG(i) + 0x50));
-
         /* set PCIC1 reset (required to prevent hangup on BIST) */
         txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
         pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
@@ -474,6 +470,53 @@ void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
         txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data);
 }
 
+void __init tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1)
+{
+        struct txx9dmac_platform_data plat_data = {
+                .have_64bit_regs = true,
+        };
+        int i;
+
+        for (i = 0; i < 2; i++) {
+                plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
+                txx9_dmac_init(i, TX4939_DMA_REG(i) & 0xfffffffffULL,
+                               TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0),
+                               &plat_data);
+        }
+}
+
+void __init tx4939_aclc_init(void)
+{
+        u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
+
+        if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_ACLC)
+                txx9_aclc_init(TX4939_ACLC_REG & 0xfffffffffULL,
+                               TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1);
+}
+
+void __init tx4939_sramc_init(void)
+{
+        if (tx4939_sram_resource.start)
+                txx9_sramc_init(&tx4939_sram_resource);
+}
+
+void __init tx4939_rng_init(void)
+{
+        static struct resource res = {
+                .start = TX4939_RNG_REG & 0xfffffffffULL,
+                .end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1,
+                .flags = IORESOURCE_MEM,
+        };
+        static struct platform_device pdev = {
+                .name = "tx4939-rng",
+                .id = -1,
+                .num_resources = 1,
+                .resource = &res,
+        };
+
+        platform_device_register(&pdev);
+}
+
 static void __init tx4939_stop_unused_modules(void)
 {
         __u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 01129a9d50fa..ee468eaee4f7 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -337,6 +337,14 @@ static void __init rbtx4927_device_init(void)
         rbtx4927_ne_init();
         tx4927_wdt_init();
         rbtx4927_mtd_init();
+        if (TX4927_REV_PCODE() == 0x4927) {
+                tx4927_dmac_init(2);
+                tx4927_aclc_init(0, 1);
+        } else {
+                tx4938_dmac_init(0, 2);
+                tx4938_aclc_init();
+        }
+        platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
         txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL);
         rbtx4927_gpioled_init();
 }
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index 65d13df8878a..d66509b14284 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -355,6 +355,10 @@ static void __init rbtx4938_device_init(void)
         /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
         tx4938_ndfmc_init(10, 35);
         tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1);
+        tx4938_dmac_init(0, 2);
+        tx4938_aclc_init();
+        platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
+        tx4938_sramc_init();
         txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
 }
 
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 4199c6fd4d1d..c033ffe71cdf 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -498,6 +498,11 @@ static void __init rbtx4939_device_init(void)
         tx4939_wdt_init();
         tx4939_ata_init();
         tx4939_rtc_init();
+        tx4939_dmac_init(0, 2);
+        tx4939_aclc_init();
+        platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
+        tx4939_sramc_init();
+        tx4939_rng_init();
 }
 
 static void __init rbtx4939_setup(void)