39 files changed, 256 insertions, 202 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ee5fbb02b28f..e8ff09fe73d9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -13,7 +13,7 @@ choice
         default SGI_IP22
 
 config MIPS_MTX1
-        bool "Support for 4G Systems MTX-1 board"
+        bool "4G Systems MTX-1 board"
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select SOC_AU1500
@@ -120,7 +120,7 @@ config MIPS_MIRAGE
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config MIPS_COBALT
-        bool "Support for Cobalt Server"
+        bool "Cobalt Server"
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select I8259
@@ -132,7 +132,7 @@ config MIPS_COBALT
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config MACH_DECSTATION
-        bool "Support for DECstations"
+        bool "DECstations"
         select BOOT_ELF32
         select DMA_NONCOHERENT
         select EARLY_PRINTK
@@ -158,7 +158,7 @@ config MACH_DECSTATION
           otherwise choose R3000.
 
 config MIPS_EV64120
-        bool "Support for Galileo EV64120 Evaluation board (EXPERIMENTAL)"
+        bool "Galileo EV64120 Evaluation board (EXPERIMENTAL)"
         depends on EXPERIMENTAL
         select DMA_NONCOHERENT
         select HW_HAS_PCI
@@ -175,7 +175,7 @@ config MIPS_EV64120
           kernel for this platform.
 
 config MIPS_EV96100
-        bool "Support for Galileo EV96100 Evaluation board (EXPERIMENTAL)"
+        bool "Galileo EV96100 Evaluation board (EXPERIMENTAL)"
         depends on EXPERIMENTAL
         select DMA_NONCOHERENT
         select HW_HAS_PCI
@@ -195,7 +195,7 @@ config MIPS_EV96100
           here if you wish to build a kernel for this platform.
 
 config MIPS_IVR
-        bool "Support for Globespan IVR board"
+        bool "Globespan IVR board"
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select ITE_BOARD_GEN
@@ -211,7 +211,7 @@ config MIPS_IVR
           build a kernel for this platform.
 
 config MIPS_ITE8172
-        bool "Support for ITE 8172G board"
+        bool "ITE 8172G board"
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select ITE_BOARD_GEN
@@ -228,7 +228,7 @@ config MIPS_ITE8172
           a kernel for this platform.
 
 config MACH_JAZZ
-        bool "Support for the Jazz family of machines"
+        bool "Jazz family of machines"
         select ARC
         select ARC32
         select ARCH_MAY_HAVE_PC_FDC
@@ -246,7 +246,7 @@ config MACH_JAZZ
          Olivetti M700-10 workstations.
 
 config LASAT
-        bool "Support for LASAT Networks platforms"
+        bool "LASAT Networks platforms"
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select MIPS_GT64120
@@ -258,7 +258,7 @@ config LASAT
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config MIPS_ATLAS
-        bool "Support for MIPS Atlas board"
+        bool "MIPS Atlas board"
         select BOOT_ELF32
         select DMA_NONCOHERENT
         select IRQ_CPU
@@ -283,7 +283,7 @@ config MIPS_ATLAS
           board.
 
 config MIPS_MALTA
-        bool "Support for MIPS Malta board"
+        bool "MIPS Malta board"
         select ARCH_MAY_HAVE_PC_FDC
         select BOOT_ELF32
         select HAVE_STD_PC_SERIAL_PORT
@@ -311,7 +311,7 @@ config MIPS_MALTA
           board.
 
 config MIPS_SEAD
-        bool "Support for MIPS SEAD board (EXPERIMENTAL)"
+        bool "MIPS SEAD board (EXPERIMENTAL)"
         depends on EXPERIMENTAL
         select IRQ_CPU
         select DMA_NONCOHERENT
@@ -328,7 +328,7 @@ config MIPS_SEAD
           board.
 
 config MIPS_SIM
-        bool 'Support for MIPS simulator (MIPSsim)'
+        bool 'MIPS simulator (MIPSsim)'
         select DMA_NONCOHERENT
         select IRQ_CPU
         select SYS_HAS_CPU_MIPS32_R1
@@ -341,7 +341,7 @@ config MIPS_SIM
           emulator.
 
 config MOMENCO_JAGUAR_ATX
-        bool "Support for Momentum Jaguar board"
+        bool "Momentum Jaguar board"
         select BOOT_ELF32
         select DMA_NONCOHERENT
         select HW_HAS_PCI
@@ -361,7 +361,7 @@ config MOMENCO_JAGUAR_ATX
           Momentum Computer <http://www.momenco.com/>.
 
 config MOMENCO_OCELOT
-        bool "Support for Momentum Ocelot board"
+        bool "Momentum Ocelot board"
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select IRQ_CPU
@@ -378,7 +378,7 @@ config MOMENCO_OCELOT
           Momentum Computer <http://www.momenco.com/>.
 
 config MOMENCO_OCELOT_3
-        bool "Support for Momentum Ocelot-3 board"
+        bool "Momentum Ocelot-3 board"
         select BOOT_ELF32
         select DMA_NONCOHERENT
         select HW_HAS_PCI
@@ -397,7 +397,7 @@ config MOMENCO_OCELOT_3
           PMC-Sierra Rm79000 core.
 
 config MOMENCO_OCELOT_C
-        bool "Support for Momentum Ocelot-C board"
+        bool "Momentum Ocelot-C board"
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select IRQ_CPU
@@ -414,7 +414,7 @@ config MOMENCO_OCELOT_C
           Momentum Computer <http://www.momenco.com/>.
 
 config MOMENCO_OCELOT_G
-        bool "Support for Momentum Ocelot-G board"
+        bool "Momentum Ocelot-G board"
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select IRQ_CPU
@@ -431,23 +431,23 @@ config MOMENCO_OCELOT_G
           Momentum Computer <http://www.momenco.com/>.
 
 config MIPS_XXS1500
-        bool "Support for MyCable XXS1500 board"
+        bool "MyCable XXS1500 board"
         select DMA_NONCOHERENT
         select SOC_AU1500
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config PNX8550_V2PCI
-        bool "Support for Philips PNX8550 based Viper2-PCI board"
+        bool "Philips PNX8550 based Viper2-PCI board"
         select PNX8550
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config PNX8550_JBS
-        bool "Support for Philips PNX8550 based JBS board"
+        bool "Philips PNX8550 based JBS board"
         select PNX8550
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config DDB5074
-        bool "Support for NEC DDB Vrc-5074 (EXPERIMENTAL)"
+        bool "NEC DDB Vrc-5074 (EXPERIMENTAL)"
         depends on EXPERIMENTAL
         select DDB5XXX_COMMON
         select DMA_NONCOHERENT
@@ -465,7 +465,7 @@ config DDB5074
           evaluation board.
 
 config DDB5476
-        bool "Support for NEC DDB Vrc-5476"
+        bool "NEC DDB Vrc-5476"
         select DDB5XXX_COMMON
         select DMA_NONCOHERENT
         select HAVE_STD_PC_SERIAL_PORT
@@ -486,7 +486,7 @@ config DDB5476
           IDE controller, PS2 keyboard, PS2 mouse, etc.
 
 config DDB5477
-        bool "Support for NEC DDB Vrc-5477"
+        bool "NEC DDB Vrc-5477"
         select DDB5XXX_COMMON
         select DMA_NONCOHERENT
         select HW_HAS_PCI
@@ -504,13 +504,13 @@ config DDB5477
           ether port USB, AC97, PCI, etc.
 
 config MACH_VR41XX
-        bool "Support for NEC VR4100 series based machines"
+        bool "NEC VR41XX-based machines"
         select SYS_HAS_CPU_VR41XX
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
 
 config PMC_YOSEMITE
-        bool "Support for PMC-Sierra Yosemite eval board"
+        bool "PMC-Sierra Yosemite eval board"
         select DMA_COHERENT
         select HW_HAS_PCI
         select IRQ_CPU
@@ -527,7 +527,7 @@ config PMC_YOSEMITE
           manufactured by PMC-Sierra.
 
 config QEMU
-        bool "Support for Qemu"
+        bool "Qemu"
         select DMA_COHERENT
         select GENERIC_ISA_DMA
         select HAVE_STD_PC_SERIAL_PORT
@@ -547,7 +547,7 @@ config QEMU
           can be found at http://www.linux-mips.org/wiki/Qemu.
 
 config SGI_IP22
-        bool "Support for SGI IP22 (Indy/Indigo2)"
+        bool "SGI IP22 (Indy/Indigo2)"
         select ARC
         select ARC32
         select BOOT_ELF32
@@ -567,7 +567,7 @@ config SGI_IP22
           that runs on these, say Y here.
 
 config SGI_IP27
-        bool "Support for SGI IP27 (Origin200/2000)"
+        bool "SGI IP27 (Origin200/2000)"
         select ARC
         select ARC64
         select BOOT_ELF64
@@ -583,7 +583,7 @@ config SGI_IP27
           here.
 
 config SGI_IP32
-        bool "Support for SGI IP32 (O2) (EXPERIMENTAL)"
+        bool "SGI IP32 (O2) (EXPERIMENTAL)"
         depends on EXPERIMENTAL
         select ARC
         select ARC32
@@ -604,7 +604,7 @@ config SGI_IP32
           If you want this kernel to run on SGI O2 workstation, say Y here.
 
 config SIBYTE_BIGSUR
-        bool "Support for Sibyte BCM91480B-BigSur"
+        bool "Sibyte BCM91480B-BigSur"
         select BOOT_ELF32
         select DMA_COHERENT
         select PCI_DOMAINS
@@ -615,7 +615,7 @@ config SIBYTE_BIGSUR
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SIBYTE_SWARM
-        bool "Support for Sibyte BCM91250A-SWARM"
+        bool "Sibyte BCM91250A-SWARM"
         select BOOT_ELF32
         select DMA_COHERENT
         select SIBYTE_SB1250
@@ -626,7 +626,7 @@ config SIBYTE_SWARM
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SIBYTE_SENTOSA
-        bool "Support for Sibyte BCM91250E-Sentosa"
+        bool "Sibyte BCM91250E-Sentosa"
         depends on EXPERIMENTAL
         select BOOT_ELF32
         select DMA_COHERENT
@@ -637,7 +637,7 @@ config SIBYTE_SENTOSA
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SIBYTE_RHONE
-        bool "Support for Sibyte BCM91125E-Rhone"
+        bool "Sibyte BCM91125E-Rhone"
         depends on EXPERIMENTAL
         select BOOT_ELF32
         select DMA_COHERENT
@@ -648,7 +648,7 @@ config SIBYTE_RHONE
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SIBYTE_CARMEL
-        bool "Support for Sibyte BCM91120x-Carmel"
+        bool "Sibyte BCM91120x-Carmel"
         depends on EXPERIMENTAL
         select BOOT_ELF32
         select DMA_COHERENT
@@ -659,7 +659,7 @@ config SIBYTE_CARMEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SIBYTE_PTSWARM
-        bool "Support for Sibyte BCM91250PT-PTSWARM"
+        bool "Sibyte BCM91250PT-PTSWARM"
         depends on EXPERIMENTAL
         select BOOT_ELF32
         select DMA_COHERENT
@@ -671,7 +671,7 @@ config SIBYTE_PTSWARM
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SIBYTE_LITTLESUR
-        bool "Support for Sibyte BCM91250C2-LittleSur"
+        bool "Sibyte BCM91250C2-LittleSur"
         depends on EXPERIMENTAL
         select BOOT_ELF32
         select DMA_COHERENT
@@ -683,7 +683,7 @@ config SIBYTE_LITTLESUR
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SIBYTE_CRHINE
-        bool "Support for Sibyte BCM91120C-CRhine"
+        bool "Sibyte BCM91120C-CRhine"
         depends on EXPERIMENTAL
         select BOOT_ELF32
         select DMA_COHERENT
@@ -694,7 +694,7 @@ config SIBYTE_CRHINE
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SIBYTE_CRHONE
-        bool "Support for Sibyte BCM91125C-CRhone"
+        bool "Sibyte BCM91125C-CRhone"
         depends on EXPERIMENTAL
         select BOOT_ELF32
         select DMA_COHERENT
@@ -706,7 +706,7 @@ config SIBYTE_CRHONE
         select SYS_SUPPORTS_LITTLE_ENDIAN
 
 config SNI_RM200_PCI
-        bool "Support for SNI RM200 PCI"
+        bool "SNI RM200 PCI"
         select ARC
         select ARC32
         select ARCH_MAY_HAVE_PC_FDC
@@ -732,7 +732,7 @@ config SNI_RM200_PCI
           support this machine type.
 
 config TOSHIBA_JMR3927
-        bool "Support for Toshiba JMR-TX3927 board"
+        bool "Toshiba JMR-TX3927 board"
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select MIPS_TX3927
@@ -743,7 +743,7 @@ config TOSHIBA_JMR3927
         select TOSHIBA_BOARDS
 
 config TOSHIBA_RBTX4927
-        bool "Support for Toshiba TBTX49[23]7 board"
+        bool "Toshiba TBTX49[23]7 board"
         select DMA_NONCOHERENT
         select HAS_TXX9_SERIAL
         select HW_HAS_PCI
@@ -760,7 +760,7 @@ config TOSHIBA_RBTX4927
           support this machine type
 
 config TOSHIBA_RBTX4938
-        bool "Support for Toshiba RBTX4938 board"
+        bool "Toshiba RBTX4938 board"
         select HAVE_STD_PC_SERIAL_PORT
         select DMA_NONCOHERENT
         select GENERIC_ISA_DMA
@@ -1411,13 +1411,12 @@ config PAGE_SIZE_8KB
 
 config PAGE_SIZE_16KB
         bool "16kB"
-        depends on EXPERIMENTAL && !CPU_R3000 && !CPU_TX39XX
+        depends on !CPU_R3000 && !CPU_TX39XX
         help
           Using 16kB page size will result in higher performance kernel at
           the price of higher memory consumption.  This option is available on
-          all non-R3000 family processor.  Not that at the time of this
-          writing this option is still high experimental; there are also
-          issues with compatibility of user applications.
+          all non-R3000 family processors.  Note that you will need a suitable
+          Linux distribution to support this.
 
 config PAGE_SIZE_64KB
         bool "64kB"
@@ -1426,8 +1425,7 @@ config PAGE_SIZE_64KB
           Using 64kB page size will result in higher performance kernel at
           the price of higher memory consumption.  This option is available on
           all non-R3000 family processor.  Not that at the time of this
-          writing this option is still high experimental; there are also
-          issues with compatibility of user applications.
+          writing this option is still high experimental.
 
 endchoice
 
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index da61de776154..afe05ec12c27 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -68,6 +68,7 @@
 
 extern void set_debug_traps(void);
 extern irq_cpustat_t irq_stat [NR_CPUS];
+extern void mips_timer_interrupt(struct pt_regs *regs);
 
 static void setup_local_irq(unsigned int irq, int type, int int_req);
 static unsigned int startup_irq(unsigned int irq);
diff --git a/arch/mips/au1000/common/prom.c b/arch/mips/au1000/common/prom.c
index 9c171afd9a53..ae7d8c57bf3f 100644
--- a/arch/mips/au1000/common/prom.c
+++ b/arch/mips/au1000/common/prom.c
@@ -1,10 +1,9 @@
 /*
  *
  * BRIEF MODULE DESCRIPTION
- *    PROM library initialisation code, assuming a version of
- *    pmon is the boot code.
+ *    PROM library initialisation code, assuming YAMON is the boot loader.
  *
- * Copyright 2000,2001 MontaVista Software Inc.
+ * Copyright 2000, 2001, 2006 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.
  *              ppopov@mvista.com or source@mvista.com
  *
@@ -49,9 +48,9 @@ extern char **prom_argv, **prom_envp;
 
 typedef struct
 {
-    char *name;
-/*    char *val; */
-}t_env_var;
+        char *name;
+        char *val;
+} t_env_var;
 
 
 char * prom_getcmdline(void)
@@ -85,21 +84,16 @@ char *prom_getenv(char *envname)
 {
         /*
          * Return a pointer to the given environment variable.
-         * Environment variables are stored in the form of "memsize=64".
          */
 
         t_env_var *env = (t_env_var *)prom_envp;
-        int i;
-
-        i = strlen(envname);
 
-        while(env->name) {
-                if(strncmp(envname, env->name, i) == 0) {
-                        return(env->name + strlen(envname) + 1);
-                }
+        while (env->name) {
+                if (strcmp(envname, env->name) == 0)
+                        return env->val;
                 env++;
         }
-        return(NULL);
+        return NULL;
 }
 
 inline unsigned char str2hexnum(unsigned char c)
diff --git a/arch/mips/au1000/common/sleeper.S b/arch/mips/au1000/common/sleeper.S
index 44dac3b0df3b..683d9da84b66 100644
--- a/arch/mips/au1000/common/sleeper.S
+++ b/arch/mips/au1000/common/sleeper.S
@@ -112,6 +112,11 @@ sdsleep:
         mtc0    k0, CP0_PAGEMASK
         lw      k0, 0x14(sp)
         mtc0    k0, CP0_CONFIG
+
+        /* We need to catch the ealry Alchemy SOCs with
+         * the write-only Config[OD] bit and set it back to one...
+         */
+        jal     au1x00_fixup_config_od
         lw      $1, PT_R1(sp)
         lw      $2, PT_R2(sp)
         lw      $3, PT_R3(sp)
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index f85f1524b366..f74d66a58a21 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -116,6 +116,7 @@ void mips_timer_interrupt(struct pt_regs *regs)
 
 null:
         ack_r4ktimer(0);
+        irq_exit();
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/mips/ddb5xxx/ddb5476/dbg_io.c b/arch/mips/ddb5xxx/ddb5476/dbg_io.c
index 85e9e5013679..f2296a999953 100644
--- a/arch/mips/ddb5xxx/ddb5476/dbg_io.c
+++ b/arch/mips/ddb5xxx/ddb5476/dbg_io.c
@@ -86,7 +86,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
         /* disable interrupts */
         UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-        /* set up buad rate */
+        /* set up baud rate */
         {
                 uint32 divisor;
 
diff --git a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
index 1d18d590495b..385bbdb10170 100644
--- a/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
+++ b/arch/mips/ddb5xxx/ddb5477/kgdb_io.c
@@ -86,7 +86,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
         /* disable interrupts */
         UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-        /* set up buad rate */
+        /* set up baud rate */
         {
                 uint32 divisor;
 
diff --git a/arch/mips/gt64120/ev64120/serialGT.c b/arch/mips/gt64120/ev64120/serialGT.c
index 16e34a546e54..8f0d835491ff 100644
--- a/arch/mips/gt64120/ev64120/serialGT.c
+++ b/arch/mips/gt64120/ev64120/serialGT.c
@@ -149,7 +149,7 @@ void serial_set(int channel, unsigned long baud)
 #else
         /*
          * Note: Set baud rate, hardcoded here for rate of 115200
-         * since became unsure of above "buad rate" algorithm (??).
+         * since became unsure of above "baud rate" algorithm (??).
          */
         outreg(channel, LCR, 0x83);
         outreg(channel, DLM, 0x00);     // See note above
diff --git a/arch/mips/gt64120/momenco_ocelot/dbg_io.c b/arch/mips/gt64120/momenco_ocelot/dbg_io.c
index 8720bccfdea2..f0a6a38fcf4d 100644
--- a/arch/mips/gt64120/momenco_ocelot/dbg_io.c
+++ b/arch/mips/gt64120/momenco_ocelot/dbg_io.c
@@ -73,7 +73,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
         /* disable interrupts */
         UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-        /* set up buad rate */
+        /* set up baud rate */
         {
                 uint32 divisor;
 
diff --git a/arch/mips/ite-boards/generic/dbg_io.c b/arch/mips/ite-boards/generic/dbg_io.c
index c4f8530fd07e..6a7ccaf93502 100644
--- a/arch/mips/ite-boards/generic/dbg_io.c
+++ b/arch/mips/ite-boards/generic/dbg_io.c
@@ -72,7 +72,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
         /* disable interrupts */
         UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-        /* set up buad rate */
+        /* set up baud rate */
         {
                 uint32 divisor;
 
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 92b28b674d6f..0facfaf4e950 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -272,8 +272,8 @@ void output_sc_defines(void)
         text("/* Linux sigcontext offsets. */");
         offset("#define SC_REGS       ", struct sigcontext, sc_regs);
         offset("#define SC_FPREGS     ", struct sigcontext, sc_fpregs);
-        offset("#define SC_MDHI       ", struct sigcontext, sc_hi);
-        offset("#define SC_MDLO       ", struct sigcontext, sc_lo);
+        offset("#define SC_MDHI       ", struct sigcontext, sc_mdhi);
+        offset("#define SC_MDLO       ", struct sigcontext, sc_mdlo);
         offset("#define SC_PC         ", struct sigcontext, sc_pc);
         offset("#define SC_FPC_CSR    ", struct sigcontext, sc_fpc_csr);
         linefeed;
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 47a087b6c11b..d268827c62bd 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -206,7 +206,7 @@ static inline void check_daddi(void)
                 "daddi  %0, %1, %3\n\t"
                 ".set   pop"
                 : "=r" (v), "=&r" (tmp)
-                : "I" (0xffffffffffffdb9a), "I" (0x1234));
+                : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
         set_except_vector(12, handler);
         local_irq_restore(flags);
 
@@ -224,7 +224,7 @@ static inline void check_daddi(void)
                 "dsrl   %1, %1, 1\n\t"
                 "daddi  %0, %1, %3"
                 : "=r" (v), "=&r" (tmp)
-                : "I" (0xffffffffffffdb9a), "I" (0x1234));
+                : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
         set_except_vector(12, handler);
         local_irq_restore(flags);
 
@@ -280,7 +280,7 @@ static inline void check_daddiu(void)
                 "daddu  %1, %2\n\t"
                 ".set   pop"
                 : "=&r" (v), "=&r" (w), "=&r" (tmp)
-                : "I" (0xffffffffffffdb9a), "I" (0x1234));
+                : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
 
         if (v == w) {
                 printk("no.\n");
@@ -296,7 +296,7 @@ static inline void check_daddiu(void)
                 "addiu  %1, $0, %4\n\t"
                 "daddu  %1, %2"
                 : "=&r" (v), "=&r" (w), "=&r" (tmp)
-                : "I" (0xffffffffffffdb9a), "I" (0x1234));
+                : "I" (0xffffffffffffdb9aUL), "I" (0x1234));
 
         if (v == w) {
                 printk("yes.\n");
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 58b3b14873cb..8c2c359a05f4 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -121,6 +121,7 @@ static inline void check_wait(void)
         case CPU_24K:
         case CPU_25KF:
         case CPU_34K:
+        case CPU_74K:
         case CPU_PR4450:
                 cpu_wait = r4k_wait;
                 printk(" available.\n");
@@ -432,6 +433,15 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                              MIPS_CPU_LLSC;
                 c->tlbsize = 64;
                 break;
+        case PRID_IMP_R14000:
+                c->cputype = CPU_R14000;
+                c->isa_level = MIPS_CPU_ISA_IV;
+                c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
+                             MIPS_CPU_FPU | MIPS_CPU_32FPR |
+                             MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
+                             MIPS_CPU_LLSC;
+                c->tlbsize = 64;
+                break;
         }
 }
 
@@ -593,6 +603,9 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
         case PRID_IMP_34K:
                 c->cputype = CPU_34K;
                 break;
+        case PRID_IMP_74K:
+                c->cputype = CPU_74K;
+                break;
         }
 }
 
@@ -642,7 +655,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
         case PRID_IMP_SB1:
                 c->cputype = CPU_SB1;
                 /* FPU in pass1 is known to have issues. */
-                if ((c->processor_id & 0xff) < 0x20)
+                if ((c->processor_id & 0xff) < 0x02)
                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
                 break;
         case PRID_IMP_SB1A:
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index d101d2fb24ca..a9c6de1b9542 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -101,7 +101,7 @@ FEXPORT(restore_all)			# restore full frame
         EMT
 1:
         mfc0    v1, CP0_TCSTATUS
-        /* We set IXMT above, XOR should cler it here */
+        /* We set IXMT above, XOR should clear it here */
         xori    v1, v1, TCSTATUS_IXMT
         or      v1, v0, v1
         mtc0    v1, CP0_TCSTATUS
diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S
index 10f28fb9f008..5fd7a8af0c62 100644
--- a/arch/mips/kernel/gdb-low.S
+++ b/arch/mips/kernel/gdb-low.S
@@ -54,9 +54,11 @@
                  */
                 mfc0    k0, CP0_CAUSE
                 andi    k0, k0, 0x7c
-                add     k1, k1, k0
-                PTR_L   k0, saved_vectors(k1)
-                jr      k0
+#ifdef CONFIG_64BIT
+                dsll    k0, k0, 1
+#endif
+                PTR_L   k1, saved_vectors(k0)
+                jr      k1
                 nop
 1:
                 move    k0, sp
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index e54a7f442f8a..d7bf0215bc1d 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -288,6 +288,9 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
                 sym = (Elf_Sym *)sechdrs[symindex].sh_addr
                         + ELF_MIPS_R_SYM(rel[i]);
                 if (!sym->st_value) {
+                        /* Ignore unresolved weak symbol */
+                        if (ELF_ST_BIND(sym->st_info) == STB_WEAK)
+                                continue;
                         printk(KERN_WARNING "%s: Unknown symbol %s\n",
                                me->name, strtab + sym->st_name);
                         return -ENOENT;
@@ -325,6 +328,9 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
                 sym = (Elf_Sym *)sechdrs[symindex].sh_addr
                         + ELF_MIPS_R_SYM(rel[i]);
                 if (!sym->st_value) {
+                        /* Ignore unresolved weak symbol */
+                        if (ELF_ST_BIND(sym->st_info) == STB_WEAK)
+                                continue;
                         printk(KERN_WARNING "%s: Unknown symbol %s\n",
                                me->name, strtab + sym->st_name);
                         return -ENOENT;
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 84ab959f924a..9def554f335b 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -42,6 +42,7 @@ static const char *cpu_name[] = {
         [CPU_R8000]     = "R8000",
         [CPU_R10000]    = "R10000",
         [CPU_R12000]    = "R12000",
+        [CPU_R14000]    = "R14000",
         [CPU_R4300]     = "R4300",
         [CPU_R4650]     = "R4650",
         [CPU_R4700]     = "R4700",
@@ -74,6 +75,7 @@ static const char *cpu_name[] = {
         [CPU_24K]       = "MIPS 24K",
         [CPU_25KF]      = "MIPS 25Kf",
         [CPU_34K]       = "MIPS 34K",
+        [CPU_74K]       = "MIPS 74K",
         [CPU_VR4111]    = "NEC VR4111",
         [CPU_VR4121]    = "NEC VR4121",
         [CPU_VR4122]    = "NEC VR4122",
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index b53a9207f530..8efb23a84131 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -209,7 +209,7 @@ sys_call_table:
         PTR     sys_fork
         PTR     sys_read
         PTR     sys_write
-        PTR     sys_open                        /* 4005 */
+        PTR     compat_sys_open                 /* 4005 */
         PTR     sys_close
         PTR     sys_waitpid
         PTR     sys_creat
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index bcf1b10e518f..397a70e651b5 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -246,7 +246,7 @@ static inline int parse_rd_cmdline(unsigned long* rd_start, unsigned long* rd_en
 #ifdef CONFIG_64BIT
         /* HACK: Guess if the sign extension was forgotten */
         if (start > 0x0000000080000000 && start < 0x00000000ffffffff)
-                start |= 0xffffffff00000000;
+                start |= 0xffffffff00000000UL;
 #endif
 
         end = start + size;
@@ -355,8 +355,6 @@ static inline void bootmem_init(void)
         }
 #endif
 
-        memory_present(0, first_usable_pfn, max_low_pfn);
-
         /* Initialize the boot-time allocator with low memory only.  */
         bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
 
@@ -410,6 +408,7 @@ static inline void bootmem_init(void)
 
                 /* Register lowmem ranges */
                 free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
+                memory_present(0, curr_pfn, curr_pfn + size - 1);
         }
 
         /* Reserve the bootmap memory.  */
@@ -419,17 +418,20 @@ static inline void bootmem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
         initrd_below_start_ok = 1;
         if (initrd_start) {
-                unsigned long initrd_size = ((unsigned char *)initrd_end) - ((unsigned char *)initrd_start);
+                unsigned long initrd_size = ((unsigned char *)initrd_end) -
+                        ((unsigned char *)initrd_start);
+                const int width = sizeof(long) * 2;
+
                 printk("Initial ramdisk at: 0x%p (%lu bytes)\n",
                        (void *)initrd_start, initrd_size);
 
                 if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) {
                         printk("initrd extends beyond end of memory "
                                "(0x%0*Lx > 0x%0*Lx)\ndisabling initrd\n",
-                               sizeof(long) * 2,
-                               (unsigned long long)CPHYSADDR(initrd_end),
-                               sizeof(long) * 2,
-                               (unsigned long long)PFN_PHYS(max_low_pfn));
+                               width,
+                               (unsigned long long) CPHYSADDR(initrd_end),
+                               width,
+                               (unsigned long long) PFN_PHYS(max_low_pfn));
                         initrd_start = initrd_end = 0;
                         initrd_reserve_bootmem = 0;
                 }
diff --git a/arch/mips/kernel/signal-common.h b/arch/mips/kernel/signal-common.h
index 3ca786215d48..ce6cb915c0a7 100644
--- a/arch/mips/kernel/signal-common.h
+++ b/arch/mips/kernel/signal-common.h
@@ -31,7 +31,6 @@ setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
         save_gp_reg(31);
 #undef save_gp_reg
 
-#ifdef CONFIG_32BIT
         err |= __put_user(regs->hi, &sc->sc_mdhi);
         err |= __put_user(regs->lo, &sc->sc_mdlo);
         if (cpu_has_dsp) {
@@ -43,20 +42,6 @@ setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
                 err |= __put_user(mflo3(), &sc->sc_lo3);
                 err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
         }
-#endif
-#ifdef CONFIG_64BIT
-        err |= __put_user(regs->hi, &sc->sc_hi[0]);
-        err |= __put_user(regs->lo, &sc->sc_lo[0]);
-        if (cpu_has_dsp) {
-                err |= __put_user(mfhi1(), &sc->sc_hi[1]);
-                err |= __put_user(mflo1(), &sc->sc_lo[1]);
-                err |= __put_user(mfhi2(), &sc->sc_hi[2]);
-                err |= __put_user(mflo2(), &sc->sc_lo[2]);
-                err |= __put_user(mfhi3(), &sc->sc_hi[3]);
-                err |= __put_user(mflo3(), &sc->sc_lo[3]);
-                err |= __put_user(rddsp(DSP_MASK), &sc->sc_dsp);
-        }
-#endif
 
         err |= __put_user(!!used_math(), &sc->sc_used_math);
 
@@ -92,7 +77,6 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
         current_thread_info()->restart_block.fn = do_no_restart_syscall;
 
         err |= __get_user(regs->cp0_epc, &sc->sc_pc);
-#ifdef CONFIG_32BIT
         err |= __get_user(regs->hi, &sc->sc_mdhi);
         err |= __get_user(regs->lo, &sc->sc_mdlo);
         if (cpu_has_dsp) {
@@ -104,20 +88,6 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
                 err |= __get_user(treg, &sc->sc_lo3); mtlo3(treg);
                 err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK);
         }
-#endif
-#ifdef CONFIG_64BIT
-        err |= __get_user(regs->hi, &sc->sc_hi[0]);
-        err |= __get_user(regs->lo, &sc->sc_lo[0]);
-        if (cpu_has_dsp) {
-                err |= __get_user(treg, &sc->sc_hi[1]); mthi1(treg);
-                err |= __get_user(treg, &sc->sc_lo[1]); mthi1(treg);
-                err |= __get_user(treg, &sc->sc_hi[2]); mthi2(treg);
-                err |= __get_user(treg, &sc->sc_lo[2]); mthi2(treg);
-                err |= __get_user(treg, &sc->sc_hi[3]); mthi3(treg);
-                err |= __get_user(treg, &sc->sc_lo[3]); mthi3(treg);
-                err |= __get_user(treg, &sc->sc_dsp); wrdsp(treg, DSP_MASK);
-        }
-#endif
 
 #define restore_gp_reg(i) do {                                          \
         err |= __get_user(regs->regs[i], &sc->sc_regs[i]);              \
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index d42f358754ad..298f82fe8440 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -247,6 +247,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         current_thread_info()->cpu = 0;
         smp_tune_scheduling();
         plat_prepare_cpus(max_cpus);
+#ifndef CONFIG_HOTPLUG_CPU
+        cpu_present_map = cpu_possible_map;
+#endif
 }
 
 /* preload SMP state for boot cpu */
@@ -442,7 +445,7 @@ static int __init topology_init(void)
         int cpu;
         int ret;
 
-        for_each_cpu(cpu) {
+        for_each_present_cpu(cpu) {
                 ret = register_cpu(&per_cpu(cpu_devices, cpu), cpu, NULL);
                 if (ret)
                         printk(KERN_WARNING "topology_init: register_cpu %d "
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 2aeaa2fd4b32..5e8a18a8e2bd 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -276,31 +276,9 @@ void sys_set_thread_area(unsigned long addr)
 
 asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
 {
-        int     tmp, len;
-        char    __user *name;
+        int     tmp;
 
         switch(cmd) {
-        case SETNAME: {
-                char nodename[__NEW_UTS_LEN + 1];
-
-                if (!capable(CAP_SYS_ADMIN))
-                        return -EPERM;
-
-                name = (char __user *) arg1;
-
-                len = strncpy_from_user(nodename, name, __NEW_UTS_LEN);
-                if (len < 0)
-                        return -EFAULT;
-
-                down_write(&uts_sem);
-                strncpy(system_utsname.nodename, nodename, len);
-                nodename[__NEW_UTS_LEN] = '\0';
-                strlcpy(system_utsname.nodename, nodename,
-                        sizeof(system_utsname.nodename));
-                up_write(&uts_sem);
-                return 0;
-        }
-
         case MIPS_ATOMIC_SET:
                 printk(KERN_CRIT "How did I get here?\n");
                 return -EINVAL;
@@ -313,9 +291,6 @@ asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
         case FLUSH_CACHE:
                 __flush_cache_all();
                 return 0;
-
-        case MIPS_RDNVRAM:
-                return -EIO;
         }
 
         return -EINVAL;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 4901f0a37fca..a7564b08eb4d 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -819,15 +819,30 @@ asmlinkage void do_watch(struct pt_regs *regs)
 
 asmlinkage void do_mcheck(struct pt_regs *regs)
 {
+        const int field = 2 * sizeof(unsigned long);
+        int multi_match = regs->cp0_status & ST0_TS;
+
         show_regs(regs);
-        dump_tlb_all();
+
+        if (multi_match) {
+                printk("Index   : %0x\n", read_c0_index());
+                printk("Pagemask: %0x\n", read_c0_pagemask());
+                printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
+                printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
+                printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
+                printk("\n");
+                dump_tlb_all();
+        }
+
+        show_code((unsigned int *) regs->cp0_epc);
+
         /*
          * Some chips may have other causes of machine check (e.g. SB1
          * graduation timer)
          */
         panic("Caught Machine Check exception - %scaused by multiple "
               "matching entries in the TLB.",
-              (regs->cp0_status & ST0_TS) ? "" : "not ");
+              (multi_match) ? "" : "not ");
 }
 
 asmlinkage void do_mt(struct pt_regs *regs)
@@ -902,6 +917,7 @@ static inline void parity_protection_init(void)
 {
         switch (current_cpu_data.cputype) {
         case CPU_24K:
+        case CPU_34K:
         case CPU_5KC:
                 write_c0_ecc(0x80000000);
                 back_to_back_c0_hazard();
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 14fa00e3cdfa..b84d1f9ce28e 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -151,23 +151,13 @@ SECTIONS
 
   /* This is the MIPS specific mdebug section.  */
   .mdebug : { *(.mdebug) }
-  /* These are needed for ELF backends which have not yet been
-     converted to the new style linker.  */
-  .stab 0 : { *(.stab) }
-  .stabstr 0 : { *(.stabstr) }
-  /* DWARF debug sections.
-     Symbols in the .debug DWARF section are relative to the beginning of the
-     section so we begin .debug at 0.  It's not clear yet what needs to happen
-     for the others.   */
-  .debug          0 : { *(.debug) }
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
-  .line           0 : { *(.line) }
+
+  STABS_DEBUG
+
+  DWARF_DEBUG
+
   /* These must appear regardless of  .  */
   .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
   .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
-  .comment : { *(.comment) }
   .note : { *(.note) }
 }
diff --git a/arch/mips/math-emu/dp_fint.c b/arch/mips/math-emu/dp_fint.c
index a1962eb460f8..39a71de16f47 100644
--- a/arch/mips/math-emu/dp_fint.c
+++ b/arch/mips/math-emu/dp_fint.c
@@ -29,7 +29,9 @@
 
 ieee754dp ieee754dp_fint(int x)
 {
-        COMPXDP;
+        u64 xm;
+        int xe;
+        int xs;
 
         CLEARCX;
 
diff --git a/arch/mips/math-emu/dp_flong.c b/arch/mips/math-emu/dp_flong.c
index eae90a866aa1..f08f223e488a 100644
--- a/arch/mips/math-emu/dp_flong.c
+++ b/arch/mips/math-emu/dp_flong.c
@@ -29,7 +29,9 @@
 
 ieee754dp ieee754dp_flong(s64 x)
 {
-        COMPXDP;
+        u64 xm;
+        int xe;
+        int xs;
 
         CLEARCX;
 
diff --git a/arch/mips/math-emu/sp_fint.c b/arch/mips/math-emu/sp_fint.c
index 7aac13afb09a..e88e125e01c2 100644
--- a/arch/mips/math-emu/sp_fint.c
+++ b/arch/mips/math-emu/sp_fint.c
@@ -29,7 +29,9 @@
 
 ieee754sp ieee754sp_fint(int x)
 {
-        COMPXSP;
+        unsigned xm;
+        int xe;
+        int xs;
 
         CLEARCX;
 
diff --git a/arch/mips/math-emu/sp_flong.c b/arch/mips/math-emu/sp_flong.c
index 3d6c1d11c178..26d6919a269a 100644
--- a/arch/mips/math-emu/sp_flong.c
+++ b/arch/mips/math-emu/sp_flong.c
@@ -29,7 +29,9 @@
 
 ieee754sp ieee754sp_flong(s64 x)
 {
-        COMPXDP;                /* <--- need 64-bit mantissa temp */
+        u64 xm;         /* <--- need 64-bit mantissa temp */
+        int xe;
+        int xs;
 
         CLEARCX;
 
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 4182e1176fae..4a43924cd4fc 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -29,6 +29,27 @@
 #include <asm/war.h>
 #include <asm/cacheflush.h> /* for run_uncached() */
 
+
+/*
+ * Special Variant of smp_call_function for use by cache functions:
+ *
+ *  o No return value
+ *  o collapses to normal function call on UP kernels
+ *  o collapses to normal function call on systems with a single shared
+ *    primary cache.
+ */
+static inline void r4k_on_each_cpu(void (*func) (void *info), void *info,
+                                   int retry, int wait)
+{
+        preempt_disable();
+
+#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
+        smp_call_function(func, info, retry, wait);
+#endif
+        func(info);
+        preempt_enable();
+}
+
 /*
  * Must die.
  */
@@ -299,7 +320,7 @@ static void r4k_flush_cache_all(void)
         if (!cpu_has_dc_aliases)
                 return;
 
-        on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
 }
 
 static inline void local_r4k___flush_cache_all(void * args)
@@ -314,13 +335,14 @@ static inline void local_r4k___flush_cache_all(void * args)
         case CPU_R4400MC:
         case CPU_R10000:
         case CPU_R12000:
+        case CPU_R14000:
                 r4k_blast_scache();
         }
 }
 
 static void r4k___flush_cache_all(void)
 {
-        on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
+        r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1, 1);
 }
 
 static inline void local_r4k_flush_cache_range(void * args)
@@ -341,7 +363,7 @@ static inline void local_r4k_flush_cache_range(void * args)
 static void r4k_flush_cache_range(struct vm_area_struct *vma,
         unsigned long start, unsigned long end)
 {
-        on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
 }
 
 static inline void local_r4k_flush_cache_mm(void * args)
@@ -370,7 +392,7 @@ static void r4k_flush_cache_mm(struct mm_struct *mm)
         if (!cpu_has_dc_aliases)
                 return;
 
-        on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
 }
 
 struct flush_cache_page_args {
@@ -461,7 +483,7 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
         args.addr = addr;
         args.pfn = pfn;
 
-        on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
 }
 
 static inline void local_r4k_flush_data_cache_page(void * addr)
@@ -471,7 +493,7 @@ static inline void local_r4k_flush_data_cache_page(void * addr)
 
 static void r4k_flush_data_cache_page(unsigned long addr)
 {
-        on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1);
 }
 
 struct flush_icache_range_args {
@@ -514,7 +536,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
         args.start = start;
         args.end = end;
 
-        on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
         instruction_hazard();
 }
 
@@ -590,7 +612,7 @@ static void r4k_flush_icache_page(struct vm_area_struct *vma,
         args.vma = vma;
         args.page = page;
 
-        on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_icache_page, &args, 1, 1);
 }
 
 
@@ -689,7 +711,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
 
 static void r4k_flush_cache_sigtramp(unsigned long addr)
 {
-        on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
+        r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1, 1);
 }
 
 static void r4k_flush_icache_all(void)
@@ -812,6 +834,7 @@ static void __init probe_pcache(void)
 
         case CPU_R10000:
         case CPU_R12000:
+        case CPU_R14000:
                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
                 c->icache.linesz = 64;
                 c->icache.ways = 2;
@@ -965,9 +988,11 @@ static void __init probe_pcache(void)
                 c->dcache.flags |= MIPS_CACHE_PINDEX;
         case CPU_R10000:
         case CPU_R12000:
+        case CPU_R14000:
         case CPU_SB1:
                 break;
         case CPU_24K:
+        case CPU_34K:
                 if (!(read_c0_config7() & (1 << 16)))
         default:
                         if (c->dcache.waysize > PAGE_SIZE)
@@ -1091,6 +1116,7 @@ static void __init setup_scache(void)
 
         case CPU_R10000:
         case CPU_R12000:
+        case CPU_R14000:
                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
                 c->scache.linesz = 64 << ((config >> 13) & 1);
                 c->scache.ways = 2;
@@ -1135,6 +1161,31 @@ static void __init setup_scache(void)
         c->options |= MIPS_CPU_SUBSET_CACHES;
 }
 
+void au1x00_fixup_config_od(void)
+{
+        /*
+         * c0_config.od (bit 19) was write only (and read as 0)
+         * on the early revisions of Alchemy SOCs.  It disables the bus
+         * transaction overlapping and needs to be set to fix various errata.
+         */
+        switch (read_c0_prid()) {
+        case 0x00030100: /* Au1000 DA */
+        case 0x00030201: /* Au1000 HA */
+        case 0x00030202: /* Au1000 HB */
+        case 0x01030200: /* Au1500 AB */
+        /*
+         * Au1100 errata actually keeps silence about this bit, so we set it
+         * just in case for those revisions that require it to be set according
+         * to arch/mips/au1000/common/cputable.c
+         */
+        case 0x02030200: /* Au1100 AB */
+        case 0x02030201: /* Au1100 BA */
+        case 0x02030202: /* Au1100 BC */
+                set_c0_config(1 << 19);
+                break;
+        }
+}
+
 static inline void coherency_setup(void)
 {
         change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
@@ -1155,6 +1206,15 @@ static inline void coherency_setup(void)
         case CPU_R4400MC:
                 clear_c0_config(CONF_CU);
                 break;
+        /*
+         * We need to catch the ealry Alchemy SOCs with
+         * the write-only co_config.od bit and set it back to one...
+         */
+        case CPU_AU1000: /* rev. DA, HA, HB */
+        case CPU_AU1100: /* rev. AB, BA, BC ?? */
+        case CPU_AU1500: /* rev. AB */
+                au1x00_fixup_config_od();
+                break;
         }
 }
 
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index c22308b93ff0..33f6e1cdfd5b 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -227,7 +227,7 @@ void __init mem_init(void)
         for (tmp = 0; tmp < max_low_pfn; tmp++)
                 if (page_is_ram(tmp)) {
                         ram++;
-                        if (PageReserved(mem_map+tmp))
+                        if (PageReserved(pfn_to_page(tmp)))
                                 reservedpages++;
                 }
 
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index e4390dc3eb48..b7c749232ffe 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -357,6 +357,7 @@ void __init build_clear_page(void)
 
                 case CPU_R10000:
                 case CPU_R12000:
+                case CPU_R14000:
                         pref_src_mode = Pref_LoadStreamed;
                         pref_dst_mode = Pref_StoreStreamed;
                         break;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 053dbacac56b..54507be2ab5b 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -875,6 +875,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
 
         case CPU_R10000:
         case CPU_R12000:
+        case CPU_R14000:
         case CPU_4KC:
         case CPU_SB1:
         case CPU_SB1A:
@@ -906,6 +907,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
         case CPU_4KEC:
         case CPU_24K:
         case CPU_34K:
+        case CPU_74K:
                 i_ehb(p);
                 tlbw(p);
                 break;
diff --git a/arch/mips/momentum/jaguar_atx/dbg_io.c b/arch/mips/momentum/jaguar_atx/dbg_io.c
index 542eac82b63c..d7dea0a136aa 100644
--- a/arch/mips/momentum/jaguar_atx/dbg_io.c
+++ b/arch/mips/momentum/jaguar_atx/dbg_io.c
@@ -73,7 +73,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
         /* disable interrupts */
         UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-        /* set up buad rate */
+        /* set up baud rate */
         {
                 uint32 divisor;
 
diff --git a/arch/mips/momentum/ocelot_c/dbg_io.c b/arch/mips/momentum/ocelot_c/dbg_io.c
index 8720bccfdea2..f0a6a38fcf4d 100644
--- a/arch/mips/momentum/ocelot_c/dbg_io.c
+++ b/arch/mips/momentum/ocelot_c/dbg_io.c
@@ -73,7 +73,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
         /* disable interrupts */
         UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-        /* set up buad rate */
+        /* set up baud rate */
         {
                 uint32 divisor;
 
diff --git a/arch/mips/momentum/ocelot_g/dbg_io.c b/arch/mips/momentum/ocelot_g/dbg_io.c
index 8720bccfdea2..f0a6a38fcf4d 100644
--- a/arch/mips/momentum/ocelot_g/dbg_io.c
+++ b/arch/mips/momentum/ocelot_g/dbg_io.c
@@ -73,7 +73,7 @@ void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
         /* disable interrupts */
         UART16550_WRITE(OFS_INTR_ENABLE, 0);
 
-        /* set up buad rate */
+        /* set up baud rate */
         {
                 uint32 divisor;
 
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index f2b4862aaae5..c31e4cff64e0 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -14,8 +14,8 @@
 
 #include "op_impl.h"
 
-extern struct op_mips_model op_model_mipsxx __attribute__((weak));
-extern struct op_mips_model op_model_rm9000 __attribute__((weak));
+extern struct op_mips_model op_model_mipsxx_ops __attribute__((weak));
+extern struct op_mips_model op_model_rm9000_ops __attribute__((weak));
 
 static struct op_mips_model *model;
 
@@ -80,13 +80,14 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
         case CPU_24K:
         case CPU_25KF:
         case CPU_34K:
+        case CPU_74K:
         case CPU_SB1:
         case CPU_SB1A:
-                lmodel = &op_model_mipsxx;
+                lmodel = &op_model_mipsxx_ops;
                 break;
 
         case CPU_RM9000:
-                lmodel = &op_model_rm9000;
+                lmodel = &op_model_rm9000_ops;
                 break;
         };
 
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 95d488ca0754..f26a00e13204 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -23,7 +23,7 @@
 
 #define M_COUNTER_OVERFLOW              (1UL    << 31)
 
-struct op_mips_model op_model_mipsxx;
+struct op_mips_model op_model_mipsxx_ops;
 
 static struct mipsxx_register_config {
         unsigned int control[4];
@@ -34,7 +34,7 @@ static struct mipsxx_register_config {
 
 static void mipsxx_reg_setup(struct op_counter_config *ctr)
 {
-        unsigned int counters = op_model_mipsxx.num_counters;
+        unsigned int counters = op_model_mipsxx_ops.num_counters;
         int i;
 
         /* Compute the performance counter control word.  */
@@ -62,7 +62,7 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
 
 static void mipsxx_cpu_setup (void *args)
 {
-        unsigned int counters = op_model_mipsxx.num_counters;
+        unsigned int counters = op_model_mipsxx_ops.num_counters;
 
         switch (counters) {
         case 4:
@@ -83,7 +83,7 @@ static void mipsxx_cpu_setup (void *args)
 /* Start all counters on current CPU */
 static void mipsxx_cpu_start(void *args)
 {
-        unsigned int counters = op_model_mipsxx.num_counters;
+        unsigned int counters = op_model_mipsxx_ops.num_counters;
 
         switch (counters) {
         case 4:
@@ -100,7 +100,7 @@ static void mipsxx_cpu_start(void *args)
 /* Stop all counters on current CPU */
 static void mipsxx_cpu_stop(void *args)
 {
-        unsigned int counters = op_model_mipsxx.num_counters;
+        unsigned int counters = op_model_mipsxx_ops.num_counters;
 
         switch (counters) {
         case 4:
@@ -116,7 +116,7 @@ static void mipsxx_cpu_stop(void *args)
 
 static int mipsxx_perfcount_handler(struct pt_regs *regs)
 {
-        unsigned int counters = op_model_mipsxx.num_counters;
+        unsigned int counters = op_model_mipsxx_ops.num_counters;
         unsigned int control;
         unsigned int counter;
         int handled = 0;
@@ -187,33 +187,37 @@ static int __init mipsxx_init(void)
 
         reset_counters(counters);
 
-        op_model_mipsxx.num_counters = counters;
+        op_model_mipsxx_ops.num_counters = counters;
         switch (current_cpu_data.cputype) {
         case CPU_20KC:
-                op_model_mipsxx.cpu_type = "mips/20K";
+                op_model_mipsxx_ops.cpu_type = "mips/20K";
                 break;
 
         case CPU_24K:
-                op_model_mipsxx.cpu_type = "mips/24K";
+                op_model_mipsxx_ops.cpu_type = "mips/24K";
                 break;
 
         case CPU_25KF:
-                op_model_mipsxx.cpu_type = "mips/25K";
+                op_model_mipsxx_ops.cpu_type = "mips/25K";
                 break;
 
 #ifndef CONFIG_SMP
         case CPU_34K:
-                op_model_mipsxx.cpu_type = "mips/34K";
+                op_model_mipsxx_ops.cpu_type = "mips/34K";
+                break;
+
+        case CPU_74K:
+                op_model_mipsxx_ops.cpu_type = "mips/74K";
                 break;
 #endif
 
         case CPU_5KC:
-                op_model_mipsxx.cpu_type = "mips/5K";
+                op_model_mipsxx_ops.cpu_type = "mips/5K";
                 break;
 
         case CPU_SB1:
         case CPU_SB1A:
-                op_model_mipsxx.cpu_type = "mips/sb1";
+                op_model_mipsxx_ops.cpu_type = "mips/sb1";
                 break;
 
         default:
@@ -229,12 +233,12 @@ static int __init mipsxx_init(void)
 
 static void mipsxx_exit(void)
 {
-        reset_counters(op_model_mipsxx.num_counters);
+        reset_counters(op_model_mipsxx_ops.num_counters);
 
         perf_irq = null_perf_irq;
 }
 
-struct op_mips_model op_model_mipsxx = {
+struct op_mips_model op_model_mipsxx_ops = {
         .reg_setup      = mipsxx_reg_setup,
         .cpu_setup      = mipsxx_cpu_setup,
         .init           = mipsxx_init,
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
index 9b75e41c78ef..b7063fefa65b 100644
--- a/arch/mips/oprofile/op_model_rm9000.c
+++ b/arch/mips/oprofile/op_model_rm9000.c
@@ -126,7 +126,7 @@ static void rm9000_exit(void)
         free_irq(rm9000_perfcount_irq, NULL);
 }
 
-struct op_mips_model op_model_rm9000 = {
+struct op_mips_model op_model_rm9000_ops = {
         .reg_setup      = rm9000_reg_setup,
         .cpu_setup      = rm9000_cpu_setup,
         .init           = rm9000_init,
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index de01c9815bdd..8ba08047d164 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -31,12 +31,12 @@
 /* issue a PIO read to make sure no PIO writes are pending */
 static void inline flush_crime_bus(void)
 {
-        volatile unsigned long junk = crime->control;
+        crime->control;
 }
 
 static void inline flush_mace_bus(void)
 {
-        volatile unsigned long junk = mace->perif.ctrl.misc;
+        mace->perif.ctrl.misc;
 }
 
 #undef DEBUG_IRQ