diff options
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/mm/c-r4k.c | 4 | ||||
-rw-r--r-- | arch/mips/mm/pg-r4k.c | 13 |
2 files changed, 10 insertions, 7 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 637052b23042..18247a7bf335 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c | |||
@@ -50,8 +50,8 @@ static struct bcache_ops no_sc_ops = { | |||
50 | 50 | ||
51 | struct bcache_ops *bcops = &no_sc_ops; | 51 | struct bcache_ops *bcops = &no_sc_ops; |
52 | 52 | ||
53 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010) | 53 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
54 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x2020) | 54 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) |
55 | 55 | ||
56 | #define R4600_HIT_CACHEOP_WAR_IMPL \ | 56 | #define R4600_HIT_CACHEOP_WAR_IMPL \ |
57 | do { \ | 57 | do { \ |
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c index 75d9ebfc5431..c9e6ee2a8a23 100644 --- a/arch/mips/mm/pg-r4k.c +++ b/arch/mips/mm/pg-r4k.c | |||
@@ -25,7 +25,10 @@ | |||
25 | #include <asm/cpu.h> | 25 | #include <asm/cpu.h> |
26 | #include <asm/war.h> | 26 | #include <asm/war.h> |
27 | 27 | ||
28 | #define half_scache_line_size() (cpu_scache_line_size() >> 1) | 28 | #define half_scache_line_size() (cpu_scache_line_size() >> 1) |
29 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) | ||
30 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) | ||
31 | |||
29 | 32 | ||
30 | /* | 33 | /* |
31 | * Maximum sizes: | 34 | * Maximum sizes: |
@@ -198,14 +201,14 @@ static inline void build_cdex_p(void) | |||
198 | if (store_offset & (cpu_dcache_line_size() - 1)) | 201 | if (store_offset & (cpu_dcache_line_size() - 1)) |
199 | return; | 202 | return; |
200 | 203 | ||
201 | if (R4600_V1_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2010)) { | 204 | if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) { |
202 | build_nop(); | 205 | build_nop(); |
203 | build_nop(); | 206 | build_nop(); |
204 | build_nop(); | 207 | build_nop(); |
205 | build_nop(); | 208 | build_nop(); |
206 | } | 209 | } |
207 | 210 | ||
208 | if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020)) | 211 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) |
209 | build_insn_word(0x8c200000); /* lw $zero, ($at) */ | 212 | build_insn_word(0x8c200000); /* lw $zero, ($at) */ |
210 | 213 | ||
211 | mi.c_format.opcode = cache_op; | 214 | mi.c_format.opcode = cache_op; |
@@ -361,7 +364,7 @@ void __init build_clear_page(void) | |||
361 | 364 | ||
362 | build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0)); | 365 | build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0)); |
363 | 366 | ||
364 | if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020)) | 367 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) |
365 | build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ | 368 | build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ |
366 | 369 | ||
367 | dest = label(); | 370 | dest = label(); |
@@ -417,7 +420,7 @@ void __init build_copy_page(void) | |||
417 | 420 | ||
418 | build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0)); | 421 | build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0)); |
419 | 422 | ||
420 | if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020)) | 423 | if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) |
421 | build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ | 424 | build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ |
422 | 425 | ||
423 | dest = label(); | 426 | dest = label(); |