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-rw-r--r--arch/mips/cavium-octeon/Makefile4
-rw-r--r--arch/mips/cavium-octeon/dma-octeon.c2
-rw-r--r--arch/mips/cavium-octeon/pci-common.c137
-rw-r--r--arch/mips/include/asm/octeon/pci-octeon.h (renamed from arch/mips/cavium-octeon/pci-common.h)30
-rw-r--r--arch/mips/pci/Makefile5
-rw-r--r--arch/mips/pci/msi-octeon.c (renamed from arch/mips/cavium-octeon/msi.c)56
-rw-r--r--arch/mips/pci/pci-octeon.c (renamed from arch/mips/cavium-octeon/pci.c)147
-rw-r--r--arch/mips/pci/pcie-octeon.c (renamed from arch/mips/cavium-octeon/pcie.c)37
8 files changed, 197 insertions, 221 deletions
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 7c0528b0e34c..d6903c3f3d51 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -14,9 +14,5 @@ obj-y += dma-octeon.o flash_setup.o
14obj-y += octeon-memcpy.o 14obj-y += octeon-memcpy.o
15 15
16obj-$(CONFIG_SMP) += smp.o 16obj-$(CONFIG_SMP) += smp.o
17obj-$(CONFIG_PCI) += pci-common.o
18obj-$(CONFIG_PCI) += pci.o
19obj-$(CONFIG_PCI) += pcie.o
20obj-$(CONFIG_PCI_MSI) += msi.o
21 17
22EXTRA_CFLAGS += -Werror 18EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index 627c162a6159..4b92bfc662db 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -29,7 +29,7 @@
29#include <dma-coherence.h> 29#include <dma-coherence.h>
30 30
31#ifdef CONFIG_PCI 31#ifdef CONFIG_PCI
32#include "pci-common.h" 32#include <asm/octeon/pci-octeon.h>
33#endif 33#endif
34 34
35#define BAR2_PCI_ADDRESS 0x8000000000ul 35#define BAR2_PCI_ADDRESS 0x8000000000ul
diff --git a/arch/mips/cavium-octeon/pci-common.c b/arch/mips/cavium-octeon/pci-common.c
deleted file mode 100644
index cd029f88da7f..000000000000
--- a/arch/mips/cavium-octeon/pci-common.c
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005-2007 Cavium Networks
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14#include "pci-common.h"
15
16typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
17enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
18
19/**
20 * Map a PCI device to the appropriate interrupt line
21 *
22 * @param dev The Linux PCI device structure for the device to map
23 * @param slot The slot number for this device on __BUS 0__. Linux
24 * enumerates through all the bridges and figures out the
25 * slot on Bus 0 where this device eventually hooks to.
26 * @param pin The PCI interrupt pin read from the device, then swizzled
27 * as it goes through each bridge.
28 * @return Interrupt number for the device
29 */
30int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
31{
32 if (octeon_pcibios_map_irq)
33 return octeon_pcibios_map_irq(dev, slot, pin);
34 else
35 panic("octeon_pcibios_map_irq doesn't point to a "
36 "pcibios_map_irq() function");
37}
38
39
40/**
41 * Called to perform platform specific PCI setup
42 *
43 * @param dev
44 * @return
45 */
46int pcibios_plat_dev_init(struct pci_dev *dev)
47{
48 uint16_t config;
49 uint32_t dconfig;
50 int pos;
51 /*
52 * Force the Cache line setting to 64 bytes. The standard
53 * Linux bus scan doesn't seem to set it. Octeon really has
54 * 128 byte lines, but Intel bridges get really upset if you
55 * try and set values above 64 bytes. Value is specified in
56 * 32bit words.
57 */
58 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
59 /* Set latency timers for all devices */
60 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
61
62 /* Enable reporting System errors and parity errors on all devices */
63 /* Enable parity checking and error reporting */
64 pci_read_config_word(dev, PCI_COMMAND, &config);
65 config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
66 pci_write_config_word(dev, PCI_COMMAND, config);
67
68 if (dev->subordinate) {
69 /* Set latency timers on sub bridges */
70 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
71 /* More bridge error detection */
72 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
73 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
74 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
75 }
76
77 /* Enable the PCIe normal error reporting */
78 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
79 if (pos) {
80 /* Update Device Control */
81 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
82 /* Correctable Error Reporting */
83 config |= PCI_EXP_DEVCTL_CERE;
84 /* Non-Fatal Error Reporting */
85 config |= PCI_EXP_DEVCTL_NFERE;
86 /* Fatal Error Reporting */
87 config |= PCI_EXP_DEVCTL_FERE;
88 /* Unsupported Request */
89 config |= PCI_EXP_DEVCTL_URRE;
90 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
91 }
92
93 /* Find the Advanced Error Reporting capability */
94 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
95 if (pos) {
96 /* Clear Uncorrectable Error Status */
97 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
98 &dconfig);
99 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
100 dconfig);
101 /* Enable reporting of all uncorrectable errors */
102 /* Uncorrectable Error Mask - turned on bits disable errors */
103 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
104 /*
105 * Leave severity at HW default. This only controls if
106 * errors are reported as uncorrectable or
107 * correctable, not if the error is reported.
108 */
109 /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
110 /* Clear Correctable Error Status */
111 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
112 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
113 /* Enable reporting of all correctable errors */
114 /* Correctable Error Mask - turned on bits disable errors */
115 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
116 /* Advanced Error Capabilities */
117 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
118 /* ECRC Generation Enable */
119 if (config & PCI_ERR_CAP_ECRC_GENC)
120 config |= PCI_ERR_CAP_ECRC_GENE;
121 /* ECRC Check Enable */
122 if (config & PCI_ERR_CAP_ECRC_CHKC)
123 config |= PCI_ERR_CAP_ECRC_CHKE;
124 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
125 /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
126 /* Report all errors to the root complex */
127 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
128 PCI_ERR_ROOT_CMD_COR_EN |
129 PCI_ERR_ROOT_CMD_NONFATAL_EN |
130 PCI_ERR_ROOT_CMD_FATAL_EN);
131 /* Clear the Root status register */
132 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
133 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
134 }
135
136 return 0;
137}
diff --git a/arch/mips/cavium-octeon/pci-common.h b/arch/mips/include/asm/octeon/pci-octeon.h
index 74ae79991e45..6ac5d3e3398e 100644
--- a/arch/mips/cavium-octeon/pci-common.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -3,23 +3,29 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2005-2007 Cavium Networks 6 * Copyright (C) 2005-2009 Cavium Networks
7 */ 7 */
8#ifndef __OCTEON_PCI_COMMON_H__ 8
9#define __OCTEON_PCI_COMMON_H__ 9#ifndef __PCI_OCTEON_H__
10#define __PCI_OCTEON_H__
10 11
11#include <linux/pci.h> 12#include <linux/pci.h>
12 13
13/* Some PCI cards require delays when accessing config space. */ 14/* Some PCI cards require delays when accessing config space. */
14#define PCI_CONFIG_SPACE_DELAY 10000 15#define PCI_CONFIG_SPACE_DELAY 10000
15 16
16/* pcibios_map_irq() is defined inside pci-common.c. All it does is call the 17/*
17 Octeon specific version pointed to by this variable. This function needs to 18 * pcibios_map_irq() is defined inside pci-octeon.c. All it does is
18 change for PCI or PCIe based hosts */ 19 * call the Octeon specific version pointed to by this variable. This
19extern typeof(pcibios_map_irq) *octeon_pcibios_map_irq; 20 * function needs to change for PCI or PCIe based hosts.
21 */
22extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
23 u8 slot, u8 pin);
20 24
21/* The following defines are only used when octeon_dma_bar_type = 25/*
22 OCTEON_DMA_BAR_TYPE_BIG */ 26 * The following defines are used when octeon_dma_bar_type =
27 * OCTEON_DMA_BAR_TYPE_BIG
28 */
23#define OCTEON_PCI_BAR1_HOLE_BITS 5 29#define OCTEON_PCI_BAR1_HOLE_BITS 5
24#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3)) 30#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
25 31
@@ -30,9 +36,9 @@ enum octeon_dma_bar_type {
30 OCTEON_DMA_BAR_TYPE_PCIE 36 OCTEON_DMA_BAR_TYPE_PCIE
31}; 37};
32 38
33/** 39/*
34 * This is a variable to tell the DMA mapping system in dma-octeon.c 40 * This tells the DMA mapping system in dma-octeon.c how to map PCI
35 * how to map PCI DMA addresses. 41 * DMA addresses.
36 */ 42 */
37extern enum octeon_dma_bar_type octeon_dma_bar_type; 43extern enum octeon_dma_bar_type octeon_dma_bar_type;
38 44
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index e8a97f59e066..63d8a297c58d 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -52,3 +52,8 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
52obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 52obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
53obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o 53obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
54obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o 54obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
55obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
56
57ifdef CONFIG_PCI_MSI
58obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
59endif
diff --git a/arch/mips/cavium-octeon/msi.c b/arch/mips/pci/msi-octeon.c
index 964b03b75a8f..03742e647657 100644
--- a/arch/mips/cavium-octeon/msi.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2005-2007 Cavium Networks 6 * Copyright (C) 2005-2009 Cavium Networks
7 */ 7 */
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/init.h> 9#include <linux/init.h>
@@ -16,8 +16,7 @@
16#include <asm/octeon/cvmx-pci-defs.h> 16#include <asm/octeon/cvmx-pci-defs.h>
17#include <asm/octeon/cvmx-npei-defs.h> 17#include <asm/octeon/cvmx-npei-defs.h>
18#include <asm/octeon/cvmx-pexp-defs.h> 18#include <asm/octeon/cvmx-pexp-defs.h>
19 19#include <asm/octeon/pci-octeon.h>
20#include "pci-common.h"
21 20
22/* 21/*
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is 22 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
@@ -47,8 +46,8 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
47 * programming the MSI control bits [6:4] before calling 46 * programming the MSI control bits [6:4] before calling
48 * pci_enable_msi(). 47 * pci_enable_msi().
49 * 48 *
50 * @param dev Device requesting MSI interrupts 49 * @dev: Device requesting MSI interrupts
51 * @param desc MSI descriptor 50 * @desc: MSI descriptor
52 * 51 *
53 * Returns 0 on success. 52 * Returns 0 on success.
54 */ 53 */
@@ -213,14 +212,9 @@ void arch_teardown_msi_irq(unsigned int irq)
213} 212}
214 213
215 214
216/** 215/*
217 * Called by the interrupt handling code when an MSI interrupt 216 * Called by the interrupt handling code when an MSI interrupt
218 * occurs. 217 * occurs.
219 *
220 * @param cpl
221 * @param dev_id
222 *
223 * @return
224 */ 218 */
225static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id) 219static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
226{ 220{
@@ -256,31 +250,37 @@ static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
256} 250}
257 251
258 252
259/** 253/*
260 * Initializes the MSI interrupt handling code 254 * Initializes the MSI interrupt handling code
261 *
262 * @return
263 */ 255 */
264int octeon_msi_initialize(void) 256int octeon_msi_initialize(void)
265{ 257{
266 int r;
267 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { 258 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
268 r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, 259 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
269 IRQF_SHARED, 260 IRQF_SHARED,
270 "MSI[0:63]", octeon_msi_interrupt); 261 "MSI[0:63]", octeon_msi_interrupt))
262 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
271 } else if (octeon_is_pci_host()) { 263 } else if (octeon_is_pci_host()) {
272 r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, 264 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
273 IRQF_SHARED, 265 IRQF_SHARED,
274 "MSI[0:15]", octeon_msi_interrupt); 266 "MSI[0:15]", octeon_msi_interrupt))
275 r += request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt, 267 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
276 IRQF_SHARED, 268
277 "MSI[16:31]", octeon_msi_interrupt); 269 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
278 r += request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt, 270 IRQF_SHARED,
279 IRQF_SHARED, 271 "MSI[16:31]", octeon_msi_interrupt))
280 "MSI[32:47]", octeon_msi_interrupt); 272 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
281 r += request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt, 273
282 IRQF_SHARED, 274 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
283 "MSI[48:63]", octeon_msi_interrupt); 275 IRQF_SHARED,
276 "MSI[32:47]", octeon_msi_interrupt))
277 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
278
279 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
280 IRQF_SHARED,
281 "MSI[48:63]", octeon_msi_interrupt))
282 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
283
284 } 284 }
285 return 0; 285 return 0;
286} 286}
diff --git a/arch/mips/cavium-octeon/pci.c b/arch/mips/pci/pci-octeon.c
index 67c0ff5e92f1..9cb0c807f564 100644
--- a/arch/mips/cavium-octeon/pci.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2005-2007 Cavium Networks 6 * Copyright (C) 2005-2009 Cavium Networks
7 */ 7 */
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/init.h> 9#include <linux/init.h>
@@ -17,8 +17,7 @@
17#include <asm/octeon/octeon.h> 17#include <asm/octeon/octeon.h>
18#include <asm/octeon/cvmx-npi-defs.h> 18#include <asm/octeon/cvmx-npi-defs.h>
19#include <asm/octeon/cvmx-pci-defs.h> 19#include <asm/octeon/cvmx-pci-defs.h>
20 20#include <asm/octeon/pci-octeon.h>
21#include "pci-common.h"
22 21
23#define USE_OCTEON_INTERNAL_ARBITER 22#define USE_OCTEON_INTERNAL_ARBITER
24 23
@@ -54,6 +53,126 @@ union octeon_pci_address {
54 } s; 53 } s;
55}; 54};
56 55
56int __initdata (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
57 u8 slot, u8 pin);
58enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
59
60/**
61 * Map a PCI device to the appropriate interrupt line
62 *
63 * @dev: The Linux PCI device structure for the device to map
64 * @slot: The slot number for this device on __BUS 0__. Linux
65 * enumerates through all the bridges and figures out the
66 * slot on Bus 0 where this device eventually hooks to.
67 * @pin: The PCI interrupt pin read from the device, then swizzled
68 * as it goes through each bridge.
69 * Returns Interrupt number for the device
70 */
71int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
72{
73 if (octeon_pcibios_map_irq)
74 return octeon_pcibios_map_irq(dev, slot, pin);
75 else
76 panic("octeon_pcibios_map_irq not set.");
77}
78
79
80/*
81 * Called to perform platform specific PCI setup
82 */
83int pcibios_plat_dev_init(struct pci_dev *dev)
84{
85 uint16_t config;
86 uint32_t dconfig;
87 int pos;
88 /*
89 * Force the Cache line setting to 64 bytes. The standard
90 * Linux bus scan doesn't seem to set it. Octeon really has
91 * 128 byte lines, but Intel bridges get really upset if you
92 * try and set values above 64 bytes. Value is specified in
93 * 32bit words.
94 */
95 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
96 /* Set latency timers for all devices */
97 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
98
99 /* Enable reporting System errors and parity errors on all devices */
100 /* Enable parity checking and error reporting */
101 pci_read_config_word(dev, PCI_COMMAND, &config);
102 config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
103 pci_write_config_word(dev, PCI_COMMAND, config);
104
105 if (dev->subordinate) {
106 /* Set latency timers on sub bridges */
107 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
108 /* More bridge error detection */
109 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
110 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
111 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
112 }
113
114 /* Enable the PCIe normal error reporting */
115 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
116 if (pos) {
117 /* Update Device Control */
118 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
119 /* Correctable Error Reporting */
120 config |= PCI_EXP_DEVCTL_CERE;
121 /* Non-Fatal Error Reporting */
122 config |= PCI_EXP_DEVCTL_NFERE;
123 /* Fatal Error Reporting */
124 config |= PCI_EXP_DEVCTL_FERE;
125 /* Unsupported Request */
126 config |= PCI_EXP_DEVCTL_URRE;
127 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
128 }
129
130 /* Find the Advanced Error Reporting capability */
131 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
132 if (pos) {
133 /* Clear Uncorrectable Error Status */
134 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
135 &dconfig);
136 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
137 dconfig);
138 /* Enable reporting of all uncorrectable errors */
139 /* Uncorrectable Error Mask - turned on bits disable errors */
140 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
141 /*
142 * Leave severity at HW default. This only controls if
143 * errors are reported as uncorrectable or
144 * correctable, not if the error is reported.
145 */
146 /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
147 /* Clear Correctable Error Status */
148 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
149 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
150 /* Enable reporting of all correctable errors */
151 /* Correctable Error Mask - turned on bits disable errors */
152 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
153 /* Advanced Error Capabilities */
154 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
155 /* ECRC Generation Enable */
156 if (config & PCI_ERR_CAP_ECRC_GENC)
157 config |= PCI_ERR_CAP_ECRC_GENE;
158 /* ECRC Check Enable */
159 if (config & PCI_ERR_CAP_ECRC_CHKC)
160 config |= PCI_ERR_CAP_ECRC_CHKE;
161 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
162 /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
163 /* Report all errors to the root complex */
164 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
165 PCI_ERR_ROOT_CMD_COR_EN |
166 PCI_ERR_ROOT_CMD_NONFATAL_EN |
167 PCI_ERR_ROOT_CMD_FATAL_EN);
168 /* Clear the Root status register */
169 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
170 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
171 }
172
173 return 0;
174}
175
57/** 176/**
58 * Return the mapping of PCI device number to IRQ line. Each 177 * Return the mapping of PCI device number to IRQ line. Each
59 * character in the return string represents the interrupt 178 * character in the return string represents the interrupt
@@ -136,9 +255,8 @@ int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
136} 255}
137 256
138 257
139/** 258/*
140 * Read a value from configuration space 259 * Read a value from configuration space
141 *
142 */ 260 */
143static int octeon_read_config(struct pci_bus *bus, unsigned int devfn, 261static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
144 int reg, int size, u32 *val) 262 int reg, int size, u32 *val)
@@ -174,15 +292,8 @@ static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
174} 292}
175 293
176 294
177/** 295/*
178 * Write a value to PCI configuration space 296 * Write a value to PCI configuration space
179 *
180 * @bus:
181 * @devfn:
182 * @reg:
183 * @size:
184 * @val:
185 * Returns
186 */ 297 */
187static int octeon_write_config(struct pci_bus *bus, unsigned int devfn, 298static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
188 int reg, int size, u32 val) 299 int reg, int size, u32 val)
@@ -251,10 +362,8 @@ static struct pci_controller octeon_pci_controller = {
251}; 362};
252 363
253 364
254/** 365/*
255 * Low level initialize the Octeon PCI controller 366 * Low level initialize the Octeon PCI controller
256 *
257 * Returns
258 */ 367 */
259static void octeon_pci_initialize(void) 368static void octeon_pci_initialize(void)
260{ 369{
@@ -398,7 +507,7 @@ static void octeon_pci_initialize(void)
398 pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */ 507 pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */
399 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64); 508 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
400 } 509 }
401#endif /* USE_OCTEON_INTERNAL_ARBITER */ 510#endif /* USE_OCTEON_INTERNAL_ARBITER */
402 511
403 /* 512 /*
404 * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE, 513 * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE,
@@ -457,10 +566,8 @@ static void octeon_pci_initialize(void)
457} 566}
458 567
459 568
460/** 569/*
461 * Initialize the Octeon PCI controller 570 * Initialize the Octeon PCI controller
462 *
463 * Returns
464 */ 571 */
465static int __init octeon_pci_setup(void) 572static int __init octeon_pci_setup(void)
466{ 573{
diff --git a/arch/mips/cavium-octeon/pcie.c b/arch/mips/pci/pcie-octeon.c
index 49d14081b3b5..75262247f3e4 100644
--- a/arch/mips/cavium-octeon/pcie.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -18,8 +18,7 @@
18#include <asm/octeon/cvmx-pescx-defs.h> 18#include <asm/octeon/cvmx-pescx-defs.h>
19#include <asm/octeon/cvmx-pexp-defs.h> 19#include <asm/octeon/cvmx-pexp-defs.h>
20#include <asm/octeon/cvmx-helper-errata.h> 20#include <asm/octeon/cvmx-helper-errata.h>
21 21#include <asm/octeon/pci-octeon.h>
22#include "pci-common.h"
23 22
24union cvmx_pcie_address { 23union cvmx_pcie_address {
25 uint64_t u64; 24 uint64_t u64;
@@ -976,13 +975,13 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
976/** 975/**
977 * Map a PCI device to the appropriate interrupt line 976 * Map a PCI device to the appropriate interrupt line
978 * 977 *
979 * @param dev The Linux PCI device structure for the device to map 978 * @dev: The Linux PCI device structure for the device to map
980 * @param slot The slot number for this device on __BUS 0__. Linux 979 * @slot: The slot number for this device on __BUS 0__. Linux
981 * enumerates through all the bridges and figures out the 980 * enumerates through all the bridges and figures out the
982 * slot on Bus 0 where this device eventually hooks to. 981 * slot on Bus 0 where this device eventually hooks to.
983 * @param pin The PCI interrupt pin read from the device, then swizzled 982 * @pin: The PCI interrupt pin read from the device, then swizzled
984 * as it goes through each bridge. 983 * as it goes through each bridge.
985 * @return Interrupt number for the device 984 * Returns Interrupt number for the device
986 */ 985 */
987int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, 986int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
988 u8 slot, u8 pin) 987 u8 slot, u8 pin)
@@ -1025,12 +1024,12 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
1025/** 1024/**
1026 * Read a value from configuration space 1025 * Read a value from configuration space
1027 * 1026 *
1028 * @param bus 1027 * @bus:
1029 * @param devfn 1028 * @devfn:
1030 * @param reg 1029 * @reg:
1031 * @param size 1030 * @size:
1032 * @param val 1031 * @val:
1033 * @return 1032 * Returns
1034 */ 1033 */
1035static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus, 1034static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
1036 unsigned int devfn, int reg, int size, 1035 unsigned int devfn, int reg, int size,
@@ -1156,12 +1155,12 @@ static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
1156/** 1155/**
1157 * Write a value to PCI configuration space 1156 * Write a value to PCI configuration space
1158 * 1157 *
1159 * @param bus 1158 * @bus:
1160 * @param devfn 1159 * @devfn:
1161 * @param reg 1160 * @reg:
1162 * @param size 1161 * @size:
1163 * @param val 1162 * @val:
1164 * @return 1163 * Returns
1165 */ 1164 */
1166static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus, 1165static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
1167 unsigned int devfn, int reg, 1166 unsigned int devfn, int reg,
@@ -1254,7 +1253,7 @@ static struct pci_controller octeon_pcie1_controller = {
1254/** 1253/**
1255 * Initialize the Octeon PCIe controllers 1254 * Initialize the Octeon PCIe controllers
1256 * 1255 *
1257 * @return 1256 * Returns
1258 */ 1257 */
1259static int __init octeon_pcie_setup(void) 1258static int __init octeon_pcie_setup(void)
1260{ 1259{
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 14:40:23 -0500