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-rw-r--r--arch/mips/au1000/common/dma.c2
-rw-r--r--arch/mips/au1000/common/irq.c52
-rw-r--r--arch/mips/au1000/common/time.c13
-rw-r--r--arch/mips/au1000/common/usbdev.c9
-rw-r--r--arch/mips/au1000/pb1200/irqmap.c5
-rw-r--r--arch/mips/basler/excite/excite_dbg_io.c2
-rw-r--r--arch/mips/basler/excite/excite_iodev.c14
-rw-r--r--arch/mips/basler/excite/excite_irq.c18
-rw-r--r--arch/mips/cobalt/irq.c51
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq.c19
-rw-r--r--arch/mips/dec/int-handler.S4
-rw-r--r--arch/mips/emma2rh/common/irq.c12
-rw-r--r--arch/mips/emma2rh/markeins/irq.c14
-rw-r--r--arch/mips/gt64120/common/time.c5
-rw-r--r--arch/mips/gt64120/ev64120/irq.c14
-rw-r--r--arch/mips/gt64120/momenco_ocelot/irq.c22
-rw-r--r--arch/mips/gt64120/wrppmc/irq.c10
-rw-r--r--arch/mips/jazz/irq.c30
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c106
-rw-r--r--arch/mips/kernel/asm-offsets.c3
-rw-r--r--arch/mips/kernel/entry.S1
-rw-r--r--arch/mips/kernel/genex.S15
-rw-r--r--arch/mips/kernel/irq-msc01.c4
-rw-r--r--arch/mips/kernel/irq-mv6434x.c6
-rw-r--r--arch/mips/kernel/irq.c6
-rw-r--r--arch/mips/kernel/rtlx.c6
-rw-r--r--arch/mips/kernel/smp-mt.c16
-rw-r--r--arch/mips/kernel/smtc.c26
-rw-r--r--arch/mips/kernel/time.c11
-rw-r--r--arch/mips/lasat/interrupt.c6
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c12
-rw-r--r--arch/mips/mips-boards/generic/time.c22
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c26
-rw-r--r--arch/mips/mips-boards/sead/sead_int.c4
-rw-r--r--arch/mips/mips-boards/sim/sim_int.c11
-rw-r--r--arch/mips/mips-boards/sim/sim_time.c14
-rw-r--r--arch/mips/momentum/jaguar_atx/irq.c20
-rw-r--r--arch/mips/momentum/ocelot_3/irq.c22
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c4
-rw-r--r--arch/mips/momentum/ocelot_c/irq.c22
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c4
-rw-r--r--arch/mips/momentum/ocelot_g/gt-irq.c4
-rw-r--r--arch/mips/momentum/ocelot_g/irq.c24
-rw-r--r--arch/mips/oprofile/op_impl.h4
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c7
-rw-r--r--arch/mips/pci/pci-ip32.c2
-rw-r--r--arch/mips/philips/pnx8550/common/int.c32
-rw-r--r--arch/mips/pmc-sierra/yosemite/irq.c54
-rw-r--r--arch/mips/pmc-sierra/yosemite/smp.c2
-rw-r--r--arch/mips/qemu/q-irq.c6
-rw-r--r--arch/mips/sgi-ip22/ip22-berr.c4
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c5
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c32
-rw-r--r--arch/mips/sgi-ip22/ip22-time.c6
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c26
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c4
-rw-r--r--arch/mips/sgi-ip32/crime.c6
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c48
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c27
-rw-r--r--arch/mips/sibyte/bcm1480/smp.c2
-rw-r--r--arch/mips/sibyte/bcm1480/time.c8
-rw-r--r--arch/mips/sibyte/sb1250/irq.c28
-rw-r--r--arch/mips/sibyte/sb1250/smp.c2
-rw-r--r--arch/mips/sibyte/sb1250/time.c6
-rw-r--r--arch/mips/sni/irq.c34
-rw-r--r--arch/mips/tx4927/common/tx4927_irq.c14
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c6
-rw-r--r--arch/mips/tx4938/common/irq.c46
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c3
-rw-r--r--arch/mips/vr41xx/common/icu.c2
-rw-r--r--arch/mips/vr41xx/common/irq.c32
71 files changed, 529 insertions, 610 deletions
diff --git a/arch/mips/au1000/common/dma.c b/arch/mips/au1000/common/dma.c
index fb7c47c1585d..c3019b9c91b1 100644
--- a/arch/mips/au1000/common/dma.c
+++ b/arch/mips/au1000/common/dma.c
@@ -160,7 +160,7 @@ void dump_au1000_dma_channel(unsigned int dmanr)
160 * Requests the DMA done IRQ if irqhandler != NULL. 160 * Requests the DMA done IRQ if irqhandler != NULL.
161 */ 161 */
162int request_au1000_dma(int dev_id, const char *dev_str, 162int request_au1000_dma(int dev_id, const char *dev_str,
163 irqreturn_t (*irqhandler)(int, void *, struct pt_regs *), 163 irqreturn_t (*irqhandler)(int, void *),
164 unsigned long irqflags, 164 unsigned long irqflags,
165 void *irq_dev_id) 165 void *irq_dev_id)
166{ 166{
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index 316722ee8cf5..b32597e05a69 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -67,7 +67,7 @@
67 67
68extern void set_debug_traps(void); 68extern void set_debug_traps(void);
69extern irq_cpustat_t irq_stat [NR_CPUS]; 69extern irq_cpustat_t irq_stat [NR_CPUS];
70extern void mips_timer_interrupt(struct pt_regs *regs); 70extern void mips_timer_interrupt(void);
71 71
72static void setup_local_irq(unsigned int irq, int type, int int_req); 72static void setup_local_irq(unsigned int irq, int type, int int_req);
73static unsigned int startup_irq(unsigned int irq); 73static unsigned int startup_irq(unsigned int irq);
@@ -81,10 +81,6 @@ inline void local_disable_irq(unsigned int irq_nr);
81 81
82void (*board_init_irq)(void); 82void (*board_init_irq)(void);
83 83
84#ifdef CONFIG_PM
85extern irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
86#endif
87
88static DEFINE_SPINLOCK(irq_lock); 84static DEFINE_SPINLOCK(irq_lock);
89 85
90 86
@@ -292,7 +288,7 @@ static struct irq_chip level_irq_type = {
292}; 288};
293 289
294#ifdef CONFIG_PM 290#ifdef CONFIG_PM
295void startup_match20_interrupt(irqreturn_t (*handler)(int, void *, struct pt_regs *)) 291void startup_match20_interrupt(irqreturn_t (*handler)(int, void *))
296{ 292{
297 struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT]; 293 struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
298 294
@@ -501,14 +497,15 @@ void __init arch_init_irq(void)
501 * intcX_reqX_irqdispatch(). 497 * intcX_reqX_irqdispatch().
502 */ 498 */
503 499
504void intc0_req0_irqdispatch(struct pt_regs *regs) 500static void intc0_req0_irqdispatch(void)
505{ 501{
506 int irq = 0; 502 int irq = 0;
507 static unsigned long intc0_req0 = 0; 503 static unsigned long intc0_req0 = 0;
508 504
509 intc0_req0 |= au_readl(IC0_REQ0INT); 505 intc0_req0 |= au_readl(IC0_REQ0INT);
510 506
511 if (!intc0_req0) return; 507 if (!intc0_req0)
508 return;
512#ifdef AU1000_USB_DEV_REQ_INT 509#ifdef AU1000_USB_DEV_REQ_INT
513 /* 510 /*
514 * Because of the tight timing of SETUP token to reply 511 * Because of the tight timing of SETUP token to reply
@@ -517,28 +514,29 @@ void intc0_req0_irqdispatch(struct pt_regs *regs)
517 */ 514 */
518 if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) { 515 if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
519 intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT); 516 intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
520 do_IRQ(AU1000_USB_DEV_REQ_INT, regs); 517 do_IRQ(AU1000_USB_DEV_REQ_INT);
521 return; 518 return;
522 } 519 }
523#endif 520#endif
524 irq = au_ffs(intc0_req0) - 1; 521 irq = au_ffs(intc0_req0) - 1;
525 intc0_req0 &= ~(1<<irq); 522 intc0_req0 &= ~(1<<irq);
526 do_IRQ(irq, regs); 523 do_IRQ(irq);
527} 524}
528 525
529 526
530void intc0_req1_irqdispatch(struct pt_regs *regs) 527static void intc0_req1_irqdispatch(void)
531{ 528{
532 int irq = 0; 529 int irq = 0;
533 static unsigned long intc0_req1 = 0; 530 static unsigned long intc0_req1 = 0;
534 531
535 intc0_req1 |= au_readl(IC0_REQ1INT); 532 intc0_req1 |= au_readl(IC0_REQ1INT);
536 533
537 if (!intc0_req1) return; 534 if (!intc0_req1)
535 return;
538 536
539 irq = au_ffs(intc0_req1) - 1; 537 irq = au_ffs(intc0_req1) - 1;
540 intc0_req1 &= ~(1<<irq); 538 intc0_req1 &= ~(1<<irq);
541 do_IRQ(irq, regs); 539 do_IRQ(irq);
542} 540}
543 541
544 542
@@ -546,35 +544,37 @@ void intc0_req1_irqdispatch(struct pt_regs *regs)
546 * Interrupt Controller 1: 544 * Interrupt Controller 1:
547 * interrupts 32 - 63 545 * interrupts 32 - 63
548 */ 546 */
549void intc1_req0_irqdispatch(struct pt_regs *regs) 547static void intc1_req0_irqdispatch(void)
550{ 548{
551 int irq = 0; 549 int irq = 0;
552 static unsigned long intc1_req0 = 0; 550 static unsigned long intc1_req0 = 0;
553 551
554 intc1_req0 |= au_readl(IC1_REQ0INT); 552 intc1_req0 |= au_readl(IC1_REQ0INT);
555 553
556 if (!intc1_req0) return; 554 if (!intc1_req0)
555 return;
557 556
558 irq = au_ffs(intc1_req0) - 1; 557 irq = au_ffs(intc1_req0) - 1;
559 intc1_req0 &= ~(1<<irq); 558 intc1_req0 &= ~(1<<irq);
560 irq += 32; 559 irq += 32;
561 do_IRQ(irq, regs); 560 do_IRQ(irq);
562} 561}
563 562
564 563
565void intc1_req1_irqdispatch(struct pt_regs *regs) 564static void intc1_req1_irqdispatch(void)
566{ 565{
567 int irq = 0; 566 int irq = 0;
568 static unsigned long intc1_req1 = 0; 567 static unsigned long intc1_req1 = 0;
569 568
570 intc1_req1 |= au_readl(IC1_REQ1INT); 569 intc1_req1 |= au_readl(IC1_REQ1INT);
571 570
572 if (!intc1_req1) return; 571 if (!intc1_req1)
572 return;
573 573
574 irq = au_ffs(intc1_req1) - 1; 574 irq = au_ffs(intc1_req1) - 1;
575 intc1_req1 &= ~(1<<irq); 575 intc1_req1 &= ~(1<<irq);
576 irq += 32; 576 irq += 32;
577 do_IRQ(irq, regs); 577 do_IRQ(irq);
578} 578}
579 579
580#ifdef CONFIG_PM 580#ifdef CONFIG_PM
@@ -660,20 +660,20 @@ restore_au1xxx_intctl(void)
660} 660}
661#endif /* CONFIG_PM */ 661#endif /* CONFIG_PM */
662 662
663asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 663asmlinkage void plat_irq_dispatch(void)
664{ 664{
665 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 665 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
666 666
667 if (pending & CAUSEF_IP7) 667 if (pending & CAUSEF_IP7)
668 mips_timer_interrupt(regs); 668 mips_timer_interrupt();
669 else if (pending & CAUSEF_IP2) 669 else if (pending & CAUSEF_IP2)
670 intc0_req0_irqdispatch(regs); 670 intc0_req0_irqdispatch();
671 else if (pending & CAUSEF_IP3) 671 else if (pending & CAUSEF_IP3)
672 intc0_req1_irqdispatch(regs); 672 intc0_req1_irqdispatch();
673 else if (pending & CAUSEF_IP4) 673 else if (pending & CAUSEF_IP4)
674 intc1_req0_irqdispatch(regs); 674 intc1_req0_irqdispatch();
675 else if (pending & CAUSEF_IP5) 675 else if (pending & CAUSEF_IP5)
676 intc1_req1_irqdispatch(regs); 676 intc1_req1_irqdispatch();
677 else 677 else
678 spurious_interrupt(regs); 678 spurious_interrupt();
679} 679}
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index 0a067f3113a5..1989d56139c8 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -62,7 +62,7 @@ static unsigned int timerhi = 0, timerlo = 0;
62#error "unsupported HZ value! Must be in [100,1000]" 62#error "unsupported HZ value! Must be in [100,1000]"
63#endif 63#endif
64#define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */ 64#define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
65extern void startup_match20_interrupt(irqreturn_t (*handler)(int, void *, struct pt_regs *)); 65extern void startup_match20_interrupt(irqreturn_t (*handler)(int, void *));
66static unsigned long last_pc0, last_match20; 66static unsigned long last_pc0, last_match20;
67#endif 67#endif
68 68
@@ -79,7 +79,8 @@ static inline void ack_r4ktimer(unsigned long newval)
79 * is provably more robust. 79 * is provably more robust.
80 */ 80 */
81unsigned long wtimer; 81unsigned long wtimer;
82void mips_timer_interrupt(struct pt_regs *regs) 82
83void mips_timer_interrupt(void)
83{ 84{
84 int irq = 63; 85 int irq = 63;
85 unsigned long count; 86 unsigned long count;
@@ -98,7 +99,7 @@ void mips_timer_interrupt(struct pt_regs *regs)
98 kstat_this_cpu.irqs[irq]++; 99 kstat_this_cpu.irqs[irq]++;
99 do_timer(1); 100 do_timer(1);
100#ifndef CONFIG_SMP 101#ifndef CONFIG_SMP
101 update_process_times(user_mode(regs)); 102 update_process_times(user_mode(get_irq_regs()));
102#endif 103#endif
103 r4k_cur += r4k_offset; 104 r4k_cur += r4k_offset;
104 ack_r4ktimer(r4k_cur); 105 ack_r4ktimer(r4k_cur);
@@ -115,7 +116,7 @@ null:
115} 116}
116 117
117#ifdef CONFIG_PM 118#ifdef CONFIG_PM
118irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs) 119irqreturn_t counter0_irq(int irq, void *dev_id)
119{ 120{
120 unsigned long pc0; 121 unsigned long pc0;
121 int time_elapsed; 122 int time_elapsed;
@@ -139,7 +140,7 @@ irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
139 while (time_elapsed > 0) { 140 while (time_elapsed > 0) {
140 do_timer(1); 141 do_timer(1);
141#ifndef CONFIG_SMP 142#ifndef CONFIG_SMP
142 update_process_times(user_mode(regs)); 143 update_process_times(user_mode(get_irq_regs()));
143#endif 144#endif
144 time_elapsed -= MATCH20_INC; 145 time_elapsed -= MATCH20_INC;
145 last_match20 += MATCH20_INC; 146 last_match20 += MATCH20_INC;
@@ -158,7 +159,7 @@ irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
158 jiffie_drift -= 999; 159 jiffie_drift -= 999;
159 do_timer(1); /* increment jiffies by one */ 160 do_timer(1); /* increment jiffies by one */
160#ifndef CONFIG_SMP 161#ifndef CONFIG_SMP
161 update_process_times(user_mode(regs)); 162 update_process_times(user_mode(get_irq_regs()));
162#endif 163#endif
163 } 164 }
164 165
diff --git a/arch/mips/au1000/common/usbdev.c b/arch/mips/au1000/common/usbdev.c
index 63bcb3a95dc7..70dc82e536cd 100644
--- a/arch/mips/au1000/common/usbdev.c
+++ b/arch/mips/au1000/common/usbdev.c
@@ -1031,8 +1031,7 @@ process_ep_receive (struct usb_dev* dev, endpoint_t *ep)
1031 1031
1032 1032
1033/* This ISR handles the receive complete and suspend events */ 1033/* This ISR handles the receive complete and suspend events */
1034static void 1034static void req_sus_intr (int irq, void *dev_id)
1035req_sus_intr (int irq, void *dev_id, struct pt_regs *regs)
1036{ 1035{
1037 struct usb_dev *dev = (struct usb_dev *) dev_id; 1036 struct usb_dev *dev = (struct usb_dev *) dev_id;
1038 u32 status; 1037 u32 status;
@@ -1050,8 +1049,7 @@ req_sus_intr (int irq, void *dev_id, struct pt_regs *regs)
1050 1049
1051 1050
1052/* This ISR handles the DMA done events on EP0 */ 1051/* This ISR handles the DMA done events on EP0 */
1053static void 1052static void dma_done_ep0_intr(int irq, void *dev_id)
1054dma_done_ep0_intr(int irq, void *dev_id, struct pt_regs *regs)
1055{ 1053{
1056 struct usb_dev *dev = (struct usb_dev *) dev_id; 1054 struct usb_dev *dev = (struct usb_dev *) dev_id;
1057 usbdev_pkt_t* pkt; 1055 usbdev_pkt_t* pkt;
@@ -1094,8 +1092,7 @@ dma_done_ep0_intr(int irq, void *dev_id, struct pt_regs *regs)
1094} 1092}
1095 1093
1096/* This ISR handles the DMA done events on endpoints 2,3,4,5 */ 1094/* This ISR handles the DMA done events on endpoints 2,3,4,5 */
1097static void 1095static void dma_done_ep_intr(int irq, void *dev_id)
1098dma_done_ep_intr(int irq, void *dev_id, struct pt_regs *regs)
1099{ 1096{
1100 struct usb_dev *dev = (struct usb_dev *) dev_id; 1097 struct usb_dev *dev = (struct usb_dev *) dev_id;
1101 int i; 1098 int i;
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
index f66779f0d4cd..91983ba407c4 100644
--- a/arch/mips/au1000/pb1200/irqmap.c
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -65,7 +65,7 @@ int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
65 */ 65 */
66static volatile int pb1200_cascade_en=0; 66static volatile int pb1200_cascade_en=0;
67 67
68irqreturn_t pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs) 68irqreturn_t pb1200_cascade_handler( int irq, void *dev_id)
69{ 69{
70 unsigned short bisr = bcsr->int_status; 70 unsigned short bisr = bcsr->int_status;
71 int extirq_nr = 0; 71 int extirq_nr = 0;
@@ -76,8 +76,9 @@ irqreturn_t pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
76 { 76 {
77 extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr); 77 extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
78 /* Ack and dispatch IRQ */ 78 /* Ack and dispatch IRQ */
79 do_IRQ(extirq_nr,regs); 79 do_IRQ(extirq_nr);
80 } 80 }
81
81 return IRQ_RETVAL(1); 82 return IRQ_RETVAL(1);
82} 83}
83 84
diff --git a/arch/mips/basler/excite/excite_dbg_io.c b/arch/mips/basler/excite/excite_dbg_io.c
index c04505afa47f..d289e3a868cf 100644
--- a/arch/mips/basler/excite/excite_dbg_io.c
+++ b/arch/mips/basler/excite/excite_dbg_io.c
@@ -112,7 +112,7 @@ int putDebugChar(int data)
112} 112}
113 113
114/* KGDB interrupt handler */ 114/* KGDB interrupt handler */
115asmlinkage void excite_kgdb_inthdl(struct pt_regs *regs) 115asmlinkage void excite_kgdb_inthdl(void)
116{ 116{
117 if (unlikely( 117 if (unlikely(
118 ((titan_readl(UAIIR) & 0x7) == 4) 118 ((titan_readl(UAIIR) & 0x7) == 4)
diff --git a/arch/mips/basler/excite/excite_iodev.c b/arch/mips/basler/excite/excite_iodev.c
index 10bbb8cfb964..6af0b21ebc32 100644
--- a/arch/mips/basler/excite/excite_iodev.c
+++ b/arch/mips/basler/excite/excite_iodev.c
@@ -38,7 +38,7 @@ static int iodev_open(struct inode *, struct file *);
38static int iodev_release(struct inode *, struct file *); 38static int iodev_release(struct inode *, struct file *);
39static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *); 39static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *);
40static unsigned int iodev_poll(struct file *, struct poll_table_struct *); 40static unsigned int iodev_poll(struct file *, struct poll_table_struct *);
41static irqreturn_t iodev_irqhdl(int, void *, struct pt_regs *); 41static irqreturn_t iodev_irqhdl(int, void *);
42 42
43 43
44 44
@@ -108,16 +108,12 @@ static int __exit iodev_remove(struct device *dev)
108 return misc_deregister(&miscdev); 108 return misc_deregister(&miscdev);
109} 109}
110 110
111
112
113static int iodev_open(struct inode *i, struct file *f) 111static int iodev_open(struct inode *i, struct file *f)
114{ 112{
115 return request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED, 113 return request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED,
116 iodev_name, &miscdev); 114 iodev_name, &miscdev);
117} 115}
118 116
119
120
121static int iodev_release(struct inode *i, struct file *f) 117static int iodev_release(struct inode *i, struct file *f)
122{ 118{
123 free_irq(iodev_irq, &miscdev); 119 free_irq(iodev_irq, &miscdev);
@@ -148,17 +144,13 @@ static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p)
148 return POLLOUT | POLLWRNORM; 144 return POLLOUT | POLLWRNORM;
149} 145}
150 146
151 147static irqreturn_t iodev_irqhdl(int irq, void *ctxt)
152
153
154static irqreturn_t iodev_irqhdl(int irq, void *ctxt, struct pt_regs *regs)
155{ 148{
156 wake_up(&wq); 149 wake_up(&wq);
150
157 return IRQ_HANDLED; 151 return IRQ_HANDLED;
158} 152}
159 153
160
161
162static int __init iodev_init_module(void) 154static int __init iodev_init_module(void)
163{ 155{
164 return driver_register(&iodev_driver); 156 return driver_register(&iodev_driver);
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c
index 511ad8730f54..2e2061a286c5 100644
--- a/arch/mips/basler/excite/excite_irq.c
+++ b/arch/mips/basler/excite/excite_irq.c
@@ -56,7 +56,7 @@ void __init arch_init_irq(void)
56#endif 56#endif
57} 57}
58 58
59asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 59asmlinkage void plat_irq_dispatch(void)
60{ 60{
61 const u32 61 const u32
62 interrupts = read_c0_cause() >> 8, 62 interrupts = read_c0_cause() >> 8,
@@ -67,7 +67,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
67 67
68 /* process timer interrupt */ 68 /* process timer interrupt */
69 if (pending & (1 << TIMER_IRQ)) { 69 if (pending & (1 << TIMER_IRQ)) {
70 do_IRQ(TIMER_IRQ, regs); 70 do_IRQ(TIMER_IRQ);
71 return; 71 return;
72 } 72 }
73 73
@@ -80,7 +80,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
80#else 80#else
81 if (pending & (1 << USB_IRQ)) { 81 if (pending & (1 << USB_IRQ)) {
82#endif 82#endif
83 do_IRQ(USB_IRQ, regs); 83 do_IRQ(USB_IRQ);
84 return; 84 return;
85 } 85 }
86 86
@@ -91,9 +91,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
91 if ((pending & (1 << TITAN_IRQ)) && msgint) { 91 if ((pending & (1 << TITAN_IRQ)) && msgint) {
92 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10)); 92 ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
93#if defined(CONFIG_KGDB) 93#if defined(CONFIG_KGDB)
94 excite_kgdb_inthdl(regs); 94 excite_kgdb_inthdl();
95#endif 95#endif
96 do_IRQ(TITAN_IRQ, regs); 96 do_IRQ(TITAN_IRQ);
97 return; 97 return;
98 } 98 }
99 99
@@ -102,7 +102,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
102 msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10)); 102 msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
103 msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20)); 103 msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
104 if ((pending & (1 << FPGA0_IRQ)) && msgint) { 104 if ((pending & (1 << FPGA0_IRQ)) && msgint) {
105 do_IRQ(FPGA0_IRQ, regs); 105 do_IRQ(FPGA0_IRQ);
106 return; 106 return;
107 } 107 }
108 108
@@ -111,7 +111,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
111 msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10)); 111 msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
112 msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20)); 112 msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
113 if ((pending & (1 << FPGA1_IRQ)) && msgint) { 113 if ((pending & (1 << FPGA1_IRQ)) && msgint) {
114 do_IRQ(FPGA1_IRQ, regs); 114 do_IRQ(FPGA1_IRQ);
115 return; 115 return;
116 } 116 }
117 117
@@ -120,10 +120,10 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
120 msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10)); 120 msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
121 msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20)); 121 msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
122 if ((pending & (1 << PHY_IRQ)) && msgint) { 122 if ((pending & (1 << PHY_IRQ)) && msgint) {
123 do_IRQ(PHY_IRQ, regs); 123 do_IRQ(PHY_IRQ);
124 return; 124 return;
125 } 125 }
126 126
127 /* Process spurious interrupts */ 127 /* Process spurious interrupts */
128 spurious_interrupt(regs); 128 spurious_interrupt();
129} 129}
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 0b75f4fb7195..1117fab19733 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -42,7 +42,7 @@
42 * 15 - IDE1 42 * 15 - IDE1
43 */ 43 */
44 44
45static inline void galileo_irq(struct pt_regs *regs) 45static inline void galileo_irq(void)
46{ 46{
47 unsigned int mask, pending, devfn; 47 unsigned int mask, pending, devfn;
48 48
@@ -52,7 +52,7 @@ static inline void galileo_irq(struct pt_regs *regs)
52 if (pending & GALILEO_INTR_T0EXP) { 52 if (pending & GALILEO_INTR_T0EXP) {
53 53
54 GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS); 54 GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
55 do_IRQ(COBALT_GALILEO_IRQ, regs); 55 do_IRQ(COBALT_GALILEO_IRQ);
56 56
57 } else if (pending & GALILEO_INTR_RETRY_CTR) { 57 } else if (pending & GALILEO_INTR_RETRY_CTR) {
58 58
@@ -68,44 +68,31 @@ static inline void galileo_irq(struct pt_regs *regs)
68 } 68 }
69} 69}
70 70
71static inline void via_pic_irq(struct pt_regs *regs) 71static inline void via_pic_irq(void)
72{ 72{
73 int irq; 73 int irq;
74 74
75 irq = i8259_irq(); 75 irq = i8259_irq();
76 if (irq >= 0) 76 if (irq >= 0)
77 do_IRQ(irq, regs); 77 do_IRQ(irq);
78} 78}
79 79
80asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 80asmlinkage void plat_irq_dispatch(void)
81{ 81{
82 unsigned pending; 82 unsigned pending = read_c0_status() & read_c0_cause();
83 83
84 pending = read_c0_status() & read_c0_cause(); 84 if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
85 85 galileo_irq();
86 if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ 86 else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
87 87 via_pic_irq();
88 galileo_irq(regs); 88 else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
89 89 do_IRQ(COBALT_CPU_IRQ + 3);
90 else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ 90 else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
91 91 do_IRQ(COBALT_CPU_IRQ + 4);
92 via_pic_irq(regs); 92 else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
93 93 do_IRQ(COBALT_CPU_IRQ + 5);
94 else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ 94 else if (pending & CAUSEF_IP7) /* IRQ 23 */
95 95 do_IRQ(COBALT_CPU_IRQ + 7);
96 do_IRQ(COBALT_CPU_IRQ + 3, regs);
97
98 else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
99
100 do_IRQ(COBALT_CPU_IRQ + 4, regs);
101
102 else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
103
104 do_IRQ(COBALT_CPU_IRQ + 5, regs);
105
106 else if (pending & CAUSEF_IP7) /* IRQ 23 */
107
108 do_IRQ(COBALT_CPU_IRQ + 7, regs);
109} 96}
110 97
111static struct irqaction irq_via = { 98static struct irqaction irq_via = {
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c
index 513fc6722d84..a8bd2e66705c 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq.c
@@ -153,8 +153,7 @@ u8 i8259_interrupt_ack(void)
153 * the first level int-handler will jump here if it is a vrc5477 irq 153 * the first level int-handler will jump here if it is a vrc5477 irq
154 */ 154 */
155#define NUM_5477_IRQS 32 155#define NUM_5477_IRQS 32
156static void 156static void vrc5477_irq_dispatch(void)
157vrc5477_irq_dispatch(struct pt_regs *regs)
158{ 157{
159 u32 intStatus; 158 u32 intStatus;
160 u32 bitmask; 159 u32 bitmask;
@@ -178,7 +177,7 @@ vrc5477_irq_dispatch(struct pt_regs *regs)
178 /* check for i8259 interrupts */ 177 /* check for i8259 interrupts */
179 if (intStatus & (1 << VRC5477_I8259_CASCADE)) { 178 if (intStatus & (1 << VRC5477_I8259_CASCADE)) {
180 int i8259_irq = i8259_interrupt_ack(); 179 int i8259_irq = i8259_interrupt_ack();
181 do_IRQ(I8259_IRQ_BASE + i8259_irq, regs); 180 do_IRQ(I8259_IRQ_BASE + i8259_irq);
182 return; 181 return;
183 } 182 }
184 } 183 }
@@ -186,7 +185,7 @@ vrc5477_irq_dispatch(struct pt_regs *regs)
186 for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) { 185 for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) {
187 /* do we need to "and" with the int mask? */ 186 /* do we need to "and" with the int mask? */
188 if (intStatus & bitmask) { 187 if (intStatus & bitmask) {
189 do_IRQ(VRC5477_IRQ_BASE + i, regs); 188 do_IRQ(VRC5477_IRQ_BASE + i);
190 return; 189 return;
191 } 190 }
192 } 191 }
@@ -194,18 +193,18 @@ vrc5477_irq_dispatch(struct pt_regs *regs)
194 193
195#define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6) 194#define VR5477INTS (STATUSF_IP2|STATUSF_IP3|STATUSF_IP4|STATUSF_IP5|STATUSF_IP6)
196 195
197asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 196asmlinkage void plat_irq_dispatch(void)
198{ 197{
199 unsigned int pending = read_c0_cause() & read_c0_status(); 198 unsigned int pending = read_c0_cause() & read_c0_status();
200 199
201 if (pending & STATUSF_IP7) 200 if (pending & STATUSF_IP7)
202 do_IRQ(CPU_IRQ_BASE + 7, regs); 201 do_IRQ(CPU_IRQ_BASE + 7);
203 else if (pending & VR5477INTS) 202 else if (pending & VR5477INTS)
204 vrc5477_irq_dispatch(regs); 203 vrc5477_irq_dispatch();
205 else if (pending & STATUSF_IP0) 204 else if (pending & STATUSF_IP0)
206 do_IRQ(CPU_IRQ_BASE, regs); 205 do_IRQ(CPU_IRQ_BASE);
207 else if (pending & STATUSF_IP1) 206 else if (pending & STATUSF_IP1)
208 do_IRQ(CPU_IRQ_BASE + 1, regs); 207 do_IRQ(CPU_IRQ_BASE + 1);
209 else 208 else
210 spurious_interrupt(regs); 209 spurious_interrupt();
211} 210}
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index 455a65b91cb0..55d60d5e0e86 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -264,8 +264,10 @@
264 srlv t3,t1,t2 264 srlv t3,t1,t2
265 265
266handle_it: 266handle_it:
267 LONG_L s0, TI_REGS($28)
268 LONG_S sp, TI_REGS($28)
267 jal do_IRQ 269 jal do_IRQ
268 move a1,sp 270 LONG_S s0, TI_REGS($28)
269 271
270 j ret_from_irq 272 j ret_from_irq
271 nop 273 nop
diff --git a/arch/mips/emma2rh/common/irq.c b/arch/mips/emma2rh/common/irq.c
index 3af57693c84c..c191b3e9d9d9 100644
--- a/arch/mips/emma2rh/common/irq.c
+++ b/arch/mips/emma2rh/common/irq.c
@@ -39,7 +39,7 @@
39/* 39/*
40 * the first level int-handler will jump here if it is a emma2rh irq 40 * the first level int-handler will jump here if it is a emma2rh irq
41 */ 41 */
42asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs) 42void emma2rh_irq_dispatch(void)
43{ 43{
44 u32 intStatus; 44 u32 intStatus;
45 u32 bitmask; 45 u32 bitmask;
@@ -56,7 +56,7 @@ asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
56 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); 56 & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
57 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { 57 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
58 if (swIntStatus & bitmask) { 58 if (swIntStatus & bitmask) {
59 do_IRQ(EMMA2RH_SW_IRQ_BASE + i, regs); 59 do_IRQ(EMMA2RH_SW_IRQ_BASE + i);
60 return; 60 return;
61 } 61 }
62 } 62 }
@@ -65,7 +65,7 @@ asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
65 65
66 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { 66 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
67 if (intStatus & bitmask) { 67 if (intStatus & bitmask) {
68 do_IRQ(EMMA2RH_IRQ_BASE + i, regs); 68 do_IRQ(EMMA2RH_IRQ_BASE + i);
69 return; 69 return;
70 } 70 }
71 } 71 }
@@ -81,7 +81,7 @@ asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
81 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK); 81 & emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
82 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { 82 for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
83 if (gpioIntStatus & bitmask) { 83 if (gpioIntStatus & bitmask) {
84 do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i, regs); 84 do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i);
85 return; 85 return;
86 } 86 }
87 } 87 }
@@ -90,7 +90,7 @@ asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
90 90
91 for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) { 91 for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
92 if (intStatus & bitmask) { 92 if (intStatus & bitmask) {
93 do_IRQ(EMMA2RH_IRQ_BASE + i, regs); 93 do_IRQ(EMMA2RH_IRQ_BASE + i);
94 return; 94 return;
95 } 95 }
96 } 96 }
@@ -100,7 +100,7 @@ asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
100 100
101 for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) { 101 for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
102 if (intStatus & bitmask) { 102 if (intStatus & bitmask) {
103 do_IRQ(EMMA2RH_IRQ_BASE + i, regs); 103 do_IRQ(EMMA2RH_IRQ_BASE + i);
104 return; 104 return;
105 } 105 }
106 } 106 }
diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c
index 2a736be42c8c..c93369cb4115 100644
--- a/arch/mips/emma2rh/markeins/irq.c
+++ b/arch/mips/emma2rh/markeins/irq.c
@@ -57,7 +57,7 @@
57extern void emma2rh_sw_irq_init(u32 base); 57extern void emma2rh_sw_irq_init(u32 base);
58extern void emma2rh_gpio_irq_init(u32 base); 58extern void emma2rh_gpio_irq_init(u32 base);
59extern void emma2rh_irq_init(u32 base); 59extern void emma2rh_irq_init(u32 base);
60extern asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs); 60extern void emma2rh_irq_dispatch(void);
61 61
62static struct irqaction irq_cascade = { 62static struct irqaction irq_cascade = {
63 .handler = no_action, 63 .handler = no_action,
@@ -114,20 +114,20 @@ void __init arch_init_irq(void)
114 setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade); 114 setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
115} 115}
116 116
117asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 117asmlinkage void plat_irq_dispatch(void)
118{ 118{
119 unsigned int pending = read_c0_status() & read_c0_cause(); 119 unsigned int pending = read_c0_status() & read_c0_cause();
120 120
121 if (pending & STATUSF_IP7) 121 if (pending & STATUSF_IP7)
122 do_IRQ(CPU_IRQ_BASE + 7, regs); 122 do_IRQ(CPU_IRQ_BASE + 7);
123 else if (pending & STATUSF_IP2) 123 else if (pending & STATUSF_IP2)
124 emma2rh_irq_dispatch(regs); 124 emma2rh_irq_dispatch();
125 else if (pending & STATUSF_IP1) 125 else if (pending & STATUSF_IP1)
126 do_IRQ(CPU_IRQ_BASE + 1, regs); 126 do_IRQ(CPU_IRQ_BASE + 1);
127 else if (pending & STATUSF_IP0) 127 else if (pending & STATUSF_IP0)
128 do_IRQ(CPU_IRQ_BASE + 0, regs); 128 do_IRQ(CPU_IRQ_BASE + 0);
129 else 129 else
130 spurious_interrupt(regs); 130 spurious_interrupt();
131} 131}
132 132
133 133
diff --git a/arch/mips/gt64120/common/time.c b/arch/mips/gt64120/common/time.c
index 7feca49350d1..b203169f19ce 100644
--- a/arch/mips/gt64120/common/time.c
+++ b/arch/mips/gt64120/common/time.c
@@ -10,6 +10,7 @@
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/sched.h> 11#include <linux/sched.h>
12#include <linux/kernel_stat.h> 12#include <linux/kernel_stat.h>
13#include <asm/irq_regs.h>
13#include <asm/ptrace.h> 14#include <asm/ptrace.h>
14#include <asm/gt64120.h> 15#include <asm/gt64120.h>
15 16
@@ -19,7 +20,7 @@
19 * differently than other MIPS interrupts. 20 * differently than other MIPS interrupts.
20 */ 21 */
21 22
22static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs) 23static void gt64120_irq(int irq, void *dev_id)
23{ 24{
24 unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask; 25 unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask;
25 int handled = 0; 26 int handled = 0;
@@ -36,7 +37,7 @@ static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs)
36 irq_src &= ~0x00000800; 37 irq_src &= ~0x00000800;
37 do_timer(1); 38 do_timer(1);
38#ifndef CONFIG_SMP 39#ifndef CONFIG_SMP
39 update_process_times(user_mode(regs)); 40 update_process_times(user_mode(get_irq_regs()));
40#endif 41#endif
41 } 42 }
42 43
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
index 5d939ac58f3f..ed4d82b9a24a 100644
--- a/arch/mips/gt64120/ev64120/irq.c
+++ b/arch/mips/gt64120/ev64120/irq.c
@@ -46,22 +46,22 @@
46#include <asm/system.h> 46#include <asm/system.h>
47#include <asm/gt64120.h> 47#include <asm/gt64120.h>
48 48
49asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 49asmlinkage void plat_irq_dispatch(void)
50{ 50{
51 unsigned int pending = read_c0_status() & read_c0_cause(); 51 unsigned int pending = read_c0_status() & read_c0_cause();
52 52
53 if (pending & STATUSF_IP4) /* int2 hardware line (timer) */ 53 if (pending & STATUSF_IP4) /* int2 hardware line (timer) */
54 do_IRQ(4, regs); 54 do_IRQ(4);
55 else if (pending & STATUSF_IP2) /* int0 hardware line */ 55 else if (pending & STATUSF_IP2) /* int0 hardware line */
56 do_IRQ(GT_INTA, regs); 56 do_IRQ(GT_INTA);
57 else if (pending & STATUSF_IP5) /* int3 hardware line */ 57 else if (pending & STATUSF_IP5) /* int3 hardware line */
58 do_IRQ(GT_INTD, regs); 58 do_IRQ(GT_INTD);
59 else if (pending & STATUSF_IP6) /* int4 hardware line */ 59 else if (pending & STATUSF_IP6) /* int4 hardware line */
60 do_IRQ(6, regs); 60 do_IRQ(6);
61 else if (pending & STATUSF_IP7) /* compare int */ 61 else if (pending & STATUSF_IP7) /* compare int */
62 do_IRQ(7, regs); 62 do_IRQ(7);
63 else 63 else
64 spurious_interrupt(regs); 64 spurious_interrupt();
65} 65}
66 66
67static void disable_ev64120_irq(unsigned int irq_nr) 67static void disable_ev64120_irq(unsigned int irq_nr)
diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c
index 885f67f32ea3..d9294401ccb0 100644
--- a/arch/mips/gt64120/momenco_ocelot/irq.c
+++ b/arch/mips/gt64120/momenco_ocelot/irq.c
@@ -48,22 +48,22 @@
48#include <asm/mipsregs.h> 48#include <asm/mipsregs.h>
49#include <asm/system.h> 49#include <asm/system.h>
50 50
51asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 51asmlinkage void plat_irq_dispatch(void)
52{ 52{
53 unsigned int pending = read_c0_status() & read_c0_cause(); 53 unsigned int pending = read_c0_status() & read_c0_cause();
54 54
55 if (pending & STATUSF_IP2) /* int0 hardware line */ 55 if (pending & STATUSF_IP2) /* int0 hardware line */
56 do_IRQ(2, regs); 56 do_IRQ(2);
57 else if (pending & STATUSF_IP3) /* int1 hardware line */ 57 else if (pending & STATUSF_IP3) /* int1 hardware line */
58 do_IRQ(3, regs); 58 do_IRQ(3);
59 else if (pending & STATUSF_IP4) /* int2 hardware line */ 59 else if (pending & STATUSF_IP4) /* int2 hardware line */
60 do_IRQ(4, regs); 60 do_IRQ(4);
61 else if (pending & STATUSF_IP5) /* int3 hardware line */ 61 else if (pending & STATUSF_IP5) /* int3 hardware line */
62 do_IRQ(5, regs); 62 do_IRQ(5);
63 else if (pending & STATUSF_IP6) /* int4 hardware line */ 63 else if (pending & STATUSF_IP6) /* int4 hardware line */
64 do_IRQ(6, regs); 64 do_IRQ(6);
65 else if (pending & STATUSF_IP7) /* cpu timer */ 65 else if (pending & STATUSF_IP7) /* cpu timer */
66 do_IRQ(7, regs); 66 do_IRQ(7);
67 else { 67 else {
68 /* 68 /*
69 * Now look at the extended interrupts 69 * Now look at the extended interrupts
@@ -71,13 +71,13 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
71 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; 71 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
72 72
73 if (pending & STATUSF_IP8) /* int6 hardware line */ 73 if (pending & STATUSF_IP8) /* int6 hardware line */
74 do_IRQ(8, regs); 74 do_IRQ(8);
75 else if (pending & STATUSF_IP9) /* int7 hardware line */ 75 else if (pending & STATUSF_IP9) /* int7 hardware line */
76 do_IRQ(9, regs); 76 do_IRQ(9);
77 else if (pending & STATUSF_IP10) /* int8 hardware line */ 77 else if (pending & STATUSF_IP10) /* int8 hardware line */
78 do_IRQ(10, regs); 78 do_IRQ(10);
79 else if (pending & STATUSF_IP11) /* int9 hardware line */ 79 else if (pending & STATUSF_IP11) /* int9 hardware line */
80 do_IRQ(11, regs); 80 do_IRQ(11);
81 } 81 }
82} 82}
83 83
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c
index 8d75a43ce877..eedfc24e1eae 100644
--- a/arch/mips/gt64120/wrppmc/irq.c
+++ b/arch/mips/gt64120/wrppmc/irq.c
@@ -30,18 +30,18 @@
30#include <asm/irq_cpu.h> 30#include <asm/irq_cpu.h>
31#include <asm/gt64120.h> 31#include <asm/gt64120.h>
32 32
33asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 33asmlinkage void plat_irq_dispatch(void)
34{ 34{
35 unsigned int pending = read_c0_status() & read_c0_cause(); 35 unsigned int pending = read_c0_status() & read_c0_cause();
36 36
37 if (pending & STATUSF_IP7) 37 if (pending & STATUSF_IP7)
38 do_IRQ(WRPPMC_MIPS_TIMER_IRQ, regs); /* CPU Compare/Count internal timer */ 38 do_IRQ(WRPPMC_MIPS_TIMER_IRQ); /* CPU Compare/Count internal timer */
39 else if (pending & STATUSF_IP6) 39 else if (pending & STATUSF_IP6)
40 do_IRQ(WRPPMC_UART16550_IRQ, regs); /* UART 16550 port */ 40 do_IRQ(WRPPMC_UART16550_IRQ); /* UART 16550 port */
41 else if (pending & STATUSF_IP3) 41 else if (pending & STATUSF_IP3)
42 do_IRQ(WRPPMC_PCI_INTA_IRQ, regs); /* PCI INT_A */ 42 do_IRQ(WRPPMC_PCI_INTA_IRQ); /* PCI INT_A */
43 else 43 else
44 spurious_interrupt(regs); 44 spurious_interrupt();
45} 45}
46 46
47/** 47/**
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index eef05093deb4..d5bd6b3a0933 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -94,26 +94,26 @@ void __init arch_init_irq(void)
94 change_c0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1); 94 change_c0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1);
95} 95}
96 96
97static void loc_call(unsigned int irq, struct pt_regs *regs, unsigned int mask) 97static void loc_call(unsigned int irq, unsigned int mask)
98{ 98{
99 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 99 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE,
100 r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) & mask); 100 r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) & mask);
101 do_IRQ(irq, regs); 101 do_IRQ(irq);
102 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 102 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE,
103 r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) | mask); 103 r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) | mask);
104} 104}
105 105
106static void ll_local_dev(struct pt_regs *regs) 106static void ll_local_dev(void)
107{ 107{
108 switch (r4030_read_reg32(JAZZ_IO_IRQ_SOURCE)) { 108 switch (r4030_read_reg32(JAZZ_IO_IRQ_SOURCE)) {
109 case 0: 109 case 0:
110 panic("Unimplemented loc_no_irq handler"); 110 panic("Unimplemented loc_no_irq handler");
111 break; 111 break;
112 case 4: 112 case 4:
113 loc_call(JAZZ_PARALLEL_IRQ, regs, JAZZ_IE_PARALLEL); 113 loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_PARALLEL);
114 break; 114 break;
115 case 8: 115 case 8:
116 loc_call(JAZZ_PARALLEL_IRQ, regs, JAZZ_IE_FLOPPY); 116 loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_FLOPPY);
117 break; 117 break;
118 case 12: 118 case 12:
119 panic("Unimplemented loc_sound handler"); 119 panic("Unimplemented loc_sound handler");
@@ -122,27 +122,27 @@ static void ll_local_dev(struct pt_regs *regs)
122 panic("Unimplemented loc_video handler"); 122 panic("Unimplemented loc_video handler");
123 break; 123 break;
124 case 20: 124 case 20:
125 loc_call(JAZZ_ETHERNET_IRQ, regs, JAZZ_IE_ETHERNET); 125 loc_call(JAZZ_ETHERNET_IRQ, JAZZ_IE_ETHERNET);
126 break; 126 break;
127 case 24: 127 case 24:
128 loc_call(JAZZ_SCSI_IRQ, regs, JAZZ_IE_SCSI); 128 loc_call(JAZZ_SCSI_IRQ, JAZZ_IE_SCSI);
129 break; 129 break;
130 case 28: 130 case 28:
131 loc_call(JAZZ_KEYBOARD_IRQ, regs, JAZZ_IE_KEYBOARD); 131 loc_call(JAZZ_KEYBOARD_IRQ, JAZZ_IE_KEYBOARD);
132 break; 132 break;
133 case 32: 133 case 32:
134 loc_call(JAZZ_MOUSE_IRQ, regs, JAZZ_IE_MOUSE); 134 loc_call(JAZZ_MOUSE_IRQ, JAZZ_IE_MOUSE);
135 break; 135 break;
136 case 36: 136 case 36:
137 loc_call(JAZZ_SERIAL1_IRQ, regs, JAZZ_IE_SERIAL1); 137 loc_call(JAZZ_SERIAL1_IRQ, JAZZ_IE_SERIAL1);
138 break; 138 break;
139 case 40: 139 case 40:
140 loc_call(JAZZ_SERIAL2_IRQ, regs, JAZZ_IE_SERIAL2); 140 loc_call(JAZZ_SERIAL2_IRQ, JAZZ_IE_SERIAL2);
141 break; 141 break;
142 } 142 }
143} 143}
144 144
145asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 145asmlinkage void plat_irq_dispatch(void)
146{ 146{
147 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 147 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
148 148
@@ -150,13 +150,13 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
150 write_c0_compare(0); 150 write_c0_compare(0);
151 else if (pending & IE_IRQ4) { 151 else if (pending & IE_IRQ4) {
152 r4030_read_reg32(JAZZ_TIMER_REGISTER); 152 r4030_read_reg32(JAZZ_TIMER_REGISTER);
153 do_IRQ(JAZZ_TIMER_IRQ, regs); 153 do_IRQ(JAZZ_TIMER_IRQ);
154 } else if (pending & IE_IRQ3) 154 } else if (pending & IE_IRQ3)
155 panic("Unimplemented ISA NMI handler"); 155 panic("Unimplemented ISA NMI handler");
156 else if (pending & IE_IRQ2) 156 else if (pending & IE_IRQ2)
157 do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK), regs); 157 do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK));
158 else if (pending & IE_IRQ1) { 158 else if (pending & IE_IRQ1) {
159 ll_local_dev(regs); 159 ll_local_dev();
160 } else if (unlikely(pending & IE_IRQ0)) 160 } else if (unlikely(pending & IE_IRQ0))
161 panic("Unimplemented local_dma handler"); 161 panic("Unimplemented local_dma handler");
162 else if (pending & IE_SW1) { 162 else if (pending & IE_SW1) {
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index 722174481467..39a0243bed9a 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -46,6 +46,7 @@
46#include <linux/smp_lock.h> 46#include <linux/smp_lock.h>
47#include <linux/bitops.h> 47#include <linux/bitops.h>
48 48
49#include <asm/irq_regs.h>
49#include <asm/io.h> 50#include <asm/io.h>
50#include <asm/mipsregs.h> 51#include <asm/mipsregs.h>
51#include <asm/system.h> 52#include <asm/system.h>
@@ -239,45 +240,80 @@ struct tb_irq_space jmr3927_ioc_irqspace = {
239 .space_id = 0, 240 .space_id = 0,
240 can_share : 1 241 can_share : 1
241}; 242};
243
242struct tb_irq_space jmr3927_irc_irqspace = { 244struct tb_irq_space jmr3927_irc_irqspace = {
243 .next = NULL, 245 .next = NULL,
244 .start_irqno = JMR3927_IRQ_IRC, 246 .start_irqno = JMR3927_IRQ_IRC,
245 nr_irqs : JMR3927_NR_IRQ_IRC, 247 .nr_irqs = JMR3927_NR_IRQ_IRC,
246 .mask_func = mask_irq_irc, 248 .mask_func = mask_irq_irc,
247 .unmask_func = unmask_irq_irc, 249 .unmask_func = unmask_irq_irc,
248 .name = "on-chip", 250 .name = "on-chip",
249 .space_id = 0, 251 .space_id = 0,
250 can_share : 0 252 .can_share = 0
251}; 253};
252 254
253void jmr3927_spurious(struct pt_regs *regs) 255
256#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
257static int tx_branch_likely_bug_count = 0;
258static int have_tx_branch_likely_bug = 0;
259
260static void tx_branch_likely_bug_fixup(void)
261{
262 struct pt_regs *regs = get_irq_regs();
263
264 /* TX39/49-BUG: Under this condition, the insn in delay slot
265 of the branch likely insn is executed (not nullified) even
266 the branch condition is false. */
267 if (!have_tx_branch_likely_bug)
268 return;
269 if ((regs->cp0_epc & 0xfff) == 0xffc &&
270 KSEGX(regs->cp0_epc) != KSEG0 &&
271 KSEGX(regs->cp0_epc) != KSEG1) {
272 unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
273 /* beql,bnel,blezl,bgtzl */
274 /* bltzl,bgezl,blezall,bgezall */
275 /* bczfl, bcztl */
276 if ((insn & 0xf0000000) == 0x50000000 ||
277 (insn & 0xfc0e0000) == 0x04020000 ||
278 (insn & 0xf3fe0000) == 0x41020000) {
279 regs->cp0_epc -= 4;
280 tx_branch_likely_bug_count++;
281 printk(KERN_INFO
282 "fix branch-likery bug in %s (insn %08x)\n",
283 current->comm, insn);
284 }
285 }
286}
287#endif
288
289static void jmr3927_spurious(void)
254{ 290{
255#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND 291#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
256 tx_branch_likely_bug_fixup(regs); 292 tx_branch_likely_bug_fixup();
257#endif 293#endif
258 printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n", 294 printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
259 regs->cp0_cause, regs->cp0_epc, regs->regs[31]); 295 regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
260} 296}
261 297
262asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 298asmlinkage void plat_irq_dispatch(void)
263{ 299{
264 int irq; 300 int irq;
265 301
266#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND 302#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
267 tx_branch_likely_bug_fixup(regs); 303 tx_branch_likely_bug_fixup();
268#endif 304#endif
269 if ((regs->cp0_cause & CAUSEF_IP7) == 0) { 305 if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
270#if 0 306#if 0
271 jmr3927_spurious(regs); 307 jmr3927_spurious();
272#endif 308#endif
273 return; 309 return;
274 } 310 }
275 irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f; 311 irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
276 312
277 do_IRQ(irq + JMR3927_IRQ_IRC, regs); 313 do_IRQ(irq + JMR3927_IRQ_IRC);
278} 314}
279 315
280static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs) 316static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id)
281{ 317{
282 unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR); 318 unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
283 int i; 319 int i;
@@ -285,7 +321,7 @@ static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *
285 for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) { 321 for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
286 if (istat & (1 << i)) { 322 if (istat & (1 << i)) {
287 irq = JMR3927_IRQ_IOC + i; 323 irq = JMR3927_IRQ_IOC + i;
288 do_IRQ(irq, regs); 324 do_IRQ(irq);
289 } 325 }
290 } 326 }
291 return IRQ_HANDLED; 327 return IRQ_HANDLED;
@@ -295,7 +331,7 @@ static struct irqaction ioc_action = {
295 jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL, 331 jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL,
296}; 332};
297 333
298static irqreturn_t jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs) 334static irqreturn_t jmr3927_isac_interrupt(int irq, void *dev_id)
299{ 335{
300 unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR); 336 unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
301 int i; 337 int i;
@@ -303,7 +339,7 @@ static irqreturn_t jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs
303 for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) { 339 for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
304 if (istat & (1 << i)) { 340 if (istat & (1 << i)) {
305 irq = JMR3927_IRQ_ISAC + i; 341 irq = JMR3927_IRQ_ISAC + i;
306 do_IRQ(irq, regs); 342 do_IRQ(irq);
307 } 343 }
308 } 344 }
309 return IRQ_HANDLED; 345 return IRQ_HANDLED;
@@ -314,7 +350,7 @@ static struct irqaction isac_action = {
314}; 350};
315 351
316 352
317static irqreturn_t jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * regs) 353static irqreturn_t jmr3927_isaerr_interrupt(int irq, void *dev_id)
318{ 354{
319 printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq); 355 printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
320 356
@@ -324,7 +360,7 @@ static struct irqaction isaerr_action = {
324 jmr3927_isaerr_interrupt, 0, CPU_MASK_NONE, "ISA error", NULL, NULL, 360 jmr3927_isaerr_interrupt, 0, CPU_MASK_NONE, "ISA error", NULL, NULL,
325}; 361};
326 362
327static irqreturn_t jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs) 363static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
328{ 364{
329 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); 365 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
330 printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n", 366 printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
@@ -439,33 +475,3 @@ void jmr3927_irq_init(u32 irq_base)
439 475
440 jmr3927_irq_base = irq_base; 476 jmr3927_irq_base = irq_base;
441} 477}
442
443#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
444static int tx_branch_likely_bug_count = 0;
445static int have_tx_branch_likely_bug = 0;
446void tx_branch_likely_bug_fixup(struct pt_regs *regs)
447{
448 /* TX39/49-BUG: Under this condition, the insn in delay slot
449 of the branch likely insn is executed (not nullified) even
450 the branch condition is false. */
451 if (!have_tx_branch_likely_bug)
452 return;
453 if ((regs->cp0_epc & 0xfff) == 0xffc &&
454 KSEGX(regs->cp0_epc) != KSEG0 &&
455 KSEGX(regs->cp0_epc) != KSEG1) {
456 unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
457 /* beql,bnel,blezl,bgtzl */
458 /* bltzl,bgezl,blezall,bgezall */
459 /* bczfl, bcztl */
460 if ((insn & 0xf0000000) == 0x50000000 ||
461 (insn & 0xfc0e0000) == 0x04020000 ||
462 (insn & 0xf3fe0000) == 0x41020000) {
463 regs->cp0_epc -= 4;
464 tx_branch_likely_bug_count++;
465 printk(KERN_INFO
466 "fix branch-likery bug in %s (insn %08x)\n",
467 current->comm, insn);
468 }
469 }
470}
471#endif
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index ec28077d5ee2..e9ce5b3721af 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -93,11 +93,12 @@ void output_thread_info_defines(void)
93 offset("#define TI_TASK ", struct thread_info, task); 93 offset("#define TI_TASK ", struct thread_info, task);
94 offset("#define TI_EXEC_DOMAIN ", struct thread_info, exec_domain); 94 offset("#define TI_EXEC_DOMAIN ", struct thread_info, exec_domain);
95 offset("#define TI_FLAGS ", struct thread_info, flags); 95 offset("#define TI_FLAGS ", struct thread_info, flags);
96 offset("#define TI_TP_VALUE ", struct thread_info, tp_value);
96 offset("#define TI_CPU ", struct thread_info, cpu); 97 offset("#define TI_CPU ", struct thread_info, cpu);
97 offset("#define TI_PRE_COUNT ", struct thread_info, preempt_count); 98 offset("#define TI_PRE_COUNT ", struct thread_info, preempt_count);
98 offset("#define TI_ADDR_LIMIT ", struct thread_info, addr_limit); 99 offset("#define TI_ADDR_LIMIT ", struct thread_info, addr_limit);
99 offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block); 100 offset("#define TI_RESTART_BLOCK ", struct thread_info, restart_block);
100 offset("#define TI_TP_VALUE ", struct thread_info, tp_value); 101 offset("#define TI_REGS ", struct thread_info, regs);
101 constant("#define _THREAD_SIZE_ORDER ", THREAD_SIZE_ORDER); 102 constant("#define _THREAD_SIZE_ORDER ", THREAD_SIZE_ORDER);
102 constant("#define _THREAD_SIZE ", THREAD_SIZE); 103 constant("#define _THREAD_SIZE ", THREAD_SIZE);
103 constant("#define _THREAD_MASK ", THREAD_MASK); 104 constant("#define _THREAD_MASK ", THREAD_MASK);
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index 766655f35250..e93e43e1f42d 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -79,7 +79,6 @@ FEXPORT(syscall_exit)
79FEXPORT(restore_all) # restore full frame 79FEXPORT(restore_all) # restore full frame
80#ifdef CONFIG_MIPS_MT_SMTC 80#ifdef CONFIG_MIPS_MT_SMTC
81/* Detect and execute deferred IPI "interrupts" */ 81/* Detect and execute deferred IPI "interrupts" */
82 move a0,sp
83 jal deferred_smtc_ipi 82 jal deferred_smtc_ipi
84/* Re-arm any temporarily masked interrupts not explicitly "acked" */ 83/* Re-arm any temporarily masked interrupts not explicitly "acked" */
85 mfc0 v0, CP0_TCSTATUS 84 mfc0 v0, CP0_TCSTATUS
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index af6ef2fd8300..50ed77297728 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -131,9 +131,11 @@ NESTED(handle_int, PT_SIZE, sp)
131 CLI 131 CLI
132 TRACE_IRQS_OFF 132 TRACE_IRQS_OFF
133 133
134 PTR_LA ra, ret_from_irq 134 LONG_L s0, TI_REGS($28)
135 move a0, sp 135 LONG_S sp, TI_REGS($28)
136 j plat_irq_dispatch 136 jal plat_irq_dispatch
137 LONG_S s0, TI_REGS($28)
138 j ret_from_irq
137 END(handle_int) 139 END(handle_int)
138 140
139 __INIT 141 __INIT
@@ -219,9 +221,12 @@ NESTED(except_vec_vi_handler, 0, sp)
219#endif /* CONFIG_MIPS_MT_SMTC */ 221#endif /* CONFIG_MIPS_MT_SMTC */
220 CLI 222 CLI
221 TRACE_IRQS_OFF 223 TRACE_IRQS_OFF
222 move a0, sp 224
225 LONG_L s0, TI_REGS($28)
226 LONG_S sp, TI_REGS($28)
227 jalr v0
228 LONG_S s0, TI_REGS($28)
223 PTR_LA ra, ret_from_irq 229 PTR_LA ra, ret_from_irq
224 jr v0
225 END(except_vec_vi_handler) 230 END(except_vec_vi_handler)
226 231
227/* 232/*
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 63dfeb41796b..71e8e45f3687 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -115,14 +115,14 @@ static void end_msc_irq(unsigned int irq)
115/* 115/*
116 * Interrupt handler for interrupts coming from SOC-it. 116 * Interrupt handler for interrupts coming from SOC-it.
117 */ 117 */
118void ll_msc_irq(struct pt_regs *regs) 118void ll_msc_irq(void)
119{ 119{
120 unsigned int irq; 120 unsigned int irq;
121 121
122 /* read the interrupt vector register */ 122 /* read the interrupt vector register */
123 MSCIC_READ(MSC01_IC_VEC, irq); 123 MSCIC_READ(MSC01_IC_VEC, irq);
124 if (irq < 64) 124 if (irq < 64)
125 do_IRQ(irq + irq_base, regs); 125 do_IRQ(irq + irq_base);
126 else { 126 else {
127 /* Ignore spurious interrupt */ 127 /* Ignore spurious interrupt */
128 } 128 }
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index b117e64da64d..39c94fd8d8ba 100644
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -113,7 +113,7 @@ static void end_mv64340_irq(unsigned int irq)
113 * Interrupt handler for interrupts coming from the Marvell chip. 113 * Interrupt handler for interrupts coming from the Marvell chip.
114 * It could be built in ethernet ports etc... 114 * It could be built in ethernet ports etc...
115 */ 115 */
116void ll_mv64340_irq(struct pt_regs *regs) 116void ll_mv64340_irq(void)
117{ 117{
118 unsigned int irq_src_low, irq_src_high; 118 unsigned int irq_src_low, irq_src_high;
119 unsigned int irq_mask_low, irq_mask_high; 119 unsigned int irq_mask_low, irq_mask_high;
@@ -129,9 +129,9 @@ void ll_mv64340_irq(struct pt_regs *regs)
129 irq_src_high &= irq_mask_high; 129 irq_src_high &= irq_mask_high;
130 130
131 if (irq_src_low) 131 if (irq_src_low)
132 do_IRQ(ls1bit32(irq_src_low) + irq_base, regs); 132 do_IRQ(ls1bit32(irq_src_low) + irq_base);
133 else 133 else
134 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32, regs); 134 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32);
135} 135}
136 136
137#define shutdown_mv64340_irq disable_mv64340_irq 137#define shutdown_mv64340_irq disable_mv64340_irq
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index a00b0e7ab9b1..dd24434392b6 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -53,9 +53,8 @@ unsigned long irq_hwmask[NR_IRQS];
53 * SMP cross-CPU interrupts have their own specific 53 * SMP cross-CPU interrupts have their own specific
54 * handlers). 54 * handlers).
55 */ 55 */
56asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs) 56asmlinkage unsigned int do_IRQ(unsigned int irq)
57{ 57{
58 struct pt_regs *old_regs = set_irq_regs(regs);
59 irq_enter(); 58 irq_enter();
60 59
61 __DO_IRQ_SMTC_HOOK(); 60 __DO_IRQ_SMTC_HOOK();
@@ -63,7 +62,6 @@ asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs)
63 62
64 irq_exit(); 63 irq_exit();
65 64
66 set_irq_regs(old_regs);
67 return 1; 65 return 1;
68} 66}
69 67
@@ -112,7 +110,7 @@ skip:
112 return 0; 110 return 0;
113} 111}
114 112
115asmlinkage void spurious_interrupt(struct pt_regs *regs) 113asmlinkage void spurious_interrupt(void)
116{ 114{
117 atomic_inc(&irq_err_count); 115 atomic_inc(&irq_err_count);
118} 116}
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index cdab1b2cd134..8c8c8324f775 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -61,16 +61,16 @@ static int sp_stopping = 0;
61 61
62extern void *vpe_get_shared(int index); 62extern void *vpe_get_shared(int index);
63 63
64static void rtlx_dispatch(struct pt_regs *regs) 64static void rtlx_dispatch(void)
65{ 65{
66 do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ, regs); 66 do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ);
67} 67}
68 68
69 69
70/* Interrupt handler may be called before rtlx_init has otherwise had 70/* Interrupt handler may be called before rtlx_init has otherwise had
71 a chance to run. 71 a chance to run.
72*/ 72*/
73static irqreturn_t rtlx_interrupt(int irq, void *dev_id, struct pt_regs *regs) 73static irqreturn_t rtlx_interrupt(int irq, void *dev_id)
74{ 74{
75 int i; 75 int i;
76 76
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 766253c44f3f..3b5f3b632622 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -106,22 +106,22 @@ void __init sanitize_tlb_entries(void)
106 clear_c0_mvpcontrol(MVPCONTROL_VPC); 106 clear_c0_mvpcontrol(MVPCONTROL_VPC);
107} 107}
108 108
109static void ipi_resched_dispatch (struct pt_regs *regs) 109static void ipi_resched_dispatch(void)
110{ 110{
111 do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ, regs); 111 do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
112} 112}
113 113
114static void ipi_call_dispatch (struct pt_regs *regs) 114static void ipi_call_dispatch(void)
115{ 115{
116 do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ, regs); 116 do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ);
117} 117}
118 118
119irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs) 119static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
120{ 120{
121 return IRQ_HANDLED; 121 return IRQ_HANDLED;
122} 122}
123 123
124irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs) 124static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
125{ 125{
126 smp_call_function_interrupt(); 126 smp_call_function_interrupt();
127 127
@@ -250,8 +250,8 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
250{ 250{
251 /* set up ipi interrupts */ 251 /* set up ipi interrupts */
252 if (cpu_has_vint) { 252 if (cpu_has_vint) {
253 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); 253 set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
254 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); 254 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
255 } 255 }
256 256
257 cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 257 cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 604bcc5cb7c8..cc1f7474f7d7 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -82,7 +82,7 @@ struct smtc_ipi_q freeIPIq;
82 82
83/* Forward declarations */ 83/* Forward declarations */
84 84
85void ipi_decode(struct pt_regs *, struct smtc_ipi *); 85void ipi_decode(struct smtc_ipi *);
86void post_direct_ipi(int cpu, struct smtc_ipi *pipi); 86void post_direct_ipi(int cpu, struct smtc_ipi *pipi);
87void setup_cross_vpe_interrupts(void); 87void setup_cross_vpe_interrupts(void);
88void init_smtc_stats(void); 88void init_smtc_stats(void);
@@ -820,19 +820,19 @@ void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
820 write_tc_c0_tcrestart(__smtc_ipi_vector); 820 write_tc_c0_tcrestart(__smtc_ipi_vector);
821} 821}
822 822
823void ipi_resched_interrupt(struct pt_regs *regs) 823static void ipi_resched_interrupt(void)
824{ 824{
825 /* Return from interrupt should be enough to cause scheduler check */ 825 /* Return from interrupt should be enough to cause scheduler check */
826} 826}
827 827
828 828
829void ipi_call_interrupt(struct pt_regs *regs) 829static void ipi_call_interrupt(void)
830{ 830{
831 /* Invoke generic function invocation code in smp.c */ 831 /* Invoke generic function invocation code in smp.c */
832 smp_call_function_interrupt(); 832 smp_call_function_interrupt();
833} 833}
834 834
835void ipi_decode(struct pt_regs *regs, struct smtc_ipi *pipi) 835void ipi_decode(struct smtc_ipi *pipi)
836{ 836{
837 void *arg_copy = pipi->arg; 837 void *arg_copy = pipi->arg;
838 int type_copy = pipi->type; 838 int type_copy = pipi->type;
@@ -846,15 +846,15 @@ void ipi_decode(struct pt_regs *regs, struct smtc_ipi *pipi)
846#ifdef SMTC_IDLE_HOOK_DEBUG 846#ifdef SMTC_IDLE_HOOK_DEBUG
847 clock_hang_reported[dest_copy] = 0; 847 clock_hang_reported[dest_copy] = 0;
848#endif /* SMTC_IDLE_HOOK_DEBUG */ 848#endif /* SMTC_IDLE_HOOK_DEBUG */
849 local_timer_interrupt(0, NULL, regs); 849 local_timer_interrupt(0, NULL);
850 break; 850 break;
851 case LINUX_SMP_IPI: 851 case LINUX_SMP_IPI:
852 switch ((int)arg_copy) { 852 switch ((int)arg_copy) {
853 case SMP_RESCHEDULE_YOURSELF: 853 case SMP_RESCHEDULE_YOURSELF:
854 ipi_resched_interrupt(regs); 854 ipi_resched_interrupt();
855 break; 855 break;
856 case SMP_CALL_FUNCTION: 856 case SMP_CALL_FUNCTION:
857 ipi_call_interrupt(regs); 857 ipi_call_interrupt();
858 break; 858 break;
859 default: 859 default:
860 printk("Impossible SMTC IPI Argument 0x%x\n", 860 printk("Impossible SMTC IPI Argument 0x%x\n",
@@ -868,7 +868,7 @@ void ipi_decode(struct pt_regs *regs, struct smtc_ipi *pipi)
868 } 868 }
869} 869}
870 870
871void deferred_smtc_ipi(struct pt_regs *regs) 871void deferred_smtc_ipi(void)
872{ 872{
873 struct smtc_ipi *pipi; 873 struct smtc_ipi *pipi;
874 unsigned long flags; 874 unsigned long flags;
@@ -883,7 +883,7 @@ void deferred_smtc_ipi(struct pt_regs *regs)
883 while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) { 883 while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) {
884 /* ipi_decode() should be called with interrupts off */ 884 /* ipi_decode() should be called with interrupts off */
885 local_irq_save(flags); 885 local_irq_save(flags);
886 ipi_decode(regs, pipi); 886 ipi_decode(pipi);
887 local_irq_restore(flags); 887 local_irq_restore(flags);
888 } 888 }
889 } 889 }
@@ -917,7 +917,7 @@ void smtc_timer_broadcast(int vpe)
917 917
918static int cpu_ipi_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_IRQ; 918static int cpu_ipi_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_IRQ;
919 919
920static irqreturn_t ipi_interrupt(int irq, void *dev_idm, struct pt_regs *regs) 920static irqreturn_t ipi_interrupt(int irq, void *dev_idm)
921{ 921{
922 int my_vpe = cpu_data[smp_processor_id()].vpe_id; 922 int my_vpe = cpu_data[smp_processor_id()].vpe_id;
923 int my_tc = cpu_data[smp_processor_id()].tc_id; 923 int my_tc = cpu_data[smp_processor_id()].tc_id;
@@ -978,7 +978,7 @@ static irqreturn_t ipi_interrupt(int irq, void *dev_idm, struct pt_regs *regs)
978 * with interrupts off 978 * with interrupts off
979 */ 979 */
980 local_irq_save(flags); 980 local_irq_save(flags);
981 ipi_decode(regs, pipi); 981 ipi_decode(pipi);
982 local_irq_restore(flags); 982 local_irq_restore(flags);
983 } 983 }
984 } 984 }
@@ -987,9 +987,9 @@ static irqreturn_t ipi_interrupt(int irq, void *dev_idm, struct pt_regs *regs)
987 return IRQ_HANDLED; 987 return IRQ_HANDLED;
988} 988}
989 989
990static void ipi_irq_dispatch(struct pt_regs *regs) 990static void ipi_irq_dispatch(void)
991{ 991{
992 do_IRQ(cpu_ipi_irq, regs); 992 do_IRQ(cpu_ipi_irq);
993} 993}
994 994
995static struct irqaction irq_ipi; 995static struct irqaction irq_ipi;
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index d349eb9e4ffb..debe86c2f691 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -324,8 +324,7 @@ static long last_rtc_update;
324 */ 324 */
325void local_timer_interrupt(int irq, void *dev_id) 325void local_timer_interrupt(int irq, void *dev_id)
326{ 326{
327 if (current->pid) 327 profile_tick(CPU_PROFILING);
328 profile_tick(CPU_PROFILING);
329 update_process_times(user_mode(get_irq_regs())); 328 update_process_times(user_mode(get_irq_regs()));
330} 329}
331 330
@@ -434,9 +433,8 @@ int (*perf_irq)(void) = null_perf_irq;
434EXPORT_SYMBOL(null_perf_irq); 433EXPORT_SYMBOL(null_perf_irq);
435EXPORT_SYMBOL(perf_irq); 434EXPORT_SYMBOL(perf_irq);
436 435
437asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs) 436asmlinkage void ll_timer_interrupt(int irq)
438{ 437{
439 struct pt_regs *old_regs = set_irq_regs(regs);
440 int r2 = cpu_has_mips_r2; 438 int r2 = cpu_has_mips_r2;
441 439
442 irq_enter(); 440 irq_enter();
@@ -458,12 +456,10 @@ asmlinkage void ll_timer_interrupt(int irq, struct pt_regs *regs)
458 456
459out: 457out:
460 irq_exit(); 458 irq_exit();
461 set_irq_regs(old_regs);
462} 459}
463 460
464asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs) 461asmlinkage void ll_local_timer_interrupt(int irq)
465{ 462{
466 struct pt_regs *old_regs = set_irq_regs(regs);
467 irq_enter(); 463 irq_enter();
468 if (smp_processor_id() != 0) 464 if (smp_processor_id() != 0)
469 kstat_this_cpu.irqs[irq]++; 465 kstat_this_cpu.irqs[irq]++;
@@ -472,7 +468,6 @@ asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs)
472 local_timer_interrupt(irq, NULL); 468 local_timer_interrupt(irq, NULL);
473 469
474 irq_exit(); 470 irq_exit();
475 set_irq_regs(old_regs);
476} 471}
477 472
478/* 473/*
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index 456be8fc961a..a144a002dcc4 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -108,14 +108,14 @@ static unsigned long get_int_status_200(void)
108 return int_status; 108 return int_status;
109} 109}
110 110
111asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 111asmlinkage void plat_irq_dispatch(void)
112{ 112{
113 unsigned long int_status; 113 unsigned long int_status;
114 unsigned int cause = read_c0_cause(); 114 unsigned int cause = read_c0_cause();
115 int irq; 115 int irq;
116 116
117 if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */ 117 if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */
118 ll_timer_interrupt(7, regs); 118 ll_timer_interrupt(7);
119 return; 119 return;
120 } 120 }
121 121
@@ -125,7 +125,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
125 if (int_status) { 125 if (int_status) {
126 irq = ls1bit32(int_status); 126 irq = ls1bit32(int_status);
127 127
128 do_IRQ(irq, regs); 128 do_IRQ(irq);
129 } 129 }
130} 130}
131 131
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index a020a3cb4f4b..be624b8c3b0e 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -101,7 +101,7 @@ static inline int ls1bit32(unsigned int x)
101 return b; 101 return b;
102} 102}
103 103
104static inline void atlas_hw0_irqdispatch(struct pt_regs *regs) 104static inline void atlas_hw0_irqdispatch(void)
105{ 105{
106 unsigned long int_status; 106 unsigned long int_status;
107 int irq; 107 int irq;
@@ -116,7 +116,7 @@ static inline void atlas_hw0_irqdispatch(struct pt_regs *regs)
116 116
117 DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq); 117 DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
118 118
119 do_IRQ(irq, regs); 119 do_IRQ(irq);
120} 120}
121 121
122static inline int clz(unsigned long x) 122static inline int clz(unsigned long x)
@@ -188,7 +188,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
188 * then we just return, if multiple IRQs are pending then we will just take 188 * then we just return, if multiple IRQs are pending then we will just take
189 * another exception, big deal. 189 * another exception, big deal.
190 */ 190 */
191asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 191asmlinkage void plat_irq_dispatch(void)
192{ 192{
193 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 193 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
194 int irq; 194 int irq;
@@ -196,11 +196,11 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
196 irq = irq_ffs(pending); 196 irq = irq_ffs(pending);
197 197
198 if (irq == MIPSCPU_INT_ATLAS) 198 if (irq == MIPSCPU_INT_ATLAS)
199 atlas_hw0_irqdispatch(regs); 199 atlas_hw0_irqdispatch();
200 else if (irq >= 0) 200 else if (irq >= 0)
201 do_IRQ(MIPSCPU_INT_BASE + irq, regs); 201 do_IRQ(MIPSCPU_INT_BASE + irq);
202 else 202 else
203 spurious_interrupt(regs); 203 spurious_interrupt();
204} 204}
205 205
206static inline void init_atlas_irqs (int base) 206static inline void init_atlas_irqs (int base)
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 8d15861fce61..d379000162f3 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -82,19 +82,19 @@ static inline void scroll_display_message(void)
82 } 82 }
83} 83}
84 84
85static void mips_timer_dispatch (struct pt_regs *regs) 85static void mips_timer_dispatch(void)
86{ 86{
87 do_IRQ (mips_cpu_timer_irq, regs); 87 do_IRQ(mips_cpu_timer_irq);
88} 88}
89 89
90/* 90/*
91 * Redeclare until I get around mopping the timer code insanity on MIPS. 91 * Redeclare until I get around mopping the timer code insanity on MIPS.
92 */ 92 */
93extern int null_perf_irq(struct pt_regs *regs); 93extern int null_perf_irq(void);
94 94
95extern int (*perf_irq)(struct pt_regs *regs); 95extern int (*perf_irq)(void);
96 96
97irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 97irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
98{ 98{
99 int cpu = smp_processor_id(); 99 int cpu = smp_processor_id();
100 100
@@ -119,7 +119,7 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
119 * perf counter overflow, or both. 119 * perf counter overflow, or both.
120 */ 120 */
121 if (read_c0_cause() & (1 << 26)) 121 if (read_c0_cause() & (1 << 26))
122 perf_irq(regs); 122 perf_irq();
123 123
124 if (read_c0_cause() & (1 << 30)) { 124 if (read_c0_cause() & (1 << 30)) {
125 /* If timer interrupt, make it de-assert */ 125 /* If timer interrupt, make it de-assert */
@@ -139,13 +139,13 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
139 * the tick on VPE 0 to run the full timer_interrupt(). 139 * the tick on VPE 0 to run the full timer_interrupt().
140 */ 140 */
141 if (cpu_data[cpu].vpe_id == 0) { 141 if (cpu_data[cpu].vpe_id == 0) {
142 timer_interrupt(irq, NULL, regs); 142 timer_interrupt(irq, NULL);
143 smtc_timer_broadcast(cpu_data[cpu].vpe_id); 143 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
144 scroll_display_message(); 144 scroll_display_message();
145 } else { 145 } else {
146 write_c0_compare(read_c0_count() + 146 write_c0_compare(read_c0_count() +
147 (mips_hpt_frequency/HZ)); 147 (mips_hpt_frequency/HZ));
148 local_timer_interrupt(irq, dev_id, regs); 148 local_timer_interrupt(irq, dev_id);
149 smtc_timer_broadcast(cpu_data[cpu].vpe_id); 149 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
150 } 150 }
151 } 151 }
@@ -159,12 +159,12 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
159 * timer int. 159 * timer int.
160 */ 160 */
161 if (!r2 || (read_c0_cause() & (1 << 26))) 161 if (!r2 || (read_c0_cause() & (1 << 26)))
162 if (perf_irq(regs)) 162 if (perf_irq())
163 goto out; 163 goto out;
164 164
165 /* we keep interrupt disabled all the time */ 165 /* we keep interrupt disabled all the time */
166 if (!r2 || (read_c0_cause() & (1 << 30))) 166 if (!r2 || (read_c0_cause() & (1 << 30)))
167 timer_interrupt(irq, NULL, regs); 167 timer_interrupt(irq, NULL);
168 168
169 scroll_display_message(); 169 scroll_display_message();
170 } else { 170 } else {
@@ -180,7 +180,7 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
180 /* 180 /*
181 * Other CPUs should do profiling and process accounting 181 * Other CPUs should do profiling and process accounting
182 */ 182 */
183 local_timer_interrupt(irq, dev_id, regs); 183 local_timer_interrupt(irq, dev_id);
184 } 184 }
185out: 185out:
186#endif /* CONFIG_MIPS_MT_SMTC */ 186#endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 7cc0ba4f553a..ed221dc7f6ac 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -114,7 +114,7 @@ static inline int get_int(void)
114 return irq; 114 return irq;
115} 115}
116 116
117static void malta_hw0_irqdispatch(struct pt_regs *regs) 117static void malta_hw0_irqdispatch(void)
118{ 118{
119 int irq; 119 int irq;
120 120
@@ -123,17 +123,21 @@ static void malta_hw0_irqdispatch(struct pt_regs *regs)
123 return; /* interrupt has already been cleared */ 123 return; /* interrupt has already been cleared */
124 } 124 }
125 125
126 do_IRQ(MALTA_INT_BASE+irq, regs); 126 do_IRQ(MALTA_INT_BASE + irq);
127} 127}
128 128
129void corehi_irqdispatch(struct pt_regs *regs) 129static void corehi_irqdispatch(void)
130{ 130{
131 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
132 unsigned int pcimstat, intisr, inten, intpol;
131 unsigned int intrcause,datalo,datahi; 133 unsigned int intrcause,datalo,datahi;
132 unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr; 134 struct pt_regs *regs;
133 135
134 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); 136 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
135 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n" 137 printk("epc : %08lx\nStatus: %08lx\n"
136, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr); 138 "Cause : %08lx\nbadVaddr : %08lx\n",
139 regs->cp0_epc, regs->cp0_status,
140 regs->cp0_cause, regs->cp0_badvaddr);
137 141
138 /* Read all the registers and then print them as there is a 142 /* Read all the registers and then print them as there is a
139 problem with interspersed printk's upsetting the Bonito controller. 143 problem with interspersed printk's upsetting the Bonito controller.
@@ -146,7 +150,7 @@ void corehi_irqdispatch(struct pt_regs *regs)
146 case MIPS_REVISION_CORID_CORE_FPGA3: 150 case MIPS_REVISION_CORID_CORE_FPGA3:
147 case MIPS_REVISION_CORID_CORE_24K: 151 case MIPS_REVISION_CORID_CORE_24K:
148 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 152 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
149 ll_msc_irq(regs); 153 ll_msc_irq();
150 break; 154 break;
151 case MIPS_REVISION_CORID_QED_RM5261: 155 case MIPS_REVISION_CORID_QED_RM5261:
152 case MIPS_REVISION_CORID_CORE_LV: 156 case MIPS_REVISION_CORID_CORE_LV:
@@ -255,7 +259,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
255 * another exception, big deal. 259 * another exception, big deal.
256 */ 260 */
257 261
258asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 262asmlinkage void plat_irq_dispatch(void)
259{ 263{
260 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 264 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
261 int irq; 265 int irq;
@@ -263,11 +267,11 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
263 irq = irq_ffs(pending); 267 irq = irq_ffs(pending);
264 268
265 if (irq == MIPSCPU_INT_I8259A) 269 if (irq == MIPSCPU_INT_I8259A)
266 malta_hw0_irqdispatch(regs); 270 malta_hw0_irqdispatch();
267 else if (irq > 0) 271 else if (irq > 0)
268 do_IRQ(MIPSCPU_INT_BASE + irq, regs); 272 do_IRQ(MIPSCPU_INT_BASE + irq);
269 else 273 else
270 spurious_interrupt(regs); 274 spurious_interrupt();
271} 275}
272 276
273static struct irqaction i8259irq = { 277static struct irqaction i8259irq = {
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index 9168d934c661..f445fcddfdfd 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -98,7 +98,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
98 * then we just return, if multiple IRQs are pending then we will just take 98 * then we just return, if multiple IRQs are pending then we will just take
99 * another exception, big deal. 99 * another exception, big deal.
100 */ 100 */
101asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 101asmlinkage void plat_irq_dispatch(void)
102{ 102{
103 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 103 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
104 int irq; 104 int irq;
@@ -106,7 +106,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
106 irq = irq_ffs(pending); 106 irq = irq_ffs(pending);
107 107
108 if (irq >= 0) 108 if (irq >= 0)
109 do_IRQ(MIPSCPU_INT_BASE + irq, regs); 109 do_IRQ(MIPSCPU_INT_BASE + irq);
110 else 110 else
111 spurious_interrupt(regs); 111 spurious_interrupt(regs);
112} 112}
diff --git a/arch/mips/mips-boards/sim/sim_int.c b/arch/mips/mips-boards/sim/sim_int.c
index 2c15c8efec4e..2ce449dce6f2 100644
--- a/arch/mips/mips-boards/sim/sim_int.c
+++ b/arch/mips/mips-boards/sim/sim_int.c
@@ -71,12 +71,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
71#endif 71#endif
72} 72}
73 73
74static inline void sim_hw0_irqdispatch(struct pt_regs *regs) 74asmlinkage void plat_irq_dispatch(void)
75{
76 do_IRQ(2, regs);
77}
78
79asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
80{ 75{
81 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 76 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
82 int irq; 77 int irq;
@@ -84,9 +79,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
84 irq = irq_ffs(pending); 79 irq = irq_ffs(pending);
85 80
86 if (irq > 0) 81 if (irq > 0)
87 do_IRQ(MIPSCPU_INT_BASE + irq, regs); 82 do_IRQ(MIPSCPU_INT_BASE + irq);
88 else 83 else
89 spurious_interrupt(regs); 84 spurious_interrupt();
90} 85}
91 86
92void __init arch_init_irq(void) 87void __init arch_init_irq(void)
diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c
index 230929ecd57f..acd83a379559 100644
--- a/arch/mips/mips-boards/sim/sim_time.c
+++ b/arch/mips/mips-boards/sim/sim_time.c
@@ -33,7 +33,7 @@
33 33
34unsigned long cpu_khz; 34unsigned long cpu_khz;
35 35
36irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs) 36irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
37{ 37{
38#ifdef CONFIG_SMP 38#ifdef CONFIG_SMP
39 int cpu = smp_processor_id(); 39 int cpu = smp_processor_id();
@@ -44,7 +44,7 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
44 */ 44 */
45#ifndef CONFIG_MIPS_MT_SMTC 45#ifndef CONFIG_MIPS_MT_SMTC
46 if (cpu == 0) { 46 if (cpu == 0) {
47 timer_interrupt(irq, dev_id, regs); 47 timer_interrupt(irq, dev_id);
48 } 48 }
49 else { 49 else {
50 /* Everyone else needs to reset the timer int here as 50 /* Everyone else needs to reset the timer int here as
@@ -84,7 +84,7 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
84 irq_enable_hazard(); 84 irq_enable_hazard();
85 evpe(vpflags); 85 evpe(vpflags);
86 86
87 if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id, regs); 87 if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id);
88 else write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ)); 88 else write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
89 smtc_timer_broadcast(cpu_data[cpu].vpe_id); 89 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
90 90
@@ -93,10 +93,10 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
93 /* 93 /*
94 * every CPU should do profiling and process accounting 94 * every CPU should do profiling and process accounting
95 */ 95 */
96 local_timer_interrupt (irq, dev_id, regs); 96 local_timer_interrupt (irq, dev_id);
97 return IRQ_HANDLED; 97 return IRQ_HANDLED;
98#else 98#else
99 return timer_interrupt (irq, dev_id, regs); 99 return timer_interrupt (irq, dev_id);
100#endif 100#endif
101} 101}
102 102
@@ -177,9 +177,9 @@ void __init sim_time_init(void)
177 177
178static int mips_cpu_timer_irq; 178static int mips_cpu_timer_irq;
179 179
180static void mips_timer_dispatch (struct pt_regs *regs) 180static void mips_timer_dispatch(void)
181{ 181{
182 do_IRQ (mips_cpu_timer_irq, regs); 182 do_IRQ(mips_cpu_timer_irq);
183} 183}
184 184
185 185
diff --git a/arch/mips/momentum/jaguar_atx/irq.c b/arch/mips/momentum/jaguar_atx/irq.c
index f9067469a656..2efb25aa1aed 100644
--- a/arch/mips/momentum/jaguar_atx/irq.c
+++ b/arch/mips/momentum/jaguar_atx/irq.c
@@ -40,33 +40,33 @@
40#include <asm/mipsregs.h> 40#include <asm/mipsregs.h>
41#include <asm/time.h> 41#include <asm/time.h>
42 42
43asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 43asmlinkage void plat_irq_dispatch(void)
44{ 44{
45 unsigned int pending = read_c0_cause() & read_c0_status(); 45 unsigned int pending = read_c0_cause() & read_c0_status();
46 46
47 if (pending & STATUSF_IP0) 47 if (pending & STATUSF_IP0)
48 do_IRQ(0, regs); 48 do_IRQ(0);
49 else if (pending & STATUSF_IP1) 49 else if (pending & STATUSF_IP1)
50 do_IRQ(1, regs); 50 do_IRQ(1);
51 else if (pending & STATUSF_IP2) 51 else if (pending & STATUSF_IP2)
52 do_IRQ(2, regs); 52 do_IRQ(2);
53 else if (pending & STATUSF_IP3) 53 else if (pending & STATUSF_IP3)
54 do_IRQ(3, regs); 54 do_IRQ(3);
55 else if (pending & STATUSF_IP4) 55 else if (pending & STATUSF_IP4)
56 do_IRQ(4, regs); 56 do_IRQ(4);
57 else if (pending & STATUSF_IP5) 57 else if (pending & STATUSF_IP5)
58 do_IRQ(5, regs); 58 do_IRQ(5);
59 else if (pending & STATUSF_IP6) 59 else if (pending & STATUSF_IP6)
60 do_IRQ(6, regs); 60 do_IRQ(6);
61 else if (pending & STATUSF_IP7) 61 else if (pending & STATUSF_IP7)
62 ll_timer_interrupt(7, regs); 62 ll_timer_interrupt(7);
63 else { 63 else {
64 /* 64 /*
65 * Now look at the extended interrupts 65 * Now look at the extended interrupts
66 */ 66 */
67 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; 67 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
68 if (pending & STATUSF_IP8) 68 if (pending & STATUSF_IP8)
69 ll_mv64340_irq(regs); 69 ll_mv64340_irq();
70 } 70 }
71} 71}
72 72
diff --git a/arch/mips/momentum/ocelot_3/irq.c b/arch/mips/momentum/ocelot_3/irq.c
index 793782a9c195..cea0e5deb80e 100644
--- a/arch/mips/momentum/ocelot_3/irq.c
+++ b/arch/mips/momentum/ocelot_3/irq.c
@@ -75,26 +75,26 @@ void __init arch_init_irq(void)
75 75
76} 76}
77 77
78asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 78asmlinkage void plat_irq_dispatch(void)
79{ 79{
80 unsigned int pending = read_c0_cause() & read_c0_status(); 80 unsigned int pending = read_c0_cause() & read_c0_status();
81 81
82 if (pending & STATUSF_IP0) 82 if (pending & STATUSF_IP0)
83 do_IRQ(0, regs); 83 do_IRQ(0);
84 else if (pending & STATUSF_IP1) 84 else if (pending & STATUSF_IP1)
85 do_IRQ(1, regs); 85 do_IRQ(1);
86 else if (pending & STATUSF_IP2) 86 else if (pending & STATUSF_IP2)
87 do_IRQ(2, regs); 87 do_IRQ(2);
88 else if (pending & STATUSF_IP3) 88 else if (pending & STATUSF_IP3)
89 do_IRQ(3, regs); 89 do_IRQ(3);
90 else if (pending & STATUSF_IP4) 90 else if (pending & STATUSF_IP4)
91 do_IRQ(4, regs); 91 do_IRQ(4);
92 else if (pending & STATUSF_IP5) 92 else if (pending & STATUSF_IP5)
93 do_IRQ(5, regs); 93 do_IRQ(5);
94 else if (pending & STATUSF_IP6) 94 else if (pending & STATUSF_IP6)
95 do_IRQ(6, regs); 95 do_IRQ(6);
96 else if (pending & STATUSF_IP7) 96 else if (pending & STATUSF_IP7)
97 do_IRQ(7, regs); 97 do_IRQ(7);
98 else { 98 else {
99 /* 99 /*
100 * Now look at the extended interrupts 100 * Now look at the extended interrupts
@@ -102,8 +102,8 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
102 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; 102 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
103 103
104 if (pending & STATUSF_IP8) 104 if (pending & STATUSF_IP8)
105 ll_mv64340_irq(regs); 105 ll_mv64340_irq();
106 else 106 else
107 spurious_interrupt(regs); 107 spurious_interrupt();
108 } 108 }
109} 109}
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index a5dc230520df..2fb14bb08e67 100644
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -112,7 +112,7 @@ static void end_cpci_irq(unsigned int irq)
112 * Interrupt handler for interrupts coming from the FPGA chip. 112 * Interrupt handler for interrupts coming from the FPGA chip.
113 * It could be built in ethernet ports etc... 113 * It could be built in ethernet ports etc...
114 */ 114 */
115void ll_cpci_irq(struct pt_regs *regs) 115void ll_cpci_irq(void)
116{ 116{
117 unsigned int irq_src, irq_mask; 117 unsigned int irq_src, irq_mask;
118 118
@@ -123,7 +123,7 @@ void ll_cpci_irq(struct pt_regs *regs)
123 /* mask for just the interrupts we want */ 123 /* mask for just the interrupts we want */
124 irq_src &= ~irq_mask; 124 irq_src &= ~irq_mask;
125 125
126 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE, regs); 126 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
127} 127}
128 128
129#define shutdown_cpci_irq disable_cpci_irq 129#define shutdown_cpci_irq disable_cpci_irq
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
index 9d44ae1e156b..4be7b26e30ef 100644
--- a/arch/mips/momentum/ocelot_c/irq.c
+++ b/arch/mips/momentum/ocelot_c/irq.c
@@ -59,31 +59,31 @@ static struct irqaction cascade_mv64340 = {
59 no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL 59 no_action, IRQF_DISABLED, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
60}; 60};
61 61
62extern void ll_uart_irq(struct pt_regs *regs); 62extern void ll_uart_irq(void);
63extern void ll_cpci_irq(struct pt_regs *regs); 63extern void ll_cpci_irq(void);
64 64
65asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 65asmlinkage void plat_irq_dispatch(void)
66{ 66{
67 unsigned int pending = read_c0_cause() & read_c0_status(); 67 unsigned int pending = read_c0_cause() & read_c0_status();
68 68
69 if (pending & STATUSF_IP0) 69 if (pending & STATUSF_IP0)
70 do_IRQ(0, regs); 70 do_IRQ(0);
71 else if (pending & STATUSF_IP1) 71 else if (pending & STATUSF_IP1)
72 do_IRQ(1, regs); 72 do_IRQ(1);
73 else if (pending & STATUSF_IP2) 73 else if (pending & STATUSF_IP2)
74 do_IRQ(2, regs); 74 do_IRQ(2);
75 else if (pending & STATUSF_IP3) 75 else if (pending & STATUSF_IP3)
76 ll_uart_irq(regs); 76 ll_uart_irq();
77 else if (pending & STATUSF_IP4) 77 else if (pending & STATUSF_IP4)
78 do_IRQ(4, regs); 78 do_IRQ(4);
79 else if (pending & STATUSF_IP5) 79 else if (pending & STATUSF_IP5)
80 ll_cpci_irq(regs); 80 ll_cpci_irq();
81 else if (pending & STATUSF_IP6) 81 else if (pending & STATUSF_IP6)
82 ll_mv64340_irq(regs); 82 ll_mv64340_irq(regs);
83 else if (pending & STATUSF_IP7) 83 else if (pending & STATUSF_IP7)
84 do_IRQ(7, regs); 84 do_IRQ(7);
85 else 85 else
86 spurious_interrupt(regs); 86 spurious_interrupt();
87} 87}
88 88
89void __init arch_init_irq(void) 89void __init arch_init_irq(void)
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index 9f33d8f1d826..f8efe2370ffd 100644
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -105,7 +105,7 @@ static void end_uart_irq(unsigned int irq)
105/* 105/*
106 * Interrupt handler for interrupts coming from the FPGA chip. 106 * Interrupt handler for interrupts coming from the FPGA chip.
107 */ 107 */
108void ll_uart_irq(struct pt_regs *regs) 108void ll_uart_irq(void)
109{ 109{
110 unsigned int irq_src, irq_mask; 110 unsigned int irq_src, irq_mask;
111 111
@@ -116,7 +116,7 @@ void ll_uart_irq(struct pt_regs *regs)
116 /* mask for just the interrupts we want */ 116 /* mask for just the interrupts we want */
117 irq_src &= ~irq_mask; 117 irq_src &= ~irq_mask;
118 118
119 do_IRQ(ls1bit8(irq_src) + 74, regs); 119 do_IRQ(ls1bit8(irq_src) + 74);
120} 120}
121 121
122#define shutdown_uart_irq disable_uart_irq 122#define shutdown_uart_irq disable_uart_irq
diff --git a/arch/mips/momentum/ocelot_g/gt-irq.c b/arch/mips/momentum/ocelot_g/gt-irq.c
index 6cd87cf0195a..b8cffa80548f 100644
--- a/arch/mips/momentum/ocelot_g/gt-irq.c
+++ b/arch/mips/momentum/ocelot_g/gt-irq.c
@@ -108,7 +108,7 @@ int disable_galileo_irq(int int_cause, int bit_num)
108 * we keep this particular structure in the function. 108 * we keep this particular structure in the function.
109 */ 109 */
110 110
111static irqreturn_t gt64240_p0int_irq(int irq, void *dev, struct pt_regs *regs) 111static irqreturn_t gt64240_p0int_irq(int irq, void *dev)
112{ 112{
113 uint32_t irq_src, irq_src_mask; 113 uint32_t irq_src, irq_src_mask;
114 int handled; 114 int handled;
@@ -135,7 +135,7 @@ static irqreturn_t gt64240_p0int_irq(int irq, void *dev, struct pt_regs *regs)
135 /* handle the timer call */ 135 /* handle the timer call */
136 do_timer(1); 136 do_timer(1);
137#ifndef CONFIG_SMP 137#ifndef CONFIG_SMP
138 update_process_times(user_mode(regs)); 138 update_process_times(user_mode(get_irq_regs()));
139#endif 139#endif
140 } 140 }
141 141
diff --git a/arch/mips/momentum/ocelot_g/irq.c b/arch/mips/momentum/ocelot_g/irq.c
index 7a4a419804f1..da46524e87cb 100644
--- a/arch/mips/momentum/ocelot_g/irq.c
+++ b/arch/mips/momentum/ocelot_g/irq.c
@@ -48,22 +48,22 @@
48#include <asm/mipsregs.h> 48#include <asm/mipsregs.h>
49#include <asm/system.h> 49#include <asm/system.h>
50 50
51asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 51asmlinkage void plat_irq_dispatch(void)
52{ 52{
53 unsigned int pending = read_c0_cause() & read_c0_status(); 53 unsigned int pending = read_c0_cause() & read_c0_status();
54 54
55 if (pending & STATUSF_IP2) 55 if (pending & STATUSF_IP2)
56 do_IRQ(2, regs); 56 do_IRQ(2);
57 else if (pending & STATUSF_IP3) 57 else if (pending & STATUSF_IP3)
58 do_IRQ(3, regs); 58 do_IRQ(3);
59 else if (pending & STATUSF_IP4) 59 else if (pending & STATUSF_IP4)
60 do_IRQ(4, regs); 60 do_IRQ(4);
61 else if (pending & STATUSF_IP5) 61 else if (pending & STATUSF_IP5)
62 do_IRQ(5, regs); 62 do_IRQ(5);
63 else if (pending & STATUSF_IP6) 63 else if (pending & STATUSF_IP6)
64 do_IRQ(6, regs); 64 do_IRQ(6);
65 else if (pending & STATUSF_IP7) 65 else if (pending & STATUSF_IP7)
66 do_IRQ(7, regs); 66 do_IRQ(7);
67 else { 67 else {
68 /* 68 /*
69 * Now look at the extended interrupts 69 * Now look at the extended interrupts
@@ -71,15 +71,15 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
71 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16; 71 pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
72 72
73 if (pending & STATUSF_IP8) 73 if (pending & STATUSF_IP8)
74 do_IRQ(8, regs); 74 do_IRQ(8);
75 else if (pending & STATUSF_IP9) 75 else if (pending & STATUSF_IP9)
76 do_IRQ(9, regs); 76 do_IRQ(9);
77 else if (pending & STATUSF_IP10) 77 else if (pending & STATUSF_IP10)
78 do_IRQ(10, regs); 78 do_IRQ(10);
79 else if (pending & STATUSF_IP11) 79 else if (pending & STATUSF_IP11)
80 do_IRQ(11, regs); 80 do_IRQ(11);
81 else 81 else
82 spurious_interrupt(regs); 82 spurious_interrupt();
83 } 83 }
84} 84}
85 85
diff --git a/arch/mips/oprofile/op_impl.h b/arch/mips/oprofile/op_impl.h
index 5cfce7d87a4d..354e54496406 100644
--- a/arch/mips/oprofile/op_impl.h
+++ b/arch/mips/oprofile/op_impl.h
@@ -12,8 +12,8 @@
12 12
13struct pt_regs; 13struct pt_regs;
14 14
15extern int null_perf_irq(struct pt_regs *regs); 15extern int null_perf_irq(void);
16extern int (*perf_irq)(struct pt_regs *regs); 16extern int (*perf_irq)(void);
17 17
18/* Per-counter configuration as set via oprofilefs. */ 18/* Per-counter configuration as set via oprofilefs. */
19struct op_counter_config { 19struct op_counter_config {
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index a175d673540f..dd0aec9c3ce1 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -3,12 +3,13 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2004, 2005 by Ralf Baechle 6 * Copyright (C) 2004, 05, 06 by Ralf Baechle
7 * Copyright (C) 2005 by MIPS Technologies, Inc. 7 * Copyright (C) 2005 by MIPS Technologies, Inc.
8 */ 8 */
9#include <linux/oprofile.h> 9#include <linux/oprofile.h>
10#include <linux/interrupt.h> 10#include <linux/interrupt.h>
11#include <linux/smp.h> 11#include <linux/smp.h>
12#include <asm/irq_regs.h>
12 13
13#include "op_impl.h" 14#include "op_impl.h"
14 15
@@ -170,7 +171,7 @@ static void mipsxx_cpu_stop(void *args)
170 } 171 }
171} 172}
172 173
173static int mipsxx_perfcount_handler(struct pt_regs *regs) 174static int mipsxx_perfcount_handler(void)
174{ 175{
175 unsigned int counters = op_model_mipsxx_ops.num_counters; 176 unsigned int counters = op_model_mipsxx_ops.num_counters;
176 unsigned int control; 177 unsigned int control;
@@ -184,7 +185,7 @@ static int mipsxx_perfcount_handler(struct pt_regs *regs)
184 counter = r_c0_perfcntr ## n(); \ 185 counter = r_c0_perfcntr ## n(); \
185 if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \ 186 if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
186 (counter & M_COUNTER_OVERFLOW)) { \ 187 (counter & M_COUNTER_OVERFLOW)) { \
187 oprofile_add_sample(regs, n); \ 188 oprofile_add_sample(get_irq_regs(), n); \
188 w_c0_perfcntr ## n(reg.counter[n]); \ 189 w_c0_perfcntr ## n(reg.counter[n]); \
189 handled = 1; \ 190 handled = 1; \
190 } 191 }
diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c
index 17c7932cf0ae..618ea7dbc474 100644
--- a/arch/mips/pci/pci-ip32.c
+++ b/arch/mips/pci/pci-ip32.c
@@ -22,7 +22,7 @@
22 * registered on the bridge error irq. It's conceivable that some of these 22 * registered on the bridge error irq. It's conceivable that some of these
23 * conditions warrant a panic. Anybody care to say which ones? 23 * conditions warrant a panic. Anybody care to say which ones?
24 */ 24 */
25static irqreturn_t macepci_error(int irq, void *dev, struct pt_regs *regs) 25static irqreturn_t macepci_error(int irq, void *dev)
26{ 26{
27 char s; 27 char s;
28 unsigned int flags = mace->pci.error; 28 unsigned int flags = mace->pci.error;
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index 3c93512be1ec..710611615ca2 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -23,6 +23,7 @@
23 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 23 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * 24 *
25 */ 25 */
26#include <linux/compiler.h>
26#include <linux/init.h> 27#include <linux/init.h>
27#include <linux/irq.h> 28#include <linux/irq.h>
28#include <linux/sched.h> 29#include <linux/sched.h>
@@ -52,7 +53,7 @@ static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
52 1 // 70 53 1 // 70
53}; 54};
54 55
55static void hw0_irqdispatch(int irq, struct pt_regs *regs) 56static void hw0_irqdispatch(int irq)
56{ 57{
57 /* find out which interrupt */ 58 /* find out which interrupt */
58 irq = PNX8550_GIC_VECTOR_0 >> 3; 59 irq = PNX8550_GIC_VECTOR_0 >> 3;
@@ -61,42 +62,39 @@ static void hw0_irqdispatch(int irq, struct pt_regs *regs)
61 printk("hw0_irqdispatch: irq 0, spurious interrupt?\n"); 62 printk("hw0_irqdispatch: irq 0, spurious interrupt?\n");
62 return; 63 return;
63 } 64 }
64 do_IRQ(PNX8550_INT_GIC_MIN + irq, regs); 65 do_IRQ(PNX8550_INT_GIC_MIN + irq);
65} 66}
66 67
67 68
68static void timer_irqdispatch(int irq, struct pt_regs *regs) 69static void timer_irqdispatch(int irq)
69{ 70{
70 irq = (0x01c0 & read_c0_config7()) >> 6; 71 irq = (0x01c0 & read_c0_config7()) >> 6;
71 72
72 if (irq == 0) { 73 if (unlikely(irq == 0)) {
73 printk("timer_irqdispatch: irq 0, spurious interrupt?\n"); 74 printk("timer_irqdispatch: irq 0, spurious interrupt?\n");
74 return; 75 return;
75 } 76 }
76 77
77 if (irq & 0x1) { 78 if (irq & 0x1)
78 do_IRQ(PNX8550_INT_TIMER1, regs); 79 do_IRQ(PNX8550_INT_TIMER1);
79 } 80 if (irq & 0x2)
80 if (irq & 0x2) { 81 do_IRQ(PNX8550_INT_TIMER2);
81 do_IRQ(PNX8550_INT_TIMER2, regs); 82 if (irq & 0x4)
82 } 83 do_IRQ(PNX8550_INT_TIMER3);
83 if (irq & 0x4) {
84 do_IRQ(PNX8550_INT_TIMER3, regs);
85 }
86} 84}
87 85
88asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 86asmlinkage void plat_irq_dispatch(void)
89{ 87{
90 unsigned int pending = read_c0_status() & read_c0_cause(); 88 unsigned int pending = read_c0_status() & read_c0_cause();
91 89
92 if (pending & STATUSF_IP2) 90 if (pending & STATUSF_IP2)
93 hw0_irqdispatch(2, regs); 91 hw0_irqdispatch(2);
94 else if (pending & STATUSF_IP7) { 92 else if (pending & STATUSF_IP7) {
95 if (read_c0_config7() & 0x01c0) 93 if (read_c0_config7() & 0x01c0)
96 timer_irqdispatch(7, regs); 94 timer_irqdispatch(7);
97 } 95 }
98 96
99 spurious_interrupt(regs); 97 spurious_interrupt();
100} 98}
101 99
102static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) 100static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
index b91d0aa3b7ed..adb048527e76 100644
--- a/arch/mips/pmc-sierra/yosemite/irq.c
+++ b/arch/mips/pmc-sierra/yosemite/irq.c
@@ -56,15 +56,13 @@
56#define HYPERTRANSPORT_INTC 0x7a /* INTC# */ 56#define HYPERTRANSPORT_INTC 0x7a /* INTC# */
57#define HYPERTRANSPORT_INTD 0x7b /* INTD# */ 57#define HYPERTRANSPORT_INTD 0x7b /* INTD# */
58 58
59extern void jaguar_mailbox_irq(struct pt_regs *);
60
61/* 59/*
62 * Handle hypertransport & SMP interrupts. The interrupt lines are scarce. 60 * Handle hypertransport & SMP interrupts. The interrupt lines are scarce.
63 * For interprocessor interrupts, the best thing to do is to use the INTMSG 61 * For interprocessor interrupts, the best thing to do is to use the INTMSG
64 * register. We use the same external interrupt line, i.e. INTB3 and monitor 62 * register. We use the same external interrupt line, i.e. INTB3 and monitor
65 * another status bit 63 * another status bit
66 */ 64 */
67asmlinkage void ll_ht_smp_irq_handler(int irq, struct pt_regs *regs) 65static void ll_ht_smp_irq_handler(int irq)
68{ 66{
69 u32 status = OCD_READ(RM9000x2_OCD_INTP0STATUS4); 67 u32 status = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
70 68
@@ -107,50 +105,35 @@ asmlinkage void ll_ht_smp_irq_handler(int irq, struct pt_regs *regs)
107 } 105 }
108#endif /* CONFIG_HT_LEVEL_TRIGGER */ 106#endif /* CONFIG_HT_LEVEL_TRIGGER */
109 107
110 do_IRQ(irq, regs); 108 do_IRQ(irq);
111}
112
113asmlinkage void do_extended_irq(struct pt_regs *regs)
114{
115 unsigned int intcontrol = read_c0_intcontrol();
116 unsigned int cause = read_c0_cause();
117 unsigned int status = read_c0_status();
118 unsigned int pending_sr, pending_ic;
119
120 pending_sr = status & cause & 0xff00;
121 pending_ic = (cause >> 8) & intcontrol & 0xff00;
122
123 if (pending_ic & (1 << 13))
124 do_IRQ(13, regs);
125
126} 109}
127 110
128asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 111asmlinkage void plat_irq_dispatch(void)
129{ 112{
130 unsigned int cause = read_c0_cause(); 113 unsigned int cause = read_c0_cause();
131 unsigned int status = read_c0_status(); 114 unsigned int status = read_c0_status();
132 unsigned int pending = cause & status; 115 unsigned int pending = cause & status;
133 116
134 if (pending & STATUSF_IP7) { 117 if (pending & STATUSF_IP7) {
135 do_IRQ(7, regs); 118 do_IRQ(7);
136 } else if (pending & STATUSF_IP2) { 119 } else if (pending & STATUSF_IP2) {
137#ifdef CONFIG_HYPERTRANSPORT 120#ifdef CONFIG_HYPERTRANSPORT
138 ll_ht_smp_irq_handler(2, regs); 121 ll_ht_smp_irq_handler(2);
139#else 122#else
140 do_IRQ(2, regs); 123 do_IRQ(2);
141#endif 124#endif
142 } else if (pending & STATUSF_IP3) { 125 } else if (pending & STATUSF_IP3) {
143 do_IRQ(3, regs); 126 do_IRQ(3);
144 } else if (pending & STATUSF_IP4) { 127 } else if (pending & STATUSF_IP4) {
145 do_IRQ(4, regs); 128 do_IRQ(4);
146 } else if (pending & STATUSF_IP5) { 129 } else if (pending & STATUSF_IP5) {
147#ifdef CONFIG_SMP 130#ifdef CONFIG_SMP
148 titan_mailbox_irq(regs); 131 titan_mailbox_irq();
149#else 132#else
150 do_IRQ(5, regs); 133 do_IRQ(5);
151#endif 134#endif
152 } else if (pending & STATUSF_IP6) { 135 } else if (pending & STATUSF_IP6) {
153 do_IRQ(4, regs); 136 do_IRQ(4);
154 } 137 }
155} 138}
156 139
@@ -178,18 +161,3 @@ void __init arch_init_irq(void)
178 register_gdb_console(); 161 register_gdb_console();
179#endif 162#endif
180} 163}
181
182#ifdef CONFIG_KGDB
183/*
184 * The 16550 DUART has two ports, but is allocated one IRQ
185 * for the serial console. Hence, a generic framework for
186 * serial IRQ routing in place. Currently, just calls the
187 * do_IRQ fuction. But, going in the future, need to check
188 * DUART registers for channel A and B, then decide the
189 * appropriate action
190 */
191asmlinkage void yosemite_kgdb_irq(int irq, struct pt_regs *regs)
192{
193 do_IRQ(irq, regs);
194}
195#endif
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index c197311e15d3..65fa3a23ea5e 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -110,7 +110,7 @@ void prom_smp_finish(void)
110{ 110{
111} 111}
112 112
113asmlinkage void titan_mailbox_irq(struct pt_regs *regs) 113asmlinkage void titan_mailbox_irq(void)
114{ 114{
115 int cpu = smp_processor_id(); 115 int cpu = smp_processor_id();
116 unsigned long status; 116 unsigned long status;
diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c
index 3352374c4c7d..f5ea2fe10f14 100644
--- a/arch/mips/qemu/q-irq.c
+++ b/arch/mips/qemu/q-irq.c
@@ -9,19 +9,19 @@
9 9
10extern asmlinkage void qemu_handle_int(void); 10extern asmlinkage void qemu_handle_int(void);
11 11
12asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 12asmlinkage void plat_irq_dispatch(void)
13{ 13{
14 unsigned int pending = read_c0_status() & read_c0_cause(); 14 unsigned int pending = read_c0_status() & read_c0_cause();
15 15
16 if (pending & 0x8000) { 16 if (pending & 0x8000) {
17 ll_timer_interrupt(Q_COUNT_COMPARE_IRQ, regs); 17 ll_timer_interrupt(Q_COUNT_COMPARE_IRQ);
18 return; 18 return;
19 } 19 }
20 if (pending & 0x0400) { 20 if (pending & 0x0400) {
21 int irq = i8259_irq(); 21 int irq = i8259_irq();
22 22
23 if (likely(irq >= 0)) 23 if (likely(irq >= 0))
24 do_IRQ(irq, regs); 24 do_IRQ(irq);
25 25
26 return; 26 return;
27 } 27 }
diff --git a/arch/mips/sgi-ip22/ip22-berr.c b/arch/mips/sgi-ip22/ip22-berr.c
index a28dc7800072..de6a0cc32fea 100644
--- a/arch/mips/sgi-ip22/ip22-berr.c
+++ b/arch/mips/sgi-ip22/ip22-berr.c
@@ -12,6 +12,7 @@
12#include <asm/system.h> 12#include <asm/system.h>
13#include <asm/traps.h> 13#include <asm/traps.h>
14#include <asm/branch.h> 14#include <asm/branch.h>
15#include <asm/irq_regs.h>
15#include <asm/sgi/mc.h> 16#include <asm/sgi/mc.h>
16#include <asm/sgi/hpc3.h> 17#include <asm/sgi/hpc3.h>
17#include <asm/sgi/ioc.h> 18#include <asm/sgi/ioc.h>
@@ -85,9 +86,10 @@ static void print_buserr(void)
85 * and then clear the interrupt when this happens. 86 * and then clear the interrupt when this happens.
86 */ 87 */
87 88
88void ip22_be_interrupt(int irq, struct pt_regs *regs) 89void ip22_be_interrupt(int irq)
89{ 90{
90 const int field = 2 * sizeof(unsigned long); 91 const int field = 2 * sizeof(unsigned long);
92 const struct pt_regs *regs = get_irq_regs();
91 93
92 save_and_clear_buserr(); 94 save_and_clear_buserr();
93 print_buserr(); 95 print_buserr();
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index ee0514a29922..0d18ed47c47a 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -70,7 +70,7 @@ static char __init *decode_eisa_sig(unsigned long addr)
70 return sig_str; 70 return sig_str;
71} 71}
72 72
73static irqreturn_t ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs) 73static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
74{ 74{
75 u8 eisa_irq; 75 u8 eisa_irq;
76 u8 dma1, dma2; 76 u8 dma1, dma2;
@@ -80,7 +80,7 @@ static irqreturn_t ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs)
80 dma2 = inb(EISA_DMA2_STATUS); 80 dma2 = inb(EISA_DMA2_STATUS);
81 81
82 if (eisa_irq < EISA_MAX_IRQ) { 82 if (eisa_irq < EISA_MAX_IRQ) {
83 do_IRQ(eisa_irq, regs); 83 do_IRQ(eisa_irq);
84 return IRQ_HANDLED; 84 return IRQ_HANDLED;
85 } 85 }
86 86
@@ -89,6 +89,7 @@ static irqreturn_t ip22_eisa_intr(int irq, void *dev_id, struct pt_regs *regs)
89 89
90 outb(0x20, EISA_INT2_CTRL); 90 outb(0x20, EISA_INT2_CTRL);
91 outb(0x20, EISA_INT1_CTRL); 91 outb(0x20, EISA_INT1_CTRL);
92
92 return IRQ_NONE; 93 return IRQ_NONE;
93} 94}
94 95
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index f66026e5d64b..af518898eaa1 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -222,7 +222,7 @@ static struct irq_chip ip22_local3_irq_type = {
222 .end = end_local3_irq, 222 .end = end_local3_irq,
223}; 223};
224 224
225static void indy_local0_irqdispatch(struct pt_regs *regs) 225static void indy_local0_irqdispatch(void)
226{ 226{
227 u8 mask = sgint->istat0 & sgint->imask0; 227 u8 mask = sgint->istat0 & sgint->imask0;
228 u8 mask2; 228 u8 mask2;
@@ -236,11 +236,10 @@ static void indy_local0_irqdispatch(struct pt_regs *regs)
236 236
237 /* if irq == 0, then the interrupt has already been cleared */ 237 /* if irq == 0, then the interrupt has already been cleared */
238 if (irq) 238 if (irq)
239 do_IRQ(irq, regs); 239 do_IRQ(irq);
240 return;
241} 240}
242 241
243static void indy_local1_irqdispatch(struct pt_regs *regs) 242static void indy_local1_irqdispatch(void)
244{ 243{
245 u8 mask = sgint->istat1 & sgint->imask1; 244 u8 mask = sgint->istat1 & sgint->imask1;
246 u8 mask2; 245 u8 mask2;
@@ -254,19 +253,18 @@ static void indy_local1_irqdispatch(struct pt_regs *regs)
254 253
255 /* if irq == 0, then the interrupt has already been cleared */ 254 /* if irq == 0, then the interrupt has already been cleared */
256 if (irq) 255 if (irq)
257 do_IRQ(irq, regs); 256 do_IRQ(irq);
258 return;
259} 257}
260 258
261extern void ip22_be_interrupt(int irq, struct pt_regs *regs); 259extern void ip22_be_interrupt(int irq);
262 260
263static void indy_buserror_irq(struct pt_regs *regs) 261static void indy_buserror_irq(void)
264{ 262{
265 int irq = SGI_BUSERR_IRQ; 263 int irq = SGI_BUSERR_IRQ;
266 264
267 irq_enter(); 265 irq_enter();
268 kstat_this_cpu.irqs[irq]++; 266 kstat_this_cpu.irqs[irq]++;
269 ip22_be_interrupt(irq, regs); 267 ip22_be_interrupt(irq);
270 irq_exit(); 268 irq_exit();
271} 269}
272 270
@@ -305,8 +303,8 @@ static struct irqaction map1_cascade = {
305#define SGI_INTERRUPTS SGINT_LOCAL3 303#define SGI_INTERRUPTS SGINT_LOCAL3
306#endif 304#endif
307 305
308extern void indy_r4k_timer_interrupt(struct pt_regs *regs); 306extern void indy_r4k_timer_interrupt(void);
309extern void indy_8254timer_irq(struct pt_regs *regs); 307extern void indy_8254timer_irq(void);
310 308
311/* 309/*
312 * IRQs on the INDY look basically (barring software IRQs which we don't use 310 * IRQs on the INDY look basically (barring software IRQs which we don't use
@@ -336,7 +334,7 @@ extern void indy_8254timer_irq(struct pt_regs *regs);
336 * another exception, big deal. 334 * another exception, big deal.
337 */ 335 */
338 336
339asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 337asmlinkage void plat_irq_dispatch(void)
340{ 338{
341 unsigned int pending = read_c0_cause(); 339 unsigned int pending = read_c0_cause();
342 340
@@ -344,15 +342,15 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
344 * First we check for r4k counter/timer IRQ. 342 * First we check for r4k counter/timer IRQ.
345 */ 343 */
346 if (pending & CAUSEF_IP7) 344 if (pending & CAUSEF_IP7)
347 indy_r4k_timer_interrupt(regs); 345 indy_r4k_timer_interrupt();
348 else if (pending & CAUSEF_IP2) 346 else if (pending & CAUSEF_IP2)
349 indy_local0_irqdispatch(regs); 347 indy_local0_irqdispatch();
350 else if (pending & CAUSEF_IP3) 348 else if (pending & CAUSEF_IP3)
351 indy_local1_irqdispatch(regs); 349 indy_local1_irqdispatch();
352 else if (pending & CAUSEF_IP6) 350 else if (pending & CAUSEF_IP6)
353 indy_buserror_irq(regs); 351 indy_buserror_irq();
354 else if (pending & (CAUSEF_IP4 | CAUSEF_IP5)) 352 else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
355 indy_8254timer_irq(regs); 353 indy_8254timer_irq();
356} 354}
357 355
358extern void mips_cpu_irq_init(unsigned int irq_base); 356extern void mips_cpu_irq_init(unsigned int irq_base);
diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c
index 3462b0d98def..205554734099 100644
--- a/arch/mips/sgi-ip22/ip22-time.c
+++ b/arch/mips/sgi-ip22/ip22-time.c
@@ -175,7 +175,7 @@ static __init void indy_time_init(void)
175} 175}
176 176
177/* Generic SGI handler for (spurious) 8254 interrupts */ 177/* Generic SGI handler for (spurious) 8254 interrupts */
178void indy_8254timer_irq(struct pt_regs *regs) 178void indy_8254timer_irq(void)
179{ 179{
180 int irq = SGI_8254_0_IRQ; 180 int irq = SGI_8254_0_IRQ;
181 ULONG cnt; 181 ULONG cnt;
@@ -189,16 +189,14 @@ void indy_8254timer_irq(struct pt_regs *regs)
189 irq_exit(); 189 irq_exit();
190} 190}
191 191
192void indy_r4k_timer_interrupt(struct pt_regs *regs) 192void indy_r4k_timer_interrupt(void)
193{ 193{
194 struct pt_regs *old_regs = set_irq_regs(regs);
195 int irq = SGI_TIMER_IRQ; 194 int irq = SGI_TIMER_IRQ;
196 195
197 irq_enter(); 196 irq_enter();
198 kstat_this_cpu.irqs[irq]++; 197 kstat_this_cpu.irqs[irq]++;
199 timer_interrupt(irq, NULL); 198 timer_interrupt(irq, NULL);
200 irq_exit(); 199 irq_exit();
201 set_irq_regs(old_regs);
202} 200}
203 201
204void __init plat_timer_setup(struct irqaction *irq) 202void __init plat_timer_setup(struct irqaction *irq)
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 24a85372284f..f41587a206e2 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -129,7 +129,7 @@ static int ms1bit(unsigned long x)
129 * Kanoj 05.13.00 129 * Kanoj 05.13.00
130 */ 130 */
131 131
132static void ip27_do_irq_mask0(struct pt_regs *regs) 132static void ip27_do_irq_mask0(void)
133{ 133{
134 int irq, swlevel; 134 int irq, swlevel;
135 hubreg_t pend0, mask0; 135 hubreg_t pend0, mask0;
@@ -164,13 +164,13 @@ static void ip27_do_irq_mask0(struct pt_regs *regs)
164 struct slice_data *si = cpu_data[cpu].data; 164 struct slice_data *si = cpu_data[cpu].data;
165 165
166 irq = si->level_to_irq[swlevel]; 166 irq = si->level_to_irq[swlevel];
167 do_IRQ(irq, regs); 167 do_IRQ(irq);
168 } 168 }
169 169
170 LOCAL_HUB_L(PI_INT_PEND0); 170 LOCAL_HUB_L(PI_INT_PEND0);
171} 171}
172 172
173static void ip27_do_irq_mask1(struct pt_regs *regs) 173static void ip27_do_irq_mask1(void)
174{ 174{
175 int irq, swlevel; 175 int irq, swlevel;
176 hubreg_t pend1, mask1; 176 hubreg_t pend1, mask1;
@@ -190,17 +190,17 @@ static void ip27_do_irq_mask1(struct pt_regs *regs)
190 /* "map" swlevel to irq */ 190 /* "map" swlevel to irq */
191 irq = si->level_to_irq[swlevel]; 191 irq = si->level_to_irq[swlevel];
192 LOCAL_HUB_CLR_INTR(swlevel); 192 LOCAL_HUB_CLR_INTR(swlevel);
193 do_IRQ(irq, regs); 193 do_IRQ(irq);
194 194
195 LOCAL_HUB_L(PI_INT_PEND1); 195 LOCAL_HUB_L(PI_INT_PEND1);
196} 196}
197 197
198static void ip27_prof_timer(struct pt_regs *regs) 198static void ip27_prof_timer(void)
199{ 199{
200 panic("CPU %d got a profiling interrupt", smp_processor_id()); 200 panic("CPU %d got a profiling interrupt", smp_processor_id());
201} 201}
202 202
203static void ip27_hub_error(struct pt_regs *regs) 203static void ip27_hub_error(void)
204{ 204{
205 panic("CPU %d got a hub error interrupt", smp_processor_id()); 205 panic("CPU %d got a hub error interrupt", smp_processor_id());
206} 206}
@@ -418,22 +418,22 @@ int __devinit request_bridge_irq(struct bridge_controller *bc)
418 return irq; 418 return irq;
419} 419}
420 420
421extern void ip27_rt_timer_interrupt(struct pt_regs *regs); 421extern void ip27_rt_timer_interrupt(void);
422 422
423asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 423asmlinkage void plat_irq_dispatch(void)
424{ 424{
425 unsigned long pending = read_c0_cause() & read_c0_status(); 425 unsigned long pending = read_c0_cause() & read_c0_status();
426 426
427 if (pending & CAUSEF_IP4) 427 if (pending & CAUSEF_IP4)
428 ip27_rt_timer_interrupt(regs); 428 ip27_rt_timer_interrupt();
429 else if (pending & CAUSEF_IP2) /* PI_INT_PEND_0 or CC_PEND_{A|B} */ 429 else if (pending & CAUSEF_IP2) /* PI_INT_PEND_0 or CC_PEND_{A|B} */
430 ip27_do_irq_mask0(regs); 430 ip27_do_irq_mask0();
431 else if (pending & CAUSEF_IP3) /* PI_INT_PEND_1 */ 431 else if (pending & CAUSEF_IP3) /* PI_INT_PEND_1 */
432 ip27_do_irq_mask1(regs); 432 ip27_do_irq_mask1();
433 else if (pending & CAUSEF_IP5) 433 else if (pending & CAUSEF_IP5)
434 ip27_prof_timer(regs); 434 ip27_prof_timer();
435 else if (pending & CAUSEF_IP6) 435 else if (pending & CAUSEF_IP6)
436 ip27_hub_error(regs); 436 ip27_hub_error();
437} 437}
438 438
439void __init arch_init_irq(void) 439void __init arch_init_irq(void)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 257ce118e380..4e870fc4469b 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -89,7 +89,7 @@ static int set_rtc_mmss(unsigned long nowtime)
89 89
90static unsigned int rt_timer_irq; 90static unsigned int rt_timer_irq;
91 91
92void ip27_rt_timer_interrupt(struct pt_regs *regs) 92void ip27_rt_timer_interrupt(void)
93{ 93{
94 int cpu = smp_processor_id(); 94 int cpu = smp_processor_id();
95 int cpuA = cputoslice(cpu) == 0; 95 int cpuA = cputoslice(cpu) == 0;
@@ -111,7 +111,7 @@ again:
111 if (cpu == 0) 111 if (cpu == 0)
112 do_timer(1); 112 do_timer(1);
113 113
114 update_process_times(user_mode(regs)); 114 update_process_times(user_mode(get_irq_regs()));
115 115
116 /* 116 /*
117 * If we have an externally synchronized Linux clock, then update 117 * If we have an externally synchronized Linux clock, then update
diff --git a/arch/mips/sgi-ip32/crime.c b/arch/mips/sgi-ip32/crime.c
index 41b5eca1148c..f1f2c45a6c80 100644
--- a/arch/mips/sgi-ip32/crime.c
+++ b/arch/mips/sgi-ip32/crime.c
@@ -40,8 +40,7 @@ void __init crime_init(void)
40 id, rev, field, (unsigned long) CRIME_BASE); 40 id, rev, field, (unsigned long) CRIME_BASE);
41} 41}
42 42
43irqreturn_t 43irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id)
44crime_memerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs)
45{ 44{
46 unsigned long stat, addr; 45 unsigned long stat, addr;
47 int fatal = 0; 46 int fatal = 0;
@@ -92,8 +91,7 @@ crime_memerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs)
92 return IRQ_HANDLED; 91 return IRQ_HANDLED;
93} 92}
94 93
95irqreturn_t 94irqreturn_t crime_cpuerr_intr(unsigned int irq, void *dev_id)
96crime_cpuerr_intr (unsigned int irq, void *dev_id, struct pt_regs *regs)
97{ 95{
98 unsigned long stat = crime->cpu_error_stat & CRIME_CPU_ERROR_MASK; 96 unsigned long stat = crime->cpu_error_stat & CRIME_CPU_ERROR_MASK;
99 unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK; 97 unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK;
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index c64a820373de..c9acadd0846b 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -120,10 +120,8 @@ static void inline flush_mace_bus(void)
120static DEFINE_SPINLOCK(ip32_irq_lock); 120static DEFINE_SPINLOCK(ip32_irq_lock);
121 121
122/* Some initial interrupts to set up */ 122/* Some initial interrupts to set up */
123extern irqreturn_t crime_memerr_intr (int irq, void *dev_id, 123extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
124 struct pt_regs *regs); 124extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
125extern irqreturn_t crime_cpuerr_intr (int irq, void *dev_id,
126 struct pt_regs *regs);
127 125
128struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED, 126struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED,
129 CPU_MASK_NONE, "CRIME memory error", NULL, NULL }; 127 CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
@@ -479,7 +477,7 @@ static struct irq_chip ip32_mace_interrupt = {
479 .end = end_mace_irq, 477 .end = end_mace_irq,
480}; 478};
481 479
482static void ip32_unknown_interrupt(struct pt_regs *regs) 480static void ip32_unknown_interrupt(void)
483{ 481{
484 printk ("Unknown interrupt occurred!\n"); 482 printk ("Unknown interrupt occurred!\n");
485 printk ("cp0_status: %08x\n", read_c0_status()); 483 printk ("cp0_status: %08x\n", read_c0_status());
@@ -492,7 +490,7 @@ static void ip32_unknown_interrupt(struct pt_regs *regs)
492 printk ("MACE PCI control register: %08x\n", mace->pci.control); 490 printk ("MACE PCI control register: %08x\n", mace->pci.control);
493 491
494 printk("Register dump:\n"); 492 printk("Register dump:\n");
495 show_regs(regs); 493 show_regs(get_irq_regs());
496 494
497 printk("Please mail this report to linux-mips@linux-mips.org\n"); 495 printk("Please mail this report to linux-mips@linux-mips.org\n");
498 printk("Spinning..."); 496 printk("Spinning...");
@@ -501,7 +499,7 @@ static void ip32_unknown_interrupt(struct pt_regs *regs)
501 499
502/* CRIME 1.1 appears to deliver all interrupts to this one pin. */ 500/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
503/* change this to loop over all edge-triggered irqs, exception masked out ones */ 501/* change this to loop over all edge-triggered irqs, exception masked out ones */
504static void ip32_irq0(struct pt_regs *regs) 502static void ip32_irq0(void)
505{ 503{
506 uint64_t crime_int; 504 uint64_t crime_int;
507 int irq = 0; 505 int irq = 0;
@@ -516,50 +514,50 @@ static void ip32_irq0(struct pt_regs *regs)
516 } 514 }
517 irq++; 515 irq++;
518 DBG("*irq %u*\n", irq); 516 DBG("*irq %u*\n", irq);
519 do_IRQ(irq, regs); 517 do_IRQ(irq);
520} 518}
521 519
522static void ip32_irq1(struct pt_regs *regs) 520static void ip32_irq1(void)
523{ 521{
524 ip32_unknown_interrupt(regs); 522 ip32_unknown_interrupt();
525} 523}
526 524
527static void ip32_irq2(struct pt_regs *regs) 525static void ip32_irq2(void)
528{ 526{
529 ip32_unknown_interrupt(regs); 527 ip32_unknown_interrupt();
530} 528}
531 529
532static void ip32_irq3(struct pt_regs *regs) 530static void ip32_irq3(void)
533{ 531{
534 ip32_unknown_interrupt(regs); 532 ip32_unknown_interrupt();
535} 533}
536 534
537static void ip32_irq4(struct pt_regs *regs) 535static void ip32_irq4(void)
538{ 536{
539 ip32_unknown_interrupt(regs); 537 ip32_unknown_interrupt();
540} 538}
541 539
542static void ip32_irq5(struct pt_regs *regs) 540static void ip32_irq5(void)
543{ 541{
544 ll_timer_interrupt(IP32_R4K_TIMER_IRQ, regs); 542 ll_timer_interrupt(IP32_R4K_TIMER_IRQ);
545} 543}
546 544
547asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 545asmlinkage void plat_irq_dispatch(void)
548{ 546{
549 unsigned int pending = read_c0_cause(); 547 unsigned int pending = read_c0_cause();
550 548
551 if (likely(pending & IE_IRQ0)) 549 if (likely(pending & IE_IRQ0))
552 ip32_irq0(regs); 550 ip32_irq0();
553 else if (unlikely(pending & IE_IRQ1)) 551 else if (unlikely(pending & IE_IRQ1))
554 ip32_irq1(regs); 552 ip32_irq1();
555 else if (unlikely(pending & IE_IRQ2)) 553 else if (unlikely(pending & IE_IRQ2))
556 ip32_irq2(regs); 554 ip32_irq2();
557 else if (unlikely(pending & IE_IRQ3)) 555 else if (unlikely(pending & IE_IRQ3))
558 ip32_irq3(regs); 556 ip32_irq3();
559 else if (unlikely(pending & IE_IRQ4)) 557 else if (unlikely(pending & IE_IRQ4))
560 ip32_irq4(regs); 558 ip32_irq4();
561 else if (likely(pending & IE_IRQ5)) 559 else if (likely(pending & IE_IRQ5))
562 ip32_irq5(regs); 560 ip32_irq5();
563} 561}
564 562
565void __init arch_init_irq(void) 563void __init arch_init_irq(void)
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index a46b75b23ecb..0c00f676b8b3 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -25,6 +25,7 @@
25#include <linux/kernel_stat.h> 25#include <linux/kernel_stat.h>
26 26
27#include <asm/errno.h> 27#include <asm/errno.h>
28#include <asm/irq_regs.h>
28#include <asm/signal.h> 29#include <asm/signal.h>
29#include <asm/system.h> 30#include <asm/system.h>
30#include <asm/ptrace.h> 31#include <asm/ptrace.h>
@@ -284,8 +285,7 @@ void __init init_bcm1480_irqs(void)
284} 285}
285 286
286 287
287static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id, 288static irqreturn_t bcm1480_dummy_handler(int irq, void *dev_id)
288 struct pt_regs *regs)
289{ 289{
290 return IRQ_NONE; 290 return IRQ_NONE;
291} 291}
@@ -453,7 +453,7 @@ void __init arch_init_irq(void)
453#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 453#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
454#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 454#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
455 455
456void bcm1480_kgdb_interrupt(struct pt_regs *regs) 456static void bcm1480_kgdb_interrupt(void)
457{ 457{
458 /* 458 /*
459 * Clear break-change status (allow some time for the remote 459 * Clear break-change status (allow some time for the remote
@@ -464,16 +464,15 @@ void bcm1480_kgdb_interrupt(struct pt_regs *regs)
464 mdelay(500); 464 mdelay(500);
465 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT | 465 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
466 M_DUART_RX_EN | M_DUART_TX_EN); 466 M_DUART_RX_EN | M_DUART_TX_EN);
467 set_async_breakpoint(&regs->cp0_epc); 467 set_async_breakpoint(&get_irq_regs()->cp0_epc);
468} 468}
469 469
470#endif /* CONFIG_KGDB */ 470#endif /* CONFIG_KGDB */
471 471
472extern void bcm1480_timer_interrupt(struct pt_regs *regs); 472extern void bcm1480_timer_interrupt(void);
473extern void bcm1480_mailbox_interrupt(struct pt_regs *regs); 473extern void bcm1480_mailbox_interrupt(void);
474extern void bcm1480_kgdb_interrupt(struct pt_regs *regs);
475 474
476asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 475asmlinkage void plat_irq_dispatch(void)
477{ 476{
478 unsigned int pending; 477 unsigned int pending;
479 478
@@ -486,21 +485,21 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
486 485
487#ifdef CONFIG_SIBYTE_BCM1480_PROF 486#ifdef CONFIG_SIBYTE_BCM1480_PROF
488 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ 487 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
489 sbprof_cpu_intr(exception_epc(regs)); 488 sbprof_cpu_intr();
490 else 489 else
491#endif 490#endif
492 491
493 if (pending & CAUSEF_IP4) 492 if (pending & CAUSEF_IP4)
494 bcm1480_timer_interrupt(regs); 493 bcm1480_timer_interrupt();
495 494
496#ifdef CONFIG_SMP 495#ifdef CONFIG_SMP
497 else if (pending & CAUSEF_IP3) 496 else if (pending & CAUSEF_IP3)
498 bcm1480_mailbox_interrupt(regs); 497 bcm1480_mailbox_interrupt();
499#endif 498#endif
500 499
501#ifdef CONFIG_KGDB 500#ifdef CONFIG_KGDB
502 else if (pending & CAUSEF_IP6) 501 else if (pending & CAUSEF_IP6)
503 bcm1480_kgdb_interrupt(regs); /* KGDB (uart 1) */ 502 bcm1480_kgdb_interrupt(); /* KGDB (uart 1) */
504#endif 503#endif
505 504
506 else if (pending & CAUSEF_IP2) { 505 else if (pending & CAUSEF_IP2) {
@@ -521,9 +520,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
521 520
522 if (mask_h) { 521 if (mask_h) {
523 if (mask_h ^ 1) 522 if (mask_h ^ 1)
524 do_IRQ(fls64(mask_h) - 1, regs); 523 do_IRQ(fls64(mask_h) - 1);
525 else 524 else
526 do_IRQ(63 + fls64(mask_l), regs); 525 do_IRQ(63 + fls64(mask_l));
527 } 526 }
528 } 527 }
529} 528}
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index 584a4b33faac..6eac36d1b8c8 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -88,7 +88,7 @@ void core_send_ipi(int cpu, unsigned int action)
88 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); 88 __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]);
89} 89}
90 90
91void bcm1480_mailbox_interrupt(struct pt_regs *regs) 91void bcm1480_mailbox_interrupt(void)
92{ 92{
93 int cpu = smp_processor_id(); 93 int cpu = smp_processor_id();
94 unsigned int action; 94 unsigned int action;
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index 7e088f6c4a86..f228f711dc34 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -100,10 +100,10 @@ void bcm1480_time_init(void)
100 100
101#include <asm/sibyte/sb1250.h> 101#include <asm/sibyte/sb1250.h>
102 102
103void bcm1480_timer_interrupt(struct pt_regs *regs) 103void bcm1480_timer_interrupt(void)
104{ 104{
105 int cpu = smp_processor_id(); 105 int cpu = smp_processor_id();
106 int irq = K_BCM1480_INT_TIMER_0+cpu; 106 int irq = K_BCM1480_INT_TIMER_0 + cpu;
107 107
108 /* Reset the timer */ 108 /* Reset the timer */
109 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, 109 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
@@ -113,13 +113,13 @@ void bcm1480_timer_interrupt(struct pt_regs *regs)
113 /* 113 /*
114 * CPU 0 handles the global timer interrupt job 114 * CPU 0 handles the global timer interrupt job
115 */ 115 */
116 ll_timer_interrupt(irq, regs); 116 ll_timer_interrupt(irq);
117 } 117 }
118 else { 118 else {
119 /* 119 /*
120 * other CPUs should just do profiling and process accounting 120 * other CPUs should just do profiling and process accounting
121 */ 121 */
122 ll_local_timer_interrupt(irq, regs); 122 ll_local_timer_interrupt(irq);
123 } 123 }
124} 124}
125 125
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index f9bd9f074517..f6d2e19592ea 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -254,8 +254,7 @@ void __init init_sb1250_irqs(void)
254} 254}
255 255
256 256
257static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id, 257static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id)
258 struct pt_regs *regs)
259{ 258{
260 return IRQ_NONE; 259 return IRQ_NONE;
261} 260}
@@ -403,7 +402,7 @@ void __init arch_init_irq(void)
403#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 402#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
404#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 403#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
405 404
406static void sb1250_kgdb_interrupt(struct pt_regs *regs) 405static void sb1250_kgdb_interrupt(void)
407{ 406{
408 /* 407 /*
409 * Clear break-change status (allow some time for the remote 408 * Clear break-change status (allow some time for the remote
@@ -414,16 +413,15 @@ static void sb1250_kgdb_interrupt(struct pt_regs *regs)
414 mdelay(500); 413 mdelay(500);
415 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT | 414 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
416 M_DUART_RX_EN | M_DUART_TX_EN); 415 M_DUART_RX_EN | M_DUART_TX_EN);
417 set_async_breakpoint(&regs->cp0_epc); 416 set_async_breakpoint(&get_irq_regs()->cp0_epc);
418} 417}
419 418
420#endif /* CONFIG_KGDB */ 419#endif /* CONFIG_KGDB */
421 420
422extern void sb1250_timer_interrupt(struct pt_regs *regs); 421extern void sb1250_timer_interrupt(void);
423extern void sb1250_mailbox_interrupt(struct pt_regs *regs); 422extern void sb1250_mailbox_interrupt(void);
424extern void sb1250_kgdb_interrupt(struct pt_regs *regs);
425 423
426asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 424asmlinkage void plat_irq_dispatch(void)
427{ 425{
428 unsigned int pending; 426 unsigned int pending;
429 427
@@ -446,21 +444,21 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
446 444
447#ifdef CONFIG_SIBYTE_SB1250_PROF 445#ifdef CONFIG_SIBYTE_SB1250_PROF
448 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ 446 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
449 sbprof_cpu_intr(exception_epc(regs)); 447 sbprof_cpu_intr();
450 else 448 else
451#endif 449#endif
452 450
453 if (pending & CAUSEF_IP4) 451 if (pending & CAUSEF_IP4)
454 sb1250_timer_interrupt(regs); 452 sb1250_timer_interrupt();
455 453
456#ifdef CONFIG_SMP 454#ifdef CONFIG_SMP
457 else if (pending & CAUSEF_IP3) 455 else if (pending & CAUSEF_IP3)
458 sb1250_mailbox_interrupt(regs); 456 sb1250_mailbox_interrupt();
459#endif 457#endif
460 458
461#ifdef CONFIG_KGDB 459#ifdef CONFIG_KGDB
462 else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */ 460 else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
463 sb1250_kgdb_interrupt(regs); 461 sb1250_kgdb_interrupt();
464#endif 462#endif
465 463
466 else if (pending & CAUSEF_IP2) { 464 else if (pending & CAUSEF_IP2) {
@@ -475,9 +473,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
475 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(), 473 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
476 R_IMR_INTERRUPT_STATUS_BASE))); 474 R_IMR_INTERRUPT_STATUS_BASE)));
477 if (mask) 475 if (mask)
478 do_IRQ(fls64(mask) - 1, regs); 476 do_IRQ(fls64(mask) - 1);
479 else 477 else
480 spurious_interrupt(regs); 478 spurious_interrupt();
481 } else 479 } else
482 spurious_interrupt(regs); 480 spurious_interrupt();
483} 481}
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
index f859db02d3c9..c38e1f34460d 100644
--- a/arch/mips/sibyte/sb1250/smp.c
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -76,7 +76,7 @@ void core_send_ipi(int cpu, unsigned int action)
76 __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); 76 __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
77} 77}
78 78
79void sb1250_mailbox_interrupt(struct pt_regs *regs) 79void sb1250_mailbox_interrupt(void)
80{ 80{
81 int cpu = smp_processor_id(); 81 int cpu = smp_processor_id();
82 unsigned int action; 82 unsigned int action;
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 4b669dc86ef4..0d17aec03dd7 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -125,7 +125,7 @@ void sb1250_time_init(void)
125 */ 125 */
126} 126}
127 127
128void sb1250_timer_interrupt(struct pt_regs *regs) 128void sb1250_timer_interrupt(void)
129{ 129{
130 int cpu = smp_processor_id(); 130 int cpu = smp_processor_id();
131 int irq = K_INT_TIMER_0 + cpu; 131 int irq = K_INT_TIMER_0 + cpu;
@@ -138,13 +138,13 @@ void sb1250_timer_interrupt(struct pt_regs *regs)
138 /* 138 /*
139 * CPU 0 handles the global timer interrupt job 139 * CPU 0 handles the global timer interrupt job
140 */ 140 */
141 ll_timer_interrupt(irq, regs); 141 ll_timer_interrupt(irq);
142 } 142 }
143 else { 143 else {
144 /* 144 /*
145 * other CPUs should just do profiling and process accounting 145 * other CPUs should just do profiling and process accounting
146 */ 146 */
147 ll_local_timer_interrupt(irq, regs); 147 ll_local_timer_interrupt(irq);
148 } 148 }
149} 149}
150 150
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index cda165f42b6a..48fb74a7aaec 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -69,20 +69,20 @@ static struct irq_chip pciasic_irq_type = {
69 * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug 69 * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
70 * button interrupts. Later ... 70 * button interrupts. Later ...
71 */ 71 */
72static void pciasic_hwint0(struct pt_regs *regs) 72static void pciasic_hwint0(void)
73{ 73{
74 panic("Received int0 but no handler yet ..."); 74 panic("Received int0 but no handler yet ...");
75} 75}
76 76
77/* This interrupt was used for the com1 console on the first prototypes. */ 77/* This interrupt was used for the com1 console on the first prototypes. */
78static void pciasic_hwint2(struct pt_regs *regs) 78static void pciasic_hwint2(void)
79{ 79{
80 /* I think this shouldn't happen on production machines. */ 80 /* I think this shouldn't happen on production machines. */
81 panic("hwint2 and no handler yet"); 81 panic("hwint2 and no handler yet");
82} 82}
83 83
84/* hwint5 is the r4k count / compare interrupt */ 84/* hwint5 is the r4k count / compare interrupt */
85static void pciasic_hwint5(struct pt_regs *regs) 85static void pciasic_hwint5(void)
86{ 86{
87 panic("hwint5 and no handler yet"); 87 panic("hwint5 and no handler yet");
88} 88}
@@ -103,7 +103,7 @@ static unsigned int ls1bit8(unsigned int x)
103 * 103 *
104 * The EISA_INT bit in CSITPEND is high active, all others are low active. 104 * The EISA_INT bit in CSITPEND is high active, all others are low active.
105 */ 105 */
106static void pciasic_hwint1(struct pt_regs *regs) 106static void pciasic_hwint1(void)
107{ 107{
108 u8 pend = *(volatile char *)PCIMT_CSITPEND; 108 u8 pend = *(volatile char *)PCIMT_CSITPEND;
109 unsigned long flags; 109 unsigned long flags;
@@ -119,13 +119,13 @@ static void pciasic_hwint1(struct pt_regs *regs)
119 if (unlikely(irq < 0)) 119 if (unlikely(irq < 0))
120 return; 120 return;
121 121
122 do_IRQ(irq, regs); 122 do_IRQ(irq);
123 } 123 }
124 124
125 if (!(pend & IT_SCSI)) { 125 if (!(pend & IT_SCSI)) {
126 flags = read_c0_status(); 126 flags = read_c0_status();
127 clear_c0_status(ST0_IM); 127 clear_c0_status(ST0_IM);
128 do_IRQ(PCIMT_IRQ_SCSI, regs); 128 do_IRQ(PCIMT_IRQ_SCSI);
129 write_c0_status(flags); 129 write_c0_status(flags);
130 } 130 }
131} 131}
@@ -133,7 +133,7 @@ static void pciasic_hwint1(struct pt_regs *regs)
133/* 133/*
134 * hwint 3 should deal with the PCI A - D interrupts, 134 * hwint 3 should deal with the PCI A - D interrupts,
135 */ 135 */
136static void pciasic_hwint3(struct pt_regs *regs) 136static void pciasic_hwint3(void)
137{ 137{
138 u8 pend = *(volatile char *)PCIMT_CSITPEND; 138 u8 pend = *(volatile char *)PCIMT_CSITPEND;
139 int irq; 139 int irq;
@@ -141,21 +141,21 @@ static void pciasic_hwint3(struct pt_regs *regs)
141 pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD); 141 pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
142 clear_c0_status(IE_IRQ3); 142 clear_c0_status(IE_IRQ3);
143 irq = PCIMT_IRQ_INT2 + ls1bit8(pend); 143 irq = PCIMT_IRQ_INT2 + ls1bit8(pend);
144 do_IRQ(irq, regs); 144 do_IRQ(irq);
145 set_c0_status(IE_IRQ3); 145 set_c0_status(IE_IRQ3);
146} 146}
147 147
148/* 148/*
149 * hwint 4 is used for only the onboard PCnet 32. 149 * hwint 4 is used for only the onboard PCnet 32.
150 */ 150 */
151static void pciasic_hwint4(struct pt_regs *regs) 151static void pciasic_hwint4(void)
152{ 152{
153 clear_c0_status(IE_IRQ4); 153 clear_c0_status(IE_IRQ4);
154 do_IRQ(PCIMT_IRQ_ETHERNET, regs); 154 do_IRQ(PCIMT_IRQ_ETHERNET);
155 set_c0_status(IE_IRQ4); 155 set_c0_status(IE_IRQ4);
156} 156}
157 157
158asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 158asmlinkage void plat_irq_dispatch(void)
159{ 159{
160 unsigned int pending = read_c0_status() & read_c0_cause(); 160 unsigned int pending = read_c0_status() & read_c0_cause();
161 static unsigned char led_cache; 161 static unsigned char led_cache;
@@ -163,17 +163,17 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
163 *(volatile unsigned char *) PCIMT_CSLED = ++led_cache; 163 *(volatile unsigned char *) PCIMT_CSLED = ++led_cache;
164 164
165 if (pending & 0x0800) 165 if (pending & 0x0800)
166 pciasic_hwint1(regs); 166 pciasic_hwint1();
167 else if (pending & 0x4000) 167 else if (pending & 0x4000)
168 pciasic_hwint4(regs); 168 pciasic_hwint4();
169 else if (pending & 0x2000) 169 else if (pending & 0x2000)
170 pciasic_hwint3(regs); 170 pciasic_hwint3();
171 else if (pending & 0x1000) 171 else if (pending & 0x1000)
172 pciasic_hwint2(regs); 172 pciasic_hwint2();
173 else if (pending & 0x8000) 173 else if (pending & 0x8000)
174 pciasic_hwint5(regs); 174 pciasic_hwint5();
175 else if (pending & 0x0400) 175 else if (pending & 0x0400)
176 pciasic_hwint0(regs); 176 pciasic_hwint0();
177} 177}
178 178
179void __init init_pciasic(void) 179void __init init_pciasic(void)
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index cd176f6a06c8..8266a88a3f88 100644
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -576,24 +576,24 @@ static int tx4927_irq_nested(void)
576 return (sw_irq); 576 return (sw_irq);
577} 577}
578 578
579asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 579asmlinkage void plat_irq_dispatch(void)
580{ 580{
581 unsigned int pending = read_c0_status() & read_c0_cause(); 581 unsigned int pending = read_c0_status() & read_c0_cause();
582 582
583 if (pending & STATUSF_IP7) /* cpu timer */ 583 if (pending & STATUSF_IP7) /* cpu timer */
584 do_IRQ(TX4927_IRQ_CPU_TIMER, regs); 584 do_IRQ(TX4927_IRQ_CPU_TIMER);
585 else if (pending & STATUSF_IP2) { /* tx4927 pic */ 585 else if (pending & STATUSF_IP2) { /* tx4927 pic */
586 unsigned int irq = tx4927_irq_nested(); 586 unsigned int irq = tx4927_irq_nested();
587 587
588 if (unlikely(irq == 0)) { 588 if (unlikely(irq == 0)) {
589 spurious_interrupt(regs); 589 spurious_interrupt();
590 return; 590 return;
591 } 591 }
592 do_IRQ(irq, regs); 592 do_IRQ(irq);
593 } else if (pending & STATUSF_IP0) /* user line 0 */ 593 } else if (pending & STATUSF_IP0) /* user line 0 */
594 do_IRQ(TX4927_IRQ_USER0, regs); 594 do_IRQ(TX4927_IRQ_USER0);
595 else if (pending & STATUSF_IP1) /* user line 1 */ 595 else if (pending & STATUSF_IP1) /* user line 1 */
596 do_IRQ(TX4927_IRQ_USER1, regs); 596 do_IRQ(TX4927_IRQ_USER1);
597 else 597 else
598 spurious_interrupt(regs); 598 spurious_interrupt();
599} 599}
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index f0d70c476005..bea19098ac28 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -58,6 +58,7 @@
58#include <asm/page.h> 58#include <asm/page.h>
59#include <asm/io.h> 59#include <asm/io.h>
60#include <asm/irq.h> 60#include <asm/irq.h>
61#include <asm/irq_regs.h>
61#include <asm/processor.h> 62#include <asm/processor.h>
62#include <asm/ptrace.h> 63#include <asm/ptrace.h>
63#include <asm/reboot.h> 64#include <asm/reboot.h>
@@ -160,8 +161,7 @@ int tx4927_pci66 = 0; /* 0:auto */
160char *toshiba_name = ""; 161char *toshiba_name = "";
161 162
162#ifdef CONFIG_PCI 163#ifdef CONFIG_PCI
163static void tx4927_pcierr_interrupt(int irq, void *dev_id, 164static void tx4927_pcierr_interrupt(int irq, void *dev_id)
164 struct pt_regs *regs)
165{ 165{
166#ifdef CONFIG_BLK_DEV_IDEPCI 166#ifdef CONFIG_BLK_DEV_IDEPCI
167 /* ignore MasterAbort for ide probing... */ 167 /* ignore MasterAbort for ide probing... */
@@ -185,7 +185,7 @@ static void tx4927_pcierr_interrupt(int irq, void *dev_id,
185 (unsigned long) tx4927_ccfgptr->ccfg, 185 (unsigned long) tx4927_ccfgptr->ccfg,
186 (unsigned long) (tx4927_ccfgptr->tear >> 32), 186 (unsigned long) (tx4927_ccfgptr->tear >> 32),
187 (unsigned long) tx4927_ccfgptr->tear); 187 (unsigned long) tx4927_ccfgptr->tear);
188 show_regs(regs); 188 show_regs(get_irq_regs());
189} 189}
190 190
191void __init toshiba_rbtx4927_pci_irq_init(void) 191void __init toshiba_rbtx4927_pci_irq_init(void)
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
index cbfb34221b59..b6024749b8f4 100644
--- a/arch/mips/tx4938/common/irq.c
+++ b/arch/mips/tx4938/common/irq.c
@@ -104,8 +104,6 @@ tx4938_irq_cp0_init(void)
104 irq_desc[i].depth = 1; 104 irq_desc[i].depth = 1;
105 irq_desc[i].chip = &tx4938_irq_cp0_type; 105 irq_desc[i].chip = &tx4938_irq_cp0_type;
106 } 106 }
107
108 return;
109} 107}
110 108
111static unsigned int 109static unsigned int
@@ -113,7 +111,7 @@ tx4938_irq_cp0_startup(unsigned int irq)
113{ 111{
114 tx4938_irq_cp0_enable(irq); 112 tx4938_irq_cp0_enable(irq);
115 113
116 return (0); 114 return 0;
117} 115}
118 116
119static void 117static void
@@ -144,16 +142,12 @@ tx4938_irq_cp0_disable(unsigned int irq)
144 clear_c0_status(tx4938_irq_cp0_mask(irq)); 142 clear_c0_status(tx4938_irq_cp0_mask(irq));
145 143
146 spin_unlock_irqrestore(&tx4938_cp0_lock, flags); 144 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
147
148 return;
149} 145}
150 146
151static void 147static void
152tx4938_irq_cp0_mask_and_ack(unsigned int irq) 148tx4938_irq_cp0_mask_and_ack(unsigned int irq)
153{ 149{
154 tx4938_irq_cp0_disable(irq); 150 tx4938_irq_cp0_disable(irq);
155
156 return;
157} 151}
158 152
159static void 153static void
@@ -162,8 +156,6 @@ tx4938_irq_cp0_end(unsigned int irq)
162 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 156 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
163 tx4938_irq_cp0_enable(irq); 157 tx4938_irq_cp0_enable(irq);
164 } 158 }
165
166 return;
167} 159}
168 160
169/**********************************************************************************/ 161/**********************************************************************************/
@@ -227,7 +219,7 @@ tx4938_irq_pic_addr(int irq)
227 } 219 }
228 } 220 }
229 221
230 return (0); 222 return 0;
231} 223}
232 224
233u32 225u32
@@ -278,7 +270,7 @@ tx4938_irq_pic_mask(int irq)
278 return (0x00000007); 270 return (0x00000007);
279 } 271 }
280 } 272 }
281 return (0x00000000); 273 return 0x00000000;
282} 274}
283 275
284static void 276static void
@@ -292,8 +284,6 @@ tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
292 TX4938_WR(pic_reg, val); 284 TX4938_WR(pic_reg, val);
293 mmiowb(); 285 mmiowb();
294 TX4938_RD(pic_reg); 286 TX4938_RD(pic_reg);
295
296 return;
297} 287}
298 288
299static void __init 289static void __init
@@ -317,8 +307,6 @@ tx4938_irq_pic_init(void)
317 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */ 307 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
318 308
319 spin_unlock_irqrestore(&tx4938_pic_lock, flags); 309 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
320
321 return;
322} 310}
323 311
324static unsigned int 312static unsigned int
@@ -326,15 +314,13 @@ tx4938_irq_pic_startup(unsigned int irq)
326{ 314{
327 tx4938_irq_pic_enable(irq); 315 tx4938_irq_pic_enable(irq);
328 316
329 return (0); 317 return 0;
330} 318}
331 319
332static void 320static void
333tx4938_irq_pic_shutdown(unsigned int irq) 321tx4938_irq_pic_shutdown(unsigned int irq)
334{ 322{
335 tx4938_irq_pic_disable(irq); 323 tx4938_irq_pic_disable(irq);
336
337 return;
338} 324}
339 325
340static void 326static void
@@ -348,8 +334,6 @@ tx4938_irq_pic_enable(unsigned int irq)
348 tx4938_irq_pic_mask(irq)); 334 tx4938_irq_pic_mask(irq));
349 335
350 spin_unlock_irqrestore(&tx4938_pic_lock, flags); 336 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
351
352 return;
353} 337}
354 338
355static void 339static void
@@ -363,16 +347,12 @@ tx4938_irq_pic_disable(unsigned int irq)
363 tx4938_irq_pic_mask(irq), 0); 347 tx4938_irq_pic_mask(irq), 0);
364 348
365 spin_unlock_irqrestore(&tx4938_pic_lock, flags); 349 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
366
367 return;
368} 350}
369 351
370static void 352static void
371tx4938_irq_pic_mask_and_ack(unsigned int irq) 353tx4938_irq_pic_mask_and_ack(unsigned int irq)
372{ 354{
373 tx4938_irq_pic_disable(irq); 355 tx4938_irq_pic_disable(irq);
374
375 return;
376} 356}
377 357
378static void 358static void
@@ -381,8 +361,6 @@ tx4938_irq_pic_end(unsigned int irq)
381 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 361 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
382 tx4938_irq_pic_enable(irq); 362 tx4938_irq_pic_enable(irq);
383 } 363 }
384
385 return;
386} 364}
387 365
388/**********************************************************************************/ 366/**********************************************************************************/
@@ -394,8 +372,6 @@ tx4938_irq_init(void)
394{ 372{
395 tx4938_irq_cp0_init(); 373 tx4938_irq_cp0_init();
396 tx4938_irq_pic_init(); 374 tx4938_irq_pic_init();
397
398 return;
399} 375}
400 376
401int 377int
@@ -417,23 +393,23 @@ tx4938_irq_nested(void)
417 } 393 }
418 394
419 wbflush(); 395 wbflush();
420 return (sw_irq); 396 return sw_irq;
421} 397}
422 398
423asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 399asmlinkage void plat_irq_dispatch(void)
424{ 400{
425 unsigned int pending = read_c0_cause() & read_c0_status(); 401 unsigned int pending = read_c0_cause() & read_c0_status();
426 402
427 if (pending & STATUSF_IP7) 403 if (pending & STATUSF_IP7)
428 do_IRQ(TX4938_IRQ_CPU_TIMER, regs); 404 do_IRQ(TX4938_IRQ_CPU_TIMER);
429 else if (pending & STATUSF_IP2) { 405 else if (pending & STATUSF_IP2) {
430 int irq = tx4938_irq_nested(); 406 int irq = tx4938_irq_nested();
431 if (irq) 407 if (irq)
432 do_IRQ(irq, regs); 408 do_IRQ(irq);
433 else 409 else
434 spurious_interrupt(regs); 410 spurious_interrupt();
435 } else if (pending & STATUSF_IP1) 411 } else if (pending & STATUSF_IP1)
436 do_IRQ(TX4938_IRQ_USER1, regs); 412 do_IRQ(TX4938_IRQ_USER1);
437 else if (pending & STATUSF_IP0) 413 else if (pending & STATUSF_IP0)
438 do_IRQ(TX4938_IRQ_USER0, regs); 414 do_IRQ(TX4938_IRQ_USER0);
439} 415}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
index fae3136f462d..b926e6a75c29 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
@@ -35,7 +35,8 @@ void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)
35} 35}
36 36
37static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait); 37static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait);
38static void txx9_spi_interrupt(int irq, void *dev_id, struct pt_regs *regs) 38
39static void txx9_spi_interrupt(int irq, void *dev_id)
39{ 40{
40 /* disable rx intr */ 41 /* disable rx intr */
41 tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE; 42 tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE;
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index 7a5c31d58378..c215c0d39fae 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -635,7 +635,7 @@ int vr41xx_set_intassign(unsigned int irq, unsigned char intassign)
635 635
636EXPORT_SYMBOL(vr41xx_set_intassign); 636EXPORT_SYMBOL(vr41xx_set_intassign);
637 637
638static int icu_get_irq(unsigned int irq, struct pt_regs *regs) 638static int icu_get_irq(unsigned int irq)
639{ 639{
640 uint16_t pend1, pend2; 640 uint16_t pend1, pend2;
641 uint16_t mask1, mask2; 641 uint16_t mask1, mask2;
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index 4733c5344467..397ba94cd7ec 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -25,7 +25,7 @@
25#include <asm/vr41xx/irq.h> 25#include <asm/vr41xx/irq.h>
26 26
27typedef struct irq_cascade { 27typedef struct irq_cascade {
28 int (*get_irq)(unsigned int, struct pt_regs *); 28 int (*get_irq)(unsigned int);
29} irq_cascade_t; 29} irq_cascade_t;
30 30
31static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned; 31static irq_cascade_t irq_cascade[NR_IRQS] __cacheline_aligned;
@@ -36,7 +36,7 @@ static struct irqaction cascade_irqaction = {
36 .name = "cascade", 36 .name = "cascade",
37}; 37};
38 38
39int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)) 39int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int))
40{ 40{
41 int retval = 0; 41 int retval = 0;
42 42
@@ -59,7 +59,7 @@ int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)
59 59
60EXPORT_SYMBOL_GPL(cascade_irq); 60EXPORT_SYMBOL_GPL(cascade_irq);
61 61
62static void irq_dispatch(unsigned int irq, struct pt_regs *regs) 62static void irq_dispatch(unsigned int irq)
63{ 63{
64 irq_cascade_t *cascade; 64 irq_cascade_t *cascade;
65 struct irq_desc *desc; 65 struct irq_desc *desc;
@@ -74,39 +74,39 @@ static void irq_dispatch(unsigned int irq, struct pt_regs *regs)
74 unsigned int source_irq = irq; 74 unsigned int source_irq = irq;
75 desc = irq_desc + source_irq; 75 desc = irq_desc + source_irq;
76 desc->chip->ack(source_irq); 76 desc->chip->ack(source_irq);
77 irq = cascade->get_irq(irq, regs); 77 irq = cascade->get_irq(irq);
78 if (irq < 0) 78 if (irq < 0)
79 atomic_inc(&irq_err_count); 79 atomic_inc(&irq_err_count);
80 else 80 else
81 irq_dispatch(irq, regs); 81 irq_dispatch(irq);
82 desc->chip->end(source_irq); 82 desc->chip->end(source_irq);
83 } else 83 } else
84 do_IRQ(irq, regs); 84 do_IRQ(irq);
85} 85}
86 86
87asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 87asmlinkage void plat_irq_dispatch(void)
88{ 88{
89 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; 89 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
90 90
91 if (pending & CAUSEF_IP7) 91 if (pending & CAUSEF_IP7)
92 do_IRQ(7, regs); 92 do_IRQ(7);
93 else if (pending & 0x7800) { 93 else if (pending & 0x7800) {
94 if (pending & CAUSEF_IP3) 94 if (pending & CAUSEF_IP3)
95 irq_dispatch(3, regs); 95 irq_dispatch(3);
96 else if (pending & CAUSEF_IP4) 96 else if (pending & CAUSEF_IP4)
97 irq_dispatch(4, regs); 97 irq_dispatch(4);
98 else if (pending & CAUSEF_IP5) 98 else if (pending & CAUSEF_IP5)
99 irq_dispatch(5, regs); 99 irq_dispatch(5);
100 else if (pending & CAUSEF_IP6) 100 else if (pending & CAUSEF_IP6)
101 irq_dispatch(6, regs); 101 irq_dispatch(6);
102 } else if (pending & CAUSEF_IP2) 102 } else if (pending & CAUSEF_IP2)
103 irq_dispatch(2, regs); 103 irq_dispatch(2);
104 else if (pending & CAUSEF_IP0) 104 else if (pending & CAUSEF_IP0)
105 do_IRQ(0, regs); 105 do_IRQ(0);
106 else if (pending & CAUSEF_IP1) 106 else if (pending & CAUSEF_IP1)
107 do_IRQ(1, regs); 107 do_IRQ(1);
108 else 108 else
109 spurious_interrupt(regs); 109 spurious_interrupt();
110} 110}
111 111
112void __init arch_init_irq(void) 112void __init arch_init_irq(void)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 10:38:32 -0500