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-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h72
-rw-r--r--arch/mips/netlogic/xlp/nlm_hal.c15
-rw-r--r--arch/mips/netlogic/xlp/wakeup.c2
-rw-r--r--arch/mips/pci/pci-xlp.c2
4 files changed, 65 insertions, 26 deletions
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 3fcbe7409177..f10bf3bba58f 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -150,12 +150,19 @@
150#define PIC_IRT0 0x74 150#define PIC_IRT0 0x74
151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) 151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
152 152
153#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL 153#define PIC_9XX_PENDING_0 0x6
154#define PIC_9XX_PENDING_1 0x8
155#define PIC_9XX_PENDING_2 0xa
156#define PIC_9XX_PENDING_3 0xc
157
158#define PIC_9XX_IRT0 0x1c0
159#define PIC_9XX_IRT(i) (PIC_9XX_IRT0 + ((i) * 2))
154 160
155/* 161/*
156 * IRT Map 162 * IRT Map
157 */ 163 */
158#define PIC_NUM_IRTS 160 164#define PIC_NUM_IRTS 160
165#define PIC_9XX_NUM_IRTS 256
159 166
160#define PIC_IRT_WD_0_INDEX 0 167#define PIC_IRT_WD_0_INDEX 0
161#define PIC_IRT_WD_1_INDEX 1 168#define PIC_IRT_WD_1_INDEX 1
@@ -205,30 +212,26 @@
205 212
206#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) 213#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
207#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) 214#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
208#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) 215#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \
216 XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node))
209#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) 217#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
210 218
211/* We use PIC on node 0 as a timer */ 219/* We use PIC on node 0 as a timer */
212#define pic_timer_freq() nlm_get_pic_frequency(0) 220#define pic_timer_freq() nlm_get_pic_frequency(0)
213 221
214/* IRT and h/w interrupt routines */ 222/* IRT and h/w interrupt routines */
215static inline int
216nlm_pic_read_irt(uint64_t base, int irt_index)
217{
218 return nlm_read_pic_reg(base, PIC_IRT(irt_index));
219}
220
221static inline void 223static inline void
222nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) 224nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
225 int sch, int vec, int dt, int db, int cpu)
223{ 226{
224 uint64_t val; 227 uint64_t val;
225 228
226 val = nlm_read_pic_reg(base, PIC_IRT(irt)); 229 val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) |
227 /* clear cpuset and mask */ 230 ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) |
228 val &= ~((0x7ull << 16) | 0xffff); 231 ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) |
229 /* set DB, cpuset and cpumask */ 232 (cpu & 0x3ff);
230 val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf)); 233
231 nlm_write_pic_reg(base, PIC_IRT(irt), val); 234 nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val);
232} 235}
233 236
234static inline void 237static inline void
@@ -249,9 +252,13 @@ static inline void
249nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, 252nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
250 int sch, int vec, int cpu) 253 int sch, int vec, int cpu)
251{ 254{
252 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, 255 if (cpu_is_xlp9xx())
253 (cpu >> 4), /* thread group */ 256 nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec,
254 1 << (cpu & 0xf)); /* thread mask */ 257 1, 0, cpu);
258 else
259 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
260 (cpu >> 4), /* thread group */
261 1 << (cpu & 0xf)); /* thread mask */
255} 262}
256 263
257static inline uint64_t 264static inline uint64_t
@@ -293,8 +300,13 @@ nlm_pic_enable_irt(uint64_t base, int irt)
293{ 300{
294 uint64_t reg; 301 uint64_t reg;
295 302
296 reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 303 if (cpu_is_xlp9xx()) {
297 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); 304 reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
305 nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22));
306 } else {
307 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
308 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
309 }
298} 310}
299 311
300static inline void 312static inline void
@@ -302,8 +314,15 @@ nlm_pic_disable_irt(uint64_t base, int irt)
302{ 314{
303 uint64_t reg; 315 uint64_t reg;
304 316
305 reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 317 if (cpu_is_xlp9xx()) {
306 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31)); 318 reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt));
319 reg &= ~((uint64_t)1 << 22);
320 nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg);
321 } else {
322 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
323 reg &= ~((uint64_t)1 << 31);
324 nlm_write_pic_reg(base, PIC_IRT(irt), reg);
325 }
307} 326}
308 327
309static inline void 328static inline void
@@ -311,8 +330,13 @@ nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
311{ 330{
312 uint64_t ipi; 331 uint64_t ipi;
313 332
314 ipi = ((uint64_t)nmi << 31) | (irq << 20); 333 if (cpu_is_xlp9xx())
315 ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */ 334 ipi = (nmi << 23) | (irq << 24) |
335 (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt;
336 else
337 ipi = ((uint64_t)nmi << 31) | (irq << 20) |
338 ((hwt >> 4) << 16) | (1 << (hwt & 0xf));
339
316 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 340 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
317} 341}
318 342
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 5f191f54f9c0..2d31cf1137fb 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -69,6 +69,17 @@ int nlm_irq_to_irt(int irq)
69 uint64_t pcibase; 69 uint64_t pcibase;
70 int devoff, irt; 70 int devoff, irt;
71 71
72 /* bypass for 9xx */
73 if (cpu_is_xlp9xx()) {
74 switch (irq) {
75 case PIC_UART_0_IRQ:
76 return 133;
77 case PIC_UART_1_IRQ:
78 return 134;
79 }
80 return -1;
81 }
82
72 devoff = 0; 83 devoff = 0;
73 switch (irq) { 84 switch (irq) {
74 case PIC_UART_0_IRQ: 85 case PIC_UART_0_IRQ:
@@ -277,6 +288,10 @@ static unsigned int nlm_2xx_get_pic_frequency(int node)
277 288
278unsigned int nlm_get_pic_frequency(int node) 289unsigned int nlm_get_pic_frequency(int node)
279{ 290{
291 /* TODO Has to calculate freq as like 2xx */
292 if (cpu_is_xlp9xx())
293 return 250000000;
294
280 if (cpu_is_xlpii()) 295 if (cpu_is_xlpii())
281 return nlm_2xx_get_pic_frequency(node); 296 return nlm_2xx_get_pic_frequency(node);
282 else 297 else
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index e6f77c053658..f11035b1ad11 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -47,8 +47,8 @@
47#include <asm/netlogic/mips-extns.h> 47#include <asm/netlogic/mips-extns.h>
48 48
49#include <asm/netlogic/xlp-hal/iomap.h> 49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/pic.h>
51#include <asm/netlogic/xlp-hal/xlp.h> 50#include <asm/netlogic/xlp-hal/xlp.h>
51#include <asm/netlogic/xlp-hal/pic.h>
52#include <asm/netlogic/xlp-hal/sys.h> 52#include <asm/netlogic/xlp-hal/sys.h>
53 53
54static int xlp_wakeup_core(uint64_t sysbase, int node, int core) 54static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c
index da7a37a55981..f390aa9970e6 100644
--- a/arch/mips/pci/pci-xlp.c
+++ b/arch/mips/pci/pci-xlp.c
@@ -50,8 +50,8 @@
50#include <asm/netlogic/mips-extns.h> 50#include <asm/netlogic/mips-extns.h>
51 51
52#include <asm/netlogic/xlp-hal/iomap.h> 52#include <asm/netlogic/xlp-hal/iomap.h>
53#include <asm/netlogic/xlp-hal/pic.h>
54#include <asm/netlogic/xlp-hal/xlp.h> 53#include <asm/netlogic/xlp-hal/xlp.h>
54#include <asm/netlogic/xlp-hal/pic.h>
55#include <asm/netlogic/xlp-hal/pcibus.h> 55#include <asm/netlogic/xlp-hal/pcibus.h>
56#include <asm/netlogic/xlp-hal/bridge.h> 56#include <asm/netlogic/xlp-hal/bridge.h>
57 57