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-rw-r--r--arch/mips/Kconfig7
-rw-r--r--arch/mips/alchemy/common/time.c2
-rw-r--r--arch/mips/cavium-octeon/setup.c2
-rw-r--r--arch/mips/configs/ip27_defconfig2
-rw-r--r--arch/mips/include/asm/atomic.h52
-rw-r--r--arch/mips/include/asm/mach-rc32434/gpio.h5
-rw-r--r--arch/mips/include/asm/mach-rc32434/irq.h3
-rw-r--r--arch/mips/include/asm/mach-rc32434/rb.h3
-rw-r--r--arch/mips/include/asm/ptrace.h2
-rw-r--r--arch/mips/include/asm/termios.h100
-rw-r--r--arch/mips/include/asm/txx9/tx4939.h1
-rw-r--r--arch/mips/kernel/genex.S6
-rw-r--r--arch/mips/kernel/mips-mt-fpaff.c3
-rw-r--r--arch/mips/kernel/traps.c16
-rw-r--r--arch/mips/lib/memcpy-inatomic.S2
-rw-r--r--arch/mips/lib/memcpy.S2
-rw-r--r--arch/mips/mm/c-r4k.c22
-rw-r--r--arch/mips/mm/fault.c21
-rw-r--r--arch/mips/pci/pci-rc32434.c11
-rw-r--r--arch/mips/rb532/devices.c57
-rw-r--r--arch/mips/rb532/gpio.c90
-rw-r--r--arch/mips/rb532/irq.c27
-rw-r--r--arch/mips/rb532/serial.c2
-rw-r--r--arch/mips/txx9/generic/setup_tx4939.c22
-rw-r--r--arch/mips/txx9/rbtx4939/setup.c1
25 files changed, 287 insertions, 174 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 52c80c2a57f2..600eef3f3ac7 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -351,7 +351,7 @@ config SGI_IP27
351 select ARC64 351 select ARC64
352 select BOOT_ELF64 352 select BOOT_ELF64
353 select DEFAULT_SGI_PARTITION 353 select DEFAULT_SGI_PARTITION
354 select DMA_IP27 354 select DMA_COHERENT
355 select SYS_HAS_EARLY_PRINTK 355 select SYS_HAS_EARLY_PRINTK
356 select HW_HAS_PCI 356 select HW_HAS_PCI
357 select NR_CPUS_DEFAULT_64 357 select NR_CPUS_DEFAULT_64
@@ -761,9 +761,6 @@ config CFE
761config DMA_COHERENT 761config DMA_COHERENT
762 bool 762 bool
763 763
764config DMA_IP27
765 bool
766
767config DMA_NONCOHERENT 764config DMA_NONCOHERENT
768 bool 765 bool
769 select DMA_NEED_PCI_MAP_STATE 766 select DMA_NEED_PCI_MAP_STATE
@@ -1368,7 +1365,7 @@ config CPU_SUPPORTS_64BIT_KERNEL
1368# 1365#
1369config HARDWARE_WATCHPOINTS 1366config HARDWARE_WATCHPOINTS
1370 bool 1367 bool
1371 default y if CPU_MIPS32 || CPU_MIPS64 1368 default y if CPU_MIPSR1 || CPU_MIPSR2
1372 1369
1373menu "Kernel type" 1370menu "Kernel type"
1374 1371
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 32880146cbc1..6fd441d16af5 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -89,7 +89,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
89 .irq = AU1000_RTC_MATCH2_INT, 89 .irq = AU1000_RTC_MATCH2_INT,
90 .set_next_event = au1x_rtcmatch2_set_next_event, 90 .set_next_event = au1x_rtcmatch2_set_next_event,
91 .set_mode = au1x_rtcmatch2_set_mode, 91 .set_mode = au1x_rtcmatch2_set_mode,
92 .cpumask = CPU_MASK_ALL, 92 .cpumask = CPU_MASK_ALL_PTR,
93}; 93};
94 94
95static struct irqaction au1x_rtcmatch2_irqaction = { 95static struct irqaction au1x_rtcmatch2_irqaction = {
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index e085feddb4a4..5f4e49ba4713 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -15,13 +15,11 @@
15#include <linux/serial.h> 15#include <linux/serial.h>
16#include <linux/types.h> 16#include <linux/types.h>
17#include <linux/string.h> /* for memset */ 17#include <linux/string.h> /* for memset */
18#include <linux/serial.h>
19#include <linux/tty.h> 18#include <linux/tty.h>
20#include <linux/time.h> 19#include <linux/time.h>
21#include <linux/platform_device.h> 20#include <linux/platform_device.h>
22#include <linux/serial_core.h> 21#include <linux/serial_core.h>
23#include <linux/serial_8250.h> 22#include <linux/serial_8250.h>
24#include <linux/string.h>
25 23
26#include <asm/processor.h> 24#include <asm/processor.h>
27#include <asm/reboot.h> 25#include <asm/reboot.h>
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig
index 34ea319be94c..f2baea3039bb 100644
--- a/arch/mips/configs/ip27_defconfig
+++ b/arch/mips/configs/ip27_defconfig
@@ -53,7 +53,7 @@ CONFIG_GENERIC_TIME=y
53CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 53CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
54CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y 54CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
55CONFIG_ARC=y 55CONFIG_ARC=y
56CONFIG_DMA_IP27=y 56CONFIG_DMA_COHERENT=y
57CONFIG_EARLY_PRINTK=y 57CONFIG_EARLY_PRINTK=y
58CONFIG_SYS_HAS_EARLY_PRINTK=y 58CONFIG_SYS_HAS_EARLY_PRINTK=y
59# CONFIG_NO_IOPORT is not set 59# CONFIG_NO_IOPORT is not set
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index c996c3b4d074..1b332e15ab52 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -50,7 +50,7 @@
50static __inline__ void atomic_add(int i, atomic_t * v) 50static __inline__ void atomic_add(int i, atomic_t * v)
51{ 51{
52 if (cpu_has_llsc && R10000_LLSC_WAR) { 52 if (cpu_has_llsc && R10000_LLSC_WAR) {
53 unsigned long temp; 53 int temp;
54 54
55 __asm__ __volatile__( 55 __asm__ __volatile__(
56 " .set mips3 \n" 56 " .set mips3 \n"
@@ -62,7 +62,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
62 : "=&r" (temp), "=m" (v->counter) 62 : "=&r" (temp), "=m" (v->counter)
63 : "Ir" (i), "m" (v->counter)); 63 : "Ir" (i), "m" (v->counter));
64 } else if (cpu_has_llsc) { 64 } else if (cpu_has_llsc) {
65 unsigned long temp; 65 int temp;
66 66
67 __asm__ __volatile__( 67 __asm__ __volatile__(
68 " .set mips3 \n" 68 " .set mips3 \n"
@@ -95,7 +95,7 @@ static __inline__ void atomic_add(int i, atomic_t * v)
95static __inline__ void atomic_sub(int i, atomic_t * v) 95static __inline__ void atomic_sub(int i, atomic_t * v)
96{ 96{
97 if (cpu_has_llsc && R10000_LLSC_WAR) { 97 if (cpu_has_llsc && R10000_LLSC_WAR) {
98 unsigned long temp; 98 int temp;
99 99
100 __asm__ __volatile__( 100 __asm__ __volatile__(
101 " .set mips3 \n" 101 " .set mips3 \n"
@@ -107,7 +107,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
107 : "=&r" (temp), "=m" (v->counter) 107 : "=&r" (temp), "=m" (v->counter)
108 : "Ir" (i), "m" (v->counter)); 108 : "Ir" (i), "m" (v->counter));
109 } else if (cpu_has_llsc) { 109 } else if (cpu_has_llsc) {
110 unsigned long temp; 110 int temp;
111 111
112 __asm__ __volatile__( 112 __asm__ __volatile__(
113 " .set mips3 \n" 113 " .set mips3 \n"
@@ -135,12 +135,12 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
135 */ 135 */
136static __inline__ int atomic_add_return(int i, atomic_t * v) 136static __inline__ int atomic_add_return(int i, atomic_t * v)
137{ 137{
138 unsigned long result; 138 int result;
139 139
140 smp_llsc_mb(); 140 smp_llsc_mb();
141 141
142 if (cpu_has_llsc && R10000_LLSC_WAR) { 142 if (cpu_has_llsc && R10000_LLSC_WAR) {
143 unsigned long temp; 143 int temp;
144 144
145 __asm__ __volatile__( 145 __asm__ __volatile__(
146 " .set mips3 \n" 146 " .set mips3 \n"
@@ -154,7 +154,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
154 : "Ir" (i), "m" (v->counter) 154 : "Ir" (i), "m" (v->counter)
155 : "memory"); 155 : "memory");
156 } else if (cpu_has_llsc) { 156 } else if (cpu_has_llsc) {
157 unsigned long temp; 157 int temp;
158 158
159 __asm__ __volatile__( 159 __asm__ __volatile__(
160 " .set mips3 \n" 160 " .set mips3 \n"
@@ -187,12 +187,12 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
187 187
188static __inline__ int atomic_sub_return(int i, atomic_t * v) 188static __inline__ int atomic_sub_return(int i, atomic_t * v)
189{ 189{
190 unsigned long result; 190 int result;
191 191
192 smp_llsc_mb(); 192 smp_llsc_mb();
193 193
194 if (cpu_has_llsc && R10000_LLSC_WAR) { 194 if (cpu_has_llsc && R10000_LLSC_WAR) {
195 unsigned long temp; 195 int temp;
196 196
197 __asm__ __volatile__( 197 __asm__ __volatile__(
198 " .set mips3 \n" 198 " .set mips3 \n"
@@ -206,7 +206,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
206 : "Ir" (i), "m" (v->counter) 206 : "Ir" (i), "m" (v->counter)
207 : "memory"); 207 : "memory");
208 } else if (cpu_has_llsc) { 208 } else if (cpu_has_llsc) {
209 unsigned long temp; 209 int temp;
210 210
211 __asm__ __volatile__( 211 __asm__ __volatile__(
212 " .set mips3 \n" 212 " .set mips3 \n"
@@ -247,12 +247,12 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
247 */ 247 */
248static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) 248static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
249{ 249{
250 unsigned long result; 250 int result;
251 251
252 smp_llsc_mb(); 252 smp_llsc_mb();
253 253
254 if (cpu_has_llsc && R10000_LLSC_WAR) { 254 if (cpu_has_llsc && R10000_LLSC_WAR) {
255 unsigned long temp; 255 int temp;
256 256
257 __asm__ __volatile__( 257 __asm__ __volatile__(
258 " .set mips3 \n" 258 " .set mips3 \n"
@@ -270,7 +270,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
270 : "Ir" (i), "m" (v->counter) 270 : "Ir" (i), "m" (v->counter)
271 : "memory"); 271 : "memory");
272 } else if (cpu_has_llsc) { 272 } else if (cpu_has_llsc) {
273 unsigned long temp; 273 int temp;
274 274
275 __asm__ __volatile__( 275 __asm__ __volatile__(
276 " .set mips3 \n" 276 " .set mips3 \n"
@@ -429,7 +429,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
429static __inline__ void atomic64_add(long i, atomic64_t * v) 429static __inline__ void atomic64_add(long i, atomic64_t * v)
430{ 430{
431 if (cpu_has_llsc && R10000_LLSC_WAR) { 431 if (cpu_has_llsc && R10000_LLSC_WAR) {
432 unsigned long temp; 432 long temp;
433 433
434 __asm__ __volatile__( 434 __asm__ __volatile__(
435 " .set mips3 \n" 435 " .set mips3 \n"
@@ -441,7 +441,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
441 : "=&r" (temp), "=m" (v->counter) 441 : "=&r" (temp), "=m" (v->counter)
442 : "Ir" (i), "m" (v->counter)); 442 : "Ir" (i), "m" (v->counter));
443 } else if (cpu_has_llsc) { 443 } else if (cpu_has_llsc) {
444 unsigned long temp; 444 long temp;
445 445
446 __asm__ __volatile__( 446 __asm__ __volatile__(
447 " .set mips3 \n" 447 " .set mips3 \n"
@@ -474,7 +474,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
474static __inline__ void atomic64_sub(long i, atomic64_t * v) 474static __inline__ void atomic64_sub(long i, atomic64_t * v)
475{ 475{
476 if (cpu_has_llsc && R10000_LLSC_WAR) { 476 if (cpu_has_llsc && R10000_LLSC_WAR) {
477 unsigned long temp; 477 long temp;
478 478
479 __asm__ __volatile__( 479 __asm__ __volatile__(
480 " .set mips3 \n" 480 " .set mips3 \n"
@@ -486,7 +486,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
486 : "=&r" (temp), "=m" (v->counter) 486 : "=&r" (temp), "=m" (v->counter)
487 : "Ir" (i), "m" (v->counter)); 487 : "Ir" (i), "m" (v->counter));
488 } else if (cpu_has_llsc) { 488 } else if (cpu_has_llsc) {
489 unsigned long temp; 489 long temp;
490 490
491 __asm__ __volatile__( 491 __asm__ __volatile__(
492 " .set mips3 \n" 492 " .set mips3 \n"
@@ -514,12 +514,12 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
514 */ 514 */
515static __inline__ long atomic64_add_return(long i, atomic64_t * v) 515static __inline__ long atomic64_add_return(long i, atomic64_t * v)
516{ 516{
517 unsigned long result; 517 long result;
518 518
519 smp_llsc_mb(); 519 smp_llsc_mb();
520 520
521 if (cpu_has_llsc && R10000_LLSC_WAR) { 521 if (cpu_has_llsc && R10000_LLSC_WAR) {
522 unsigned long temp; 522 long temp;
523 523
524 __asm__ __volatile__( 524 __asm__ __volatile__(
525 " .set mips3 \n" 525 " .set mips3 \n"
@@ -533,7 +533,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
533 : "Ir" (i), "m" (v->counter) 533 : "Ir" (i), "m" (v->counter)
534 : "memory"); 534 : "memory");
535 } else if (cpu_has_llsc) { 535 } else if (cpu_has_llsc) {
536 unsigned long temp; 536 long temp;
537 537
538 __asm__ __volatile__( 538 __asm__ __volatile__(
539 " .set mips3 \n" 539 " .set mips3 \n"
@@ -566,12 +566,12 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
566 566
567static __inline__ long atomic64_sub_return(long i, atomic64_t * v) 567static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
568{ 568{
569 unsigned long result; 569 long result;
570 570
571 smp_llsc_mb(); 571 smp_llsc_mb();
572 572
573 if (cpu_has_llsc && R10000_LLSC_WAR) { 573 if (cpu_has_llsc && R10000_LLSC_WAR) {
574 unsigned long temp; 574 long temp;
575 575
576 __asm__ __volatile__( 576 __asm__ __volatile__(
577 " .set mips3 \n" 577 " .set mips3 \n"
@@ -585,7 +585,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
585 : "Ir" (i), "m" (v->counter) 585 : "Ir" (i), "m" (v->counter)
586 : "memory"); 586 : "memory");
587 } else if (cpu_has_llsc) { 587 } else if (cpu_has_llsc) {
588 unsigned long temp; 588 long temp;
589 589
590 __asm__ __volatile__( 590 __asm__ __volatile__(
591 " .set mips3 \n" 591 " .set mips3 \n"
@@ -626,12 +626,12 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
626 */ 626 */
627static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) 627static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
628{ 628{
629 unsigned long result; 629 long result;
630 630
631 smp_llsc_mb(); 631 smp_llsc_mb();
632 632
633 if (cpu_has_llsc && R10000_LLSC_WAR) { 633 if (cpu_has_llsc && R10000_LLSC_WAR) {
634 unsigned long temp; 634 long temp;
635 635
636 __asm__ __volatile__( 636 __asm__ __volatile__(
637 " .set mips3 \n" 637 " .set mips3 \n"
@@ -649,7 +649,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
649 : "Ir" (i), "m" (v->counter) 649 : "Ir" (i), "m" (v->counter)
650 : "memory"); 650 : "memory");
651 } else if (cpu_has_llsc) { 651 } else if (cpu_has_llsc) {
652 unsigned long temp; 652 long temp;
653 653
654 __asm__ __volatile__( 654 __asm__ __volatile__(
655 " .set mips3 \n" 655 " .set mips3 \n"
diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h
index b5cf6457305a..3cb50d17b62d 100644
--- a/arch/mips/include/asm/mach-rc32434/gpio.h
+++ b/arch/mips/include/asm/mach-rc32434/gpio.h
@@ -80,11 +80,8 @@ struct rb532_gpio_reg {
80/* Compact Flash GPIO pin */ 80/* Compact Flash GPIO pin */
81#define CF_GPIO_NUM 13 81#define CF_GPIO_NUM 13
82 82
83extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
84extern unsigned get_434_reg(unsigned reg_offs);
85extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
86extern unsigned char get_latch_u5(void);
87extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); 83extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
88extern void rb532_gpio_set_istat(int bit, unsigned gpio); 84extern void rb532_gpio_set_istat(int bit, unsigned gpio);
85extern void rb532_gpio_set_func(unsigned gpio);
89 86
90#endif /* _RC32434_GPIO_H_ */ 87#endif /* _RC32434_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h
index 56738d8ec4e2..023a5b100ed0 100644
--- a/arch/mips/include/asm/mach-rc32434/irq.h
+++ b/arch/mips/include/asm/mach-rc32434/irq.h
@@ -30,4 +30,7 @@
30#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9) 30#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
31#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10) 31#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
32 32
33#define GPIO_MAPPED_IRQ_BASE GROUP4_IRQ_BASE
34#define GPIO_MAPPED_IRQ_GROUP 4
35
33#endif /* __ASM_RC32434_IRQ_H */ 36#endif /* __ASM_RC32434_IRQ_H */
diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
index f25a84916703..6dc5f8df1f3e 100644
--- a/arch/mips/include/asm/mach-rc32434/rb.h
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -83,4 +83,7 @@ struct mpmc_device {
83 void __iomem *base; 83 void __iomem *base;
84}; 84};
85 85
86extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
87extern unsigned char get_latch_u5(void);
88
86#endif /* __ASM_RC32434_RB_H */ 89#endif /* __ASM_RC32434_RB_H */
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index 1f30d16d4669..ce47118e52b7 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -105,7 +105,7 @@ struct pt_watch_regs {
105 enum pt_watch_style style; 105 enum pt_watch_style style;
106 union { 106 union {
107 struct mips32_watch_regs mips32; 107 struct mips32_watch_regs mips32;
108 struct mips32_watch_regs mips64; 108 struct mips64_watch_regs mips64;
109 }; 109 };
110}; 110};
111 111
diff --git a/arch/mips/include/asm/termios.h b/arch/mips/include/asm/termios.h
index a275661fa7e1..8f77f774a2a0 100644
--- a/arch/mips/include/asm/termios.h
+++ b/arch/mips/include/asm/termios.h
@@ -9,6 +9,7 @@
9#ifndef _ASM_TERMIOS_H 9#ifndef _ASM_TERMIOS_H
10#define _ASM_TERMIOS_H 10#define _ASM_TERMIOS_H
11 11
12#include <linux/errno.h>
12#include <asm/termbits.h> 13#include <asm/termbits.h>
13#include <asm/ioctls.h> 14#include <asm/ioctls.h>
14 15
@@ -94,38 +95,81 @@ struct termio {
94/* 95/*
95 * Translate a "termio" structure into a "termios". Ugh. 96 * Translate a "termio" structure into a "termios". Ugh.
96 */ 97 */
97#define user_termio_to_kernel_termios(termios, termio) \ 98static inline int user_termio_to_kernel_termios(struct ktermios *termios,
98({ \ 99 struct termio __user *termio)
99 unsigned short tmp; \ 100{
100 get_user(tmp, &(termio)->c_iflag); \ 101 unsigned short iflag, oflag, cflag, lflag;
101 (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \ 102 unsigned int err;
102 get_user(tmp, &(termio)->c_oflag); \ 103
103 (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \ 104 if (!access_ok(VERIFY_READ, termio, sizeof(struct termio)))
104 get_user(tmp, &(termio)->c_cflag); \ 105 return -EFAULT;
105 (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \ 106
106 get_user(tmp, &(termio)->c_lflag); \ 107 err = __get_user(iflag, &termio->c_iflag);
107 (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \ 108 termios->c_iflag = (termios->c_iflag & 0xffff0000) | iflag;
108 get_user((termios)->c_line, &(termio)->c_line); \ 109 err |=__get_user(oflag, &termio->c_oflag);
109 copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ 110 termios->c_oflag = (termios->c_oflag & 0xffff0000) | oflag;
110}) 111 err |=__get_user(cflag, &termio->c_cflag);
112 termios->c_cflag = (termios->c_cflag & 0xffff0000) | cflag;
113 err |=__get_user(lflag, &termio->c_lflag);
114 termios->c_lflag = (termios->c_lflag & 0xffff0000) | lflag;
115 err |=__get_user(termios->c_line, &termio->c_line);
116 if (err)
117 return -EFAULT;
118
119 if (__copy_from_user(termios->c_cc, termio->c_cc, NCC))
120 return -EFAULT;
121
122 return 0;
123}
111 124
112/* 125/*
113 * Translate a "termios" structure into a "termio". Ugh. 126 * Translate a "termios" structure into a "termio". Ugh.
114 */ 127 */
115#define kernel_termios_to_user_termio(termio, termios) \ 128static inline int kernel_termios_to_user_termio(struct termio __user *termio,
116({ \ 129 struct ktermios *termios)
117 put_user((termios)->c_iflag, &(termio)->c_iflag); \ 130{
118 put_user((termios)->c_oflag, &(termio)->c_oflag); \ 131 int err;
119 put_user((termios)->c_cflag, &(termio)->c_cflag); \ 132
120 put_user((termios)->c_lflag, &(termio)->c_lflag); \ 133 if (!access_ok(VERIFY_WRITE, termio, sizeof(struct termio)))
121 put_user((termios)->c_line, &(termio)->c_line); \ 134 return -EFAULT;
122 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ 135
123}) 136 err = __put_user(termios->c_iflag, &termio->c_iflag);
124 137 err |= __put_user(termios->c_oflag, &termio->c_oflag);
125#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) 138 err |= __put_user(termios->c_cflag, &termio->c_cflag);
126#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) 139 err |= __put_user(termios->c_lflag, &termio->c_lflag);
127#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) 140 err |= __put_user(termios->c_line, &termio->c_line);
128#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) 141 if (err)
142 return -EFAULT;
143
144 if (__copy_to_user(termio->c_cc, termios->c_cc, NCC))
145 return -EFAULT;
146
147 return 0;
148}
149
150static inline int user_termios_to_kernel_termios(struct ktermios __user *k,
151 struct termios2 *u)
152{
153 return copy_from_user(k, u, sizeof(struct termios2)) ? -EFAULT : 0;
154}
155
156static inline int kernel_termios_to_user_termios(struct termios2 __user *u,
157 struct ktermios *k)
158{
159 return copy_to_user(u, k, sizeof(struct termios2)) ? -EFAULT : 0;
160}
161
162static inline int user_termios_to_kernel_termios_1(struct ktermios *k,
163 struct termios __user *u)
164{
165 return copy_from_user(k, u, sizeof(struct termios)) ? -EFAULT : 0;
166}
167
168static inline int kernel_termios_to_user_termios_1(struct termios __user *u,
169 struct ktermios *k)
170{
171 return copy_to_user(u, k, sizeof(struct termios)) ? -EFAULT : 0;
172}
129 173
130#endif /* defined(__KERNEL__) */ 174#endif /* defined(__KERNEL__) */
131 175
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
index 88badb423010..964ef7ede268 100644
--- a/arch/mips/include/asm/txx9/tx4939.h
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -541,5 +541,6 @@ void tx4939_irq_init(void);
541int tx4939_irq(void); 541int tx4939_irq(void);
542void tx4939_mtd_init(int ch); 542void tx4939_mtd_init(int ch);
543void tx4939_ata_init(void); 543void tx4939_ata_init(void);
544void tx4939_rtc_init(void);
544 545
545#endif /* __ASM_TXX9_TX4939_H */ 546#endif /* __ASM_TXX9_TX4939_H */
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index fb6f73148df2..8882e5766f27 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -458,7 +458,11 @@ NESTED(nmi_handler, PT_SIZE, sp)
458 BUILD_HANDLER fpe fpe fpe silent /* #15 */ 458 BUILD_HANDLER fpe fpe fpe silent /* #15 */
459 BUILD_HANDLER mdmx mdmx sti silent /* #22 */ 459 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
460#ifdef CONFIG_HARDWARE_WATCHPOINTS 460#ifdef CONFIG_HARDWARE_WATCHPOINTS
461 BUILD_HANDLER watch watch sti silent /* #23 */ 461 /*
462 * For watch, interrupts will be enabled after the watch
463 * registers are read.
464 */
465 BUILD_HANDLER watch watch cli silent /* #23 */
462#else 466#else
463 BUILD_HANDLER watch watch sti verbose /* #23 */ 467 BUILD_HANDLER watch watch sti verbose /* #23 */
464#endif 468#endif
diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c
index 5e77a3a21f98..42461310b185 100644
--- a/arch/mips/kernel/mips-mt-fpaff.c
+++ b/arch/mips/kernel/mips-mt-fpaff.c
@@ -79,7 +79,8 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
79 79
80 euid = current_euid(); 80 euid = current_euid();
81 retval = -EPERM; 81 retval = -EPERM;
82 if (euid != p->euid && euid != p->uid && !capable(CAP_SYS_NICE)) { 82 if (euid != p->cred->euid && euid != p->cred->uid &&
83 !capable(CAP_SYS_NICE)) {
83 read_unlock(&tasklist_lock); 84 read_unlock(&tasklist_lock);
84 goto out_unlock; 85 goto out_unlock;
85 } 86 }
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index f6083c6bfaa4..b2d7041341b8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -944,6 +944,9 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
944 force_sig(SIGILL, current); 944 force_sig(SIGILL, current);
945} 945}
946 946
947/*
948 * Called with interrupts disabled.
949 */
947asmlinkage void do_watch(struct pt_regs *regs) 950asmlinkage void do_watch(struct pt_regs *regs)
948{ 951{
949 u32 cause; 952 u32 cause;
@@ -963,9 +966,12 @@ asmlinkage void do_watch(struct pt_regs *regs)
963 */ 966 */
964 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 967 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
965 mips_read_watch_registers(); 968 mips_read_watch_registers();
969 local_irq_enable();
966 force_sig(SIGTRAP, current); 970 force_sig(SIGTRAP, current);
967 } else 971 } else {
968 mips_clear_watch_registers(); 972 mips_clear_watch_registers();
973 local_irq_enable();
974 }
969} 975}
970 976
971asmlinkage void do_mcheck(struct pt_regs *regs) 977asmlinkage void do_mcheck(struct pt_regs *regs)
@@ -1582,7 +1588,11 @@ void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1582static char panic_null_cerr[] __cpuinitdata = 1588static char panic_null_cerr[] __cpuinitdata =
1583 "Trying to set NULL cache error exception handler"; 1589 "Trying to set NULL cache error exception handler";
1584 1590
1585/* Install uncached CPU exception handler */ 1591/*
1592 * Install uncached CPU exception handler.
1593 * This is suitable only for the cache error exception which is the only
1594 * exception handler that is being run uncached.
1595 */
1586void __cpuinit set_uncached_handler(unsigned long offset, void *addr, 1596void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1587 unsigned long size) 1597 unsigned long size)
1588{ 1598{
@@ -1593,7 +1603,7 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1593 unsigned long uncached_ebase = TO_UNCAC(ebase); 1603 unsigned long uncached_ebase = TO_UNCAC(ebase);
1594#endif 1604#endif
1595 if (cpu_has_mips_r2) 1605 if (cpu_has_mips_r2)
1596 ebase += (read_c0_ebase() & 0x3ffff000); 1606 uncached_ebase += (read_c0_ebase() & 0x3ffff000);
1597 1607
1598 if (!addr) 1608 if (!addr)
1599 panic(panic_null_cerr); 1609 panic(panic_null_cerr);
diff --git a/arch/mips/lib/memcpy-inatomic.S b/arch/mips/lib/memcpy-inatomic.S
index 736d0fb56a94..68853a038d3f 100644
--- a/arch/mips/lib/memcpy-inatomic.S
+++ b/arch/mips/lib/memcpy-inatomic.S
@@ -21,7 +21,7 @@
21 * end of memory on some systems. It's also a seriously bad idea on non 21 * end of memory on some systems. It's also a seriously bad idea on non
22 * dma-coherent systems. 22 * dma-coherent systems.
23 */ 23 */
24#if !defined(CONFIG_DMA_COHERENT) || !defined(CONFIG_DMA_IP27) 24#ifdef CONFIG_DMA_NONCOHERENT
25#undef CONFIG_CPU_HAS_PREFETCH 25#undef CONFIG_CPU_HAS_PREFETCH
26#endif 26#endif
27#ifdef CONFIG_MIPS_MALTA 27#ifdef CONFIG_MIPS_MALTA
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index c06cccf60bec..56a1f85a1ce8 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -21,7 +21,7 @@
21 * end of memory on some systems. It's also a seriously bad idea on non 21 * end of memory on some systems. It's also a seriously bad idea on non
22 * dma-coherent systems. 22 * dma-coherent systems.
23 */ 23 */
24#if !defined(CONFIG_DMA_COHERENT) || !defined(CONFIG_DMA_IP27) 24#ifdef CONFIG_DMA_NONCOHERENT
25#undef CONFIG_CPU_HAS_PREFETCH 25#undef CONFIG_CPU_HAS_PREFETCH
26#endif 26#endif
27#ifdef CONFIG_MIPS_MALTA 27#ifdef CONFIG_MIPS_MALTA
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 6e99665ae860..c43f4b26a690 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -618,15 +618,35 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
618 if (cpu_has_inclusive_pcaches) { 618 if (cpu_has_inclusive_pcaches) {
619 if (size >= scache_size) 619 if (size >= scache_size)
620 r4k_blast_scache(); 620 r4k_blast_scache();
621 else 621 else {
622 unsigned long lsize = cpu_scache_line_size();
623 unsigned long almask = ~(lsize - 1);
624
625 /*
626 * There is no clearly documented alignment requirement
627 * for the cache instruction on MIPS processors and
628 * some processors, among them the RM5200 and RM7000
629 * QED processors will throw an address error for cache
630 * hit ops with insufficient alignment. Solved by
631 * aligning the address to cache line size.
632 */
633 cache_op(Hit_Writeback_Inv_SD, addr & almask);
634 cache_op(Hit_Writeback_Inv_SD,
635 (addr + size - 1) & almask);
622 blast_inv_scache_range(addr, addr + size); 636 blast_inv_scache_range(addr, addr + size);
637 }
623 return; 638 return;
624 } 639 }
625 640
626 if (cpu_has_safe_index_cacheops && size >= dcache_size) { 641 if (cpu_has_safe_index_cacheops && size >= dcache_size) {
627 r4k_blast_dcache(); 642 r4k_blast_dcache();
628 } else { 643 } else {
644 unsigned long lsize = cpu_dcache_line_size();
645 unsigned long almask = ~(lsize - 1);
646
629 R4600_HIT_CACHEOP_WAR_IMPL; 647 R4600_HIT_CACHEOP_WAR_IMPL;
648 cache_op(Hit_Writeback_Inv_D, addr & almask);
649 cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & almask);
630 blast_inv_dcache_range(addr, addr + size); 650 blast_inv_dcache_range(addr, addr + size);
631 } 651 }
632 652
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index fa636fc6b7b9..55767ad9f00e 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -97,7 +97,6 @@ good_area:
97 goto bad_area; 97 goto bad_area;
98 } 98 }
99 99
100survive:
101 /* 100 /*
102 * If for any reason at all we couldn't handle the fault, 101 * If for any reason at all we couldn't handle the fault,
103 * make sure we exit gracefully rather than endlessly redo 102 * make sure we exit gracefully rather than endlessly redo
@@ -167,21 +166,13 @@ no_context:
167 field, regs->regs[31]); 166 field, regs->regs[31]);
168 die("Oops", regs); 167 die("Oops", regs);
169 168
170/*
171 * We ran out of memory, or some other thing happened to us that made
172 * us unable to handle the page fault gracefully.
173 */
174out_of_memory: 169out_of_memory:
175 up_read(&mm->mmap_sem); 170 /*
176 if (is_global_init(tsk)) { 171 * We ran out of memory, call the OOM killer, and return the userspace
177 yield(); 172 * (which will retry the fault, or kill us if we got oom-killed).
178 down_read(&mm->mmap_sem); 173 */
179 goto survive; 174 pagefault_out_of_memory();
180 } 175 return;
181 printk("VM: killing process %s\n", tsk->comm);
182 if (user_mode(regs))
183 do_group_exit(SIGKILL);
184 goto no_context;
185 176
186do_sigbus: 177do_sigbus:
187 up_read(&mm->mmap_sem); 178 up_read(&mm->mmap_sem);
diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
index 1c2821e2f494..71f7d27b0d4c 100644
--- a/arch/mips/pci/pci-rc32434.c
+++ b/arch/mips/pci/pci-rc32434.c
@@ -205,6 +205,8 @@ static int __init rc32434_pcibridge_init(void)
205 205
206static int __init rc32434_pci_init(void) 206static int __init rc32434_pci_init(void)
207{ 207{
208 void __iomem *io_map_base;
209
208 pr_info("PCI: Initializing PCI\n"); 210 pr_info("PCI: Initializing PCI\n");
209 211
210 ioport_resource.start = rc32434_res_pci_io1.start; 212 ioport_resource.start = rc32434_res_pci_io1.start;
@@ -212,6 +214,15 @@ static int __init rc32434_pci_init(void)
212 214
213 rc32434_pcibridge_init(); 215 rc32434_pcibridge_init();
214 216
217 io_map_base = ioremap(rc32434_res_pci_io1.start,
218 rc32434_res_pci_io1.end - rc32434_res_pci_io1.start + 1);
219
220 if (!io_map_base)
221 return -ENOMEM;
222
223 rc32434_controller.io_map_base =
224 (unsigned long)io_map_base - rc32434_res_pci_io1.start;
225
215 register_pci_controller(&rc32434_controller); 226 register_pci_controller(&rc32434_controller);
216 rc32434_sync(); 227 rc32434_sync();
217 228
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index c1c29181bd46..4a5f05b662ae 100644
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -24,6 +24,7 @@
24#include <linux/mtd/partitions.h> 24#include <linux/mtd/partitions.h>
25#include <linux/gpio_keys.h> 25#include <linux/gpio_keys.h>
26#include <linux/input.h> 26#include <linux/input.h>
27#include <linux/serial_8250.h>
27 28
28#include <asm/bootinfo.h> 29#include <asm/bootinfo.h>
29 30
@@ -39,6 +40,29 @@
39#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET) 40#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
40#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET) 41#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
41 42
43extern unsigned int idt_cpu_freq;
44
45static struct mpmc_device dev3;
46
47void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
48{
49 unsigned long flags;
50
51 spin_lock_irqsave(&dev3.lock, flags);
52
53 dev3.state = (dev3.state | or_mask) & ~nand_mask;
54 writeb(dev3.state, dev3.base);
55
56 spin_unlock_irqrestore(&dev3.lock, flags);
57}
58EXPORT_SYMBOL(set_latch_u5);
59
60unsigned char get_latch_u5(void)
61{
62 return dev3.state;
63}
64EXPORT_SYMBOL(get_latch_u5);
65
42static struct resource korina_dev0_res[] = { 66static struct resource korina_dev0_res[] = {
43 { 67 {
44 .name = "korina_regs", 68 .name = "korina_regs",
@@ -86,7 +110,7 @@ static struct korina_device korina_dev0_data = {
86static struct platform_device korina_dev0 = { 110static struct platform_device korina_dev0 = {
87 .id = -1, 111 .id = -1,
88 .name = "korina", 112 .name = "korina",
89 .dev.platform_data = &korina_dev0_data, 113 .dev.driver_data = &korina_dev0_data,
90 .resource = korina_dev0_res, 114 .resource = korina_dev0_res,
91 .num_resources = ARRAY_SIZE(korina_dev0_res), 115 .num_resources = ARRAY_SIZE(korina_dev0_res),
92}; 116};
@@ -214,12 +238,32 @@ static struct platform_device rb532_wdt = {
214 .num_resources = ARRAY_SIZE(rb532_wdt_res), 238 .num_resources = ARRAY_SIZE(rb532_wdt_res),
215}; 239};
216 240
241static struct plat_serial8250_port rb532_uart_res[] = {
242 {
243 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
244 .irq = UART0_IRQ,
245 .regshift = 2,
246 .iotype = UPIO_MEM,
247 .flags = UPF_BOOT_AUTOCONF,
248 },
249 {
250 .flags = 0,
251 }
252};
253
254static struct platform_device rb532_uart = {
255 .name = "serial8250",
256 .id = PLAT8250_DEV_PLATFORM,
257 .dev.platform_data = &rb532_uart_res,
258};
259
217static struct platform_device *rb532_devs[] = { 260static struct platform_device *rb532_devs[] = {
218 &korina_dev0, 261 &korina_dev0,
219 &nand_slot0, 262 &nand_slot0,
220 &cf_slot0, 263 &cf_slot0,
221 &rb532_led, 264 &rb532_led,
222 &rb532_button, 265 &rb532_button,
266 &rb532_uart,
223 &rb532_wdt 267 &rb532_wdt
224}; 268};
225 269
@@ -291,9 +335,20 @@ static int __init plat_setup_devices(void)
291 nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE); 335 nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
292 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; 336 nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
293 337
338 /* Read and map device controller 3 */
339 dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1);
340
341 if (!dev3.base) {
342 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
343 return -ENXIO;
344 }
345
294 /* Initialise the NAND device */ 346 /* Initialise the NAND device */
295 rb532_nand_setup(); 347 rb532_nand_setup();
296 348
349 /* set the uart clock to the current cpu frequency */
350 rb532_uart_res[0].uartclk = idt_cpu_freq;
351
297 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs)); 352 return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
298} 353}
299 354
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index 0e84c8ab6a39..37de05d595e7 100644
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -41,8 +41,6 @@ struct rb532_gpio_chip {
41 void __iomem *regbase; 41 void __iomem *regbase;
42}; 42};
43 43
44struct mpmc_device dev3;
45
46static struct resource rb532_gpio_reg0_res[] = { 44static struct resource rb532_gpio_reg0_res[] = {
47 { 45 {
48 .name = "gpio_reg0", 46 .name = "gpio_reg0",
@@ -52,61 +50,6 @@ static struct resource rb532_gpio_reg0_res[] = {
52 } 50 }
53}; 51};
54 52
55static struct resource rb532_dev3_ctl_res[] = {
56 {
57 .name = "dev3_ctl",
58 .start = REGBASE + DEV3BASE,
59 .end = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
60 .flags = IORESOURCE_MEM,
61 }
62};
63
64void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
65{
66 unsigned long flags;
67 unsigned data;
68 unsigned i = 0;
69
70 spin_lock_irqsave(&dev3.lock, flags);
71
72 data = readl(IDT434_REG_BASE + reg_offs);
73 for (i = 0; i != len; ++i) {
74 if (val & (1 << i))
75 data |= (1 << (i + bit));
76 else
77 data &= ~(1 << (i + bit));
78 }
79 writel(data, (IDT434_REG_BASE + reg_offs));
80
81 spin_unlock_irqrestore(&dev3.lock, flags);
82}
83EXPORT_SYMBOL(set_434_reg);
84
85unsigned get_434_reg(unsigned reg_offs)
86{
87 return readl(IDT434_REG_BASE + reg_offs);
88}
89EXPORT_SYMBOL(get_434_reg);
90
91void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
92{
93 unsigned long flags;
94
95 spin_lock_irqsave(&dev3.lock, flags);
96
97 dev3.state = (dev3.state | or_mask) & ~nand_mask;
98 writel(dev3.state, &dev3.base);
99
100 spin_unlock_irqrestore(&dev3.lock, flags);
101}
102EXPORT_SYMBOL(set_latch_u5);
103
104unsigned char get_latch_u5(void)
105{
106 return dev3.state;
107}
108EXPORT_SYMBOL(get_latch_u5);
109
110/* rb532_set_bit - sanely set a bit 53/* rb532_set_bit - sanely set a bit
111 * 54 *
112 * bitval: new value for the bit 55 * bitval: new value for the bit
@@ -119,13 +62,11 @@ static inline void rb532_set_bit(unsigned bitval,
119 unsigned long flags; 62 unsigned long flags;
120 u32 val; 63 u32 val;
121 64
122 bitval = !!bitval; /* map parameter to {0,1} */
123
124 local_irq_save(flags); 65 local_irq_save(flags);
125 66
126 val = readl(ioaddr); 67 val = readl(ioaddr);
127 val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */ 68 val &= ~(!bitval << offset); /* unset bit if bitval == 0 */
128 val |= ( bitval << offset ); /* set bit if bitval == 1 */ 69 val |= (!!bitval << offset); /* set bit if bitval == 1 */
129 writel(val, ioaddr); 70 writel(val, ioaddr);
130 71
131 local_irq_restore(flags); 72 local_irq_restore(flags);
@@ -171,8 +112,8 @@ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
171 112
172 gpch = container_of(chip, struct rb532_gpio_chip, chip); 113 gpch = container_of(chip, struct rb532_gpio_chip, chip);
173 114
174 if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) 115 /* disable alternate function in case it's set */
175 return 1; /* alternate function, GPIOCFG is ignored */ 116 rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC);
176 117
177 rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); 118 rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
178 return 0; 119 return 0;
@@ -188,8 +129,8 @@ static int rb532_gpio_direction_output(struct gpio_chip *chip,
188 129
189 gpch = container_of(chip, struct rb532_gpio_chip, chip); 130 gpch = container_of(chip, struct rb532_gpio_chip, chip);
190 131
191 if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) 132 /* disable alternate function in case it's set */
192 return 1; /* alternate function, GPIOCFG is ignored */ 133 rb532_set_bit(0, offset, gpch->regbase + GPIOFUNC);
193 134
194 /* set the initial output value */ 135 /* set the initial output value */
195 rb532_set_bit(value, offset, gpch->regbase + GPIOD); 136 rb532_set_bit(value, offset, gpch->regbase + GPIOD);
@@ -233,10 +174,11 @@ EXPORT_SYMBOL(rb532_gpio_set_istat);
233/* 174/*
234 * Configure GPIO alternate function 175 * Configure GPIO alternate function
235 */ 176 */
236static void rb532_gpio_set_func(int bit, unsigned gpio) 177void rb532_gpio_set_func(unsigned gpio)
237{ 178{
238 rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC); 179 rb532_set_bit(1, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
239} 180}
181EXPORT_SYMBOL(rb532_gpio_set_func);
240 182
241int __init rb532_gpio_init(void) 183int __init rb532_gpio_init(void)
242{ 184{
@@ -253,20 +195,6 @@ int __init rb532_gpio_init(void)
253 /* Register our GPIO chip */ 195 /* Register our GPIO chip */
254 gpiochip_add(&rb532_gpio_chip->chip); 196 gpiochip_add(&rb532_gpio_chip->chip);
255 197
256 r = rb532_dev3_ctl_res;
257 dev3.base = ioremap_nocache(r->start, r->end - r->start);
258
259 if (!dev3.base) {
260 printk(KERN_ERR "rb532: cannot remap device controller 3\n");
261 return -ENXIO;
262 }
263
264 /* configure CF_GPIO_NUM as CFRDY IRQ source */
265 rb532_gpio_set_func(0, CF_GPIO_NUM);
266 rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM);
267 rb532_gpio_set_ilevel(1, CF_GPIO_NUM);
268 rb532_gpio_set_istat(0, CF_GPIO_NUM);
269
270 return 0; 198 return 0;
271} 199}
272arch_initcall(rb532_gpio_init); 200arch_initcall(rb532_gpio_init);
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index 549b46d2fcee..53eeb5e7bc5b 100644
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -46,6 +46,7 @@
46#include <asm/system.h> 46#include <asm/system.h>
47 47
48#include <asm/mach-rc32434/irq.h> 48#include <asm/mach-rc32434/irq.h>
49#include <asm/mach-rc32434/gpio.h>
49 50
50struct intr_group { 51struct intr_group {
51 u32 mask; /* mask of valid bits in pending/mask registers */ 52 u32 mask; /* mask of valid bits in pending/mask registers */
@@ -150,6 +151,9 @@ static void rb532_disable_irq(unsigned int irq_nr)
150 mask |= intr_bit; 151 mask |= intr_bit;
151 WRITE_MASK(addr, mask); 152 WRITE_MASK(addr, mask);
152 153
154 if (group == GPIO_MAPPED_IRQ_GROUP)
155 rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
156
153 /* 157 /*
154 * if there are no more interrupts enabled in this 158 * if there are no more interrupts enabled in this
155 * group, disable corresponding IP 159 * group, disable corresponding IP
@@ -165,12 +169,35 @@ static void rb532_mask_and_ack_irq(unsigned int irq_nr)
165 ack_local_irq(group_to_ip(irq_to_group(irq_nr))); 169 ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
166} 170}
167 171
172static int rb532_set_type(unsigned int irq_nr, unsigned type)
173{
174 int gpio = irq_nr - GPIO_MAPPED_IRQ_BASE;
175 int group = irq_to_group(irq_nr);
176
177 if (group != GPIO_MAPPED_IRQ_GROUP)
178 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
179
180 switch (type) {
181 case IRQ_TYPE_LEVEL_HIGH:
182 rb532_gpio_set_ilevel(1, gpio);
183 break;
184 case IRQ_TYPE_LEVEL_LOW:
185 rb532_gpio_set_ilevel(0, gpio);
186 break;
187 default:
188 return -EINVAL;
189 }
190
191 return 0;
192}
193
168static struct irq_chip rc32434_irq_type = { 194static struct irq_chip rc32434_irq_type = {
169 .name = "RB532", 195 .name = "RB532",
170 .ack = rb532_disable_irq, 196 .ack = rb532_disable_irq,
171 .mask = rb532_disable_irq, 197 .mask = rb532_disable_irq,
172 .mask_ack = rb532_mask_and_ack_irq, 198 .mask_ack = rb532_mask_and_ack_irq,
173 .unmask = rb532_enable_irq, 199 .unmask = rb532_enable_irq,
200 .set_type = rb532_set_type,
174}; 201};
175 202
176void __init arch_init_irq(void) 203void __init arch_init_irq(void)
diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c
index 3e0d7ec3a579..00ed19f0bdb5 100644
--- a/arch/mips/rb532/serial.c
+++ b/arch/mips/rb532/serial.c
@@ -36,7 +36,7 @@
36extern unsigned int idt_cpu_freq; 36extern unsigned int idt_cpu_freq;
37 37
38static struct uart_port rb532_uart = { 38static struct uart_port rb532_uart = {
39 .type = PORT_16550A, 39 .flags = UPF_BOOT_AUTOCONF,
40 .line = 0, 40 .line = 0,
41 .irq = UART0_IRQ, 41 .irq = UART0_IRQ,
42 .iotype = UPIO_MEM, 42 .iotype = UPIO_MEM,
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
index 6c0049a5bbc1..55440967b3a8 100644
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -435,6 +435,28 @@ void __init tx4939_ata_init(void)
435 platform_device_register(&ata1_dev); 435 platform_device_register(&ata1_dev);
436} 436}
437 437
438void __init tx4939_rtc_init(void)
439{
440 static struct resource res[] = {
441 {
442 .start = TX4939_RTC_REG & 0xfffffffffULL,
443 .end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1,
444 .flags = IORESOURCE_MEM,
445 }, {
446 .start = TXX9_IRQ_BASE + TX4939_IR_RTC,
447 .flags = IORESOURCE_IRQ,
448 },
449 };
450 static struct platform_device rtc_dev = {
451 .name = "tx4939rtc",
452 .id = -1,
453 .num_resources = ARRAY_SIZE(res),
454 .resource = res,
455 };
456
457 platform_device_register(&rtc_dev);
458}
459
438static void __init tx4939_stop_unused_modules(void) 460static void __init tx4939_stop_unused_modules(void)
439{ 461{
440 __u64 pcfg, rst = 0, ckd = 0; 462 __u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 98fbd9391bf8..656603b85b71 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -336,6 +336,7 @@ static void __init rbtx4939_device_init(void)
336 rbtx4939_led_setup(); 336 rbtx4939_led_setup();
337 tx4939_wdt_init(); 337 tx4939_wdt_init();
338 tx4939_ata_init(); 338 tx4939_ata_init();
339 tx4939_rtc_init();
339} 340}
340 341
341static void __init rbtx4939_setup(void) 342static void __init rbtx4939_setup(void)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 04:03:33 -0500