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-rw-r--r--arch/mips/Kconfig25
-rw-r--r--arch/mips/Makefile11
-rw-r--r--arch/mips/alchemy/common/time.c2
-rw-r--r--arch/mips/cavium-octeon/csrc-octeon.c2
-rw-r--r--arch/mips/include/asm/bitops.h4
-rw-r--r--arch/mips/include/asm/checksum.h4
-rw-r--r--arch/mips/include/asm/compat.h1
-rw-r--r--arch/mips/include/asm/cpu-features.h9
-rw-r--r--arch/mips/include/asm/cpu-info.h4
-rw-r--r--arch/mips/include/asm/delay.h92
-rw-r--r--arch/mips/include/asm/div64.h142
-rw-r--r--arch/mips/include/asm/dma-mapping.h9
-rw-r--r--arch/mips/include/asm/fixmap.h3
-rw-r--r--arch/mips/include/asm/hazards.h5
-rw-r--r--arch/mips/include/asm/highmem.h6
-rw-r--r--arch/mips/include/asm/ioctl.h4
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h6
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_ide.h17
-rw-r--r--arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h59
-rw-r--r--arch/mips/include/asm/mipsregs.h38
-rw-r--r--arch/mips/include/asm/page.h3
-rw-r--r--arch/mips/include/asm/pgtable-64.h6
-rw-r--r--arch/mips/include/asm/sn/addrs.h4
-rw-r--r--arch/mips/include/asm/sn/nmi.h4
-rw-r--r--arch/mips/include/asm/thread_info.h3
-rw-r--r--arch/mips/include/asm/time.h6
-rw-r--r--arch/mips/include/asm/uaccess.h68
-rw-r--r--arch/mips/kernel/cevt-smtc.c2
-rw-r--r--arch/mips/kernel/proc.c2
-rw-r--r--arch/mips/kernel/scall64-n32.S4
-rw-r--r--arch/mips/kernel/scall64-o32.S4
-rw-r--r--arch/mips/kernel/unaligned.c6
-rw-r--r--arch/mips/lib/Makefile4
-rw-r--r--arch/mips/lib/delay.c56
-rw-r--r--arch/mips/lib/dump_tlb.c9
-rw-r--r--arch/mips/mm/c-r4k.c2
-rw-r--r--arch/mips/mm/dma-default.c19
-rw-r--r--arch/mips/mm/highmem.c25
-rw-r--r--arch/mips/mm/init.c26
-rw-r--r--arch/mips/mm/sc-rm7k.c4
-rw-r--r--arch/mips/mm/tlb-r3k.c6
-rw-r--r--arch/mips/mm/tlb-r4k.c6
-rw-r--r--arch/mips/mm/tlb-r8k.c3
-rw-r--r--arch/mips/pmc-sierra/Kconfig12
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_prom.c60
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_setup.c8
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_time.c7
-rw-r--r--arch/mips/sgi-ip22/ip22-reset.c2
-rw-r--r--arch/mips/sgi-ip32/ip32-berr.c2
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c4
-rw-r--r--arch/mips/sgi-ip32/ip32-reset.c9
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c7
-rw-r--r--arch/mips/sibyte/cfe/setup.c8
-rw-r--r--arch/mips/sibyte/sb1250/irq.c7
-rw-r--r--arch/mips/txx9/generic/setup_tx4927.c2
-rw-r--r--arch/mips/txx9/generic/setup_tx4938.c2
-rw-r--r--arch/mips/txx9/generic/setup_tx4939.c2
-rw-r--r--arch/mips/txx9/rbtx4939/setup.c2
58 files changed, 399 insertions, 450 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 998e5db8cc0f..25f3b0a11ca8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -72,6 +72,7 @@ config MIPS_COBALT
72 select IRQ_CPU 72 select IRQ_CPU
73 select IRQ_GT641XX 73 select IRQ_GT641XX
74 select PCI_GT64XXX_PCI0 74 select PCI_GT64XXX_PCI0
75 select PCI
75 select SYS_HAS_CPU_NEVADA 76 select SYS_HAS_CPU_NEVADA
76 select SYS_HAS_EARLY_PRINTK 77 select SYS_HAS_EARLY_PRINTK
77 select SYS_SUPPORTS_32BIT_KERNEL 78 select SYS_SUPPORTS_32BIT_KERNEL
@@ -593,7 +594,7 @@ config WR_PPMC
593 board, which is based on GT64120 bridge chip. 594 board, which is based on GT64120 bridge chip.
594 595
595config CAVIUM_OCTEON_SIMULATOR 596config CAVIUM_OCTEON_SIMULATOR
596 bool "Support for the Cavium Networks Octeon Simulator" 597 bool "Cavium Networks Octeon Simulator"
597 select CEVT_R4K 598 select CEVT_R4K
598 select 64BIT_PHYS_ADDR 599 select 64BIT_PHYS_ADDR
599 select DMA_COHERENT 600 select DMA_COHERENT
@@ -607,7 +608,7 @@ config CAVIUM_OCTEON_SIMULATOR
607 hardware. 608 hardware.
608 609
609config CAVIUM_OCTEON_REFERENCE_BOARD 610config CAVIUM_OCTEON_REFERENCE_BOARD
610 bool "Support for the Cavium Networks Octeon reference board" 611 bool "Cavium Networks Octeon reference board"
611 select CEVT_R4K 612 select CEVT_R4K
612 select 64BIT_PHYS_ADDR 613 select 64BIT_PHYS_ADDR
613 select DMA_COHERENT 614 select DMA_COHERENT
@@ -1411,13 +1412,12 @@ config PAGE_SIZE_4KB
1411 1412
1412config PAGE_SIZE_8KB 1413config PAGE_SIZE_8KB
1413 bool "8kB" 1414 bool "8kB"
1414 depends on EXPERIMENTAL && CPU_R8000 1415 depends on (EXPERIMENTAL && CPU_R8000) || CPU_CAVIUM_OCTEON
1415 help 1416 help
1416 Using 8kB page size will result in higher performance kernel at 1417 Using 8kB page size will result in higher performance kernel at
1417 the price of higher memory consumption. This option is available 1418 the price of higher memory consumption. This option is available
1418 only on the R8000 processor. Not that at the time of this writing 1419 only on R8000 and cnMIPS processors. Note that you will need a
1419 this option is still high experimental; there are also issues with 1420 suitable Linux distribution to support this.
1420 compatibility of user applications.
1421 1421
1422config PAGE_SIZE_16KB 1422config PAGE_SIZE_16KB
1423 bool "16kB" 1423 bool "16kB"
@@ -1428,6 +1428,15 @@ config PAGE_SIZE_16KB
1428 all non-R3000 family processors. Note that you will need a suitable 1428 all non-R3000 family processors. Note that you will need a suitable
1429 Linux distribution to support this. 1429 Linux distribution to support this.
1430 1430
1431config PAGE_SIZE_32KB
1432 bool "32kB"
1433 depends on CPU_CAVIUM_OCTEON
1434 help
1435 Using 32kB page size will result in higher performance kernel at
1436 the price of higher memory consumption. This option is available
1437 only on cnMIPS cores. Note that you will need a suitable Linux
1438 distribution to support this.
1439
1431config PAGE_SIZE_64KB 1440config PAGE_SIZE_64KB
1432 bool "64kB" 1441 bool "64kB"
1433 depends on EXPERIMENTAL && !CPU_R3000 && !CPU_TX39XX 1442 depends on EXPERIMENTAL && !CPU_R3000 && !CPU_TX39XX
@@ -1958,10 +1967,6 @@ config SECCOMP
1958 1967
1959endmenu 1968endmenu
1960 1969
1961config RWSEM_GENERIC_SPINLOCK
1962 bool
1963 default y
1964
1965config LOCKDEP_SUPPORT 1970config LOCKDEP_SUPPORT
1966 bool 1971 bool
1967 default y 1972 default y
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 8d544c7c9fe9..c4cae9e6b802 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -14,8 +14,6 @@
14 14
15KBUILD_DEFCONFIG := ip22_defconfig 15KBUILD_DEFCONFIG := ip22_defconfig
16 16
17cflags-y := -ffunction-sections
18
19# 17#
20# Select the object file format to substitute into the linker script. 18# Select the object file format to substitute into the linker script.
21# 19#
@@ -50,6 +48,9 @@ ifneq ($(SUBARCH),$(ARCH))
50 endif 48 endif
51endif 49endif
52 50
51cflags-y := -ffunction-sections
52cflags-y += $(call cc-option, -mno-check-zero-division)
53
53ifdef CONFIG_32BIT 54ifdef CONFIG_32BIT
54ld-emul = $(32bit-emul) 55ld-emul = $(32bit-emul)
55vmlinux-32 = vmlinux 56vmlinux-32 = vmlinux
@@ -472,12 +473,12 @@ endif
472# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys 473# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys
473# 474#
474ifdef CONFIG_SGI_IP28 475ifdef CONFIG_SGI_IP28
475 ifeq ($(call cc-option-yn,-mr10k-cache-barrier=1), n) 476 ifeq ($(call cc-option-yn,-mr10k-cache-barrier=store), n)
476 $(error gcc doesn't support needed option -mr10k-cache-barrier=1) 477 $(error gcc doesn't support needed option -mr10k-cache-barrier=store)
477 endif 478 endif
478endif 479endif
479core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ 480core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/
480cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -I$(srctree)/arch/mips/include/asm/mach-ip28 481cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=store -I$(srctree)/arch/mips/include/asm/mach-ip28
481load-$(CONFIG_SGI_IP28) += 0xa800000020004000 482load-$(CONFIG_SGI_IP28) += 0xa800000020004000
482 483
483# 484#
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index f58d4ffb8945..33fbae79af5e 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -44,7 +44,7 @@
44 44
45extern int allow_au1k_wait; /* default off for CP0 Counter */ 45extern int allow_au1k_wait; /* default off for CP0 Counter */
46 46
47static cycle_t au1x_counter1_read(void) 47static cycle_t au1x_counter1_read(struct clocksource *cs)
48{ 48{
49 return au_readl(SYS_RTCREAD); 49 return au_readl(SYS_RTCREAD);
50} 50}
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index 70fd92c31657..96110f217dcd 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -38,7 +38,7 @@ void octeon_init_cvmcount(void)
38 local_irq_restore(flags); 38 local_irq_restore(flags);
39} 39}
40 40
41static cycle_t octeon_cvmcount_read(void) 41static cycle_t octeon_cvmcount_read(struct clocksource *cs)
42{ 42{
43 return read_c0_cvmcount(); 43 return read_c0_cvmcount();
44} 44}
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index bac4a960b24c..b1e9e97a9c78 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -567,7 +567,7 @@ static inline unsigned long __fls(unsigned long word)
567 int num; 567 int num;
568 568
569 if (BITS_PER_LONG == 32 && 569 if (BITS_PER_LONG == 32 &&
570 __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { 570 __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
571 __asm__( 571 __asm__(
572 " .set push \n" 572 " .set push \n"
573 " .set mips32 \n" 573 " .set mips32 \n"
@@ -644,7 +644,7 @@ static inline int fls(int x)
644{ 644{
645 int r; 645 int r;
646 646
647 if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) { 647 if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
648 __asm__("clz %0, %1" : "=r" (x) : "r" (x)); 648 __asm__("clz %0, %1" : "=r" (x) : "r" (x));
649 649
650 return 32 - x; 650 return 32 - x;
diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h
index 290485ac5407..f2f7c6c264da 100644
--- a/arch/mips/include/asm/checksum.h
+++ b/arch/mips/include/asm/checksum.h
@@ -40,7 +40,7 @@ static inline
40__wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len, 40__wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len,
41 __wsum sum, int *err_ptr) 41 __wsum sum, int *err_ptr)
42{ 42{
43 might_sleep(); 43 might_fault();
44 return __csum_partial_copy_user((__force void *)src, dst, 44 return __csum_partial_copy_user((__force void *)src, dst,
45 len, sum, err_ptr); 45 len, sum, err_ptr);
46} 46}
@@ -53,7 +53,7 @@ static inline
53__wsum csum_and_copy_to_user(const void *src, void __user *dst, int len, 53__wsum csum_and_copy_to_user(const void *src, void __user *dst, int len,
54 __wsum sum, int *err_ptr) 54 __wsum sum, int *err_ptr)
55{ 55{
56 might_sleep(); 56 might_fault();
57 if (access_ok(VERIFY_WRITE, dst, len)) 57 if (access_ok(VERIFY_WRITE, dst, len))
58 return __csum_partial_copy_user(src, (__force void *)dst, 58 return __csum_partial_copy_user(src, (__force void *)dst,
59 len, sum, err_ptr); 59 len, sum, err_ptr);
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index 6c5b40905dd6..f58aed354bfd 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -3,7 +3,6 @@
3/* 3/*
4 * Architecture specific compatibility types 4 * Architecture specific compatibility types
5 */ 5 */
6#include <linux/seccomp.h>
7#include <linux/thread_info.h> 6#include <linux/thread_info.h>
8#include <linux/types.h> 7#include <linux/types.h>
9#include <asm/page.h> 8#include <asm/page.h>
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index a0d14f85b781..c0047f861337 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -147,6 +147,15 @@
147#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 147#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
148 cpu_has_mips64r1 | cpu_has_mips64r2) 148 cpu_has_mips64r1 | cpu_has_mips64r2)
149 149
150/*
151 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
152 * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
153 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
154 */
155# ifndef cpu_has_clo_clz
156# define cpu_has_clo_clz cpu_has_mips_r
157# endif
158
150#ifndef cpu_has_dsp 159#ifndef cpu_has_dsp
151#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) 160#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
152#endif 161#endif
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 744cd8fb107f..126044308dec 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -39,8 +39,8 @@ struct cache_desc {
39#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */ 39#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
40 40
41struct cpuinfo_mips { 41struct cpuinfo_mips {
42 unsigned long udelay_val; 42 unsigned int udelay_val;
43 unsigned long asid_cache; 43 unsigned int asid_cache;
44 44
45 /* 45 /*
46 * Capability and feature descriptor structure for MIPS CPU 46 * Capability and feature descriptor structure for MIPS CPU
diff --git a/arch/mips/include/asm/delay.h b/arch/mips/include/asm/delay.h
index b0bccd2c4ed5..a07e51b2be13 100644
--- a/arch/mips/include/asm/delay.h
+++ b/arch/mips/include/asm/delay.h
@@ -11,94 +11,12 @@
11#ifndef _ASM_DELAY_H 11#ifndef _ASM_DELAY_H
12#define _ASM_DELAY_H 12#define _ASM_DELAY_H
13 13
14#include <linux/param.h> 14extern void __delay(unsigned int loops);
15#include <linux/smp.h> 15extern void __ndelay(unsigned int ns);
16extern void __udelay(unsigned int us);
16 17
17#include <asm/compiler.h> 18#define ndelay(ns) __udelay(ns)
18#include <asm/war.h> 19#define udelay(us) __udelay(us)
19
20static inline void __delay(unsigned long loops)
21{
22 if (sizeof(long) == 4)
23 __asm__ __volatile__ (
24 " .set noreorder \n"
25 " .align 3 \n"
26 "1: bnez %0, 1b \n"
27 " subu %0, 1 \n"
28 " .set reorder \n"
29 : "=r" (loops)
30 : "0" (loops));
31 else if (sizeof(long) == 8 && !DADDI_WAR)
32 __asm__ __volatile__ (
33 " .set noreorder \n"
34 " .align 3 \n"
35 "1: bnez %0, 1b \n"
36 " dsubu %0, 1 \n"
37 " .set reorder \n"
38 : "=r" (loops)
39 : "0" (loops));
40 else if (sizeof(long) == 8 && DADDI_WAR)
41 __asm__ __volatile__ (
42 " .set noreorder \n"
43 " .align 3 \n"
44 "1: bnez %0, 1b \n"
45 " dsubu %0, %2 \n"
46 " .set reorder \n"
47 : "=r" (loops)
48 : "0" (loops), "r" (1));
49}
50
51
52/*
53 * Division by multiplication: you don't have to worry about
54 * loss of precision.
55 *
56 * Use only for very small delays ( < 1 msec). Should probably use a
57 * lookup table, really, as the multiplications take much too long with
58 * short delays. This is a "reasonable" implementation, though (and the
59 * first constant multiplications gets optimized away if the delay is
60 * a constant)
61 */
62
63static inline void __udelay(unsigned long usecs, unsigned long lpj)
64{
65 unsigned long hi, lo;
66
67 /*
68 * The rates of 128 is rounded wrongly by the catchall case
69 * for 64-bit. Excessive precission? Probably ...
70 */
71#if defined(CONFIG_64BIT) && (HZ == 128)
72 usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */
73#elif defined(CONFIG_64BIT)
74 usecs *= (0x8000000000000000UL / (500000 / HZ));
75#else /* 32-bit junk follows here */
76 usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) +
77 0x80000000ULL) >> 32);
78#endif
79
80 if (sizeof(long) == 4)
81 __asm__("multu\t%2, %3"
82 : "=h" (usecs), "=l" (lo)
83 : "r" (usecs), "r" (lpj)
84 : GCC_REG_ACCUM);
85 else if (sizeof(long) == 8 && !R4000_WAR)
86 __asm__("dmultu\t%2, %3"
87 : "=h" (usecs), "=l" (lo)
88 : "r" (usecs), "r" (lpj)
89 : GCC_REG_ACCUM);
90 else if (sizeof(long) == 8 && R4000_WAR)
91 __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
92 : "=r" (usecs), "=h" (hi), "=l" (lo)
93 : "r" (usecs), "r" (lpj)
94 : GCC_REG_ACCUM);
95
96 __delay(usecs);
97}
98
99#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val
100
101#define udelay(usecs) __udelay((usecs), __udelay_val)
102 20
103/* make sure "usecs *= ..." in udelay do not overflow. */ 21/* make sure "usecs *= ..." in udelay do not overflow. */
104#if HZ >= 1000 22#if HZ >= 1000
diff --git a/arch/mips/include/asm/div64.h b/arch/mips/include/asm/div64.h
index d1d699105c11..dc5ea5736440 100644
--- a/arch/mips/include/asm/div64.h
+++ b/arch/mips/include/asm/div64.h
@@ -6,105 +6,63 @@
6 * License. See the file "COPYING" in the main directory of this archive 6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details. 7 * for more details.
8 */ 8 */
9#ifndef _ASM_DIV64_H 9#ifndef __ASM_DIV64_H
10#define _ASM_DIV64_H 10#define __ASM_DIV64_H
11 11
12#include <linux/types.h> 12#include <asm-generic/div64.h>
13 13
14#if (_MIPS_SZLONG == 32) 14#if BITS_PER_LONG == 64
15 15
16#include <asm/compiler.h> 16#include <linux/types.h>
17 17
18/* 18/*
19 * No traps on overflows for any of these... 19 * No traps on overflows for any of these...
20 */ 20 */
21 21
22#define do_div64_32(res, high, low, base) ({ \ 22#define __div64_32(n, base) \
23 unsigned long __quot32, __mod32; \ 23({ \
24 unsigned long __cf, __tmp, __tmp2, __i; \ 24 unsigned long __cf, __tmp, __tmp2, __i; \
25 \ 25 unsigned long __quot32, __mod32; \
26 __asm__(".set push\n\t" \ 26 unsigned long __high, __low; \
27 ".set noat\n\t" \ 27 unsigned long long __n; \
28 ".set noreorder\n\t" \ 28 \
29 "move %2, $0\n\t" \ 29 __high = *__n >> 32; \
30 "move %3, $0\n\t" \ 30 __low = __n; \
31 "b 1f\n\t" \ 31 __asm__( \
32 " li %4, 0x21\n" \ 32 " .set push \n" \
33 "0:\n\t" \ 33 " .set noat \n" \
34 "sll $1, %0, 0x1\n\t" \ 34 " .set noreorder \n" \
35 "srl %3, %0, 0x1f\n\t" \ 35 " move %2, $0 \n" \
36 "or %0, $1, %5\n\t" \ 36 " move %3, $0 \n" \
37 "sll %1, %1, 0x1\n\t" \ 37 " b 1f \n" \
38 "sll %2, %2, 0x1\n" \ 38 " li %4, 0x21 \n" \
39 "1:\n\t" \ 39 "0: \n" \
40 "bnez %3, 2f\n\t" \ 40 " sll $1, %0, 0x1 \n" \
41 " sltu %5, %0, %z6\n\t" \ 41 " srl %3, %0, 0x1f \n" \
42 "bnez %5, 3f\n" \ 42 " or %0, $1, %5 \n" \
43 "2:\n\t" \ 43 " sll %1, %1, 0x1 \n" \
44 " addiu %4, %4, -1\n\t" \ 44 " sll %2, %2, 0x1 \n" \
45 "subu %0, %0, %z6\n\t" \ 45 "1: \n" \
46 "addiu %2, %2, 1\n" \ 46 " bnez %3, 2f \n" \
47 "3:\n\t" \ 47 " sltu %5, %0, %z6 \n" \
48 "bnez %4, 0b\n\t" \ 48 " bnez %5, 3f \n" \
49 " srl %5, %1, 0x1f\n\t" \ 49 "2: \n" \
50 ".set pop" \ 50 " addiu %4, %4, -1 \n" \
51 : "=&r" (__mod32), "=&r" (__tmp), \ 51 " subu %0, %0, %z6 \n" \
52 "=&r" (__quot32), "=&r" (__cf), \ 52 " addiu %2, %2, 1 \n" \
53 "=&r" (__i), "=&r" (__tmp2) \ 53 "3: \n" \
54 : "Jr" (base), "0" (high), "1" (low)); \ 54 " bnez %4, 0b\n\t" \
55 \ 55 " srl %5, %1, 0x1f\n\t" \
56 (res) = __quot32; \ 56 " .set pop" \
57 __mod32; }) 57 : "=&r" (__mod32), "=&r" (__tmp), \
58 58 "=&r" (__quot32), "=&r" (__cf), \
59#define do_div(n, base) ({ \ 59 "=&r" (__i), "=&r" (__tmp2) \
60 unsigned long long __quot; \ 60 : "Jr" (base), "0" (__high), "1" (__low)); \
61 unsigned long __mod; \ 61 \
62 unsigned long long __div; \ 62 (__n) = __quot32; \
63 unsigned long __upper, __low, __high, __base; \ 63 __mod32; \
64 \ 64})
65 __div = (n); \
66 __base = (base); \
67 \
68 __high = __div >> 32; \
69 __low = __div; \
70 __upper = __high; \
71 \
72 if (__high) \
73 __asm__("divu $0, %z2, %z3" \
74 : "=h" (__upper), "=l" (__high) \
75 : "Jr" (__high), "Jr" (__base) \
76 : GCC_REG_ACCUM); \
77 \
78 __mod = do_div64_32(__low, __upper, __low, __base); \
79 \
80 __quot = __high; \
81 __quot = __quot << 32 | __low; \
82 (n) = __quot; \
83 __mod; })
84
85#endif /* (_MIPS_SZLONG == 32) */
86
87#if (_MIPS_SZLONG == 64)
88
89/*
90 * Hey, we're already 64-bit, no
91 * need to play games..
92 */
93#define do_div(n, base) ({ \
94 unsigned long __quot; \
95 unsigned int __mod; \
96 unsigned long __div; \
97 unsigned int __base; \
98 \
99 __div = (n); \
100 __base = (base); \
101 \
102 __mod = __div % __base; \
103 __quot = __div / __base; \
104 \
105 (n) = __quot; \
106 __mod; })
107 65
108#endif /* (_MIPS_SZLONG == 64) */ 66#endif /* BITS_PER_LONG == 64 */
109 67
110#endif /* _ASM_DIV64_H */ 68#endif /* __ASM_DIV64_H */
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index c64afb40cd06..d16afddb09a9 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -24,8 +24,13 @@ extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
24 enum dma_data_direction direction); 24 enum dma_data_direction direction);
25extern dma_addr_t dma_map_page(struct device *dev, struct page *page, 25extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
26 unsigned long offset, size_t size, enum dma_data_direction direction); 26 unsigned long offset, size_t size, enum dma_data_direction direction);
27extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address, 27
28 size_t size, enum dma_data_direction direction); 28static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
29 size_t size, enum dma_data_direction direction)
30{
31 dma_unmap_single(dev, dma_address, size, direction);
32}
33
29extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, 34extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
30 int nhwentries, enum dma_data_direction direction); 35 int nhwentries, enum dma_data_direction direction);
31extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, 36extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h
index 9cc8522a394f..0f5caa1307f1 100644
--- a/arch/mips/include/asm/fixmap.h
+++ b/arch/mips/include/asm/fixmap.h
@@ -108,6 +108,9 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr)
108 return __virt_to_fix(vaddr); 108 return __virt_to_fix(vaddr);
109} 109}
110 110
111#define kmap_get_fixmap_pte(vaddr) \
112 pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr))
113
111/* 114/*
112 * Called from pgtable_init() 115 * Called from pgtable_init()
113 */ 116 */
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index a12d971db4f9..0eaf77ffbc4f 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -138,8 +138,9 @@ do { \
138 __instruction_hazard(); \ 138 __instruction_hazard(); \
139} while (0) 139} while (0)
140 140
141#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 141#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
142 defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY) 142 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
143 defined(CONFIG_CPU_R5500)
143 144
144/* 145/*
145 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 146 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h
index 4374ab2adc75..25adfb02923d 100644
--- a/arch/mips/include/asm/highmem.h
+++ b/arch/mips/include/asm/highmem.h
@@ -30,8 +30,6 @@
30/* declarations for highmem.c */ 30/* declarations for highmem.c */
31extern unsigned long highstart_pfn, highend_pfn; 31extern unsigned long highstart_pfn, highend_pfn;
32 32
33extern pte_t *kmap_pte;
34extern pgprot_t kmap_prot;
35extern pte_t *pkmap_page_table; 33extern pte_t *pkmap_page_table;
36 34
37/* 35/*
@@ -62,6 +60,10 @@ extern struct page *__kmap_atomic_to_page(void *ptr);
62 60
63#define flush_cache_kmaps() flush_cache_all() 61#define flush_cache_kmaps() flush_cache_all()
64 62
63extern void kmap_init(void);
64
65#define kmap_prot PAGE_KERNEL
66
65#endif /* __KERNEL__ */ 67#endif /* __KERNEL__ */
66 68
67#endif /* _ASM_HIGHMEM_H */ 69#endif /* _ASM_HIGHMEM_H */
diff --git a/arch/mips/include/asm/ioctl.h b/arch/mips/include/asm/ioctl.h
index 85067e248a83..916163401b2c 100644
--- a/arch/mips/include/asm/ioctl.h
+++ b/arch/mips/include/asm/ioctl.h
@@ -60,12 +60,16 @@
60 ((nr) << _IOC_NRSHIFT) | \ 60 ((nr) << _IOC_NRSHIFT) | \
61 ((size) << _IOC_SIZESHIFT)) 61 ((size) << _IOC_SIZESHIFT))
62 62
63#ifdef __KERNEL__
63/* provoke compile error for invalid uses of size argument */ 64/* provoke compile error for invalid uses of size argument */
64extern unsigned int __invalid_size_argument_for_IOC; 65extern unsigned int __invalid_size_argument_for_IOC;
65#define _IOC_TYPECHECK(t) \ 66#define _IOC_TYPECHECK(t) \
66 ((sizeof(t) == sizeof(t[1]) && \ 67 ((sizeof(t) == sizeof(t[1]) && \
67 sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ 68 sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
68 sizeof(t) : __invalid_size_argument_for_IOC) 69 sizeof(t) : __invalid_size_argument_for_IOC)
70#else
71#define _IOC_TYPECHECK(t) (sizeof(t))
72#endif
69 73
70/* used to create numbers */ 74/* used to create numbers */
71#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0) 75#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 62f91f50b5b5..854e95f1b07c 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -715,7 +715,7 @@ enum soc_au1500_ints {
715#ifdef CONFIG_SOC_AU1100 715#ifdef CONFIG_SOC_AU1100
716enum soc_au1100_ints { 716enum soc_au1100_ints {
717 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8, 717 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
718 AU1100_UART0_INT, 718 AU1100_UART0_INT = AU1100_FIRST_INT,
719 AU1100_UART1_INT, 719 AU1100_UART1_INT,
720 AU1100_SD_INT, 720 AU1100_SD_INT,
721 AU1100_UART3_INT, 721 AU1100_UART3_INT,
@@ -902,8 +902,8 @@ enum soc_au1200_ints {
902 AU1000_RTC_MATCH0_INT, 902 AU1000_RTC_MATCH0_INT,
903 AU1000_RTC_MATCH1_INT, 903 AU1000_RTC_MATCH1_INT,
904 AU1000_RTC_MATCH2_INT, 904 AU1000_RTC_MATCH2_INT,
905 905 AU1200_GPIO_203,
906 AU1200_NAND_INT = AU1200_FIRST_INT + 23, 906 AU1200_NAND_INT,
907 AU1200_GPIO_204, 907 AU1200_GPIO_204,
908 AU1200_GPIO_205, 908 AU1200_GPIO_205,
909 AU1200_GPIO_206, 909 AU1200_GPIO_206,
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
index 60638b8969ba..5656c72de6d3 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
@@ -46,20 +46,6 @@
46#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0 46#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
47#endif 47#endif
48 48
49#ifdef CONFIG_PM
50/*
51 * This will enable the device to be powered up when write() or read()
52 * is called. If this is not defined, the driver will return -EBUSY.
53 */
54#define WAKE_ON_ACCESS 1
55
56typedef struct {
57 spinlock_t lock; /* Used to block on state transitions */
58 au1xxx_power_dev_t *dev; /* Power Managers device structure */
59 unsigned stopped; /* Used to signal device is stopped */
60} pm_state;
61#endif
62
63typedef struct { 49typedef struct {
64 u32 tx_dev_id, rx_dev_id, target_dev_id; 50 u32 tx_dev_id, rx_dev_id, target_dev_id;
65 u32 tx_chan, rx_chan; 51 u32 tx_chan, rx_chan;
@@ -72,9 +58,6 @@ typedef struct {
72#endif 58#endif
73 int irq; 59 int irq;
74 u32 regbase; 60 u32 regbase;
75#ifdef CONFIG_PM
76 pm_state pm;
77#endif
78} _auide_hwif; 61} _auide_hwif;
79 62
80/******************************************************************************/ 63/******************************************************************************/
diff --git a/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h
new file mode 100644
index 000000000000..550a10dc9dba
--- /dev/null
+++ b/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h
@@ -0,0 +1,59 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009 Wu Zhangjin <wuzj@lemote.com>
7 * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca>
8 * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org>
9 *
10 * reference: /proc/cpuinfo,
11 * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy),
12 * arch/mips/kernel/proc.c(show_cpuinfo),
13 * loongson2f user manual.
14 */
15
16#ifndef __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H
17#define __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H
18
19#define cpu_dcache_line_size() 32
20#define cpu_icache_line_size() 32
21#define cpu_scache_line_size() 32
22
23
24#define cpu_has_32fpr 1
25#define cpu_has_3k_cache 0
26#define cpu_has_4k_cache 1
27#define cpu_has_4kex 1
28#define cpu_has_64bits 1
29#define cpu_has_cache_cdex_p 0
30#define cpu_has_cache_cdex_s 0
31#define cpu_has_counter 1
32#define cpu_has_dc_aliases 1
33#define cpu_has_divec 0
34#define cpu_has_dsp 0
35#define cpu_has_ejtag 0
36#define cpu_has_fpu 1
37#define cpu_has_ic_fills_f_dc 0
38#define cpu_has_inclusive_pcaches 1
39#define cpu_has_llsc 1
40#define cpu_has_mcheck 0
41#define cpu_has_mdmx 0
42#define cpu_has_mips16 0
43#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 0
45#define cpu_has_mips3d 0
46#define cpu_has_mips64r1 0
47#define cpu_has_mips64r2 0
48#define cpu_has_mipsmt 0
49#define cpu_has_prefetch 0
50#define cpu_has_smartmips 0
51#define cpu_has_tlb 1
52#define cpu_has_tx39_cache 0
53#define cpu_has_userlocal 0
54#define cpu_has_vce 0
55#define cpu_has_vtag_icache 0
56#define cpu_has_watch 1
57#define cpu_icache_snoops_remote_store 1
58
59#endif /* __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 526f327475ce..32ef8bec5c85 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -184,12 +184,19 @@
184#else 184#else
185 185
186#define PM_4K 0x00000000 186#define PM_4K 0x00000000
187#define PM_8K 0x00002000
187#define PM_16K 0x00006000 188#define PM_16K 0x00006000
189#define PM_32K 0x0000e000
188#define PM_64K 0x0001e000 190#define PM_64K 0x0001e000
191#define PM_128K 0x0003e000
189#define PM_256K 0x0007e000 192#define PM_256K 0x0007e000
193#define PM_512K 0x000fe000
190#define PM_1M 0x001fe000 194#define PM_1M 0x001fe000
195#define PM_2M 0x003fe000
191#define PM_4M 0x007fe000 196#define PM_4M 0x007fe000
197#define PM_8M 0x00ffe000
192#define PM_16M 0x01ffe000 198#define PM_16M 0x01ffe000
199#define PM_32M 0x03ffe000
193#define PM_64M 0x07ffe000 200#define PM_64M 0x07ffe000
194#define PM_256M 0x1fffe000 201#define PM_256M 0x1fffe000
195#define PM_1G 0x7fffe000 202#define PM_1G 0x7fffe000
@@ -201,8 +208,12 @@
201 */ 208 */
202#ifdef CONFIG_PAGE_SIZE_4KB 209#ifdef CONFIG_PAGE_SIZE_4KB
203#define PM_DEFAULT_MASK PM_4K 210#define PM_DEFAULT_MASK PM_4K
211#elif defined(CONFIG_PAGE_SIZE_8KB)
212#define PM_DEFAULT_MASK PM_8K
204#elif defined(CONFIG_PAGE_SIZE_16KB) 213#elif defined(CONFIG_PAGE_SIZE_16KB)
205#define PM_DEFAULT_MASK PM_16K 214#define PM_DEFAULT_MASK PM_16K
215#elif defined(CONFIG_PAGE_SIZE_32KB)
216#define PM_DEFAULT_MASK PM_32K
206#elif defined(CONFIG_PAGE_SIZE_64KB) 217#elif defined(CONFIG_PAGE_SIZE_64KB)
207#define PM_DEFAULT_MASK PM_64K 218#define PM_DEFAULT_MASK PM_64K
208#else 219#else
@@ -717,8 +728,8 @@ do { \
717 ".set\tmips64\n\t" \ 728 ".set\tmips64\n\t" \
718 "dmfc0\t%M0, " #source "\n\t" \ 729 "dmfc0\t%M0, " #source "\n\t" \
719 "dsll\t%L0, %M0, 32\n\t" \ 730 "dsll\t%L0, %M0, 32\n\t" \
720 "dsrl\t%M0, %M0, 32\n\t" \ 731 "dsra\t%M0, %M0, 32\n\t" \
721 "dsrl\t%L0, %L0, 32\n\t" \ 732 "dsra\t%L0, %L0, 32\n\t" \
722 ".set\tmips0" \ 733 ".set\tmips0" \
723 : "=r" (__val)); \ 734 : "=r" (__val)); \
724 else \ 735 else \
@@ -726,8 +737,8 @@ do { \
726 ".set\tmips64\n\t" \ 737 ".set\tmips64\n\t" \
727 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 738 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
728 "dsll\t%L0, %M0, 32\n\t" \ 739 "dsll\t%L0, %M0, 32\n\t" \
729 "dsrl\t%M0, %M0, 32\n\t" \ 740 "dsra\t%M0, %M0, 32\n\t" \
730 "dsrl\t%L0, %L0, 32\n\t" \ 741 "dsra\t%L0, %L0, 32\n\t" \
731 ".set\tmips0" \ 742 ".set\tmips0" \
732 : "=r" (__val)); \ 743 : "=r" (__val)); \
733 local_irq_restore(__flags); \ 744 local_irq_restore(__flags); \
@@ -1484,14 +1495,15 @@ static inline unsigned int \
1484set_c0_##name(unsigned int set) \ 1495set_c0_##name(unsigned int set) \
1485{ \ 1496{ \
1486 unsigned int res; \ 1497 unsigned int res; \
1498 unsigned int new; \
1487 unsigned int omt; \ 1499 unsigned int omt; \
1488 unsigned long flags; \ 1500 unsigned long flags; \
1489 \ 1501 \
1490 local_irq_save(flags); \ 1502 local_irq_save(flags); \
1491 omt = __dmt(); \ 1503 omt = __dmt(); \
1492 res = read_c0_##name(); \ 1504 res = read_c0_##name(); \
1493 res |= set; \ 1505 new = res | set; \
1494 write_c0_##name(res); \ 1506 write_c0_##name(new); \
1495 __emt(omt); \ 1507 __emt(omt); \
1496 local_irq_restore(flags); \ 1508 local_irq_restore(flags); \
1497 \ 1509 \
@@ -1502,14 +1514,15 @@ static inline unsigned int \
1502clear_c0_##name(unsigned int clear) \ 1514clear_c0_##name(unsigned int clear) \
1503{ \ 1515{ \
1504 unsigned int res; \ 1516 unsigned int res; \
1517 unsigned int new; \
1505 unsigned int omt; \ 1518 unsigned int omt; \
1506 unsigned long flags; \ 1519 unsigned long flags; \
1507 \ 1520 \
1508 local_irq_save(flags); \ 1521 local_irq_save(flags); \
1509 omt = __dmt(); \ 1522 omt = __dmt(); \
1510 res = read_c0_##name(); \ 1523 res = read_c0_##name(); \
1511 res &= ~clear; \ 1524 new = res & ~clear; \
1512 write_c0_##name(res); \ 1525 write_c0_##name(new); \
1513 __emt(omt); \ 1526 __emt(omt); \
1514 local_irq_restore(flags); \ 1527 local_irq_restore(flags); \
1515 \ 1528 \
@@ -1517,9 +1530,10 @@ clear_c0_##name(unsigned int clear) \
1517} \ 1530} \
1518 \ 1531 \
1519static inline unsigned int \ 1532static inline unsigned int \
1520change_c0_##name(unsigned int change, unsigned int new) \ 1533change_c0_##name(unsigned int change, unsigned int newbits) \
1521{ \ 1534{ \
1522 unsigned int res; \ 1535 unsigned int res; \
1536 unsigned int new; \
1523 unsigned int omt; \ 1537 unsigned int omt; \
1524 unsigned long flags; \ 1538 unsigned long flags; \
1525 \ 1539 \
@@ -1527,9 +1541,9 @@ change_c0_##name(unsigned int change, unsigned int new) \
1527 \ 1541 \
1528 omt = __dmt(); \ 1542 omt = __dmt(); \
1529 res = read_c0_##name(); \ 1543 res = read_c0_##name(); \
1530 res &= ~change; \ 1544 new = res & ~change; \
1531 res |= (new & change); \ 1545 new |= (newbits & change); \
1532 write_c0_##name(res); \ 1546 write_c0_##name(new); \
1533 __emt(omt); \ 1547 __emt(omt); \
1534 local_irq_restore(flags); \ 1548 local_irq_restore(flags); \
1535 \ 1549 \
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index fe7a88ea066e..9f946e4ca057 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -23,6 +23,9 @@
23#ifdef CONFIG_PAGE_SIZE_16KB 23#ifdef CONFIG_PAGE_SIZE_16KB
24#define PAGE_SHIFT 14 24#define PAGE_SHIFT 14
25#endif 25#endif
26#ifdef CONFIG_PAGE_SIZE_32KB
27#define PAGE_SHIFT 15
28#endif
26#ifdef CONFIG_PAGE_SIZE_64KB 29#ifdef CONFIG_PAGE_SIZE_64KB
27#define PAGE_SHIFT 16 30#define PAGE_SHIFT 16
28#endif 31#endif
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 943515f0ef87..4ed9d1bba2ba 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -83,6 +83,12 @@
83#define PMD_ORDER 0 83#define PMD_ORDER 0
84#define PTE_ORDER 0 84#define PTE_ORDER 0
85#endif 85#endif
86#ifdef CONFIG_PAGE_SIZE_32KB
87#define PGD_ORDER 0
88#define PUD_ORDER aieeee_attempt_to_allocate_pud
89#define PMD_ORDER 0
90#define PTE_ORDER 0
91#endif
86#ifdef CONFIG_PAGE_SIZE_64KB 92#ifdef CONFIG_PAGE_SIZE_64KB
87#define PGD_ORDER 0 93#define PGD_ORDER 0
88#define PUD_ORDER aieeee_attempt_to_allocate_pud 94#define PUD_ORDER aieeee_attempt_to_allocate_pud
diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
index fec9bdd34913..3a56d90abfa6 100644
--- a/arch/mips/include/asm/sn/addrs.h
+++ b/arch/mips/include/asm/sn/addrs.h
@@ -359,11 +359,11 @@
359 TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice)) 359 TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
360#define LAUNCH_SIZE(nasid) KLD_LAUNCH(nasid)->size 360#define LAUNCH_SIZE(nasid) KLD_LAUNCH(nasid)->size
361 361
362#define NMI_OFFSET(nasid, slice) \ 362#define SN_NMI_OFFSET(nasid, slice) \
363 (KLD_NMI(nasid)->offset + \ 363 (KLD_NMI(nasid)->offset + \
364 KLD_NMI(nasid)->stride * (slice)) 364 KLD_NMI(nasid)->stride * (slice))
365#define NMI_ADDR(nasid, slice) \ 365#define NMI_ADDR(nasid, slice) \
366 TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice)) 366 TO_NODE_UNCAC((nasid), SN_NMI_OFFSET(nasid, slice))
367#define NMI_SIZE(nasid) KLD_NMI(nasid)->size 367#define NMI_SIZE(nasid) KLD_NMI(nasid)->size
368 368
369#define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset 369#define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset
diff --git a/arch/mips/include/asm/sn/nmi.h b/arch/mips/include/asm/sn/nmi.h
index 6b7b0b5f3729..1af49897d4e1 100644
--- a/arch/mips/include/asm/sn/nmi.h
+++ b/arch/mips/include/asm/sn/nmi.h
@@ -3,13 +3,13 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Derived from IRIX <sys/SN/nmi.h>, Revision 1.5.
7 *
6 * Copyright (C) 1992 - 1997 Silicon Graphics, Inc. 8 * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
7 */ 9 */
8#ifndef __ASM_SN_NMI_H 10#ifndef __ASM_SN_NMI_H
9#define __ASM_SN_NMI_H 11#define __ASM_SN_NMI_H
10 12
11#ident "$Revision: 1.5 $"
12
13#include <asm/sn/addrs.h> 13#include <asm/sn/addrs.h>
14 14
15/* 15/*
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 676aa2ae1913..143a48136a4b 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -75,6 +75,9 @@ register struct thread_info *__current_thread_info __asm__("$28");
75#ifdef CONFIG_PAGE_SIZE_16KB 75#ifdef CONFIG_PAGE_SIZE_16KB
76#define THREAD_SIZE_ORDER (0) 76#define THREAD_SIZE_ORDER (0)
77#endif 77#endif
78#ifdef CONFIG_PAGE_SIZE_32KB
79#define THREAD_SIZE_ORDER (0)
80#endif
78#ifdef CONFIG_PAGE_SIZE_64KB 81#ifdef CONFIG_PAGE_SIZE_64KB
79#define THREAD_SIZE_ORDER (0) 82#define THREAD_SIZE_ORDER (0)
80#endif 83#endif
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 38a30d2ee959..df6a430de5eb 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -57,7 +57,11 @@ extern int r4k_clockevent_init(void);
57 57
58static inline int mips_clockevent_init(void) 58static inline int mips_clockevent_init(void)
59{ 59{
60#ifdef CONFIG_CEVT_R4K 60#ifdef CONFIG_MIPS_MT_SMTC
61 extern int smtc_clockevent_init(void);
62
63 return smtc_clockevent_init();
64#elif defined(CONFIG_CEVT_R4K)
61 return r4k_clockevent_init(); 65 return r4k_clockevent_init();
62#else 66#else
63 return -ENXIO; 67 return -ENXIO;
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index 09ff5bb17445..c2d53c18fd36 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -105,10 +105,20 @@
105#define __access_mask get_fs().seg 105#define __access_mask get_fs().seg
106 106
107#define __access_ok(addr, size, mask) \ 107#define __access_ok(addr, size, mask) \
108 (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) 108({ \
109 unsigned long __addr = (unsigned long) (addr); \
110 unsigned long __size = size; \
111 unsigned long __mask = mask; \
112 unsigned long __ok; \
113 \
114 __chk_user_ptr(addr); \
115 __ok = (signed long)(__mask & (__addr | (__addr + __size) | \
116 __ua_size(__size))); \
117 __ok == 0; \
118})
109 119
110#define access_ok(type, addr, size) \ 120#define access_ok(type, addr, size) \
111 likely(__access_ok((unsigned long)(addr), (size), __access_mask)) 121 likely(__access_ok((addr), (size), __access_mask))
112 122
113/* 123/*
114 * put_user: - Write a simple value into user space. 124 * put_user: - Write a simple value into user space.
@@ -225,6 +235,7 @@ do { \
225({ \ 235({ \
226 int __gu_err; \ 236 int __gu_err; \
227 \ 237 \
238 __chk_user_ptr(ptr); \
228 __get_user_common((x), size, ptr); \ 239 __get_user_common((x), size, ptr); \
229 __gu_err; \ 240 __gu_err; \
230}) 241})
@@ -234,6 +245,7 @@ do { \
234 int __gu_err = -EFAULT; \ 245 int __gu_err = -EFAULT; \
235 const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \ 246 const __typeof__(*(ptr)) __user * __gu_ptr = (ptr); \
236 \ 247 \
248 might_fault(); \
237 if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \ 249 if (likely(access_ok(VERIFY_READ, __gu_ptr, size))) \
238 __get_user_common((x), size, __gu_ptr); \ 250 __get_user_common((x), size, __gu_ptr); \
239 \ 251 \
@@ -305,6 +317,7 @@ do { \
305 __typeof__(*(ptr)) __pu_val; \ 317 __typeof__(*(ptr)) __pu_val; \
306 int __pu_err = 0; \ 318 int __pu_err = 0; \
307 \ 319 \
320 __chk_user_ptr(ptr); \
308 __pu_val = (x); \ 321 __pu_val = (x); \
309 switch (size) { \ 322 switch (size) { \
310 case 1: __put_user_asm("sb", ptr); break; \ 323 case 1: __put_user_asm("sb", ptr); break; \
@@ -322,6 +335,7 @@ do { \
322 __typeof__(*(ptr)) __pu_val = (x); \ 335 __typeof__(*(ptr)) __pu_val = (x); \
323 int __pu_err = -EFAULT; \ 336 int __pu_err = -EFAULT; \
324 \ 337 \
338 might_fault(); \
325 if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \ 339 if (likely(access_ok(VERIFY_WRITE, __pu_addr, size))) { \
326 switch (size) { \ 340 switch (size) { \
327 case 1: __put_user_asm("sb", __pu_addr); break; \ 341 case 1: __put_user_asm("sb", __pu_addr); break; \
@@ -696,10 +710,10 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
696 const void *__cu_from; \ 710 const void *__cu_from; \
697 long __cu_len; \ 711 long __cu_len; \
698 \ 712 \
699 might_sleep(); \
700 __cu_to = (to); \ 713 __cu_to = (to); \
701 __cu_from = (from); \ 714 __cu_from = (from); \
702 __cu_len = (n); \ 715 __cu_len = (n); \
716 might_fault(); \
703 __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \ 717 __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
704 __cu_len; \ 718 __cu_len; \
705}) 719})
@@ -752,13 +766,14 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
752 const void *__cu_from; \ 766 const void *__cu_from; \
753 long __cu_len; \ 767 long __cu_len; \
754 \ 768 \
755 might_sleep(); \
756 __cu_to = (to); \ 769 __cu_to = (to); \
757 __cu_from = (from); \ 770 __cu_from = (from); \
758 __cu_len = (n); \ 771 __cu_len = (n); \
759 if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) \ 772 if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) { \
773 might_fault(); \
760 __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, \ 774 __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, \
761 __cu_len); \ 775 __cu_len); \
776 } \
762 __cu_len; \ 777 __cu_len; \
763}) 778})
764 779
@@ -831,10 +846,10 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
831 const void __user *__cu_from; \ 846 const void __user *__cu_from; \
832 long __cu_len; \ 847 long __cu_len; \
833 \ 848 \
834 might_sleep(); \
835 __cu_to = (to); \ 849 __cu_to = (to); \
836 __cu_from = (from); \ 850 __cu_from = (from); \
837 __cu_len = (n); \ 851 __cu_len = (n); \
852 might_fault(); \
838 __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ 853 __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \
839 __cu_len); \ 854 __cu_len); \
840 __cu_len; \ 855 __cu_len; \
@@ -862,17 +877,31 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
862 const void __user *__cu_from; \ 877 const void __user *__cu_from; \
863 long __cu_len; \ 878 long __cu_len; \
864 \ 879 \
865 might_sleep(); \
866 __cu_to = (to); \ 880 __cu_to = (to); \
867 __cu_from = (from); \ 881 __cu_from = (from); \
868 __cu_len = (n); \ 882 __cu_len = (n); \
869 if (access_ok(VERIFY_READ, __cu_from, __cu_len)) \ 883 if (access_ok(VERIFY_READ, __cu_from, __cu_len)) { \
884 might_fault(); \
870 __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ 885 __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \
871 __cu_len); \ 886 __cu_len); \
887 } \
872 __cu_len; \ 888 __cu_len; \
873}) 889})
874 890
875#define __copy_in_user(to, from, n) __copy_from_user(to, from, n) 891#define __copy_in_user(to, from, n) \
892({ \
893 void __user *__cu_to; \
894 const void __user *__cu_from; \
895 long __cu_len; \
896 \
897 __cu_to = (to); \
898 __cu_from = (from); \
899 __cu_len = (n); \
900 might_fault(); \
901 __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \
902 __cu_len); \
903 __cu_len; \
904})
876 905
877#define copy_in_user(to, from, n) \ 906#define copy_in_user(to, from, n) \
878({ \ 907({ \
@@ -880,14 +909,15 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
880 const void __user *__cu_from; \ 909 const void __user *__cu_from; \
881 long __cu_len; \ 910 long __cu_len; \
882 \ 911 \
883 might_sleep(); \
884 __cu_to = (to); \ 912 __cu_to = (to); \
885 __cu_from = (from); \ 913 __cu_from = (from); \
886 __cu_len = (n); \ 914 __cu_len = (n); \
887 if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) && \ 915 if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) && \
888 access_ok(VERIFY_WRITE, __cu_to, __cu_len))) \ 916 access_ok(VERIFY_WRITE, __cu_to, __cu_len))) { \
917 might_fault(); \
889 __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ 918 __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \
890 __cu_len); \ 919 __cu_len); \
920 } \
891 __cu_len; \ 921 __cu_len; \
892}) 922})
893 923
@@ -907,7 +937,7 @@ __clear_user(void __user *addr, __kernel_size_t size)
907{ 937{
908 __kernel_size_t res; 938 __kernel_size_t res;
909 939
910 might_sleep(); 940 might_fault();
911 __asm__ __volatile__( 941 __asm__ __volatile__(
912 "move\t$4, %1\n\t" 942 "move\t$4, %1\n\t"
913 "move\t$5, $0\n\t" 943 "move\t$5, $0\n\t"
@@ -926,7 +956,7 @@ __clear_user(void __user *addr, __kernel_size_t size)
926 void __user * __cl_addr = (addr); \ 956 void __user * __cl_addr = (addr); \
927 unsigned long __cl_size = (n); \ 957 unsigned long __cl_size = (n); \
928 if (__cl_size && access_ok(VERIFY_WRITE, \ 958 if (__cl_size && access_ok(VERIFY_WRITE, \
929 ((unsigned long)(__cl_addr)), __cl_size)) \ 959 __cl_addr, __cl_size)) \
930 __cl_size = __clear_user(__cl_addr, __cl_size); \ 960 __cl_size = __clear_user(__cl_addr, __cl_size); \
931 __cl_size; \ 961 __cl_size; \
932}) 962})
@@ -956,7 +986,7 @@ __strncpy_from_user(char *__to, const char __user *__from, long __len)
956{ 986{
957 long res; 987 long res;
958 988
959 might_sleep(); 989 might_fault();
960 __asm__ __volatile__( 990 __asm__ __volatile__(
961 "move\t$4, %1\n\t" 991 "move\t$4, %1\n\t"
962 "move\t$5, %2\n\t" 992 "move\t$5, %2\n\t"
@@ -993,7 +1023,7 @@ strncpy_from_user(char *__to, const char __user *__from, long __len)
993{ 1023{
994 long res; 1024 long res;
995 1025
996 might_sleep(); 1026 might_fault();
997 __asm__ __volatile__( 1027 __asm__ __volatile__(
998 "move\t$4, %1\n\t" 1028 "move\t$4, %1\n\t"
999 "move\t$5, %2\n\t" 1029 "move\t$5, %2\n\t"
@@ -1012,7 +1042,7 @@ static inline long __strlen_user(const char __user *s)
1012{ 1042{
1013 long res; 1043 long res;
1014 1044
1015 might_sleep(); 1045 might_fault();
1016 __asm__ __volatile__( 1046 __asm__ __volatile__(
1017 "move\t$4, %1\n\t" 1047 "move\t$4, %1\n\t"
1018 __MODULE_JAL(__strlen_user_nocheck_asm) 1048 __MODULE_JAL(__strlen_user_nocheck_asm)
@@ -1042,7 +1072,7 @@ static inline long strlen_user(const char __user *s)
1042{ 1072{
1043 long res; 1073 long res;
1044 1074
1045 might_sleep(); 1075 might_fault();
1046 __asm__ __volatile__( 1076 __asm__ __volatile__(
1047 "move\t$4, %1\n\t" 1077 "move\t$4, %1\n\t"
1048 __MODULE_JAL(__strlen_user_asm) 1078 __MODULE_JAL(__strlen_user_asm)
@@ -1059,7 +1089,7 @@ static inline long __strnlen_user(const char __user *s, long n)
1059{ 1089{
1060 long res; 1090 long res;
1061 1091
1062 might_sleep(); 1092 might_fault();
1063 __asm__ __volatile__( 1093 __asm__ __volatile__(
1064 "move\t$4, %1\n\t" 1094 "move\t$4, %1\n\t"
1065 "move\t$5, %2\n\t" 1095 "move\t$5, %2\n\t"
@@ -1090,7 +1120,7 @@ static inline long strnlen_user(const char __user *s, long n)
1090{ 1120{
1091 long res; 1121 long res;
1092 1122
1093 might_sleep(); 1123 might_fault();
1094 __asm__ __volatile__( 1124 __asm__ __volatile__(
1095 "move\t$4, %1\n\t" 1125 "move\t$4, %1\n\t"
1096 "move\t$5, %2\n\t" 1126 "move\t$5, %2\n\t"
diff --git a/arch/mips/kernel/cevt-smtc.c b/arch/mips/kernel/cevt-smtc.c
index 6d45e24db5bf..df6f5bc60572 100644
--- a/arch/mips/kernel/cevt-smtc.c
+++ b/arch/mips/kernel/cevt-smtc.c
@@ -245,7 +245,7 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
245} 245}
246 246
247 247
248int __cpuinit mips_clockevent_init(void) 248int __cpuinit smtc_clockevent_init(void)
249{ 249{
250 uint64_t mips_freq = mips_hpt_frequency; 250 uint64_t mips_freq = mips_hpt_frequency;
251 unsigned int cpu = smp_processor_id(); 251 unsigned int cpu = smp_processor_id();
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 26760cad8b69..e0a4ac18fa07 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -42,7 +42,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
42 seq_printf(m, fmt, __cpu_name[n], 42 seq_printf(m, fmt, __cpu_name[n],
43 (version >> 4) & 0x0f, version & 0x0f, 43 (version >> 4) & 0x0f, version & 0x0f,
44 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); 44 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
45 seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", 45 seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
46 cpu_data[n].udelay_val / (500000/HZ), 46 cpu_data[n].udelay_val / (500000/HZ),
47 (cpu_data[n].udelay_val / (5000/HZ)) % 100); 47 (cpu_data[n].udelay_val / (5000/HZ)) % 100);
48 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); 48 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index c2c16ef9218f..93cc672f4522 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -405,8 +405,8 @@ EXPORT(sysn32_call_table)
405 PTR sys_eventfd 405 PTR sys_eventfd
406 PTR sys_fallocate 406 PTR sys_fallocate
407 PTR sys_timerfd_create 407 PTR sys_timerfd_create
408 PTR sys_timerfd_gettime /* 5285 */ 408 PTR compat_sys_timerfd_gettime /* 5285 */
409 PTR sys_timerfd_settime 409 PTR compat_sys_timerfd_settime
410 PTR sys_signalfd4 410 PTR sys_signalfd4
411 PTR sys_eventfd2 411 PTR sys_eventfd2
412 PTR sys_epoll_create1 412 PTR sys_epoll_create1
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 002fac27021e..a5598b2339dd 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -525,8 +525,8 @@ sys_call_table:
525 PTR sys_eventfd 525 PTR sys_eventfd
526 PTR sys32_fallocate /* 4320 */ 526 PTR sys32_fallocate /* 4320 */
527 PTR sys_timerfd_create 527 PTR sys_timerfd_create
528 PTR sys_timerfd_gettime 528 PTR compat_sys_timerfd_gettime
529 PTR sys_timerfd_settime 529 PTR compat_sys_timerfd_settime
530 PTR compat_sys_signalfd4 530 PTR compat_sys_signalfd4
531 PTR sys_eventfd2 /* 4325 */ 531 PTR sys_eventfd2 /* 4325 */
532 PTR sys_epoll_create1 532 PTR sys_epoll_create1
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index bf4c4a979abb..67bd626942ab 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -482,19 +482,19 @@ fault:
482 return; 482 return;
483 483
484 die_if_kernel("Unhandled kernel unaligned access", regs); 484 die_if_kernel("Unhandled kernel unaligned access", regs);
485 send_sig(SIGSEGV, current, 1); 485 force_sig(SIGSEGV, current);
486 486
487 return; 487 return;
488 488
489sigbus: 489sigbus:
490 die_if_kernel("Unhandled kernel unaligned access", regs); 490 die_if_kernel("Unhandled kernel unaligned access", regs);
491 send_sig(SIGBUS, current, 1); 491 force_sig(SIGBUS, current);
492 492
493 return; 493 return;
494 494
495sigill: 495sigill:
496 die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); 496 die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs);
497 send_sig(SIGILL, current, 1); 497 force_sig(SIGILL, current);
498} 498}
499 499
500asmlinkage void do_ade(struct pt_regs *regs) 500asmlinkage void do_ade(struct pt_regs *regs)
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index c13c7ad2cdae..2adead5a8a37 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -2,8 +2,8 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial.o memcpy.o memcpy-inatomic.o memset.o strlen_user.o \ 5lib-y += csum_partial.o delay.o memcpy.o memcpy-inatomic.o memset.o \
6 strncpy_user.o strnlen_user.o uncached.o 6 strlen_user.o strncpy_user.o strnlen_user.o uncached.o
7 7
8obj-y += iomap.o 8obj-y += iomap.o
9obj-$(CONFIG_PCI) += iomap-pci.o 9obj-$(CONFIG_PCI) += iomap-pci.o
diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c
new file mode 100644
index 000000000000..f69c6b569eb3
--- /dev/null
+++ b/arch/mips/lib/delay.c
@@ -0,0 +1,56 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 by Waldorf Electronics
7 * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2007 Maciej W. Rozycki
10 */
11#include <linux/module.h>
12#include <linux/param.h>
13#include <linux/smp.h>
14
15#include <asm/compiler.h>
16#include <asm/war.h>
17
18inline void __delay(unsigned int loops)
19{
20 __asm__ __volatile__ (
21 " .set noreorder \n"
22 " .align 3 \n"
23 "1: bnez %0, 1b \n"
24 " subu %0, 1 \n"
25 " .set reorder \n"
26 : "=r" (loops)
27 : "0" (loops));
28}
29EXPORT_SYMBOL(__delay);
30
31/*
32 * Division by multiplication: you don't have to worry about
33 * loss of precision.
34 *
35 * Use only for very small delays ( < 1 msec). Should probably use a
36 * lookup table, really, as the multiplications take much too long with
37 * short delays. This is a "reasonable" implementation, though (and the
38 * first constant multiplications gets optimized away if the delay is
39 * a constant)
40 */
41
42void __udelay(unsigned long us)
43{
44 unsigned int lpj = current_cpu_data.udelay_val;
45
46 __delay((us * 0x000010c7 * HZ * lpj) >> 32);
47}
48EXPORT_SYMBOL(__udelay);
49
50void __ndelay(unsigned long ns)
51{
52 unsigned int lpj = current_cpu_data.udelay_val;
53
54 __delay((us * 0x00000005 * HZ * lpj) >> 32);
55}
56EXPORT_SYMBOL(__ndelay);
diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index 779821cd54ab..3f69725556af 100644
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -19,6 +19,15 @@ static inline const char *msk2str(unsigned int mask)
19 case PM_16K: return "16kb"; 19 case PM_16K: return "16kb";
20 case PM_64K: return "64kb"; 20 case PM_64K: return "64kb";
21 case PM_256K: return "256kb"; 21 case PM_256K: return "256kb";
22#ifdef CONFIG_CPU_CAVIUM_OCTEON
23 case PM_8K: return "8kb";
24 case PM_32K: return "32kb";
25 case PM_128K: return "128kb";
26 case PM_512K: return "512kb";
27 case PM_2M: return "2Mb";
28 case PM_8M: return "8Mb";
29 case PM_32M: return "32Mb";
30#endif
22#ifndef CONFIG_CPU_VR41XX 31#ifndef CONFIG_CPU_VR41XX
23 case PM_1M: return "1Mb"; 32 case PM_1M: return "1Mb";
24 case PM_4M: return "4Mb"; 33 case PM_4M: return "4Mb";
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 58d9075e86fe..171951d2305b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1041,7 +1041,7 @@ static void __cpuinit probe_pcache(void)
1041 1041
1042 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", 1042 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1043 icache_size >> 10, 1043 icache_size >> 10,
1044 cpu_has_vtag_icache ? "VIVT" : "VIPT", 1044 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1045 way_string[c->icache.ways], c->icache.linesz); 1045 way_string[c->icache.ways], c->icache.linesz);
1046 1046
1047 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", 1047 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index bed56f1ac837..4fdb7f5216b9 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -209,7 +209,7 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page,
209 unsigned long addr; 209 unsigned long addr;
210 210
211 addr = (unsigned long) page_address(page) + offset; 211 addr = (unsigned long) page_address(page) + offset;
212 dma_cache_wback_inv(addr, size); 212 __dma_sync(addr, size, direction);
213 } 213 }
214 214
215 return plat_map_dma_mem_page(dev, page) + offset; 215 return plat_map_dma_mem_page(dev, page) + offset;
@@ -217,23 +217,6 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page,
217 217
218EXPORT_SYMBOL(dma_map_page); 218EXPORT_SYMBOL(dma_map_page);
219 219
220void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
221 enum dma_data_direction direction)
222{
223 BUG_ON(direction == DMA_NONE);
224
225 if (!plat_device_is_coherent(dev) && direction != DMA_TO_DEVICE) {
226 unsigned long addr;
227
228 addr = dma_addr_to_virt(dma_address);
229 dma_cache_wback_inv(addr, size);
230 }
231
232 plat_unmap_dma_mem(dev, dma_address);
233}
234
235EXPORT_SYMBOL(dma_unmap_page);
236
237void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, 220void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
238 enum dma_data_direction direction) 221 enum dma_data_direction direction)
239{ 222{
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index 4481656d1065..2b1309b2580a 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -1,7 +1,12 @@
1#include <linux/module.h> 1#include <linux/module.h>
2#include <linux/highmem.h> 2#include <linux/highmem.h>
3#include <asm/fixmap.h>
3#include <asm/tlbflush.h> 4#include <asm/tlbflush.h>
4 5
6static pte_t *kmap_pte;
7
8unsigned long highstart_pfn, highend_pfn;
9
5void *__kmap(struct page *page) 10void *__kmap(struct page *page)
6{ 11{
7 void *addr; 12 void *addr;
@@ -14,6 +19,7 @@ void *__kmap(struct page *page)
14 19
15 return addr; 20 return addr;
16} 21}
22EXPORT_SYMBOL(__kmap);
17 23
18void __kunmap(struct page *page) 24void __kunmap(struct page *page)
19{ 25{
@@ -22,6 +28,7 @@ void __kunmap(struct page *page)
22 return; 28 return;
23 kunmap_high(page); 29 kunmap_high(page);
24} 30}
31EXPORT_SYMBOL(__kunmap);
25 32
26/* 33/*
27 * kmap_atomic/kunmap_atomic is significantly faster than kmap/kunmap because 34 * kmap_atomic/kunmap_atomic is significantly faster than kmap/kunmap because
@@ -48,11 +55,12 @@ void *__kmap_atomic(struct page *page, enum km_type type)
48#ifdef CONFIG_DEBUG_HIGHMEM 55#ifdef CONFIG_DEBUG_HIGHMEM
49 BUG_ON(!pte_none(*(kmap_pte - idx))); 56 BUG_ON(!pte_none(*(kmap_pte - idx)));
50#endif 57#endif
51 set_pte(kmap_pte-idx, mk_pte(page, kmap_prot)); 58 set_pte(kmap_pte-idx, mk_pte(page, PAGE_KERNEL));
52 local_flush_tlb_one((unsigned long)vaddr); 59 local_flush_tlb_one((unsigned long)vaddr);
53 60
54 return (void*) vaddr; 61 return (void*) vaddr;
55} 62}
63EXPORT_SYMBOL(__kmap_atomic);
56 64
57void __kunmap_atomic(void *kvaddr, enum km_type type) 65void __kunmap_atomic(void *kvaddr, enum km_type type)
58{ 66{
@@ -77,6 +85,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type)
77 85
78 pagefault_enable(); 86 pagefault_enable();
79} 87}
88EXPORT_SYMBOL(__kunmap_atomic);
80 89
81/* 90/*
82 * This is the same as kmap_atomic() but can map memory that doesn't 91 * This is the same as kmap_atomic() but can map memory that doesn't
@@ -92,7 +101,7 @@ void *kmap_atomic_pfn(unsigned long pfn, enum km_type type)
92 debug_kmap_atomic(type); 101 debug_kmap_atomic(type);
93 idx = type + KM_TYPE_NR*smp_processor_id(); 102 idx = type + KM_TYPE_NR*smp_processor_id();
94 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); 103 vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
95 set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot)); 104 set_pte(kmap_pte-idx, pfn_pte(pfn, PAGE_KERNEL));
96 flush_tlb_one(vaddr); 105 flush_tlb_one(vaddr);
97 106
98 return (void*) vaddr; 107 return (void*) vaddr;
@@ -111,7 +120,11 @@ struct page *__kmap_atomic_to_page(void *ptr)
111 return pte_page(*pte); 120 return pte_page(*pte);
112} 121}
113 122
114EXPORT_SYMBOL(__kmap); 123void __init kmap_init(void)
115EXPORT_SYMBOL(__kunmap); 124{
116EXPORT_SYMBOL(__kmap_atomic); 125 unsigned long kmap_vstart;
117EXPORT_SYMBOL(__kunmap_atomic); 126
127 /* cache the first kmap pte */
128 kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN);
129 kmap_pte = kmap_get_fixmap_pte(kmap_vstart);
130}
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index d9348946a19e..c5511294a9ee 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -104,14 +104,6 @@ unsigned long setup_zero_pages(void)
104 return 1UL << order; 104 return 1UL << order;
105} 105}
106 106
107/*
108 * These are almost like kmap_atomic / kunmap_atmic except they take an
109 * additional address argument as the hint.
110 */
111
112#define kmap_get_fixmap_pte(vaddr) \
113 pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr))
114
115#ifdef CONFIG_MIPS_MT_SMTC 107#ifdef CONFIG_MIPS_MT_SMTC
116static pte_t *kmap_coherent_pte; 108static pte_t *kmap_coherent_pte;
117static void __init kmap_coherent_init(void) 109static void __init kmap_coherent_init(void)
@@ -264,24 +256,6 @@ void copy_from_user_page(struct vm_area_struct *vma,
264 } 256 }
265} 257}
266 258
267#ifdef CONFIG_HIGHMEM
268unsigned long highstart_pfn, highend_pfn;
269
270pte_t *kmap_pte;
271pgprot_t kmap_prot;
272
273static void __init kmap_init(void)
274{
275 unsigned long kmap_vstart;
276
277 /* cache the first kmap pte */
278 kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN);
279 kmap_pte = kmap_get_fixmap_pte(kmap_vstart);
280
281 kmap_prot = PAGE_KERNEL;
282}
283#endif /* CONFIG_HIGHMEM */
284
285void __init fixrange_init(unsigned long start, unsigned long end, 259void __init fixrange_init(unsigned long start, unsigned long end,
286 pgd_t *pgd_base) 260 pgd_t *pgd_base)
287{ 261{
diff --git a/arch/mips/mm/sc-rm7k.c b/arch/mips/mm/sc-rm7k.c
index e3abfb2d7e86..de69bfbf506e 100644
--- a/arch/mips/mm/sc-rm7k.c
+++ b/arch/mips/mm/sc-rm7k.c
@@ -29,7 +29,7 @@ extern unsigned long icache_way_size, dcache_way_size;
29 29
30#include <asm/r4kcache.h> 30#include <asm/r4kcache.h>
31 31
32int rm7k_tcache_enabled; 32static int rm7k_tcache_enabled;
33 33
34/* 34/*
35 * Writeback and invalidate the primary cache dcache before DMA. 35 * Writeback and invalidate the primary cache dcache before DMA.
@@ -121,7 +121,7 @@ static void rm7k_sc_disable(void)
121 clear_c0_config(RM7K_CONF_SE); 121 clear_c0_config(RM7K_CONF_SE);
122} 122}
123 123
124struct bcache_ops rm7k_sc_ops = { 124static struct bcache_ops rm7k_sc_ops = {
125 .bc_enable = rm7k_sc_enable, 125 .bc_enable = rm7k_sc_enable,
126 .bc_disable = rm7k_sc_disable, 126 .bc_disable = rm7k_sc_disable,
127 .bc_wback_inv = rm7k_sc_wback_inv, 127 .bc_wback_inv = rm7k_sc_wback_inv,
diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c
index f0cf46adb978..1c0048a6f5cf 100644
--- a/arch/mips/mm/tlb-r3k.c
+++ b/arch/mips/mm/tlb-r3k.c
@@ -82,8 +82,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
82 int cpu = smp_processor_id(); 82 int cpu = smp_processor_id();
83 83
84 if (cpu_context(cpu, mm) != 0) { 84 if (cpu_context(cpu, mm) != 0) {
85 unsigned long flags; 85 unsigned long size, flags;
86 int size;
87 86
88#ifdef DEBUG_TLB 87#ifdef DEBUG_TLB
89 printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", 88 printk("[tlbrange<%lu,0x%08lx,0x%08lx>]",
@@ -121,8 +120,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
121 120
122void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) 121void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
123{ 122{
124 unsigned long flags; 123 unsigned long size, flags;
125 int size;
126 124
127#ifdef DEBUG_TLB 125#ifdef DEBUG_TLB
128 printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", start, end); 126 printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", start, end);
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 9619f66e531e..892be426787c 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -117,8 +117,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
117 int cpu = smp_processor_id(); 117 int cpu = smp_processor_id();
118 118
119 if (cpu_context(cpu, mm) != 0) { 119 if (cpu_context(cpu, mm) != 0) {
120 unsigned long flags; 120 unsigned long size, flags;
121 int size;
122 121
123 ENTER_CRITICAL(flags); 122 ENTER_CRITICAL(flags);
124 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 123 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
@@ -160,8 +159,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
160 159
161void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) 160void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
162{ 161{
163 unsigned long flags; 162 unsigned long size, flags;
164 int size;
165 163
166 ENTER_CRITICAL(flags); 164 ENTER_CRITICAL(flags);
167 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 165 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c
index 4f01a3be215c..4ec95cc2df2f 100644
--- a/arch/mips/mm/tlb-r8k.c
+++ b/arch/mips/mm/tlb-r8k.c
@@ -111,8 +111,7 @@ out_restore:
111/* Usable for KV1 addresses only! */ 111/* Usable for KV1 addresses only! */
112void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) 112void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
113{ 113{
114 unsigned long flags; 114 unsigned long size, flags;
115 int size;
116 115
117 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 116 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
118 size = (size + 1) >> 1; 117 size = (size + 1) >> 1;
diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig
index 90261b83db04..c139988bb85d 100644
--- a/arch/mips/pmc-sierra/Kconfig
+++ b/arch/mips/pmc-sierra/Kconfig
@@ -36,18 +36,6 @@ config PMC_MSP7120_FPGA
36 36
37endchoice 37endchoice
38 38
39menu "Options for PMC-Sierra MSP chipsets"
40 depends on PMC_MSP
41
42config PMC_MSP_EMBEDDED_ROOTFS
43 bool "Root filesystem embedded in kernel image"
44 select MTD
45 select MTD_BLOCK
46 select MTD_PMC_MSP_RAMROOT
47 select MTD_RAM
48
49endmenu
50
51config HYPERTRANSPORT 39config HYPERTRANSPORT
52 bool "Hypertransport Support for PMC-Sierra Yosemite" 40 bool "Hypertransport Support for PMC-Sierra Yosemite"
53 depends on PMC_YOSEMITE 41 depends on PMC_YOSEMITE
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_prom.c b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
index e5bd5481d8db..c317a3623ce9 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_prom.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
@@ -40,12 +40,6 @@
40#include <linux/string.h> 40#include <linux/string.h>
41#include <linux/interrupt.h> 41#include <linux/interrupt.h>
42#include <linux/mm.h> 42#include <linux/mm.h>
43#ifdef CONFIG_CRAMFS
44#include <linux/cramfs_fs.h>
45#endif
46#ifdef CONFIG_SQUASHFS
47#include <linux/squashfs_fs.h>
48#endif
49 43
50#include <asm/addrspace.h> 44#include <asm/addrspace.h>
51#include <asm/bootinfo.h> 45#include <asm/bootinfo.h>
@@ -435,10 +429,6 @@ struct prom_pmemblock *__init prom_getmdesc(void)
435 char *str; 429 char *str;
436 unsigned int memsize; 430 unsigned int memsize;
437 unsigned int heaptop; 431 unsigned int heaptop;
438#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
439 void *ramroot_start;
440 unsigned long ramroot_size;
441#endif
442 int i; 432 int i;
443 433
444 str = prom_getenv(memsz_env); 434 str = prom_getenv(memsz_env);
@@ -506,19 +496,7 @@ struct prom_pmemblock *__init prom_getmdesc(void)
506 i++; /* 3 */ 496 i++; /* 3 */
507 mdesc[i].type = BOOT_MEM_RESERVED; 497 mdesc[i].type = BOOT_MEM_RESERVED;
508 mdesc[i].base = CPHYSADDR((u32)_text); 498 mdesc[i].base = CPHYSADDR((u32)_text);
509#ifdef CONFIG_MTD_PMC_MSP_RAMROOT 499 mdesc[i].size = CPHYSADDR(PAGE_ALIGN((u32)_end)) - mdesc[i].base;
510 if (get_ramroot(&ramroot_start, &ramroot_size)) {
511 /*
512 * Rootfs in RAM -- follows kernel
513 * Combine rootfs image with kernel block so a
514 * page (4k) isn't wasted between memory blocks
515 */
516 mdesc[i].size = CPHYSADDR(PAGE_ALIGN(
517 (u32)ramroot_start + ramroot_size)) - mdesc[i].base;
518 } else
519#endif
520 mdesc[i].size = CPHYSADDR(PAGE_ALIGN(
521 (u32)_end)) - mdesc[i].base;
522 500
523 /* Remainder of RAM -- under memsize */ 501 /* Remainder of RAM -- under memsize */
524 i++; /* 5 */ 502 i++; /* 5 */
@@ -528,39 +506,3 @@ struct prom_pmemblock *__init prom_getmdesc(void)
528 506
529 return &mdesc[0]; 507 return &mdesc[0];
530} 508}
531
532/* rootfs functions */
533#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
534bool get_ramroot(void **start, unsigned long *size)
535{
536 extern char _end[];
537
538 /* Check for start following the end of the kernel */
539 void *check_start = (void *)_end;
540
541 /* Check for supported rootfs types */
542#ifdef CONFIG_CRAMFS
543 if (*(__u32 *)check_start == CRAMFS_MAGIC) {
544 /* Get CRAMFS size */
545 *start = check_start;
546 *size = PAGE_ALIGN(((struct cramfs_super *)
547 check_start)->size);
548
549 return true;
550 }
551#endif
552#ifdef CONFIG_SQUASHFS
553 if (*((unsigned int *)check_start) == SQUASHFS_MAGIC) {
554 /* Get SQUASHFS size */
555 *start = check_start;
556 *size = PAGE_ALIGN(((struct squashfs_super_block *)
557 check_start)->bytes_used);
558
559 return true;
560 }
561#endif
562
563 return false;
564}
565EXPORT_SYMBOL(get_ramroot);
566#endif
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
index c93675615f5d..a54e85b3cf29 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
@@ -21,7 +21,6 @@
21 21
22#if defined(CONFIG_PMC_MSP7120_GW) 22#if defined(CONFIG_PMC_MSP7120_GW)
23#include <msp_regops.h> 23#include <msp_regops.h>
24#include <msp_gpio.h>
25#define MSP_BOARD_RESET_GPIO 9 24#define MSP_BOARD_RESET_GPIO 9
26#endif 25#endif
27 26
@@ -88,11 +87,8 @@ void msp7120_reset(void)
88 * as GPIO char driver may not be enabled and it would look up 87 * as GPIO char driver may not be enabled and it would look up
89 * data inRAM! 88 * data inRAM!
90 */ 89 */
91 set_value_reg32(GPIO_CFG3_REG, 90 set_value_reg32(GPIO_CFG3_REG, 0xf000, 0x8000);
92 basic_mode_mask(MSP_BOARD_RESET_GPIO), 91 set_reg32(GPIO_DATA3_REG, 8);
93 basic_mode(MSP_GPIO_OUTPUT, MSP_BOARD_RESET_GPIO));
94 set_reg32(GPIO_DATA3_REG,
95 basic_data_mask(MSP_BOARD_RESET_GPIO));
96 92
97 /* 93 /*
98 * In case GPIO9 doesn't reset the board (jumper configurable!) 94 * In case GPIO9 doesn't reset the board (jumper configurable!)
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c
index 7cfeda5a651b..cca64e15f57f 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_time.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c
@@ -81,10 +81,7 @@ void __init plat_time_init(void)
81 mips_hpt_frequency = cpu_rate/2; 81 mips_hpt_frequency = cpu_rate/2;
82} 82}
83 83
84void __init plat_timer_setup(struct irqaction *irq) 84unsigned int __init get_c0_compare_int(void)
85{ 85{
86#ifdef CONFIG_IRQ_MSP_CIC 86 return MSP_INT_VPE0_TIMER;
87 /* we are using the vpe0 counter for timer interrupts */
88 setup_irq(MSP_INT_VPE0_TIMER, irq);
89#endif
90} 87}
diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c
index 4ad5c3393fd3..45b6694c2079 100644
--- a/arch/mips/sgi-ip22/ip22-reset.c
+++ b/arch/mips/sgi-ip22/ip22-reset.c
@@ -148,7 +148,7 @@ static irqreturn_t panel_int(int irq, void *dev_id)
148 148
149 if (sgint->istat1 & SGINT_ISTAT1_PWR) { 149 if (sgint->istat1 & SGINT_ISTAT1_PWR) {
150 /* Wait until interrupt goes away */ 150 /* Wait until interrupt goes away */
151 disable_irq(SGI_PANEL_IRQ); 151 disable_irq_nosync(SGI_PANEL_IRQ);
152 init_timer(&debounce_timer); 152 init_timer(&debounce_timer);
153 debounce_timer.function = debounce; 153 debounce_timer.function = debounce;
154 debounce_timer.expires = jiffies + 5; 154 debounce_timer.expires = jiffies + 5;
diff --git a/arch/mips/sgi-ip32/ip32-berr.c b/arch/mips/sgi-ip32/ip32-berr.c
index a278e918a019..afc1cadbba37 100644
--- a/arch/mips/sgi-ip32/ip32-berr.c
+++ b/arch/mips/sgi-ip32/ip32-berr.c
@@ -16,7 +16,7 @@
16#include <asm/ptrace.h> 16#include <asm/ptrace.h>
17#include <asm/tlbdebug.h> 17#include <asm/tlbdebug.h>
18 18
19int ip32_be_handler(struct pt_regs *regs, int is_fixup) 19static int ip32_be_handler(struct pt_regs *regs, int is_fixup)
20{ 20{
21 int data = regs->cp0_cause & 4; 21 int data = regs->cp0_cause & 4;
22 22
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index 83a0b3c359da..5c2bf111ca67 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -112,13 +112,13 @@ static void inline flush_mace_bus(void)
112extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); 112extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
113extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); 113extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
114 114
115struct irqaction memerr_irq = { 115static struct irqaction memerr_irq = {
116 .handler = crime_memerr_intr, 116 .handler = crime_memerr_intr,
117 .flags = IRQF_DISABLED, 117 .flags = IRQF_DISABLED,
118 .name = "CRIME memory error", 118 .name = "CRIME memory error",
119}; 119};
120 120
121struct irqaction cpuerr_irq = { 121static struct irqaction cpuerr_irq = {
122 .handler = crime_cpuerr_intr, 122 .handler = crime_cpuerr_intr,
123 .flags = IRQF_DISABLED, 123 .flags = IRQF_DISABLED,
124 .name = "CRIME CPU error", 124 .name = "CRIME CPU error",
diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c
index b6cab089561e..9b95d80ebc6e 100644
--- a/arch/mips/sgi-ip32/ip32-reset.c
+++ b/arch/mips/sgi-ip32/ip32-reset.c
@@ -53,7 +53,7 @@ static inline void ip32_machine_halt(void)
53 53
54static void ip32_machine_power_off(void) 54static void ip32_machine_power_off(void)
55{ 55{
56 volatile unsigned char reg_a, xctrl_a, xctrl_b; 56 unsigned char reg_a, xctrl_a, xctrl_b;
57 57
58 disable_irq(MACEISA_RTC_IRQ); 58 disable_irq(MACEISA_RTC_IRQ);
59 reg_a = CMOS_READ(RTC_REG_A); 59 reg_a = CMOS_READ(RTC_REG_A);
@@ -91,9 +91,10 @@ static void blink_timeout(unsigned long data)
91 91
92static void debounce(unsigned long data) 92static void debounce(unsigned long data)
93{ 93{
94 volatile unsigned char reg_a, reg_c, xctrl_a; 94 unsigned char reg_a, reg_c, xctrl_a;
95 95
96 reg_c = CMOS_READ(RTC_INTR_FLAGS); 96 reg_c = CMOS_READ(RTC_INTR_FLAGS);
97 reg_a = CMOS_READ(RTC_REG_A);
97 CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A); 98 CMOS_WRITE(reg_a | DS_REGA_DV0, RTC_REG_A);
98 wbflush(); 99 wbflush();
99 xctrl_a = CMOS_READ(DS_B1_XCTRL4A); 100 xctrl_a = CMOS_READ(DS_B1_XCTRL4A);
@@ -137,7 +138,7 @@ static inline void ip32_power_button(void)
137 138
138static irqreturn_t ip32_rtc_int(int irq, void *dev_id) 139static irqreturn_t ip32_rtc_int(int irq, void *dev_id)
139{ 140{
140 volatile unsigned char reg_c; 141 unsigned char reg_c;
141 142
142 reg_c = CMOS_READ(RTC_INTR_FLAGS); 143 reg_c = CMOS_READ(RTC_INTR_FLAGS);
143 if (!(reg_c & RTC_IRQF)) { 144 if (!(reg_c & RTC_IRQF)) {
@@ -145,7 +146,7 @@ static irqreturn_t ip32_rtc_int(int irq, void *dev_id)
145 "%s: RTC IRQ without RTC_IRQF\n", __func__); 146 "%s: RTC IRQ without RTC_IRQF\n", __func__);
146 } 147 }
147 /* Wait until interrupt goes away */ 148 /* Wait until interrupt goes away */
148 disable_irq(MACEISA_RTC_IRQ); 149 disable_irq_nosync(MACEISA_RTC_IRQ);
149 init_timer(&debounce_timer); 150 init_timer(&debounce_timer);
150 debounce_timer.function = debounce; 151 debounce_timer.function = debounce;
151 debounce_timer.expires = jiffies + 50; 152 debounce_timer.expires = jiffies + 50;
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 352352b3cb2f..c147c4b35d3f 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -113,7 +113,6 @@ static void bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
113{ 113{
114 int i = 0, old_cpu, cpu, int_on, k; 114 int i = 0, old_cpu, cpu, int_on, k;
115 u64 cur_ints; 115 u64 cur_ints;
116 struct irq_desc *desc = irq_desc + irq;
117 unsigned long flags; 116 unsigned long flags;
118 unsigned int irq_dirty; 117 unsigned int irq_dirty;
119 118
@@ -127,8 +126,7 @@ static void bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
127 cpu = cpu_logical_map(i); 126 cpu = cpu_logical_map(i);
128 127
129 /* Protect against other affinity changers and IMR manipulation */ 128 /* Protect against other affinity changers and IMR manipulation */
130 spin_lock_irqsave(&desc->lock, flags); 129 spin_lock_irqsave(&bcm1480_imr_lock, flags);
131 spin_lock(&bcm1480_imr_lock);
132 130
133 /* Swizzle each CPU's IMR (but leave the IP selection alone) */ 131 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
134 old_cpu = bcm1480_irq_owner[irq]; 132 old_cpu = bcm1480_irq_owner[irq];
@@ -153,8 +151,7 @@ static void bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
153 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); 151 ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
154 } 152 }
155 } 153 }
156 spin_unlock(&bcm1480_imr_lock); 154 spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
157 spin_unlock_irqrestore(&desc->lock, flags);
158} 155}
159#endif 156#endif
160 157
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index 3de30f79db3f..eb5396cf81bb 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -288,13 +288,7 @@ void __init prom_init(void)
288 */ 288 */
289 cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); 289 cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
290 if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) { 290 if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) {
291 if (argc < 0) { 291 if (argc >= 0) {
292 /*
293 * It's OK for direct boot to not provide a
294 * command line
295 */
296 strcpy(arcs_cmdline, "root=/dev/ram0 ");
297 } else {
298 /* The loader should have set the command line */ 292 /* The loader should have set the command line */
299 /* too early for panic to do any good */ 293 /* too early for panic to do any good */
300 printk("LINUX_CMDLINE not defined in cfe."); 294 printk("LINUX_CMDLINE not defined in cfe.");
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index c08ff582da6f..38cb998ade22 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -107,7 +107,6 @@ static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
107{ 107{
108 int i = 0, old_cpu, cpu, int_on; 108 int i = 0, old_cpu, cpu, int_on;
109 u64 cur_ints; 109 u64 cur_ints;
110 struct irq_desc *desc = irq_desc + irq;
111 unsigned long flags; 110 unsigned long flags;
112 111
113 i = cpumask_first(mask); 112 i = cpumask_first(mask);
@@ -121,8 +120,7 @@ static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
121 cpu = cpu_logical_map(i); 120 cpu = cpu_logical_map(i);
122 121
123 /* Protect against other affinity changers and IMR manipulation */ 122 /* Protect against other affinity changers and IMR manipulation */
124 spin_lock_irqsave(&desc->lock, flags); 123 spin_lock_irqsave(&sb1250_imr_lock, flags);
125 spin_lock(&sb1250_imr_lock);
126 124
127 /* Swizzle each CPU's IMR (but leave the IP selection alone) */ 125 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
128 old_cpu = sb1250_irq_owner[irq]; 126 old_cpu = sb1250_irq_owner[irq];
@@ -144,8 +142,7 @@ static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
144 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + 142 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
145 R_IMR_INTERRUPT_MASK)); 143 R_IMR_INTERRUPT_MASK));
146 } 144 }
147 spin_unlock(&sb1250_imr_lock); 145 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
148 spin_unlock_irqrestore(&desc->lock, flags);
149} 146}
150#endif 147#endif
151 148
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
index 914e93c62639..1093549df1a8 100644
--- a/arch/mips/txx9/generic/setup_tx4927.c
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -88,7 +88,7 @@ void __init tx4927_setup(void)
88{ 88{
89 int i; 89 int i;
90 __u32 divmode; 90 __u32 divmode;
91 int cpuclk = 0; 91 unsigned int cpuclk = 0;
92 u64 ccfg; 92 u64 ccfg;
93 93
94 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE, 94 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index f0844f891f0b..3925219b8973 100644
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -93,7 +93,7 @@ void __init tx4938_setup(void)
93{ 93{
94 int i; 94 int i;
95 __u32 divmode; 95 __u32 divmode;
96 int cpuclk = 0; 96 unsigned int cpuclk = 0;
97 u64 ccfg; 97 u64 ccfg;
98 98
99 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE, 99 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
index 7a25b573e9b0..c2bf150c8838 100644
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -114,7 +114,7 @@ void __init tx4939_setup(void)
114 int i; 114 int i;
115 __u32 divmode; 115 __u32 divmode;
116 __u64 pcfg; 116 __u64 pcfg;
117 int cpuclk = 0; 117 unsigned int cpuclk = 0;
118 118
119 txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE, 119 txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
120 TX4939_REG_SIZE); 120 TX4939_REG_SIZE);
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 011e1e332f47..4199c6fd4d1d 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -536,7 +536,7 @@ static void __init rbtx4939_setup(void)
536} 536}
537 537
538struct txx9_board_vec rbtx4939_vec __initdata = { 538struct txx9_board_vec rbtx4939_vec __initdata = {
539 .system = "Tothiba RBTX4939", 539 .system = "Toshiba RBTX4939",
540 .prom_init = rbtx4939_prom_init, 540 .prom_init = rbtx4939_prom_init,
541 .mem_setup = rbtx4939_setup, 541 .mem_setup = rbtx4939_setup,
542 .irq_setup = rbtx4939_irq_setup, 542 .irq_setup = rbtx4939_irq_setup,
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 22:41:26 -0400