diff options
Diffstat (limited to 'arch/mips')
27 files changed, 63 insertions, 33 deletions
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c index d0af08bdbb4e..269b22b34313 100644 --- a/arch/mips/dec/ioasic-irq.c +++ b/arch/mips/dec/ioasic-irq.c | |||
@@ -103,9 +103,11 @@ void __init init_ioasic_irqs(int base) | |||
103 | fast_iob(); | 103 | fast_iob(); |
104 | 104 | ||
105 | for (i = base; i < base + IO_INR_DMA; i++) | 105 | for (i = base; i < base + IO_INR_DMA; i++) |
106 | set_irq_chip(i, &ioasic_irq_type); | 106 | set_irq_chip_and_handler(i, &ioasic_irq_type, |
107 | handle_level_irq); | ||
107 | for (; i < base + IO_IRQ_LINES; i++) | 108 | for (; i < base + IO_IRQ_LINES; i++) |
108 | set_irq_chip(i, &ioasic_dma_irq_type); | 109 | set_irq_chip_and_handler(i, &ioasic_dma_irq_type, |
110 | handle_level_irq); | ||
109 | 111 | ||
110 | ioasic_irq_base = base; | 112 | ioasic_irq_base = base; |
111 | } | 113 | } |
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c index c761d97787ec..5a9be4c93584 100644 --- a/arch/mips/dec/kn02-irq.c +++ b/arch/mips/dec/kn02-irq.c | |||
@@ -85,7 +85,7 @@ void __init init_kn02_irqs(int base) | |||
85 | iob(); | 85 | iob(); |
86 | 86 | ||
87 | for (i = base; i < base + KN02_IRQ_LINES; i++) | 87 | for (i = base; i < base + KN02_IRQ_LINES; i++) |
88 | set_irq_chip(i, &kn02_irq_type); | 88 | set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq); |
89 | 89 | ||
90 | kn02_irq_base = base; | 90 | kn02_irq_base = base; |
91 | } | 91 | } |
diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c index bf1b83ba925e..59b98299c896 100644 --- a/arch/mips/emma2rh/common/irq_emma2rh.c +++ b/arch/mips/emma2rh/common/irq_emma2rh.c | |||
@@ -76,7 +76,8 @@ void emma2rh_irq_init(u32 irq_base) | |||
76 | u32 i; | 76 | u32 i; |
77 | 77 | ||
78 | for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) | 78 | for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) |
79 | set_irq_chip(i, &emma2rh_irq_controller); | 79 | set_irq_chip_and_handler(i, &emma2rh_irq_controller, |
80 | handle_level_irq); | ||
80 | 81 | ||
81 | emma2rh_irq_base = irq_base; | 82 | emma2rh_irq_base = irq_base; |
82 | } | 83 | } |
diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c index 8e5f08a4245d..3ac4e405ecdc 100644 --- a/arch/mips/emma2rh/markeins/irq_markeins.c +++ b/arch/mips/emma2rh/markeins/irq_markeins.c | |||
@@ -68,7 +68,8 @@ void emma2rh_sw_irq_init(u32 irq_base) | |||
68 | u32 i; | 68 | u32 i; |
69 | 69 | ||
70 | for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) | 70 | for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) |
71 | set_irq_chip(i, &emma2rh_sw_irq_controller); | 71 | set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller, |
72 | handle_level_irq); | ||
72 | 73 | ||
73 | emma2rh_sw_irq_base = irq_base; | 74 | emma2rh_sw_irq_base = irq_base; |
74 | } | 75 | } |
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 4bbb6cb08d6e..5c4f50cdf157 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c | |||
@@ -59,7 +59,7 @@ void __init init_r4030_ints(void) | |||
59 | int i; | 59 | int i; |
60 | 60 | ||
61 | for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) | 61 | for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) |
62 | set_irq_chip(i, &r4030_irq_type); | 62 | set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq); |
63 | 63 | ||
64 | r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); | 64 | r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); |
65 | r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ | 65 | r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ |
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index e1880b27381b..bcaad6696082 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
@@ -117,6 +117,7 @@ struct irq_chip msc_levelirq_type = { | |||
117 | .mask = mask_msc_irq, | 117 | .mask = mask_msc_irq, |
118 | .mask_ack = level_mask_and_ack_msc_irq, | 118 | .mask_ack = level_mask_and_ack_msc_irq, |
119 | .unmask = unmask_msc_irq, | 119 | .unmask = unmask_msc_irq, |
120 | .eoi = unmask_msc_irq, | ||
120 | .end = end_msc_irq, | 121 | .end = end_msc_irq, |
121 | }; | 122 | }; |
122 | 123 | ||
@@ -126,6 +127,7 @@ struct irq_chip msc_edgeirq_type = { | |||
126 | .mask = mask_msc_irq, | 127 | .mask = mask_msc_irq, |
127 | .mask_ack = edge_mask_and_ack_msc_irq, | 128 | .mask_ack = edge_mask_and_ack_msc_irq, |
128 | .unmask = unmask_msc_irq, | 129 | .unmask = unmask_msc_irq, |
130 | .eoi = unmask_msc_irq, | ||
129 | .end = end_msc_irq, | 131 | .end = end_msc_irq, |
130 | }; | 132 | }; |
131 | 133 | ||
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c index 5012b9df1b5a..6cfb31cafde2 100644 --- a/arch/mips/kernel/irq-mv6434x.c +++ b/arch/mips/kernel/irq-mv6434x.c | |||
@@ -114,7 +114,8 @@ void __init mv64340_irq_init(unsigned int base) | |||
114 | int i; | 114 | int i; |
115 | 115 | ||
116 | for (i = base; i < base + 64; i++) | 116 | for (i = base; i < base + 64; i++) |
117 | set_irq_chip(i, &mv64340_irq_type); | 117 | set_irq_chip_and_handler(i, &mv64340_irq_type, |
118 | handle_level_irq); | ||
118 | 119 | ||
119 | irq_base = base; | 120 | irq_base = base; |
120 | } | 121 | } |
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index 6a297e3b8899..ddcc2a5f8a06 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c | |||
@@ -51,7 +51,8 @@ void __init rm7k_cpu_irq_init(int base) | |||
51 | clear_c0_intcontrol(0x00000f00); /* Mask all */ | 51 | clear_c0_intcontrol(0x00000f00); /* Mask all */ |
52 | 52 | ||
53 | for (i = base; i < base + 4; i++) | 53 | for (i = base; i < base + 4; i++) |
54 | set_irq_chip(i, &rm7k_irq_controller); | 54 | set_irq_chip_and_handler(i, &rm7k_irq_controller, |
55 | handle_level_irq); | ||
55 | 56 | ||
56 | irq_base = base; | 57 | irq_base = base; |
57 | } | 58 | } |
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index 977538445cf3..ba6440c88abd 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c | |||
@@ -117,10 +117,12 @@ void __init rm9k_cpu_irq_init(int base) | |||
117 | clear_c0_intcontrol(0x0000f000); /* Mask all */ | 117 | clear_c0_intcontrol(0x0000f000); /* Mask all */ |
118 | 118 | ||
119 | for (i = base; i < base + 4; i++) | 119 | for (i = base; i < base + 4; i++) |
120 | set_irq_chip(i, &rm9k_irq_controller); | 120 | set_irq_chip_and_handler(i, &rm9k_irq_controller, |
121 | handle_level_irq); | ||
121 | 122 | ||
122 | rm9000_perfcount_irq = base + 1; | 123 | rm9000_perfcount_irq = base + 1; |
123 | set_irq_chip(rm9000_perfcount_irq, &rm9k_perfcounter_irq); | 124 | set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, |
125 | handle_level_irq); | ||
124 | 126 | ||
125 | irq_base = base; | 127 | irq_base = base; |
126 | } | 128 | } |
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 3b7cfa407e87..be5ac23d3812 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c | |||
@@ -62,6 +62,7 @@ static struct irq_chip mips_cpu_irq_controller = { | |||
62 | .mask = mask_mips_irq, | 62 | .mask = mask_mips_irq, |
63 | .mask_ack = mask_mips_irq, | 63 | .mask_ack = mask_mips_irq, |
64 | .unmask = unmask_mips_irq, | 64 | .unmask = unmask_mips_irq, |
65 | .eoi = unmask_mips_irq, | ||
65 | .end = mips_cpu_irq_end, | 66 | .end = mips_cpu_irq_end, |
66 | }; | 67 | }; |
67 | 68 | ||
@@ -104,6 +105,7 @@ static struct irq_chip mips_mt_cpu_irq_controller = { | |||
104 | .mask = mask_mips_mt_irq, | 105 | .mask = mask_mips_mt_irq, |
105 | .mask_ack = mips_mt_cpu_irq_ack, | 106 | .mask_ack = mips_mt_cpu_irq_ack, |
106 | .unmask = unmask_mips_mt_irq, | 107 | .unmask = unmask_mips_mt_irq, |
108 | .eoi = unmask_mips_mt_irq, | ||
107 | .end = mips_mt_cpu_irq_end, | 109 | .end = mips_mt_cpu_irq_end, |
108 | }; | 110 | }; |
109 | 111 | ||
@@ -124,7 +126,8 @@ void __init mips_cpu_irq_init(int irq_base) | |||
124 | set_irq_chip(i, &mips_mt_cpu_irq_controller); | 126 | set_irq_chip(i, &mips_mt_cpu_irq_controller); |
125 | 127 | ||
126 | for (i = irq_base + 2; i < irq_base + 8; i++) | 128 | for (i = irq_base + 2; i < irq_base + 8; i++) |
127 | set_irq_chip(i, &mips_cpu_irq_controller); | 129 | set_irq_chip_and_handler(i, &mips_cpu_irq_controller, |
130 | handle_level_irq); | ||
128 | 131 | ||
129 | mips_cpu_irq_base = irq_base; | 132 | mips_cpu_irq_base = irq_base; |
130 | } | 133 | } |
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 2ac19a6cbf68..1ee689c0e0c9 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c | |||
@@ -278,7 +278,9 @@ void __init plat_prepare_cpus(unsigned int max_cpus) | |||
278 | 278 | ||
279 | /* need to mark IPI's as IRQ_PER_CPU */ | 279 | /* need to mark IPI's as IRQ_PER_CPU */ |
280 | irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU; | 280 | irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU; |
281 | set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); | ||
281 | irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU; | 282 | irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU; |
283 | set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); | ||
282 | } | 284 | } |
283 | 285 | ||
284 | /* | 286 | /* |
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 3b78caf112f5..802febed7df5 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c | |||
@@ -1009,6 +1009,7 @@ void setup_cross_vpe_interrupts(void) | |||
1009 | setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); | 1009 | setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); |
1010 | 1010 | ||
1011 | irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU; | 1011 | irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU; |
1012 | set_irq_handler(cpu_ipi_irq, handle_percpu_irq); | ||
1012 | } | 1013 | } |
1013 | 1014 | ||
1014 | /* | 1015 | /* |
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c index cac82afe5eb4..4a84a7beac53 100644 --- a/arch/mips/lasat/interrupt.c +++ b/arch/mips/lasat/interrupt.c | |||
@@ -133,5 +133,5 @@ void __init arch_init_irq(void) | |||
133 | } | 133 | } |
134 | 134 | ||
135 | for (i = 0; i <= LASATINT_END; i++) | 135 | for (i = 0; i <= LASATINT_END; i++) |
136 | set_irq_chip(i, &lasat_irq_type); | 136 | set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq); |
137 | } | 137 | } |
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index 7c710040d3f1..43dba6ce6603 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c | |||
@@ -74,6 +74,7 @@ static struct irq_chip atlas_irq_type = { | |||
74 | .mask = disable_atlas_irq, | 74 | .mask = disable_atlas_irq, |
75 | .mask_ack = disable_atlas_irq, | 75 | .mask_ack = disable_atlas_irq, |
76 | .unmask = enable_atlas_irq, | 76 | .unmask = enable_atlas_irq, |
77 | .eoi = enable_atlas_irq, | ||
77 | .end = end_atlas_irq, | 78 | .end = end_atlas_irq, |
78 | }; | 79 | }; |
79 | 80 | ||
@@ -207,7 +208,7 @@ static inline void init_atlas_irqs (int base) | |||
207 | atlas_hw0_icregs->intrsten = 0xffffffff; | 208 | atlas_hw0_icregs->intrsten = 0xffffffff; |
208 | 209 | ||
209 | for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) | 210 | for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) |
210 | set_irq_chip(i, &atlas_irq_type); | 211 | set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq); |
211 | } | 212 | } |
212 | 213 | ||
213 | static struct irqaction atlasirq = { | 214 | static struct irqaction atlasirq = { |
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index d817c60c5ca5..e4604c73f02e 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c | |||
@@ -288,6 +288,7 @@ void __init plat_timer_setup(struct irqaction *irq) | |||
288 | The effect is that the int remains disabled on the second cpu. | 288 | The effect is that the int remains disabled on the second cpu. |
289 | Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ | 289 | Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ |
290 | irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; | 290 | irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; |
291 | set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); | ||
291 | #endif | 292 | #endif |
292 | 293 | ||
293 | /* to generate the first timer interrupt */ | 294 | /* to generate the first timer interrupt */ |
diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c index 24a4ed00cc0a..f2d998d2c169 100644 --- a/arch/mips/mips-boards/sim/sim_time.c +++ b/arch/mips/mips-boards/sim/sim_time.c | |||
@@ -203,7 +203,8 @@ void __init plat_timer_setup(struct irqaction *irq) | |||
203 | on seperate cpu's the first one tries to handle the second interrupt. | 203 | on seperate cpu's the first one tries to handle the second interrupt. |
204 | The effect is that the int remains disabled on the second cpu. | 204 | The effect is that the int remains disabled on the second cpu. |
205 | Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ | 205 | Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ |
206 | irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; | 206 | irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU; |
207 | set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); | ||
207 | #endif | 208 | #endif |
208 | 209 | ||
209 | /* to generate the first timer interrupt */ | 210 | /* to generate the first timer interrupt */ |
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c index 7723f0998944..e5a4a0a8a7f0 100644 --- a/arch/mips/momentum/ocelot_c/cpci-irq.c +++ b/arch/mips/momentum/ocelot_c/cpci-irq.c | |||
@@ -106,5 +106,5 @@ void cpci_irq_init(void) | |||
106 | int i; | 106 | int i; |
107 | 107 | ||
108 | for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) | 108 | for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) |
109 | set_irq_chip(i, &cpci_irq_type); | 109 | set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq); |
110 | } | 110 | } |
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c index 72faf81b36cc..0029f0008dea 100644 --- a/arch/mips/momentum/ocelot_c/uart-irq.c +++ b/arch/mips/momentum/ocelot_c/uart-irq.c | |||
@@ -96,6 +96,6 @@ struct irq_chip uart_irq_type = { | |||
96 | 96 | ||
97 | void uart_irq_init(void) | 97 | void uart_irq_init(void) |
98 | { | 98 | { |
99 | set_irq_chip(80, &uart_irq_type); | 99 | set_irq_chip_and_handler(80, &uart_irq_type, handle_level_irq); |
100 | set_irq_chip(81, &uart_irq_type); | 100 | set_irq_chip_and_handler(81, &uart_irq_type, handle_level_irq); |
101 | } | 101 | } |
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c index e4bf494dd435..0dc23930edbd 100644 --- a/arch/mips/philips/pnx8550/common/int.c +++ b/arch/mips/philips/pnx8550/common/int.c | |||
@@ -192,7 +192,7 @@ void __init arch_init_irq(void) | |||
192 | int configPR; | 192 | int configPR; |
193 | 193 | ||
194 | for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { | 194 | for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { |
195 | set_irq_chip(i, &level_irq_type); | 195 | set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); |
196 | mask_irq(i); /* mask the irq just in case */ | 196 | mask_irq(i); /* mask the irq just in case */ |
197 | } | 197 | } |
198 | 198 | ||
@@ -229,7 +229,7 @@ void __init arch_init_irq(void) | |||
229 | /* mask/priority is still 0 so we will not get any | 229 | /* mask/priority is still 0 so we will not get any |
230 | * interrupts until it is unmasked */ | 230 | * interrupts until it is unmasked */ |
231 | 231 | ||
232 | set_irq_chip(i, &level_irq_type); | 232 | set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); |
233 | } | 233 | } |
234 | 234 | ||
235 | /* Priority level 0 */ | 235 | /* Priority level 0 */ |
@@ -238,19 +238,21 @@ void __init arch_init_irq(void) | |||
238 | /* Set int vector table address */ | 238 | /* Set int vector table address */ |
239 | PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; | 239 | PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; |
240 | 240 | ||
241 | set_irq_chip(MIPS_CPU_GIC_IRQ, &level_irq_type); | 241 | set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type, |
242 | handle_level_irq); | ||
242 | setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); | 243 | setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); |
243 | 244 | ||
244 | /* init of Timer interrupts */ | 245 | /* init of Timer interrupts */ |
245 | for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) | 246 | for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) |
246 | set_irq_chip(i, &level_irq_type); | 247 | set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq); |
247 | 248 | ||
248 | /* Stop Timer 1-3 */ | 249 | /* Stop Timer 1-3 */ |
249 | configPR = read_c0_config7(); | 250 | configPR = read_c0_config7(); |
250 | configPR |= 0x00000038; | 251 | configPR |= 0x00000038; |
251 | write_c0_config7(configPR); | 252 | write_c0_config7(configPR); |
252 | 253 | ||
253 | set_irq_chip(MIPS_CPU_TIMER_IRQ, &level_irq_type); | 254 | set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type, |
255 | handle_level_irq); | ||
254 | setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); | 256 | setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); |
255 | } | 257 | } |
256 | 258 | ||
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index 8e2074b4ce43..c7b138053159 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c | |||
@@ -358,7 +358,7 @@ void __init arch_init_irq(void) | |||
358 | else | 358 | else |
359 | handler = &ip22_local3_irq_type; | 359 | handler = &ip22_local3_irq_type; |
360 | 360 | ||
361 | set_irq_chip(i, handler); | 361 | set_irq_chip_and_handler(i, handler, handle_level_irq); |
362 | } | 362 | } |
363 | 363 | ||
364 | /* vector handler. this register the IRQ as non-sharable */ | 364 | /* vector handler. this register the IRQ as non-sharable */ |
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c index 824320281a3a..5f8835b4e84a 100644 --- a/arch/mips/sgi-ip27/ip27-irq.c +++ b/arch/mips/sgi-ip27/ip27-irq.c | |||
@@ -352,7 +352,7 @@ static struct irq_chip bridge_irq_type = { | |||
352 | 352 | ||
353 | void __devinit register_bridge_irq(unsigned int irq) | 353 | void __devinit register_bridge_irq(unsigned int irq) |
354 | { | 354 | { |
355 | set_irq_chip(irq, &bridge_irq_type); | 355 | set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq); |
356 | } | 356 | } |
357 | 357 | ||
358 | int __devinit request_bridge_irq(struct bridge_controller *bc) | 358 | int __devinit request_bridge_irq(struct bridge_controller *bc) |
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 86ba7fc10c38..e5441c3a0b07 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c | |||
@@ -190,6 +190,7 @@ static struct irq_chip rt_irq_type = { | |||
190 | .mask = disable_rt_irq, | 190 | .mask = disable_rt_irq, |
191 | .mask_ack = disable_rt_irq, | 191 | .mask_ack = disable_rt_irq, |
192 | .unmask = enable_rt_irq, | 192 | .unmask = enable_rt_irq, |
193 | .eoi = enable_rt_irq, | ||
193 | .end = end_rt_irq, | 194 | .end = end_rt_irq, |
194 | }; | 195 | }; |
195 | 196 | ||
@@ -207,7 +208,7 @@ void __init plat_timer_setup(struct irqaction *irq) | |||
207 | if (irqno < 0) | 208 | if (irqno < 0) |
208 | panic("Can't allocate interrupt number for timer interrupt"); | 209 | panic("Can't allocate interrupt number for timer interrupt"); |
209 | 210 | ||
210 | set_irq_chip(irqno, &rt_irq_type); | 211 | set_irq_chip_and_handler(irqno, &rt_irq_type, handle_percpu_irq); |
211 | 212 | ||
212 | /* over-write the handler, we use our own way */ | 213 | /* over-write the handler, we use our own way */ |
213 | irq->handler = no_action; | 214 | irq->handler = no_action; |
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c index 2c57ced5c68c..21873de49aa8 100644 --- a/arch/mips/tx4927/common/tx4927_irq.c +++ b/arch/mips/tx4927/common/tx4927_irq.c | |||
@@ -196,7 +196,8 @@ static void __init tx4927_irq_cp0_init(void) | |||
196 | TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END); | 196 | TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END); |
197 | 197 | ||
198 | for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) | 198 | for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) |
199 | set_irq_chip(i, &tx4927_irq_cp0_type); | 199 | set_irq_chip_and_handler(i, &tx4927_irq_cp0_type, |
200 | handle_level_irq); | ||
200 | } | 201 | } |
201 | 202 | ||
202 | static void tx4927_irq_cp0_enable(unsigned int irq) | 203 | static void tx4927_irq_cp0_enable(unsigned int irq) |
@@ -350,7 +351,8 @@ static void __init tx4927_irq_pic_init(void) | |||
350 | TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END); | 351 | TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END); |
351 | 352 | ||
352 | for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) | 353 | for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) |
353 | set_irq_chip(i, &tx4927_irq_pic_type); | 354 | set_irq_chip_and_handler(i, &tx4927_irq_pic_type, |
355 | handle_level_irq); | ||
354 | 356 | ||
355 | setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); | 357 | setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); |
356 | 358 | ||
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 1fdace89ae6d..34cdb2a240e9 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | |||
@@ -342,7 +342,8 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void) | |||
342 | 342 | ||
343 | for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; | 343 | for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; |
344 | i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) | 344 | i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) |
345 | set_irq_chip(i, &toshiba_rbtx4927_irq_ioc_type); | 345 | set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type, |
346 | handle_level_irq); | ||
346 | 347 | ||
347 | setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, | 348 | setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, |
348 | &toshiba_rbtx4927_irq_ioc_action); | 349 | &toshiba_rbtx4927_irq_ioc_action); |
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c index 19c9ee9e3d0c..42e127683ae9 100644 --- a/arch/mips/tx4938/common/irq.c +++ b/arch/mips/tx4938/common/irq.c | |||
@@ -88,7 +88,8 @@ tx4938_irq_cp0_init(void) | |||
88 | int i; | 88 | int i; |
89 | 89 | ||
90 | for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) | 90 | for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) |
91 | set_irq_chip(i, &tx4938_irq_cp0_type); | 91 | set_irq_chip_and_handler(i, &tx4938_irq_cp0_type, |
92 | handle_level_irq); | ||
92 | } | 93 | } |
93 | 94 | ||
94 | static void | 95 | static void |
@@ -245,7 +246,8 @@ tx4938_irq_pic_init(void) | |||
245 | int i; | 246 | int i; |
246 | 247 | ||
247 | for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) | 248 | for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) |
248 | set_irq_chip(i, &tx4938_irq_pic_type); | 249 | set_irq_chip_and_handler(i, &tx4938_irq_pic_type, |
250 | handle_level_irq); | ||
249 | 251 | ||
250 | setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); | 252 | setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); |
251 | 253 | ||
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c index 2735ffe9ec28..8c87a35f3068 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c | |||
@@ -136,7 +136,8 @@ toshiba_rbtx4938_irq_ioc_init(void) | |||
136 | 136 | ||
137 | for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; | 137 | for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; |
138 | i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) | 138 | i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) |
139 | set_irq_chip(i, &toshiba_rbtx4938_irq_ioc_type); | 139 | set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type, |
140 | handle_level_irq); | ||
140 | 141 | ||
141 | setup_irq(RBTX4938_IRQ_IOCINT, | 142 | setup_irq(RBTX4938_IRQ_IOCINT, |
142 | &toshiba_rbtx4938_irq_ioc_action); | 143 | &toshiba_rbtx4938_irq_ioc_action); |
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index 33d70a6547ad..54b92a74c7ac 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c | |||
@@ -701,10 +701,12 @@ static int __init vr41xx_icu_init(void) | |||
701 | icu2_write(MGIUINTHREG, 0xffff); | 701 | icu2_write(MGIUINTHREG, 0xffff); |
702 | 702 | ||
703 | for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) | 703 | for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) |
704 | set_irq_chip(i, &sysint1_irq_type); | 704 | set_irq_chip_and_handler(i, &sysint1_irq_type, |
705 | handle_level_irq); | ||
705 | 706 | ||
706 | for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) | 707 | for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) |
707 | set_irq_chip(i, &sysint2_irq_type); | 708 | set_irq_chip_and_handler(i, &sysint2_irq_type, |
709 | handle_level_irq); | ||
708 | 710 | ||
709 | cascade_irq(INT0_IRQ, icu_get_irq); | 711 | cascade_irq(INT0_IRQ, icu_get_irq); |
710 | cascade_irq(INT1_IRQ, icu_get_irq); | 712 | cascade_irq(INT1_IRQ, icu_get_irq); |