16 files changed, 138 insertions, 58 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4da736e25333..49896a2a1d72 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1886,6 +1886,15 @@ config STACKTRACE_SUPPORT
 
 source "init/Kconfig"
 
+config PROBE_INITRD_HEADER
+        bool "Probe initrd header created by addinitrd"
+        depends on BLK_DEV_INITRD
+        help
+          Probe initrd header at the last page of kernel image.
+          Say Y here if you are using arch/mips/boot/addinitrd.c to
+          add initrd or initramfs image to the kernel image.
+          Otherwise, say N.
+
 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
 
 config HW_HAS_EISA
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 335a6ae3d594..11c92dc53791 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -45,18 +45,7 @@ static void r39xx_wait(void)
         local_irq_enable();
 }
 
-/*
- * There is a race when WAIT instruction executed with interrupt
- * enabled.
- * But it is implementation-dependent wheter the pipelie restarts when
- * a non-enabled interrupt is requested.
- */
-static void r4k_wait(void)
-{
-        __asm__("       .set    mips3                   \n"
-                "       wait                            \n"
-                "       .set    mips0                   \n");
-}
+extern void r4k_wait(void);
 
 /*
  * This variant is preferable as it allows testing need_resched and going to
@@ -128,7 +117,7 @@ static int __init wait_disable(char *s)
 
 __setup("nowait", wait_disable);
 
-static inline void check_wait(void)
+void __init check_wait(void)
 {
         struct cpuinfo_mips *c = &current_cpu_data;
 
@@ -242,7 +231,6 @@ static inline void check_errata(void)
 
 void __init check_bugs32(void)
 {
-        check_wait();
         check_errata();
 }
 
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index c6ada98ee042..f886dd7f708e 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -20,6 +20,7 @@
 #include <asm/stackframe.h>
 #include <asm/war.h>
 #include <asm/page.h>
+#include <asm/thread_info.h>
 
 #define PANIC_PIC(msg)                                  \
                 .set push;                              \
@@ -126,7 +127,42 @@ handle_vcei:
 
         __FINIT
 
+        .align  5       /* 32 byte rollback region */
+LEAF(r4k_wait)
+        .set    push
+        .set    noreorder
+        /* start of rollback region */
+        LONG_L  t0, TI_FLAGS($28)
+        nop
+        andi    t0, _TIF_NEED_RESCHED
+        bnez    t0, 1f
+         nop
+        nop
+        nop
+        .set    mips3
+        wait
+        /* end of rollback region (the region size must be power of two) */
+        .set    pop
+1:
+        jr      ra
+        END(r4k_wait)
+
+        .macro  BUILD_ROLLBACK_PROLOGUE handler
+        FEXPORT(rollback_\handler)
+        .set    push
+        .set    noat
+        MFC0    k0, CP0_EPC
+        PTR_LA  k1, r4k_wait
+        ori     k0, 0x1f        /* 32 byte rollback region */
+        xori    k0, 0x1f
+        bne     k0, k1, 9f
+        MTC0    k0, CP0_EPC
+9:
+        .set pop
+        .endm
+
         .align  5
+BUILD_ROLLBACK_PROLOGUE handle_int
 NESTED(handle_int, PT_SIZE, sp)
 #ifdef CONFIG_TRACE_IRQFLAGS
         /*
@@ -201,6 +237,7 @@ NESTED(except_vec_ejtag_debug, 0, sp)
  * This prototype is copied to ebase + n*IntCtl.VS and patched
  * to invoke the handler
  */
+BUILD_ROLLBACK_PROLOGUE except_vec_vi
 NESTED(except_vec_vi, 0, sp)
         SAVE_SOME
         SAVE_AT
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index b16facd9ea8e..ce7684335a41 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -148,6 +148,8 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
         clear_tsk_thread_flag(p, TIF_USEDFPU);
 
 #ifdef CONFIG_MIPS_MT_FPAFF
+        clear_tsk_thread_flag(p, TIF_FPUBOUND);
+
         /*
          * FPU affinity support is cleaner if we track the
          * user-visible CPU affinity from the very beginning.
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 2aae76bce293..16f8edfe5cdc 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -160,30 +160,33 @@ early_param("rd_size", rd_size_early);
 static unsigned long __init init_initrd(void)
 {
         unsigned long end;
-        u32 *initrd_header;
 
         /*
          * Board specific code or command line parser should have
          * already set up initrd_start and initrd_end. In these cases
          * perfom sanity checks and use them if all looks good.
          */
-        if (initrd_start && initrd_end > initrd_start)
-                goto sanitize;
+        if (!initrd_start || initrd_end <= initrd_start) {
+#ifdef CONFIG_PROBE_INITRD_HEADER
+                u32 *initrd_header;
 
-        /*
-         * See if initrd has been added to the kernel image by
-         * arch/mips/boot/addinitrd.c. In that case a header is
-         * prepended to initrd and is made up by 8 bytes. The fisrt
-         * word is a magic number and the second one is the size of
-         * initrd.  Initrd start must be page aligned in any cases.
-         */
-        initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8;
-        if (initrd_header[0] != 0x494E5244)
+                /*
+                 * See if initrd has been added to the kernel image by
+                 * arch/mips/boot/addinitrd.c. In that case a header is
+                 * prepended to initrd and is made up by 8 bytes. The first
+                 * word is a magic number and the second one is the size of
+                 * initrd.  Initrd start must be page aligned in any cases.
+                 */
+                initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8;
+                if (initrd_header[0] != 0x494E5244)
+                        goto disable;
+                initrd_start = (unsigned long)(initrd_header + 2);
+                initrd_end = initrd_start + initrd_header[1];
+#else
                 goto disable;
-        initrd_start = (unsigned long)(initrd_header + 2);
-        initrd_end = initrd_start + initrd_header[1];
+#endif
+        }
 
-sanitize:
         if (initrd_start & ~PAGE_MASK) {
                 pr_err("initrd start must be page aligned\n");
                 goto disable;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 426cced1e9dc..5fd0cd020af5 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -46,6 +46,9 @@
 #include <asm/types.h>
 #include <asm/stacktrace.h>
 
+extern void check_wait(void);
+extern asmlinkage void r4k_wait(void);
+extern asmlinkage void rollback_handle_int(void);
 extern asmlinkage void handle_int(void);
 extern asmlinkage void handle_tlbm(void);
 extern asmlinkage void handle_tlbl(void);
@@ -373,8 +376,8 @@ void __noreturn die(const char * str, const struct pt_regs * regs)
         do_exit(SIGSEGV);
 }
 
-extern const struct exception_table_entry __start___dbe_table[];
-extern const struct exception_table_entry __stop___dbe_table[];
+extern struct exception_table_entry __start___dbe_table[];
+extern struct exception_table_entry __stop___dbe_table[];
 
 __asm__(
 "       .section        __dbe_table, \"a\"\n"
@@ -1200,7 +1203,7 @@ void *set_except_vector(int n, void *addr)
         if (n == 0 && cpu_has_divec) {
                 *(u32 *)(ebase + 0x200) = 0x08000000 |
                                           (0x03ffffff & (handler >> 2));
-                flush_icache_range(ebase + 0x200, ebase + 0x204);
+                local_flush_icache_range(ebase + 0x200, ebase + 0x204);
         }
         return (void *)old_handler;
 }
@@ -1251,6 +1254,9 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
 
                 extern char except_vec_vi, except_vec_vi_lui;
                 extern char except_vec_vi_ori, except_vec_vi_end;
+                extern char rollback_except_vec_vi;
+                char *vec_start = (cpu_wait == r4k_wait) ?
+                        &rollback_except_vec_vi : &except_vec_vi;
 #ifdef CONFIG_MIPS_MT_SMTC
                 /*
                  * We need to provide the SMTC vectored interrupt handler
@@ -1258,11 +1264,11 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
                  * Status.IM bit to be masked before going there.
                  */
                 extern char except_vec_vi_mori;
-                const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
+                const int mori_offset = &except_vec_vi_mori - vec_start;
 #endif /* CONFIG_MIPS_MT_SMTC */
-                const int handler_len = &except_vec_vi_end - &except_vec_vi;
-                const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
-                const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
+                const int handler_len = &except_vec_vi_end - vec_start;
+                const int lui_offset = &except_vec_vi_lui - vec_start;
+                const int ori_offset = &except_vec_vi_ori - vec_start;
 
                 if (handler_len > VECTORSPACING) {
                         /*
@@ -1272,7 +1278,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
                         panic("VECTORSPACING too small");
                 }
 
-                memcpy(b, &except_vec_vi, handler_len);
+                memcpy(b, vec_start, handler_len);
 #ifdef CONFIG_MIPS_MT_SMTC
                 BUG_ON(n > 7);  /* Vector index %d exceeds SMTC maximum. */
 
@@ -1283,7 +1289,8 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
                 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
                 w = (u32 *)(b + ori_offset);
                 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
-                flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
+                local_flush_icache_range((unsigned long)b,
+                                         (unsigned long)(b+handler_len));
         }
         else {
                 /*
@@ -1295,7 +1302,8 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
                 w = (u32 *)b;
                 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
                 *w = 0;
-                flush_icache_range((unsigned long)b, (unsigned long)(b+8));
+                local_flush_icache_range((unsigned long)b,
+                                         (unsigned long)(b+8));
         }
 
         return (void *)old_handler;
@@ -1515,7 +1523,7 @@ void __cpuinit per_cpu_trap_init(void)
 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
 {
         memcpy((void *)(ebase + offset), addr, size);
-        flush_icache_range(ebase + offset, ebase + offset + size);
+        local_flush_icache_range(ebase + offset, ebase + offset + size);
 }
 
 static char panic_null_cerr[] __cpuinitdata =
@@ -1552,6 +1560,10 @@ void __init trap_init(void)
         extern char except_vec3_generic, except_vec3_r4000;
         extern char except_vec4;
         unsigned long i;
+        int rollback;
+
+        check_wait();
+        rollback = (cpu_wait == r4k_wait);
 
 #if defined(CONFIG_KGDB)
         if (kgdb_early_setup)
@@ -1616,7 +1628,7 @@ void __init trap_init(void)
         if (board_be_init)
                 board_be_init();
 
-        set_except_vector(0, handle_int);
+        set_except_vector(0, rollback ? rollback_handle_int : handle_int);
         set_except_vector(1, handle_tlbm);
         set_except_vector(2, handle_tlbl);
         set_except_vector(3, handle_tlbs);
@@ -1680,6 +1692,8 @@ void __init trap_init(void)
         signal32_init();
 #endif
 
-        flush_icache_range(ebase, ebase + 0x400);
+        local_flush_icache_range(ebase, ebase + 0x400);
         flush_tlb_handlers();
+
+        sort_extable(__start___dbe_table, __stop___dbe_table);
 }
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index b5470ceb418b..afb119f35682 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -36,6 +36,7 @@ SECTIONS
                 SCHED_TEXT
                 LOCK_TEXT
                 KPROBES_TEXT
+                *(.text.*)
                 *(.fixup)
                 *(.gnu.warning)
         } :text = 0
diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 8d7784122c14..edac9892c51a 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -39,12 +39,14 @@
 #ifdef USE_DOUBLE
 
 #define LOAD   ld
+#define LOAD32 lwu
 #define ADD    daddu
 #define NBYTES 8
 
 #else
 
 #define LOAD   lw
+#define LOAD32 lw
 #define ADD    addu
 #define NBYTES 4
 
@@ -60,6 +62,14 @@
         ADD     sum, v1;                                        \
         .set    pop
 
+#define ADDC32(sum,reg)                                         \
+        .set    push;                                           \
+        .set    noat;                                           \
+        addu    sum, reg;                                       \
+        sltu    v1, sum, reg;                                   \
+        addu    sum, v1;                                        \
+        .set    pop
+
 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)    \
         LOAD    _t0, (offset + UNIT(0))(src);                   \
         LOAD    _t1, (offset + UNIT(1))(src);                   \
@@ -132,7 +142,7 @@ LEAF(csum_partial)
         beqz    t8, .Lqword_align
          andi   t8, src, 0x8
 
-        lw      t0, 0x00(src)
+        LOAD32  t0, 0x00(src)
         LONG_SUBU       a1, a1, 0x4
         ADDC(sum, t0)
         PTR_ADDU        src, src, 0x4
@@ -211,7 +221,7 @@ LEAF(csum_partial)
         LONG_SRL        t8, t8, 0x2
 
 .Lend_words:
-        lw      t0, (src)
+        LOAD32  t0, (src)
         LONG_SUBU       t8, t8, 0x1
         ADDC(sum, t0)
         .set    reorder                         /* DADDI_WAR */
@@ -230,6 +240,9 @@ LEAF(csum_partial)
         /* Still a full word to go  */
         ulw     t1, (src)
         PTR_ADDIU       src, 4
+#ifdef USE_DOUBLE
+        dsll    t1, t1, 32                      /* clear lower 32bit */
+#endif
         ADDC(sum, t1)
 
 1:      move    t1, zero
@@ -280,7 +293,7 @@ LEAF(csum_partial)
 1:
         .set    reorder
         /* Add the passed partial csum.  */
-        ADDC(sum, a2)
+        ADDC32(sum, a2)
         jr      ra
         .set    noreorder
         END(csum_partial)
@@ -681,7 +694,7 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
         .set    pop
 1:
         .set reorder
-        ADDC(sum, psum)
+        ADDC32(sum, psum)
         jr      ra
         .set noreorder
 
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 27a5b466c85c..5500c20c79ae 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -320,6 +320,7 @@ void __cpuinit r3k_cache_init(void)
         flush_cache_range = r3k_flush_cache_range;
         flush_cache_page = r3k_flush_cache_page;
         flush_icache_range = r3k_flush_icache_range;
+        local_flush_icache_range = r3k_flush_icache_range;
 
         flush_cache_sigtramp = r3k_flush_cache_sigtramp;
         local_flush_data_cache_page = local_r3k_flush_data_cache_page;
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 71df3390c07b..6e99665ae860 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -543,12 +543,8 @@ struct flush_icache_range_args {
         unsigned long end;
 };
 
-static inline void local_r4k_flush_icache_range(void *args)
+static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
 {
-        struct flush_icache_range_args *fir_args = args;
-        unsigned long start = fir_args->start;
-        unsigned long end = fir_args->end;
-
         if (!cpu_has_ic_fills_f_dc) {
                 if (end - start >= dcache_size) {
                         r4k_blast_dcache();
@@ -564,6 +560,15 @@ static inline void local_r4k_flush_icache_range(void *args)
                 protected_blast_icache_range(start, end);
 }
 
+static inline void local_r4k_flush_icache_range_ipi(void *args)
+{
+        struct flush_icache_range_args *fir_args = args;
+        unsigned long start = fir_args->start;
+        unsigned long end = fir_args->end;
+
+        local_r4k_flush_icache_range(start, end);
+}
+
 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 {
         struct flush_icache_range_args args;
@@ -571,7 +576,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
         args.start = start;
         args.end = end;
 
-        r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1);
+        r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args, 1);
         instruction_hazard();
 }
 
@@ -1375,6 +1380,7 @@ void __cpuinit r4k_cache_init(void)
         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
         flush_data_cache_page   = r4k_flush_data_cache_page;
         flush_icache_range      = r4k_flush_icache_range;
+        local_flush_icache_range        = local_r4k_flush_icache_range;
 
 #if defined(CONFIG_DMA_NONCOHERENT)
         if (coherentio) {
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index a9f7f1f5e9b4..f7c8f9ce39c1 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -362,6 +362,7 @@ void __cpuinit tx39_cache_init(void)
                 flush_cache_range       = (void *) tx39h_flush_icache_all;
                 flush_cache_page        = (void *) tx39h_flush_icache_all;
                 flush_icache_range      = (void *) tx39h_flush_icache_all;
+                local_flush_icache_range = (void *) tx39h_flush_icache_all;
 
                 flush_cache_sigtramp    = (void *) tx39h_flush_icache_all;
                 local_flush_data_cache_page     = (void *) tx39h_flush_icache_all;
@@ -390,6 +391,7 @@ void __cpuinit tx39_cache_init(void)
                 flush_cache_range = tx39_flush_cache_range;
                 flush_cache_page = tx39_flush_cache_page;
                 flush_icache_range = tx39_flush_icache_range;
+                local_flush_icache_range = tx39_flush_icache_range;
 
                 flush_cache_sigtramp = tx39_flush_cache_sigtramp;
                 local_flush_data_cache_page = local_tx39_flush_data_cache_page;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 034e8506f6ea..1eb7c71e3d6a 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -29,6 +29,7 @@ void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
 void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
         unsigned long pfn);
 void (*flush_icache_range)(unsigned long start, unsigned long end);
+void (*local_flush_icache_range)(unsigned long start, unsigned long end);
 
 void (*__flush_cache_vmap)(void);
 void (*__flush_cache_vunmap)(void);
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 76da73a5ab3c..979cf9197282 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1273,10 +1273,10 @@ void __cpuinit build_tlb_refill_handler(void)
 
 void __cpuinit flush_tlb_handlers(void)
 {
-        flush_icache_range((unsigned long)handle_tlbl,
+        local_flush_icache_range((unsigned long)handle_tlbl,
                            (unsigned long)handle_tlbl + sizeof(handle_tlbl));
-        flush_icache_range((unsigned long)handle_tlbs,
+        local_flush_icache_range((unsigned long)handle_tlbs,
                            (unsigned long)handle_tlbs + sizeof(handle_tlbs));
-        flush_icache_range((unsigned long)handle_tlbm,
+        local_flush_icache_range((unsigned long)handle_tlbm,
                            (unsigned long)handle_tlbm + sizeof(handle_tlbm));
 }
diff --git a/arch/mips/sgi-ip22/ip22-platform.c b/arch/mips/sgi-ip22/ip22-platform.c
index 60141235ec40..52486c4d2b01 100644
--- a/arch/mips/sgi-ip22/ip22-platform.c
+++ b/arch/mips/sgi-ip22/ip22-platform.c
@@ -150,7 +150,7 @@ static int __init sgiseeq_devinit(void)
                 return res;
 
         /* Second HPC is missing? */
-        if (!ip22_is_fullhouse() ||
+        if (ip22_is_fullhouse() ||
             get_dbe(tmp, (unsigned int *)&hpc3c1->pbdma[1]))
                 return 0;
 
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 0afe94c48fb6..fe6bee09cece 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -53,6 +53,7 @@ txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size)
                 txx9_ce_res[i].name = txx9_ce_res_name[i];
         }
 
+        txx9_pcode = pcode;
         sprintf(txx9_pcode_str, "TX%x", pcode);
         if (base) {
                 txx9_reg_res.start = base & 0xfffffffffULL;
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index cba36a247e32..92dd1a0ca352 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -72,6 +72,7 @@ static void irq_dispatch(unsigned int irq)
         cascade = irq_cascade + irq;
         if (cascade->get_irq != NULL) {
                 unsigned int source_irq = irq;
+                int ret;
                 desc = irq_desc + source_irq;
                 if (desc->chip->mask_ack)
                         desc->chip->mask_ack(source_irq);
@@ -79,8 +80,9 @@ static void irq_dispatch(unsigned int irq)
                         desc->chip->mask(source_irq);
                         desc->chip->ack(source_irq);
                 }
-                irq = cascade->get_irq(irq);
-                if (irq < 0)
+                ret = cascade->get_irq(irq);
+                irq = ret;
+                if (ret < 0)
                         atomic_inc(&irq_err_count);
                 else
                         irq_dispatch(irq);