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-rw-r--r--arch/mips/pci/ops-mace.c7
-rw-r--r--arch/mips/pci/pci-ip32.c4
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c1
-rw-r--r--arch/mips/sgi-ip32/ip32-platform.c20
4 files changed, 19 insertions, 13 deletions
diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c
index fe5451449304..e95881897ec9 100644
--- a/arch/mips/pci/ops-mace.c
+++ b/arch/mips/pci/ops-mace.c
@@ -42,6 +42,10 @@ static int
42mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, 42mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
43 int reg, int size, u32 *val) 43 int reg, int size, u32 *val)
44{ 44{
45 u32 control = mace->pci.control;
46
47 /* disable master aborts interrupts during config read */
48 mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
45 mace->pci.config_addr = mkaddr(bus, devfn, reg); 49 mace->pci.config_addr = mkaddr(bus, devfn, reg);
46 switch (size) { 50 switch (size) {
47 case 1: 51 case 1:
@@ -54,6 +58,9 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
54 *val = mace->pci.config_data.l; 58 *val = mace->pci.config_data.l;
55 break; 59 break;
56 } 60 }
61 /* ack possible master abort */
62 mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
63 mace->pci.control = control;
57 64
58 DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val); 65 DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
59 66
diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c
index 618ea7dbc474..532b561b4442 100644
--- a/arch/mips/pci/pci-ip32.c
+++ b/arch/mips/pci/pci-ip32.c
@@ -119,6 +119,7 @@ static struct pci_controller mace_pci_controller = {
119 .iommu = 0, 119 .iommu = 0,
120 .mem_offset = MACE_PCI_MEM_OFFSET, 120 .mem_offset = MACE_PCI_MEM_OFFSET,
121 .io_offset = 0, 121 .io_offset = 0,
122 .io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO),
122}; 123};
123 124
124static int __init mace_init(void) 125static int __init mace_init(void)
@@ -135,7 +136,8 @@ static int __init mace_init(void)
135 BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0, 136 BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
136 "MACE PCI error", NULL)); 137 "MACE PCI error", NULL));
137 138
138 iomem_resource = mace_pci_mem_resource; 139 /* extend memory resources */
140 iomem_resource.end = mace_pci_mem_resource.end;
139 ioport_resource = mace_pci_io_resource; 141 ioport_resource = mace_pci_io_resource;
140 142
141 register_pci_controller(&mace_pci_controller); 143 register_pci_controller(&mace_pci_controller);
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index cab7cc22ab67..b0ea0e43ba48 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -426,7 +426,6 @@ static void ip32_irq0(void)
426 426
427 crime_int = crime->istat & crime_mask; 427 crime_int = crime->istat & crime_mask;
428 irq = MACE_VID_IN1_IRQ + __ffs(crime_int); 428 irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
429 crime_int = 1 << irq;
430 429
431 if (crime_int & CRIME_MACEISA_INT_MASK) { 430 if (crime_int & CRIME_MACEISA_INT_MASK) {
432 unsigned long mace_int = mace->perif.ctrl.istat; 431 unsigned long mace_int = mace->perif.ctrl.istat;
diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c
index 77febd68fcd4..89a71f49b692 100644
--- a/arch/mips/sgi-ip32/ip32-platform.c
+++ b/arch/mips/sgi-ip32/ip32-platform.c
@@ -13,21 +13,22 @@
13#include <asm/ip32/mace.h> 13#include <asm/ip32/mace.h>
14#include <asm/ip32/ip32_ints.h> 14#include <asm/ip32/ip32_ints.h>
15 15
16/* 16#define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1)
17 * .iobase isn't a constant (in the sense of C) so we fill it in at runtime. 17#define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2)
18 */ 18
19#define MACE_PORT(int) \ 19#define MACE_PORT(offset,_irq) \
20{ \ 20{ \
21 .irq = int, \ 21 .mapbase = MACE_BASE + offset, \
22 .irq = _irq, \
22 .uartclk = 1843200, \ 23 .uartclk = 1843200, \
23 .iotype = UPIO_MEM, \ 24 .iotype = UPIO_MEM, \
24 .flags = UPF_SKIP_TEST, \ 25 .flags = UPF_SKIP_TEST|UPF_IOREMAP, \
25 .regshift = 8, \ 26 .regshift = 8, \
26} 27}
27 28
28static struct plat_serial8250_port uart8250_data[] = { 29static struct plat_serial8250_port uart8250_data[] = {
29 MACE_PORT(MACEISA_SERIAL1_IRQ), 30 MACE_PORT(MACEISA_SERIAL1_OFFS, MACEISA_SERIAL1_IRQ),
30 MACE_PORT(MACEISA_SERIAL2_IRQ), 31 MACE_PORT(MACEISA_SERIAL2_OFFS, MACEISA_SERIAL2_IRQ),
31 { }, 32 { },
32}; 33};
33 34
@@ -41,9 +42,6 @@ static struct platform_device uart8250_device = {
41 42
42static int __init uart8250_init(void) 43static int __init uart8250_init(void)
43{ 44{
44 uart8250_data[0].membase = (void __iomem *) &mace->isa.serial1;
45 uart8250_data[1].membase = (void __iomem *) &mace->isa.serial2;
46
47 return platform_device_register(&uart8250_device); 45 return platform_device_register(&uart8250_device);
48} 46}
49 47