19 files changed, 142 insertions, 91 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 767de847b4ab..3a0f89d2c8dc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1053,6 +1053,7 @@ config CPU_MIPS32_R1
         depends on SYS_HAS_CPU_MIPS32_R1
         select CPU_HAS_PREFETCH
         select CPU_SUPPORTS_32BIT_KERNEL
+        select CPU_SUPPORTS_HIGHMEM
         help
           Choose this option to build a kernel for release 1 or later of the
           MIPS32 architecture.  Most modern embedded systems with a 32-bit
@@ -1069,6 +1070,7 @@ config CPU_MIPS32_R2
         depends on SYS_HAS_CPU_MIPS32_R2
         select CPU_HAS_PREFETCH
         select CPU_SUPPORTS_32BIT_KERNEL
+        select CPU_SUPPORTS_HIGHMEM
         help
           Choose this option to build a kernel for release 2 or later of the
           MIPS32 architecture.  Most modern embedded systems with a 32-bit
@@ -1082,6 +1084,7 @@ config CPU_MIPS64_R1
         select CPU_HAS_PREFETCH
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HIGHMEM
         help
           Choose this option to build a kernel for release 1 or later of the
           MIPS64 architecture.  Many modern embedded systems with a 64-bit
@@ -1099,6 +1102,7 @@ config CPU_MIPS64_R2
         select CPU_HAS_PREFETCH
         select CPU_SUPPORTS_32BIT_KERNEL
         select CPU_SUPPORTS_64BIT_KERNEL
+        select CPU_SUPPORTS_HIGHMEM
         help
           Choose this option to build a kernel for release 2 or later of the
           MIPS64 architecture.  Many modern embedded systems with a 64-bit
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 38c0f3360d51..3d8dac681c63 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -95,6 +95,7 @@ endif
 # crossformat linking we rely on the elf2ecoff tool for format conversion.
 #
 cflags-y                        += -G 0 -mno-abicalls -fno-pic -pipe
+cflags-y                        += -msoft-float
 LDFLAGS_vmlinux                 += -G 0 -static -n -nostdlib
 MODFLAGS                        += -mlong-calls
 
@@ -107,7 +108,8 @@ MODFLAGS			+= -mlong-calls
 cflags-$(CONFIG_CPU_BIG_ENDIAN)         += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB)
 cflags-$(CONFIG_CPU_LITTLE_ENDIAN)      += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL)
 
-cflags-$(CONFIG_SB1XXX_CORELIS) += -mno-sched-prolog -fno-omit-frame-pointer
+cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
+                                   -fno-omit-frame-pointer
 
 #
 # Use: $(call set_gccflags,<cpu0>,<isa0>,<cpu1>,<isa1>,<isa2>)
diff --git a/arch/mips/arc/arc_con.c b/arch/mips/arc/arc_con.c
index 51785a6a7328..bc32fe64f42a 100644
--- a/arch/mips/arc/arc_con.c
+++ b/arch/mips/arc/arc_con.c
@@ -24,7 +24,7 @@ static void prom_console_write(struct console *co, const char *s,
         }
 }
 
-static int __init prom_console_setup(struct console *co, char *options)
+static int prom_console_setup(struct console *co, char *options)
 {
         return !(prom_flags & PROM_FLAG_USE_AS_CONSOLE);
 }
diff --git a/arch/mips/arc/misc.c b/arch/mips/arc/misc.c
index 84867de22028..b2e10b9e9452 100644
--- a/arch/mips/arc/misc.c
+++ b/arch/mips/arc/misc.c
@@ -9,7 +9,6 @@
  * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
  * Copyright (C) 1999 Silicon Graphics, Inc.
  */
-#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 
@@ -20,17 +19,11 @@
 #include <asm/bootinfo.h>
 #include <asm/system.h>
 
-extern void *sgiwd93_host;
-extern void reset_wd33c93(void *instance);
-
 VOID
 ArcHalt(VOID)
 {
         bc_disable();
         local_irq_disable();
-#ifdef CONFIG_SCSI_SGIWD93
-        reset_wd33c93(sgiwd93_host);
-#endif
         ARC_CALL0(halt);
 never:  goto never;
 }
@@ -40,9 +33,6 @@ ArcPowerDown(VOID)
 {
         bc_disable();
         local_irq_disable();
-#ifdef CONFIG_SCSI_SGIWD93
-        reset_wd33c93(sgiwd93_host);
-#endif
         ARC_CALL0(pdown);
 never:  goto never;
 }
@@ -53,9 +43,6 @@ ArcRestart(VOID)
 {
         bc_disable();
         local_irq_disable();
-#ifdef CONFIG_SCSI_SGIWD93
-        reset_wd33c93(sgiwd93_host);
-#endif
         ARC_CALL0(restart);
 never:  goto never;
 }
@@ -65,9 +52,6 @@ ArcReboot(VOID)
 {
         bc_disable();
         local_irq_disable();
-#ifdef CONFIG_SCSI_SGIWD93
-        reset_wd33c93(sgiwd93_host);
-#endif
         ARC_CALL0(reboot);
 never:  goto never;
 }
@@ -77,9 +61,6 @@ ArcEnterInteractiveMode(VOID)
 {
         bc_disable();
         local_irq_disable();
-#ifdef CONFIG_SCSI_SGIWD93
-        reset_wd33c93(sgiwd93_host);
-#endif
         ARC_CALL0(imode);
 never:  goto never;
 }
diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/au1000/common/reset.c
index 4ffccedf5967..c93af224c1b3 100644
--- a/arch/mips/au1000/common/reset.c
+++ b/arch/mips/au1000/common/reset.c
@@ -164,17 +164,20 @@ void au1000_restart(char *command)
 
 void au1000_halt(void)
 {
-#if defined(CONFIG_MIPS_PB1550)
+#if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
         /* power off system */
-        printk("\n** Powering off Pb1550\n");
+        printk("\n** Powering off...\n");
         au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C);
         au_sync();
         while(1); /* should not get here */
-#endif
+#else
         printk(KERN_NOTICE "\n** You can safely turn off the power\n");
 #ifdef CONFIG_MIPS_MIRAGE
         au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
 #endif
+#ifdef CONFIG_MIPS_DB1200
+        au_writew(au_readw(0xB980001C) | (1<<14), 0xB980001C);
+#endif
 #ifdef CONFIG_PM
         au_sleep();
 
@@ -187,6 +190,7 @@ void au1000_halt(void)
                         "wait\n\t"
                         ".set\tmips0");
 #endif
+#endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */
 }
 
 void au1000_power_off(void)
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index 0ac067f45cf5..0613f1f36b1b 100644
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -11,12 +11,14 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
-#include <asm/ptrace.h>
-#include <linux/sched.h>
 #include <linux/kernel_stat.h>
+#include <linux/mv643xx.h>
+#include <linux/sched.h>
+
+#include <asm/ptrace.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <linux/mv643xx.h>
+#include <asm/marvell.h>
 
 static unsigned int irq_base;
 
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 42c94c771afb..51273b7297a7 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -424,6 +424,8 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
         unsigned long j;
         unsigned int count;
 
+        write_seqlock(&xtime_lock);
+
         count = mips_hpt_read();
         mips_timer_ack();
 
@@ -441,7 +443,6 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
          * CMOS clock accordingly every ~11 minutes. rtc_set_time() has to be
          * called as close as possible to 500 ms before the new second starts.
          */
-        write_seqlock(&xtime_lock);
         if (ntp_synced() &&
             xtime.tv_sec > last_rtc_update + 660 &&
             (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
@@ -453,7 +454,6 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
                         last_rtc_update = xtime.tv_sec - 600;
                 }
         }
-        write_sequnlock(&xtime_lock);
 
         /*
          * If jiffies has overflown in this timer_interrupt, we must
@@ -496,6 +496,8 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
                 }
         }
 
+        write_sequnlock(&xtime_lock);
+
         /*
          * In UP mode, we call local_timer_interrupt() to do profiling
          * and process accouting.
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index ff699dbb99f7..2ad0cedf29fe 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -106,6 +106,9 @@ SECTIONS
   .con_initcall.init : { *(.con_initcall.init) }
   __con_initcall_end = .;
   SECURITY_INIT
+    /* .exit.text is discarded at runtime, not link time, to deal with
+     references from .rodata */
+  .exit.text : { *(.exit.text) }
   . = ALIGN(_PAGE_SIZE);
   __initramfs_start = .;
   .init.ramfs : { *(.init.ramfs) }
@@ -133,7 +136,6 @@ SECTIONS
 
   /* Sections to be discarded */
   /DISCARD/ : {
-        *(.exit.text)
         *(.exit.data)
         *(.exitcall.exit)
 
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 0668e9bfce41..9572ed44f0d5 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -375,6 +375,7 @@ static void r4k_flush_cache_mm(struct mm_struct *mm)
 struct flush_cache_page_args {
         struct vm_area_struct *vma;
         unsigned long addr;
+        unsigned long pfn;
 };
 
 static inline void local_r4k_flush_cache_page(void *args)
@@ -382,6 +383,7 @@ static inline void local_r4k_flush_cache_page(void *args)
         struct flush_cache_page_args *fcp_args = args;
         struct vm_area_struct *vma = fcp_args->vma;
         unsigned long addr = fcp_args->addr;
+        unsigned long paddr = fcp_args->pfn << PAGE_SHIFT;
         int exec = vma->vm_flags & VM_EXEC;
         struct mm_struct *mm = vma->vm_mm;
         pgd_t *pgdp;
@@ -431,11 +433,12 @@ static inline void local_r4k_flush_cache_page(void *args)
          * Do indexed flush, too much work to get the (possible) TLB refills
          * to work correctly.
          */
-        addr = INDEX_BASE + (addr & (dcache_size - 1));
         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
-                r4k_blast_dcache_page_indexed(addr);
-                if (exec && !cpu_icache_snoops_remote_store)
-                        r4k_blast_scache_page_indexed(addr);
+                r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ?
+                                              paddr : addr);
+                if (exec && !cpu_icache_snoops_remote_store) {
+                        r4k_blast_scache_page_indexed(paddr);
+                }
         }
         if (exec) {
                 if (cpu_has_vtag_icache) {
@@ -455,6 +458,7 @@ static void r4k_flush_cache_page(struct vm_area_struct *vma,
 
         args.vma = vma;
         args.addr = addr;
+        args.pfn = pfn;
 
         on_each_cpu(local_r4k_flush_cache_page, &args, 1, 1);
 }
@@ -956,6 +960,7 @@ static void __init probe_pcache(void)
         switch (c->cputype) {
         case CPU_20KC:
         case CPU_25KF:
+                c->dcache.flags |= MIPS_CACHE_PINDEX;
         case CPU_R10000:
         case CPU_R12000:
         case CPU_SB1:
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 7c572bea4a98..fe232e3988e3 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -210,7 +210,6 @@ static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
          * Do indexed flush, too much work to get the (possible) TLB refills
          * to work correctly.
          */
-        page = (KSEG0 + (page & (dcache_size - 1)));
         if (cpu_has_dc_aliases || exec)
                 tx39_blast_dcache_page_indexed(page);
         if (exec)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 0f9485806bac..ac4f4bfaae50 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -280,69 +280,69 @@ static void __init build_insn(u32 **buf, enum opcode opc, ...)
 }
 
 #define I_u1u2u3(op)                                            \
-        static inline void i##op(u32 **buf, unsigned int a,     \
+        static inline void __init i##op(u32 **buf, unsigned int a,      \
                 unsigned int b, unsigned int c)                 \
         {                                                       \
                 build_insn(buf, insn##op, a, b, c);             \
         }
 
 #define I_u2u1u3(op)                                            \
-        static inline void i##op(u32 **buf, unsigned int a,     \
+        static inline void __init i##op(u32 **buf, unsigned int a,      \
                 unsigned int b, unsigned int c)                 \
         {                                                       \
                 build_insn(buf, insn##op, b, a, c);             \
         }
 
 #define I_u3u1u2(op)                                            \
-        static inline void i##op(u32 **buf, unsigned int a,     \
+        static inline void __init i##op(u32 **buf, unsigned int a,      \
                 unsigned int b, unsigned int c)                 \
         {                                                       \
                 build_insn(buf, insn##op, b, c, a);             \
         }
 
 #define I_u1u2s3(op)                                            \
-        static inline void i##op(u32 **buf, unsigned int a,     \
+        static inline void __init i##op(u32 **buf, unsigned int a,      \
                 unsigned int b, signed int c)                   \
         {                                                       \
                 build_insn(buf, insn##op, a, b, c);             \
         }
 
 #define I_u2s3u1(op)                                            \
-        static inline void i##op(u32 **buf, unsigned int a,     \
+        static inline void __init i##op(u32 **buf, unsigned int a,      \
                 signed int b, unsigned int c)                   \
         {                                                       \
                 build_insn(buf, insn##op, c, a, b);             \
         }
 
 #define I_u2u1s3(op)                                            \
-        static inline void i##op(u32 **buf, unsigned int a,     \
+        static inline void __init i##op(u32 **buf, unsigned int a,      \
                 unsigned int b, signed int c)                   \
         {                                                       \
                 build_insn(buf, insn##op, b, a, c);             \
         }
 
 #define I_u1u2(op)                                              \
-        static inline void i##op(u32 **buf, unsigned int a,     \
+        static inline void __init i##op(u32 **buf, unsigned int a,      \
                 unsigned int b)                                 \
         {                                                       \
                 build_insn(buf, insn##op, a, b);                \
         }
 
 #define I_u1s2(op)                                              \
-        static inline void i##op(u32 **buf, unsigned int a,     \
+        static inline void __init i##op(u32 **buf, unsigned int a,      \
                 signed int b)                                   \
         {                                                       \
                 build_insn(buf, insn##op, a, b);                \
         }
 
 #define I_u1(op)                                                \
-        static inline void i##op(u32 **buf, unsigned int a)     \
+        static inline void __init i##op(u32 **buf, unsigned int a)      \
         {                                                       \
                 build_insn(buf, insn##op, a);                   \
         }
 
 #define I_0(op)                                                 \
-        static inline void i##op(u32 **buf)                     \
+        static inline void __init i##op(u32 **buf)              \
         {                                                       \
                 build_insn(buf, insn##op);                      \
         }
@@ -623,42 +623,42 @@ static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel,
 }
 
 /* convenience functions for labeled branches */
-static void __attribute__((unused)) il_bltz(u32 **p, struct reloc **r,
-                                            unsigned int reg, enum label_id l)
+static void __init __attribute__((unused))
+        il_bltz(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
 {
         r_mips_pc16(r, *p, l);
         i_bltz(p, reg, 0);
 }
 
-static void __attribute__((unused)) il_b(u32 **p, struct reloc **r,
+static void __init __attribute__((unused)) il_b(u32 **p, struct reloc **r,
                                          enum label_id l)
 {
         r_mips_pc16(r, *p, l);
         i_b(p, 0);
 }
 
-static void il_beqz(u32 **p, struct reloc **r, unsigned int reg,
+static void __init il_beqz(u32 **p, struct reloc **r, unsigned int reg,
                     enum label_id l)
 {
         r_mips_pc16(r, *p, l);
         i_beqz(p, reg, 0);
 }
 
-static void __attribute__((unused))
+static void __init __attribute__((unused))
 il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
 {
         r_mips_pc16(r, *p, l);
         i_beqzl(p, reg, 0);
 }
 
-static void il_bnez(u32 **p, struct reloc **r, unsigned int reg,
+static void __init il_bnez(u32 **p, struct reloc **r, unsigned int reg,
                     enum label_id l)
 {
         r_mips_pc16(r, *p, l);
         i_bnez(p, reg, 0);
 }
 
-static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
+static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
                      enum label_id l)
 {
         r_mips_pc16(r, *p, l);
diff --git a/arch/mips/momentum/jaguar_atx/prom.c b/arch/mips/momentum/jaguar_atx/prom.c
index aae7a802767a..1cadaa92946a 100644
--- a/arch/mips/momentum/jaguar_atx/prom.c
+++ b/arch/mips/momentum/jaguar_atx/prom.c
@@ -21,10 +21,10 @@
 #include <linux/mm.h>
 #include <linux/sched.h>
 #include <linux/bootmem.h>
+#include <linux/mv643xx.h>
 
 #include <asm/addrspace.h>
 #include <asm/bootinfo.h>
-#include <asm/mv64340.h>
 #include <asm/pmon.h>
 
 #include "jaguar_atx_fpga.h"
diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c
index 301d67226d72..2699917b640a 100644
--- a/arch/mips/momentum/jaguar_atx/setup.c
+++ b/arch/mips/momentum/jaguar_atx/setup.c
@@ -2,7 +2,7 @@
  * BRIEF MODULE DESCRIPTION
  * Momentum Computer Jaguar-ATX board dependent boot routines
  *
- * Copyright (C) 1996, 1997, 2001, 2004  Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 1996, 1997, 2001, 04, 06  Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 2000 RidgeRun, Inc.
  * Copyright (C) 2001 Red Hat, Inc.
  * Copyright (C) 2002 Momentum Computer
@@ -55,6 +55,8 @@
 #include <linux/interrupt.h>
 #include <linux/timex.h>
 #include <linux/vmalloc.h>
+#include <linux/mv643xx.h>
+
 #include <asm/time.h>
 #include <asm/bootinfo.h>
 #include <asm/page.h>
@@ -64,7 +66,6 @@
 #include <asm/ptrace.h>
 #include <asm/reboot.h>
 #include <asm/tlbflush.h>
-#include <asm/mv64340.h>
 
 #include "jaguar_atx_fpga.h"
 
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
index 300fe8e4fbe8..a5764bc20e36 100644
--- a/arch/mips/momentum/ocelot_c/irq.c
+++ b/arch/mips/momentum/ocelot_c/irq.c
@@ -41,11 +41,11 @@
 #include <linux/slab.h>
 #include <linux/random.h>
 #include <linux/bitops.h>
+#include <linux/mv643xx.h>
 #include <asm/bootinfo.h>
 #include <asm/io.h>
 #include <asm/irq_cpu.h>
 #include <asm/mipsregs.h>
-#include <asm/mv64340.h>
 #include <asm/system.h>
 
 extern asmlinkage void ocelot_handle_int(void);
diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c
index 5b6809724b15..e92364482c7b 100644
--- a/arch/mips/momentum/ocelot_c/prom.c
+++ b/arch/mips/momentum/ocelot_c/prom.c
@@ -19,10 +19,10 @@
 #include <linux/mm.h>
 #include <linux/sched.h>
 #include <linux/bootmem.h>
+#include <linux/mv643xx.h>
 
 #include <asm/addrspace.h>
 #include <asm/bootinfo.h>
-#include <asm/mv64340.h>
 #include <asm/pmon.h>
 
 #include "ocelot_c_fpga.h"
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c
index 15998d8a9341..bd02e60d037a 100644
--- a/arch/mips/momentum/ocelot_c/setup.c
+++ b/arch/mips/momentum/ocelot_c/setup.c
@@ -54,6 +54,7 @@
 #include <linux/pm.h>
 #include <linux/timex.h>
 #include <linux/vmalloc.h>
+#include <linux/mv643xx.h>
 
 #include <asm/time.h>
 #include <asm/bootinfo.h>
@@ -64,9 +65,9 @@
 #include <asm/processor.h>
 #include <asm/ptrace.h>
 #include <asm/reboot.h>
+#include <asm/marvell.h>
 #include <linux/bootmem.h>
 #include <linux/blkdev.h>
-#include <asm/mv64340.h>
 #include "ocelot_c_fpga.h"
 
 unsigned long marvell_base;
@@ -252,22 +253,22 @@ void __init plat_setup(void)
         /* shut down ethernet ports, just to be sure our memory doesn't get
          * corrupted by random ethernet traffic.
          */
-        MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
-        MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
-        MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
-        MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
+        MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
+        MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
+        MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
+        MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
         do {}
-          while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
+          while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
         do {}
-          while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
+          while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
         do {}
-          while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
+          while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
         do {}
-          while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
-        MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
-                 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
-        MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
-                 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
+          while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
+        MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
+                 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
+        MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
+                 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
 
         /* Turn off the Bit-Error LED */
         OCELOT_FPGA_WRITE(0x80, CLR);
diff --git a/arch/mips/pci/pci-ocelot-c.c b/arch/mips/pci/pci-ocelot-c.c
index 1d84d36e034d..027759f7c904 100644
--- a/arch/mips/pci/pci-ocelot-c.c
+++ b/arch/mips/pci/pci-ocelot-c.c
@@ -3,15 +3,17 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2004, 06 by Ralf Baechle (ralf@linux-mips.org)
  */
 
 #include <linux/types.h>
 #include <linux/pci.h>
-#include <asm/mv64340.h>
+#include <linux/mv643xx.h>
 
 #include <linux/init.h>
 
+#include <asm/marvell.h>
+
 /*
  * We assume the address ranges have already been setup appropriately by
  * the firmware.  PMON in case of the Ocelot C does that.
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 511c89d65f38..1588f6debd90 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -47,23 +47,51 @@
 #define IMR_IP3_VAL     K_INT_MAP_I1
 #define IMR_IP4_VAL     K_INT_MAP_I2
 
+#define SB1250_HPT_NUM          3
+#define SB1250_HPT_VALUE        M_SCD_TIMER_CNT /* max value */
+#define SB1250_HPT_SHIFT        ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH)
+
+
 extern int sb1250_steal_irq(int irq);
 
+static unsigned int sb1250_hpt_read(void);
+static void sb1250_hpt_init(unsigned int);
+
+static unsigned int hpt_offset;
+
+void __init sb1250_hpt_setup(void)
+{
+        int cpu = smp_processor_id();
+
+        if (!cpu) {
+                /* Setup hpt using timer #3 but do not enable irq for it */
+                __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
+                __raw_writeq(SB1250_HPT_VALUE,
+                             IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT)));
+                __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
+                             IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
+
+                /*
+                 * we need to fill 32 bits, so just use the upper 23 bits and pretend
+                 * the timer is going 512Mhz instead of 1Mhz
+                 */
+                mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT;
+                mips_hpt_init = sb1250_hpt_init;
+                mips_hpt_read = sb1250_hpt_read;
+        }
+}
+
+
 void sb1250_time_init(void)
 {
         int cpu = smp_processor_id();
         int irq = K_INT_TIMER_0+cpu;
 
-        /* Only have 4 general purpose timers */
-        if (cpu > 3) {
+        /* Only have 4 general purpose timers, and we use last one as hpt */
+        if (cpu > 2) {
                 BUG();
         }
 
-        if (!cpu) {
-                /* Use our own gettimeoffset() routine */
-                do_gettimeoffset = sb1250_gettimeoffset;
-        }
-
         sb1250_mask_irq(cpu, irq);
 
         /* Map the timer interrupt to ip[4] of this cpu */
@@ -75,10 +103,10 @@ void sb1250_time_init(void)
         /* Disable the timer and set up the count */
         __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
 #ifdef CONFIG_SIMULATION
-        __raw_writeq(50000 / HZ,
+        __raw_writeq((50000 / HZ) - 1,
                      IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 #else
-        __raw_writeq(1000000 / HZ,
+        __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
                      IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
 #endif
 
@@ -103,7 +131,7 @@ void sb1250_timer_interrupt(struct pt_regs *regs)
         int cpu = smp_processor_id();
         int irq = K_INT_TIMER_0 + cpu;
 
-        /* Reset the timer */
+        /* ACK interrupt */
         ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
                        IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
 
@@ -122,15 +150,26 @@ void sb1250_timer_interrupt(struct pt_regs *regs)
 }
 
 /*
- * We use our own do_gettimeoffset() instead of the generic one,
- * because the generic one does not work for SMP case.
- * In addition, since we use general timer 0 for system time,
- * we can get accurate intra-jiffy offset without calibration.
+ * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
+ * again. There's no easy way to set to a specific value so store init value
+ * in hpt_offset and subtract each time.
+ *
+ * Note: Timer isn't full 32bits so shift it into the upper part making
+ *       it appear to run at a higher frequency.
  */
-unsigned long sb1250_gettimeoffset(void)
+static unsigned int sb1250_hpt_read(void)
 {
-        unsigned long count =
-                __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
+        unsigned int count;
 
-        return 1000000/HZ - count;
- }
+        count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
+
+        count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT;
+
+        return count - hpt_offset;
+}
+
+static void sb1250_hpt_init(unsigned int count)
+{
+        hpt_offset = count;
+        return;
+}
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index b614ca0ddb69..b661d2425a36 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -70,6 +70,12 @@ const char *get_system_type(void)
         return "SiByte " SIBYTE_BOARD_NAME;
 }
 
+void __init swarm_time_init(void)
+{
+        /* Setup HPT */
+        sb1250_hpt_setup();
+}
+
 void __init swarm_timer_setup(struct irqaction *irq)
 {
         /*
@@ -109,6 +115,7 @@ void __init plat_setup(void)
 
         panic_timeout = 5;  /* For debug.  */
 
+        board_time_init = swarm_time_init;
         board_timer_setup = swarm_timer_setup;
         board_be_handler = swarm_be_handler;