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-rw-r--r--arch/mips/include/asm/mach-ip27/kernel-entry-init.h12
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
index 3f6bc85ea61d..b087cb83da3a 100644
--- a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
@@ -23,6 +23,14 @@
23 dsrl \res, NSRI_NODEID_SHFT 23 dsrl \res, NSRI_NODEID_SHFT
24 .endm 24 .endm
25 25
26/*
27 * TLB bits
28 */
29#define PAGE_GLOBAL (1 << 6)
30#define PAGE_VALID (1 << 7)
31#define PAGE_DIRTY (1 << 8)
32#define CACHE_CACHABLE_COW (5 << 9)
33
26 /* 34 /*
27 * inputs are the text nasid in t1, data nasid in t2. 35 * inputs are the text nasid in t1, data nasid in t2.
28 */ 36 */
@@ -44,10 +52,10 @@
44 dsrl t2, 12 # 4K pfn 52 dsrl t2, 12 # 4K pfn
45 dsll t1, 6 # Get pfn into place 53 dsll t1, 6 # Get pfn into place
46 dsll t2, 6 # Get pfn into place 54 dsll t2, 6 # Get pfn into place
47 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6) 55 li t0, ((PAGE_GLOBAL | PAGE_VALID | CACHE_CACHABLE_COW) >> 6)
48 or t0, t0, t1 56 or t0, t0, t1
49 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr 57 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
50 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6) 58 li t0, ((PAGE_GLOBAL | PAGE_VALID | PAGE_DIRTY | CACHE_CACHABLE_COW) >> 6)
51 or t0, t0, t2 59 or t0, t0, t2
52 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr 60 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
53 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M 61 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M