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-rw-r--r--arch/mips/Kconfig40
-rw-r--r--arch/mips/au1000/common/dbdma.c2
-rw-r--r--arch/mips/au1000/common/irq.c63
-rw-r--r--arch/mips/au1000/common/prom.c2
-rw-r--r--arch/mips/au1000/common/setup.c2
-rw-r--r--arch/mips/au1000/common/time.c106
-rw-r--r--arch/mips/au1000/pb1200/board_setup.c8
-rw-r--r--arch/mips/cobalt/irq.c31
-rw-r--r--arch/mips/cobalt/setup.c16
-rw-r--r--arch/mips/configs/pnx8550-jbs_defconfig384
-rw-r--r--arch/mips/configs/pnx8550-v2pci_defconfig441
-rw-r--r--arch/mips/configs/tb0287_defconfig182
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq_5477.c23
-rw-r--r--arch/mips/dec/ecc-berr.c6
-rw-r--r--arch/mips/dec/int-handler.S2
-rw-r--r--arch/mips/dec/ioasic-irq.c74
-rw-r--r--arch/mips/dec/kn02-irq.c53
-rw-r--r--arch/mips/dec/setup.c6
-rw-r--r--arch/mips/dec/time.c13
-rw-r--r--arch/mips/emma2rh/common/irq_emma2rh.c35
-rw-r--r--arch/mips/emma2rh/markeins/irq_markeins.c56
-rw-r--r--arch/mips/emma2rh/markeins/platform.c88
-rw-r--r--arch/mips/gt64120/common/time.c4
-rw-r--r--arch/mips/gt64120/ev64120/irq.c40
-rw-r--r--arch/mips/gt64120/ev64120/setup.c2
-rw-r--r--arch/mips/gt64120/momenco_ocelot/setup.c3
-rw-r--r--arch/mips/jazz/irq.c27
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c35
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c40
-rw-r--r--arch/mips/kernel/Makefile5
-rw-r--r--arch/mips/kernel/asm-offsets.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c19
-rw-r--r--arch/mips/kernel/dma-no-isa.c28
-rw-r--r--arch/mips/kernel/entry.S3
-rw-r--r--arch/mips/kernel/genex.S63
-rw-r--r--arch/mips/kernel/head.S6
-rw-r--r--arch/mips/kernel/i8259.c21
-rw-r--r--arch/mips/kernel/irq-msc01.c47
-rw-r--r--arch/mips/kernel/irq-mv6434x.c54
-rw-r--r--arch/mips/kernel/irq-rm7000.c54
-rw-r--r--arch/mips/kernel/irq-rm9000.c47
-rw-r--r--arch/mips/kernel/irq.c74
-rw-r--r--arch/mips/kernel/irq_cpu.c80
-rw-r--r--arch/mips/kernel/linux32.c4
-rw-r--r--arch/mips/kernel/machine_kexec.c85
-rw-r--r--arch/mips/kernel/module.c15
-rw-r--r--arch/mips/kernel/process.c8
-rw-r--r--arch/mips/kernel/r4k_switch.S5
-rw-r--r--arch/mips/kernel/relocate_kernel.S80
-rw-r--r--arch/mips/kernel/scall32-o32.S5
-rw-r--r--arch/mips/kernel/scall64-64.S3
-rw-r--r--arch/mips/kernel/scall64-n32.S5
-rw-r--r--arch/mips/kernel/scall64-o32.S5
-rw-r--r--arch/mips/kernel/setup.c93
-rw-r--r--arch/mips/kernel/signal_n32.c1
-rw-r--r--arch/mips/kernel/smp-mt.c156
-rw-r--r--arch/mips/kernel/smp.c23
-rw-r--r--arch/mips/kernel/smtc-asm.S7
-rw-r--r--arch/mips/kernel/smtc.c2
-rw-r--r--arch/mips/kernel/stacktrace.c2
-rw-r--r--arch/mips/kernel/time.c349
-rw-r--r--arch/mips/kernel/topology.c29
-rw-r--r--arch/mips/kernel/traps.c74
-rw-r--r--arch/mips/kernel/vmlinux.lds.S18
-rw-r--r--arch/mips/lasat/interrupt.c36
-rw-r--r--arch/mips/lib-64/dump_tlb.c6
-rw-r--r--arch/mips/lib/csum_partial_copy.c8
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c29
-rw-r--r--arch/mips/mips-boards/generic/memory.c2
-rw-r--r--arch/mips/mips-boards/generic/pci.c2
-rw-r--r--arch/mips/mips-boards/generic/time.c10
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c3
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c2
-rw-r--r--arch/mips/mips-boards/sim/sim_time.c20
-rw-r--r--arch/mips/mm/c-r4k.c22
-rw-r--r--arch/mips/mm/c-sb1.c42
-rw-r--r--arch/mips/mm/fault.c4
-rw-r--r--arch/mips/mm/init.c209
-rw-r--r--arch/mips/mm/ioremap.c2
-rw-r--r--arch/mips/mm/pg-r4k.c30
-rw-r--r--arch/mips/mm/pgtable-32.c7
-rw-r--r--arch/mips/mm/pgtable-64.c14
-rw-r--r--arch/mips/mm/tlbex.c68
-rw-r--r--arch/mips/momentum/ocelot_3/Makefile2
-rw-r--r--arch/mips/momentum/ocelot_3/ocelot_3_fpga.h6
-rw-r--r--arch/mips/momentum/ocelot_3/platform.c235
-rw-r--r--arch/mips/momentum/ocelot_3/prom.c58
-rw-r--r--arch/mips/momentum/ocelot_3/setup.c2
-rw-r--r--arch/mips/momentum/ocelot_c/Makefile2
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c53
-rw-r--r--arch/mips/momentum/ocelot_c/ocelot_c_fpga.h6
-rw-r--r--arch/mips/momentum/ocelot_c/platform.c201
-rw-r--r--arch/mips/momentum/ocelot_c/prom.c60
-rw-r--r--arch/mips/momentum/ocelot_c/setup.c23
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c56
-rw-r--r--arch/mips/momentum/ocelot_g/gt-irq.c8
-rw-r--r--arch/mips/momentum/ocelot_g/ocelot_pld.h6
-rw-r--r--arch/mips/momentum/ocelot_g/setup.c5
-rw-r--r--arch/mips/oprofile/Makefile1
-rw-r--r--arch/mips/oprofile/common.c3
-rw-r--r--arch/mips/oprofile/op_impl.h2
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c44
-rw-r--r--arch/mips/oprofile/op_model_rm9000.c3
-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/fixup-cobalt.c11
-rw-r--r--arch/mips/pci/fixup-ev64120.c34
-rw-r--r--arch/mips/pci/ops-gt64111.c16
-rw-r--r--arch/mips/pci/pci-ev64120.c21
-rw-r--r--arch/mips/philips/pnx8550/common/int.c68
-rw-r--r--arch/mips/philips/pnx8550/common/time.c4
-rw-r--r--arch/mips/pmc-sierra/yosemite/i2c-yosemite.c2
-rw-r--r--arch/mips/pmc-sierra/yosemite/smp.c6
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c33
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c109
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c40
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c46
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c133
-rw-r--r--arch/mips/sgi-ip32/ip32-reset.c2
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c30
-rw-r--r--arch/mips/sibyte/bcm1480/time.c35
-rw-r--r--arch/mips/sibyte/sb1250/bcm1250_tbprof.c4
-rw-r--r--arch/mips/sibyte/sb1250/bus_watcher.c2
-rw-r--r--arch/mips/sibyte/sb1250/irq.c30
-rw-r--r--arch/mips/sibyte/sb1250/time.c34
-rw-r--r--arch/mips/sni/irq.c40
-rw-r--r--arch/mips/tx4927/common/smsc_fdc37m81x.c172
-rw-r--r--arch/mips/tx4927/common/tx4927_irq.c164
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c2
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c184
-rw-r--r--arch/mips/tx4938/common/irq.c115
-rw-r--r--arch/mips/tx4938/common/setup.c1
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/irq.c54
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c8
-rw-r--r--arch/mips/vr41xx/common/icu.c48
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/irq.c20
135 files changed, 3015 insertions, 3003 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 14af6cce2fa2..27f83e642968 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -266,8 +266,8 @@ config MIPS_MALTA
266 select BOOT_ELF32 266 select BOOT_ELF32
267 select HAVE_STD_PC_SERIAL_PORT 267 select HAVE_STD_PC_SERIAL_PORT
268 select DMA_NONCOHERENT 268 select DMA_NONCOHERENT
269 select IRQ_CPU
270 select GENERIC_ISA_DMA 269 select GENERIC_ISA_DMA
270 select IRQ_CPU
271 select HW_HAS_PCI 271 select HW_HAS_PCI
272 select I8259 272 select I8259
273 select MIPS_BOARDS_GEN 273 select MIPS_BOARDS_GEN
@@ -425,9 +425,8 @@ config MOMENCO_OCELOT_G
425 select SWAP_IO_SPACE 425 select SWAP_IO_SPACE
426 select SYS_HAS_CPU_RM7000 426 select SYS_HAS_CPU_RM7000
427 select SYS_SUPPORTS_32BIT_KERNEL 427 select SYS_SUPPORTS_32BIT_KERNEL
428 select SYS_SUPPORTS_64BIT_KERNEL 428 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
429 select SYS_SUPPORTS_BIG_ENDIAN 429 select SYS_SUPPORTS_BIG_ENDIAN
430 select ARCH_SPARSEMEM_ENABLE
431 help 430 help
432 The Ocelot is a MIPS-based Single Board Computer (SBC) made by 431 The Ocelot is a MIPS-based Single Board Computer (SBC) made by
433 Momentum Computer <http://www.momenco.com/>. 432 Momentum Computer <http://www.momenco.com/>.
@@ -535,7 +534,7 @@ config SGI_IP22
535 select HW_HAS_EISA 534 select HW_HAS_EISA
536 select IP22_CPU_SCACHE 535 select IP22_CPU_SCACHE
537 select IRQ_CPU 536 select IRQ_CPU
538 select NO_ISA if ISA 537 select GENERIC_ISA_DMA_SUPPORT_BROKEN
539 select SWAP_IO_SPACE 538 select SWAP_IO_SPACE
540 select SYS_HAS_CPU_R4X00 539 select SYS_HAS_CPU_R4X00
541 select SYS_HAS_CPU_R5000 540 select SYS_HAS_CPU_R5000
@@ -560,6 +559,7 @@ config SGI_IP27
560 select SYS_SUPPORTS_64BIT_KERNEL 559 select SYS_SUPPORTS_64BIT_KERNEL
561 select SYS_SUPPORTS_BIG_ENDIAN 560 select SYS_SUPPORTS_BIG_ENDIAN
562 select SYS_SUPPORTS_NUMA 561 select SYS_SUPPORTS_NUMA
562 select SYS_SUPPORTS_SMP
563 help 563 help
564 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics 564 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
565 workstations. To compile a Linux kernel that runs on these, say Y 565 workstations. To compile a Linux kernel that runs on these, say Y
@@ -766,6 +766,23 @@ config TOSHIBA_RBTX4938
766 766
767endchoice 767endchoice
768 768
769config KEXEC
770 bool "Kexec system call (EXPERIMENTAL)"
771 depends on EXPERIMENTAL
772 help
773 kexec is a system call that implements the ability to shutdown your
774 current kernel, and to start another kernel. It is like a reboot
775 but it is indepedent of the system firmware. And like a reboot
776 you can start any kernel with it, not just Linux.
777
778 The name comes from the similiarity to the exec system call.
779
780 It is an ongoing process to be certain the hardware in a machine
781 is properly shutdown, so do not be surprised if this code does not
782 initially work for you. It may help to enable device hotplugging
783 support. As of this writing the exact hardware interface is
784 strongly in flux, so no good recommendation can be made.
785
769source "arch/mips/ddb5xxx/Kconfig" 786source "arch/mips/ddb5xxx/Kconfig"
770source "arch/mips/gt64120/ev64120/Kconfig" 787source "arch/mips/gt64120/ev64120/Kconfig"
771source "arch/mips/jazz/Kconfig" 788source "arch/mips/jazz/Kconfig"
@@ -864,8 +881,11 @@ config MIPS_NILE4
864config MIPS_DISABLE_OBSOLETE_IDE 881config MIPS_DISABLE_OBSOLETE_IDE
865 bool 882 bool
866 883
884config GENERIC_ISA_DMA_SUPPORT_BROKEN
885 bool
886
867# 887#
868# Endianess selection. Suffiently obscure so many users don't know what to 888# Endianess selection. Sufficiently obscure so many users don't know what to
869# answer,so we try hard to limit the available choices. Also the use of a 889# answer,so we try hard to limit the available choices. Also the use of a
870# choice statement should be more obvious to the user. 890# choice statement should be more obvious to the user.
871# 891#
@@ -874,7 +894,7 @@ choice
874 help 894 help
875 Some MIPS machines can be configured for either little or big endian 895 Some MIPS machines can be configured for either little or big endian
876 byte order. These modes require different kernels and a different 896 byte order. These modes require different kernels and a different
877 Linux distribution. In general there is one prefered byteorder for a 897 Linux distribution. In general there is one preferred byteorder for a
878 particular system but some systems are just as commonly used in the 898 particular system but some systems are just as commonly used in the
879 one or the other endianess. 899 one or the other endianess.
880 900
@@ -1633,9 +1653,6 @@ config ARCH_DISCONTIGMEM_ENABLE
1633 1653
1634config ARCH_SPARSEMEM_ENABLE 1654config ARCH_SPARSEMEM_ENABLE
1635 bool 1655 bool
1636
1637config ARCH_SPARSEMEM_ENABLE
1638 bool
1639 select SPARSEMEM_STATIC 1656 select SPARSEMEM_STATIC
1640 1657
1641config NUMA 1658config NUMA
@@ -1690,6 +1707,7 @@ config NR_CPUS
1690 depends on SMP 1707 depends on SMP
1691 default "64" if SGI_IP27 1708 default "64" if SGI_IP27
1692 default "2" 1709 default "2"
1710 default "8" if MIPS_MT_SMTC
1693 help 1711 help
1694 This allows you to specify the maximum number of CPUs which this 1712 This allows you to specify the maximum number of CPUs which this
1695 kernel will support. The maximum supported value is 32 for 32-bit 1713 kernel will support. The maximum supported value is 32 for 32-bit
@@ -1837,13 +1855,11 @@ source "drivers/pci/Kconfig"
1837config ISA 1855config ISA
1838 bool 1856 bool
1839 1857
1840config NO_ISA
1841 bool
1842
1843config EISA 1858config EISA
1844 bool "EISA support" 1859 bool "EISA support"
1845 depends on HW_HAS_EISA 1860 depends on HW_HAS_EISA
1846 select ISA 1861 select ISA
1862 select GENERIC_ISA_DMA
1847 ---help--- 1863 ---help---
1848 The Extended Industry Standard Architecture (EISA) bus was 1864 The Extended Industry Standard Architecture (EISA) bus was
1849 developed as an open alternative to the IBM MicroChannel bus. 1865 developed as an open alternative to the IBM MicroChannel bus.
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c
index c4fae8ff4671..626de44bd888 100644
--- a/arch/mips/au1000/common/dbdma.c
+++ b/arch/mips/au1000/common/dbdma.c
@@ -849,7 +849,7 @@ au1xxx_dbdma_chan_free(u32 chanid)
849EXPORT_SYMBOL(au1xxx_dbdma_chan_free); 849EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
850 850
851static irqreturn_t 851static irqreturn_t
852dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs) 852dbdma_interrupt(int irq, void *dev_id)
853{ 853{
854 u32 intstat; 854 u32 intstat;
855 u32 chan_index; 855 u32 chan_index;
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index 2abe132bb07d..9cf7b6715836 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -70,7 +70,6 @@ extern irq_cpustat_t irq_stat [NR_CPUS];
70extern void mips_timer_interrupt(void); 70extern void mips_timer_interrupt(void);
71 71
72static void setup_local_irq(unsigned int irq, int type, int int_req); 72static void setup_local_irq(unsigned int irq, int type, int int_req);
73static unsigned int startup_irq(unsigned int irq);
74static void end_irq(unsigned int irq_nr); 73static void end_irq(unsigned int irq_nr);
75static inline void mask_and_ack_level_irq(unsigned int irq_nr); 74static inline void mask_and_ack_level_irq(unsigned int irq_nr);
76static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); 75static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
@@ -84,20 +83,6 @@ void (*board_init_irq)(void);
84static DEFINE_SPINLOCK(irq_lock); 83static DEFINE_SPINLOCK(irq_lock);
85 84
86 85
87static unsigned int startup_irq(unsigned int irq_nr)
88{
89 local_enable_irq(irq_nr);
90 return 0;
91}
92
93
94static void shutdown_irq(unsigned int irq_nr)
95{
96 local_disable_irq(irq_nr);
97 return;
98}
99
100
101inline void local_enable_irq(unsigned int irq_nr) 86inline void local_enable_irq(unsigned int irq_nr)
102{ 87{
103 if (irq_nr > AU1000_LAST_INTC0_INT) { 88 if (irq_nr > AU1000_LAST_INTC0_INT) {
@@ -249,41 +234,37 @@ void restore_local_and_enable(int controller, unsigned long mask)
249 234
250static struct irq_chip rise_edge_irq_type = { 235static struct irq_chip rise_edge_irq_type = {
251 .typename = "Au1000 Rise Edge", 236 .typename = "Au1000 Rise Edge",
252 .startup = startup_irq,
253 .shutdown = shutdown_irq,
254 .enable = local_enable_irq,
255 .disable = local_disable_irq,
256 .ack = mask_and_ack_rise_edge_irq, 237 .ack = mask_and_ack_rise_edge_irq,
238 .mask = local_disable_irq,
239 .mask_ack = mask_and_ack_rise_edge_irq,
240 .unmask = local_enable_irq,
257 .end = end_irq, 241 .end = end_irq,
258}; 242};
259 243
260static struct irq_chip fall_edge_irq_type = { 244static struct irq_chip fall_edge_irq_type = {
261 .typename = "Au1000 Fall Edge", 245 .typename = "Au1000 Fall Edge",
262 .startup = startup_irq,
263 .shutdown = shutdown_irq,
264 .enable = local_enable_irq,
265 .disable = local_disable_irq,
266 .ack = mask_and_ack_fall_edge_irq, 246 .ack = mask_and_ack_fall_edge_irq,
247 .mask = local_disable_irq,
248 .mask_ack = mask_and_ack_fall_edge_irq,
249 .unmask = local_enable_irq,
267 .end = end_irq, 250 .end = end_irq,
268}; 251};
269 252
270static struct irq_chip either_edge_irq_type = { 253static struct irq_chip either_edge_irq_type = {
271 .typename = "Au1000 Rise or Fall Edge", 254 .typename = "Au1000 Rise or Fall Edge",
272 .startup = startup_irq,
273 .shutdown = shutdown_irq,
274 .enable = local_enable_irq,
275 .disable = local_disable_irq,
276 .ack = mask_and_ack_either_edge_irq, 255 .ack = mask_and_ack_either_edge_irq,
256 .mask = local_disable_irq,
257 .mask_ack = mask_and_ack_either_edge_irq,
258 .unmask = local_enable_irq,
277 .end = end_irq, 259 .end = end_irq,
278}; 260};
279 261
280static struct irq_chip level_irq_type = { 262static struct irq_chip level_irq_type = {
281 .typename = "Au1000 Level", 263 .typename = "Au1000 Level",
282 .startup = startup_irq,
283 .shutdown = shutdown_irq,
284 .enable = local_enable_irq,
285 .disable = local_disable_irq,
286 .ack = mask_and_ack_level_irq, 264 .ack = mask_and_ack_level_irq,
265 .mask = local_disable_irq,
266 .mask_ack = mask_and_ack_level_irq,
267 .unmask = local_enable_irq,
287 .end = end_irq, 268 .end = end_irq,
288}; 269};
289 270
@@ -328,31 +309,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
328 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 309 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
329 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 310 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
330 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 311 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
331 irq_desc[irq_nr].chip = &rise_edge_irq_type; 312 set_irq_chip(irq_nr, &rise_edge_irq_type);
332 break; 313 break;
333 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 314 case INTC_INT_FALL_EDGE: /* 0:1:0 */
334 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 315 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
335 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 316 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
336 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 317 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
337 irq_desc[irq_nr].chip = &fall_edge_irq_type; 318 set_irq_chip(irq_nr, &fall_edge_irq_type);
338 break; 319 break;
339 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 320 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
340 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 321 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
341 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 322 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
342 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 323 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
343 irq_desc[irq_nr].chip = &either_edge_irq_type; 324 set_irq_chip(irq_nr, &either_edge_irq_type);
344 break; 325 break;
345 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 326 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
346 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 327 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
347 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 328 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
348 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 329 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
349 irq_desc[irq_nr].chip = &level_irq_type; 330 set_irq_chip(irq_nr, &level_irq_type);
350 break; 331 break;
351 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 332 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
352 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 333 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
353 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 334 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
354 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 335 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
355 irq_desc[irq_nr].chip = &level_irq_type; 336 set_irq_chip(irq_nr, &level_irq_type);
356 break; 337 break;
357 case INTC_INT_DISABLED: /* 0:0:0 */ 338 case INTC_INT_DISABLED: /* 0:0:0 */
358 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 339 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
@@ -380,31 +361,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
380 au_writel(1<<irq_nr, IC0_CFG2CLR); 361 au_writel(1<<irq_nr, IC0_CFG2CLR);
381 au_writel(1<<irq_nr, IC0_CFG1CLR); 362 au_writel(1<<irq_nr, IC0_CFG1CLR);
382 au_writel(1<<irq_nr, IC0_CFG0SET); 363 au_writel(1<<irq_nr, IC0_CFG0SET);
383 irq_desc[irq_nr].chip = &rise_edge_irq_type; 364 set_irq_chip(irq_nr, &rise_edge_irq_type);
384 break; 365 break;
385 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 366 case INTC_INT_FALL_EDGE: /* 0:1:0 */
386 au_writel(1<<irq_nr, IC0_CFG2CLR); 367 au_writel(1<<irq_nr, IC0_CFG2CLR);
387 au_writel(1<<irq_nr, IC0_CFG1SET); 368 au_writel(1<<irq_nr, IC0_CFG1SET);
388 au_writel(1<<irq_nr, IC0_CFG0CLR); 369 au_writel(1<<irq_nr, IC0_CFG0CLR);
389 irq_desc[irq_nr].chip = &fall_edge_irq_type; 370 set_irq_chip(irq_nr, &fall_edge_irq_type);
390 break; 371 break;
391 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 372 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
392 au_writel(1<<irq_nr, IC0_CFG2CLR); 373 au_writel(1<<irq_nr, IC0_CFG2CLR);
393 au_writel(1<<irq_nr, IC0_CFG1SET); 374 au_writel(1<<irq_nr, IC0_CFG1SET);
394 au_writel(1<<irq_nr, IC0_CFG0SET); 375 au_writel(1<<irq_nr, IC0_CFG0SET);
395 irq_desc[irq_nr].chip = &either_edge_irq_type; 376 set_irq_chip(irq_nr, &either_edge_irq_type);
396 break; 377 break;
397 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 378 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
398 au_writel(1<<irq_nr, IC0_CFG2SET); 379 au_writel(1<<irq_nr, IC0_CFG2SET);
399 au_writel(1<<irq_nr, IC0_CFG1CLR); 380 au_writel(1<<irq_nr, IC0_CFG1CLR);
400 au_writel(1<<irq_nr, IC0_CFG0SET); 381 au_writel(1<<irq_nr, IC0_CFG0SET);
401 irq_desc[irq_nr].chip = &level_irq_type; 382 set_irq_chip(irq_nr, &level_irq_type);
402 break; 383 break;
403 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 384 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
404 au_writel(1<<irq_nr, IC0_CFG2SET); 385 au_writel(1<<irq_nr, IC0_CFG2SET);
405 au_writel(1<<irq_nr, IC0_CFG1SET); 386 au_writel(1<<irq_nr, IC0_CFG1SET);
406 au_writel(1<<irq_nr, IC0_CFG0CLR); 387 au_writel(1<<irq_nr, IC0_CFG0CLR);
407 irq_desc[irq_nr].chip = &level_irq_type; 388 set_irq_chip(irq_nr, &level_irq_type);
408 break; 389 break;
409 case INTC_INT_DISABLED: /* 0:0:0 */ 390 case INTC_INT_DISABLED: /* 0:0:0 */
410 au_writel(1<<irq_nr, IC0_CFG0CLR); 391 au_writel(1<<irq_nr, IC0_CFG0CLR);
diff --git a/arch/mips/au1000/common/prom.c b/arch/mips/au1000/common/prom.c
index b4b010a2fe36..6fce60af005d 100644
--- a/arch/mips/au1000/common/prom.c
+++ b/arch/mips/au1000/common/prom.c
@@ -47,7 +47,7 @@ extern int prom_argc;
47extern char **prom_argv, **prom_envp; 47extern char **prom_argv, **prom_envp;
48 48
49 49
50char * prom_getcmdline(void) 50char * __init_or_module prom_getcmdline(void)
51{ 51{
52 return &(arcs_cmdline[0]); 52 return &(arcs_cmdline[0]);
53} 53}
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index 377ae0d8ff00..919172db560c 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -43,7 +43,7 @@
43#include <asm/mach-au1x00/au1000.h> 43#include <asm/mach-au1x00/au1000.h>
44#include <asm/time.h> 44#include <asm/time.h>
45 45
46extern char * __init prom_getcmdline(void); 46extern char * prom_getcmdline(void);
47extern void __init board_setup(void); 47extern void __init board_setup(void);
48extern void au1000_restart(char *); 48extern void au1000_restart(char *);
49extern void au1000_halt(void); 49extern void au1000_halt(void);
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index 94f09194d63d..fa1c62f05515 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -53,9 +53,6 @@ static unsigned long r4k_cur; /* What counter should be at next timer irq */
53int no_au1xxx_32khz; 53int no_au1xxx_32khz;
54extern int allow_au1k_wait; /* default off for CP0 Counter */ 54extern int allow_au1k_wait; /* default off for CP0 Counter */
55 55
56/* Cycle counter value at the previous timer interrupt.. */
57static unsigned int timerhi = 0, timerlo = 0;
58
59#ifdef CONFIG_PM 56#ifdef CONFIG_PM
60#if HZ < 100 || HZ > 1000 57#if HZ < 100 || HZ > 1000
61#error "unsupported HZ value! Must be in [100,1000]" 58#error "unsupported HZ value! Must be in [100,1000]"
@@ -82,7 +79,6 @@ unsigned long wtimer;
82void mips_timer_interrupt(void) 79void mips_timer_interrupt(void)
83{ 80{
84 int irq = 63; 81 int irq = 63;
85 unsigned long count;
86 82
87 irq_enter(); 83 irq_enter();
88 kstat_this_cpu.irqs[irq]++; 84 kstat_this_cpu.irqs[irq]++;
@@ -91,10 +87,6 @@ void mips_timer_interrupt(void)
91 goto null; 87 goto null;
92 88
93 do { 89 do {
94 count = read_c0_count();
95 timerhi += (count < timerlo); /* Wrap around */
96 timerlo = count;
97
98 kstat_this_cpu.irqs[irq]++; 90 kstat_this_cpu.irqs[irq]++;
99 do_timer(1); 91 do_timer(1);
100#ifndef CONFIG_SMP 92#ifndef CONFIG_SMP
@@ -231,7 +223,6 @@ wakeup_counter0_set(int ticks)
231 */ 223 */
232unsigned long cal_r4koff(void) 224unsigned long cal_r4koff(void)
233{ 225{
234 unsigned long count;
235 unsigned long cpu_speed; 226 unsigned long cpu_speed;
236 unsigned long flags; 227 unsigned long flags;
237 unsigned long counter; 228 unsigned long counter;
@@ -258,7 +249,7 @@ unsigned long cal_r4koff(void)
258 249
259#if defined(CONFIG_AU1000_USE32K) 250#if defined(CONFIG_AU1000_USE32K)
260 { 251 {
261 unsigned long start, end; 252 unsigned long start, end, count;
262 253
263 start = au_readl(SYS_RTCREAD); 254 start = au_readl(SYS_RTCREAD);
264 start += 2; 255 start += 2;
@@ -282,7 +273,6 @@ unsigned long cal_r4koff(void)
282#else 273#else
283 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * 274 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
284 AU1000_SRC_CLK; 275 AU1000_SRC_CLK;
285 count = cpu_speed / 2;
286#endif 276#endif
287 } 277 }
288 else { 278 else {
@@ -291,98 +281,15 @@ unsigned long cal_r4koff(void)
291 * NOTE: some old silicon doesn't allow reading the PLL. 281 * NOTE: some old silicon doesn't allow reading the PLL.
292 */ 282 */
293 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; 283 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
294 count = cpu_speed / 2;
295 no_au1xxx_32khz = 1; 284 no_au1xxx_32khz = 1;
296 } 285 }
297 mips_hpt_frequency = count; 286 mips_hpt_frequency = cpu_speed;
298 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) 287 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
299 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16)); 288 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
300 spin_unlock_irqrestore(&time_lock, flags); 289 spin_unlock_irqrestore(&time_lock, flags);
301 return (cpu_speed / HZ); 290 return (cpu_speed / HZ);
302} 291}
303 292
304/* This is for machines which generate the exact clock. */
305#define USECS_PER_JIFFY (1000000/HZ)
306#define USECS_PER_JIFFY_FRAC (0x100000000LL*1000000/HZ&0xffffffff)
307
308static unsigned long
309div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
310{
311 unsigned long r0;
312 do_div64_32(r0, v1, v2, v3);
313 return r0;
314}
315
316static unsigned long do_fast_cp0_gettimeoffset(void)
317{
318 u32 count;
319 unsigned long res, tmp;
320 unsigned long r0;
321
322 /* Last jiffy when do_fast_gettimeoffset() was called. */
323 static unsigned long last_jiffies=0;
324 unsigned long quotient;
325
326 /*
327 * Cached "1/(clocks per usec)*2^32" value.
328 * It has to be recalculated once each jiffy.
329 */
330 static unsigned long cached_quotient=0;
331
332 tmp = jiffies;
333
334 quotient = cached_quotient;
335
336 if (tmp && last_jiffies != tmp) {
337 last_jiffies = tmp;
338 if (last_jiffies != 0) {
339 r0 = div64_32(timerhi, timerlo, tmp);
340 quotient = div64_32(USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0);
341 cached_quotient = quotient;
342 }
343 }
344
345 /* Get last timer tick in absolute kernel time */
346 count = read_c0_count();
347
348 /* .. relative to previous jiffy (32 bits is enough) */
349 count -= timerlo;
350
351 __asm__("multu\t%1,%2\n\t"
352 "mfhi\t%0"
353 : "=r" (res)
354 : "r" (count), "r" (quotient)
355 : "hi", "lo", GCC_REG_ACCUM);
356
357 /*
358 * Due to possible jiffies inconsistencies, we need to check
359 * the result so that we'll get a timer that is monotonic.
360 */
361 if (res >= USECS_PER_JIFFY)
362 res = USECS_PER_JIFFY-1;
363
364 return res;
365}
366
367#ifdef CONFIG_PM
368static unsigned long do_fast_pm_gettimeoffset(void)
369{
370 unsigned long pc0;
371 unsigned long offset;
372
373 pc0 = au_readl(SYS_TOYREAD);
374 au_sync();
375 offset = pc0 - last_pc0;
376 if (offset > 2*MATCH20_INC) {
377 printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
378 (unsigned)offset, (unsigned)last_pc0,
379 (unsigned)last_match20, (unsigned)pc0);
380 }
381 offset = (unsigned long)((offset * 305) / 10);
382 return offset;
383}
384#endif
385
386void __init plat_timer_setup(struct irqaction *irq) 293void __init plat_timer_setup(struct irqaction *irq)
387{ 294{
388 unsigned int est_freq; 295 unsigned int est_freq;
@@ -420,7 +327,6 @@ void __init plat_timer_setup(struct irqaction *irq)
420 unsigned int c0_status; 327 unsigned int c0_status;
421 328
422 printk("WARNING: no 32KHz clock found.\n"); 329 printk("WARNING: no 32KHz clock found.\n");
423 do_gettimeoffset = do_fast_cp0_gettimeoffset;
424 330
425 /* Ensure we get CPO_COUNTER interrupts. 331 /* Ensure we get CPO_COUNTER interrupts.
426 */ 332 */
@@ -445,19 +351,11 @@ void __init plat_timer_setup(struct irqaction *irq)
445 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); 351 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
446 startup_match20_interrupt(counter0_irq); 352 startup_match20_interrupt(counter0_irq);
447 353
448 do_gettimeoffset = do_fast_pm_gettimeoffset;
449
450 /* We can use the real 'wait' instruction. 354 /* We can use the real 'wait' instruction.
451 */ 355 */
452 allow_au1k_wait = 1; 356 allow_au1k_wait = 1;
453 } 357 }
454 358
455#else
456 /* We have to do this here instead of in timer_init because
457 * the generic code in arch/mips/kernel/time.c will write
458 * over our function pointer.
459 */
460 do_gettimeoffset = do_fast_cp0_gettimeoffset;
461#endif 359#endif
462} 360}
463 361
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c
index 8b953b9fc25c..043302b7fe58 100644
--- a/arch/mips/au1000/pb1200/board_setup.c
+++ b/arch/mips/au1000/pb1200/board_setup.c
@@ -55,7 +55,7 @@
55#endif 55#endif
56 56
57extern void _board_init_irq(void); 57extern void _board_init_irq(void);
58extern void (*board_init_irq)(void); 58extern void (*board_init_irq)(void);
59 59
60void board_reset (void) 60void board_reset (void)
61{ 61{
@@ -151,11 +151,7 @@ void __init board_setup(void)
151#endif 151#endif
152 152
153 /* Setup Pb1200 External Interrupt Controller */ 153 /* Setup Pb1200 External Interrupt Controller */
154 { 154 board_init_irq = _board_init_irq;
155 extern void (*board_init_irq)(void);
156 extern void _board_init_irq(void);
157 board_init_irq = _board_init_irq;
158 }
159} 155}
160 156
161int 157int
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 82e569d5b02c..4c46f0e73783 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -45,25 +45,22 @@ static inline void galileo_irq(void)
45{ 45{
46 unsigned int mask, pending, devfn; 46 unsigned int mask, pending, devfn;
47 47
48 mask = GALILEO_INL(GT_INTRMASK_OFS); 48 mask = GT_READ(GT_INTRMASK_OFS);
49 pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask; 49 pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
50 50
51 if (pending & GALILEO_INTR_T0EXP) { 51 if (pending & GT_INTR_T0EXP_MSK) {
52 52 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
53 GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS);
54 do_IRQ(COBALT_GALILEO_IRQ); 53 do_IRQ(COBALT_GALILEO_IRQ);
55 54 } else if (pending & GT_INTR_RETRYCTR0_MSK) {
56 } else if (pending & GALILEO_INTR_RETRY_CTR) { 55 devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
57 56 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
58 devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8; 57 printk(KERN_WARNING
59 GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS); 58 "Galileo: PCI retry count exceeded (%02x.%u)\n",
60 printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n", 59 PCI_SLOT(devfn), PCI_FUNC(devfn));
61 PCI_SLOT(devfn), PCI_FUNC(devfn));
62
63 } else { 60 } else {
64 61 GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
65 GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS); 62 printk(KERN_WARNING
66 printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending); 63 "Galileo: masking unexpected interrupt %08x\n", pending);
67 } 64 }
68} 65}
69 66
@@ -104,7 +101,7 @@ void __init arch_init_irq(void)
104 * Mask all Galileo interrupts. The Galileo 101 * Mask all Galileo interrupts. The Galileo
105 * handler is set in cobalt_timer_setup() 102 * handler is set in cobalt_timer_setup()
106 */ 103 */
107 GALILEO_OUTL(0, GT_INTRMASK_OFS); 104 GT_WRITE(GT_INTRMASK_OFS, 0);
108 105
109 init_i8259_irqs(); /* 0 ... 15 */ 106 init_i8259_irqs(); /* 0 ... 15 */
110 mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ 107 mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index bf9dc72b9720..e8f0f20b852d 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -51,23 +51,23 @@ const char *get_system_type(void)
51void __init plat_timer_setup(struct irqaction *irq) 51void __init plat_timer_setup(struct irqaction *irq)
52{ 52{
53 /* Load timer value for HZ (TCLK is 50MHz) */ 53 /* Load timer value for HZ (TCLK is 50MHz) */
54 GALILEO_OUTL(50*1000*1000 / HZ, GT_TC0_OFS); 54 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
55 55
56 /* Enable timer */ 56 /* Enable timer */
57 GALILEO_OUTL(GALILEO_ENTC0 | GALILEO_SELTC0, GT_TC_CONTROL_OFS); 57 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
58 58
59 /* Register interrupt */ 59 /* Register interrupt */
60 setup_irq(COBALT_GALILEO_IRQ, irq); 60 setup_irq(COBALT_GALILEO_IRQ, irq);
61 61
62 /* Enable interrupt */ 62 /* Enable interrupt */
63 GALILEO_OUTL(GALILEO_INTR_T0EXP | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); 63 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
64} 64}
65 65
66extern struct pci_ops gt64111_pci_ops; 66extern struct pci_ops gt64111_pci_ops;
67 67
68static struct resource cobalt_mem_resource = { 68static struct resource cobalt_mem_resource = {
69 .start = GT64111_MEM_BASE, 69 .start = GT_DEF_PCI0_MEM0_BASE,
70 .end = GT64111_MEM_END, 70 .end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1,
71 .name = "PCI memory", 71 .name = "PCI memory",
72 .flags = IORESOURCE_MEM 72 .flags = IORESOURCE_MEM
73}; 73};
@@ -115,7 +115,7 @@ static struct pci_controller cobalt_pci_controller = {
115 .mem_resource = &cobalt_mem_resource, 115 .mem_resource = &cobalt_mem_resource,
116 .mem_offset = 0, 116 .mem_offset = 0,
117 .io_resource = &cobalt_io_resource, 117 .io_resource = &cobalt_io_resource,
118 .io_offset = 0 - GT64111_IO_BASE 118 .io_offset = 0 - GT_DEF_PCI0_IO_BASE,
119}; 119};
120 120
121void __init plat_mem_setup(void) 121void __init plat_mem_setup(void)
@@ -128,7 +128,7 @@ void __init plat_mem_setup(void)
128 _machine_halt = cobalt_machine_halt; 128 _machine_halt = cobalt_machine_halt;
129 pm_power_off = cobalt_machine_power_off; 129 pm_power_off = cobalt_machine_power_off;
130 130
131 set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE)); 131 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
132 132
133 /* I/O port resource must include UART and LCD/buttons */ 133 /* I/O port resource must include UART and LCD/buttons */
134 ioport_resource.end = 0x0fffffff; 134 ioport_resource.end = 0x0fffffff;
@@ -139,7 +139,7 @@ void __init plat_mem_setup(void)
139 139
140 /* Read the cobalt id register out of the PCI config space */ 140 /* Read the cobalt id register out of the PCI config space */
141 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3)); 141 PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
142 cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 142 cobalt_board_id = GT_READ(GT_PCI0_CFGDATA_OFS);
143 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8); 143 cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
144 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id); 144 cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
145 145
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
index 26b0b9883496..280a8001eacf 100644
--- a/arch/mips/configs/pnx8550-jbs_defconfig
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.18-rc1 3# Linux kernel version: 2.6.19-rc2
4# Thu Jul 6 10:04:18 2006 4# Sat Oct 14 23:01:16 2006
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -25,8 +25,6 @@ CONFIG_MIPS=y
25# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
26# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
27# CONFIG_MIPS_EV64120 is not set 27# CONFIG_MIPS_EV64120 is not set
28# CONFIG_MIPS_IVR is not set
29# CONFIG_MIPS_ITE8172 is not set
30# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set 29# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
@@ -41,13 +39,13 @@ CONFIG_MIPS=y
41# CONFIG_MOMENCO_OCELOT_G is not set 39# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set 40# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_V2PCI is not set 41# CONFIG_PNX8550_V2PCI is not set
44# CONFIG_PNX8550_JBS is not set 42CONFIG_PNX8550_JBS=y
45# CONFIG_DDB5477 is not set 43# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 44# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 45# CONFIG_PMC_YOSEMITE is not set
48# CONFIG_QEMU is not set 46# CONFIG_QEMU is not set
49# CONFIG_MARKEINS is not set 47# CONFIG_MARKEINS is not set
50CONFIG_SGI_IP22=y 48# CONFIG_SGI_IP22 is not set
51# CONFIG_SGI_IP27 is not set 49# CONFIG_SGI_IP27 is not set
52# CONFIG_SGI_IP32 is not set 50# CONFIG_SGI_IP32 is not set
53# CONFIG_SIBYTE_BIGSUR is not set 51# CONFIG_SIBYTE_BIGSUR is not set
@@ -67,25 +65,21 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
67CONFIG_GENERIC_FIND_NEXT_BIT=y 65CONFIG_GENERIC_FIND_NEXT_BIT=y
68CONFIG_GENERIC_HWEIGHT=y 66CONFIG_GENERIC_HWEIGHT=y
69CONFIG_GENERIC_CALIBRATE_DELAY=y 67CONFIG_GENERIC_CALIBRATE_DELAY=y
68CONFIG_GENERIC_TIME=y
70CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 69CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
71CONFIG_ARC=y
72CONFIG_DMA_NONCOHERENT=y 70CONFIG_DMA_NONCOHERENT=y
73CONFIG_DMA_NEED_PCI_MAP_STATE=y 71CONFIG_DMA_NEED_PCI_MAP_STATE=y
74CONFIG_CPU_BIG_ENDIAN=y 72# CONFIG_CPU_BIG_ENDIAN is not set
75# CONFIG_CPU_LITTLE_ENDIAN is not set 73CONFIG_CPU_LITTLE_ENDIAN=y
76CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y 74CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
77CONFIG_IRQ_CPU=y 75CONFIG_PNX8550=y
78CONFIG_SWAP_IO_SPACE=y 76CONFIG_SOC_PNX8550=y
79CONFIG_ARC32=y
80CONFIG_BOOT_ELF32=y
81CONFIG_MIPS_L1_CACHE_SHIFT=5 77CONFIG_MIPS_L1_CACHE_SHIFT=5
82# CONFIG_ARC_CONSOLE is not set
83CONFIG_ARC_PROMLIB=y
84 78
85# 79#
86# CPU selection 80# CPU selection
87# 81#
88# CONFIG_CPU_MIPS32_R1 is not set 82CONFIG_CPU_MIPS32_R1=y
89# CONFIG_CPU_MIPS32_R2 is not set 83# CONFIG_CPU_MIPS32_R2 is not set
90# CONFIG_CPU_MIPS64_R1 is not set 84# CONFIG_CPU_MIPS64_R1 is not set
91# CONFIG_CPU_MIPS64_R2 is not set 85# CONFIG_CPU_MIPS64_R2 is not set
@@ -93,7 +87,7 @@ CONFIG_ARC_PROMLIB=y
93# CONFIG_CPU_TX39XX is not set 87# CONFIG_CPU_TX39XX is not set
94# CONFIG_CPU_VR41XX is not set 88# CONFIG_CPU_VR41XX is not set
95# CONFIG_CPU_R4300 is not set 89# CONFIG_CPU_R4300 is not set
96CONFIG_CPU_R4X00=y 90# CONFIG_CPU_R4X00 is not set
97# CONFIG_CPU_TX49XX is not set 91# CONFIG_CPU_TX49XX is not set
98# CONFIG_CPU_R5000 is not set 92# CONFIG_CPU_R5000 is not set
99# CONFIG_CPU_R5432 is not set 93# CONFIG_CPU_R5432 is not set
@@ -104,12 +98,11 @@ CONFIG_CPU_R4X00=y
104# CONFIG_CPU_RM7000 is not set 98# CONFIG_CPU_RM7000 is not set
105# CONFIG_CPU_RM9000 is not set 99# CONFIG_CPU_RM9000 is not set
106# CONFIG_CPU_SB1 is not set 100# CONFIG_CPU_SB1 is not set
107CONFIG_SYS_HAS_CPU_R4X00=y 101CONFIG_SYS_HAS_CPU_MIPS32_R1=y
108CONFIG_SYS_HAS_CPU_R5000=y 102CONFIG_CPU_MIPS32=y
103CONFIG_CPU_MIPSR1=y
109CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y 104CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
110CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
111CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y 105CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
112CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
113 106
114# 107#
115# Kernel type 108# Kernel type
@@ -120,17 +113,17 @@ CONFIG_PAGE_SIZE_4KB=y
120# CONFIG_PAGE_SIZE_8KB is not set 113# CONFIG_PAGE_SIZE_8KB is not set
121# CONFIG_PAGE_SIZE_16KB is not set 114# CONFIG_PAGE_SIZE_16KB is not set
122# CONFIG_PAGE_SIZE_64KB is not set 115# CONFIG_PAGE_SIZE_64KB is not set
123CONFIG_BOARD_SCACHE=y 116CONFIG_CPU_HAS_PREFETCH=y
124CONFIG_IP22_CPU_SCACHE=y
125CONFIG_MIPS_MT_DISABLED=y 117CONFIG_MIPS_MT_DISABLED=y
126# CONFIG_MIPS_MT_SMTC is not set
127# CONFIG_MIPS_MT_SMP is not set 118# CONFIG_MIPS_MT_SMP is not set
119# CONFIG_MIPS_MT_SMTC is not set
128# CONFIG_MIPS_VPE_LOADER is not set 120# CONFIG_MIPS_VPE_LOADER is not set
129# CONFIG_64BIT_PHYS_ADDR is not set 121# CONFIG_64BIT_PHYS_ADDR is not set
130CONFIG_CPU_HAS_LLSC=y 122CONFIG_CPU_HAS_LLSC=y
131CONFIG_CPU_HAS_SYNC=y 123CONFIG_CPU_HAS_SYNC=y
132CONFIG_GENERIC_HARDIRQS=y 124CONFIG_GENERIC_HARDIRQS=y
133CONFIG_GENERIC_IRQ_PROBE=y 125CONFIG_GENERIC_IRQ_PROBE=y
126CONFIG_CPU_SUPPORTS_HIGHMEM=y
134CONFIG_ARCH_FLATMEM_ENABLE=y 127CONFIG_ARCH_FLATMEM_ENABLE=y
135CONFIG_SELECT_MEMORY_MODEL=y 128CONFIG_SELECT_MEMORY_MODEL=y
136CONFIG_FLATMEM_MANUAL=y 129CONFIG_FLATMEM_MANUAL=y
@@ -144,12 +137,12 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
144# CONFIG_HZ_48 is not set 137# CONFIG_HZ_48 is not set
145# CONFIG_HZ_100 is not set 138# CONFIG_HZ_100 is not set
146# CONFIG_HZ_128 is not set 139# CONFIG_HZ_128 is not set
147# CONFIG_HZ_250 is not set 140CONFIG_HZ_250=y
148# CONFIG_HZ_256 is not set 141# CONFIG_HZ_256 is not set
149CONFIG_HZ_1000=y 142# CONFIG_HZ_1000 is not set
150# CONFIG_HZ_1024 is not set 143# CONFIG_HZ_1024 is not set
151CONFIG_SYS_SUPPORTS_ARBIT_HZ=y 144CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
152CONFIG_HZ=1000 145CONFIG_HZ=250
153CONFIG_PREEMPT_NONE=y 146CONFIG_PREEMPT_NONE=y
154# CONFIG_PREEMPT_VOLUNTARY is not set 147# CONFIG_PREEMPT_VOLUNTARY is not set
155# CONFIG_PREEMPT is not set 148# CONFIG_PREEMPT is not set
@@ -171,16 +164,20 @@ CONFIG_LOCALVERSION=""
171CONFIG_LOCALVERSION_AUTO=y 164CONFIG_LOCALVERSION_AUTO=y
172CONFIG_SWAP=y 165CONFIG_SWAP=y
173CONFIG_SYSVIPC=y 166CONFIG_SYSVIPC=y
167# CONFIG_IPC_NS is not set
174# CONFIG_POSIX_MQUEUE is not set 168# CONFIG_POSIX_MQUEUE is not set
175# CONFIG_BSD_PROCESS_ACCT is not set 169# CONFIG_BSD_PROCESS_ACCT is not set
176CONFIG_SYSCTL=y 170# CONFIG_TASKSTATS is not set
171# CONFIG_UTS_NS is not set
177# CONFIG_AUDIT is not set 172# CONFIG_AUDIT is not set
178CONFIG_IKCONFIG=y 173CONFIG_IKCONFIG=y
179CONFIG_IKCONFIG_PROC=y 174CONFIG_IKCONFIG_PROC=y
180# CONFIG_RELAY is not set 175# CONFIG_RELAY is not set
181CONFIG_INITRAMFS_SOURCE="" 176CONFIG_INITRAMFS_SOURCE=""
182# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 177# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
178CONFIG_SYSCTL=y
183CONFIG_EMBEDDED=y 179CONFIG_EMBEDDED=y
180# CONFIG_SYSCTL_SYSCALL is not set
184CONFIG_KALLSYMS=y 181CONFIG_KALLSYMS=y
185# CONFIG_KALLSYMS_ALL is not set 182# CONFIG_KALLSYMS_ALL is not set
186# CONFIG_KALLSYMS_EXTRA_PASS is not set 183# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -189,12 +186,12 @@ CONFIG_PRINTK=y
189CONFIG_BUG=y 186CONFIG_BUG=y
190CONFIG_ELF_CORE=y 187CONFIG_ELF_CORE=y
191CONFIG_BASE_FULL=y 188CONFIG_BASE_FULL=y
192CONFIG_RT_MUTEXES=y
193CONFIG_FUTEX=y 189CONFIG_FUTEX=y
194CONFIG_EPOLL=y 190CONFIG_EPOLL=y
195CONFIG_SHMEM=y 191CONFIG_SHMEM=y
196CONFIG_SLAB=y 192CONFIG_SLAB=y
197CONFIG_VM_EVENT_COUNTERS=y 193CONFIG_VM_EVENT_COUNTERS=y
194CONFIG_RT_MUTEXES=y
198# CONFIG_TINY_SHMEM is not set 195# CONFIG_TINY_SHMEM is not set
199CONFIG_BASE_SMALL=0 196CONFIG_BASE_SMALL=0
200# CONFIG_SLOB is not set 197# CONFIG_SLOB is not set
@@ -211,6 +208,7 @@ CONFIG_KMOD=y
211# 208#
212# Block layer 209# Block layer
213# 210#
211CONFIG_BLOCK=y
214# CONFIG_LBD is not set 212# CONFIG_LBD is not set
215# CONFIG_BLK_DEV_IO_TRACE is not set 213# CONFIG_BLK_DEV_IO_TRACE is not set
216# CONFIG_LSF is not set 214# CONFIG_LSF is not set
@@ -231,8 +229,10 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
231# 229#
232# Bus options (PCI, PCMCIA, EISA, ISA, TC) 230# Bus options (PCI, PCMCIA, EISA, ISA, TC)
233# 231#
234CONFIG_HW_HAS_EISA=y 232CONFIG_HW_HAS_PCI=y
235# CONFIG_EISA is not set 233CONFIG_PCI=y
234# CONFIG_PCI_MULTITHREAD_PROBE is not set
235# CONFIG_PCI_DEBUG is not set
236CONFIG_MMU=y 236CONFIG_MMU=y
237 237
238# 238#
@@ -243,6 +243,7 @@ CONFIG_MMU=y
243# 243#
244# PCI Hotplug Support 244# PCI Hotplug Support
245# 245#
246# CONFIG_HOTPLUG_PCI is not set
246 247
247# 248#
248# Executable file formats 249# Executable file formats
@@ -265,6 +266,7 @@ CONFIG_PACKET=y
265CONFIG_UNIX=y 266CONFIG_UNIX=y
266CONFIG_XFRM=y 267CONFIG_XFRM=y
267# CONFIG_XFRM_USER is not set 268# CONFIG_XFRM_USER is not set
269# CONFIG_XFRM_SUB_POLICY is not set
268# CONFIG_NET_KEY is not set 270# CONFIG_NET_KEY is not set
269CONFIG_INET=y 271CONFIG_INET=y
270# CONFIG_IP_MULTICAST is not set 272# CONFIG_IP_MULTICAST is not set
@@ -283,16 +285,18 @@ CONFIG_IP_PNP_BOOTP=y
283# CONFIG_INET_IPCOMP is not set 285# CONFIG_INET_IPCOMP is not set
284# CONFIG_INET_XFRM_TUNNEL is not set 286# CONFIG_INET_XFRM_TUNNEL is not set
285# CONFIG_INET_TUNNEL is not set 287# CONFIG_INET_TUNNEL is not set
286CONFIG_INET_XFRM_MODE_TRANSPORT=m 288CONFIG_INET_XFRM_MODE_TRANSPORT=y
287CONFIG_INET_XFRM_MODE_TUNNEL=m 289CONFIG_INET_XFRM_MODE_TUNNEL=y
290CONFIG_INET_XFRM_MODE_BEET=y
288CONFIG_INET_DIAG=y 291CONFIG_INET_DIAG=y
289CONFIG_INET_TCP_DIAG=y 292CONFIG_INET_TCP_DIAG=y
290# CONFIG_TCP_CONG_ADVANCED is not set 293# CONFIG_TCP_CONG_ADVANCED is not set
291CONFIG_TCP_CONG_BIC=y 294CONFIG_TCP_CONG_CUBIC=y
295CONFIG_DEFAULT_TCP_CONG="cubic"
292# CONFIG_IPV6 is not set 296# CONFIG_IPV6 is not set
293# CONFIG_INET6_XFRM_TUNNEL is not set 297# CONFIG_INET6_XFRM_TUNNEL is not set
294# CONFIG_INET6_TUNNEL is not set 298# CONFIG_INET6_TUNNEL is not set
295CONFIG_NETWORK_SECMARK=y 299# CONFIG_NETWORK_SECMARK is not set
296# CONFIG_NETFILTER is not set 300# CONFIG_NETFILTER is not set
297 301
298# 302#
@@ -318,7 +322,6 @@ CONFIG_NETWORK_SECMARK=y
318# CONFIG_ATALK is not set 322# CONFIG_ATALK is not set
319# CONFIG_X25 is not set 323# CONFIG_X25 is not set
320# CONFIG_LAPB is not set 324# CONFIG_LAPB is not set
321# CONFIG_NET_DIVERT is not set
322# CONFIG_ECONET is not set 325# CONFIG_ECONET is not set
323# CONFIG_WAN_ROUTER is not set 326# CONFIG_WAN_ROUTER is not set
324 327
@@ -371,13 +374,20 @@ CONFIG_FW_LOADER=y
371# 374#
372# Block devices 375# Block devices
373# 376#
377# CONFIG_BLK_CPQ_DA is not set
378# CONFIG_BLK_CPQ_CISS_DA is not set
379# CONFIG_BLK_DEV_DAC960 is not set
380# CONFIG_BLK_DEV_UMEM is not set
374# CONFIG_BLK_DEV_COW_COMMON is not set 381# CONFIG_BLK_DEV_COW_COMMON is not set
375CONFIG_BLK_DEV_LOOP=y 382CONFIG_BLK_DEV_LOOP=y
376# CONFIG_BLK_DEV_CRYPTOLOOP is not set 383# CONFIG_BLK_DEV_CRYPTOLOOP is not set
377# CONFIG_BLK_DEV_NBD is not set 384# CONFIG_BLK_DEV_NBD is not set
385# CONFIG_BLK_DEV_SX8 is not set
386# CONFIG_BLK_DEV_UB is not set
378CONFIG_BLK_DEV_RAM=y 387CONFIG_BLK_DEV_RAM=y
379CONFIG_BLK_DEV_RAM_COUNT=16 388CONFIG_BLK_DEV_RAM_COUNT=16
380CONFIG_BLK_DEV_RAM_SIZE=8192 389CONFIG_BLK_DEV_RAM_SIZE=8192
390CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
381CONFIG_BLK_DEV_INITRD=y 391CONFIG_BLK_DEV_INITRD=y
382# CONFIG_CDROM_PKTCDVD is not set 392# CONFIG_CDROM_PKTCDVD is not set
383# CONFIG_ATA_OVER_ETH is not set 393# CONFIG_ATA_OVER_ETH is not set
@@ -386,6 +396,7 @@ CONFIG_BLK_DEV_INITRD=y
386# ATA/ATAPI/MFM/RLL support 396# ATA/ATAPI/MFM/RLL support
387# 397#
388CONFIG_IDE=y 398CONFIG_IDE=y
399CONFIG_IDE_MAX_HWIFS=4
389CONFIG_BLK_DEV_IDE=y 400CONFIG_BLK_DEV_IDE=y
390 401
391# 402#
@@ -404,8 +415,39 @@ CONFIG_BLK_DEV_IDESCSI=y
404# IDE chipset support/bugfixes 415# IDE chipset support/bugfixes
405# 416#
406CONFIG_IDE_GENERIC=y 417CONFIG_IDE_GENERIC=y
418CONFIG_BLK_DEV_IDEPCI=y
419CONFIG_IDEPCI_SHARE_IRQ=y
420CONFIG_BLK_DEV_OFFBOARD=y
421CONFIG_BLK_DEV_GENERIC=y
422# CONFIG_BLK_DEV_OPTI621 is not set
423CONFIG_BLK_DEV_IDEDMA_PCI=y
424# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
425# CONFIG_IDEDMA_PCI_AUTO is not set
426# CONFIG_BLK_DEV_AEC62XX is not set
427# CONFIG_BLK_DEV_ALI15X3 is not set
428# CONFIG_BLK_DEV_AMD74XX is not set
429# CONFIG_BLK_DEV_CMD64X is not set
430# CONFIG_BLK_DEV_TRIFLEX is not set
431# CONFIG_BLK_DEV_CY82C693 is not set
432# CONFIG_BLK_DEV_CS5520 is not set
433# CONFIG_BLK_DEV_CS5530 is not set
434# CONFIG_BLK_DEV_HPT34X is not set
435CONFIG_BLK_DEV_HPT366=y
436# CONFIG_BLK_DEV_JMICRON is not set
437# CONFIG_BLK_DEV_SC1200 is not set
438# CONFIG_BLK_DEV_PIIX is not set
439# CONFIG_BLK_DEV_IT821X is not set
440# CONFIG_BLK_DEV_NS87415 is not set
441# CONFIG_BLK_DEV_PDC202XX_OLD is not set
442# CONFIG_BLK_DEV_PDC202XX_NEW is not set
443# CONFIG_BLK_DEV_SVWKS is not set
444# CONFIG_BLK_DEV_SIIMAGE is not set
445# CONFIG_BLK_DEV_SLC90E66 is not set
446# CONFIG_BLK_DEV_TRM290 is not set
447# CONFIG_BLK_DEV_VIA82CXXX is not set
407# CONFIG_IDE_ARM is not set 448# CONFIG_IDE_ARM is not set
408# CONFIG_BLK_DEV_IDEDMA is not set 449CONFIG_BLK_DEV_IDEDMA=y
450# CONFIG_IDEDMA_IVB is not set
409# CONFIG_IDEDMA_AUTO is not set 451# CONFIG_IDEDMA_AUTO is not set
410# CONFIG_BLK_DEV_HD is not set 452# CONFIG_BLK_DEV_HD is not set
411 453
@@ -414,6 +456,7 @@ CONFIG_IDE_GENERIC=y
414# 456#
415# CONFIG_RAID_ATTRS is not set 457# CONFIG_RAID_ATTRS is not set
416CONFIG_SCSI=y 458CONFIG_SCSI=y
459CONFIG_SCSI_NETLINK=y
417CONFIG_SCSI_PROC_FS=y 460CONFIG_SCSI_PROC_FS=y
418 461
419# 462#
@@ -434,22 +477,54 @@ CONFIG_SCSI_CONSTANTS=y
434# CONFIG_SCSI_LOGGING is not set 477# CONFIG_SCSI_LOGGING is not set
435 478
436# 479#
437# SCSI Transport Attributes 480# SCSI Transports
438# 481#
439# CONFIG_SCSI_SPI_ATTRS is not set 482# CONFIG_SCSI_SPI_ATTRS is not set
440CONFIG_SCSI_FC_ATTRS=y 483CONFIG_SCSI_FC_ATTRS=y
441CONFIG_SCSI_ISCSI_ATTRS=m 484CONFIG_SCSI_ISCSI_ATTRS=m
442# CONFIG_SCSI_SAS_ATTRS is not set 485# CONFIG_SCSI_SAS_ATTRS is not set
486# CONFIG_SCSI_SAS_LIBSAS is not set
443 487
444# 488#
445# SCSI low-level drivers 489# SCSI low-level drivers
446# 490#
447CONFIG_ISCSI_TCP=m 491CONFIG_ISCSI_TCP=m
448# CONFIG_SGIWD93_SCSI is not set 492# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
449# CONFIG_SCSI_SATA is not set 493# CONFIG_SCSI_3W_9XXX is not set
494# CONFIG_SCSI_ACARD is not set
495# CONFIG_SCSI_AACRAID is not set
496# CONFIG_SCSI_AIC7XXX is not set
497# CONFIG_SCSI_AIC7XXX_OLD is not set
498# CONFIG_SCSI_AIC79XX is not set
499# CONFIG_SCSI_AIC94XX is not set
500# CONFIG_SCSI_DPT_I2O is not set
501# CONFIG_SCSI_ARCMSR is not set
502# CONFIG_MEGARAID_NEWGEN is not set
503# CONFIG_MEGARAID_LEGACY is not set
504# CONFIG_MEGARAID_SAS is not set
505# CONFIG_SCSI_HPTIOP is not set
506# CONFIG_SCSI_DMX3191D is not set
507# CONFIG_SCSI_FUTURE_DOMAIN is not set
508# CONFIG_SCSI_IPS is not set
509# CONFIG_SCSI_INITIO is not set
510# CONFIG_SCSI_INIA100 is not set
511# CONFIG_SCSI_STEX is not set
512# CONFIG_SCSI_SYM53C8XX_2 is not set
513# CONFIG_SCSI_QLOGIC_1280 is not set
514# CONFIG_SCSI_QLA_FC is not set
515# CONFIG_SCSI_QLA_ISCSI is not set
516# CONFIG_SCSI_LPFC is not set
517# CONFIG_SCSI_DC395x is not set
518# CONFIG_SCSI_DC390T is not set
519# CONFIG_SCSI_NSP32 is not set
450# CONFIG_SCSI_DEBUG is not set 520# CONFIG_SCSI_DEBUG is not set
451 521
452# 522#
523# Serial ATA (prod) and Parallel ATA (experimental) drivers
524#
525# CONFIG_ATA is not set
526
527#
453# Multi-device support (RAID and LVM) 528# Multi-device support (RAID and LVM)
454# 529#
455# CONFIG_MD is not set 530# CONFIG_MD is not set
@@ -458,14 +533,19 @@ CONFIG_ISCSI_TCP=m
458# Fusion MPT device support 533# Fusion MPT device support
459# 534#
460# CONFIG_FUSION is not set 535# CONFIG_FUSION is not set
536# CONFIG_FUSION_SPI is not set
537# CONFIG_FUSION_FC is not set
538# CONFIG_FUSION_SAS is not set
461 539
462# 540#
463# IEEE 1394 (FireWire) support 541# IEEE 1394 (FireWire) support
464# 542#
543# CONFIG_IEEE1394 is not set
465 544
466# 545#
467# I2O device support 546# I2O device support
468# 547#
548# CONFIG_I2O is not set
469 549
470# 550#
471# Network device support 551# Network device support
@@ -477,6 +557,11 @@ CONFIG_NETDEVICES=y
477# CONFIG_TUN is not set 557# CONFIG_TUN is not set
478 558
479# 559#
560# ARCnet devices
561#
562# CONFIG_ARCNET is not set
563
564#
480# PHY device support 565# PHY device support
481# 566#
482# CONFIG_PHYLIB is not set 567# CONFIG_PHYLIB is not set
@@ -486,20 +571,73 @@ CONFIG_NETDEVICES=y
486# 571#
487CONFIG_NET_ETHERNET=y 572CONFIG_NET_ETHERNET=y
488CONFIG_MII=y 573CONFIG_MII=y
574# CONFIG_HAPPYMEAL is not set
575# CONFIG_SUNGEM is not set
576# CONFIG_CASSINI is not set
577# CONFIG_NET_VENDOR_3COM is not set
489# CONFIG_DM9000 is not set 578# CONFIG_DM9000 is not set
490# CONFIG_SGISEEQ is not set 579
580#
581# Tulip family network device support
582#
583# CONFIG_NET_TULIP is not set
584# CONFIG_HP100 is not set
585CONFIG_NET_PCI=y
586# CONFIG_PCNET32 is not set
587# CONFIG_AMD8111_ETH is not set
588# CONFIG_ADAPTEC_STARFIRE is not set
589# CONFIG_B44 is not set
590# CONFIG_FORCEDETH is not set
591# CONFIG_DGRS is not set
592# CONFIG_EEPRO100 is not set
593# CONFIG_E100 is not set
594# CONFIG_FEALNX is not set
595# CONFIG_NATSEMI is not set
596# CONFIG_NE2K_PCI is not set
597# CONFIG_8139CP is not set
598CONFIG_8139TOO=y
599# CONFIG_8139TOO_PIO is not set
600CONFIG_8139TOO_TUNE_TWISTER=y
601CONFIG_8139TOO_8129=y
602# CONFIG_8139_OLD_RX_RESET is not set
603# CONFIG_SIS900 is not set
604# CONFIG_EPIC100 is not set
605# CONFIG_SUNDANCE is not set
606# CONFIG_TLAN is not set
607# CONFIG_VIA_RHINE is not set
608# CONFIG_LAN_SAA9730 is not set
491 609
492# 610#
493# Ethernet (1000 Mbit) 611# Ethernet (1000 Mbit)
494# 612#
613# CONFIG_ACENIC is not set
614# CONFIG_DL2K is not set
615# CONFIG_E1000 is not set
616# CONFIG_NS83820 is not set
617# CONFIG_HAMACHI is not set
618# CONFIG_YELLOWFIN is not set
619# CONFIG_R8169 is not set
620# CONFIG_SIS190 is not set
621# CONFIG_SKGE is not set
622# CONFIG_SKY2 is not set
623# CONFIG_SK98LIN is not set
624# CONFIG_VIA_VELOCITY is not set
625# CONFIG_TIGON3 is not set
626# CONFIG_BNX2 is not set
627# CONFIG_QLA3XXX is not set
495 628
496# 629#
497# Ethernet (10000 Mbit) 630# Ethernet (10000 Mbit)
498# 631#
632# CONFIG_CHELSIO_T1 is not set
633# CONFIG_IXGB is not set
634# CONFIG_S2IO is not set
635# CONFIG_MYRI10GE is not set
499 636
500# 637#
501# Token Ring devices 638# Token Ring devices
502# 639#
640# CONFIG_TR is not set
503 641
504# 642#
505# Wireless LAN (non-hamradio) 643# Wireless LAN (non-hamradio)
@@ -510,8 +648,11 @@ CONFIG_MII=y
510# Wan interfaces 648# Wan interfaces
511# 649#
512# CONFIG_WAN is not set 650# CONFIG_WAN is not set
651# CONFIG_FDDI is not set
652# CONFIG_HIPPI is not set
513# CONFIG_PPP is not set 653# CONFIG_PPP is not set
514# CONFIG_SLIP is not set 654# CONFIG_SLIP is not set
655# CONFIG_NET_FC is not set
515# CONFIG_SHAPER is not set 656# CONFIG_SHAPER is not set
516# CONFIG_NETCONSOLE is not set 657# CONFIG_NETCONSOLE is not set
517# CONFIG_NETPOLL is not set 658# CONFIG_NETPOLL is not set
@@ -531,6 +672,7 @@ CONFIG_MII=y
531# Input device support 672# Input device support
532# 673#
533CONFIG_INPUT=y 674CONFIG_INPUT=y
675# CONFIG_INPUT_FF_MEMLESS is not set
534 676
535# 677#
536# Userland interfaces 678# Userland interfaces
@@ -556,6 +698,7 @@ CONFIG_INPUT=y
556CONFIG_SERIO=y 698CONFIG_SERIO=y
557# CONFIG_SERIO_I8042 is not set 699# CONFIG_SERIO_I8042 is not set
558# CONFIG_SERIO_SERPORT is not set 700# CONFIG_SERIO_SERPORT is not set
701# CONFIG_SERIO_PCIPS2 is not set
559CONFIG_SERIO_LIBPS2=y 702CONFIG_SERIO_LIBPS2=y
560# CONFIG_SERIO_RAW is not set 703# CONFIG_SERIO_RAW is not set
561# CONFIG_GAMEPORT is not set 704# CONFIG_GAMEPORT is not set
@@ -566,7 +709,7 @@ CONFIG_SERIO_LIBPS2=y
566CONFIG_VT=y 709CONFIG_VT=y
567CONFIG_VT_CONSOLE=y 710CONFIG_VT_CONSOLE=y
568CONFIG_HW_CONSOLE=y 711CONFIG_HW_CONSOLE=y
569CONFIG_VT_HW_CONSOLE_BINDING=y 712# CONFIG_VT_HW_CONSOLE_BINDING is not set
570# CONFIG_SERIAL_NONSTANDARD is not set 713# CONFIG_SERIAL_NONSTANDARD is not set
571 714
572# 715#
@@ -577,7 +720,8 @@ CONFIG_VT_HW_CONSOLE_BINDING=y
577# 720#
578# Non-8250 serial port support 721# Non-8250 serial port support
579# 722#
580# CONFIG_SERIAL_IP22_ZILOG is not set 723# CONFIG_SERIAL_IP3106 is not set
724# CONFIG_SERIAL_JSM is not set
581CONFIG_UNIX98_PTYS=y 725CONFIG_UNIX98_PTYS=y
582CONFIG_LEGACY_PTYS=y 726CONFIG_LEGACY_PTYS=y
583CONFIG_LEGACY_PTY_COUNT=256 727CONFIG_LEGACY_PTY_COUNT=256
@@ -591,16 +735,17 @@ CONFIG_LEGACY_PTY_COUNT=256
591# Watchdog Cards 735# Watchdog Cards
592# 736#
593# CONFIG_WATCHDOG is not set 737# CONFIG_WATCHDOG is not set
594# CONFIG_HW_RANDOM is not set 738CONFIG_HW_RANDOM=y
595# CONFIG_RTC is not set 739# CONFIG_RTC is not set
596# CONFIG_SGI_DS1286 is not set
597# CONFIG_GEN_RTC is not set 740# CONFIG_GEN_RTC is not set
598# CONFIG_DTLK is not set 741# CONFIG_DTLK is not set
599# CONFIG_R3964 is not set 742# CONFIG_R3964 is not set
743# CONFIG_APPLICOM is not set
600 744
601# 745#
602# Ftape, the floppy tape device driver 746# Ftape, the floppy tape device driver
603# 747#
748# CONFIG_DRM is not set
604# CONFIG_RAW_DRIVER is not set 749# CONFIG_RAW_DRIVER is not set
605 750
606# 751#
@@ -631,35 +776,37 @@ CONFIG_HWMON=y
631# CONFIG_HWMON_VID is not set 776# CONFIG_HWMON_VID is not set
632# CONFIG_SENSORS_ABITUGURU is not set 777# CONFIG_SENSORS_ABITUGURU is not set
633# CONFIG_SENSORS_F71805F is not set 778# CONFIG_SENSORS_F71805F is not set
779# CONFIG_SENSORS_VT1211 is not set
634# CONFIG_HWMON_DEBUG_CHIP is not set 780# CONFIG_HWMON_DEBUG_CHIP is not set
635 781
636# 782#
637# Misc devices 783# Misc devices
638# 784#
785# CONFIG_TIFM_CORE is not set
639 786
640# 787#
641# Multimedia devices 788# Multimedia devices
642# 789#
643# CONFIG_VIDEO_DEV is not set 790# CONFIG_VIDEO_DEV is not set
644CONFIG_VIDEO_V4L2=y
645 791
646# 792#
647# Digital Video Broadcasting Devices 793# Digital Video Broadcasting Devices
648# 794#
649# CONFIG_DVB is not set 795# CONFIG_DVB is not set
796# CONFIG_USB_DABUSB is not set
650 797
651# 798#
652# Graphics support 799# Graphics support
653# 800#
654# CONFIG_FIRMWARE_EDID is not set 801CONFIG_FIRMWARE_EDID=y
655# CONFIG_FB is not set 802# CONFIG_FB is not set
656 803
657# 804#
658# Console display driver support 805# Console display driver support
659# 806#
660# CONFIG_VGA_CONSOLE is not set 807# CONFIG_VGA_CONSOLE is not set
661# CONFIG_SGI_NEWPORT_CONSOLE is not set
662CONFIG_DUMMY_CONSOLE=y 808CONFIG_DUMMY_CONSOLE=y
809# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
663 810
664# 811#
665# Sound 812# Sound
@@ -669,15 +816,131 @@ CONFIG_DUMMY_CONSOLE=y
669# 816#
670# USB support 817# USB support
671# 818#
672# CONFIG_USB_ARCH_HAS_HCD is not set 819CONFIG_USB_ARCH_HAS_HCD=y
673# CONFIG_USB_ARCH_HAS_OHCI is not set 820CONFIG_USB_ARCH_HAS_OHCI=y
674# CONFIG_USB_ARCH_HAS_EHCI is not set 821CONFIG_USB_ARCH_HAS_EHCI=y
822CONFIG_USB=y
823# CONFIG_USB_DEBUG is not set
824
825#
826# Miscellaneous USB options
827#
828# CONFIG_USB_DEVICEFS is not set
829# CONFIG_USB_BANDWIDTH is not set
830# CONFIG_USB_DYNAMIC_MINORS is not set
831# CONFIG_USB_OTG is not set
832
833#
834# USB Host Controller Drivers
835#
836# CONFIG_USB_EHCI_HCD is not set
837# CONFIG_USB_ISP116X_HCD is not set
838CONFIG_USB_OHCI_HCD=y
839# CONFIG_USB_OHCI_BIG_ENDIAN is not set
840CONFIG_USB_OHCI_LITTLE_ENDIAN=y
841# CONFIG_USB_UHCI_HCD is not set
842# CONFIG_USB_SL811_HCD is not set
843
844#
845# USB Device Class drivers
846#
847# CONFIG_USB_ACM is not set
848# CONFIG_USB_PRINTER is not set
675 849
676# 850#
677# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 851# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
678# 852#
679 853
680# 854#
855# may also be needed; see USB_STORAGE Help for more information
856#
857CONFIG_USB_STORAGE=y
858# CONFIG_USB_STORAGE_DEBUG is not set
859CONFIG_USB_STORAGE_DATAFAB=y
860CONFIG_USB_STORAGE_FREECOM=y
861CONFIG_USB_STORAGE_ISD200=y
862CONFIG_USB_STORAGE_DPCM=y
863CONFIG_USB_STORAGE_USBAT=y
864CONFIG_USB_STORAGE_SDDR09=y
865CONFIG_USB_STORAGE_SDDR55=y
866CONFIG_USB_STORAGE_JUMPSHOT=y
867# CONFIG_USB_STORAGE_ALAUDA is not set
868# CONFIG_USB_STORAGE_KARMA is not set
869# CONFIG_USB_LIBUSUAL is not set
870
871#
872# USB Input Devices
873#
874# CONFIG_USB_HID is not set
875
876#
877# USB HID Boot Protocol drivers
878#
879# CONFIG_USB_KBD is not set
880# CONFIG_USB_MOUSE is not set
881# CONFIG_USB_AIPTEK is not set
882# CONFIG_USB_WACOM is not set
883# CONFIG_USB_ACECAD is not set
884# CONFIG_USB_KBTAB is not set
885# CONFIG_USB_POWERMATE is not set
886# CONFIG_USB_TOUCHSCREEN is not set
887# CONFIG_USB_YEALINK is not set
888# CONFIG_USB_XPAD is not set
889# CONFIG_USB_ATI_REMOTE is not set
890# CONFIG_USB_ATI_REMOTE2 is not set
891# CONFIG_USB_KEYSPAN_REMOTE is not set
892# CONFIG_USB_APPLETOUCH is not set
893# CONFIG_USB_TRANCEVIBRATOR is not set
894
895#
896# USB Imaging devices
897#
898# CONFIG_USB_MDC800 is not set
899# CONFIG_USB_MICROTEK is not set
900
901#
902# USB Network Adapters
903#
904# CONFIG_USB_CATC is not set
905# CONFIG_USB_KAWETH is not set
906# CONFIG_USB_PEGASUS is not set
907# CONFIG_USB_RTL8150 is not set
908# CONFIG_USB_USBNET is not set
909CONFIG_USB_MON=y
910
911#
912# USB port drivers
913#
914
915#
916# USB Serial Converter support
917#
918# CONFIG_USB_SERIAL is not set
919
920#
921# USB Miscellaneous drivers
922#
923# CONFIG_USB_EMI62 is not set
924# CONFIG_USB_EMI26 is not set
925# CONFIG_USB_ADUTUX is not set
926# CONFIG_USB_AUERSWALD is not set
927# CONFIG_USB_RIO500 is not set
928# CONFIG_USB_LEGOTOWER is not set
929# CONFIG_USB_LCD is not set
930# CONFIG_USB_LED is not set
931# CONFIG_USB_CYPRESS_CY7C63 is not set
932# CONFIG_USB_CYTHERM is not set
933# CONFIG_USB_PHIDGET is not set
934# CONFIG_USB_IDMOUSE is not set
935# CONFIG_USB_FTDI_ELAN is not set
936# CONFIG_USB_APPLEDISPLAY is not set
937# CONFIG_USB_LD is not set
938
939#
940# USB DSL modem support
941#
942
943#
681# USB Gadget Support 944# USB Gadget Support
682# 945#
683# CONFIG_USB_GADGET is not set 946# CONFIG_USB_GADGET is not set
@@ -703,6 +966,7 @@ CONFIG_DUMMY_CONSOLE=y
703# 966#
704# InfiniBand support 967# InfiniBand support
705# 968#
969# CONFIG_INFINIBAND is not set
706 970
707# 971#
708# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) 972# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
@@ -733,10 +997,12 @@ CONFIG_EXT2_FS=y
733# CONFIG_EXT2_FS_XATTR is not set 997# CONFIG_EXT2_FS_XATTR is not set
734# CONFIG_EXT2_FS_XIP is not set 998# CONFIG_EXT2_FS_XIP is not set
735# CONFIG_EXT3_FS is not set 999# CONFIG_EXT3_FS is not set
1000# CONFIG_EXT4DEV_FS is not set
736# CONFIG_REISERFS_FS is not set 1001# CONFIG_REISERFS_FS is not set
737# CONFIG_JFS_FS is not set 1002# CONFIG_JFS_FS is not set
738# CONFIG_FS_POSIX_ACL is not set 1003# CONFIG_FS_POSIX_ACL is not set
739# CONFIG_XFS_FS is not set 1004# CONFIG_XFS_FS is not set
1005# CONFIG_GFS2_FS is not set
740# CONFIG_OCFS2_FS is not set 1006# CONFIG_OCFS2_FS is not set
741# CONFIG_MINIX_FS is not set 1007# CONFIG_MINIX_FS is not set
742# CONFIG_ROMFS_FS is not set 1008# CONFIG_ROMFS_FS is not set
@@ -769,8 +1035,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
769# 1035#
770CONFIG_PROC_FS=y 1036CONFIG_PROC_FS=y
771# CONFIG_PROC_KCORE is not set 1037# CONFIG_PROC_KCORE is not set
1038CONFIG_PROC_SYSCTL=y
772CONFIG_SYSFS=y 1039CONFIG_SYSFS=y
773CONFIG_TMPFS=y 1040CONFIG_TMPFS=y
1041# CONFIG_TMPFS_POSIX_ACL is not set
774# CONFIG_HUGETLB_PAGE is not set 1042# CONFIG_HUGETLB_PAGE is not set
775CONFIG_RAMFS=y 1043CONFIG_RAMFS=y
776# CONFIG_CONFIGFS_FS is not set 1044# CONFIG_CONFIGFS_FS is not set
@@ -813,7 +1081,6 @@ CONFIG_SUNRPC=y
813# CONFIG_RPCSEC_GSS_SPKM3 is not set 1081# CONFIG_RPCSEC_GSS_SPKM3 is not set
814# CONFIG_SMB_FS is not set 1082# CONFIG_SMB_FS is not set
815# CONFIG_CIFS is not set 1083# CONFIG_CIFS is not set
816# CONFIG_CIFS_DEBUG2 is not set
817# CONFIG_NCP_FS is not set 1084# CONFIG_NCP_FS is not set
818# CONFIG_CODA_FS is not set 1085# CONFIG_CODA_FS is not set
819# CONFIG_AFS_FS is not set 1086# CONFIG_AFS_FS is not set
@@ -824,7 +1091,6 @@ CONFIG_SUNRPC=y
824# 1091#
825# CONFIG_PARTITION_ADVANCED is not set 1092# CONFIG_PARTITION_ADVANCED is not set
826CONFIG_MSDOS_PARTITION=y 1093CONFIG_MSDOS_PARTITION=y
827CONFIG_SGI_PARTITION=y
828 1094
829# 1095#
830# Native Language Support 1096# Native Language Support
@@ -880,6 +1146,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
880# 1146#
881CONFIG_TRACE_IRQFLAGS_SUPPORT=y 1147CONFIG_TRACE_IRQFLAGS_SUPPORT=y
882# CONFIG_PRINTK_TIME is not set 1148# CONFIG_PRINTK_TIME is not set
1149CONFIG_ENABLE_MUST_CHECK=y
883CONFIG_MAGIC_SYSRQ=y 1150CONFIG_MAGIC_SYSRQ=y
884# CONFIG_UNUSED_SYMBOLS is not set 1151# CONFIG_UNUSED_SYMBOLS is not set
885CONFIG_DEBUG_KERNEL=y 1152CONFIG_DEBUG_KERNEL=y
@@ -893,13 +1160,17 @@ CONFIG_DEBUG_SLAB=y
893# CONFIG_DEBUG_SPINLOCK is not set 1160# CONFIG_DEBUG_SPINLOCK is not set
894CONFIG_DEBUG_MUTEXES=y 1161CONFIG_DEBUG_MUTEXES=y
895# CONFIG_DEBUG_RWSEMS is not set 1162# CONFIG_DEBUG_RWSEMS is not set
1163# CONFIG_DEBUG_LOCK_ALLOC is not set
1164# CONFIG_PROVE_LOCKING is not set
896# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1165# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
897# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1166# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
898# CONFIG_DEBUG_KOBJECT is not set 1167# CONFIG_DEBUG_KOBJECT is not set
899# CONFIG_DEBUG_INFO is not set 1168# CONFIG_DEBUG_INFO is not set
900# CONFIG_DEBUG_FS is not set 1169# CONFIG_DEBUG_FS is not set
901# CONFIG_DEBUG_VM is not set 1170# CONFIG_DEBUG_VM is not set
1171# CONFIG_DEBUG_LIST is not set
902CONFIG_FORCED_INLINING=y 1172CONFIG_FORCED_INLINING=y
1173# CONFIG_HEADERS_CHECK is not set
903# CONFIG_RCU_TORTURE_TEST is not set 1174# CONFIG_RCU_TORTURE_TEST is not set
904CONFIG_CROSSCOMPILE=y 1175CONFIG_CROSSCOMPILE=y
905CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp" 1176CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp"
@@ -918,6 +1189,9 @@ CONFIG_CMDLINE="console=ttyS1,38400n8 kgdb=ttyS0 root=/dev/nfs ip=bootp"
918# Cryptographic options 1189# Cryptographic options
919# 1190#
920CONFIG_CRYPTO=y 1191CONFIG_CRYPTO=y
1192CONFIG_CRYPTO_ALGAPI=m
1193CONFIG_CRYPTO_BLKCIPHER=m
1194CONFIG_CRYPTO_MANAGER=m
921# CONFIG_CRYPTO_HMAC is not set 1195# CONFIG_CRYPTO_HMAC is not set
922# CONFIG_CRYPTO_NULL is not set 1196# CONFIG_CRYPTO_NULL is not set
923# CONFIG_CRYPTO_MD4 is not set 1197# CONFIG_CRYPTO_MD4 is not set
@@ -927,6 +1201,8 @@ CONFIG_CRYPTO_MD5=m
927# CONFIG_CRYPTO_SHA512 is not set 1201# CONFIG_CRYPTO_SHA512 is not set
928# CONFIG_CRYPTO_WP512 is not set 1202# CONFIG_CRYPTO_WP512 is not set
929# CONFIG_CRYPTO_TGR192 is not set 1203# CONFIG_CRYPTO_TGR192 is not set
1204CONFIG_CRYPTO_ECB=m
1205CONFIG_CRYPTO_CBC=m
930# CONFIG_CRYPTO_DES is not set 1206# CONFIG_CRYPTO_DES is not set
931# CONFIG_CRYPTO_BLOWFISH is not set 1207# CONFIG_CRYPTO_BLOWFISH is not set
932# CONFIG_CRYPTO_TWOFISH is not set 1208# CONFIG_CRYPTO_TWOFISH is not set
diff --git a/arch/mips/configs/pnx8550-v2pci_defconfig b/arch/mips/configs/pnx8550-v2pci_defconfig
index e93266b37dd9..64b9fbf44a64 100644
--- a/arch/mips/configs/pnx8550-v2pci_defconfig
+++ b/arch/mips/configs/pnx8550-v2pci_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.18-rc1 3# Linux kernel version: 2.6.19-rc2
4# Thu Jul 6 10:04:18 2006 4# Sat Oct 14 23:12:15 2006
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -25,8 +25,6 @@ CONFIG_MIPS=y
25# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
26# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
27# CONFIG_MIPS_EV64120 is not set 27# CONFIG_MIPS_EV64120 is not set
28# CONFIG_MIPS_IVR is not set
29# CONFIG_MIPS_ITE8172 is not set
30# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set 29# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
@@ -40,14 +38,14 @@ CONFIG_MIPS=y
40# CONFIG_MOMENCO_OCELOT_C is not set 38# CONFIG_MOMENCO_OCELOT_C is not set
41# CONFIG_MOMENCO_OCELOT_G is not set 39# CONFIG_MOMENCO_OCELOT_G is not set
42# CONFIG_MIPS_XXS1500 is not set 40# CONFIG_MIPS_XXS1500 is not set
43# CONFIG_PNX8550_V2PCI is not set 41CONFIG_PNX8550_V2PCI=y
44# CONFIG_PNX8550_JBS is not set 42# CONFIG_PNX8550_JBS is not set
45# CONFIG_DDB5477 is not set 43# CONFIG_DDB5477 is not set
46# CONFIG_MACH_VR41XX is not set 44# CONFIG_MACH_VR41XX is not set
47# CONFIG_PMC_YOSEMITE is not set 45# CONFIG_PMC_YOSEMITE is not set
48# CONFIG_QEMU is not set 46# CONFIG_QEMU is not set
49# CONFIG_MARKEINS is not set 47# CONFIG_MARKEINS is not set
50CONFIG_SGI_IP22=y 48# CONFIG_SGI_IP22 is not set
51# CONFIG_SGI_IP27 is not set 49# CONFIG_SGI_IP27 is not set
52# CONFIG_SGI_IP32 is not set 50# CONFIG_SGI_IP32 is not set
53# CONFIG_SIBYTE_BIGSUR is not set 51# CONFIG_SIBYTE_BIGSUR is not set
@@ -67,25 +65,21 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
67CONFIG_GENERIC_FIND_NEXT_BIT=y 65CONFIG_GENERIC_FIND_NEXT_BIT=y
68CONFIG_GENERIC_HWEIGHT=y 66CONFIG_GENERIC_HWEIGHT=y
69CONFIG_GENERIC_CALIBRATE_DELAY=y 67CONFIG_GENERIC_CALIBRATE_DELAY=y
68CONFIG_GENERIC_TIME=y
70CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 69CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
71CONFIG_ARC=y
72CONFIG_DMA_NONCOHERENT=y 70CONFIG_DMA_NONCOHERENT=y
73CONFIG_DMA_NEED_PCI_MAP_STATE=y 71CONFIG_DMA_NEED_PCI_MAP_STATE=y
74CONFIG_CPU_BIG_ENDIAN=y 72# CONFIG_CPU_BIG_ENDIAN is not set
75# CONFIG_CPU_LITTLE_ENDIAN is not set 73CONFIG_CPU_LITTLE_ENDIAN=y
76CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y 74CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
77CONFIG_IRQ_CPU=y 75CONFIG_PNX8550=y
78CONFIG_SWAP_IO_SPACE=y 76CONFIG_SOC_PNX8550=y
79CONFIG_ARC32=y
80CONFIG_BOOT_ELF32=y
81CONFIG_MIPS_L1_CACHE_SHIFT=5 77CONFIG_MIPS_L1_CACHE_SHIFT=5
82# CONFIG_ARC_CONSOLE is not set
83CONFIG_ARC_PROMLIB=y
84 78
85# 79#
86# CPU selection 80# CPU selection
87# 81#
88# CONFIG_CPU_MIPS32_R1 is not set 82CONFIG_CPU_MIPS32_R1=y
89# CONFIG_CPU_MIPS32_R2 is not set 83# CONFIG_CPU_MIPS32_R2 is not set
90# CONFIG_CPU_MIPS64_R1 is not set 84# CONFIG_CPU_MIPS64_R1 is not set
91# CONFIG_CPU_MIPS64_R2 is not set 85# CONFIG_CPU_MIPS64_R2 is not set
@@ -93,7 +87,7 @@ CONFIG_ARC_PROMLIB=y
93# CONFIG_CPU_TX39XX is not set 87# CONFIG_CPU_TX39XX is not set
94# CONFIG_CPU_VR41XX is not set 88# CONFIG_CPU_VR41XX is not set
95# CONFIG_CPU_R4300 is not set 89# CONFIG_CPU_R4300 is not set
96CONFIG_CPU_R4X00=y 90# CONFIG_CPU_R4X00 is not set
97# CONFIG_CPU_TX49XX is not set 91# CONFIG_CPU_TX49XX is not set
98# CONFIG_CPU_R5000 is not set 92# CONFIG_CPU_R5000 is not set
99# CONFIG_CPU_R5432 is not set 93# CONFIG_CPU_R5432 is not set
@@ -104,12 +98,11 @@ CONFIG_CPU_R4X00=y
104# CONFIG_CPU_RM7000 is not set 98# CONFIG_CPU_RM7000 is not set
105# CONFIG_CPU_RM9000 is not set 99# CONFIG_CPU_RM9000 is not set
106# CONFIG_CPU_SB1 is not set 100# CONFIG_CPU_SB1 is not set
107CONFIG_SYS_HAS_CPU_R4X00=y 101CONFIG_SYS_HAS_CPU_MIPS32_R1=y
108CONFIG_SYS_HAS_CPU_R5000=y 102CONFIG_CPU_MIPS32=y
103CONFIG_CPU_MIPSR1=y
109CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y 104CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
110CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
111CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y 105CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
112CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
113 106
114# 107#
115# Kernel type 108# Kernel type
@@ -120,17 +113,17 @@ CONFIG_PAGE_SIZE_4KB=y
120# CONFIG_PAGE_SIZE_8KB is not set 113# CONFIG_PAGE_SIZE_8KB is not set
121# CONFIG_PAGE_SIZE_16KB is not set 114# CONFIG_PAGE_SIZE_16KB is not set
122# CONFIG_PAGE_SIZE_64KB is not set 115# CONFIG_PAGE_SIZE_64KB is not set
123CONFIG_BOARD_SCACHE=y 116CONFIG_CPU_HAS_PREFETCH=y
124CONFIG_IP22_CPU_SCACHE=y
125CONFIG_MIPS_MT_DISABLED=y 117CONFIG_MIPS_MT_DISABLED=y
126# CONFIG_MIPS_MT_SMTC is not set
127# CONFIG_MIPS_MT_SMP is not set 118# CONFIG_MIPS_MT_SMP is not set
119# CONFIG_MIPS_MT_SMTC is not set
128# CONFIG_MIPS_VPE_LOADER is not set 120# CONFIG_MIPS_VPE_LOADER is not set
129# CONFIG_64BIT_PHYS_ADDR is not set 121# CONFIG_64BIT_PHYS_ADDR is not set
130CONFIG_CPU_HAS_LLSC=y 122CONFIG_CPU_HAS_LLSC=y
131CONFIG_CPU_HAS_SYNC=y 123CONFIG_CPU_HAS_SYNC=y
132CONFIG_GENERIC_HARDIRQS=y 124CONFIG_GENERIC_HARDIRQS=y
133CONFIG_GENERIC_IRQ_PROBE=y 125CONFIG_GENERIC_IRQ_PROBE=y
126CONFIG_CPU_SUPPORTS_HIGHMEM=y
134CONFIG_ARCH_FLATMEM_ENABLE=y 127CONFIG_ARCH_FLATMEM_ENABLE=y
135CONFIG_SELECT_MEMORY_MODEL=y 128CONFIG_SELECT_MEMORY_MODEL=y
136CONFIG_FLATMEM_MANUAL=y 129CONFIG_FLATMEM_MANUAL=y
@@ -144,12 +137,12 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
144# CONFIG_HZ_48 is not set 137# CONFIG_HZ_48 is not set
145# CONFIG_HZ_100 is not set 138# CONFIG_HZ_100 is not set
146# CONFIG_HZ_128 is not set 139# CONFIG_HZ_128 is not set
147# CONFIG_HZ_250 is not set 140CONFIG_HZ_250=y
148# CONFIG_HZ_256 is not set 141# CONFIG_HZ_256 is not set
149CONFIG_HZ_1000=y 142# CONFIG_HZ_1000 is not set
150# CONFIG_HZ_1024 is not set 143# CONFIG_HZ_1024 is not set
151CONFIG_SYS_SUPPORTS_ARBIT_HZ=y 144CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
152CONFIG_HZ=1000 145CONFIG_HZ=250
153CONFIG_PREEMPT_NONE=y 146CONFIG_PREEMPT_NONE=y
154# CONFIG_PREEMPT_VOLUNTARY is not set 147# CONFIG_PREEMPT_VOLUNTARY is not set
155# CONFIG_PREEMPT is not set 148# CONFIG_PREEMPT is not set
@@ -171,16 +164,20 @@ CONFIG_LOCALVERSION=""
171CONFIG_LOCALVERSION_AUTO=y 164CONFIG_LOCALVERSION_AUTO=y
172CONFIG_SWAP=y 165CONFIG_SWAP=y
173CONFIG_SYSVIPC=y 166CONFIG_SYSVIPC=y
167# CONFIG_IPC_NS is not set
174# CONFIG_POSIX_MQUEUE is not set 168# CONFIG_POSIX_MQUEUE is not set
175# CONFIG_BSD_PROCESS_ACCT is not set 169# CONFIG_BSD_PROCESS_ACCT is not set
176CONFIG_SYSCTL=y 170# CONFIG_TASKSTATS is not set
171# CONFIG_UTS_NS is not set
177# CONFIG_AUDIT is not set 172# CONFIG_AUDIT is not set
178CONFIG_IKCONFIG=y 173CONFIG_IKCONFIG=y
179CONFIG_IKCONFIG_PROC=y 174CONFIG_IKCONFIG_PROC=y
180# CONFIG_RELAY is not set 175# CONFIG_RELAY is not set
181CONFIG_INITRAMFS_SOURCE="" 176CONFIG_INITRAMFS_SOURCE=""
182# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 177# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
178CONFIG_SYSCTL=y
183CONFIG_EMBEDDED=y 179CONFIG_EMBEDDED=y
180# CONFIG_SYSCTL_SYSCALL is not set
184CONFIG_KALLSYMS=y 181CONFIG_KALLSYMS=y
185# CONFIG_KALLSYMS_EXTRA_PASS is not set 182# CONFIG_KALLSYMS_EXTRA_PASS is not set
186CONFIG_HOTPLUG=y 183CONFIG_HOTPLUG=y
@@ -188,12 +185,12 @@ CONFIG_PRINTK=y
188CONFIG_BUG=y 185CONFIG_BUG=y
189CONFIG_ELF_CORE=y 186CONFIG_ELF_CORE=y
190CONFIG_BASE_FULL=y 187CONFIG_BASE_FULL=y
191CONFIG_RT_MUTEXES=y
192CONFIG_FUTEX=y 188CONFIG_FUTEX=y
193CONFIG_EPOLL=y 189CONFIG_EPOLL=y
194CONFIG_SHMEM=y 190CONFIG_SHMEM=y
195CONFIG_SLAB=y 191CONFIG_SLAB=y
196CONFIG_VM_EVENT_COUNTERS=y 192CONFIG_VM_EVENT_COUNTERS=y
193CONFIG_RT_MUTEXES=y
197# CONFIG_TINY_SHMEM is not set 194# CONFIG_TINY_SHMEM is not set
198CONFIG_BASE_SMALL=0 195CONFIG_BASE_SMALL=0
199# CONFIG_SLOB is not set 196# CONFIG_SLOB is not set
@@ -210,6 +207,7 @@ CONFIG_KMOD=y
210# 207#
211# Block layer 208# Block layer
212# 209#
210CONFIG_BLOCK=y
213# CONFIG_LBD is not set 211# CONFIG_LBD is not set
214# CONFIG_BLK_DEV_IO_TRACE is not set 212# CONFIG_BLK_DEV_IO_TRACE is not set
215# CONFIG_LSF is not set 213# CONFIG_LSF is not set
@@ -230,8 +228,9 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
230# 228#
231# Bus options (PCI, PCMCIA, EISA, ISA, TC) 229# Bus options (PCI, PCMCIA, EISA, ISA, TC)
232# 230#
233CONFIG_HW_HAS_EISA=y 231CONFIG_HW_HAS_PCI=y
234# CONFIG_EISA is not set 232CONFIG_PCI=y
233# CONFIG_PCI_MULTITHREAD_PROBE is not set
235CONFIG_MMU=y 234CONFIG_MMU=y
236 235
237# 236#
@@ -242,6 +241,7 @@ CONFIG_MMU=y
242# 241#
243# PCI Hotplug Support 242# PCI Hotplug Support
244# 243#
244# CONFIG_HOTPLUG_PCI is not set
245 245
246# 246#
247# Executable file formats 247# Executable file formats
@@ -264,6 +264,7 @@ CONFIG_PACKET=y
264CONFIG_UNIX=y 264CONFIG_UNIX=y
265CONFIG_XFRM=y 265CONFIG_XFRM=y
266# CONFIG_XFRM_USER is not set 266# CONFIG_XFRM_USER is not set
267# CONFIG_XFRM_SUB_POLICY is not set
267# CONFIG_NET_KEY is not set 268# CONFIG_NET_KEY is not set
268CONFIG_INET=y 269CONFIG_INET=y
269# CONFIG_IP_MULTICAST is not set 270# CONFIG_IP_MULTICAST is not set
@@ -282,12 +283,14 @@ CONFIG_IP_PNP=y
282# CONFIG_INET_IPCOMP is not set 283# CONFIG_INET_IPCOMP is not set
283# CONFIG_INET_XFRM_TUNNEL is not set 284# CONFIG_INET_XFRM_TUNNEL is not set
284# CONFIG_INET_TUNNEL is not set 285# CONFIG_INET_TUNNEL is not set
285CONFIG_INET_XFRM_MODE_TRANSPORT=m 286CONFIG_INET_XFRM_MODE_TRANSPORT=y
286CONFIG_INET_XFRM_MODE_TUNNEL=m 287CONFIG_INET_XFRM_MODE_TUNNEL=y
288CONFIG_INET_XFRM_MODE_BEET=y
287CONFIG_INET_DIAG=y 289CONFIG_INET_DIAG=y
288CONFIG_INET_TCP_DIAG=y 290CONFIG_INET_TCP_DIAG=y
289# CONFIG_TCP_CONG_ADVANCED is not set 291# CONFIG_TCP_CONG_ADVANCED is not set
290CONFIG_TCP_CONG_BIC=y 292CONFIG_TCP_CONG_CUBIC=y
293CONFIG_DEFAULT_TCP_CONG="cubic"
291 294
292# 295#
293# IP: Virtual Server Configuration 296# IP: Virtual Server Configuration
@@ -300,12 +303,18 @@ CONFIG_IPV6_ROUTE_INFO=y
300# CONFIG_INET6_AH is not set 303# CONFIG_INET6_AH is not set
301# CONFIG_INET6_ESP is not set 304# CONFIG_INET6_ESP is not set
302# CONFIG_INET6_IPCOMP is not set 305# CONFIG_INET6_IPCOMP is not set
306# CONFIG_IPV6_MIP6 is not set
303# CONFIG_INET6_XFRM_TUNNEL is not set 307# CONFIG_INET6_XFRM_TUNNEL is not set
304# CONFIG_INET6_TUNNEL is not set 308# CONFIG_INET6_TUNNEL is not set
305CONFIG_INET6_XFRM_MODE_TRANSPORT=m 309CONFIG_INET6_XFRM_MODE_TRANSPORT=m
306CONFIG_INET6_XFRM_MODE_TUNNEL=m 310CONFIG_INET6_XFRM_MODE_TUNNEL=m
311CONFIG_INET6_XFRM_MODE_BEET=m
312# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
313CONFIG_IPV6_SIT=m
307# CONFIG_IPV6_TUNNEL is not set 314# CONFIG_IPV6_TUNNEL is not set
308CONFIG_NETWORK_SECMARK=y 315# CONFIG_IPV6_SUBTREES is not set
316# CONFIG_IPV6_MULTIPLE_TABLES is not set
317# CONFIG_NETWORK_SECMARK is not set
309CONFIG_NETFILTER=y 318CONFIG_NETFILTER=y
310# CONFIG_NETFILTER_DEBUG is not set 319# CONFIG_NETFILTER_DEBUG is not set
311 320
@@ -318,9 +327,9 @@ CONFIG_NETFILTER_XTABLES=m
318CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m 327CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
319CONFIG_NETFILTER_XT_TARGET_MARK=m 328CONFIG_NETFILTER_XT_TARGET_MARK=m
320CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 329CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
321CONFIG_NETFILTER_XT_TARGET_SECMARK=m
322CONFIG_NETFILTER_XT_MATCH_COMMENT=m 330CONFIG_NETFILTER_XT_MATCH_COMMENT=m
323CONFIG_NETFILTER_XT_MATCH_DCCP=m 331CONFIG_NETFILTER_XT_MATCH_DCCP=m
332# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
324CONFIG_NETFILTER_XT_MATCH_ESP=m 333CONFIG_NETFILTER_XT_MATCH_ESP=m
325CONFIG_NETFILTER_XT_MATCH_LENGTH=m 334CONFIG_NETFILTER_XT_MATCH_LENGTH=m
326CONFIG_NETFILTER_XT_MATCH_LIMIT=m 335CONFIG_NETFILTER_XT_MATCH_LIMIT=m
@@ -329,10 +338,10 @@ CONFIG_NETFILTER_XT_MATCH_MARK=m
329# CONFIG_NETFILTER_XT_MATCH_POLICY is not set 338# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
330CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m 339CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
331CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m 340CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
332CONFIG_NETFILTER_XT_MATCH_QUOTA=m 341# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
333CONFIG_NETFILTER_XT_MATCH_REALM=m 342CONFIG_NETFILTER_XT_MATCH_REALM=m
334CONFIG_NETFILTER_XT_MATCH_SCTP=m 343CONFIG_NETFILTER_XT_MATCH_SCTP=m
335CONFIG_NETFILTER_XT_MATCH_STATISTIC=m 344# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
336CONFIG_NETFILTER_XT_MATCH_STRING=m 345CONFIG_NETFILTER_XT_MATCH_STRING=m
337CONFIG_NETFILTER_XT_MATCH_TCPMSS=m 346CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
338 347
@@ -373,7 +382,6 @@ CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
373# CONFIG_ATALK is not set 382# CONFIG_ATALK is not set
374# CONFIG_X25 is not set 383# CONFIG_X25 is not set
375# CONFIG_LAPB is not set 384# CONFIG_LAPB is not set
376# CONFIG_NET_DIVERT is not set
377# CONFIG_ECONET is not set 385# CONFIG_ECONET is not set
378# CONFIG_WAN_ROUTER is not set 386# CONFIG_WAN_ROUTER is not set
379 387
@@ -426,13 +434,20 @@ CONFIG_FW_LOADER=y
426# 434#
427# Block devices 435# Block devices
428# 436#
437# CONFIG_BLK_CPQ_DA is not set
438# CONFIG_BLK_CPQ_CISS_DA is not set
439# CONFIG_BLK_DEV_DAC960 is not set
440# CONFIG_BLK_DEV_UMEM is not set
429# CONFIG_BLK_DEV_COW_COMMON is not set 441# CONFIG_BLK_DEV_COW_COMMON is not set
430CONFIG_BLK_DEV_LOOP=y 442CONFIG_BLK_DEV_LOOP=y
431# CONFIG_BLK_DEV_CRYPTOLOOP is not set 443# CONFIG_BLK_DEV_CRYPTOLOOP is not set
432# CONFIG_BLK_DEV_NBD is not set 444# CONFIG_BLK_DEV_NBD is not set
445# CONFIG_BLK_DEV_SX8 is not set
446# CONFIG_BLK_DEV_UB is not set
433CONFIG_BLK_DEV_RAM=y 447CONFIG_BLK_DEV_RAM=y
434CONFIG_BLK_DEV_RAM_COUNT=16 448CONFIG_BLK_DEV_RAM_COUNT=16
435CONFIG_BLK_DEV_RAM_SIZE=8192 449CONFIG_BLK_DEV_RAM_SIZE=8192
450CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
436CONFIG_BLK_DEV_INITRD=y 451CONFIG_BLK_DEV_INITRD=y
437# CONFIG_CDROM_PKTCDVD is not set 452# CONFIG_CDROM_PKTCDVD is not set
438# CONFIG_ATA_OVER_ETH is not set 453# CONFIG_ATA_OVER_ETH is not set
@@ -441,6 +456,7 @@ CONFIG_BLK_DEV_INITRD=y
441# ATA/ATAPI/MFM/RLL support 456# ATA/ATAPI/MFM/RLL support
442# 457#
443CONFIG_IDE=y 458CONFIG_IDE=y
459CONFIG_IDE_MAX_HWIFS=4
444CONFIG_BLK_DEV_IDE=y 460CONFIG_BLK_DEV_IDE=y
445 461
446# 462#
@@ -459,9 +475,41 @@ CONFIG_IDEDISK_MULTI_MODE=y
459# IDE chipset support/bugfixes 475# IDE chipset support/bugfixes
460# 476#
461CONFIG_IDE_GENERIC=y 477CONFIG_IDE_GENERIC=y
478CONFIG_BLK_DEV_IDEPCI=y
479CONFIG_IDEPCI_SHARE_IRQ=y
480# CONFIG_BLK_DEV_OFFBOARD is not set
481# CONFIG_BLK_DEV_GENERIC is not set
482# CONFIG_BLK_DEV_OPTI621 is not set
483CONFIG_BLK_DEV_IDEDMA_PCI=y
484# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
485CONFIG_IDEDMA_PCI_AUTO=y
486# CONFIG_IDEDMA_ONLYDISK is not set
487# CONFIG_BLK_DEV_AEC62XX is not set
488# CONFIG_BLK_DEV_ALI15X3 is not set
489# CONFIG_BLK_DEV_AMD74XX is not set
490CONFIG_BLK_DEV_CMD64X=y
491# CONFIG_BLK_DEV_TRIFLEX is not set
492# CONFIG_BLK_DEV_CY82C693 is not set
493# CONFIG_BLK_DEV_CS5520 is not set
494# CONFIG_BLK_DEV_CS5530 is not set
495# CONFIG_BLK_DEV_HPT34X is not set
496# CONFIG_BLK_DEV_HPT366 is not set
497# CONFIG_BLK_DEV_JMICRON is not set
498# CONFIG_BLK_DEV_SC1200 is not set
499# CONFIG_BLK_DEV_PIIX is not set
500# CONFIG_BLK_DEV_IT821X is not set
501# CONFIG_BLK_DEV_NS87415 is not set
502# CONFIG_BLK_DEV_PDC202XX_OLD is not set
503# CONFIG_BLK_DEV_PDC202XX_NEW is not set
504# CONFIG_BLK_DEV_SVWKS is not set
505# CONFIG_BLK_DEV_SIIMAGE is not set
506# CONFIG_BLK_DEV_SLC90E66 is not set
507# CONFIG_BLK_DEV_TRM290 is not set
508# CONFIG_BLK_DEV_VIA82CXXX is not set
462# CONFIG_IDE_ARM is not set 509# CONFIG_IDE_ARM is not set
463# CONFIG_BLK_DEV_IDEDMA is not set 510CONFIG_BLK_DEV_IDEDMA=y
464# CONFIG_IDEDMA_AUTO is not set 511# CONFIG_IDEDMA_IVB is not set
512CONFIG_IDEDMA_AUTO=y
465# CONFIG_BLK_DEV_HD is not set 513# CONFIG_BLK_DEV_HD is not set
466 514
467# 515#
@@ -469,6 +517,7 @@ CONFIG_IDE_GENERIC=y
469# 517#
470# CONFIG_RAID_ATTRS is not set 518# CONFIG_RAID_ATTRS is not set
471CONFIG_SCSI=y 519CONFIG_SCSI=y
520CONFIG_SCSI_NETLINK=y
472CONFIG_SCSI_PROC_FS=y 521CONFIG_SCSI_PROC_FS=y
473 522
474# 523#
@@ -489,22 +538,59 @@ CONFIG_BLK_DEV_SD=y
489# CONFIG_SCSI_LOGGING is not set 538# CONFIG_SCSI_LOGGING is not set
490 539
491# 540#
492# SCSI Transport Attributes 541# SCSI Transports
493# 542#
494CONFIG_SCSI_SPI_ATTRS=m 543CONFIG_SCSI_SPI_ATTRS=m
495CONFIG_SCSI_FC_ATTRS=y 544CONFIG_SCSI_FC_ATTRS=y
496CONFIG_SCSI_ISCSI_ATTRS=m 545CONFIG_SCSI_ISCSI_ATTRS=m
497# CONFIG_SCSI_SAS_ATTRS is not set 546# CONFIG_SCSI_SAS_ATTRS is not set
547# CONFIG_SCSI_SAS_LIBSAS is not set
498 548
499# 549#
500# SCSI low-level drivers 550# SCSI low-level drivers
501# 551#
502CONFIG_ISCSI_TCP=m 552CONFIG_ISCSI_TCP=m
503# CONFIG_SGIWD93_SCSI is not set 553# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
504# CONFIG_SCSI_SATA is not set 554# CONFIG_SCSI_3W_9XXX is not set
555# CONFIG_SCSI_ACARD is not set
556# CONFIG_SCSI_AACRAID is not set
557CONFIG_SCSI_AIC7XXX=m
558CONFIG_AIC7XXX_CMDS_PER_DEVICE=32
559CONFIG_AIC7XXX_RESET_DELAY_MS=15000
560# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
561CONFIG_AIC7XXX_DEBUG_MASK=0
562# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
563# CONFIG_SCSI_AIC7XXX_OLD is not set
564# CONFIG_SCSI_AIC79XX is not set
565# CONFIG_SCSI_AIC94XX is not set
566# CONFIG_SCSI_DPT_I2O is not set
567# CONFIG_SCSI_ARCMSR is not set
568# CONFIG_MEGARAID_NEWGEN is not set
569# CONFIG_MEGARAID_LEGACY is not set
570# CONFIG_MEGARAID_SAS is not set
571# CONFIG_SCSI_HPTIOP is not set
572# CONFIG_SCSI_DMX3191D is not set
573# CONFIG_SCSI_FUTURE_DOMAIN is not set
574# CONFIG_SCSI_IPS is not set
575# CONFIG_SCSI_INITIO is not set
576# CONFIG_SCSI_INIA100 is not set
577# CONFIG_SCSI_STEX is not set
578# CONFIG_SCSI_SYM53C8XX_2 is not set
579# CONFIG_SCSI_QLOGIC_1280 is not set
580# CONFIG_SCSI_QLA_FC is not set
581# CONFIG_SCSI_QLA_ISCSI is not set
582# CONFIG_SCSI_LPFC is not set
583# CONFIG_SCSI_DC395x is not set
584# CONFIG_SCSI_DC390T is not set
585# CONFIG_SCSI_NSP32 is not set
505# CONFIG_SCSI_DEBUG is not set 586# CONFIG_SCSI_DEBUG is not set
506 587
507# 588#
589# Serial ATA (prod) and Parallel ATA (experimental) drivers
590#
591# CONFIG_ATA is not set
592
593#
508# Multi-device support (RAID and LVM) 594# Multi-device support (RAID and LVM)
509# 595#
510# CONFIG_MD is not set 596# CONFIG_MD is not set
@@ -513,14 +599,19 @@ CONFIG_ISCSI_TCP=m
513# Fusion MPT device support 599# Fusion MPT device support
514# 600#
515# CONFIG_FUSION is not set 601# CONFIG_FUSION is not set
602# CONFIG_FUSION_SPI is not set
603# CONFIG_FUSION_FC is not set
604# CONFIG_FUSION_SAS is not set
516 605
517# 606#
518# IEEE 1394 (FireWire) support 607# IEEE 1394 (FireWire) support
519# 608#
609# CONFIG_IEEE1394 is not set
520 610
521# 611#
522# I2O device support 612# I2O device support
523# 613#
614# CONFIG_I2O is not set
524 615
525# 616#
526# Network device support 617# Network device support
@@ -532,6 +623,11 @@ CONFIG_NETDEVICES=y
532CONFIG_TUN=m 623CONFIG_TUN=m
533 624
534# 625#
626# ARCnet devices
627#
628# CONFIG_ARCNET is not set
629
630#
535# PHY device support 631# PHY device support
536# 632#
537# CONFIG_PHYLIB is not set 633# CONFIG_PHYLIB is not set
@@ -541,20 +637,73 @@ CONFIG_TUN=m
541# 637#
542CONFIG_NET_ETHERNET=y 638CONFIG_NET_ETHERNET=y
543CONFIG_MII=y 639CONFIG_MII=y
640# CONFIG_HAPPYMEAL is not set
641# CONFIG_SUNGEM is not set
642# CONFIG_CASSINI is not set
643# CONFIG_NET_VENDOR_3COM is not set
544# CONFIG_DM9000 is not set 644# CONFIG_DM9000 is not set
545# CONFIG_SGISEEQ is not set 645
646#
647# Tulip family network device support
648#
649# CONFIG_NET_TULIP is not set
650# CONFIG_HP100 is not set
651CONFIG_NET_PCI=y
652# CONFIG_PCNET32 is not set
653# CONFIG_AMD8111_ETH is not set
654# CONFIG_ADAPTEC_STARFIRE is not set
655# CONFIG_B44 is not set
656# CONFIG_FORCEDETH is not set
657# CONFIG_DGRS is not set
658# CONFIG_EEPRO100 is not set
659# CONFIG_E100 is not set
660# CONFIG_FEALNX is not set
661CONFIG_NATSEMI=y
662# CONFIG_NE2K_PCI is not set
663# CONFIG_8139CP is not set
664CONFIG_8139TOO=y
665# CONFIG_8139TOO_PIO is not set
666# CONFIG_8139TOO_TUNE_TWISTER is not set
667# CONFIG_8139TOO_8129 is not set
668# CONFIG_8139_OLD_RX_RESET is not set
669# CONFIG_SIS900 is not set
670# CONFIG_EPIC100 is not set
671# CONFIG_SUNDANCE is not set
672# CONFIG_TLAN is not set
673# CONFIG_VIA_RHINE is not set
674# CONFIG_LAN_SAA9730 is not set
546 675
547# 676#
548# Ethernet (1000 Mbit) 677# Ethernet (1000 Mbit)
549# 678#
679# CONFIG_ACENIC is not set
680# CONFIG_DL2K is not set
681# CONFIG_E1000 is not set
682# CONFIG_NS83820 is not set
683# CONFIG_HAMACHI is not set
684# CONFIG_YELLOWFIN is not set
685# CONFIG_R8169 is not set
686# CONFIG_SIS190 is not set
687# CONFIG_SKGE is not set
688# CONFIG_SKY2 is not set
689# CONFIG_SK98LIN is not set
690# CONFIG_VIA_VELOCITY is not set
691# CONFIG_TIGON3 is not set
692# CONFIG_BNX2 is not set
693# CONFIG_QLA3XXX is not set
550 694
551# 695#
552# Ethernet (10000 Mbit) 696# Ethernet (10000 Mbit)
553# 697#
698# CONFIG_CHELSIO_T1 is not set
699# CONFIG_IXGB is not set
700# CONFIG_S2IO is not set
701# CONFIG_MYRI10GE is not set
554 702
555# 703#
556# Token Ring devices 704# Token Ring devices
557# 705#
706# CONFIG_TR is not set
558 707
559# 708#
560# Wireless LAN (non-hamradio) 709# Wireless LAN (non-hamradio)
@@ -565,6 +714,8 @@ CONFIG_MII=y
565# Wan interfaces 714# Wan interfaces
566# 715#
567# CONFIG_WAN is not set 716# CONFIG_WAN is not set
717# CONFIG_FDDI is not set
718# CONFIG_HIPPI is not set
568CONFIG_PPP=m 719CONFIG_PPP=m
569# CONFIG_PPP_MULTILINK is not set 720# CONFIG_PPP_MULTILINK is not set
570# CONFIG_PPP_FILTER is not set 721# CONFIG_PPP_FILTER is not set
@@ -575,6 +726,8 @@ CONFIG_PPP_DEFLATE=m
575CONFIG_PPP_MPPE=m 726CONFIG_PPP_MPPE=m
576# CONFIG_PPPOE is not set 727# CONFIG_PPPOE is not set
577# CONFIG_SLIP is not set 728# CONFIG_SLIP is not set
729CONFIG_SLHC=m
730# CONFIG_NET_FC is not set
578# CONFIG_SHAPER is not set 731# CONFIG_SHAPER is not set
579# CONFIG_NETCONSOLE is not set 732# CONFIG_NETCONSOLE is not set
580# CONFIG_NETPOLL is not set 733# CONFIG_NETPOLL is not set
@@ -594,6 +747,7 @@ CONFIG_PPP_MPPE=m
594# Input device support 747# Input device support
595# 748#
596CONFIG_INPUT=y 749CONFIG_INPUT=y
750# CONFIG_INPUT_FF_MEMLESS is not set
597 751
598# 752#
599# Userland interfaces 753# Userland interfaces
@@ -616,6 +770,7 @@ CONFIG_KEYBOARD_ATKBD=y
616# CONFIG_KEYBOARD_LKKBD is not set 770# CONFIG_KEYBOARD_LKKBD is not set
617# CONFIG_KEYBOARD_XTKBD is not set 771# CONFIG_KEYBOARD_XTKBD is not set
618# CONFIG_KEYBOARD_NEWTON is not set 772# CONFIG_KEYBOARD_NEWTON is not set
773# CONFIG_KEYBOARD_STOWAWAY is not set
619CONFIG_INPUT_MOUSE=y 774CONFIG_INPUT_MOUSE=y
620CONFIG_MOUSE_PS2=y 775CONFIG_MOUSE_PS2=y
621# CONFIG_MOUSE_SERIAL is not set 776# CONFIG_MOUSE_SERIAL is not set
@@ -630,6 +785,7 @@ CONFIG_MOUSE_PS2=y
630CONFIG_SERIO=y 785CONFIG_SERIO=y
631CONFIG_SERIO_I8042=y 786CONFIG_SERIO_I8042=y
632CONFIG_SERIO_SERPORT=y 787CONFIG_SERIO_SERPORT=y
788# CONFIG_SERIO_PCIPS2 is not set
633CONFIG_SERIO_LIBPS2=y 789CONFIG_SERIO_LIBPS2=y
634# CONFIG_SERIO_RAW is not set 790# CONFIG_SERIO_RAW is not set
635# CONFIG_GAMEPORT is not set 791# CONFIG_GAMEPORT is not set
@@ -640,7 +796,7 @@ CONFIG_SERIO_LIBPS2=y
640CONFIG_VT=y 796CONFIG_VT=y
641# CONFIG_VT_CONSOLE is not set 797# CONFIG_VT_CONSOLE is not set
642CONFIG_HW_CONSOLE=y 798CONFIG_HW_CONSOLE=y
643CONFIG_VT_HW_CONSOLE_BINDING=y 799# CONFIG_VT_HW_CONSOLE_BINDING is not set
644CONFIG_SERIAL_NONSTANDARD=y 800CONFIG_SERIAL_NONSTANDARD=y
645# CONFIG_COMPUTONE is not set 801# CONFIG_COMPUTONE is not set
646# CONFIG_ROCKETPORT is not set 802# CONFIG_ROCKETPORT is not set
@@ -650,6 +806,7 @@ CONFIG_SERIAL_NONSTANDARD=y
650# CONFIG_MOXA_SMARTIO is not set 806# CONFIG_MOXA_SMARTIO is not set
651# CONFIG_ISI is not set 807# CONFIG_ISI is not set
652# CONFIG_SYNCLINKMP is not set 808# CONFIG_SYNCLINKMP is not set
809# CONFIG_SYNCLINK_GT is not set
653# CONFIG_N_HDLC is not set 810# CONFIG_N_HDLC is not set
654# CONFIG_RISCOM8 is not set 811# CONFIG_RISCOM8 is not set
655# CONFIG_SPECIALIX is not set 812# CONFIG_SPECIALIX is not set
@@ -665,7 +822,8 @@ CONFIG_SERIAL_NONSTANDARD=y
665# 822#
666# Non-8250 serial port support 823# Non-8250 serial port support
667# 824#
668# CONFIG_SERIAL_IP22_ZILOG is not set 825# CONFIG_SERIAL_IP3106 is not set
826# CONFIG_SERIAL_JSM is not set
669CONFIG_UNIX98_PTYS=y 827CONFIG_UNIX98_PTYS=y
670CONFIG_LEGACY_PTYS=y 828CONFIG_LEGACY_PTYS=y
671CONFIG_LEGACY_PTY_COUNT=256 829CONFIG_LEGACY_PTY_COUNT=256
@@ -679,16 +837,17 @@ CONFIG_LEGACY_PTY_COUNT=256
679# Watchdog Cards 837# Watchdog Cards
680# 838#
681# CONFIG_WATCHDOG is not set 839# CONFIG_WATCHDOG is not set
682# CONFIG_HW_RANDOM is not set 840CONFIG_HW_RANDOM=y
683# CONFIG_RTC is not set 841# CONFIG_RTC is not set
684# CONFIG_SGI_DS1286 is not set
685# CONFIG_GEN_RTC is not set 842# CONFIG_GEN_RTC is not set
686# CONFIG_DTLK is not set 843# CONFIG_DTLK is not set
687# CONFIG_R3964 is not set 844# CONFIG_R3964 is not set
845# CONFIG_APPLICOM is not set
688 846
689# 847#
690# Ftape, the floppy tape device driver 848# Ftape, the floppy tape device driver
691# 849#
850# CONFIG_DRM is not set
692# CONFIG_RAW_DRIVER is not set 851# CONFIG_RAW_DRIVER is not set
693 852
694# 853#
@@ -709,14 +868,30 @@ CONFIG_I2C_CHARDEV=m
709CONFIG_I2C_ALGOBIT=m 868CONFIG_I2C_ALGOBIT=m
710# CONFIG_I2C_ALGOPCF is not set 869# CONFIG_I2C_ALGOPCF is not set
711# CONFIG_I2C_ALGOPCA is not set 870# CONFIG_I2C_ALGOPCA is not set
712# CONFIG_I2C_ALGO_SGI is not set
713 871
714# 872#
715# I2C Hardware Bus support 873# I2C Hardware Bus support
716# 874#
875# CONFIG_I2C_ALI1535 is not set
876# CONFIG_I2C_ALI1563 is not set
877# CONFIG_I2C_ALI15X3 is not set
878# CONFIG_I2C_AMD756 is not set
879# CONFIG_I2C_AMD8111 is not set
880# CONFIG_I2C_I801 is not set
881# CONFIG_I2C_I810 is not set
882# CONFIG_I2C_PIIX4 is not set
883# CONFIG_I2C_NFORCE2 is not set
717# CONFIG_I2C_OCORES is not set 884# CONFIG_I2C_OCORES is not set
718# CONFIG_I2C_PARPORT_LIGHT is not set 885# CONFIG_I2C_PARPORT_LIGHT is not set
886# CONFIG_I2C_PROSAVAGE is not set
887# CONFIG_I2C_SAVAGE4 is not set
888# CONFIG_I2C_SIS5595 is not set
889# CONFIG_I2C_SIS630 is not set
890# CONFIG_I2C_SIS96X is not set
719# CONFIG_I2C_STUB is not set 891# CONFIG_I2C_STUB is not set
892# CONFIG_I2C_VIA is not set
893# CONFIG_I2C_VIAPRO is not set
894# CONFIG_I2C_VOODOO3 is not set
720# CONFIG_I2C_PCA_ISA is not set 895# CONFIG_I2C_PCA_ISA is not set
721 896
722# 897#
@@ -776,9 +951,13 @@ CONFIG_HWMON=y
776# CONFIG_SENSORS_LM92 is not set 951# CONFIG_SENSORS_LM92 is not set
777# CONFIG_SENSORS_MAX1619 is not set 952# CONFIG_SENSORS_MAX1619 is not set
778# CONFIG_SENSORS_PC87360 is not set 953# CONFIG_SENSORS_PC87360 is not set
954# CONFIG_SENSORS_SIS5595 is not set
779# CONFIG_SENSORS_SMSC47M1 is not set 955# CONFIG_SENSORS_SMSC47M1 is not set
780# CONFIG_SENSORS_SMSC47M192 is not set 956# CONFIG_SENSORS_SMSC47M192 is not set
781# CONFIG_SENSORS_SMSC47B397 is not set 957# CONFIG_SENSORS_SMSC47B397 is not set
958# CONFIG_SENSORS_VIA686A is not set
959# CONFIG_SENSORS_VT1211 is not set
960# CONFIG_SENSORS_VT8231 is not set
782# CONFIG_SENSORS_W83781D is not set 961# CONFIG_SENSORS_W83781D is not set
783# CONFIG_SENSORS_W83791D is not set 962# CONFIG_SENSORS_W83791D is not set
784# CONFIG_SENSORS_W83792D is not set 963# CONFIG_SENSORS_W83792D is not set
@@ -790,23 +969,25 @@ CONFIG_HWMON=y
790# 969#
791# Misc devices 970# Misc devices
792# 971#
972# CONFIG_TIFM_CORE is not set
793 973
794# 974#
795# Multimedia devices 975# Multimedia devices
796# 976#
797# CONFIG_VIDEO_DEV is not set 977# CONFIG_VIDEO_DEV is not set
798CONFIG_VIDEO_V4L2=y
799 978
800# 979#
801# Digital Video Broadcasting Devices 980# Digital Video Broadcasting Devices
802# 981#
803# CONFIG_DVB is not set 982# CONFIG_DVB is not set
983# CONFIG_USB_DABUSB is not set
804 984
805# 985#
806# Graphics support 986# Graphics support
807# 987#
808# CONFIG_FIRMWARE_EDID is not set 988CONFIG_FIRMWARE_EDID=y
809CONFIG_FB=y 989CONFIG_FB=y
990# CONFIG_FB_DDC is not set
810# CONFIG_FB_CFB_FILLRECT is not set 991# CONFIG_FB_CFB_FILLRECT is not set
811# CONFIG_FB_CFB_COPYAREA is not set 992# CONFIG_FB_CFB_COPYAREA is not set
812# CONFIG_FB_CFB_IMAGEBLIT is not set 993# CONFIG_FB_CFB_IMAGEBLIT is not set
@@ -814,14 +995,32 @@ CONFIG_FB=y
814# CONFIG_FB_BACKLIGHT is not set 995# CONFIG_FB_BACKLIGHT is not set
815# CONFIG_FB_MODE_HELPERS is not set 996# CONFIG_FB_MODE_HELPERS is not set
816# CONFIG_FB_TILEBLITTING is not set 997# CONFIG_FB_TILEBLITTING is not set
998# CONFIG_FB_CIRRUS is not set
999# CONFIG_FB_PM2 is not set
1000# CONFIG_FB_CYBER2000 is not set
1001# CONFIG_FB_ASILIANT is not set
1002# CONFIG_FB_IMSTT is not set
817# CONFIG_FB_S1D13XXX is not set 1003# CONFIG_FB_S1D13XXX is not set
1004# CONFIG_FB_NVIDIA is not set
1005# CONFIG_FB_RIVA is not set
1006# CONFIG_FB_MATROX is not set
1007# CONFIG_FB_RADEON is not set
1008# CONFIG_FB_ATY128 is not set
1009# CONFIG_FB_ATY is not set
1010# CONFIG_FB_SAVAGE is not set
1011# CONFIG_FB_SIS is not set
1012# CONFIG_FB_NEOMAGIC is not set
1013# CONFIG_FB_KYRO is not set
1014# CONFIG_FB_3DFX is not set
1015# CONFIG_FB_VOODOO1 is not set
1016# CONFIG_FB_SMIVGX is not set
1017# CONFIG_FB_TRIDENT is not set
818# CONFIG_FB_VIRTUAL is not set 1018# CONFIG_FB_VIRTUAL is not set
819 1019
820# 1020#
821# Console display driver support 1021# Console display driver support
822# 1022#
823# CONFIG_VGA_CONSOLE is not set 1023# CONFIG_VGA_CONSOLE is not set
824# CONFIG_SGI_NEWPORT_CONSOLE is not set
825CONFIG_DUMMY_CONSOLE=y 1024CONFIG_DUMMY_CONSOLE=y
826# CONFIG_FRAMEBUFFER_CONSOLE is not set 1025# CONFIG_FRAMEBUFFER_CONSOLE is not set
827 1026
@@ -839,15 +1038,129 @@ CONFIG_DUMMY_CONSOLE=y
839# 1038#
840# USB support 1039# USB support
841# 1040#
842# CONFIG_USB_ARCH_HAS_HCD is not set 1041CONFIG_USB_ARCH_HAS_HCD=y
843# CONFIG_USB_ARCH_HAS_OHCI is not set 1042CONFIG_USB_ARCH_HAS_OHCI=y
844# CONFIG_USB_ARCH_HAS_EHCI is not set 1043CONFIG_USB_ARCH_HAS_EHCI=y
1044CONFIG_USB=y
1045# CONFIG_USB_DEBUG is not set
1046
1047#
1048# Miscellaneous USB options
1049#
1050CONFIG_USB_DEVICEFS=y
1051# CONFIG_USB_BANDWIDTH is not set
1052# CONFIG_USB_DYNAMIC_MINORS is not set
1053# CONFIG_USB_OTG is not set
1054
1055#
1056# USB Host Controller Drivers
1057#
1058# CONFIG_USB_EHCI_HCD is not set
1059# CONFIG_USB_ISP116X_HCD is not set
1060# CONFIG_USB_OHCI_HCD is not set
1061# CONFIG_USB_UHCI_HCD is not set
1062# CONFIG_USB_SL811_HCD is not set
1063
1064#
1065# USB Device Class drivers
1066#
1067# CONFIG_USB_ACM is not set
1068# CONFIG_USB_PRINTER is not set
845 1069
846# 1070#
847# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1071# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
848# 1072#
849 1073
850# 1074#
1075# may also be needed; see USB_STORAGE Help for more information
1076#
1077CONFIG_USB_STORAGE=y
1078# CONFIG_USB_STORAGE_DEBUG is not set
1079# CONFIG_USB_STORAGE_DATAFAB is not set
1080# CONFIG_USB_STORAGE_FREECOM is not set
1081# CONFIG_USB_STORAGE_ISD200 is not set
1082# CONFIG_USB_STORAGE_DPCM is not set
1083# CONFIG_USB_STORAGE_USBAT is not set
1084# CONFIG_USB_STORAGE_SDDR09 is not set
1085# CONFIG_USB_STORAGE_SDDR55 is not set
1086# CONFIG_USB_STORAGE_JUMPSHOT is not set
1087# CONFIG_USB_STORAGE_ALAUDA is not set
1088# CONFIG_USB_STORAGE_ONETOUCH is not set
1089# CONFIG_USB_STORAGE_KARMA is not set
1090# CONFIG_USB_LIBUSUAL is not set
1091
1092#
1093# USB Input Devices
1094#
1095CONFIG_USB_HID=y
1096CONFIG_USB_HIDINPUT=y
1097# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1098# CONFIG_HID_FF is not set
1099CONFIG_USB_HIDDEV=y
1100# CONFIG_USB_AIPTEK is not set
1101# CONFIG_USB_WACOM is not set
1102# CONFIG_USB_ACECAD is not set
1103# CONFIG_USB_KBTAB is not set
1104# CONFIG_USB_POWERMATE is not set
1105# CONFIG_USB_TOUCHSCREEN is not set
1106# CONFIG_USB_YEALINK is not set
1107# CONFIG_USB_XPAD is not set
1108# CONFIG_USB_ATI_REMOTE is not set
1109# CONFIG_USB_ATI_REMOTE2 is not set
1110# CONFIG_USB_KEYSPAN_REMOTE is not set
1111# CONFIG_USB_APPLETOUCH is not set
1112# CONFIG_USB_TRANCEVIBRATOR is not set
1113
1114#
1115# USB Imaging devices
1116#
1117# CONFIG_USB_MDC800 is not set
1118# CONFIG_USB_MICROTEK is not set
1119
1120#
1121# USB Network Adapters
1122#
1123# CONFIG_USB_CATC is not set
1124# CONFIG_USB_KAWETH is not set
1125# CONFIG_USB_PEGASUS is not set
1126# CONFIG_USB_RTL8150 is not set
1127# CONFIG_USB_USBNET is not set
1128CONFIG_USB_MON=y
1129
1130#
1131# USB port drivers
1132#
1133
1134#
1135# USB Serial Converter support
1136#
1137# CONFIG_USB_SERIAL is not set
1138
1139#
1140# USB Miscellaneous drivers
1141#
1142# CONFIG_USB_EMI62 is not set
1143# CONFIG_USB_EMI26 is not set
1144# CONFIG_USB_ADUTUX is not set
1145# CONFIG_USB_AUERSWALD is not set
1146# CONFIG_USB_RIO500 is not set
1147# CONFIG_USB_LEGOTOWER is not set
1148# CONFIG_USB_LCD is not set
1149# CONFIG_USB_LED is not set
1150# CONFIG_USB_CYPRESS_CY7C63 is not set
1151# CONFIG_USB_CYTHERM is not set
1152# CONFIG_USB_PHIDGET is not set
1153# CONFIG_USB_IDMOUSE is not set
1154# CONFIG_USB_FTDI_ELAN is not set
1155# CONFIG_USB_APPLEDISPLAY is not set
1156# CONFIG_USB_LD is not set
1157# CONFIG_USB_TEST is not set
1158
1159#
1160# USB DSL modem support
1161#
1162
1163#
851# USB Gadget Support 1164# USB Gadget Support
852# 1165#
853# CONFIG_USB_GADGET is not set 1166# CONFIG_USB_GADGET is not set
@@ -873,6 +1186,7 @@ CONFIG_DUMMY_CONSOLE=y
873# 1186#
874# InfiniBand support 1187# InfiniBand support
875# 1188#
1189# CONFIG_INFINIBAND is not set
876 1190
877# 1191#
878# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) 1192# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
@@ -906,6 +1220,7 @@ CONFIG_EXT3_FS=y
906CONFIG_EXT3_FS_XATTR=y 1220CONFIG_EXT3_FS_XATTR=y
907# CONFIG_EXT3_FS_POSIX_ACL is not set 1221# CONFIG_EXT3_FS_POSIX_ACL is not set
908# CONFIG_EXT3_FS_SECURITY is not set 1222# CONFIG_EXT3_FS_SECURITY is not set
1223# CONFIG_EXT4DEV_FS is not set
909CONFIG_JBD=y 1224CONFIG_JBD=y
910# CONFIG_JBD_DEBUG is not set 1225# CONFIG_JBD_DEBUG is not set
911CONFIG_FS_MBCACHE=y 1226CONFIG_FS_MBCACHE=y
@@ -917,6 +1232,7 @@ CONFIG_XFS_FS=m
917# CONFIG_XFS_SECURITY is not set 1232# CONFIG_XFS_SECURITY is not set
918# CONFIG_XFS_POSIX_ACL is not set 1233# CONFIG_XFS_POSIX_ACL is not set
919# CONFIG_XFS_RT is not set 1234# CONFIG_XFS_RT is not set
1235# CONFIG_GFS2_FS is not set
920# CONFIG_OCFS2_FS is not set 1236# CONFIG_OCFS2_FS is not set
921# CONFIG_MINIX_FS is not set 1237# CONFIG_MINIX_FS is not set
922# CONFIG_ROMFS_FS is not set 1238# CONFIG_ROMFS_FS is not set
@@ -949,8 +1265,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
949# 1265#
950CONFIG_PROC_FS=y 1266CONFIG_PROC_FS=y
951# CONFIG_PROC_KCORE is not set 1267# CONFIG_PROC_KCORE is not set
1268CONFIG_PROC_SYSCTL=y
952CONFIG_SYSFS=y 1269CONFIG_SYSFS=y
953CONFIG_TMPFS=y 1270CONFIG_TMPFS=y
1271# CONFIG_TMPFS_POSIX_ACL is not set
954# CONFIG_HUGETLB_PAGE is not set 1272# CONFIG_HUGETLB_PAGE is not set
955CONFIG_RAMFS=y 1273CONFIG_RAMFS=y
956# CONFIG_CONFIGFS_FS is not set 1274# CONFIG_CONFIGFS_FS is not set
@@ -994,7 +1312,6 @@ CONFIG_SUNRPC=y
994CONFIG_SMB_FS=m 1312CONFIG_SMB_FS=m
995# CONFIG_SMB_NLS_DEFAULT is not set 1313# CONFIG_SMB_NLS_DEFAULT is not set
996# CONFIG_CIFS is not set 1314# CONFIG_CIFS is not set
997# CONFIG_CIFS_DEBUG2 is not set
998# CONFIG_NCP_FS is not set 1315# CONFIG_NCP_FS is not set
999# CONFIG_CODA_FS is not set 1316# CONFIG_CODA_FS is not set
1000# CONFIG_AFS_FS is not set 1317# CONFIG_AFS_FS is not set
@@ -1005,7 +1322,6 @@ CONFIG_SMB_FS=m
1005# 1322#
1006# CONFIG_PARTITION_ADVANCED is not set 1323# CONFIG_PARTITION_ADVANCED is not set
1007CONFIG_MSDOS_PARTITION=y 1324CONFIG_MSDOS_PARTITION=y
1008CONFIG_SGI_PARTITION=y
1009 1325
1010# 1326#
1011# Native Language Support 1327# Native Language Support
@@ -1061,11 +1377,13 @@ CONFIG_NLS_DEFAULT="iso8859-1"
1061# 1377#
1062CONFIG_TRACE_IRQFLAGS_SUPPORT=y 1378CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1063# CONFIG_PRINTK_TIME is not set 1379# CONFIG_PRINTK_TIME is not set
1380CONFIG_ENABLE_MUST_CHECK=y
1064# CONFIG_MAGIC_SYSRQ is not set 1381# CONFIG_MAGIC_SYSRQ is not set
1065# CONFIG_UNUSED_SYMBOLS is not set 1382# CONFIG_UNUSED_SYMBOLS is not set
1066# CONFIG_DEBUG_KERNEL is not set 1383# CONFIG_DEBUG_KERNEL is not set
1067CONFIG_LOG_BUF_SHIFT=14 1384CONFIG_LOG_BUF_SHIFT=14
1068# CONFIG_DEBUG_FS is not set 1385# CONFIG_DEBUG_FS is not set
1386# CONFIG_HEADERS_CHECK is not set
1069CONFIG_CROSSCOMPILE=y 1387CONFIG_CROSSCOMPILE=y
1070CONFIG_CMDLINE="" 1388CONFIG_CMDLINE=""
1071 1389
@@ -1079,6 +1397,9 @@ CONFIG_CMDLINE=""
1079# Cryptographic options 1397# Cryptographic options
1080# 1398#
1081CONFIG_CRYPTO=y 1399CONFIG_CRYPTO=y
1400CONFIG_CRYPTO_ALGAPI=m
1401CONFIG_CRYPTO_BLKCIPHER=m
1402CONFIG_CRYPTO_MANAGER=m
1082# CONFIG_CRYPTO_HMAC is not set 1403# CONFIG_CRYPTO_HMAC is not set
1083# CONFIG_CRYPTO_NULL is not set 1404# CONFIG_CRYPTO_NULL is not set
1084# CONFIG_CRYPTO_MD4 is not set 1405# CONFIG_CRYPTO_MD4 is not set
@@ -1088,6 +1409,8 @@ CONFIG_CRYPTO_SHA1=m
1088# CONFIG_CRYPTO_SHA512 is not set 1409# CONFIG_CRYPTO_SHA512 is not set
1089# CONFIG_CRYPTO_WP512 is not set 1410# CONFIG_CRYPTO_WP512 is not set
1090# CONFIG_CRYPTO_TGR192 is not set 1411# CONFIG_CRYPTO_TGR192 is not set
1412CONFIG_CRYPTO_ECB=m
1413CONFIG_CRYPTO_CBC=m
1091# CONFIG_CRYPTO_DES is not set 1414# CONFIG_CRYPTO_DES is not set
1092# CONFIG_CRYPTO_BLOWFISH is not set 1415# CONFIG_CRYPTO_BLOWFISH is not set
1093# CONFIG_CRYPTO_TWOFISH is not set 1416# CONFIG_CRYPTO_TWOFISH is not set
diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig
index ad7271b3f266..f7e8194809a1 100644
--- a/arch/mips/configs/tb0287_defconfig
+++ b/arch/mips/configs/tb0287_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.18-rc1 3# Linux kernel version: 2.6.19-rc2
4# Thu Jul 6 10:04:21 2006 4# Wed Oct 18 12:57:11 2006
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -25,8 +25,6 @@ CONFIG_MIPS=y
25# CONFIG_MIPS_COBALT is not set 25# CONFIG_MIPS_COBALT is not set
26# CONFIG_MACH_DECSTATION is not set 26# CONFIG_MACH_DECSTATION is not set
27# CONFIG_MIPS_EV64120 is not set 27# CONFIG_MIPS_EV64120 is not set
28# CONFIG_MIPS_IVR is not set
29# CONFIG_MIPS_ITE8172 is not set
30# CONFIG_MACH_JAZZ is not set 28# CONFIG_MACH_JAZZ is not set
31# CONFIG_LASAT is not set 29# CONFIG_LASAT is not set
32# CONFIG_MIPS_ATLAS is not set 30# CONFIG_MIPS_ATLAS is not set
@@ -72,11 +70,11 @@ CONFIG_TANBAC_TB0287=y
72# CONFIG_VICTOR_MPC30X is not set 70# CONFIG_VICTOR_MPC30X is not set
73# CONFIG_ZAO_CAPCELLA is not set 71# CONFIG_ZAO_CAPCELLA is not set
74CONFIG_PCI_VR41XX=y 72CONFIG_PCI_VR41XX=y
75# CONFIG_VRC4173 is not set
76CONFIG_RWSEM_GENERIC_SPINLOCK=y 73CONFIG_RWSEM_GENERIC_SPINLOCK=y
77CONFIG_GENERIC_FIND_NEXT_BIT=y 74CONFIG_GENERIC_FIND_NEXT_BIT=y
78CONFIG_GENERIC_HWEIGHT=y 75CONFIG_GENERIC_HWEIGHT=y
79CONFIG_GENERIC_CALIBRATE_DELAY=y 76CONFIG_GENERIC_CALIBRATE_DELAY=y
77CONFIG_GENERIC_TIME=y
80CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y 78CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
81CONFIG_DMA_NONCOHERENT=y 79CONFIG_DMA_NONCOHERENT=y
82CONFIG_DMA_NEED_PCI_MAP_STATE=y 80CONFIG_DMA_NEED_PCI_MAP_STATE=y
@@ -123,8 +121,8 @@ CONFIG_PAGE_SIZE_4KB=y
123# CONFIG_PAGE_SIZE_16KB is not set 121# CONFIG_PAGE_SIZE_16KB is not set
124# CONFIG_PAGE_SIZE_64KB is not set 122# CONFIG_PAGE_SIZE_64KB is not set
125CONFIG_MIPS_MT_DISABLED=y 123CONFIG_MIPS_MT_DISABLED=y
126# CONFIG_MIPS_MT_SMTC is not set
127# CONFIG_MIPS_MT_SMP is not set 124# CONFIG_MIPS_MT_SMP is not set
125# CONFIG_MIPS_MT_SMTC is not set
128# CONFIG_MIPS_VPE_LOADER is not set 126# CONFIG_MIPS_VPE_LOADER is not set
129CONFIG_CPU_HAS_SYNC=y 127CONFIG_CPU_HAS_SYNC=y
130CONFIG_GENERIC_HARDIRQS=y 128CONFIG_GENERIC_HARDIRQS=y
@@ -169,15 +167,19 @@ CONFIG_LOCALVERSION=""
169CONFIG_LOCALVERSION_AUTO=y 167CONFIG_LOCALVERSION_AUTO=y
170CONFIG_SWAP=y 168CONFIG_SWAP=y
171CONFIG_SYSVIPC=y 169CONFIG_SYSVIPC=y
170# CONFIG_IPC_NS is not set
172# CONFIG_POSIX_MQUEUE is not set 171# CONFIG_POSIX_MQUEUE is not set
173# CONFIG_BSD_PROCESS_ACCT is not set 172# CONFIG_BSD_PROCESS_ACCT is not set
174CONFIG_SYSCTL=y 173# CONFIG_TASKSTATS is not set
174# CONFIG_UTS_NS is not set
175# CONFIG_AUDIT is not set 175# CONFIG_AUDIT is not set
176# CONFIG_IKCONFIG is not set 176# CONFIG_IKCONFIG is not set
177# CONFIG_RELAY is not set 177# CONFIG_RELAY is not set
178CONFIG_INITRAMFS_SOURCE="" 178CONFIG_INITRAMFS_SOURCE=""
179# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 179# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
180CONFIG_SYSCTL=y
180CONFIG_EMBEDDED=y 181CONFIG_EMBEDDED=y
182# CONFIG_SYSCTL_SYSCALL is not set
181CONFIG_KALLSYMS=y 183CONFIG_KALLSYMS=y
182# CONFIG_KALLSYMS_EXTRA_PASS is not set 184# CONFIG_KALLSYMS_EXTRA_PASS is not set
183# CONFIG_HOTPLUG is not set 185# CONFIG_HOTPLUG is not set
@@ -185,12 +187,12 @@ CONFIG_PRINTK=y
185CONFIG_BUG=y 187CONFIG_BUG=y
186CONFIG_ELF_CORE=y 188CONFIG_ELF_CORE=y
187CONFIG_BASE_FULL=y 189CONFIG_BASE_FULL=y
188CONFIG_RT_MUTEXES=y
189CONFIG_FUTEX=y 190CONFIG_FUTEX=y
190CONFIG_EPOLL=y 191CONFIG_EPOLL=y
191CONFIG_SHMEM=y 192CONFIG_SHMEM=y
192CONFIG_SLAB=y 193CONFIG_SLAB=y
193CONFIG_VM_EVENT_COUNTERS=y 194CONFIG_VM_EVENT_COUNTERS=y
195CONFIG_RT_MUTEXES=y
194# CONFIG_TINY_SHMEM is not set 196# CONFIG_TINY_SHMEM is not set
195CONFIG_BASE_SMALL=0 197CONFIG_BASE_SMALL=0
196# CONFIG_SLOB is not set 198# CONFIG_SLOB is not set
@@ -208,6 +210,7 @@ CONFIG_KMOD=y
208# 210#
209# Block layer 211# Block layer
210# 212#
213CONFIG_BLOCK=y
211# CONFIG_LBD is not set 214# CONFIG_LBD is not set
212# CONFIG_BLK_DEV_IO_TRACE is not set 215# CONFIG_BLK_DEV_IO_TRACE is not set
213# CONFIG_LSF is not set 216# CONFIG_LSF is not set
@@ -230,17 +233,16 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
230# 233#
231CONFIG_HW_HAS_PCI=y 234CONFIG_HW_HAS_PCI=y
232CONFIG_PCI=y 235CONFIG_PCI=y
236# CONFIG_PCI_MULTITHREAD_PROBE is not set
233CONFIG_MMU=y 237CONFIG_MMU=y
234 238
235# 239#
236# PCCARD (PCMCIA/CardBus) support 240# PCCARD (PCMCIA/CardBus) support
237# 241#
238# CONFIG_PCCARD is not set
239 242
240# 243#
241# PCI Hotplug Support 244# PCI Hotplug Support
242# 245#
243# CONFIG_HOTPLUG_PCI is not set
244 246
245# 247#
246# Executable file formats 248# Executable file formats
@@ -263,6 +265,7 @@ CONFIG_PACKET=y
263CONFIG_UNIX=y 265CONFIG_UNIX=y
264CONFIG_XFRM=y 266CONFIG_XFRM=y
265# CONFIG_XFRM_USER is not set 267# CONFIG_XFRM_USER is not set
268# CONFIG_XFRM_SUB_POLICY is not set
266# CONFIG_NET_KEY is not set 269# CONFIG_NET_KEY is not set
267CONFIG_INET=y 270CONFIG_INET=y
268CONFIG_IP_MULTICAST=y 271CONFIG_IP_MULTICAST=y
@@ -291,13 +294,10 @@ CONFIG_SYN_COOKIES=y
291CONFIG_INET_TUNNEL=m 294CONFIG_INET_TUNNEL=m
292CONFIG_INET_XFRM_MODE_TRANSPORT=m 295CONFIG_INET_XFRM_MODE_TRANSPORT=m
293CONFIG_INET_XFRM_MODE_TUNNEL=m 296CONFIG_INET_XFRM_MODE_TUNNEL=m
297CONFIG_INET_XFRM_MODE_BEET=y
294CONFIG_INET_DIAG=y 298CONFIG_INET_DIAG=y
295CONFIG_INET_TCP_DIAG=y 299CONFIG_INET_TCP_DIAG=y
296CONFIG_TCP_CONG_ADVANCED=y 300CONFIG_TCP_CONG_ADVANCED=y
297
298#
299# TCP congestion control
300#
301CONFIG_TCP_CONG_BIC=y 301CONFIG_TCP_CONG_BIC=y
302CONFIG_TCP_CONG_CUBIC=m 302CONFIG_TCP_CONG_CUBIC=m
303CONFIG_TCP_CONG_WESTWOOD=m 303CONFIG_TCP_CONG_WESTWOOD=m
@@ -308,7 +308,13 @@ CONFIG_TCP_CONG_HTCP=m
308# CONFIG_TCP_CONG_SCALABLE is not set 308# CONFIG_TCP_CONG_SCALABLE is not set
309# CONFIG_TCP_CONG_LP is not set 309# CONFIG_TCP_CONG_LP is not set
310# CONFIG_TCP_CONG_VENO is not set 310# CONFIG_TCP_CONG_VENO is not set
311# CONFIG_TCP_CONG_COMPOUND is not set 311CONFIG_DEFAULT_BIC=y
312# CONFIG_DEFAULT_CUBIC is not set
313# CONFIG_DEFAULT_HTCP is not set
314# CONFIG_DEFAULT_VEGAS is not set
315# CONFIG_DEFAULT_WESTWOOD is not set
316# CONFIG_DEFAULT_RENO is not set
317CONFIG_DEFAULT_TCP_CONG="bic"
312# CONFIG_IPV6 is not set 318# CONFIG_IPV6 is not set
313# CONFIG_INET6_XFRM_TUNNEL is not set 319# CONFIG_INET6_XFRM_TUNNEL is not set
314# CONFIG_INET6_TUNNEL is not set 320# CONFIG_INET6_TUNNEL is not set
@@ -338,7 +344,6 @@ CONFIG_NETWORK_SECMARK=y
338# CONFIG_ATALK is not set 344# CONFIG_ATALK is not set
339# CONFIG_X25 is not set 345# CONFIG_X25 is not set
340# CONFIG_LAPB is not set 346# CONFIG_LAPB is not set
341# CONFIG_NET_DIVERT is not set
342# CONFIG_ECONET is not set 347# CONFIG_ECONET is not set
343# CONFIG_WAN_ROUTER is not set 348# CONFIG_WAN_ROUTER is not set
344 349
@@ -355,6 +360,7 @@ CONFIG_NETWORK_SECMARK=y
355# CONFIG_IRDA is not set 360# CONFIG_IRDA is not set
356# CONFIG_BT is not set 361# CONFIG_BT is not set
357# CONFIG_IEEE80211 is not set 362# CONFIG_IEEE80211 is not set
363CONFIG_FIB_RULES=y
358 364
359# 365#
360# Device Drivers 366# Device Drivers
@@ -365,7 +371,6 @@ CONFIG_NETWORK_SECMARK=y
365# 371#
366CONFIG_STANDALONE=y 372CONFIG_STANDALONE=y
367CONFIG_PREVENT_FIRMWARE_BUILD=y 373CONFIG_PREVENT_FIRMWARE_BUILD=y
368# CONFIG_FW_LOADER is not set
369# CONFIG_SYS_HYPERVISOR is not set 374# CONFIG_SYS_HYPERVISOR is not set
370 375
371# 376#
@@ -403,6 +408,7 @@ CONFIG_BLK_DEV_NBD=m
403CONFIG_BLK_DEV_RAM=y 408CONFIG_BLK_DEV_RAM=y
404CONFIG_BLK_DEV_RAM_COUNT=16 409CONFIG_BLK_DEV_RAM_COUNT=16
405CONFIG_BLK_DEV_RAM_SIZE=4096 410CONFIG_BLK_DEV_RAM_SIZE=4096
411CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
406# CONFIG_BLK_DEV_INITRD is not set 412# CONFIG_BLK_DEV_INITRD is not set
407# CONFIG_CDROM_PKTCDVD is not set 413# CONFIG_CDROM_PKTCDVD is not set
408# CONFIG_ATA_OVER_ETH is not set 414# CONFIG_ATA_OVER_ETH is not set
@@ -410,65 +416,14 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
410# 416#
411# ATA/ATAPI/MFM/RLL support 417# ATA/ATAPI/MFM/RLL support
412# 418#
413CONFIG_IDE=y 419# CONFIG_IDE is not set
414CONFIG_BLK_DEV_IDE=y
415
416#
417# Please see Documentation/ide.txt for help/info on IDE drives
418#
419# CONFIG_BLK_DEV_IDE_SATA is not set
420CONFIG_BLK_DEV_IDEDISK=y
421# CONFIG_IDEDISK_MULTI_MODE is not set
422# CONFIG_BLK_DEV_IDECD is not set
423# CONFIG_BLK_DEV_IDETAPE is not set
424# CONFIG_BLK_DEV_IDEFLOPPY is not set
425# CONFIG_BLK_DEV_IDESCSI is not set
426# CONFIG_IDE_TASK_IOCTL is not set
427
428#
429# IDE chipset support/bugfixes
430#
431CONFIG_IDE_GENERIC=y
432CONFIG_BLK_DEV_IDEPCI=y
433# CONFIG_IDEPCI_SHARE_IRQ is not set
434# CONFIG_BLK_DEV_OFFBOARD is not set
435# CONFIG_BLK_DEV_GENERIC is not set
436# CONFIG_BLK_DEV_OPTI621 is not set
437CONFIG_BLK_DEV_IDEDMA_PCI=y
438# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
439# CONFIG_IDEDMA_PCI_AUTO is not set
440# CONFIG_BLK_DEV_AEC62XX is not set
441# CONFIG_BLK_DEV_ALI15X3 is not set
442# CONFIG_BLK_DEV_AMD74XX is not set
443# CONFIG_BLK_DEV_CMD64X is not set
444# CONFIG_BLK_DEV_TRIFLEX is not set
445# CONFIG_BLK_DEV_CY82C693 is not set
446# CONFIG_BLK_DEV_CS5520 is not set
447# CONFIG_BLK_DEV_CS5530 is not set
448# CONFIG_BLK_DEV_HPT34X is not set
449# CONFIG_BLK_DEV_HPT366 is not set
450# CONFIG_BLK_DEV_SC1200 is not set
451# CONFIG_BLK_DEV_PIIX is not set
452# CONFIG_BLK_DEV_IT821X is not set
453# CONFIG_BLK_DEV_NS87415 is not set
454# CONFIG_BLK_DEV_PDC202XX_OLD is not set
455# CONFIG_BLK_DEV_PDC202XX_NEW is not set
456# CONFIG_BLK_DEV_SVWKS is not set
457CONFIG_BLK_DEV_SIIMAGE=y
458# CONFIG_BLK_DEV_SLC90E66 is not set
459# CONFIG_BLK_DEV_TRM290 is not set
460# CONFIG_BLK_DEV_VIA82CXXX is not set
461# CONFIG_IDE_ARM is not set
462CONFIG_BLK_DEV_IDEDMA=y
463# CONFIG_IDEDMA_IVB is not set
464# CONFIG_IDEDMA_AUTO is not set
465# CONFIG_BLK_DEV_HD is not set
466 420
467# 421#
468# SCSI device support 422# SCSI device support
469# 423#
470# CONFIG_RAID_ATTRS is not set 424# CONFIG_RAID_ATTRS is not set
471CONFIG_SCSI=y 425CONFIG_SCSI=y
426# CONFIG_SCSI_NETLINK is not set
472CONFIG_SCSI_PROC_FS=y 427CONFIG_SCSI_PROC_FS=y
473 428
474# 429#
@@ -489,12 +444,13 @@ CONFIG_BLK_DEV_SD=y
489# CONFIG_SCSI_LOGGING is not set 444# CONFIG_SCSI_LOGGING is not set
490 445
491# 446#
492# SCSI Transport Attributes 447# SCSI Transports
493# 448#
494# CONFIG_SCSI_SPI_ATTRS is not set 449# CONFIG_SCSI_SPI_ATTRS is not set
495# CONFIG_SCSI_FC_ATTRS is not set 450# CONFIG_SCSI_FC_ATTRS is not set
496# CONFIG_SCSI_ISCSI_ATTRS is not set 451# CONFIG_SCSI_ISCSI_ATTRS is not set
497# CONFIG_SCSI_SAS_ATTRS is not set 452# CONFIG_SCSI_SAS_ATTRS is not set
453# CONFIG_SCSI_SAS_LIBSAS is not set
498 454
499# 455#
500# SCSI low-level drivers 456# SCSI low-level drivers
@@ -507,21 +463,24 @@ CONFIG_BLK_DEV_SD=y
507# CONFIG_SCSI_AIC7XXX is not set 463# CONFIG_SCSI_AIC7XXX is not set
508# CONFIG_SCSI_AIC7XXX_OLD is not set 464# CONFIG_SCSI_AIC7XXX_OLD is not set
509# CONFIG_SCSI_AIC79XX is not set 465# CONFIG_SCSI_AIC79XX is not set
466# CONFIG_SCSI_AIC94XX is not set
510# CONFIG_SCSI_DPT_I2O is not set 467# CONFIG_SCSI_DPT_I2O is not set
468# CONFIG_SCSI_ARCMSR is not set
511# CONFIG_MEGARAID_NEWGEN is not set 469# CONFIG_MEGARAID_NEWGEN is not set
512# CONFIG_MEGARAID_LEGACY is not set 470# CONFIG_MEGARAID_LEGACY is not set
513# CONFIG_MEGARAID_SAS is not set 471# CONFIG_MEGARAID_SAS is not set
514# CONFIG_SCSI_SATA is not set
515# CONFIG_SCSI_HPTIOP is not set 472# CONFIG_SCSI_HPTIOP is not set
516# CONFIG_SCSI_DMX3191D is not set 473# CONFIG_SCSI_DMX3191D is not set
517# CONFIG_SCSI_FUTURE_DOMAIN is not set 474# CONFIG_SCSI_FUTURE_DOMAIN is not set
518# CONFIG_SCSI_IPS is not set 475# CONFIG_SCSI_IPS is not set
519# CONFIG_SCSI_INITIO is not set 476# CONFIG_SCSI_INITIO is not set
520# CONFIG_SCSI_INIA100 is not set 477# CONFIG_SCSI_INIA100 is not set
478# CONFIG_SCSI_STEX is not set
521# CONFIG_SCSI_SYM53C8XX_2 is not set 479# CONFIG_SCSI_SYM53C8XX_2 is not set
522# CONFIG_SCSI_IPR is not set 480# CONFIG_SCSI_IPR is not set
523# CONFIG_SCSI_QLOGIC_1280 is not set 481# CONFIG_SCSI_QLOGIC_1280 is not set
524# CONFIG_SCSI_QLA_FC is not set 482# CONFIG_SCSI_QLA_FC is not set
483# CONFIG_SCSI_QLA_ISCSI is not set
525# CONFIG_SCSI_LPFC is not set 484# CONFIG_SCSI_LPFC is not set
526# CONFIG_SCSI_DC395x is not set 485# CONFIG_SCSI_DC395x is not set
527# CONFIG_SCSI_DC390T is not set 486# CONFIG_SCSI_DC390T is not set
@@ -529,6 +488,59 @@ CONFIG_BLK_DEV_SD=y
529# CONFIG_SCSI_DEBUG is not set 488# CONFIG_SCSI_DEBUG is not set
530 489
531# 490#
491# Serial ATA (prod) and Parallel ATA (experimental) drivers
492#
493CONFIG_ATA=y
494# CONFIG_SATA_AHCI is not set
495# CONFIG_SATA_SVW is not set
496# CONFIG_ATA_PIIX is not set
497# CONFIG_SATA_MV is not set
498# CONFIG_SATA_NV is not set
499# CONFIG_PDC_ADMA is not set
500# CONFIG_SATA_QSTOR is not set
501# CONFIG_SATA_PROMISE is not set
502# CONFIG_SATA_SX4 is not set
503# CONFIG_SATA_SIL is not set
504# CONFIG_SATA_SIL24 is not set
505# CONFIG_SATA_SIS is not set
506# CONFIG_SATA_ULI is not set
507# CONFIG_SATA_VIA is not set
508# CONFIG_SATA_VITESSE is not set
509# CONFIG_PATA_ALI is not set
510# CONFIG_PATA_AMD is not set
511# CONFIG_PATA_ARTOP is not set
512# CONFIG_PATA_ATIIXP is not set
513# CONFIG_PATA_CMD64X is not set
514# CONFIG_PATA_CS5520 is not set
515# CONFIG_PATA_CS5530 is not set
516# CONFIG_PATA_CYPRESS is not set
517# CONFIG_PATA_EFAR is not set
518# CONFIG_ATA_GENERIC is not set
519# CONFIG_PATA_HPT366 is not set
520# CONFIG_PATA_HPT37X is not set
521# CONFIG_PATA_HPT3X2N is not set
522# CONFIG_PATA_HPT3X3 is not set
523# CONFIG_PATA_IT821X is not set
524# CONFIG_PATA_JMICRON is not set
525# CONFIG_PATA_TRIFLEX is not set
526# CONFIG_PATA_MPIIX is not set
527# CONFIG_PATA_OLDPIIX is not set
528# CONFIG_PATA_NETCELL is not set
529# CONFIG_PATA_NS87410 is not set
530# CONFIG_PATA_OPTI is not set
531# CONFIG_PATA_OPTIDMA is not set
532# CONFIG_PATA_PDC_OLD is not set
533# CONFIG_PATA_RADISYS is not set
534# CONFIG_PATA_RZ1000 is not set
535# CONFIG_PATA_SC1200 is not set
536# CONFIG_PATA_SERVERWORKS is not set
537# CONFIG_PATA_PDC2027X is not set
538CONFIG_PATA_SIL680=y
539# CONFIG_PATA_SIS is not set
540# CONFIG_PATA_VIA is not set
541# CONFIG_PATA_WINBOND is not set
542
543#
532# Multi-device support (RAID and LVM) 544# Multi-device support (RAID and LVM)
533# 545#
534# CONFIG_MD is not set 546# CONFIG_MD is not set
@@ -632,6 +644,7 @@ CONFIG_R8169=y
632# CONFIG_SK98LIN is not set 644# CONFIG_SK98LIN is not set
633# CONFIG_TIGON3 is not set 645# CONFIG_TIGON3 is not set
634# CONFIG_BNX2 is not set 646# CONFIG_BNX2 is not set
647# CONFIG_QLA3XXX is not set
635 648
636# 649#
637# Ethernet (10000 Mbit) 650# Ethernet (10000 Mbit)
@@ -679,6 +692,7 @@ CONFIG_R8169=y
679# Input device support 692# Input device support
680# 693#
681CONFIG_INPUT=y 694CONFIG_INPUT=y
695# CONFIG_INPUT_FF_MEMLESS is not set
682 696
683# 697#
684# Userland interfaces 698# Userland interfaces
@@ -758,7 +772,6 @@ CONFIG_GPIO_VR41XX=y
758# TPM devices 772# TPM devices
759# 773#
760# CONFIG_TCG_TPM is not set 774# CONFIG_TCG_TPM is not set
761# CONFIG_TELCLOCK is not set
762 775
763# 776#
764# I2C support 777# I2C support
@@ -784,12 +797,12 @@ CONFIG_GPIO_VR41XX=y
784# 797#
785# Misc devices 798# Misc devices
786# 799#
800# CONFIG_TIFM_CORE is not set
787 801
788# 802#
789# Multimedia devices 803# Multimedia devices
790# 804#
791# CONFIG_VIDEO_DEV is not set 805# CONFIG_VIDEO_DEV is not set
792CONFIG_VIDEO_V4L2=y
793 806
794# 807#
795# Digital Video Broadcasting Devices 808# Digital Video Broadcasting Devices
@@ -897,13 +910,13 @@ CONFIG_USB_STORAGE=m
897# CONFIG_USB_STORAGE_DEBUG is not set 910# CONFIG_USB_STORAGE_DEBUG is not set
898# CONFIG_USB_STORAGE_DATAFAB is not set 911# CONFIG_USB_STORAGE_DATAFAB is not set
899# CONFIG_USB_STORAGE_FREECOM is not set 912# CONFIG_USB_STORAGE_FREECOM is not set
900# CONFIG_USB_STORAGE_ISD200 is not set
901# CONFIG_USB_STORAGE_DPCM is not set 913# CONFIG_USB_STORAGE_DPCM is not set
902# CONFIG_USB_STORAGE_USBAT is not set 914# CONFIG_USB_STORAGE_USBAT is not set
903# CONFIG_USB_STORAGE_SDDR09 is not set 915# CONFIG_USB_STORAGE_SDDR09 is not set
904# CONFIG_USB_STORAGE_SDDR55 is not set 916# CONFIG_USB_STORAGE_SDDR55 is not set
905# CONFIG_USB_STORAGE_JUMPSHOT is not set 917# CONFIG_USB_STORAGE_JUMPSHOT is not set
906# CONFIG_USB_STORAGE_ALAUDA is not set 918# CONFIG_USB_STORAGE_ALAUDA is not set
919# CONFIG_USB_STORAGE_KARMA is not set
907# CONFIG_USB_LIBUSUAL is not set 920# CONFIG_USB_LIBUSUAL is not set
908 921
909# 922#
@@ -932,6 +945,7 @@ CONFIG_USB_HIDINPUT=y
932# CONFIG_USB_ATI_REMOTE2 is not set 945# CONFIG_USB_ATI_REMOTE2 is not set
933# CONFIG_USB_KEYSPAN_REMOTE is not set 946# CONFIG_USB_KEYSPAN_REMOTE is not set
934# CONFIG_USB_APPLETOUCH is not set 947# CONFIG_USB_APPLETOUCH is not set
948# CONFIG_USB_TRANCEVIBRATOR is not set
935 949
936# 950#
937# USB Imaging devices 951# USB Imaging devices
@@ -963,16 +977,17 @@ CONFIG_USB_MON=y
963# 977#
964# CONFIG_USB_EMI62 is not set 978# CONFIG_USB_EMI62 is not set
965# CONFIG_USB_EMI26 is not set 979# CONFIG_USB_EMI26 is not set
980# CONFIG_USB_ADUTUX is not set
966# CONFIG_USB_AUERSWALD is not set 981# CONFIG_USB_AUERSWALD is not set
967# CONFIG_USB_RIO500 is not set 982# CONFIG_USB_RIO500 is not set
968# CONFIG_USB_LEGOTOWER is not set 983# CONFIG_USB_LEGOTOWER is not set
969# CONFIG_USB_LCD is not set 984# CONFIG_USB_LCD is not set
970# CONFIG_USB_LED is not set 985# CONFIG_USB_LED is not set
971# CONFIG_USB_CY7C63 is not set 986# CONFIG_USB_CYPRESS_CY7C63 is not set
972# CONFIG_USB_CYTHERM is not set 987# CONFIG_USB_CYTHERM is not set
973# CONFIG_USB_PHIDGETKIT is not set 988# CONFIG_USB_PHIDGET is not set
974# CONFIG_USB_PHIDGETSERVO is not set
975# CONFIG_USB_IDMOUSE is not set 989# CONFIG_USB_IDMOUSE is not set
990# CONFIG_USB_FTDI_ELAN is not set
976# CONFIG_USB_APPLEDISPLAY is not set 991# CONFIG_USB_APPLEDISPLAY is not set
977# CONFIG_USB_SISUSBVGA is not set 992# CONFIG_USB_SISUSBVGA is not set
978# CONFIG_USB_LD is not set 993# CONFIG_USB_LD is not set
@@ -1041,6 +1056,7 @@ CONFIG_EXT3_FS=y
1041CONFIG_EXT3_FS_XATTR=y 1056CONFIG_EXT3_FS_XATTR=y
1042# CONFIG_EXT3_FS_POSIX_ACL is not set 1057# CONFIG_EXT3_FS_POSIX_ACL is not set
1043# CONFIG_EXT3_FS_SECURITY is not set 1058# CONFIG_EXT3_FS_SECURITY is not set
1059# CONFIG_EXT4DEV_FS is not set
1044CONFIG_JBD=y 1060CONFIG_JBD=y
1045# CONFIG_JBD_DEBUG is not set 1061# CONFIG_JBD_DEBUG is not set
1046CONFIG_FS_MBCACHE=y 1062CONFIG_FS_MBCACHE=y
@@ -1052,6 +1068,7 @@ CONFIG_XFS_QUOTA=y
1052# CONFIG_XFS_SECURITY is not set 1068# CONFIG_XFS_SECURITY is not set
1053CONFIG_XFS_POSIX_ACL=y 1069CONFIG_XFS_POSIX_ACL=y
1054# CONFIG_XFS_RT is not set 1070# CONFIG_XFS_RT is not set
1071# CONFIG_GFS2_FS is not set
1055# CONFIG_OCFS2_FS is not set 1072# CONFIG_OCFS2_FS is not set
1056# CONFIG_MINIX_FS is not set 1073# CONFIG_MINIX_FS is not set
1057CONFIG_ROMFS_FS=m 1074CONFIG_ROMFS_FS=m
@@ -1082,8 +1099,10 @@ CONFIG_AUTOFS4_FS=y
1082# 1099#
1083CONFIG_PROC_FS=y 1100CONFIG_PROC_FS=y
1084CONFIG_PROC_KCORE=y 1101CONFIG_PROC_KCORE=y
1102CONFIG_PROC_SYSCTL=y
1085CONFIG_SYSFS=y 1103CONFIG_SYSFS=y
1086CONFIG_TMPFS=y 1104CONFIG_TMPFS=y
1105# CONFIG_TMPFS_POSIX_ACL is not set
1087# CONFIG_HUGETLB_PAGE is not set 1106# CONFIG_HUGETLB_PAGE is not set
1088CONFIG_RAMFS=y 1107CONFIG_RAMFS=y
1089# CONFIG_CONFIGFS_FS is not set 1108# CONFIG_CONFIGFS_FS is not set
@@ -1123,7 +1142,6 @@ CONFIG_SUNRPC=y
1123# CONFIG_RPCSEC_GSS_SPKM3 is not set 1142# CONFIG_RPCSEC_GSS_SPKM3 is not set
1124# CONFIG_SMB_FS is not set 1143# CONFIG_SMB_FS is not set
1125# CONFIG_CIFS is not set 1144# CONFIG_CIFS is not set
1126# CONFIG_CIFS_DEBUG2 is not set
1127# CONFIG_NCP_FS is not set 1145# CONFIG_NCP_FS is not set
1128# CONFIG_CODA_FS is not set 1146# CONFIG_CODA_FS is not set
1129# CONFIG_AFS_FS is not set 1147# CONFIG_AFS_FS is not set
@@ -1150,11 +1168,13 @@ CONFIG_MSDOS_PARTITION=y
1150# 1168#
1151CONFIG_TRACE_IRQFLAGS_SUPPORT=y 1169CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1152# CONFIG_PRINTK_TIME is not set 1170# CONFIG_PRINTK_TIME is not set
1171CONFIG_ENABLE_MUST_CHECK=y
1153# CONFIG_MAGIC_SYSRQ is not set 1172# CONFIG_MAGIC_SYSRQ is not set
1154# CONFIG_UNUSED_SYMBOLS is not set 1173# CONFIG_UNUSED_SYMBOLS is not set
1155# CONFIG_DEBUG_KERNEL is not set 1174# CONFIG_DEBUG_KERNEL is not set
1156CONFIG_LOG_BUF_SHIFT=14 1175CONFIG_LOG_BUF_SHIFT=14
1157# CONFIG_DEBUG_FS is not set 1176# CONFIG_DEBUG_FS is not set
1177# CONFIG_HEADERS_CHECK is not set
1158CONFIG_CROSSCOMPILE=y 1178CONFIG_CROSSCOMPILE=y
1159CONFIG_CMDLINE="mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs" 1179CONFIG_CMDLINE="mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
1160 1180
@@ -1170,10 +1190,6 @@ CONFIG_CMDLINE="mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs"
1170# CONFIG_CRYPTO is not set 1190# CONFIG_CRYPTO is not set
1171 1191
1172# 1192#
1173# Hardware crypto devices
1174#
1175
1176#
1177# Library routines 1193# Library routines
1178# 1194#
1179# CONFIG_CRC_CCITT is not set 1195# CONFIG_CRC_CCITT is not set
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
index ba52705a2738..96249aa5df5d 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
@@ -53,14 +53,6 @@ vrc5477_irq_disable(unsigned int irq)
53 ll_vrc5477_irq_disable(irq - vrc5477_irq_base); 53 ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
54} 54}
55 55
56static unsigned int vrc5477_irq_startup(unsigned int irq)
57{
58 vrc5477_irq_enable(irq);
59 return 0;
60}
61
62#define vrc5477_irq_shutdown vrc5477_irq_disable
63
64static void 56static void
65vrc5477_irq_ack(unsigned int irq) 57vrc5477_irq_ack(unsigned int irq)
66{ 58{
@@ -91,11 +83,10 @@ vrc5477_irq_end(unsigned int irq)
91 83
92struct irq_chip vrc5477_irq_controller = { 84struct irq_chip vrc5477_irq_controller = {
93 .typename = "vrc5477_irq", 85 .typename = "vrc5477_irq",
94 .startup = vrc5477_irq_startup,
95 .shutdown = vrc5477_irq_shutdown,
96 .enable = vrc5477_irq_enable,
97 .disable = vrc5477_irq_disable,
98 .ack = vrc5477_irq_ack, 86 .ack = vrc5477_irq_ack,
87 .mask = vrc5477_irq_disable,
88 .mask_ack = vrc5477_irq_ack,
89 .unmask = vrc5477_irq_enable,
99 .end = vrc5477_irq_end 90 .end = vrc5477_irq_end
100}; 91};
101 92
@@ -103,12 +94,8 @@ void __init vrc5477_irq_init(u32 irq_base)
103{ 94{
104 u32 i; 95 u32 i;
105 96
106 for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++) { 97 for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++)
107 irq_desc[i].status = IRQ_DISABLED; 98 set_irq_chip(i, &vrc5477_irq_controller);
108 irq_desc[i].action = NULL;
109 irq_desc[i].depth = 1;
110 irq_desc[i].chip = &vrc5477_irq_controller;
111 }
112 99
113 vrc5477_irq_base = irq_base; 100 vrc5477_irq_base = irq_base;
114} 101}
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 3e374d05978f..c8430c07355e 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -18,7 +18,6 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/spinlock.h>
22#include <linux/types.h> 21#include <linux/types.h>
23 22
24#include <asm/addrspace.h> 23#include <asm/addrspace.h>
@@ -231,13 +230,10 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
231static inline void dec_kn02_be_init(void) 230static inline void dec_kn02_be_init(void)
232{ 231{
233 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); 232 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
234 unsigned long flags;
235 233
236 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); 234 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
237 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); 235 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
238 236
239 spin_lock_irqsave(&kn02_lock, flags);
240
241 /* Preset write-only bits of the Control Register cache. */ 237 /* Preset write-only bits of the Control Register cache. */
242 cached_kn02_csr = *csr | KN02_CSR_LEDS; 238 cached_kn02_csr = *csr | KN02_CSR_LEDS;
243 239
@@ -247,8 +243,6 @@ static inline void dec_kn02_be_init(void)
247 cached_kn02_csr |= KN02_CSR_CORRECT; 243 cached_kn02_csr |= KN02_CSR_CORRECT;
248 *csr = cached_kn02_csr; 244 *csr = cached_kn02_csr;
249 iob(); 245 iob();
250
251 spin_unlock_irqrestore(&kn02_lock, flags);
252} 246}
253 247
254static inline void dec_kn03_be_init(void) 248static inline void dec_kn03_be_init(void)
diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index 31dd47d1002d..b251ef864c33 100644
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -267,7 +267,7 @@ handle_it:
267 LONG_L s0, TI_REGS($28) 267 LONG_L s0, TI_REGS($28)
268 LONG_S sp, TI_REGS($28) 268 LONG_S sp, TI_REGS($28)
269 PTR_LA ra, ret_from_irq 269 PTR_LA ra, ret_from_irq
270 j do_IRQ 270 j dec_irq_dispatch
271 nop 271 nop
272 272
273#ifdef CONFIG_32BIT 273#ifdef CONFIG_32BIT
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 41cd2a96148b..269b22b34313 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -13,7 +13,6 @@
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/spinlock.h>
17#include <linux/types.h> 16#include <linux/types.h>
18 17
19#include <asm/dec/ioasic.h> 18#include <asm/dec/ioasic.h>
@@ -21,8 +20,6 @@
21#include <asm/dec/ioasic_ints.h> 20#include <asm/dec/ioasic_ints.h>
22 21
23 22
24static DEFINE_SPINLOCK(ioasic_lock);
25
26static int ioasic_irq_base; 23static int ioasic_irq_base;
27 24
28 25
@@ -52,65 +49,31 @@ static inline void clear_ioasic_irq(unsigned int irq)
52 ioasic_write(IO_REG_SIR, sir); 49 ioasic_write(IO_REG_SIR, sir);
53} 50}
54 51
55static inline void enable_ioasic_irq(unsigned int irq)
56{
57 unsigned long flags;
58
59 spin_lock_irqsave(&ioasic_lock, flags);
60 unmask_ioasic_irq(irq);
61 spin_unlock_irqrestore(&ioasic_lock, flags);
62}
63
64static inline void disable_ioasic_irq(unsigned int irq)
65{
66 unsigned long flags;
67
68 spin_lock_irqsave(&ioasic_lock, flags);
69 mask_ioasic_irq(irq);
70 spin_unlock_irqrestore(&ioasic_lock, flags);
71}
72
73
74static inline unsigned int startup_ioasic_irq(unsigned int irq)
75{
76 enable_ioasic_irq(irq);
77 return 0;
78}
79
80#define shutdown_ioasic_irq disable_ioasic_irq
81
82static inline void ack_ioasic_irq(unsigned int irq) 52static inline void ack_ioasic_irq(unsigned int irq)
83{ 53{
84 spin_lock(&ioasic_lock);
85 mask_ioasic_irq(irq); 54 mask_ioasic_irq(irq);
86 spin_unlock(&ioasic_lock);
87 fast_iob(); 55 fast_iob();
88} 56}
89 57
90static inline void end_ioasic_irq(unsigned int irq) 58static inline void end_ioasic_irq(unsigned int irq)
91{ 59{
92 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 60 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
93 enable_ioasic_irq(irq); 61 unmask_ioasic_irq(irq);
94} 62}
95 63
96static struct irq_chip ioasic_irq_type = { 64static struct irq_chip ioasic_irq_type = {
97 .typename = "IO-ASIC", 65 .typename = "IO-ASIC",
98 .startup = startup_ioasic_irq,
99 .shutdown = shutdown_ioasic_irq,
100 .enable = enable_ioasic_irq,
101 .disable = disable_ioasic_irq,
102 .ack = ack_ioasic_irq, 66 .ack = ack_ioasic_irq,
67 .mask = mask_ioasic_irq,
68 .mask_ack = ack_ioasic_irq,
69 .unmask = unmask_ioasic_irq,
103 .end = end_ioasic_irq, 70 .end = end_ioasic_irq,
104}; 71};
105 72
106 73
107#define startup_ioasic_dma_irq startup_ioasic_irq 74#define unmask_ioasic_dma_irq unmask_ioasic_irq
108
109#define shutdown_ioasic_dma_irq shutdown_ioasic_irq
110
111#define enable_ioasic_dma_irq enable_ioasic_irq
112 75
113#define disable_ioasic_dma_irq disable_ioasic_irq 76#define mask_ioasic_dma_irq mask_ioasic_irq
114 77
115#define ack_ioasic_dma_irq ack_ioasic_irq 78#define ack_ioasic_dma_irq ack_ioasic_irq
116 79
@@ -123,11 +86,10 @@ static inline void end_ioasic_dma_irq(unsigned int irq)
123 86
124static struct irq_chip ioasic_dma_irq_type = { 87static struct irq_chip ioasic_dma_irq_type = {
125 .typename = "IO-ASIC-DMA", 88 .typename = "IO-ASIC-DMA",
126 .startup = startup_ioasic_dma_irq,
127 .shutdown = shutdown_ioasic_dma_irq,
128 .enable = enable_ioasic_dma_irq,
129 .disable = disable_ioasic_dma_irq,
130 .ack = ack_ioasic_dma_irq, 89 .ack = ack_ioasic_dma_irq,
90 .mask = mask_ioasic_dma_irq,
91 .mask_ack = ack_ioasic_dma_irq,
92 .unmask = unmask_ioasic_dma_irq,
131 .end = end_ioasic_dma_irq, 93 .end = end_ioasic_dma_irq,
132}; 94};
133 95
@@ -140,18 +102,12 @@ void __init init_ioasic_irqs(int base)
140 ioasic_write(IO_REG_SIMR, 0); 102 ioasic_write(IO_REG_SIMR, 0);
141 fast_iob(); 103 fast_iob();
142 104
143 for (i = base; i < base + IO_INR_DMA; i++) { 105 for (i = base; i < base + IO_INR_DMA; i++)
144 irq_desc[i].status = IRQ_DISABLED; 106 set_irq_chip_and_handler(i, &ioasic_irq_type,
145 irq_desc[i].action = 0; 107 handle_level_irq);
146 irq_desc[i].depth = 1; 108 for (; i < base + IO_IRQ_LINES; i++)
147 irq_desc[i].chip = &ioasic_irq_type; 109 set_irq_chip_and_handler(i, &ioasic_dma_irq_type,
148 } 110 handle_level_irq);
149 for (; i < base + IO_IRQ_LINES; i++) {
150 irq_desc[i].status = IRQ_DISABLED;
151 irq_desc[i].action = 0;
152 irq_desc[i].depth = 1;
153 irq_desc[i].chip = &ioasic_dma_irq_type;
154 }
155 111
156 ioasic_irq_base = base; 112 ioasic_irq_base = base;
157} 113}
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index 04a367a60a57..5a9be4c93584 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -14,7 +14,6 @@
14 14
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/spinlock.h>
18#include <linux/types.h> 17#include <linux/types.h>
19 18
20#include <asm/dec/kn02.h> 19#include <asm/dec/kn02.h>
@@ -29,7 +28,6 @@
29 * There is no default value -- it has to be initialized. 28 * There is no default value -- it has to be initialized.
30 */ 29 */
31u32 cached_kn02_csr; 30u32 cached_kn02_csr;
32DEFINE_SPINLOCK(kn02_lock);
33 31
34 32
35static int kn02_irq_base; 33static int kn02_irq_base;
@@ -53,54 +51,24 @@ static inline void mask_kn02_irq(unsigned int irq)
53 *csr = cached_kn02_csr; 51 *csr = cached_kn02_csr;
54} 52}
55 53
56static inline void enable_kn02_irq(unsigned int irq)
57{
58 unsigned long flags;
59
60 spin_lock_irqsave(&kn02_lock, flags);
61 unmask_kn02_irq(irq);
62 spin_unlock_irqrestore(&kn02_lock, flags);
63}
64
65static inline void disable_kn02_irq(unsigned int irq)
66{
67 unsigned long flags;
68
69 spin_lock_irqsave(&kn02_lock, flags);
70 mask_kn02_irq(irq);
71 spin_unlock_irqrestore(&kn02_lock, flags);
72}
73
74
75static unsigned int startup_kn02_irq(unsigned int irq)
76{
77 enable_kn02_irq(irq);
78 return 0;
79}
80
81#define shutdown_kn02_irq disable_kn02_irq
82
83static void ack_kn02_irq(unsigned int irq) 54static void ack_kn02_irq(unsigned int irq)
84{ 55{
85 spin_lock(&kn02_lock);
86 mask_kn02_irq(irq); 56 mask_kn02_irq(irq);
87 spin_unlock(&kn02_lock);
88 iob(); 57 iob();
89} 58}
90 59
91static void end_kn02_irq(unsigned int irq) 60static void end_kn02_irq(unsigned int irq)
92{ 61{
93 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 62 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
94 enable_kn02_irq(irq); 63 unmask_kn02_irq(irq);
95} 64}
96 65
97static struct irq_chip kn02_irq_type = { 66static struct irq_chip kn02_irq_type = {
98 .typename = "KN02-CSR", 67 .typename = "KN02-CSR",
99 .startup = startup_kn02_irq,
100 .shutdown = shutdown_kn02_irq,
101 .enable = enable_kn02_irq,
102 .disable = disable_kn02_irq,
103 .ack = ack_kn02_irq, 68 .ack = ack_kn02_irq,
69 .mask = mask_kn02_irq,
70 .mask_ack = ack_kn02_irq,
71 .unmask = unmask_kn02_irq,
104 .end = end_kn02_irq, 72 .end = end_kn02_irq,
105}; 73};
106 74
@@ -109,22 +77,15 @@ void __init init_kn02_irqs(int base)
109{ 77{
110 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 78 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
111 KN02_CSR); 79 KN02_CSR);
112 unsigned long flags;
113 int i; 80 int i;
114 81
115 /* Mask interrupts. */ 82 /* Mask interrupts. */
116 spin_lock_irqsave(&kn02_lock, flags);
117 cached_kn02_csr &= ~KN02_CSR_IOINTEN; 83 cached_kn02_csr &= ~KN02_CSR_IOINTEN;
118 *csr = cached_kn02_csr; 84 *csr = cached_kn02_csr;
119 iob(); 85 iob();
120 spin_unlock_irqrestore(&kn02_lock, flags); 86
121 87 for (i = base; i < base + KN02_IRQ_LINES; i++)
122 for (i = base; i < base + KN02_IRQ_LINES; i++) { 88 set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
123 irq_desc[i].status = IRQ_DISABLED;
124 irq_desc[i].action = 0;
125 irq_desc[i].depth = 1;
126 irq_desc[i].chip = &kn02_irq_type;
127 }
128 89
129 kn02_irq_base = base; 90 kn02_irq_base = base;
130} 91}
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 6b7481e97bec..d34032ac492a 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -761,3 +761,9 @@ void __init arch_init_irq(void)
761 if (dec_interrupt[DEC_IRQ_HALT] >= 0) 761 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
762 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq); 762 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
763} 763}
764
765asmlinkage unsigned int dec_irq_dispatch(unsigned int irq)
766{
767 do_IRQ(irq);
768 return 0;
769}
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 4cf0c06e2414..8b7e0c17ac35 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -151,7 +151,7 @@ static void dec_timer_ack(void)
151 CMOS_READ(RTC_REG_C); /* Ack the RTC interrupt. */ 151 CMOS_READ(RTC_REG_C); /* Ack the RTC interrupt. */
152} 152}
153 153
154static unsigned int dec_ioasic_hpt_read(void) 154static cycle_t dec_ioasic_hpt_read(void)
155{ 155{
156 /* 156 /*
157 * The free-running counter is 32-bit which is good for about 157 * The free-running counter is 32-bit which is good for about
@@ -160,11 +160,6 @@ static unsigned int dec_ioasic_hpt_read(void)
160 return ioasic_read(IO_REG_FCTR); 160 return ioasic_read(IO_REG_FCTR);
161} 161}
162 162
163static void dec_ioasic_hpt_init(unsigned int count)
164{
165 ioasic_write(IO_REG_FCTR, ioasic_read(IO_REG_FCTR) - count);
166}
167
168 163
169void __init dec_time_init(void) 164void __init dec_time_init(void)
170{ 165{
@@ -174,11 +169,9 @@ void __init dec_time_init(void)
174 mips_timer_state = dec_timer_state; 169 mips_timer_state = dec_timer_state;
175 mips_timer_ack = dec_timer_ack; 170 mips_timer_ack = dec_timer_ack;
176 171
177 if (!cpu_has_counter && IOASIC) { 172 if (!cpu_has_counter && IOASIC)
178 /* For pre-R4k systems we use the I/O ASIC's counter. */ 173 /* For pre-R4k systems we use the I/O ASIC's counter. */
179 mips_hpt_read = dec_ioasic_hpt_read; 174 clocksource_mips.read = dec_ioasic_hpt_read;
180 mips_hpt_init = dec_ioasic_hpt_init;
181 }
182 175
183 /* Set up the rate of periodic DS1287 interrupts. */ 176 /* Set up the rate of periodic DS1287 interrupts. */
184 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A); 177 CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);
diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c
index 7c930860c921..59b98299c896 100644
--- a/arch/mips/emma2rh/common/irq_emma2rh.c
+++ b/arch/mips/emma2rh/common/irq_emma2rh.c
@@ -56,22 +56,6 @@ static void emma2rh_irq_disable(unsigned int irq)
56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base); 56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
57} 57}
58 58
59static unsigned int emma2rh_irq_startup(unsigned int irq)
60{
61 emma2rh_irq_enable(irq);
62 return 0;
63}
64
65#define emma2rh_irq_shutdown emma2rh_irq_disable
66
67static void emma2rh_irq_ack(unsigned int irq)
68{
69 /* disable interrupt - some handler will re-enable the irq
70 * and if the interrupt is leveled, we will have infinite loop
71 */
72 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
73}
74
75static void emma2rh_irq_end(unsigned int irq) 59static void emma2rh_irq_end(unsigned int irq)
76{ 60{
77 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 61 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -80,25 +64,20 @@ static void emma2rh_irq_end(unsigned int irq)
80 64
81struct irq_chip emma2rh_irq_controller = { 65struct irq_chip emma2rh_irq_controller = {
82 .typename = "emma2rh_irq", 66 .typename = "emma2rh_irq",
83 .startup = emma2rh_irq_startup, 67 .ack = emma2rh_irq_disable,
84 .shutdown = emma2rh_irq_shutdown, 68 .mask = emma2rh_irq_disable,
85 .enable = emma2rh_irq_enable, 69 .mask_ack = emma2rh_irq_disable,
86 .disable = emma2rh_irq_disable, 70 .unmask = emma2rh_irq_enable,
87 .ack = emma2rh_irq_ack,
88 .end = emma2rh_irq_end, 71 .end = emma2rh_irq_end,
89 .set_affinity = NULL /* no affinity stuff for UP */
90}; 72};
91 73
92void emma2rh_irq_init(u32 irq_base) 74void emma2rh_irq_init(u32 irq_base)
93{ 75{
94 u32 i; 76 u32 i;
95 77
96 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) { 78 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++)
97 irq_desc[i].status = IRQ_DISABLED; 79 set_irq_chip_and_handler(i, &emma2rh_irq_controller,
98 irq_desc[i].action = NULL; 80 handle_level_irq);
99 irq_desc[i].depth = 1;
100 irq_desc[i].handler = &emma2rh_irq_controller;
101 }
102 81
103 emma2rh_irq_base = irq_base; 82 emma2rh_irq_base = irq_base;
104} 83}
diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c
index f23ae9fcffa0..3ac4e405ecdc 100644
--- a/arch/mips/emma2rh/markeins/irq_markeins.c
+++ b/arch/mips/emma2rh/markeins/irq_markeins.c
@@ -48,19 +48,6 @@ static void emma2rh_sw_irq_disable(unsigned int irq)
48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base); 48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
49} 49}
50 50
51static unsigned int emma2rh_sw_irq_startup(unsigned int irq)
52{
53 emma2rh_sw_irq_enable(irq);
54 return 0;
55}
56
57#define emma2rh_sw_irq_shutdown emma2rh_sw_irq_disable
58
59static void emma2rh_sw_irq_ack(unsigned int irq)
60{
61 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
62}
63
64static void emma2rh_sw_irq_end(unsigned int irq) 51static void emma2rh_sw_irq_end(unsigned int irq)
65{ 52{
66 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 53 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -69,25 +56,20 @@ static void emma2rh_sw_irq_end(unsigned int irq)
69 56
70struct irq_chip emma2rh_sw_irq_controller = { 57struct irq_chip emma2rh_sw_irq_controller = {
71 .typename = "emma2rh_sw_irq", 58 .typename = "emma2rh_sw_irq",
72 .startup = emma2rh_sw_irq_startup, 59 .ack = emma2rh_sw_irq_disable,
73 .shutdown = emma2rh_sw_irq_shutdown, 60 .mask = emma2rh_sw_irq_disable,
74 .enable = emma2rh_sw_irq_enable, 61 .mask_ack = emma2rh_sw_irq_disable,
75 .disable = emma2rh_sw_irq_disable, 62 .unmask = emma2rh_sw_irq_enable,
76 .ack = emma2rh_sw_irq_ack,
77 .end = emma2rh_sw_irq_end, 63 .end = emma2rh_sw_irq_end,
78 .set_affinity = NULL,
79}; 64};
80 65
81void emma2rh_sw_irq_init(u32 irq_base) 66void emma2rh_sw_irq_init(u32 irq_base)
82{ 67{
83 u32 i; 68 u32 i;
84 69
85 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) { 70 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++)
86 irq_desc[i].status = IRQ_DISABLED; 71 set_irq_chip_and_handler(i, &emma2rh_sw_irq_controller,
87 irq_desc[i].action = NULL; 72 handle_level_irq);
88 irq_desc[i].depth = 2;
89 irq_desc[i].handler = &emma2rh_sw_irq_controller;
90 }
91 73
92 emma2rh_sw_irq_base = irq_base; 74 emma2rh_sw_irq_base = irq_base;
93} 75}
@@ -126,14 +108,6 @@ static void emma2rh_gpio_irq_disable(unsigned int irq)
126 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base); 108 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
127} 109}
128 110
129static unsigned int emma2rh_gpio_irq_startup(unsigned int irq)
130{
131 emma2rh_gpio_irq_enable(irq);
132 return 0;
133}
134
135#define emma2rh_gpio_irq_shutdown emma2rh_gpio_irq_disable
136
137static void emma2rh_gpio_irq_ack(unsigned int irq) 111static void emma2rh_gpio_irq_ack(unsigned int irq)
138{ 112{
139 irq -= emma2rh_gpio_irq_base; 113 irq -= emma2rh_gpio_irq_base;
@@ -149,25 +123,19 @@ static void emma2rh_gpio_irq_end(unsigned int irq)
149 123
150struct irq_chip emma2rh_gpio_irq_controller = { 124struct irq_chip emma2rh_gpio_irq_controller = {
151 .typename = "emma2rh_gpio_irq", 125 .typename = "emma2rh_gpio_irq",
152 .startup = emma2rh_gpio_irq_startup,
153 .shutdown = emma2rh_gpio_irq_shutdown,
154 .enable = emma2rh_gpio_irq_enable,
155 .disable = emma2rh_gpio_irq_disable,
156 .ack = emma2rh_gpio_irq_ack, 126 .ack = emma2rh_gpio_irq_ack,
127 .mask = emma2rh_gpio_irq_disable,
128 .mask_ack = emma2rh_gpio_irq_ack,
129 .unmask = emma2rh_gpio_irq_enable,
157 .end = emma2rh_gpio_irq_end, 130 .end = emma2rh_gpio_irq_end,
158 .set_affinity = NULL,
159}; 131};
160 132
161void emma2rh_gpio_irq_init(u32 irq_base) 133void emma2rh_gpio_irq_init(u32 irq_base)
162{ 134{
163 u32 i; 135 u32 i;
164 136
165 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) { 137 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++)
166 irq_desc[i].status = IRQ_DISABLED; 138 set_irq_chip(i, &emma2rh_gpio_irq_controller);
167 irq_desc[i].action = NULL;
168 irq_desc[i].depth = 2;
169 irq_desc[i].handler = &emma2rh_gpio_irq_controller;
170 }
171 139
172 emma2rh_gpio_irq_base = irq_base; 140 emma2rh_gpio_irq_base = irq_base;
173} 141}
diff --git a/arch/mips/emma2rh/markeins/platform.c b/arch/mips/emma2rh/markeins/platform.c
index 15cc61df3622..11567702b155 100644
--- a/arch/mips/emma2rh/markeins/platform.c
+++ b/arch/mips/emma2rh/markeins/platform.c
@@ -44,18 +44,45 @@
44#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */ 44#define I2C_EMMA2RH "emma2rh-iic" /* must be in sync with IIC driver */
45 45
46static struct resource i2c_emma_resources_0[] = { 46static struct resource i2c_emma_resources_0[] = {
47 { NULL, EMMA2RH_IRQ_PIIC0, EMMA2RH_IRQ_PIIC0, IORESOURCE_IRQ }, 47 {
48 { NULL, KSEG1ADDR(EMMA2RH_PIIC0_BASE), KSEG1ADDR(EMMA2RH_PIIC0_BASE + 0x1000), 0 }, 48 .name = NULL,
49 .start = EMMA2RH_IRQ_PIIC0,
50 .end = EMMA2RH_IRQ_PIIC0,
51 .flags = IORESOURCE_IRQ
52 }, {
53 .name = NULL,
54 .start = EMMA2RH_PIIC0_BASE,
55 .end = EMMA2RH_PIIC0_BASE + 0x1000,
56 .flags = 0
57 },
49}; 58};
50 59
51struct resource i2c_emma_resources_1[] = { 60struct resource i2c_emma_resources_1[] = {
52 { NULL, EMMA2RH_IRQ_PIIC1, EMMA2RH_IRQ_PIIC1, IORESOURCE_IRQ }, 61 {
53 { NULL, KSEG1ADDR(EMMA2RH_PIIC1_BASE), KSEG1ADDR(EMMA2RH_PIIC1_BASE + 0x1000), 0 }, 62 .name = NULL,
63 .start = EMMA2RH_IRQ_PIIC1,
64 .end = EMMA2RH_IRQ_PIIC1,
65 .flags = IORESOURCE_IRQ
66 }, {
67 .name = NULL,
68 .start = EMMA2RH_PIIC1_BASE,
69 .end = EMMA2RH_PIIC1_BASE + 0x1000,
70 .flags = 0
71 },
54}; 72};
55 73
56struct resource i2c_emma_resources_2[] = { 74struct resource i2c_emma_resources_2[] = {
57 { NULL, EMMA2RH_IRQ_PIIC2, EMMA2RH_IRQ_PIIC2, IORESOURCE_IRQ }, 75 {
58 { NULL, KSEG1ADDR(EMMA2RH_PIIC2_BASE), KSEG1ADDR(EMMA2RH_PIIC2_BASE + 0x1000), 0 }, 76 .name = NULL,
77 .start = EMMA2RH_IRQ_PIIC2,
78 .end = EMMA2RH_IRQ_PIIC2,
79 .flags = IORESOURCE_IRQ
80 }, {
81 .name = NULL,
82 .start = EMMA2RH_PIIC2_BASE,
83 .end = EMMA2RH_PIIC2_BASE + 0x1000,
84 .flags = 0
85 },
59}; 86};
60 87
61struct platform_device i2c_emma_devices[] = { 88struct platform_device i2c_emma_devices[] = {
@@ -83,32 +110,29 @@ struct platform_device i2c_emma_devices[] = {
83#define EMMA2RH_SERIAL_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST 110#define EMMA2RH_SERIAL_FLAGS UPF_BOOT_AUTOCONF | UPF_SKIP_TEST
84 111
85static struct plat_serial8250_port platform_serial_ports[] = { 112static struct plat_serial8250_port platform_serial_ports[] = {
86 [0] = { 113 [0] = {
87 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3), 114 .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3),
88 .irq = EMMA2RH_IRQ_PFUR0, 115 .irq = EMMA2RH_IRQ_PFUR0,
89 .uartclk = EMMA2RH_SERIAL_CLOCK, 116 .uartclk = EMMA2RH_SERIAL_CLOCK,
90 .regshift = 4, 117 .regshift = 4,
91 .iotype = UPIO_MEM, 118 .iotype = UPIO_MEM,
92 .flags = EMMA2RH_SERIAL_FLAGS, 119 .flags = EMMA2RH_SERIAL_FLAGS,
93 }, 120 }, [1] = {
94 [1] = { 121 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3),
95 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3), 122 .irq = EMMA2RH_IRQ_PFUR1,
96 .irq = EMMA2RH_IRQ_PFUR1, 123 .uartclk = EMMA2RH_SERIAL_CLOCK,
97 .uartclk = EMMA2RH_SERIAL_CLOCK, 124 .regshift = 4,
98 .regshift = 4, 125 .iotype = UPIO_MEM,
99 .iotype = UPIO_MEM, 126 .flags = EMMA2RH_SERIAL_FLAGS,
100 .flags = EMMA2RH_SERIAL_FLAGS, 127 }, [2] = {
101 }, 128 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3),
102 [2] = { 129 .irq = EMMA2RH_IRQ_PFUR2,
103 .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3), 130 .uartclk = EMMA2RH_SERIAL_CLOCK,
104 .irq = EMMA2RH_IRQ_PFUR2, 131 .regshift = 4,
105 .uartclk = EMMA2RH_SERIAL_CLOCK, 132 .iotype = UPIO_MEM,
106 .regshift = 4, 133 .flags = EMMA2RH_SERIAL_FLAGS,
107 .iotype = UPIO_MEM, 134 }, [3] = {
108 .flags = EMMA2RH_SERIAL_FLAGS, 135 .flags = 0,
109 },
110 [3] = {
111 .flags = 0,
112 }, 136 },
113}; 137};
114 138
diff --git a/arch/mips/gt64120/common/time.c b/arch/mips/gt64120/common/time.c
index c83ae6acd601..c47eeb768192 100644
--- a/arch/mips/gt64120/common/time.c
+++ b/arch/mips/gt64120/common/time.c
@@ -64,14 +64,14 @@ static irqreturn_t gt64120_irq(int irq, void *dev_id)
64 * as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt 64 * as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt
65 * handling. 65 * handling.
66 */ 66 */
67void gt64120_time_init(void) 67void __init plat_timer_setup(struct irqaction *irq)
68{ 68{
69 static struct irqaction timer; 69 static struct irqaction timer;
70 70
71 /* Disable timer first */ 71 /* Disable timer first */
72 GT_WRITE(GT_TC_CONTROL_OFS, 0); 72 GT_WRITE(GT_TC_CONTROL_OFS, 0);
73 /* Load timer value for 100 Hz */ 73 /* Load timer value for 100 Hz */
74 GT_WRITE(GT_TC3_OFS, Sys_clock / 100); 74 GT_WRITE(GT_TC3_OFS, Sys_clock / HZ);
75 75
76 /* 76 /*
77 * Create the IRQ structure entry for the timer. Since we're too early 77 * Create the IRQ structure entry for the timer. Since we're too early
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
index ed4d82b9a24a..b3e5796c81d7 100644
--- a/arch/mips/gt64120/ev64120/irq.c
+++ b/arch/mips/gt64120/ev64120/irq.c
@@ -66,38 +66,21 @@ asmlinkage void plat_irq_dispatch(void)
66 66
67static void disable_ev64120_irq(unsigned int irq_nr) 67static void disable_ev64120_irq(unsigned int irq_nr)
68{ 68{
69 unsigned long flags;
70
71 local_irq_save(flags);
72 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2 69 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2
73 clear_c0_status(9 << 10); 70 clear_c0_status(9 << 10);
74 } else { 71 } else {
75 clear_c0_status(1 << (irq_nr + 8)); 72 clear_c0_status(1 << (irq_nr + 8));
76 } 73 }
77 local_irq_restore(flags);
78} 74}
79 75
80static void enable_ev64120_irq(unsigned int irq_nr) 76static void enable_ev64120_irq(unsigned int irq_nr)
81{ 77{
82 unsigned long flags;
83
84 local_irq_save(flags);
85 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2 78 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2
86 set_c0_status(9 << 10); 79 set_c0_status(9 << 10);
87 else 80 else
88 set_c0_status(1 << (irq_nr + 8)); 81 set_c0_status(1 << (irq_nr + 8));
89 local_irq_restore(flags);
90}
91
92static unsigned int startup_ev64120_irq(unsigned int irq)
93{
94 enable_ev64120_irq(irq);
95 return 0; /* Never anything pending */
96} 82}
97 83
98#define shutdown_ev64120_irq disable_ev64120_irq
99#define mask_and_ack_ev64120_irq disable_ev64120_irq
100
101static void end_ev64120_irq(unsigned int irq) 84static void end_ev64120_irq(unsigned int irq)
102{ 85{
103 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 86 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -106,13 +89,11 @@ static void end_ev64120_irq(unsigned int irq)
106 89
107static struct irq_chip ev64120_irq_type = { 90static struct irq_chip ev64120_irq_type = {
108 .typename = "EV64120", 91 .typename = "EV64120",
109 .startup = startup_ev64120_irq, 92 .ack = disable_ev64120_irq,
110 .shutdown = shutdown_ev64120_irq, 93 .mask = disable_ev64120_irq,
111 .enable = enable_ev64120_irq, 94 .mask_ack = disable_ev64120_irq,
112 .disable = disable_ev64120_irq, 95 .unmask = enable_ev64120_irq,
113 .ack = mask_and_ack_ev64120_irq,
114 .end = end_ev64120_irq, 96 .end = end_ev64120_irq,
115 .set_affinity = NULL
116}; 97};
117 98
118void gt64120_irq_setup(void) 99void gt64120_irq_setup(void)
@@ -122,8 +103,6 @@ void gt64120_irq_setup(void)
122 */ 103 */
123 clear_c0_status(ST0_IM); 104 clear_c0_status(ST0_IM);
124 105
125 local_irq_disable();
126
127 /* 106 /*
128 * Enable timer. Other interrupts will be enabled as they are 107 * Enable timer. Other interrupts will be enabled as they are
129 * registered. 108 * registered.
@@ -133,16 +112,5 @@ void gt64120_irq_setup(void)
133 112
134void __init arch_init_irq(void) 113void __init arch_init_irq(void)
135{ 114{
136 int i;
137
138 /* Let's initialize our IRQ descriptors */
139 for (i = 0; i < NR_IRQS; i++) {
140 irq_desc[i].status = 0;
141 irq_desc[i].chip = &no_irq_chip;
142 irq_desc[i].action = NULL;
143 irq_desc[i].depth = 0;
144 spin_lock_init(&irq_desc[i].lock);
145 }
146
147 gt64120_irq_setup(); 115 gt64120_irq_setup();
148} 116}
diff --git a/arch/mips/gt64120/ev64120/setup.c b/arch/mips/gt64120/ev64120/setup.c
index 91c2d3f41617..99c8d42212e2 100644
--- a/arch/mips/gt64120/ev64120/setup.c
+++ b/arch/mips/gt64120/ev64120/setup.c
@@ -68,7 +68,6 @@ unsigned long __init prom_free_prom_memory(void)
68 * Initializes basic routines and structures pointers, memory size (as 68 * Initializes basic routines and structures pointers, memory size (as
69 * given by the bios and saves the command line. 69 * given by the bios and saves the command line.
70 */ 70 */
71extern void gt64120_time_init(void);
72 71
73void __init plat_mem_setup(void) 72void __init plat_mem_setup(void)
74{ 73{
@@ -76,7 +75,6 @@ void __init plat_mem_setup(void)
76 _machine_halt = galileo_machine_halt; 75 _machine_halt = galileo_machine_halt;
77 pm_power_off = galileo_machine_power_off; 76 pm_power_off = galileo_machine_power_off;
78 77
79 board_time_init = gt64120_time_init;
80 set_io_port_base(KSEG1); 78 set_io_port_base(KSEG1);
81} 79}
82 80
diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c
index 0e5bbee2d5b7..94f94ebbda6c 100644
--- a/arch/mips/gt64120/momenco_ocelot/setup.c
+++ b/arch/mips/gt64120/momenco_ocelot/setup.c
@@ -70,7 +70,6 @@ extern void momenco_ocelot_restart(char *command);
70extern void momenco_ocelot_halt(void); 70extern void momenco_ocelot_halt(void);
71extern void momenco_ocelot_power_off(void); 71extern void momenco_ocelot_power_off(void);
72 72
73extern void gt64120_time_init(void);
74extern void momenco_ocelot_irq_setup(void); 73extern void momenco_ocelot_irq_setup(void);
75 74
76static char reset_reason; 75static char reset_reason;
@@ -156,8 +155,6 @@ void __init plat_mem_setup(void)
156 void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache); 155 void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
157 unsigned int tmpword; 156 unsigned int tmpword;
158 157
159 board_time_init = gt64120_time_init;
160
161 _machine_restart = momenco_ocelot_restart; 158 _machine_restart = momenco_ocelot_restart;
162 _machine_halt = momenco_ocelot_halt; 159 _machine_halt = momenco_ocelot_halt;
163 pm_power_off = momenco_ocelot_power_off; 160 pm_power_off = momenco_ocelot_power_off;
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index d5bd6b3a0933..5c4f50cdf157 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -28,14 +28,6 @@ static void enable_r4030_irq(unsigned int irq)
28 spin_unlock_irqrestore(&r4030_lock, flags); 28 spin_unlock_irqrestore(&r4030_lock, flags);
29} 29}
30 30
31static unsigned int startup_r4030_irq(unsigned int irq)
32{
33 enable_r4030_irq(irq);
34 return 0; /* never anything pending */
35}
36
37#define shutdown_r4030_irq disable_r4030_irq
38
39void disable_r4030_irq(unsigned int irq) 31void disable_r4030_irq(unsigned int irq)
40{ 32{
41 unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ)); 33 unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ));
@@ -47,8 +39,6 @@ void disable_r4030_irq(unsigned int irq)
47 spin_unlock_irqrestore(&r4030_lock, flags); 39 spin_unlock_irqrestore(&r4030_lock, flags);
48} 40}
49 41
50#define mask_and_ack_r4030_irq disable_r4030_irq
51
52static void end_r4030_irq(unsigned int irq) 42static void end_r4030_irq(unsigned int irq)
53{ 43{
54 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 44 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -57,11 +47,10 @@ static void end_r4030_irq(unsigned int irq)
57 47
58static struct irq_chip r4030_irq_type = { 48static struct irq_chip r4030_irq_type = {
59 .typename = "R4030", 49 .typename = "R4030",
60 .startup = startup_r4030_irq, 50 .ack = disable_r4030_irq,
61 .shutdown = shutdown_r4030_irq, 51 .mask = disable_r4030_irq,
62 .enable = enable_r4030_irq, 52 .mask_ack = disable_r4030_irq,
63 .disable = disable_r4030_irq, 53 .unmask = enable_r4030_irq,
64 .ack = mask_and_ack_r4030_irq,
65 .end = end_r4030_irq, 54 .end = end_r4030_irq,
66}; 55};
67 56
@@ -69,12 +58,8 @@ void __init init_r4030_ints(void)
69{ 58{
70 int i; 59 int i;
71 60
72 for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) { 61 for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++)
73 irq_desc[i].status = IRQ_DISABLED; 62 set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
74 irq_desc[i].action = 0;
75 irq_desc[i].depth = 1;
76 irq_desc[i].chip = &r4030_irq_type;
77 }
78 63
79 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); 64 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
80 r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ 65 r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index 39a0243bed9a..3da49c5aaf49 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -90,17 +90,6 @@ static unsigned char irc_level[TX3927_NUM_IR] = {
90static void jmr3927_irq_disable(unsigned int irq_nr); 90static void jmr3927_irq_disable(unsigned int irq_nr);
91static void jmr3927_irq_enable(unsigned int irq_nr); 91static void jmr3927_irq_enable(unsigned int irq_nr);
92 92
93static DEFINE_SPINLOCK(jmr3927_irq_lock);
94
95static unsigned int jmr3927_irq_startup(unsigned int irq)
96{
97 jmr3927_irq_enable(irq);
98
99 return 0;
100}
101
102#define jmr3927_irq_shutdown jmr3927_irq_disable
103
104static void jmr3927_irq_ack(unsigned int irq) 93static void jmr3927_irq_ack(unsigned int irq)
105{ 94{
106 if (irq == JMR3927_IRQ_IRC_TMR0) 95 if (irq == JMR3927_IRQ_IRC_TMR0)
@@ -118,9 +107,7 @@ static void jmr3927_irq_end(unsigned int irq)
118static void jmr3927_irq_disable(unsigned int irq_nr) 107static void jmr3927_irq_disable(unsigned int irq_nr)
119{ 108{
120 struct tb_irq_space* sp; 109 struct tb_irq_space* sp;
121 unsigned long flags;
122 110
123 spin_lock_irqsave(&jmr3927_irq_lock, flags);
124 for (sp = tb_irq_spaces; sp; sp = sp->next) { 111 for (sp = tb_irq_spaces; sp; sp = sp->next) {
125 if (sp->start_irqno <= irq_nr && 112 if (sp->start_irqno <= irq_nr &&
126 irq_nr < sp->start_irqno + sp->nr_irqs) { 113 irq_nr < sp->start_irqno + sp->nr_irqs) {
@@ -130,15 +117,12 @@ static void jmr3927_irq_disable(unsigned int irq_nr)
130 break; 117 break;
131 } 118 }
132 } 119 }
133 spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
134} 120}
135 121
136static void jmr3927_irq_enable(unsigned int irq_nr) 122static void jmr3927_irq_enable(unsigned int irq_nr)
137{ 123{
138 struct tb_irq_space* sp; 124 struct tb_irq_space* sp;
139 unsigned long flags;
140 125
141 spin_lock_irqsave(&jmr3927_irq_lock, flags);
142 for (sp = tb_irq_spaces; sp; sp = sp->next) { 126 for (sp = tb_irq_spaces; sp; sp = sp->next) {
143 if (sp->start_irqno <= irq_nr && 127 if (sp->start_irqno <= irq_nr &&
144 irq_nr < sp->start_irqno + sp->nr_irqs) { 128 irq_nr < sp->start_irqno + sp->nr_irqs) {
@@ -148,7 +132,6 @@ static void jmr3927_irq_enable(unsigned int irq_nr)
148 break; 132 break;
149 } 133 }
150 } 134 }
151 spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
152} 135}
153 136
154/* 137/*
@@ -288,6 +271,8 @@ static void tx_branch_likely_bug_fixup(void)
288 271
289static void jmr3927_spurious(void) 272static void jmr3927_spurious(void)
290{ 273{
274 struct pt_regs * regs = get_irq_regs();
275
291#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND 276#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
292 tx_branch_likely_bug_fixup(); 277 tx_branch_likely_bug_fixup();
293#endif 278#endif
@@ -297,6 +282,7 @@ static void jmr3927_spurious(void)
297 282
298asmlinkage void plat_irq_dispatch(void) 283asmlinkage void plat_irq_dispatch(void)
299{ 284{
285 struct pt_regs * regs = get_irq_regs();
300 int irq; 286 int irq;
301 287
302#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND 288#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
@@ -454,11 +440,10 @@ void __init arch_init_irq(void)
454 440
455static struct irq_chip jmr3927_irq_controller = { 441static struct irq_chip jmr3927_irq_controller = {
456 .typename = "jmr3927_irq", 442 .typename = "jmr3927_irq",
457 .startup = jmr3927_irq_startup,
458 .shutdown = jmr3927_irq_shutdown,
459 .enable = jmr3927_irq_enable,
460 .disable = jmr3927_irq_disable,
461 .ack = jmr3927_irq_ack, 443 .ack = jmr3927_irq_ack,
444 .mask = jmr3927_irq_disable,
445 .mask_ack = jmr3927_irq_ack,
446 .unmask = jmr3927_irq_enable,
462 .end = jmr3927_irq_end, 447 .end = jmr3927_irq_end,
463}; 448};
464 449
@@ -466,12 +451,8 @@ void jmr3927_irq_init(u32 irq_base)
466{ 451{
467 u32 i; 452 u32 i;
468 453
469 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) { 454 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++)
470 irq_desc[i].status = IRQ_DISABLED; 455 set_irq_chip(i, &jmr3927_irq_controller);
471 irq_desc[i].action = NULL;
472 irq_desc[i].depth = 1;
473 irq_desc[i].chip = &jmr3927_irq_controller;
474 }
475 456
476 jmr3927_irq_base = irq_base; 457 jmr3927_irq_base = irq_base;
477} 458}
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index 025434054ed0..138f25efe38a 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -170,12 +170,20 @@ static void jmr3927_machine_power_off(void)
170 while (1); 170 while (1);
171} 171}
172 172
173static cycle_t jmr3927_hpt_read(void)
174{
175 /* We assume this function is called xtime_lock held. */
176 return jiffies * (JMR3927_TIMER_CLK / HZ) + jmr3927_tmrptr->trr;
177}
178
173#define USE_RTC_DS1742 179#define USE_RTC_DS1742
174#ifdef USE_RTC_DS1742 180#ifdef USE_RTC_DS1742
175extern void rtc_ds1742_init(unsigned long base); 181extern void rtc_ds1742_init(unsigned long base);
176#endif 182#endif
177static void __init jmr3927_time_init(void) 183static void __init jmr3927_time_init(void)
178{ 184{
185 clocksource_mips.read = jmr3927_hpt_read;
186 mips_hpt_frequency = JMR3927_TIMER_CLK;
179#ifdef USE_RTC_DS1742 187#ifdef USE_RTC_DS1742
180 if (jmr3927_have_nvram()) { 188 if (jmr3927_have_nvram()) {
181 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR); 189 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
@@ -183,12 +191,8 @@ static void __init jmr3927_time_init(void)
183#endif 191#endif
184} 192}
185 193
186unsigned long jmr3927_do_gettimeoffset(void);
187
188void __init plat_timer_setup(struct irqaction *irq) 194void __init plat_timer_setup(struct irqaction *irq)
189{ 195{
190 do_gettimeoffset = jmr3927_do_gettimeoffset;
191
192 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ; 196 jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
193 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE; 197 jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
194 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD; 198 jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
@@ -200,34 +204,6 @@ void __init plat_timer_setup(struct irqaction *irq)
200 204
201#define USECS_PER_JIFFY (1000000/HZ) 205#define USECS_PER_JIFFY (1000000/HZ)
202 206
203unsigned long jmr3927_do_gettimeoffset(void)
204{
205 unsigned long count;
206 unsigned long res = 0;
207
208 /* MUST read TRR before TISR. */
209 count = jmr3927_tmrptr->trr;
210
211 if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
212 /* timer interrupt is pending. use Max value. */
213 res = USECS_PER_JIFFY - 1;
214 } else {
215 /* convert to usec */
216 /* res = count / (JMR3927_TIMER_CLK / 1000000); */
217 res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
218
219 /*
220 * Due to possible jiffies inconsistencies, we need to check
221 * the result so that we'll get a timer that is monotonic.
222 */
223 if (res >= USECS_PER_JIFFY)
224 res = USECS_PER_JIFFY-1;
225 }
226
227 return res;
228}
229
230
231//#undef DO_WRITE_THROUGH 207//#undef DO_WRITE_THROUGH
232#define DO_WRITE_THROUGH 208#define DO_WRITE_THROUGH
233#define DO_ENABLE_CACHE 209#define DO_ENABLE_CACHE
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index cd9cec9e39e9..bbbb8d7cb89b 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -6,7 +6,7 @@ extra-y := head.o init_task.o vmlinux.lds
6 6
7obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ 7obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
8 ptrace.o reset.o semaphore.o setup.o signal.o syscall.o \ 8 ptrace.o reset.o semaphore.o setup.o signal.o syscall.o \
9 time.o traps.o unaligned.o 9 time.o topology.o traps.o unaligned.o
10 10
11binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ 11binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
12 irix5sys.o sysirix.o 12 irix5sys.o sysirix.o
@@ -45,7 +45,6 @@ obj-$(CONFIG_MIPS_APSP_KSPD) += kspd.o
45obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o 45obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
46obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o 46obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
47 47
48obj-$(CONFIG_NO_ISA) += dma-no-isa.o
49obj-$(CONFIG_I8259) += i8259.o 48obj-$(CONFIG_I8259) += i8259.o
50obj-$(CONFIG_IRQ_CPU) += irq_cpu.o 49obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
51obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o 50obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
@@ -67,6 +66,8 @@ obj-$(CONFIG_64BIT) += cpu-bugs64.o
67 66
68obj-$(CONFIG_I8253) += i8253.o 67obj-$(CONFIG_I8253) += i8253.o
69 68
69obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
70
70CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) 71CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
71 72
72EXTRA_AFLAGS := $(CFLAGS) 73EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index e9ce5b3721af..ff88b06f89df 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -22,7 +22,7 @@
22#define offset(string, ptr, member) \ 22#define offset(string, ptr, member) \
23 __asm__("\n@@@" string "%0" : : "i" (_offset(ptr, member))) 23 __asm__("\n@@@" string "%0" : : "i" (_offset(ptr, member)))
24#define constant(string, member) \ 24#define constant(string, member) \
25 __asm__("\n@@@" string "%x0" : : "ri" (member)) 25 __asm__("\n@@@" string "%X0" : : "ri" (member))
26#define size(string, size) \ 26#define size(string, size) \
27 __asm__("\n@@@" string "%0" : : "i" (sizeof(size))) 27 __asm__("\n@@@" string "%0" : : "i" (sizeof(size)))
28#define linefeed text("") 28#define linefeed text("")
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 8485af340ee1..442839e9578c 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -110,9 +110,8 @@ static inline void check_wait(void)
110{ 110{
111 struct cpuinfo_mips *c = &current_cpu_data; 111 struct cpuinfo_mips *c = &current_cpu_data;
112 112
113 printk("Checking for 'wait' instruction... ");
114 if (nowait) { 113 if (nowait) {
115 printk (" disabled.\n"); 114 printk("Wait instruction disabled.\n");
116 return; 115 return;
117 } 116 }
118 117
@@ -120,11 +119,9 @@ static inline void check_wait(void)
120 case CPU_R3081: 119 case CPU_R3081:
121 case CPU_R3081E: 120 case CPU_R3081E:
122 cpu_wait = r3081_wait; 121 cpu_wait = r3081_wait;
123 printk(" available.\n");
124 break; 122 break;
125 case CPU_TX3927: 123 case CPU_TX3927:
126 cpu_wait = r39xx_wait; 124 cpu_wait = r39xx_wait;
127 printk(" available.\n");
128 break; 125 break;
129 case CPU_R4200: 126 case CPU_R4200:
130/* case CPU_R4300: */ 127/* case CPU_R4300: */
@@ -146,33 +143,23 @@ static inline void check_wait(void)
146 case CPU_74K: 143 case CPU_74K:
147 case CPU_PR4450: 144 case CPU_PR4450:
148 cpu_wait = r4k_wait; 145 cpu_wait = r4k_wait;
149 printk(" available.\n");
150 break; 146 break;
151 case CPU_TX49XX: 147 case CPU_TX49XX:
152 cpu_wait = r4k_wait_irqoff; 148 cpu_wait = r4k_wait_irqoff;
153 printk(" available.\n");
154 break; 149 break;
155 case CPU_AU1000: 150 case CPU_AU1000:
156 case CPU_AU1100: 151 case CPU_AU1100:
157 case CPU_AU1500: 152 case CPU_AU1500:
158 case CPU_AU1550: 153 case CPU_AU1550:
159 case CPU_AU1200: 154 case CPU_AU1200:
160 if (allow_au1k_wait) { 155 if (allow_au1k_wait)
161 cpu_wait = au1k_wait; 156 cpu_wait = au1k_wait;
162 printk(" available.\n");
163 } else
164 printk(" unavailable.\n");
165 break; 157 break;
166 case CPU_RM9000: 158 case CPU_RM9000:
167 if ((c->processor_id & 0x00ff) >= 0x40) { 159 if ((c->processor_id & 0x00ff) >= 0x40)
168 cpu_wait = r4k_wait; 160 cpu_wait = r4k_wait;
169 printk(" available.\n");
170 } else {
171 printk(" unavailable.\n");
172 }
173 break; 161 break;
174 default: 162 default:
175 printk(" unavailable.\n");
176 break; 163 break;
177 } 164 }
178} 165}
diff --git a/arch/mips/kernel/dma-no-isa.c b/arch/mips/kernel/dma-no-isa.c
deleted file mode 100644
index 6df8b07741e3..000000000000
--- a/arch/mips/kernel/dma-no-isa.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 by Ralf Baechle
7 *
8 * Dummy ISA DMA functions for systems that don't have ISA but share drivers
9 * with ISA such as legacy free PCI.
10 */
11#include <linux/errno.h>
12#include <linux/module.h>
13#include <linux/spinlock.h>
14
15DEFINE_SPINLOCK(dma_spin_lock);
16
17int request_dma(unsigned int dmanr, const char * device_id)
18{
19 return -EINVAL;
20}
21
22void free_dma(unsigned int dmanr)
23{
24}
25
26EXPORT_SYMBOL(dma_spin_lock);
27EXPORT_SYMBOL(request_dma);
28EXPORT_SYMBOL(free_dma);
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index 417c08ac76eb..f10b6a19f8bf 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -83,7 +83,10 @@ FEXPORT(syscall_exit)
83FEXPORT(restore_all) # restore full frame 83FEXPORT(restore_all) # restore full frame
84#ifdef CONFIG_MIPS_MT_SMTC 84#ifdef CONFIG_MIPS_MT_SMTC
85/* Detect and execute deferred IPI "interrupts" */ 85/* Detect and execute deferred IPI "interrupts" */
86 LONG_L s0, TI_REGS($28)
87 LONG_S sp, TI_REGS($28)
86 jal deferred_smtc_ipi 88 jal deferred_smtc_ipi
89 LONG_S s0, TI_REGS($28)
87/* Re-arm any temporarily masked interrupts not explicitly "acked" */ 90/* Re-arm any temporarily masked interrupts not explicitly "acked" */
88 mfc0 v0, CP0_TCSTATUS 91 mfc0 v0, CP0_TCSTATUS
89 ori v1, v0, TCSTATUS_IXMT 92 ori v1, v0, TCSTATUS_IXMT
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 5baca16993d0..aacd4a005c5f 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -19,6 +19,7 @@
19#include <asm/mipsregs.h> 19#include <asm/mipsregs.h>
20#include <asm/stackframe.h> 20#include <asm/stackframe.h>
21#include <asm/war.h> 21#include <asm/war.h>
22#include <asm/page.h>
22 23
23#define PANIC_PIC(msg) \ 24#define PANIC_PIC(msg) \
24 .set push; \ 25 .set push; \
@@ -378,6 +379,68 @@ NESTED(nmi_handler, PT_SIZE, sp)
378 BUILD_HANDLER dsp dsp sti silent /* #26 */ 379 BUILD_HANDLER dsp dsp sti silent /* #26 */
379 BUILD_HANDLER reserved reserved sti verbose /* others */ 380 BUILD_HANDLER reserved reserved sti verbose /* others */
380 381
382 .align 5
383 LEAF(handle_ri_rdhwr_vivt)
384#ifdef CONFIG_MIPS_MT_SMTC
385 PANIC_PIC("handle_ri_rdhwr_vivt called")
386#else
387 .set push
388 .set noat
389 .set noreorder
390 /* check if TLB contains a entry for EPC */
391 MFC0 k1, CP0_ENTRYHI
392 andi k1, 0xff /* ASID_MASK */
393 MFC0 k0, CP0_EPC
394 PTR_SRL k0, PAGE_SHIFT + 1
395 PTR_SLL k0, PAGE_SHIFT + 1
396 or k1, k0
397 MTC0 k1, CP0_ENTRYHI
398 mtc0_tlbw_hazard
399 tlbp
400 tlb_probe_hazard
401 mfc0 k1, CP0_INDEX
402 .set pop
403 bltz k1, handle_ri /* slow path */
404 /* fall thru */
405#endif
406 END(handle_ri_rdhwr_vivt)
407
408 LEAF(handle_ri_rdhwr)
409 .set push
410 .set noat
411 .set noreorder
412 /* 0x7c03e83b: rdhwr v1,$29 */
413 MFC0 k1, CP0_EPC
414 lui k0, 0x7c03
415 lw k1, (k1)
416 ori k0, 0xe83b
417 .set reorder
418 bne k0, k1, handle_ri /* if not ours */
419 /* The insn is rdhwr. No need to check CAUSE.BD here. */
420 get_saved_sp /* k1 := current_thread_info */
421 .set noreorder
422 MFC0 k0, CP0_EPC
423#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
424 ori k1, _THREAD_MASK
425 xori k1, _THREAD_MASK
426 LONG_L v1, TI_TP_VALUE(k1)
427 LONG_ADDIU k0, 4
428 jr k0
429 rfe
430#else
431 LONG_ADDIU k0, 4 /* stall on $k0 */
432 MTC0 k0, CP0_EPC
433 /* I hope three instructions between MTC0 and ERET are enough... */
434 ori k1, _THREAD_MASK
435 xori k1, _THREAD_MASK
436 LONG_L v1, TI_TP_VALUE(k1)
437 .set mips3
438 eret
439 .set mips0
440#endif
441 .set pop
442 END(handle_ri_rdhwr)
443
381#ifdef CONFIG_64BIT 444#ifdef CONFIG_64BIT
382/* A temporary overflow handler used by check_daddi(). */ 445/* A temporary overflow handler used by check_daddi(). */
383 446
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 8c6db0fc72f0..a2e095adaa3f 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -189,7 +189,8 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
189 189
190 MTC0 zero, CP0_CONTEXT # clear context register 190 MTC0 zero, CP0_CONTEXT # clear context register
191 PTR_LA $28, init_thread_union 191 PTR_LA $28, init_thread_union
192 PTR_ADDIU sp, $28, _THREAD_SIZE - 32 192 PTR_LI sp, _THREAD_SIZE - 32
193 PTR_ADDU sp, $28
193 set_saved_sp sp, t0, t1 194 set_saved_sp sp, t0, t1
194 PTR_SUBU sp, 4 * SZREG # init stack pointer 195 PTR_SUBU sp, 4 * SZREG # init stack pointer
195 196
@@ -249,6 +250,9 @@ NESTED(smp_bootstrap, 16, sp)
249 */ 250 */
250 page swapper_pg_dir, _PGD_ORDER 251 page swapper_pg_dir, _PGD_ORDER
251#ifdef CONFIG_64BIT 252#ifdef CONFIG_64BIT
253#if defined(CONFIG_MODULES) && !defined(CONFIG_BUILD_ELF64)
254 page module_pg_dir, _PGD_ORDER
255#endif
252 page invalid_pmd_table, _PMD_ORDER 256 page invalid_pmd_table, _PMD_ORDER
253#endif 257#endif
254 page invalid_pte_table, _PTE_ORDER 258 page invalid_pte_table, _PTE_ORDER
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 48e3418c217b..2526c0ca4d81 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -40,21 +40,10 @@ static void end_8259A_irq (unsigned int irq)
40 enable_8259A_irq(irq); 40 enable_8259A_irq(irq);
41} 41}
42 42
43#define shutdown_8259A_irq disable_8259A_irq
44
45void mask_and_ack_8259A(unsigned int); 43void mask_and_ack_8259A(unsigned int);
46 44
47static unsigned int startup_8259A_irq(unsigned int irq)
48{
49 enable_8259A_irq(irq);
50
51 return 0; /* never anything pending */
52}
53
54static struct irq_chip i8259A_irq_type = { 45static struct irq_chip i8259A_irq_type = {
55 .typename = "XT-PIC", 46 .typename = "XT-PIC",
56 .startup = startup_8259A_irq,
57 .shutdown = shutdown_8259A_irq,
58 .enable = enable_8259A_irq, 47 .enable = enable_8259A_irq,
59 .disable = disable_8259A_irq, 48 .disable = disable_8259A_irq,
60 .ack = mask_and_ack_8259A, 49 .ack = mask_and_ack_8259A,
@@ -120,7 +109,7 @@ int i8259A_irq_pending(unsigned int irq)
120void make_8259A_irq(unsigned int irq) 109void make_8259A_irq(unsigned int irq)
121{ 110{
122 disable_irq_nosync(irq); 111 disable_irq_nosync(irq);
123 irq_desc[irq].chip = &i8259A_irq_type; 112 set_irq_chip(irq, &i8259A_irq_type);
124 enable_irq(irq); 113 enable_irq(irq);
125} 114}
126 115
@@ -323,12 +312,8 @@ void __init init_i8259_irqs (void)
323 312
324 init_8259A(0); 313 init_8259A(0);
325 314
326 for (i = 0; i < 16; i++) { 315 for (i = 0; i < 16; i++)
327 irq_desc[i].status = IRQ_DISABLED; 316 set_irq_chip(i, &i8259A_irq_type);
328 irq_desc[i].action = NULL;
329 irq_desc[i].depth = 1;
330 irq_desc[i].chip = &i8259A_irq_type;
331 }
332 317
333 setup_irq(2, &irq2); 318 setup_irq(2, &irq2);
334} 319}
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 650a80ca3741..bcaad6696082 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -45,31 +45,6 @@ static inline void unmask_msc_irq(unsigned int irq)
45} 45}
46 46
47/* 47/*
48 * Enables the IRQ on SOC-it
49 */
50static void enable_msc_irq(unsigned int irq)
51{
52 unmask_msc_irq(irq);
53}
54
55/*
56 * Initialize the IRQ on SOC-it
57 */
58static unsigned int startup_msc_irq(unsigned int irq)
59{
60 unmask_msc_irq(irq);
61 return 0;
62}
63
64/*
65 * Disables the IRQ on SOC-it
66 */
67static void disable_msc_irq(unsigned int irq)
68{
69 mask_msc_irq(irq);
70}
71
72/*
73 * Masks and ACKs an IRQ 48 * Masks and ACKs an IRQ
74 */ 49 */
75static void level_mask_and_ack_msc_irq(unsigned int irq) 50static void level_mask_and_ack_msc_irq(unsigned int irq)
@@ -136,25 +111,23 @@ msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
136 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); 111 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
137} 112}
138 113
139#define shutdown_msc_irq disable_msc_irq
140
141struct irq_chip msc_levelirq_type = { 114struct irq_chip msc_levelirq_type = {
142 .typename = "SOC-it-Level", 115 .typename = "SOC-it-Level",
143 .startup = startup_msc_irq,
144 .shutdown = shutdown_msc_irq,
145 .enable = enable_msc_irq,
146 .disable = disable_msc_irq,
147 .ack = level_mask_and_ack_msc_irq, 116 .ack = level_mask_and_ack_msc_irq,
117 .mask = mask_msc_irq,
118 .mask_ack = level_mask_and_ack_msc_irq,
119 .unmask = unmask_msc_irq,
120 .eoi = unmask_msc_irq,
148 .end = end_msc_irq, 121 .end = end_msc_irq,
149}; 122};
150 123
151struct irq_chip msc_edgeirq_type = { 124struct irq_chip msc_edgeirq_type = {
152 .typename = "SOC-it-Edge", 125 .typename = "SOC-it-Edge",
153 .startup =startup_msc_irq,
154 .shutdown = shutdown_msc_irq,
155 .enable = enable_msc_irq,
156 .disable = disable_msc_irq,
157 .ack = edge_mask_and_ack_msc_irq, 126 .ack = edge_mask_and_ack_msc_irq,
127 .mask = mask_msc_irq,
128 .mask_ack = edge_mask_and_ack_msc_irq,
129 .unmask = unmask_msc_irq,
130 .eoi = unmask_msc_irq,
158 .end = end_msc_irq, 131 .end = end_msc_irq,
159}; 132};
160 133
@@ -175,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
175 148
176 switch (imp->im_type) { 149 switch (imp->im_type) {
177 case MSC01_IRQ_EDGE: 150 case MSC01_IRQ_EDGE:
178 irq_desc[base+n].chip = &msc_edgeirq_type; 151 set_irq_chip(base+n, &msc_edgeirq_type);
179 if (cpu_has_veic) 152 if (cpu_has_veic)
180 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 153 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
181 else 154 else
182 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 155 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
183 break; 156 break;
184 case MSC01_IRQ_LEVEL: 157 case MSC01_IRQ_LEVEL:
185 irq_desc[base+n].chip = &msc_levelirq_type; 158 set_irq_chip(base+n, &msc_levelirq_type);
186 if (cpu_has_veic) 159 if (cpu_has_veic)
187 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 160 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
188 else 161 else
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index 37d106202b83..6cfb31cafde2 100644
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -67,39 +67,6 @@ static inline void unmask_mv64340_irq(unsigned int irq)
67} 67}
68 68
69/* 69/*
70 * Enables the IRQ on Marvell Chip
71 */
72static void enable_mv64340_irq(unsigned int irq)
73{
74 unmask_mv64340_irq(irq);
75}
76
77/*
78 * Initialize the IRQ on Marvell Chip
79 */
80static unsigned int startup_mv64340_irq(unsigned int irq)
81{
82 unmask_mv64340_irq(irq);
83 return 0;
84}
85
86/*
87 * Disables the IRQ on Marvell Chip
88 */
89static void disable_mv64340_irq(unsigned int irq)
90{
91 mask_mv64340_irq(irq);
92}
93
94/*
95 * Masks and ACKs an IRQ
96 */
97static void mask_and_ack_mv64340_irq(unsigned int irq)
98{
99 mask_mv64340_irq(irq);
100}
101
102/*
103 * End IRQ processing 70 * End IRQ processing
104 */ 71 */
105static void end_mv64340_irq(unsigned int irq) 72static void end_mv64340_irq(unsigned int irq)
@@ -133,15 +100,12 @@ void ll_mv64340_irq(void)
133 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32); 100 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32);
134} 101}
135 102
136#define shutdown_mv64340_irq disable_mv64340_irq
137
138struct irq_chip mv64340_irq_type = { 103struct irq_chip mv64340_irq_type = {
139 .typename = "MV-64340", 104 .typename = "MV-64340",
140 .startup = startup_mv64340_irq, 105 .ack = mask_mv64340_irq,
141 .shutdown = shutdown_mv64340_irq, 106 .mask = mask_mv64340_irq,
142 .enable = enable_mv64340_irq, 107 .mask_ack = mask_mv64340_irq,
143 .disable = disable_mv64340_irq, 108 .unmask = unmask_mv64340_irq,
144 .ack = mask_and_ack_mv64340_irq,
145 .end = end_mv64340_irq, 109 .end = end_mv64340_irq,
146}; 110};
147 111
@@ -149,13 +113,9 @@ void __init mv64340_irq_init(unsigned int base)
149{ 113{
150 int i; 114 int i;
151 115
152 /* Reset irq handlers pointers to NULL */ 116 for (i = base; i < base + 64; i++)
153 for (i = base; i < base + 64; i++) { 117 set_irq_chip_and_handler(i, &mv64340_irq_type,
154 irq_desc[i].status = IRQ_DISABLED; 118 handle_level_irq);
155 irq_desc[i].action = 0;
156 irq_desc[i].depth = 2;
157 irq_desc[i].chip = &mv64340_irq_type;
158 }
159 119
160 irq_base = base; 120 irq_base = base;
161} 121}
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 6b54c7109e2e..ddcc2a5f8a06 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -29,42 +29,6 @@ static inline void mask_rm7k_irq(unsigned int irq)
29 clear_c0_intcontrol(0x100 << (irq - irq_base)); 29 clear_c0_intcontrol(0x100 << (irq - irq_base));
30} 30}
31 31
32static inline void rm7k_cpu_irq_enable(unsigned int irq)
33{
34 unsigned long flags;
35
36 local_irq_save(flags);
37 unmask_rm7k_irq(irq);
38 local_irq_restore(flags);
39}
40
41static void rm7k_cpu_irq_disable(unsigned int irq)
42{
43 unsigned long flags;
44
45 local_irq_save(flags);
46 mask_rm7k_irq(irq);
47 local_irq_restore(flags);
48}
49
50static unsigned int rm7k_cpu_irq_startup(unsigned int irq)
51{
52 rm7k_cpu_irq_enable(irq);
53
54 return 0;
55}
56
57#define rm7k_cpu_irq_shutdown rm7k_cpu_irq_disable
58
59/*
60 * While we ack the interrupt interrupts are disabled and thus we don't need
61 * to deal with concurrency issues. Same for rm7k_cpu_irq_end.
62 */
63static void rm7k_cpu_irq_ack(unsigned int irq)
64{
65 mask_rm7k_irq(irq);
66}
67
68static void rm7k_cpu_irq_end(unsigned int irq) 32static void rm7k_cpu_irq_end(unsigned int irq)
69{ 33{
70 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 34 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -73,11 +37,10 @@ static void rm7k_cpu_irq_end(unsigned int irq)
73 37
74static struct irq_chip rm7k_irq_controller = { 38static struct irq_chip rm7k_irq_controller = {
75 .typename = "RM7000", 39 .typename = "RM7000",
76 .startup = rm7k_cpu_irq_startup, 40 .ack = mask_rm7k_irq,
77 .shutdown = rm7k_cpu_irq_shutdown, 41 .mask = mask_rm7k_irq,
78 .enable = rm7k_cpu_irq_enable, 42 .mask_ack = mask_rm7k_irq,
79 .disable = rm7k_cpu_irq_disable, 43 .unmask = unmask_rm7k_irq,
80 .ack = rm7k_cpu_irq_ack,
81 .end = rm7k_cpu_irq_end, 44 .end = rm7k_cpu_irq_end,
82}; 45};
83 46
@@ -87,12 +50,9 @@ void __init rm7k_cpu_irq_init(int base)
87 50
88 clear_c0_intcontrol(0x00000f00); /* Mask all */ 51 clear_c0_intcontrol(0x00000f00); /* Mask all */
89 52
90 for (i = base; i < base + 4; i++) { 53 for (i = base; i < base + 4; i++)
91 irq_desc[i].status = IRQ_DISABLED; 54 set_irq_chip_and_handler(i, &rm7k_irq_controller,
92 irq_desc[i].action = NULL; 55 handle_level_irq);
93 irq_desc[i].depth = 1;
94 irq_desc[i].chip = &rm7k_irq_controller;
95 }
96 56
97 irq_base = base; 57 irq_base = base;
98} 58}
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index 62f011ba97a2..ba6440c88abd 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -48,15 +48,6 @@ static void rm9k_cpu_irq_disable(unsigned int irq)
48 local_irq_restore(flags); 48 local_irq_restore(flags);
49} 49}
50 50
51static unsigned int rm9k_cpu_irq_startup(unsigned int irq)
52{
53 rm9k_cpu_irq_enable(irq);
54
55 return 0;
56}
57
58#define rm9k_cpu_irq_shutdown rm9k_cpu_irq_disable
59
60/* 51/*
61 * Performance counter interrupts are global on all processors. 52 * Performance counter interrupts are global on all processors.
62 */ 53 */
@@ -89,16 +80,6 @@ static void rm9k_perfcounter_irq_shutdown(unsigned int irq)
89 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1); 80 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1);
90} 81}
91 82
92
93/*
94 * While we ack the interrupt interrupts are disabled and thus we don't need
95 * to deal with concurrency issues. Same for rm9k_cpu_irq_end.
96 */
97static void rm9k_cpu_irq_ack(unsigned int irq)
98{
99 mask_rm9k_irq(irq);
100}
101
102static void rm9k_cpu_irq_end(unsigned int irq) 83static void rm9k_cpu_irq_end(unsigned int irq)
103{ 84{
104 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 85 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -107,11 +88,10 @@ static void rm9k_cpu_irq_end(unsigned int irq)
107 88
108static struct irq_chip rm9k_irq_controller = { 89static struct irq_chip rm9k_irq_controller = {
109 .typename = "RM9000", 90 .typename = "RM9000",
110 .startup = rm9k_cpu_irq_startup, 91 .ack = mask_rm9k_irq,
111 .shutdown = rm9k_cpu_irq_shutdown, 92 .mask = mask_rm9k_irq,
112 .enable = rm9k_cpu_irq_enable, 93 .mask_ack = mask_rm9k_irq,
113 .disable = rm9k_cpu_irq_disable, 94 .unmask = unmask_rm9k_irq,
114 .ack = rm9k_cpu_irq_ack,
115 .end = rm9k_cpu_irq_end, 95 .end = rm9k_cpu_irq_end,
116}; 96};
117 97
@@ -119,9 +99,10 @@ static struct irq_chip rm9k_perfcounter_irq = {
119 .typename = "RM9000", 99 .typename = "RM9000",
120 .startup = rm9k_perfcounter_irq_startup, 100 .startup = rm9k_perfcounter_irq_startup,
121 .shutdown = rm9k_perfcounter_irq_shutdown, 101 .shutdown = rm9k_perfcounter_irq_shutdown,
122 .enable = rm9k_cpu_irq_enable, 102 .ack = mask_rm9k_irq,
123 .disable = rm9k_cpu_irq_disable, 103 .mask = mask_rm9k_irq,
124 .ack = rm9k_cpu_irq_ack, 104 .mask_ack = mask_rm9k_irq,
105 .unmask = unmask_rm9k_irq,
125 .end = rm9k_cpu_irq_end, 106 .end = rm9k_cpu_irq_end,
126}; 107};
127 108
@@ -135,15 +116,13 @@ void __init rm9k_cpu_irq_init(int base)
135 116
136 clear_c0_intcontrol(0x0000f000); /* Mask all */ 117 clear_c0_intcontrol(0x0000f000); /* Mask all */
137 118
138 for (i = base; i < base + 4; i++) { 119 for (i = base; i < base + 4; i++)
139 irq_desc[i].status = IRQ_DISABLED; 120 set_irq_chip_and_handler(i, &rm9k_irq_controller,
140 irq_desc[i].action = NULL; 121 handle_level_irq);
141 irq_desc[i].depth = 1;
142 irq_desc[i].chip = &rm9k_irq_controller;
143 }
144 122
145 rm9000_perfcount_irq = base + 1; 123 rm9000_perfcount_irq = base + 1;
146 irq_desc[rm9000_perfcount_irq].chip = &rm9k_perfcounter_irq; 124 set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
125 handle_level_irq);
147 126
148 irq_base = base; 127 irq_base = base;
149} 128}
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index dd24434392b6..b339798b3172 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -26,6 +26,48 @@
26#include <asm/system.h> 26#include <asm/system.h>
27#include <asm/uaccess.h> 27#include <asm/uaccess.h>
28 28
29static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
30
31int __devinit allocate_irqno(void)
32{
33 int irq;
34
35again:
36 irq = find_first_zero_bit(irq_map, NR_IRQS);
37
38 if (irq >= NR_IRQS)
39 return -ENOSPC;
40
41 if (test_and_set_bit(irq, irq_map))
42 goto again;
43
44 return irq;
45}
46
47EXPORT_SYMBOL_GPL(allocate_irqno);
48
49/*
50 * Allocate the 16 legacy interrupts for i8259 devices. This happens early
51 * in the kernel initialization so treating allocation failure as BUG() is
52 * ok.
53 */
54void __init alloc_legacy_irqno(void)
55{
56 int i;
57
58 for (i = 0; i <= 16; i++)
59 BUG_ON(test_and_set_bit(i, irq_map));
60}
61
62void __devinit free_irqno(unsigned int irq)
63{
64 smp_mb__before_clear_bit();
65 clear_bit(irq, irq_map);
66 smp_mb__after_clear_bit();
67}
68
69EXPORT_SYMBOL_GPL(free_irqno);
70
29/* 71/*
30 * 'what should we do if we get a hw irq event on an illegal vector'. 72 * 'what should we do if we get a hw irq event on an illegal vector'.
31 * each architecture has to answer this themselves. 73 * each architecture has to answer this themselves.
@@ -46,25 +88,6 @@ atomic_t irq_err_count;
46unsigned long irq_hwmask[NR_IRQS]; 88unsigned long irq_hwmask[NR_IRQS];
47#endif /* CONFIG_MIPS_MT_SMTC */ 89#endif /* CONFIG_MIPS_MT_SMTC */
48 90
49#undef do_IRQ
50
51/*
52 * do_IRQ handles all normal device IRQ's (the special
53 * SMP cross-CPU interrupts have their own specific
54 * handlers).
55 */
56asmlinkage unsigned int do_IRQ(unsigned int irq)
57{
58 irq_enter();
59
60 __DO_IRQ_SMTC_HOOK();
61 __do_IRQ(irq);
62
63 irq_exit();
64
65 return 1;
66}
67
68/* 91/*
69 * Generic, controller-independent functions: 92 * Generic, controller-independent functions:
70 */ 93 */
@@ -130,19 +153,6 @@ __setup("nokgdb", nokgdb);
130 153
131void __init init_IRQ(void) 154void __init init_IRQ(void)
132{ 155{
133 int i;
134
135 for (i = 0; i < NR_IRQS; i++) {
136 irq_desc[i].status = IRQ_DISABLED;
137 irq_desc[i].action = NULL;
138 irq_desc[i].depth = 1;
139 irq_desc[i].chip = &no_irq_chip;
140 spin_lock_init(&irq_desc[i].lock);
141#ifdef CONFIG_MIPS_MT_SMTC
142 irq_hwmask[i] = 0;
143#endif /* CONFIG_MIPS_MT_SMTC */
144 }
145
146 arch_init_irq(); 156 arch_init_irq();
147 157
148#ifdef CONFIG_KGDB 158#ifdef CONFIG_KGDB
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 9bb21c7f2149..be5ac23d3812 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -50,44 +50,6 @@ static inline void mask_mips_irq(unsigned int irq)
50 irq_disable_hazard(); 50 irq_disable_hazard();
51} 51}
52 52
53static inline void mips_cpu_irq_enable(unsigned int irq)
54{
55 unsigned long flags;
56
57 local_irq_save(flags);
58 unmask_mips_irq(irq);
59 back_to_back_c0_hazard();
60 local_irq_restore(flags);
61}
62
63static void mips_cpu_irq_disable(unsigned int irq)
64{
65 unsigned long flags;
66
67 local_irq_save(flags);
68 mask_mips_irq(irq);
69 back_to_back_c0_hazard();
70 local_irq_restore(flags);
71}
72
73static unsigned int mips_cpu_irq_startup(unsigned int irq)
74{
75 mips_cpu_irq_enable(irq);
76
77 return 0;
78}
79
80#define mips_cpu_irq_shutdown mips_cpu_irq_disable
81
82/*
83 * While we ack the interrupt interrupts are disabled and thus we don't need
84 * to deal with concurrency issues. Same for mips_cpu_irq_end.
85 */
86static void mips_cpu_irq_ack(unsigned int irq)
87{
88 mask_mips_irq(irq);
89}
90
91static void mips_cpu_irq_end(unsigned int irq) 53static void mips_cpu_irq_end(unsigned int irq)
92{ 54{
93 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 55 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -96,11 +58,11 @@ static void mips_cpu_irq_end(unsigned int irq)
96 58
97static struct irq_chip mips_cpu_irq_controller = { 59static struct irq_chip mips_cpu_irq_controller = {
98 .typename = "MIPS", 60 .typename = "MIPS",
99 .startup = mips_cpu_irq_startup, 61 .ack = mask_mips_irq,
100 .shutdown = mips_cpu_irq_shutdown, 62 .mask = mask_mips_irq,
101 .enable = mips_cpu_irq_enable, 63 .mask_ack = mask_mips_irq,
102 .disable = mips_cpu_irq_disable, 64 .unmask = unmask_mips_irq,
103 .ack = mips_cpu_irq_ack, 65 .eoi = unmask_mips_irq,
104 .end = mips_cpu_irq_end, 66 .end = mips_cpu_irq_end,
105}; 67};
106 68
@@ -110,8 +72,6 @@ static struct irq_chip mips_cpu_irq_controller = {
110 72
111#define unmask_mips_mt_irq unmask_mips_irq 73#define unmask_mips_mt_irq unmask_mips_irq
112#define mask_mips_mt_irq mask_mips_irq 74#define mask_mips_mt_irq mask_mips_irq
113#define mips_mt_cpu_irq_enable mips_cpu_irq_enable
114#define mips_mt_cpu_irq_disable mips_cpu_irq_disable
115 75
116static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) 76static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
117{ 77{
@@ -119,13 +79,11 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
119 79
120 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); 80 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
121 evpe(vpflags); 81 evpe(vpflags);
122 mips_mt_cpu_irq_enable(irq); 82 unmask_mips_mt_irq(irq);
123 83
124 return 0; 84 return 0;
125} 85}
126 86
127#define mips_mt_cpu_irq_shutdown mips_mt_cpu_irq_disable
128
129/* 87/*
130 * While we ack the interrupt interrupts are disabled and thus we don't need 88 * While we ack the interrupt interrupts are disabled and thus we don't need
131 * to deal with concurrency issues. Same for mips_cpu_irq_end. 89 * to deal with concurrency issues. Same for mips_cpu_irq_end.
@@ -143,10 +101,11 @@ static void mips_mt_cpu_irq_ack(unsigned int irq)
143static struct irq_chip mips_mt_cpu_irq_controller = { 101static struct irq_chip mips_mt_cpu_irq_controller = {
144 .typename = "MIPS", 102 .typename = "MIPS",
145 .startup = mips_mt_cpu_irq_startup, 103 .startup = mips_mt_cpu_irq_startup,
146 .shutdown = mips_mt_cpu_irq_shutdown,
147 .enable = mips_mt_cpu_irq_enable,
148 .disable = mips_mt_cpu_irq_disable,
149 .ack = mips_mt_cpu_irq_ack, 104 .ack = mips_mt_cpu_irq_ack,
105 .mask = mask_mips_mt_irq,
106 .mask_ack = mips_mt_cpu_irq_ack,
107 .unmask = unmask_mips_mt_irq,
108 .eoi = unmask_mips_mt_irq,
150 .end = mips_mt_cpu_irq_end, 109 .end = mips_mt_cpu_irq_end,
151}; 110};
152 111
@@ -163,19 +122,12 @@ void __init mips_cpu_irq_init(int irq_base)
163 * leave them uninitialized for other processors. 122 * leave them uninitialized for other processors.
164 */ 123 */
165 if (cpu_has_mipsmt) 124 if (cpu_has_mipsmt)
166 for (i = irq_base; i < irq_base + 2; i++) { 125 for (i = irq_base; i < irq_base + 2; i++)
167 irq_desc[i].status = IRQ_DISABLED; 126 set_irq_chip(i, &mips_mt_cpu_irq_controller);
168 irq_desc[i].action = NULL; 127
169 irq_desc[i].depth = 1; 128 for (i = irq_base + 2; i < irq_base + 8; i++)
170 irq_desc[i].chip = &mips_mt_cpu_irq_controller; 129 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
171 } 130 handle_level_irq);
172
173 for (i = irq_base + 2; i < irq_base + 8; i++) {
174 irq_desc[i].status = IRQ_DISABLED;
175 irq_desc[i].action = NULL;
176 irq_desc[i].depth = 1;
177 irq_desc[i].chip = &mips_cpu_irq_controller;
178 }
179 131
180 mips_cpu_irq_base = irq_base; 132 mips_cpu_irq_base = irq_base;
181} 133}
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 53f4171fc188..7a3ebbeba1f3 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -1055,7 +1055,9 @@ asmlinkage long sys32_newuname(struct new_utsname __user * name)
1055asmlinkage int sys32_personality(unsigned long personality) 1055asmlinkage int sys32_personality(unsigned long personality)
1056{ 1056{
1057 int ret; 1057 int ret;
1058 if (current->personality == PER_LINUX32 && personality == PER_LINUX) 1058 personality &= 0xffffffff;
1059 if (personality(current->personality) == PER_LINUX32 &&
1060 personality == PER_LINUX)
1059 personality = PER_LINUX32; 1061 personality = PER_LINUX32;
1060 ret = sys_personality(personality); 1062 ret = sys_personality(personality);
1061 if (ret == PER_LINUX32) 1063 if (ret == PER_LINUX32)
diff --git a/arch/mips/kernel/machine_kexec.c b/arch/mips/kernel/machine_kexec.c
new file mode 100644
index 000000000000..e0ad754c7edd
--- /dev/null
+++ b/arch/mips/kernel/machine_kexec.c
@@ -0,0 +1,85 @@
1/*
2 * machine_kexec.c for kexec
3 * Created by <nschichan@corp.free.fr> on Thu Oct 12 15:15:06 2006
4 *
5 * This source code is licensed under the GNU General Public License,
6 * Version 2. See the file COPYING for more details.
7 */
8
9#include <linux/kexec.h>
10#include <linux/mm.h>
11#include <linux/delay.h>
12
13#include <asm/cacheflush.h>
14#include <asm/page.h>
15
16const extern unsigned char relocate_new_kernel[];
17const extern unsigned int relocate_new_kernel_size;
18
19extern unsigned long kexec_start_address;
20extern unsigned long kexec_indirection_page;
21
22int
23machine_kexec_prepare(struct kimage *kimage)
24{
25 return 0;
26}
27
28void
29machine_kexec_cleanup(struct kimage *kimage)
30{
31}
32
33void
34machine_shutdown(void)
35{
36}
37
38void
39machine_crash_shutdown(struct pt_regs *regs)
40{
41}
42
43void
44machine_kexec(struct kimage *image)
45{
46 unsigned long reboot_code_buffer;
47 unsigned long entry;
48 unsigned long *ptr;
49
50 reboot_code_buffer =
51 (unsigned long)page_address(image->control_code_page);
52
53 kexec_start_address = image->start;
54 kexec_indirection_page = phys_to_virt(image->head & PAGE_MASK);
55
56 memcpy((void*)reboot_code_buffer, relocate_new_kernel,
57 relocate_new_kernel_size);
58
59 /*
60 * The generic kexec code builds a page list with physical
61 * addresses. they are directly accessible through KSEG0 (or
62 * CKSEG0 or XPHYS if on 64bit system), hence the
63 * pys_to_virt() call.
64 */
65 for (ptr = &image->head; (entry = *ptr) && !(entry &IND_DONE);
66 ptr = (entry & IND_INDIRECTION) ?
67 phys_to_virt(entry & PAGE_MASK) : ptr + 1) {
68 if (*ptr & IND_SOURCE || *ptr & IND_INDIRECTION ||
69 *ptr & IND_DESTINATION)
70 *ptr = phys_to_virt(*ptr);
71 }
72
73 /*
74 * we do not want to be bothered.
75 */
76 local_irq_disable();
77
78 flush_icache_range(reboot_code_buffer,
79 reboot_code_buffer + KEXEC_CONTROL_CODE_SIZE);
80
81 printk("Will call new kernel at %08x\n", image->start);
82 printk("Bye ...\n");
83 flush_cache_all();
84 ((void (*)(void))reboot_code_buffer)();
85}
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index d7bf0215bc1d..cb0801437b66 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -29,6 +29,7 @@
29#include <linux/kernel.h> 29#include <linux/kernel.h>
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/spinlock.h> 31#include <linux/spinlock.h>
32#include <asm/pgtable.h> /* MODULE_START */
32 33
33struct mips_hi16 { 34struct mips_hi16 {
34 struct mips_hi16 *next; 35 struct mips_hi16 *next;
@@ -43,9 +44,23 @@ static DEFINE_SPINLOCK(dbe_lock);
43 44
44void *module_alloc(unsigned long size) 45void *module_alloc(unsigned long size)
45{ 46{
47#ifdef MODULE_START
48 struct vm_struct *area;
49
50 size = PAGE_ALIGN(size);
51 if (!size)
52 return NULL;
53
54 area = __get_vm_area(size, VM_ALLOC, MODULE_START, MODULE_END);
55 if (!area)
56 return NULL;
57
58 return __vmalloc_area(area, GFP_KERNEL, PAGE_KERNEL);
59#else
46 if (size == 0) 60 if (size == 0)
47 return NULL; 61 return NULL;
48 return vmalloc(size); 62 return vmalloc(size);
63#endif
49} 64}
50 65
51/* Free memory returned from module_alloc */ 66/* Free memory returned from module_alloc */
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 9f307eb1a31e..ec8209f3a0c6 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -358,10 +358,8 @@ static int __init frame_info_init(void)
358 unsigned long size = 0; 358 unsigned long size = 0;
359#ifdef CONFIG_KALLSYMS 359#ifdef CONFIG_KALLSYMS
360 unsigned long ofs; 360 unsigned long ofs;
361 char *modname;
362 char namebuf[KSYM_NAME_LEN + 1];
363 361
364 kallsyms_lookup((unsigned long)schedule, &size, &ofs, &modname, namebuf); 362 kallsyms_lookup_size_offset((unsigned long)schedule, &size, &ofs);
365#endif 363#endif
366 schedule_mfi.func = schedule; 364 schedule_mfi.func = schedule;
367 schedule_mfi.func_size = size; 365 schedule_mfi.func_size = size;
@@ -403,8 +401,6 @@ unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
403{ 401{
404 unsigned long stack_page; 402 unsigned long stack_page;
405 struct mips_frame_info info; 403 struct mips_frame_info info;
406 char *modname;
407 char namebuf[KSYM_NAME_LEN + 1];
408 unsigned long size, ofs; 404 unsigned long size, ofs;
409 int leaf; 405 int leaf;
410 extern void ret_from_irq(void); 406 extern void ret_from_irq(void);
@@ -433,7 +429,7 @@ unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
433 } 429 }
434 return 0; 430 return 0;
435 } 431 }
436 if (!kallsyms_lookup(pc, &size, &ofs, &modname, namebuf)) 432 if (!kallsyms_lookup_size_offset(pc, &size, &ofs))
437 return 0; 433 return 0;
438 /* 434 /*
439 * Return ra if an exception occured at the first instruction 435 * Return ra if an exception occured at the first instruction
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index d5c8b82fed72..cc566cf12246 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -85,7 +85,12 @@
85 move $28, a2 85 move $28, a2
86 cpu_restore_nonscratch a1 86 cpu_restore_nonscratch a1
87 87
88#if (_THREAD_SIZE - 32) < 0x10000
88 PTR_ADDIU t0, $28, _THREAD_SIZE - 32 89 PTR_ADDIU t0, $28, _THREAD_SIZE - 32
90#else
91 PTR_LI t0, _THREAD_SIZE - 32
92 PTR_ADDU t0, $28
93#endif
89 set_saved_sp t0, t1, t2 94 set_saved_sp t0, t1, t2
90#ifdef CONFIG_MIPS_MT_SMTC 95#ifdef CONFIG_MIPS_MT_SMTC
91 /* Read-modify-writes of Status must be atomic on a VPE */ 96 /* Read-modify-writes of Status must be atomic on a VPE */
diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S
new file mode 100644
index 000000000000..a3f0d00c1334
--- /dev/null
+++ b/arch/mips/kernel/relocate_kernel.S
@@ -0,0 +1,80 @@
1/*
2 * relocate_kernel.S for kexec
3 * Created by <nschichan@corp.free.fr> on Thu Oct 12 17:49:57 2006
4 *
5 * This source code is licensed under the GNU General Public License,
6 * Version 2. See the file COPYING for more details.
7 */
8
9#include <asm/asm.h>
10#include <asm/asmmacro.h>
11#include <asm/regdef.h>
12#include <asm/page.h>
13#include <asm/mipsregs.h>
14#include <asm/stackframe.h>
15#include <asm/addrspace.h>
16
17 .globl relocate_new_kernel
18relocate_new_kernel:
19
20 PTR_L s0, kexec_indirection_page
21 PTR_L s1, kexec_start_address
22
23process_entry:
24 PTR_L s2, (s0)
25 PTR_ADD s0, s0, SZREG
26
27 /* destination page */
28 and s3, s2, 0x1
29 beq s3, zero, 1f
30 and s4, s2, ~0x1 /* store destination addr in s4 */
31 move a0, s4
32 b process_entry
33
341:
35 /* indirection page, update s0 */
36 and s3, s2, 0x2
37 beq s3, zero, 1f
38 and s0, s2, ~0x2
39 b process_entry
40
411:
42 /* done page */
43 and s3, s2, 0x4
44 beq s3, zero, 1f
45 b done
461:
47 /* source page */
48 and s3, s2, 0x8
49 beq s3, zero, process_entry
50 and s2, s2, ~0x8
51 li s6, (1 << PAGE_SHIFT) / SZREG
52
53copy_word:
54 /* copy page word by word */
55 REG_L s5, (s2)
56 REG_S s5, (s4)
57 INT_ADD s4, s4, SZREG
58 INT_ADD s2, s2, SZREG
59 INT_SUB s6, s6, 1
60 beq s6, zero, process_entry
61 b copy_word
62 b process_entry
63
64done:
65 /* jump to kexec_start_address */
66 j s1
67
68 .globl kexec_start_address
69kexec_start_address:
70 .long 0x0
71
72 .globl kexec_indirection_page
73kexec_indirection_page:
74 .long 0x0
75
76relocate_new_kernel_end:
77
78 .globl relocate_new_kernel_size
79relocate_new_kernel_size:
80 .long relocate_new_kernel_end - relocate_new_kernel
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 61362e6fa9ec..7c0b3936ba44 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -652,7 +652,10 @@ einval: li v0, -EINVAL
652 sys sys_vmsplice 4 652 sys sys_vmsplice 4
653 sys sys_move_pages 6 653 sys sys_move_pages 6
654 sys sys_set_robust_list 2 654 sys sys_set_robust_list 2
655 sys sys_get_robust_list 3 655 sys sys_get_robust_list 3 /* 4310 */
656 sys sys_kexec_load 4
657 sys sys_getcpu 3
658 sys sys_epoll_pwait 6
656 .endm 659 .endm
657 660
658 /* We pre-compute the number of _instruction_ bytes needed to 661 /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 6c7b5ed0ea6e..e569b846e9a3 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -468,3 +468,6 @@ sys_call_table:
468 PTR sys_move_pages 468 PTR sys_move_pages
469 PTR sys_set_robust_list 469 PTR sys_set_robust_list
470 PTR sys_get_robust_list 470 PTR sys_get_robust_list
471 PTR sys_kexec_load /* 5270 */
472 PTR sys_getcpu
473 PTR sys_epoll_pwait
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 6d9f18727ac5..5b18f265d75b 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -280,7 +280,7 @@ EXPORT(sysn32_call_table)
280 PTR sys_sync 280 PTR sys_sync
281 PTR sys_acct 281 PTR sys_acct
282 PTR sys32_settimeofday 282 PTR sys32_settimeofday
283 PTR sys_mount /* 6160 */ 283 PTR compat_sys_mount /* 6160 */
284 PTR sys_umount 284 PTR sys_umount
285 PTR sys_swapon 285 PTR sys_swapon
286 PTR sys_swapoff 286 PTR sys_swapoff
@@ -394,3 +394,6 @@ EXPORT(sysn32_call_table)
394 PTR sys_move_pages 394 PTR sys_move_pages
395 PTR compat_sys_set_robust_list 395 PTR compat_sys_set_robust_list
396 PTR compat_sys_get_robust_list 396 PTR compat_sys_get_robust_list
397 PTR compat_sys_kexec_load
398 PTR sys_getcpu
399 PTR sys_epoll_pwait
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 2e6d0673163e..e91379c1be1d 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -226,7 +226,7 @@ sys_call_table:
226 PTR sys_ni_syscall /* was sys_stat */ 226 PTR sys_ni_syscall /* was sys_stat */
227 PTR sys_lseek 227 PTR sys_lseek
228 PTR sys_getpid /* 4020 */ 228 PTR sys_getpid /* 4020 */
229 PTR sys_mount 229 PTR compat_sys_mount
230 PTR sys_oldumount 230 PTR sys_oldumount
231 PTR sys_setuid 231 PTR sys_setuid
232 PTR sys_getuid 232 PTR sys_getuid
@@ -516,4 +516,7 @@ sys_call_table:
516 PTR compat_sys_move_pages 516 PTR compat_sys_move_pages
517 PTR compat_sys_set_robust_list 517 PTR compat_sys_set_robust_list
518 PTR compat_sys_get_robust_list /* 4310 */ 518 PTR compat_sys_get_robust_list /* 4310 */
519 PTR compat_sys_kexec_load
520 PTR sys_getcpu
521 PTR sys_epoll_pwait
519 .size sys_call_table,.-sys_call_table 522 .size sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index fdbb508661c5..89440a0d8528 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -145,13 +145,12 @@ static int __init rd_start_early(char *p)
145 unsigned long start = memparse(p, &p); 145 unsigned long start = memparse(p, &p);
146 146
147#ifdef CONFIG_64BIT 147#ifdef CONFIG_64BIT
148 /* HACK: Guess if the sign extension was forgotten */ 148 /* Guess if the sign extension was forgotten by bootloader */
149 if (start > 0x0000000080000000 && start < 0x00000000ffffffff) 149 if (start < XKPHYS)
150 start |= 0xffffffff00000000UL; 150 start = (int)start;
151#endif 151#endif
152 initrd_start = start; 152 initrd_start = start;
153 initrd_end += start; 153 initrd_end += start;
154
155 return 0; 154 return 0;
156} 155}
157early_param("rd_start", rd_start_early); 156early_param("rd_start", rd_start_early);
@@ -159,41 +158,64 @@ early_param("rd_start", rd_start_early);
159static int __init rd_size_early(char *p) 158static int __init rd_size_early(char *p)
160{ 159{
161 initrd_end += memparse(p, &p); 160 initrd_end += memparse(p, &p);
162
163 return 0; 161 return 0;
164} 162}
165early_param("rd_size", rd_size_early); 163early_param("rd_size", rd_size_early);
166 164
165/* it returns the next free pfn after initrd */
167static unsigned long __init init_initrd(void) 166static unsigned long __init init_initrd(void)
168{ 167{
169 unsigned long tmp, end, size; 168 unsigned long end;
170 u32 *initrd_header; 169 u32 *initrd_header;
171 170
172 ROOT_DEV = Root_RAM0;
173
174 /* 171 /*
175 * Board specific code or command line parser should have 172 * Board specific code or command line parser should have
176 * already set up initrd_start and initrd_end. In these cases 173 * already set up initrd_start and initrd_end. In these cases
177 * perfom sanity checks and use them if all looks good. 174 * perfom sanity checks and use them if all looks good.
178 */ 175 */
179 size = initrd_end - initrd_start; 176 if (initrd_start && initrd_end > initrd_start)
180 if (initrd_end == 0 || size == 0) { 177 goto sanitize;
181 initrd_start = 0; 178
182 initrd_end = 0; 179 /*
183 } else 180 * See if initrd has been added to the kernel image by
184 return initrd_end; 181 * arch/mips/boot/addinitrd.c. In that case a header is
185 182 * prepended to initrd and is made up by 8 bytes. The fisrt
186 end = (unsigned long)&_end; 183 * word is a magic number and the second one is the size of
187 tmp = PAGE_ALIGN(end) - sizeof(u32) * 2; 184 * initrd. Initrd start must be page aligned in any cases.
188 if (tmp < end) 185 */
189 tmp += PAGE_SIZE; 186 initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8;
190 187 if (initrd_header[0] != 0x494E5244)
191 initrd_header = (u32 *)tmp; 188 goto disable;
192 if (initrd_header[0] == 0x494E5244) { 189 initrd_start = (unsigned long)(initrd_header + 2);
193 initrd_start = (unsigned long)&initrd_header[2]; 190 initrd_end = initrd_start + initrd_header[1];
194 initrd_end = initrd_start + initrd_header[1]; 191
192sanitize:
193 if (initrd_start & ~PAGE_MASK) {
194 printk(KERN_ERR "initrd start must be page aligned\n");
195 goto disable;
195 } 196 }
196 return initrd_end; 197 if (initrd_start < PAGE_OFFSET) {
198 printk(KERN_ERR "initrd start < PAGE_OFFSET\n");
199 goto disable;
200 }
201
202 /*
203 * Sanitize initrd addresses. For example firmware
204 * can't guess if they need to pass them through
205 * 64-bits values if the kernel has been built in pure
206 * 32-bit. We need also to switch from KSEG0 to XKPHYS
207 * addresses now, so the code can now safely use __pa().
208 */
209 end = __pa(initrd_end);
210 initrd_end = (unsigned long)__va(end);
211 initrd_start = (unsigned long)__va(__pa(initrd_start));
212
213 ROOT_DEV = Root_RAM0;
214 return PFN_UP(end);
215disable:
216 initrd_start = 0;
217 initrd_end = 0;
218 return 0;
197} 219}
198 220
199static void __init finalize_initrd(void) 221static void __init finalize_initrd(void)
@@ -204,12 +226,12 @@ static void __init finalize_initrd(void)
204 printk(KERN_INFO "Initrd not found or empty"); 226 printk(KERN_INFO "Initrd not found or empty");
205 goto disable; 227 goto disable;
206 } 228 }
207 if (CPHYSADDR(initrd_end) > PFN_PHYS(max_low_pfn)) { 229 if (__pa(initrd_end) > PFN_PHYS(max_low_pfn)) {
208 printk("Initrd extends beyond end of memory"); 230 printk("Initrd extends beyond end of memory");
209 goto disable; 231 goto disable;
210 } 232 }
211 233
212 reserve_bootmem(CPHYSADDR(initrd_start), size); 234 reserve_bootmem(__pa(initrd_start), size);
213 initrd_below_start_ok = 1; 235 initrd_below_start_ok = 1;
214 236
215 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n", 237 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
@@ -223,7 +245,11 @@ disable:
223 245
224#else /* !CONFIG_BLK_DEV_INITRD */ 246#else /* !CONFIG_BLK_DEV_INITRD */
225 247
226#define init_initrd() 0 248static unsigned long __init init_initrd(void)
249{
250 return 0;
251}
252
227#define finalize_initrd() do {} while (0) 253#define finalize_initrd() do {} while (0)
228 254
229#endif 255#endif
@@ -255,8 +281,7 @@ static void __init bootmem_init(void)
255 * not selected. Once that done we can determine the low bound 281 * not selected. Once that done we can determine the low bound
256 * of usable memory. 282 * of usable memory.
257 */ 283 */
258 reserved_end = init_initrd(); 284 reserved_end = max(init_initrd(), PFN_UP(__pa_symbol(&_end)));
259 reserved_end = PFN_UP(CPHYSADDR(max(reserved_end, (unsigned long)&_end)));
260 285
261 /* 286 /*
262 * Find the highest page frame number we have available. 287 * Find the highest page frame number we have available.
@@ -428,10 +453,10 @@ static void __init resource_init(void)
428 if (UNCAC_BASE != IO_BASE) 453 if (UNCAC_BASE != IO_BASE)
429 return; 454 return;
430 455
431 code_resource.start = virt_to_phys(&_text); 456 code_resource.start = __pa_symbol(&_text);
432 code_resource.end = virt_to_phys(&_etext) - 1; 457 code_resource.end = __pa_symbol(&_etext) - 1;
433 data_resource.start = virt_to_phys(&_etext); 458 data_resource.start = __pa_symbol(&_etext);
434 data_resource.end = virt_to_phys(&_edata) - 1; 459 data_resource.end = __pa_symbol(&_edata) - 1;
435 460
436 /* 461 /*
437 * Request address space for all standard RAM. 462 * Request address space for all standard RAM.
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index 477c5334ec1b..a67c18555ed3 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -17,7 +17,6 @@
17 */ 17 */
18#include <linux/cache.h> 18#include <linux/cache.h>
19#include <linux/sched.h> 19#include <linux/sched.h>
20#include <linux/sched.h>
21#include <linux/mm.h> 20#include <linux/mm.h>
22#include <linux/smp.h> 21#include <linux/smp.h>
23#include <linux/smp_lock.h> 22#include <linux/smp_lock.h>
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 3b5f3b632622..1ee689c0e0c9 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -140,15 +140,90 @@ static struct irqaction irq_call = {
140 .name = "IPI_call" 140 .name = "IPI_call"
141}; 141};
142 142
143static void __init smp_copy_vpe_config(void)
144{
145 write_vpe_c0_status(
146 (read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
147
148 /* set config to be the same as vpe0, particularly kseg0 coherency alg */
149 write_vpe_c0_config( read_c0_config());
150
151 /* make sure there are no software interrupts pending */
152 write_vpe_c0_cause(0);
153
154 /* Propagate Config7 */
155 write_vpe_c0_config7(read_c0_config7());
156
157 write_vpe_c0_count(read_c0_count());
158}
159
160static unsigned int __init smp_vpe_init(unsigned int tc, unsigned int mvpconf0,
161 unsigned int ncpu)
162{
163 if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
164 return ncpu;
165
166 /* Deactivate all but VPE 0 */
167 if (tc != 0) {
168 unsigned long tmp = read_vpe_c0_vpeconf0();
169
170 tmp &= ~VPECONF0_VPA;
171
172 /* master VPE */
173 tmp |= VPECONF0_MVP;
174 write_vpe_c0_vpeconf0(tmp);
175
176 /* Record this as available CPU */
177 cpu_set(tc, phys_cpu_present_map);
178 __cpu_number_map[tc] = ++ncpu;
179 __cpu_logical_map[ncpu] = tc;
180 }
181
182 /* Disable multi-threading with TC's */
183 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
184
185 if (tc != 0)
186 smp_copy_vpe_config();
187
188 return ncpu;
189}
190
191static void __init smp_tc_init(unsigned int tc, unsigned int mvpconf0)
192{
193 unsigned long tmp;
194
195 if (!tc)
196 return;
197
198 /* bind a TC to each VPE, May as well put all excess TC's
199 on the last VPE */
200 if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
201 write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
202 else {
203 write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);
204
205 /* and set XTC */
206 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
207 }
208
209 tmp = read_tc_c0_tcstatus();
210
211 /* mark not allocated and not dynamically allocatable */
212 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
213 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
214 write_tc_c0_tcstatus(tmp);
215
216 write_tc_c0_tchalt(TCHALT_H);
217}
218
143/* 219/*
144 * Common setup before any secondaries are started 220 * Common setup before any secondaries are started
145 * Make sure all CPU's are in a sensible state before we boot any of the 221 * Make sure all CPU's are in a sensible state before we boot any of the
146 * secondarys 222 * secondarys
147 */ 223 */
148void plat_smp_setup(void) 224void __init plat_smp_setup(void)
149{ 225{
150 unsigned long val; 226 unsigned int mvpconf0, ntc, tc, ncpu = 0;
151 int i, num;
152 227
153#ifdef CONFIG_MIPS_MT_FPAFF 228#ifdef CONFIG_MIPS_MT_FPAFF
154 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 229 /* If we have an FPU, enroll ourselves in the FPU-full mask */
@@ -167,75 +242,16 @@ void plat_smp_setup(void)
167 /* Put MVPE's into 'configuration state' */ 242 /* Put MVPE's into 'configuration state' */
168 set_c0_mvpcontrol(MVPCONTROL_VPC); 243 set_c0_mvpcontrol(MVPCONTROL_VPC);
169 244
170 val = read_c0_mvpconf0(); 245 mvpconf0 = read_c0_mvpconf0();
246 ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
171 247
172 /* we'll always have more TC's than VPE's, so loop setting everything 248 /* we'll always have more TC's than VPE's, so loop setting everything
173 to a sensible state */ 249 to a sensible state */
174 for (i = 0, num = 0; i <= ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT); i++) { 250 for (tc = 0; tc <= ntc; tc++) {
175 settc(i); 251 settc(tc);
176
177 /* VPE's */
178 if (i <= ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) {
179
180 /* deactivate all but vpe0 */
181 if (i != 0) {
182 unsigned long tmp = read_vpe_c0_vpeconf0();
183
184 tmp &= ~VPECONF0_VPA;
185
186 /* master VPE */
187 tmp |= VPECONF0_MVP;
188 write_vpe_c0_vpeconf0(tmp);
189
190 /* Record this as available CPU */
191 cpu_set(i, phys_cpu_present_map);
192 __cpu_number_map[i] = ++num;
193 __cpu_logical_map[num] = i;
194 }
195
196 /* disable multi-threading with TC's */
197 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
198
199 if (i != 0) {
200 write_vpe_c0_status((read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
201 252
202 /* set config to be the same as vpe0, particularly kseg0 coherency alg */ 253 smp_tc_init(tc, mvpconf0);
203 write_vpe_c0_config( read_c0_config()); 254 ncpu = smp_vpe_init(tc, mvpconf0, ncpu);
204
205 /* make sure there are no software interrupts pending */
206 write_vpe_c0_cause(0);
207
208 /* Propagate Config7 */
209 write_vpe_c0_config7(read_c0_config7());
210 }
211
212 }
213
214 /* TC's */
215
216 if (i != 0) {
217 unsigned long tmp;
218
219 /* bind a TC to each VPE, May as well put all excess TC's
220 on the last VPE */
221 if ( i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1) )
222 write_tc_c0_tcbind(read_tc_c0_tcbind() | ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) );
223 else {
224 write_tc_c0_tcbind( read_tc_c0_tcbind() | i);
225
226 /* and set XTC */
227 write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | (i << VPECONF0_XTC_SHIFT));
228 }
229
230 tmp = read_tc_c0_tcstatus();
231
232 /* mark not allocated and not dynamically allocatable */
233 tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
234 tmp |= TCSTATUS_IXMT; /* interrupt exempt */
235 write_tc_c0_tcstatus(tmp);
236
237 write_tc_c0_tchalt(TCHALT_H);
238 }
239 } 255 }
240 256
241 /* Release config state */ 257 /* Release config state */
@@ -243,7 +259,7 @@ void plat_smp_setup(void)
243 259
244 /* We'll wait until starting the secondaries before starting MVPE */ 260 /* We'll wait until starting the secondaries before starting MVPE */
245 261
246 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); 262 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
247} 263}
248 264
249void __init plat_prepare_cpus(unsigned int max_cpus) 265void __init plat_prepare_cpus(unsigned int max_cpus)
@@ -262,7 +278,9 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
262 278
263 /* need to mark IPI's as IRQ_PER_CPU */ 279 /* need to mark IPI's as IRQ_PER_CPU */
264 irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU; 280 irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU;
281 set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
265 irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU; 282 irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU;
283 set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
266} 284}
267 285
268/* 286/*
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index db80957ada89..49db516789e0 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -463,28 +463,5 @@ void flush_tlb_one(unsigned long vaddr)
463 smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); 463 smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
464} 464}
465 465
466static DEFINE_PER_CPU(struct cpu, cpu_devices);
467
468static int __init topology_init(void)
469{
470 int i, ret;
471
472#ifdef CONFIG_NUMA
473 for_each_online_node(i)
474 register_one_node(i);
475#endif /* CONFIG_NUMA */
476
477 for_each_present_cpu(i) {
478 ret = register_cpu(&per_cpu(cpu_devices, i), i);
479 if (ret)
480 printk(KERN_WARNING "topology_init: register_cpu %d "
481 "failed (%d)\n", i, ret);
482 }
483
484 return 0;
485}
486
487subsys_initcall(topology_init);
488
489EXPORT_SYMBOL(flush_tlb_page); 466EXPORT_SYMBOL(flush_tlb_page);
490EXPORT_SYMBOL(flush_tlb_one); 467EXPORT_SYMBOL(flush_tlb_one);
diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S
index 1cb9441f1474..921207c4a83c 100644
--- a/arch/mips/kernel/smtc-asm.S
+++ b/arch/mips/kernel/smtc-asm.S
@@ -101,7 +101,9 @@ FEXPORT(__smtc_ipi_vector)
101 lw t0,PT_PADSLOT5(sp) 101 lw t0,PT_PADSLOT5(sp)
102 /* Argument from sender passed in stack pad slot 4 */ 102 /* Argument from sender passed in stack pad slot 4 */
103 lw a0,PT_PADSLOT4(sp) 103 lw a0,PT_PADSLOT4(sp)
104 PTR_LA ra, _ret_from_irq 104 LONG_L s0, TI_REGS($28)
105 LONG_S sp, TI_REGS($28)
106 PTR_LA ra, ret_from_irq
105 jr t0 107 jr t0
106 108
107/* 109/*
@@ -119,7 +121,10 @@ LEAF(self_ipi)
119 subu t1,sp,PT_SIZE 121 subu t1,sp,PT_SIZE
120 sw ra,PT_EPC(t1) 122 sw ra,PT_EPC(t1)
121 sw a0,PT_PADSLOT4(t1) 123 sw a0,PT_PADSLOT4(t1)
124 LONG_L s0, TI_REGS($28)
125 LONG_S sp, TI_REGS($28)
122 la t2,ipi_decode 126 la t2,ipi_decode
127 LONG_S s0, TI_REGS($28)
123 sw t2,PT_PADSLOT5(t1) 128 sw t2,PT_PADSLOT5(t1)
124 /* Save pre-disable value of TCStatus */ 129 /* Save pre-disable value of TCStatus */
125 sw t0,PT_TCSTATUS(t1) 130 sw t0,PT_TCSTATUS(t1)
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index cc1f7474f7d7..802febed7df5 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -476,6 +476,7 @@ void mipsmt_prepare_cpus(void)
476 write_vpe_c0_compare(0); 476 write_vpe_c0_compare(0);
477 /* Propagate Config7 */ 477 /* Propagate Config7 */
478 write_vpe_c0_config7(read_c0_config7()); 478 write_vpe_c0_config7(read_c0_config7());
479 write_vpe_c0_count(read_c0_count());
479 } 480 }
480 /* enable multi-threading within VPE */ 481 /* enable multi-threading within VPE */
481 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE); 482 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE);
@@ -1008,6 +1009,7 @@ void setup_cross_vpe_interrupts(void)
1008 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); 1009 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
1009 1010
1010 irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU; 1011 irq_desc[cpu_ipi_irq].status |= IRQ_PER_CPU;
1012 set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
1011} 1013}
1012 1014
1013/* 1015/*
diff --git a/arch/mips/kernel/stacktrace.c b/arch/mips/kernel/stacktrace.c
index 4aabe526a68e..a586aba337a7 100644
--- a/arch/mips/kernel/stacktrace.c
+++ b/arch/mips/kernel/stacktrace.c
@@ -57,7 +57,7 @@ static void save_context_stack(struct stack_trace *trace,
57 pc = unwind_stack(task, &sp, pc, &ra); 57 pc = unwind_stack(task, &sp, pc, &ra);
58 } while (pc); 58 } while (pc);
59#else 59#else
60 save_raw_context_stack(sp); 60 save_raw_context_stack(trace, sp);
61#endif 61#endif
62} 62}
63 63
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index debe86c2f691..11aab6d6bfe5 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -67,15 +67,9 @@ int (*rtc_mips_set_time)(unsigned long) = null_rtc_set_time;
67int (*rtc_mips_set_mmss)(unsigned long); 67int (*rtc_mips_set_mmss)(unsigned long);
68 68
69 69
70/* usecs per counter cycle, shifted to left by 32 bits */
71static unsigned int sll32_usecs_per_cycle;
72
73/* how many counter cycles in a jiffy */ 70/* how many counter cycles in a jiffy */
74static unsigned long cycles_per_jiffy __read_mostly; 71static unsigned long cycles_per_jiffy __read_mostly;
75 72
76/* Cycle counter value at the previous timer interrupt.. */
77static unsigned int timerhi, timerlo;
78
79/* expirelo is the count value for next CPU timer interrupt */ 73/* expirelo is the count value for next CPU timer interrupt */
80static unsigned int expirelo; 74static unsigned int expirelo;
81 75
@@ -88,17 +82,11 @@ static void null_timer_ack(void) { /* nothing */ }
88/* 82/*
89 * Null high precision timer functions for systems lacking one. 83 * Null high precision timer functions for systems lacking one.
90 */ 84 */
91static unsigned int null_hpt_read(void) 85static cycle_t null_hpt_read(void)
92{ 86{
93 return 0; 87 return 0;
94} 88}
95 89
96static void null_hpt_init(unsigned int count)
97{
98 /* nothing */
99}
100
101
102/* 90/*
103 * Timer ack for an R4k-compatible timer of a known frequency. 91 * Timer ack for an R4k-compatible timer of a known frequency.
104 */ 92 */
@@ -123,191 +111,20 @@ static void c0_timer_ack(void)
123/* 111/*
124 * High precision timer functions for a R4k-compatible timer. 112 * High precision timer functions for a R4k-compatible timer.
125 */ 113 */
126static unsigned int c0_hpt_read(void) 114static cycle_t c0_hpt_read(void)
127{ 115{
128 return read_c0_count(); 116 return read_c0_count();
129} 117}
130 118
131/* For use solely as a high precision timer. */
132static void c0_hpt_init(unsigned int count)
133{
134 write_c0_count(read_c0_count() - count);
135}
136
137/* For use both as a high precision timer and an interrupt source. */ 119/* For use both as a high precision timer and an interrupt source. */
138static void c0_hpt_timer_init(unsigned int count) 120static void __init c0_hpt_timer_init(void)
139{ 121{
140 count = read_c0_count() - count; 122 expirelo = read_c0_count() + cycles_per_jiffy;
141 expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
142 write_c0_count(expirelo - cycles_per_jiffy);
143 write_c0_compare(expirelo); 123 write_c0_compare(expirelo);
144 write_c0_count(count);
145} 124}
146 125
147int (*mips_timer_state)(void); 126int (*mips_timer_state)(void);
148void (*mips_timer_ack)(void); 127void (*mips_timer_ack)(void);
149unsigned int (*mips_hpt_read)(void);
150void (*mips_hpt_init)(unsigned int);
151
152/*
153 * Gettimeoffset routines. These routines returns the time duration
154 * since last timer interrupt in usecs.
155 *
156 * If the exact CPU counter frequency is known, use fixed_rate_gettimeoffset.
157 * Otherwise use calibrate_gettimeoffset()
158 *
159 * If the CPU does not have the counter register, you can either supply
160 * your own gettimeoffset() routine, or use null_gettimeoffset(), which
161 * gives the same resolution as HZ.
162 */
163
164static unsigned long null_gettimeoffset(void)
165{
166 return 0;
167}
168
169
170/* The function pointer to one of the gettimeoffset funcs. */
171unsigned long (*do_gettimeoffset)(void) = null_gettimeoffset;
172
173
174static unsigned long fixed_rate_gettimeoffset(void)
175{
176 u32 count;
177 unsigned long res;
178
179 /* Get last timer tick in absolute kernel time */
180 count = mips_hpt_read();
181
182 /* .. relative to previous jiffy (32 bits is enough) */
183 count -= timerlo;
184
185 __asm__("multu %1,%2"
186 : "=h" (res)
187 : "r" (count), "r" (sll32_usecs_per_cycle)
188 : "lo", GCC_REG_ACCUM);
189
190 /*
191 * Due to possible jiffies inconsistencies, we need to check
192 * the result so that we'll get a timer that is monotonic.
193 */
194 if (res >= USECS_PER_JIFFY)
195 res = USECS_PER_JIFFY - 1;
196
197 return res;
198}
199
200
201/*
202 * Cached "1/(clocks per usec) * 2^32" value.
203 * It has to be recalculated once each jiffy.
204 */
205static unsigned long cached_quotient;
206
207/* Last jiffy when calibrate_divXX_gettimeoffset() was called. */
208static unsigned long last_jiffies;
209
210/*
211 * This is moved from dec/time.c:do_ioasic_gettimeoffset() by Maciej.
212 */
213static unsigned long calibrate_div32_gettimeoffset(void)
214{
215 u32 count;
216 unsigned long res, tmp;
217 unsigned long quotient;
218
219 tmp = jiffies;
220
221 quotient = cached_quotient;
222
223 if (last_jiffies != tmp) {
224 last_jiffies = tmp;
225 if (last_jiffies != 0) {
226 unsigned long r0;
227 do_div64_32(r0, timerhi, timerlo, tmp);
228 do_div64_32(quotient, USECS_PER_JIFFY,
229 USECS_PER_JIFFY_FRAC, r0);
230 cached_quotient = quotient;
231 }
232 }
233
234 /* Get last timer tick in absolute kernel time */
235 count = mips_hpt_read();
236
237 /* .. relative to previous jiffy (32 bits is enough) */
238 count -= timerlo;
239
240 __asm__("multu %1,%2"
241 : "=h" (res)
242 : "r" (count), "r" (quotient)
243 : "lo", GCC_REG_ACCUM);
244
245 /*
246 * Due to possible jiffies inconsistencies, we need to check
247 * the result so that we'll get a timer that is monotonic.
248 */
249 if (res >= USECS_PER_JIFFY)
250 res = USECS_PER_JIFFY - 1;
251
252 return res;
253}
254
255static unsigned long calibrate_div64_gettimeoffset(void)
256{
257 u32 count;
258 unsigned long res, tmp;
259 unsigned long quotient;
260
261 tmp = jiffies;
262
263 quotient = cached_quotient;
264
265 if (last_jiffies != tmp) {
266 last_jiffies = tmp;
267 if (last_jiffies) {
268 unsigned long r0;
269 __asm__(".set push\n\t"
270 ".set mips3\n\t"
271 "lwu %0,%3\n\t"
272 "dsll32 %1,%2,0\n\t"
273 "or %1,%1,%0\n\t"
274 "ddivu $0,%1,%4\n\t"
275 "mflo %1\n\t"
276 "dsll32 %0,%5,0\n\t"
277 "or %0,%0,%6\n\t"
278 "ddivu $0,%0,%1\n\t"
279 "mflo %0\n\t"
280 ".set pop"
281 : "=&r" (quotient), "=&r" (r0)
282 : "r" (timerhi), "m" (timerlo),
283 "r" (tmp), "r" (USECS_PER_JIFFY),
284 "r" (USECS_PER_JIFFY_FRAC)
285 : "hi", "lo", GCC_REG_ACCUM);
286 cached_quotient = quotient;
287 }
288 }
289
290 /* Get last timer tick in absolute kernel time */
291 count = mips_hpt_read();
292
293 /* .. relative to previous jiffy (32 bits is enough) */
294 count -= timerlo;
295
296 __asm__("multu %1,%2"
297 : "=h" (res)
298 : "r" (count), "r" (quotient)
299 : "lo", GCC_REG_ACCUM);
300
301 /*
302 * Due to possible jiffies inconsistencies, we need to check
303 * the result so that we'll get a timer that is monotonic.
304 */
305 if (res >= USECS_PER_JIFFY)
306 res = USECS_PER_JIFFY - 1;
307
308 return res;
309}
310
311 128
312/* last time when xtime and rtc are sync'ed up */ 129/* last time when xtime and rtc are sync'ed up */
313static long last_rtc_update; 130static long last_rtc_update;
@@ -334,18 +151,10 @@ void local_timer_interrupt(int irq, void *dev_id)
334 */ 151 */
335irqreturn_t timer_interrupt(int irq, void *dev_id) 152irqreturn_t timer_interrupt(int irq, void *dev_id)
336{ 153{
337 unsigned long j;
338 unsigned int count;
339
340 write_seqlock(&xtime_lock); 154 write_seqlock(&xtime_lock);
341 155
342 count = mips_hpt_read();
343 mips_timer_ack(); 156 mips_timer_ack();
344 157
345 /* Update timerhi/timerlo for intra-jiffy calibration. */
346 timerhi += count < timerlo; /* Wrap around */
347 timerlo = count;
348
349 /* 158 /*
350 * call the generic timer interrupt handling 159 * call the generic timer interrupt handling
351 */ 160 */
@@ -368,47 +177,6 @@ irqreturn_t timer_interrupt(int irq, void *dev_id)
368 } 177 }
369 } 178 }
370 179
371 /*
372 * If jiffies has overflown in this timer_interrupt, we must
373 * update the timer[hi]/[lo] to make fast gettimeoffset funcs
374 * quotient calc still valid. -arca
375 *
376 * The first timer interrupt comes late as interrupts are
377 * enabled long after timers are initialized. Therefore the
378 * high precision timer is fast, leading to wrong gettimeoffset()
379 * calculations. We deal with it by setting it based on the
380 * number of its ticks between the second and the third interrupt.
381 * That is still somewhat imprecise, but it's a good estimate.
382 * --macro
383 */
384 j = jiffies;
385 if (j < 4) {
386 static unsigned int prev_count;
387 static int hpt_initialized;
388
389 switch (j) {
390 case 0:
391 timerhi = timerlo = 0;
392 mips_hpt_init(count);
393 break;
394 case 2:
395 prev_count = count;
396 break;
397 case 3:
398 if (!hpt_initialized) {
399 unsigned int c3 = 3 * (count - prev_count);
400
401 timerhi = 0;
402 timerlo = c3;
403 mips_hpt_init(count - c3);
404 hpt_initialized = 1;
405 }
406 break;
407 default:
408 break;
409 }
410 }
411
412 write_sequnlock(&xtime_lock); 180 write_sequnlock(&xtime_lock);
413 181
414 /* 182 /*
@@ -476,12 +244,11 @@ asmlinkage void ll_local_timer_interrupt(int irq)
476 * 1) board_time_init() - 244 * 1) board_time_init() -
477 * a) (optional) set up RTC routines, 245 * a) (optional) set up RTC routines,
478 * b) (optional) calibrate and set the mips_hpt_frequency 246 * b) (optional) calibrate and set the mips_hpt_frequency
479 * (only needed if you intended to use fixed_rate_gettimeoffset 247 * (only needed if you intended to use cpu counter as timer interrupt
480 * or use cpu counter as timer interrupt source) 248 * source)
481 * 2) setup xtime based on rtc_mips_get_time(). 249 * 2) setup xtime based on rtc_mips_get_time().
482 * 3) choose a appropriate gettimeoffset routine. 250 * 3) calculate a couple of cached variables for later usage
483 * 4) calculate a couple of cached variables for later usage 251 * 4) plat_timer_setup() -
484 * 5) plat_timer_setup() -
485 * a) (optional) over-write any choices made above by time_init(). 252 * a) (optional) over-write any choices made above by time_init().
486 * b) machine specific code should setup the timer irqaction. 253 * b) machine specific code should setup the timer irqaction.
487 * c) enable the timer interrupt 254 * c) enable the timer interrupt
@@ -499,8 +266,7 @@ static struct irqaction timer_irqaction = {
499 266
500static unsigned int __init calibrate_hpt(void) 267static unsigned int __init calibrate_hpt(void)
501{ 268{
502 u64 frequency; 269 cycle_t frequency, hpt_start, hpt_end, hpt_count, hz;
503 u32 hpt_start, hpt_end, hpt_count, hz;
504 270
505 const int loops = HZ / 10; 271 const int loops = HZ / 10;
506 int log_2_loops = 0; 272 int log_2_loops = 0;
@@ -526,20 +292,49 @@ static unsigned int __init calibrate_hpt(void)
526 * during the calculated number of periods between timer 292 * during the calculated number of periods between timer
527 * interrupts. 293 * interrupts.
528 */ 294 */
529 hpt_start = mips_hpt_read(); 295 hpt_start = clocksource_mips.read();
530 do { 296 do {
531 while (mips_timer_state()); 297 while (mips_timer_state());
532 while (!mips_timer_state()); 298 while (!mips_timer_state());
533 } while (--i); 299 } while (--i);
534 hpt_end = mips_hpt_read(); 300 hpt_end = clocksource_mips.read();
535 301
536 hpt_count = hpt_end - hpt_start; 302 hpt_count = (hpt_end - hpt_start) & clocksource_mips.mask;
537 hz = HZ; 303 hz = HZ;
538 frequency = (u64)hpt_count * (u64)hz; 304 frequency = hpt_count * hz;
539 305
540 return frequency >> log_2_loops; 306 return frequency >> log_2_loops;
541} 307}
542 308
309struct clocksource clocksource_mips = {
310 .name = "MIPS",
311 .mask = 0xffffffff,
312 .is_continuous = 1,
313};
314
315static void __init init_mips_clocksource(void)
316{
317 u64 temp;
318 u32 shift;
319
320 if (!mips_hpt_frequency || clocksource_mips.read == null_hpt_read)
321 return;
322
323 /* Calclate a somewhat reasonable rating value */
324 clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
325 /* Find a shift value */
326 for (shift = 32; shift > 0; shift--) {
327 temp = (u64) NSEC_PER_SEC << shift;
328 do_div(temp, mips_hpt_frequency);
329 if ((temp >> 32) == 0)
330 break;
331 }
332 clocksource_mips.shift = shift;
333 clocksource_mips.mult = (u32)temp;
334
335 clocksource_register(&clocksource_mips);
336}
337
543void __init time_init(void) 338void __init time_init(void)
544{ 339{
545 if (board_time_init) 340 if (board_time_init)
@@ -555,59 +350,36 @@ void __init time_init(void)
555 -xtime.tv_sec, -xtime.tv_nsec); 350 -xtime.tv_sec, -xtime.tv_nsec);
556 351
557 /* Choose appropriate high precision timer routines. */ 352 /* Choose appropriate high precision timer routines. */
558 if (!cpu_has_counter && !mips_hpt_read) { 353 if (!cpu_has_counter && !clocksource_mips.read)
559 /* No high precision timer -- sorry. */ 354 /* No high precision timer -- sorry. */
560 mips_hpt_read = null_hpt_read; 355 clocksource_mips.read = null_hpt_read;
561 mips_hpt_init = null_hpt_init; 356 else if (!mips_hpt_frequency && !mips_timer_state) {
562 } else if (!mips_hpt_frequency && !mips_timer_state) {
563 /* A high precision timer of unknown frequency. */ 357 /* A high precision timer of unknown frequency. */
564 if (!mips_hpt_read) { 358 if (!clocksource_mips.read)
565 /* No external high precision timer -- use R4k. */ 359 /* No external high precision timer -- use R4k. */
566 mips_hpt_read = c0_hpt_read; 360 clocksource_mips.read = c0_hpt_read;
567 mips_hpt_init = c0_hpt_init;
568 }
569
570 if (cpu_has_mips32r1 || cpu_has_mips32r2 ||
571 (current_cpu_data.isa_level == MIPS_CPU_ISA_I) ||
572 (current_cpu_data.isa_level == MIPS_CPU_ISA_II))
573 /*
574 * We need to calibrate the counter but we don't have
575 * 64-bit division.
576 */
577 do_gettimeoffset = calibrate_div32_gettimeoffset;
578 else
579 /*
580 * We need to calibrate the counter but we *do* have
581 * 64-bit division.
582 */
583 do_gettimeoffset = calibrate_div64_gettimeoffset;
584 } else { 361 } else {
585 /* We know counter frequency. Or we can get it. */ 362 /* We know counter frequency. Or we can get it. */
586 if (!mips_hpt_read) { 363 if (!clocksource_mips.read) {
587 /* No external high precision timer -- use R4k. */ 364 /* No external high precision timer -- use R4k. */
588 mips_hpt_read = c0_hpt_read; 365 clocksource_mips.read = c0_hpt_read;
589 366
590 if (mips_timer_state) 367 if (!mips_timer_state) {
591 mips_hpt_init = c0_hpt_init;
592 else {
593 /* No external timer interrupt -- use R4k. */ 368 /* No external timer interrupt -- use R4k. */
594 mips_hpt_init = c0_hpt_timer_init;
595 mips_timer_ack = c0_timer_ack; 369 mips_timer_ack = c0_timer_ack;
370 /* Calculate cache parameters. */
371 cycles_per_jiffy =
372 (mips_hpt_frequency + HZ / 2) / HZ;
373 /*
374 * This sets up the high precision
375 * timer for the first interrupt.
376 */
377 c0_hpt_timer_init();
596 } 378 }
597 } 379 }
598 if (!mips_hpt_frequency) 380 if (!mips_hpt_frequency)
599 mips_hpt_frequency = calibrate_hpt(); 381 mips_hpt_frequency = calibrate_hpt();
600 382
601 do_gettimeoffset = fixed_rate_gettimeoffset;
602
603 /* Calculate cache parameters. */
604 cycles_per_jiffy = (mips_hpt_frequency + HZ / 2) / HZ;
605
606 /* sll32_usecs_per_cycle = 10^6 * 2^32 / mips_counter_freq */
607 do_div64_32(sll32_usecs_per_cycle,
608 1000000, mips_hpt_frequency / 2,
609 mips_hpt_frequency);
610
611 /* Report the high precision timer rate for a reference. */ 383 /* Report the high precision timer rate for a reference. */
612 printk("Using %u.%03u MHz high precision timer.\n", 384 printk("Using %u.%03u MHz high precision timer.\n",
613 ((mips_hpt_frequency + 500) / 1000) / 1000, 385 ((mips_hpt_frequency + 500) / 1000) / 1000,
@@ -618,9 +390,6 @@ void __init time_init(void)
618 /* No timer interrupt ack (e.g. i8254). */ 390 /* No timer interrupt ack (e.g. i8254). */
619 mips_timer_ack = null_timer_ack; 391 mips_timer_ack = null_timer_ack;
620 392
621 /* This sets up the high precision timer for the first interrupt. */
622 mips_hpt_init(mips_hpt_read());
623
624 /* 393 /*
625 * Call board specific timer interrupt setup. 394 * Call board specific timer interrupt setup.
626 * 395 *
@@ -633,6 +402,8 @@ void __init time_init(void)
633 * is not invoked accidentally. 402 * is not invoked accidentally.
634 */ 403 */
635 plat_timer_setup(&timer_irqaction); 404 plat_timer_setup(&timer_irqaction);
405
406 init_mips_clocksource();
636} 407}
637 408
638#define FEBRUARY 2 409#define FEBRUARY 2
diff --git a/arch/mips/kernel/topology.c b/arch/mips/kernel/topology.c
new file mode 100644
index 000000000000..660e44ed44d7
--- /dev/null
+++ b/arch/mips/kernel/topology.c
@@ -0,0 +1,29 @@
1#include <linux/cpu.h>
2#include <linux/cpumask.h>
3#include <linux/init.h>
4#include <linux/node.h>
5#include <linux/nodemask.h>
6#include <linux/percpu.h>
7
8static DEFINE_PER_CPU(struct cpu, cpu_devices);
9
10static int __init topology_init(void)
11{
12 int i, ret;
13
14#ifdef CONFIG_NUMA
15 for_each_online_node(i)
16 register_one_node(i);
17#endif /* CONFIG_NUMA */
18
19 for_each_present_cpu(i) {
20 ret = register_cpu(&per_cpu(cpu_devices, i), i);
21 if (ret)
22 printk(KERN_WARNING "topology_init: register_cpu %d "
23 "failed (%d)\n", i, ret);
24 }
25
26 return 0;
27}
28
29subsys_initcall(topology_init);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index cce8313ec27d..2a932cada244 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -54,6 +54,8 @@ extern asmlinkage void handle_dbe(void);
54extern asmlinkage void handle_sys(void); 54extern asmlinkage void handle_sys(void);
55extern asmlinkage void handle_bp(void); 55extern asmlinkage void handle_bp(void);
56extern asmlinkage void handle_ri(void); 56extern asmlinkage void handle_ri(void);
57extern asmlinkage void handle_ri_rdhwr_vivt(void);
58extern asmlinkage void handle_ri_rdhwr(void);
57extern asmlinkage void handle_cpu(void); 59extern asmlinkage void handle_cpu(void);
58extern asmlinkage void handle_ov(void); 60extern asmlinkage void handle_ov(void);
59extern asmlinkage void handle_tr(void); 61extern asmlinkage void handle_tr(void);
@@ -397,19 +399,6 @@ asmlinkage void do_be(struct pt_regs *regs)
397 force_sig(SIGBUS, current); 399 force_sig(SIGBUS, current);
398} 400}
399 401
400static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
401{
402 unsigned int __user *epc;
403
404 epc = (unsigned int __user *) regs->cp0_epc +
405 ((regs->cp0_cause & CAUSEF_BD) != 0);
406 if (!get_user(*opcode, epc))
407 return 0;
408
409 force_sig(SIGSEGV, current);
410 return 1;
411}
412
413/* 402/*
414 * ll/sc emulation 403 * ll/sc emulation
415 */ 404 */
@@ -544,8 +533,8 @@ static inline int simulate_llsc(struct pt_regs *regs)
544{ 533{
545 unsigned int opcode; 534 unsigned int opcode;
546 535
547 if (unlikely(get_insn_opcode(regs, &opcode))) 536 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
548 return -EFAULT; 537 goto out_sigsegv;
549 538
550 if ((opcode & OPCODE) == LL) { 539 if ((opcode & OPCODE) == LL) {
551 simulate_ll(regs, opcode); 540 simulate_ll(regs, opcode);
@@ -557,6 +546,10 @@ static inline int simulate_llsc(struct pt_regs *regs)
557 } 546 }
558 547
559 return -EFAULT; /* Strange things going on ... */ 548 return -EFAULT; /* Strange things going on ... */
549
550out_sigsegv:
551 force_sig(SIGSEGV, current);
552 return -EFAULT;
560} 553}
561 554
562/* 555/*
@@ -569,8 +562,8 @@ static inline int simulate_rdhwr(struct pt_regs *regs)
569 struct thread_info *ti = task_thread_info(current); 562 struct thread_info *ti = task_thread_info(current);
570 unsigned int opcode; 563 unsigned int opcode;
571 564
572 if (unlikely(get_insn_opcode(regs, &opcode))) 565 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
573 return -EFAULT; 566 goto out_sigsegv;
574 567
575 if (unlikely(compute_return_epc(regs))) 568 if (unlikely(compute_return_epc(regs)))
576 return -EFAULT; 569 return -EFAULT;
@@ -589,6 +582,10 @@ static inline int simulate_rdhwr(struct pt_regs *regs)
589 582
590 /* Not ours. */ 583 /* Not ours. */
591 return -EFAULT; 584 return -EFAULT;
585
586out_sigsegv:
587 force_sig(SIGSEGV, current);
588 return -EFAULT;
592} 589}
593 590
594asmlinkage void do_ov(struct pt_regs *regs) 591asmlinkage void do_ov(struct pt_regs *regs)
@@ -672,10 +669,8 @@ asmlinkage void do_bp(struct pt_regs *regs)
672 unsigned int opcode, bcode; 669 unsigned int opcode, bcode;
673 siginfo_t info; 670 siginfo_t info;
674 671
675 die_if_kernel("Break instruction in kernel code", regs); 672 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
676 673 goto out_sigsegv;
677 if (get_insn_opcode(regs, &opcode))
678 return;
679 674
680 /* 675 /*
681 * There is the ancient bug in the MIPS assemblers that the break 676 * There is the ancient bug in the MIPS assemblers that the break
@@ -696,6 +691,7 @@ asmlinkage void do_bp(struct pt_regs *regs)
696 switch (bcode) { 691 switch (bcode) {
697 case BRK_OVERFLOW << 10: 692 case BRK_OVERFLOW << 10:
698 case BRK_DIVZERO << 10: 693 case BRK_DIVZERO << 10:
694 die_if_kernel("Break instruction in kernel code", regs);
699 if (bcode == (BRK_DIVZERO << 10)) 695 if (bcode == (BRK_DIVZERO << 10))
700 info.si_code = FPE_INTDIV; 696 info.si_code = FPE_INTDIV;
701 else 697 else
@@ -705,9 +701,16 @@ asmlinkage void do_bp(struct pt_regs *regs)
705 info.si_addr = (void __user *) regs->cp0_epc; 701 info.si_addr = (void __user *) regs->cp0_epc;
706 force_sig_info(SIGFPE, &info, current); 702 force_sig_info(SIGFPE, &info, current);
707 break; 703 break;
704 case BRK_BUG:
705 die("Kernel bug detected", regs);
706 break;
708 default: 707 default:
708 die_if_kernel("Break instruction in kernel code", regs);
709 force_sig(SIGTRAP, current); 709 force_sig(SIGTRAP, current);
710 } 710 }
711
712out_sigsegv:
713 force_sig(SIGSEGV, current);
711} 714}
712 715
713asmlinkage void do_tr(struct pt_regs *regs) 716asmlinkage void do_tr(struct pt_regs *regs)
@@ -715,10 +718,8 @@ asmlinkage void do_tr(struct pt_regs *regs)
715 unsigned int opcode, tcode = 0; 718 unsigned int opcode, tcode = 0;
716 siginfo_t info; 719 siginfo_t info;
717 720
718 die_if_kernel("Trap instruction in kernel code", regs); 721 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
719 722 goto out_sigsegv;
720 if (get_insn_opcode(regs, &opcode))
721 return;
722 723
723 /* Immediate versions don't provide a code. */ 724 /* Immediate versions don't provide a code. */
724 if (!(opcode & OPCODE)) 725 if (!(opcode & OPCODE))
@@ -733,6 +734,7 @@ asmlinkage void do_tr(struct pt_regs *regs)
733 switch (tcode) { 734 switch (tcode) {
734 case BRK_OVERFLOW: 735 case BRK_OVERFLOW:
735 case BRK_DIVZERO: 736 case BRK_DIVZERO:
737 die_if_kernel("Trap instruction in kernel code", regs);
736 if (tcode == BRK_DIVZERO) 738 if (tcode == BRK_DIVZERO)
737 info.si_code = FPE_INTDIV; 739 info.si_code = FPE_INTDIV;
738 else 740 else
@@ -742,9 +744,16 @@ asmlinkage void do_tr(struct pt_regs *regs)
742 info.si_addr = (void __user *) regs->cp0_epc; 744 info.si_addr = (void __user *) regs->cp0_epc;
743 force_sig_info(SIGFPE, &info, current); 745 force_sig_info(SIGFPE, &info, current);
744 break; 746 break;
747 case BRK_BUG:
748 die("Kernel bug detected", regs);
749 break;
745 default: 750 default:
751 die_if_kernel("Trap instruction in kernel code", regs);
746 force_sig(SIGTRAP, current); 752 force_sig(SIGTRAP, current);
747 } 753 }
754
755out_sigsegv:
756 force_sig(SIGSEGV, current);
748} 757}
749 758
750asmlinkage void do_ri(struct pt_regs *regs) 759asmlinkage void do_ri(struct pt_regs *regs)
@@ -1111,7 +1120,7 @@ static struct shadow_registers {
1111static void mips_srs_init(void) 1120static void mips_srs_init(void)
1112{ 1121{
1113 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1122 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1114 printk(KERN_INFO "%d MIPSR2 register sets available\n", 1123 printk(KERN_INFO "%ld MIPSR2 register sets available\n",
1115 shadow_registers.sr_supported); 1124 shadow_registers.sr_supported);
1116 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ 1125 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1117} 1126}
@@ -1423,6 +1432,15 @@ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned lon
1423 memcpy((void *)(uncached_ebase + offset), addr, size); 1432 memcpy((void *)(uncached_ebase + offset), addr, size);
1424} 1433}
1425 1434
1435static int __initdata rdhwr_noopt;
1436static int __init set_rdhwr_noopt(char *str)
1437{
1438 rdhwr_noopt = 1;
1439 return 1;
1440}
1441
1442__setup("rdhwr_noopt", set_rdhwr_noopt);
1443
1426void __init trap_init(void) 1444void __init trap_init(void)
1427{ 1445{
1428 extern char except_vec3_generic, except_vec3_r4000; 1446 extern char except_vec3_generic, except_vec3_r4000;
@@ -1502,7 +1520,9 @@ void __init trap_init(void)
1502 1520
1503 set_except_vector(8, handle_sys); 1521 set_except_vector(8, handle_sys);
1504 set_except_vector(9, handle_bp); 1522 set_except_vector(9, handle_bp);
1505 set_except_vector(10, handle_ri); 1523 set_except_vector(10, rdhwr_noopt ? handle_ri :
1524 (cpu_has_vtag_icache ?
1525 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1506 set_except_vector(11, handle_cpu); 1526 set_except_vector(11, handle_cpu);
1507 set_except_vector(12, handle_ov); 1527 set_except_vector(12, handle_ov);
1508 set_except_vector(13, handle_tr); 1528 set_except_vector(13, handle_tr);
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 0bb9cd889456..79f0317d84ac 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -50,6 +50,16 @@ SECTIONS
50 /* writeable */ 50 /* writeable */
51 .data : { /* Data */ 51 .data : { /* Data */
52 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ 52 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
53 /*
54 * This ALIGN is needed as a workaround for a bug a gcc bug upto 4.1 which
55 * limits the maximum alignment to at most 32kB and results in the following
56 * warning:
57 *
58 * CC arch/mips/kernel/init_task.o
59 * arch/mips/kernel/init_task.c:30: warning: alignment of ‘init_thread_union’
60 * is greater than maximum object file alignment. Using 32768
61 */
62 . = ALIGN(_PAGE_SIZE);
53 *(.data.init_task) 63 *(.data.init_task)
54 64
55 *(.data) 65 *(.data)
@@ -91,13 +101,7 @@ SECTIONS
91 101
92 __initcall_start = .; 102 __initcall_start = .;
93 .initcall.init : { 103 .initcall.init : {
94 *(.initcall1.init) 104 INITCALLS
95 *(.initcall2.init)
96 *(.initcall3.init)
97 *(.initcall4.init)
98 *(.initcall5.init)
99 *(.initcall6.init)
100 *(.initcall7.init)
101 } 105 }
102 __initcall_end = .; 106 __initcall_end = .;
103 107
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index a144a002dcc4..4a84a7beac53 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -36,33 +36,14 @@ static volatile int lasat_int_mask_shift;
36 36
37void disable_lasat_irq(unsigned int irq_nr) 37void disable_lasat_irq(unsigned int irq_nr)
38{ 38{
39 unsigned long flags;
40
41 local_irq_save(flags);
42 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift; 39 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift;
43 local_irq_restore(flags);
44} 40}
45 41
46void enable_lasat_irq(unsigned int irq_nr) 42void enable_lasat_irq(unsigned int irq_nr)
47{ 43{
48 unsigned long flags;
49
50 local_irq_save(flags);
51 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; 44 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
52 local_irq_restore(flags);
53} 45}
54 46
55static unsigned int startup_lasat_irq(unsigned int irq)
56{
57 enable_lasat_irq(irq);
58
59 return 0; /* never anything pending */
60}
61
62#define shutdown_lasat_irq disable_lasat_irq
63
64#define mask_and_ack_lasat_irq disable_lasat_irq
65
66static void end_lasat_irq(unsigned int irq) 47static void end_lasat_irq(unsigned int irq)
67{ 48{
68 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 49 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -71,11 +52,10 @@ static void end_lasat_irq(unsigned int irq)
71 52
72static struct irq_chip lasat_irq_type = { 53static struct irq_chip lasat_irq_type = {
73 .typename = "Lasat", 54 .typename = "Lasat",
74 .startup = startup_lasat_irq, 55 .ack = disable_lasat_irq,
75 .shutdown = shutdown_lasat_irq, 56 .mask = disable_lasat_irq,
76 .enable = enable_lasat_irq, 57 .mask_ack = disable_lasat_irq,
77 .disable = disable_lasat_irq, 58 .unmask = enable_lasat_irq,
78 .ack = mask_and_ack_lasat_irq,
79 .end = end_lasat_irq, 59 .end = end_lasat_irq,
80}; 60};
81 61
@@ -152,10 +132,6 @@ void __init arch_init_irq(void)
152 panic("arch_init_irq: mips_machtype incorrect"); 132 panic("arch_init_irq: mips_machtype incorrect");
153 } 133 }
154 134
155 for (i = 0; i <= LASATINT_END; i++) { 135 for (i = 0; i <= LASATINT_END; i++)
156 irq_desc[i].status = IRQ_DISABLED; 136 set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
157 irq_desc[i].action = 0;
158 irq_desc[i].depth = 1;
159 irq_desc[i].chip = &lasat_irq_type;
160 }
161} 137}
diff --git a/arch/mips/lib-64/dump_tlb.c b/arch/mips/lib-64/dump_tlb.c
index be8261be679b..594df1a05ecc 100644
--- a/arch/mips/lib-64/dump_tlb.c
+++ b/arch/mips/lib-64/dump_tlb.c
@@ -149,7 +149,7 @@ void dump_list_process(struct task_struct *t, void *address)
149 printk("Addr == %08lx\n", addr); 149 printk("Addr == %08lx\n", addr);
150 printk("tasks->mm.pgd == %08lx\n", (unsigned long) t->mm->pgd); 150 printk("tasks->mm.pgd == %08lx\n", (unsigned long) t->mm->pgd);
151 151
152 page_dir = pgd_offset(t->mm, 0); 152 page_dir = pgd_offset(t->mm, 0UL);
153 printk("page_dir == %016lx\n", (unsigned long) page_dir); 153 printk("page_dir == %016lx\n", (unsigned long) page_dir);
154 154
155 pgd = pgd_offset(t->mm, addr); 155 pgd = pgd_offset(t->mm, addr);
@@ -184,13 +184,13 @@ void dump_list_current(void *address)
184 dump_list_process(current, address); 184 dump_list_process(current, address);
185} 185}
186 186
187unsigned int vtop(void *address) 187unsigned long vtop(void *address)
188{ 188{
189 pgd_t *pgd; 189 pgd_t *pgd;
190 pud_t *pud; 190 pud_t *pud;
191 pmd_t *pmd; 191 pmd_t *pmd;
192 pte_t *pte; 192 pte_t *pte;
193 unsigned int addr, paddr; 193 unsigned long addr, paddr;
194 194
195 addr = (unsigned long) address; 195 addr = (unsigned long) address;
196 pgd = pgd_offset(current->mm, addr); 196 pgd = pgd_offset(current->mm, addr);
diff --git a/arch/mips/lib/csum_partial_copy.c b/arch/mips/lib/csum_partial_copy.c
index 6e9f366f961d..1720f2ceeeae 100644
--- a/arch/mips/lib/csum_partial_copy.c
+++ b/arch/mips/lib/csum_partial_copy.c
@@ -16,8 +16,8 @@
16/* 16/*
17 * copy while checksumming, otherwise like csum_partial 17 * copy while checksumming, otherwise like csum_partial
18 */ 18 */
19unsigned int csum_partial_copy_nocheck(const unsigned char *src, 19__wsum csum_partial_copy_nocheck(const void *src,
20 unsigned char *dst, int len, unsigned int sum) 20 void *dst, int len, __wsum sum)
21{ 21{
22 /* 22 /*
23 * It's 2:30 am and I don't feel like doing it real ... 23 * It's 2:30 am and I don't feel like doing it real ...
@@ -33,8 +33,8 @@ unsigned int csum_partial_copy_nocheck(const unsigned char *src,
33 * Copy from userspace and compute checksum. If we catch an exception 33 * Copy from userspace and compute checksum. If we catch an exception
34 * then zero the rest of the buffer. 34 * then zero the rest of the buffer.
35 */ 35 */
36unsigned int csum_partial_copy_from_user (const unsigned char __user *src, 36__wsum csum_partial_copy_from_user (const void __user *src,
37 unsigned char *dst, int len, unsigned int sum, int *err_ptr) 37 void *dst, int len, __wsum sum, int *err_ptr)
38{ 38{
39 int missing; 39 int missing;
40 40
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index be624b8c3b0e..43dba6ce6603 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -62,16 +62,6 @@ void enable_atlas_irq(unsigned int irq_nr)
62 iob(); 62 iob();
63} 63}
64 64
65static unsigned int startup_atlas_irq(unsigned int irq)
66{
67 enable_atlas_irq(irq);
68 return 0; /* never anything pending */
69}
70
71#define shutdown_atlas_irq disable_atlas_irq
72
73#define mask_and_ack_atlas_irq disable_atlas_irq
74
75static void end_atlas_irq(unsigned int irq) 65static void end_atlas_irq(unsigned int irq)
76{ 66{
77 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 67 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -80,11 +70,11 @@ static void end_atlas_irq(unsigned int irq)
80 70
81static struct irq_chip atlas_irq_type = { 71static struct irq_chip atlas_irq_type = {
82 .typename = "Atlas", 72 .typename = "Atlas",
83 .startup = startup_atlas_irq, 73 .ack = disable_atlas_irq,
84 .shutdown = shutdown_atlas_irq, 74 .mask = disable_atlas_irq,
85 .enable = enable_atlas_irq, 75 .mask_ack = disable_atlas_irq,
86 .disable = disable_atlas_irq, 76 .unmask = enable_atlas_irq,
87 .ack = mask_and_ack_atlas_irq, 77 .eoi = enable_atlas_irq,
88 .end = end_atlas_irq, 78 .end = end_atlas_irq,
89}; 79};
90 80
@@ -217,13 +207,8 @@ static inline void init_atlas_irqs (int base)
217 */ 207 */
218 atlas_hw0_icregs->intrsten = 0xffffffff; 208 atlas_hw0_icregs->intrsten = 0xffffffff;
219 209
220 for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) { 210 for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++)
221 irq_desc[i].status = IRQ_DISABLED; 211 set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq);
222 irq_desc[i].action = 0;
223 irq_desc[i].depth = 1;
224 irq_desc[i].chip = &atlas_irq_type;
225 spin_lock_init(&irq_desc[i].lock);
226 }
227} 212}
228 213
229static struct irqaction atlasirq = { 214static struct irqaction atlasirq = {
diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c
index be80c5dd4a0c..eeed944e0f83 100644
--- a/arch/mips/mips-boards/generic/memory.c
+++ b/arch/mips/mips-boards/generic/memory.c
@@ -176,7 +176,7 @@ unsigned long __init prom_free_prom_memory(void)
176 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) 176 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
177 continue; 177 continue;
178 178
179 addr = boot_mem_map.map[i].addr; 179 addr = PAGE_ALIGN(boot_mem_map.map[i].addr);
180 while (addr < boot_mem_map.map[i].addr 180 while (addr < boot_mem_map.map[i].addr
181 + boot_mem_map.map[i].size) { 181 + boot_mem_map.map[i].size) {
182 ClearPageReserved(virt_to_page(__va(addr))); 182 ClearPageReserved(virt_to_page(__va(addr)));
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index 9337f6c8873a..3192a14698c8 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -90,7 +90,7 @@ static struct pci_controller msc_controller = {
90void __init mips_pcibios_init(void) 90void __init mips_pcibios_init(void)
91{ 91{
92 struct pci_controller *controller; 92 struct pci_controller *controller;
93 unsigned long start, end, map, start1, end1, map1, map2, map3, mask; 93 resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;
94 94
95 switch (mips_revision_corid) { 95 switch (mips_revision_corid) {
96 case MIPS_REVISION_CORID_QED_RM5261: 96 case MIPS_REVISION_CORID_QED_RM5261:
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 6f8a9fe7c1e3..e4604c73f02e 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -187,7 +187,7 @@ out:
187} 187}
188 188
189/* 189/*
190 * Estimate CPU frequency. Sets mips_counter_frequency as a side-effect 190 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
191 */ 191 */
192static unsigned int __init estimate_cpu_frequency(void) 192static unsigned int __init estimate_cpu_frequency(void)
193{ 193{
@@ -208,7 +208,8 @@ static unsigned int __init estimate_cpu_frequency(void)
208 count = 6000000; 208 count = 6000000;
209#endif 209#endif
210#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) 210#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
211 unsigned int flags; 211 unsigned long flags;
212 unsigned int start;
212 213
213 local_irq_save(flags); 214 local_irq_save(flags);
214 215
@@ -217,13 +218,13 @@ static unsigned int __init estimate_cpu_frequency(void)
217 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 218 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
218 219
219 /* Start r4k counter. */ 220 /* Start r4k counter. */
220 write_c0_count(0); 221 start = read_c0_count();
221 222
222 /* Read counter exactly on falling edge of update flag */ 223 /* Read counter exactly on falling edge of update flag */
223 while (CMOS_READ(RTC_REG_A) & RTC_UIP); 224 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
224 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 225 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
225 226
226 count = read_c0_count(); 227 count = read_c0_count() - start;
227 228
228 /* restore interrupts */ 229 /* restore interrupts */
229 local_irq_restore(flags); 230 local_irq_restore(flags);
@@ -287,6 +288,7 @@ void __init plat_timer_setup(struct irqaction *irq)
287 The effect is that the int remains disabled on the second cpu. 288 The effect is that the int remains disabled on the second cpu.
288 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ 289 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
289 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; 290 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
291 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
290#endif 292#endif
291 293
292 /* to generate the first timer interrupt */ 294 /* to generate the first timer interrupt */
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 6244d0e2c7de..90ad5bf3e2f1 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -32,6 +32,7 @@
32#include <asm/i8259.h> 32#include <asm/i8259.h>
33#include <asm/irq_cpu.h> 33#include <asm/irq_cpu.h>
34#include <asm/io.h> 34#include <asm/io.h>
35#include <asm/irq_regs.h>
35#include <asm/mips-boards/malta.h> 36#include <asm/mips-boards/malta.h>
36#include <asm/mips-boards/maltaint.h> 37#include <asm/mips-boards/maltaint.h>
37#include <asm/mips-boards/piix4.h> 38#include <asm/mips-boards/piix4.h>
@@ -131,7 +132,7 @@ static void corehi_irqdispatch(void)
131 unsigned int intedge, intsteer, pcicmd, pcibadaddr; 132 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
132 unsigned int pcimstat, intisr, inten, intpol; 133 unsigned int pcimstat, intisr, inten, intpol;
133 unsigned int intrcause,datalo,datahi; 134 unsigned int intrcause,datalo,datahi;
134 struct pt_regs *regs; 135 struct pt_regs *regs = get_irq_regs();
135 136
136 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); 137 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
137 printk("epc : %08lx\nStatus: %08lx\n" 138 printk("epc : %08lx\nStatus: %08lx\n"
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index ab460f805bef..282f3e52eea3 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -159,7 +159,7 @@ void __init plat_mem_setup(void)
159 BONITO_PCIMEMBASECFG |= 159 BONITO_PCIMEMBASECFG |=
160 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | 160 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
161 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); 161 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
162 printk("Disabled Bonito IOBC coherency\n"); 162 printk("Enabled Bonito IOBC coherency\n");
163 } 163 }
164 } 164 }
165 else 165 else
diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c
index c566b9bd0427..30711d016fed 100644
--- a/arch/mips/mips-boards/sim/sim_time.c
+++ b/arch/mips/mips-boards/sim/sim_time.c
@@ -3,31 +3,24 @@
3#include <linux/kernel_stat.h> 3#include <linux/kernel_stat.h>
4#include <linux/sched.h> 4#include <linux/sched.h>
5#include <linux/spinlock.h> 5#include <linux/spinlock.h>
6
7#include <asm/mipsregs.h>
8#include <asm/ptrace.h>
9#include <asm/hardirq.h>
10#include <asm/div64.h>
11#include <asm/cpu.h>
12#include <asm/time.h>
13
14#include <linux/interrupt.h> 6#include <linux/interrupt.h>
15#include <linux/mc146818rtc.h> 7#include <linux/mc146818rtc.h>
16#include <linux/timex.h> 8#include <linux/timex.h>
9
17#include <asm/mipsregs.h> 10#include <asm/mipsregs.h>
11#include <asm/ptrace.h>
18#include <asm/hardirq.h> 12#include <asm/hardirq.h>
19#include <asm/irq.h>
20#include <asm/div64.h> 13#include <asm/div64.h>
21#include <asm/cpu.h> 14#include <asm/cpu.h>
22#include <asm/time.h> 15#include <asm/time.h>
16#include <asm/irq.h>
23#include <asm/mc146818-time.h> 17#include <asm/mc146818-time.h>
24#include <asm/msc01_ic.h> 18#include <asm/msc01_ic.h>
19#include <asm/smp.h>
25 20
26#include <asm/mips-boards/generic.h> 21#include <asm/mips-boards/generic.h>
27#include <asm/mips-boards/prom.h> 22#include <asm/mips-boards/prom.h>
28#include <asm/mips-boards/simint.h> 23#include <asm/mips-boards/simint.h>
29#include <asm/mc146818-time.h>
30#include <asm/smp.h>
31 24
32 25
33unsigned long cpu_khz; 26unsigned long cpu_khz;
@@ -102,7 +95,7 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
102 95
103 96
104/* 97/*
105 * Estimate CPU frequency. Sets mips_counter_frequency as a side-effect 98 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
106 */ 99 */
107static unsigned int __init estimate_cpu_frequency(void) 100static unsigned int __init estimate_cpu_frequency(void)
108{ 101{
@@ -203,7 +196,8 @@ void __init plat_timer_setup(struct irqaction *irq)
203 on seperate cpu's the first one tries to handle the second interrupt. 196 on seperate cpu's the first one tries to handle the second interrupt.
204 The effect is that the int remains disabled on the second cpu. 197 The effect is that the int remains disabled on the second cpu.
205 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ 198 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
206 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; 199 irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU;
200 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
207#endif 201#endif
208 202
209 /* to generate the first timer interrupt */ 203 /* to generate the first timer interrupt */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index cc895dad71d2..df04a315d830 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -323,7 +323,6 @@ static void __init r4k_blast_scache_setup(void)
323static inline void local_r4k_flush_cache_all(void * args) 323static inline void local_r4k_flush_cache_all(void * args)
324{ 324{
325 r4k_blast_dcache(); 325 r4k_blast_dcache();
326 r4k_blast_icache();
327} 326}
328 327
329static void r4k_flush_cache_all(void) 328static void r4k_flush_cache_all(void)
@@ -359,21 +358,19 @@ static void r4k___flush_cache_all(void)
359static inline void local_r4k_flush_cache_range(void * args) 358static inline void local_r4k_flush_cache_range(void * args)
360{ 359{
361 struct vm_area_struct *vma = args; 360 struct vm_area_struct *vma = args;
362 int exec;
363 361
364 if (!(cpu_context(smp_processor_id(), vma->vm_mm))) 362 if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
365 return; 363 return;
366 364
367 exec = vma->vm_flags & VM_EXEC; 365 r4k_blast_dcache();
368 if (cpu_has_dc_aliases || exec)
369 r4k_blast_dcache();
370 if (exec)
371 r4k_blast_icache();
372} 366}
373 367
374static void r4k_flush_cache_range(struct vm_area_struct *vma, 368static void r4k_flush_cache_range(struct vm_area_struct *vma,
375 unsigned long start, unsigned long end) 369 unsigned long start, unsigned long end)
376{ 370{
371 if (!cpu_has_dc_aliases)
372 return;
373
377 r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1); 374 r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
378} 375}
379 376
@@ -384,18 +381,21 @@ static inline void local_r4k_flush_cache_mm(void * args)
384 if (!cpu_context(smp_processor_id(), mm)) 381 if (!cpu_context(smp_processor_id(), mm))
385 return; 382 return;
386 383
387 r4k_blast_dcache();
388 r4k_blast_icache();
389
390 /* 384 /*
391 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we 385 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
392 * only flush the primary caches but R10000 and R12000 behave sane ... 386 * only flush the primary caches but R10000 and R12000 behave sane ...
387 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
388 * caches, so we can bail out early.
393 */ 389 */
394 if (current_cpu_data.cputype == CPU_R4000SC || 390 if (current_cpu_data.cputype == CPU_R4000SC ||
395 current_cpu_data.cputype == CPU_R4000MC || 391 current_cpu_data.cputype == CPU_R4000MC ||
396 current_cpu_data.cputype == CPU_R4400SC || 392 current_cpu_data.cputype == CPU_R4400SC ||
397 current_cpu_data.cputype == CPU_R4400MC) 393 current_cpu_data.cputype == CPU_R4400MC) {
398 r4k_blast_scache(); 394 r4k_blast_scache();
395 return;
396 }
397
398 r4k_blast_dcache();
399} 399}
400 400
401static void r4k_flush_cache_mm(struct mm_struct *mm) 401static void r4k_flush_cache_mm(struct mm_struct *mm)
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
index 5537558f19f7..3a8afd47feaa 100644
--- a/arch/mips/mm/c-sb1.c
+++ b/arch/mips/mm/c-sb1.c
@@ -19,6 +19,7 @@
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */ 20 */
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/hardirq.h>
22 23
23#include <asm/asm.h> 24#include <asm/asm.h>
24#include <asm/bootinfo.h> 25#include <asm/bootinfo.h>
@@ -49,6 +50,15 @@ static unsigned short dcache_sets;
49static unsigned int icache_range_cutoff; 50static unsigned int icache_range_cutoff;
50static unsigned int dcache_range_cutoff; 51static unsigned int dcache_range_cutoff;
51 52
53static inline void sb1_on_each_cpu(void (*func) (void *info), void *info,
54 int retry, int wait)
55{
56 preempt_disable();
57 smp_call_function(func, info, retry, wait);
58 func(info);
59 preempt_enable();
60}
61
52/* 62/*
53 * The dcache is fully coherent to the system, with one 63 * The dcache is fully coherent to the system, with one
54 * big caveat: the instruction stream. In other words, 64 * big caveat: the instruction stream. In other words,
@@ -226,13 +236,32 @@ static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
226 args.vma = vma; 236 args.vma = vma;
227 args.addr = addr; 237 args.addr = addr;
228 args.pfn = pfn; 238 args.pfn = pfn;
229 on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1); 239 sb1_on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1);
230} 240}
231#else 241#else
232void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn) 242void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
233 __attribute__((alias("local_sb1_flush_cache_page"))); 243 __attribute__((alias("local_sb1_flush_cache_page")));
234#endif 244#endif
235 245
246#ifdef CONFIG_SMP
247static void sb1_flush_cache_data_page_ipi(void *info)
248{
249 unsigned long start = (unsigned long)info;
250
251 __sb1_writeback_inv_dcache_range(start, start + PAGE_SIZE);
252}
253
254static void sb1_flush_cache_data_page(unsigned long addr)
255{
256 if (in_atomic())
257 __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
258 else
259 on_each_cpu(sb1_flush_cache_data_page_ipi, (void *) addr, 1, 1);
260}
261#else
262void sb1_flush_cache_data_page(unsigned long)
263 __attribute__((alias("local_sb1_flush_cache_data_page")));
264#endif
236 265
237/* 266/*
238 * Invalidate all caches on this CPU 267 * Invalidate all caches on this CPU
@@ -249,7 +278,7 @@ void sb1___flush_cache_all_ipi(void *ignored)
249 278
250static void sb1___flush_cache_all(void) 279static void sb1___flush_cache_all(void)
251{ 280{
252 on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1); 281 sb1_on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1);
253} 282}
254#else 283#else
255void sb1___flush_cache_all(void) 284void sb1___flush_cache_all(void)
@@ -299,7 +328,7 @@ void sb1_flush_icache_range(unsigned long start, unsigned long end)
299 328
300 args.start = start; 329 args.start = start;
301 args.end = end; 330 args.end = end;
302 on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1); 331 sb1_on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1);
303} 332}
304#else 333#else
305void sb1_flush_icache_range(unsigned long start, unsigned long end) 334void sb1_flush_icache_range(unsigned long start, unsigned long end)
@@ -326,7 +355,7 @@ static void sb1_flush_cache_sigtramp_ipi(void *info)
326 355
327static void sb1_flush_cache_sigtramp(unsigned long addr) 356static void sb1_flush_cache_sigtramp(unsigned long addr)
328{ 357{
329 on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1); 358 sb1_on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
330} 359}
331#else 360#else
332void sb1_flush_cache_sigtramp(unsigned long addr) 361void sb1_flush_cache_sigtramp(unsigned long addr)
@@ -444,7 +473,6 @@ static __init void probe_cache_sizes(void)
444void sb1_cache_init(void) 473void sb1_cache_init(void)
445{ 474{
446 extern char except_vec2_sb1; 475 extern char except_vec2_sb1;
447 extern char handle_vec2_sb1;
448 476
449 /* Special cache error handler for SB1 */ 477 /* Special cache error handler for SB1 */
450 set_uncached_handler (0x100, &except_vec2_sb1, 0x80); 478 set_uncached_handler (0x100, &except_vec2_sb1, 0x80);
@@ -473,7 +501,7 @@ void sb1_cache_init(void)
473 501
474 flush_cache_sigtramp = sb1_flush_cache_sigtramp; 502 flush_cache_sigtramp = sb1_flush_cache_sigtramp;
475 local_flush_data_cache_page = (void *) sb1_nop; 503 local_flush_data_cache_page = (void *) sb1_nop;
476 flush_data_cache_page = (void *) sb1_nop; 504 flush_data_cache_page = sb1_flush_cache_data_page;
477 505
478 /* Full flush */ 506 /* Full flush */
479 __flush_cache_all = sb1___flush_cache_all; 507 __flush_cache_all = sb1___flush_cache_all;
@@ -497,5 +525,5 @@ void sb1_cache_init(void)
497 : 525 :
498 : "memory"); 526 : "memory");
499 527
500 flush_cache_all(); 528 local_sb1___flush_cache_all();
501} 529}
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index 8423d8590779..6f90e7ef66ac 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -60,6 +60,10 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write,
60 */ 60 */
61 if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END)) 61 if (unlikely(address >= VMALLOC_START && address <= VMALLOC_END))
62 goto vmalloc_fault; 62 goto vmalloc_fault;
63#ifdef MODULE_START
64 if (unlikely(address >= MODULE_START && address < MODULE_END))
65 goto vmalloc_fault;
66#endif
63 67
64 /* 68 /*
65 * If we're in an interrupt or have no user 69 * If we're in an interrupt or have no user
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 88b72c9a8495..9e29ba9205f0 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -30,11 +30,34 @@
30#include <asm/cachectl.h> 30#include <asm/cachectl.h>
31#include <asm/cpu.h> 31#include <asm/cpu.h>
32#include <asm/dma.h> 32#include <asm/dma.h>
33#include <asm/kmap_types.h>
33#include <asm/mmu_context.h> 34#include <asm/mmu_context.h>
34#include <asm/sections.h> 35#include <asm/sections.h>
35#include <asm/pgtable.h> 36#include <asm/pgtable.h>
36#include <asm/pgalloc.h> 37#include <asm/pgalloc.h>
37#include <asm/tlb.h> 38#include <asm/tlb.h>
39#include <asm/fixmap.h>
40
41/* Atomicity and interruptability */
42#ifdef CONFIG_MIPS_MT_SMTC
43
44#include <asm/mipsmtregs.h>
45
46#define ENTER_CRITICAL(flags) \
47 { \
48 unsigned int mvpflags; \
49 local_irq_save(flags);\
50 mvpflags = dvpe()
51#define EXIT_CRITICAL(flags) \
52 evpe(mvpflags); \
53 local_irq_restore(flags); \
54 }
55#else
56
57#define ENTER_CRITICAL(flags) local_irq_save(flags)
58#define EXIT_CRITICAL(flags) local_irq_restore(flags)
59
60#endif /* CONFIG_MIPS_MT_SMTC */
38 61
39DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); 62DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
40 63
@@ -67,9 +90,9 @@ unsigned long setup_zero_pages(void)
67 if (!empty_zero_page) 90 if (!empty_zero_page)
68 panic("Oh boy, that early out of memory?"); 91 panic("Oh boy, that early out of memory?");
69 92
70 page = virt_to_page(empty_zero_page); 93 page = virt_to_page((void *)empty_zero_page);
71 split_page(page, order); 94 split_page(page, order);
72 while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) { 95 while (page < virt_to_page((void *)(empty_zero_page + (PAGE_SIZE << order)))) {
73 SetPageReserved(page); 96 SetPageReserved(page);
74 page++; 97 page++;
75 } 98 }
@@ -80,13 +103,142 @@ unsigned long setup_zero_pages(void)
80 return 1UL << order; 103 return 1UL << order;
81} 104}
82 105
83#ifdef CONFIG_HIGHMEM 106/*
84pte_t *kmap_pte; 107 * These are almost like kmap_atomic / kunmap_atmic except they take an
85pgprot_t kmap_prot; 108 * additional address argument as the hint.
109 */
86 110
87#define kmap_get_fixmap_pte(vaddr) \ 111#define kmap_get_fixmap_pte(vaddr) \
88 pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) 112 pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr))
89 113
114#ifdef CONFIG_MIPS_MT_SMTC
115static pte_t *kmap_coherent_pte;
116static void __init kmap_coherent_init(void)
117{
118 unsigned long vaddr;
119
120 /* cache the first coherent kmap pte */
121 vaddr = __fix_to_virt(FIX_CMAP_BEGIN);
122 kmap_coherent_pte = kmap_get_fixmap_pte(vaddr);
123}
124#else
125static inline void kmap_coherent_init(void) {}
126#endif
127
128static inline void *kmap_coherent(struct page *page, unsigned long addr)
129{
130 enum fixed_addresses idx;
131 unsigned long vaddr, flags, entrylo;
132 unsigned long old_ctx;
133 pte_t pte;
134 int tlbidx;
135
136 inc_preempt_count();
137 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
138#ifdef CONFIG_MIPS_MT_SMTC
139 idx += FIX_N_COLOURS * smp_processor_id();
140#endif
141 vaddr = __fix_to_virt(FIX_CMAP_END - idx);
142 pte = mk_pte(page, PAGE_KERNEL);
143#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
144 entrylo = pte.pte_high;
145#else
146 entrylo = pte_val(pte) >> 6;
147#endif
148
149 ENTER_CRITICAL(flags);
150 old_ctx = read_c0_entryhi();
151 write_c0_entryhi(vaddr & (PAGE_MASK << 1));
152 write_c0_entrylo0(entrylo);
153 write_c0_entrylo1(entrylo);
154#ifdef CONFIG_MIPS_MT_SMTC
155 set_pte(kmap_coherent_pte - (FIX_CMAP_END - idx), pte);
156 /* preload TLB instead of local_flush_tlb_one() */
157 mtc0_tlbw_hazard();
158 tlb_probe();
159 tlb_probe_hazard();
160 tlbidx = read_c0_index();
161 mtc0_tlbw_hazard();
162 if (tlbidx < 0)
163 tlb_write_random();
164 else
165 tlb_write_indexed();
166#else
167 tlbidx = read_c0_wired();
168 write_c0_wired(tlbidx + 1);
169 write_c0_index(tlbidx);
170 mtc0_tlbw_hazard();
171 tlb_write_indexed();
172#endif
173 tlbw_use_hazard();
174 write_c0_entryhi(old_ctx);
175 EXIT_CRITICAL(flags);
176
177 return (void*) vaddr;
178}
179
180#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
181
182static inline void kunmap_coherent(struct page *page)
183{
184#ifndef CONFIG_MIPS_MT_SMTC
185 unsigned int wired;
186 unsigned long flags, old_ctx;
187
188 ENTER_CRITICAL(flags);
189 old_ctx = read_c0_entryhi();
190 wired = read_c0_wired() - 1;
191 write_c0_wired(wired);
192 write_c0_index(wired);
193 write_c0_entryhi(UNIQUE_ENTRYHI(wired));
194 write_c0_entrylo0(0);
195 write_c0_entrylo1(0);
196 mtc0_tlbw_hazard();
197 tlb_write_indexed();
198 tlbw_use_hazard();
199 write_c0_entryhi(old_ctx);
200 EXIT_CRITICAL(flags);
201#endif
202 dec_preempt_count();
203 preempt_check_resched();
204}
205
206void copy_to_user_page(struct vm_area_struct *vma,
207 struct page *page, unsigned long vaddr, void *dst, const void *src,
208 unsigned long len)
209{
210 if (cpu_has_dc_aliases) {
211 void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
212 memcpy(vto, src, len);
213 kunmap_coherent(page);
214 } else
215 memcpy(dst, src, len);
216 if ((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc)
217 flush_cache_page(vma, vaddr, page_to_pfn(page));
218}
219
220EXPORT_SYMBOL(copy_to_user_page);
221
222void copy_from_user_page(struct vm_area_struct *vma,
223 struct page *page, unsigned long vaddr, void *dst, const void *src,
224 unsigned long len)
225{
226 if (cpu_has_dc_aliases) {
227 void *vfrom =
228 kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
229 memcpy(dst, vfrom, len);
230 kunmap_coherent(page);
231 } else
232 memcpy(dst, src, len);
233}
234
235EXPORT_SYMBOL(copy_from_user_page);
236
237
238#ifdef CONFIG_HIGHMEM
239pte_t *kmap_pte;
240pgprot_t kmap_prot;
241
90static void __init kmap_init(void) 242static void __init kmap_init(void)
91{ 243{
92 unsigned long kmap_vstart; 244 unsigned long kmap_vstart;
@@ -97,11 +249,12 @@ static void __init kmap_init(void)
97 249
98 kmap_prot = PAGE_KERNEL; 250 kmap_prot = PAGE_KERNEL;
99} 251}
252#endif /* CONFIG_HIGHMEM */
100 253
101#ifdef CONFIG_32BIT
102void __init fixrange_init(unsigned long start, unsigned long end, 254void __init fixrange_init(unsigned long start, unsigned long end,
103 pgd_t *pgd_base) 255 pgd_t *pgd_base)
104{ 256{
257#if defined(CONFIG_HIGHMEM) || defined(CONFIG_MIPS_MT_SMTC)
105 pgd_t *pgd; 258 pgd_t *pgd;
106 pud_t *pud; 259 pud_t *pud;
107 pmd_t *pmd; 260 pmd_t *pmd;
@@ -122,7 +275,7 @@ void __init fixrange_init(unsigned long start, unsigned long end,
122 for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) { 275 for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) {
123 if (pmd_none(*pmd)) { 276 if (pmd_none(*pmd)) {
124 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); 277 pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
125 set_pmd(pmd, __pmd(pte)); 278 set_pmd(pmd, __pmd((unsigned long)pte));
126 if (pte != pte_offset_kernel(pmd, 0)) 279 if (pte != pte_offset_kernel(pmd, 0))
127 BUG(); 280 BUG();
128 } 281 }
@@ -132,9 +285,8 @@ void __init fixrange_init(unsigned long start, unsigned long end,
132 } 285 }
133 j = 0; 286 j = 0;
134 } 287 }
288#endif
135} 289}
136#endif /* CONFIG_32BIT */
137#endif /* CONFIG_HIGHMEM */
138 290
139#ifndef CONFIG_NEED_MULTIPLE_NODES 291#ifndef CONFIG_NEED_MULTIPLE_NODES
140extern void pagetable_init(void); 292extern void pagetable_init(void);
@@ -175,6 +327,7 @@ void __init paging_init(void)
175#ifdef CONFIG_HIGHMEM 327#ifdef CONFIG_HIGHMEM
176 kmap_init(); 328 kmap_init();
177#endif 329#endif
330 kmap_coherent_init();
178 331
179 max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT; 332 max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
180 low = max_low_pfn; 333 low = max_low_pfn;
@@ -290,15 +443,18 @@ void __init mem_init(void)
290} 443}
291#endif /* !CONFIG_NEED_MULTIPLE_NODES */ 444#endif /* !CONFIG_NEED_MULTIPLE_NODES */
292 445
293void free_init_pages(char *what, unsigned long begin, unsigned long end) 446static void free_init_pages(char *what, unsigned long begin, unsigned long end)
294{ 447{
295 unsigned long addr; 448 unsigned long pfn;
449
450 for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
451 struct page *page = pfn_to_page(pfn);
452 void *addr = phys_to_virt(PFN_PHYS(pfn));
296 453
297 for (addr = begin; addr < end; addr += PAGE_SIZE) { 454 ClearPageReserved(page);
298 ClearPageReserved(virt_to_page(addr)); 455 init_page_count(page);
299 init_page_count(virt_to_page(addr)); 456 memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
300 memset((void *)addr, 0xcc, PAGE_SIZE); 457 __free_page(page);
301 free_page(addr);
302 totalram_pages++; 458 totalram_pages++;
303 } 459 }
304 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10); 460 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
@@ -307,12 +463,9 @@ void free_init_pages(char *what, unsigned long begin, unsigned long end)
307#ifdef CONFIG_BLK_DEV_INITRD 463#ifdef CONFIG_BLK_DEV_INITRD
308void free_initrd_mem(unsigned long start, unsigned long end) 464void free_initrd_mem(unsigned long start, unsigned long end)
309{ 465{
310#ifdef CONFIG_64BIT 466 free_init_pages("initrd memory",
311 /* Switch from KSEG0 to XKPHYS addresses */ 467 virt_to_phys((void *)start),
312 start = (unsigned long)phys_to_virt(CPHYSADDR(start)); 468 virt_to_phys((void *)end));
313 end = (unsigned long)phys_to_virt(CPHYSADDR(end));
314#endif
315 free_init_pages("initrd memory", start, end);
316} 469}
317#endif 470#endif
318 471
@@ -320,17 +473,13 @@ extern unsigned long prom_free_prom_memory(void);
320 473
321void free_initmem(void) 474void free_initmem(void)
322{ 475{
323 unsigned long start, end, freed; 476 unsigned long freed;
324 477
325 freed = prom_free_prom_memory(); 478 freed = prom_free_prom_memory();
326 if (freed) 479 if (freed)
327 printk(KERN_INFO "Freeing firmware memory: %ldk freed\n",freed); 480 printk(KERN_INFO "Freeing firmware memory: %ldk freed\n",freed);
328 481
329 start = (unsigned long)(&__init_begin); 482 free_init_pages("unused kernel memory",
330 end = (unsigned long)(&__init_end); 483 __pa_symbol(&__init_begin),
331#ifdef CONFIG_64BIT 484 __pa_symbol(&__init_end));
332 start = PAGE_OFFSET | CPHYSADDR(start);
333 end = PAGE_OFFSET | CPHYSADDR(end);
334#endif
335 free_init_pages("unused kernel memory", start, end);
336} 485}
diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index 3101d1db5592..cea7d0ea36e4 100644
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -176,7 +176,7 @@ void __iomem * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
176 176
177#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) 177#define IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
178 178
179void __iounmap(volatile void __iomem *addr) 179void __iounmap(const volatile void __iomem *addr)
180{ 180{
181 struct vm_struct *p; 181 struct vm_struct *p;
182 182
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index b7c749232ffe..d41fc5885e87 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -270,6 +270,20 @@ static inline void build_addiu_a2_a0(unsigned long offset)
270 emit_instruction(mi); 270 emit_instruction(mi);
271} 271}
272 272
273static inline void build_addiu_a2(unsigned long offset)
274{
275 union mips_instruction mi;
276
277 BUG_ON(offset > 0x7fff);
278
279 mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
280 mi.i_format.rs = 6; /* $a2 */
281 mi.i_format.rt = 6; /* $a2 */
282 mi.i_format.simmediate = offset;
283
284 emit_instruction(mi);
285}
286
273static inline void build_addiu_a1(unsigned long offset) 287static inline void build_addiu_a1(unsigned long offset)
274{ 288{
275 union mips_instruction mi; 289 union mips_instruction mi;
@@ -333,6 +347,7 @@ static inline void build_jr_ra(void)
333void __init build_clear_page(void) 347void __init build_clear_page(void)
334{ 348{
335 unsigned int loop_start; 349 unsigned int loop_start;
350 unsigned long off;
336 351
337 epc = (unsigned int *) &clear_page_array; 352 epc = (unsigned int *) &clear_page_array;
338 instruction_pending = 0; 353 instruction_pending = 0;
@@ -369,7 +384,12 @@ void __init build_clear_page(void)
369 } 384 }
370 } 385 }
371 386
372 build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0)); 387 off = PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0);
388 if (off > 0x7fff) {
389 build_addiu_a2_a0(off >> 1);
390 build_addiu_a2(off >> 1);
391 } else
392 build_addiu_a2_a0(off);
373 393
374 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) 394 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
375 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ 395 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
@@ -420,12 +440,18 @@ dest = label();
420void __init build_copy_page(void) 440void __init build_copy_page(void)
421{ 441{
422 unsigned int loop_start; 442 unsigned int loop_start;
443 unsigned long off;
423 444
424 epc = (unsigned int *) &copy_page_array; 445 epc = (unsigned int *) &copy_page_array;
425 store_offset = load_offset = 0; 446 store_offset = load_offset = 0;
426 instruction_pending = 0; 447 instruction_pending = 0;
427 448
428 build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0)); 449 off = PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0);
450 if (off > 0x7fff) {
451 build_addiu_a2_a0(off >> 1);
452 build_addiu_a2(off >> 1);
453 } else
454 build_addiu_a2_a0(off);
429 455
430 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) 456 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
431 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */ 457 build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
diff --git a/arch/mips/mm/pgtable-32.c b/arch/mips/mm/pgtable-32.c
index 4bdaa05f485b..4a61e624b0ec 100644
--- a/arch/mips/mm/pgtable-32.c
+++ b/arch/mips/mm/pgtable-32.c
@@ -31,9 +31,10 @@ void pgd_init(unsigned long page)
31 31
32void __init pagetable_init(void) 32void __init pagetable_init(void)
33{ 33{
34#ifdef CONFIG_HIGHMEM
35 unsigned long vaddr; 34 unsigned long vaddr;
36 pgd_t *pgd, *pgd_base; 35 pgd_t *pgd_base;
36#ifdef CONFIG_HIGHMEM
37 pgd_t *pgd;
37 pud_t *pud; 38 pud_t *pud;
38 pmd_t *pmd; 39 pmd_t *pmd;
39 pte_t *pte; 40 pte_t *pte;
@@ -44,7 +45,6 @@ void __init pagetable_init(void)
44 pgd_init((unsigned long)swapper_pg_dir 45 pgd_init((unsigned long)swapper_pg_dir
45 + sizeof(pgd_t) * USER_PTRS_PER_PGD); 46 + sizeof(pgd_t) * USER_PTRS_PER_PGD);
46 47
47#ifdef CONFIG_HIGHMEM
48 pgd_base = swapper_pg_dir; 48 pgd_base = swapper_pg_dir;
49 49
50 /* 50 /*
@@ -53,6 +53,7 @@ void __init pagetable_init(void)
53 vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK; 53 vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;
54 fixrange_init(vaddr, 0, pgd_base); 54 fixrange_init(vaddr, 0, pgd_base);
55 55
56#ifdef CONFIG_HIGHMEM
56 /* 57 /*
57 * Permanent kmaps: 58 * Permanent kmaps:
58 */ 59 */
diff --git a/arch/mips/mm/pgtable-64.c b/arch/mips/mm/pgtable-64.c
index 44b5e97fff65..c46eb651bf09 100644
--- a/arch/mips/mm/pgtable-64.c
+++ b/arch/mips/mm/pgtable-64.c
@@ -8,6 +8,7 @@
8 */ 8 */
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/mm.h> 10#include <linux/mm.h>
11#include <asm/fixmap.h>
11#include <asm/pgtable.h> 12#include <asm/pgtable.h>
12 13
13void pgd_init(unsigned long page) 14void pgd_init(unsigned long page)
@@ -52,7 +53,20 @@ void pmd_init(unsigned long addr, unsigned long pagetable)
52 53
53void __init pagetable_init(void) 54void __init pagetable_init(void)
54{ 55{
56 unsigned long vaddr;
57 pgd_t *pgd_base;
58
55 /* Initialize the entire pgd. */ 59 /* Initialize the entire pgd. */
56 pgd_init((unsigned long)swapper_pg_dir); 60 pgd_init((unsigned long)swapper_pg_dir);
61#ifdef MODULE_START
62 pgd_init((unsigned long)module_pg_dir);
63#endif
57 pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table); 64 pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table);
65
66 pgd_base = swapper_pg_dir;
67 /*
68 * Fixed mappings:
69 */
70 vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;
71 fixrange_init(vaddr, 0, pgd_base);
58} 72}
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 6f8b25cfa6f0..492c518e7ba5 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -102,7 +102,7 @@ enum opcode {
102 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, 102 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
103 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 103 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
104 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, 104 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
105 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 105 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32,
106 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, 106 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
107 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, 107 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
108 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, 108 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
@@ -145,6 +145,7 @@ static __initdata struct insn insn_table[] = {
145 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, 145 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE },
146 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, 146 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE },
147 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, 147 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE },
148 { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE },
148 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, 149 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD },
149 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, 150 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 },
150 { insn_j, M(j_op,0,0,0,0,0), JIMM }, 151 { insn_j, M(j_op,0,0,0,0,0), JIMM },
@@ -385,6 +386,7 @@ I_u2u1u3(_dsll);
385I_u2u1u3(_dsll32); 386I_u2u1u3(_dsll32);
386I_u2u1u3(_dsra); 387I_u2u1u3(_dsra);
387I_u2u1u3(_dsrl); 388I_u2u1u3(_dsrl);
389I_u2u1u3(_dsrl32);
388I_u3u1u2(_dsubu); 390I_u3u1u2(_dsubu);
389I_0(_eret); 391I_0(_eret);
390I_u1(_j); 392I_u1(_j);
@@ -421,6 +423,9 @@ enum label_id {
421 label_invalid, 423 label_invalid,
422 label_second_part, 424 label_second_part,
423 label_leave, 425 label_leave,
426#ifdef MODULE_START
427 label_module_alloc,
428#endif
424 label_vmalloc, 429 label_vmalloc,
425 label_vmalloc_done, 430 label_vmalloc_done,
426 label_tlbw_hazard, 431 label_tlbw_hazard,
@@ -453,6 +458,9 @@ static __init void build_label(struct label **lab, u32 *addr,
453 458
454L_LA(_second_part) 459L_LA(_second_part)
455L_LA(_leave) 460L_LA(_leave)
461#ifdef MODULE_START
462L_LA(_module_alloc)
463#endif
456L_LA(_vmalloc) 464L_LA(_vmalloc)
457L_LA(_vmalloc_done) 465L_LA(_vmalloc_done)
458L_LA(_tlbw_hazard) 466L_LA(_tlbw_hazard)
@@ -684,6 +692,13 @@ static void __init il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
684 i_bgezl(p, reg, 0); 692 i_bgezl(p, reg, 0);
685} 693}
686 694
695static void __init __attribute__((unused))
696il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
697{
698 r_mips_pc16(r, *p, l);
699 i_bgez(p, reg, 0);
700}
701
687/* The only general purpose registers allowed in TLB handlers. */ 702/* The only general purpose registers allowed in TLB handlers. */
688#define K0 26 703#define K0 26
689#define K1 27 704#define K1 27
@@ -968,7 +983,11 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
968 * The vmalloc handling is not in the hotpath. 983 * The vmalloc handling is not in the hotpath.
969 */ 984 */
970 i_dmfc0(p, tmp, C0_BADVADDR); 985 i_dmfc0(p, tmp, C0_BADVADDR);
986#ifdef MODULE_START
987 il_bltz(p, r, tmp, label_module_alloc);
988#else
971 il_bltz(p, r, tmp, label_vmalloc); 989 il_bltz(p, r, tmp, label_vmalloc);
990#endif
972 /* No i_nop needed here, since the next insn doesn't touch TMP. */ 991 /* No i_nop needed here, since the next insn doesn't touch TMP. */
973 992
974#ifdef CONFIG_SMP 993#ifdef CONFIG_SMP
@@ -996,7 +1015,12 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
996#endif 1015#endif
997 1016
998 l_vmalloc_done(l, *p); 1017 l_vmalloc_done(l, *p);
999 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */ 1018
1019 if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */
1020 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3);
1021 else
1022 i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32);
1023
1000 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 1024 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
1001 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 1025 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
1002 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 1026 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
@@ -1016,8 +1040,46 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1016{ 1040{
1017 long swpd = (long)swapper_pg_dir; 1041 long swpd = (long)swapper_pg_dir;
1018 1042
1043#ifdef MODULE_START
1044 long modd = (long)module_pg_dir;
1045
1046 l_module_alloc(l, *p);
1047 /*
1048 * Assumption:
1049 * VMALLOC_START >= 0xc000000000000000UL
1050 * MODULE_START >= 0xe000000000000000UL
1051 */
1052 i_SLL(p, ptr, bvaddr, 2);
1053 il_bgez(p, r, ptr, label_vmalloc);
1054
1055 if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START)) {
1056 i_lui(p, ptr, rel_hi(MODULE_START)); /* delay slot */
1057 } else {
1058 /* unlikely configuration */
1059 i_nop(p); /* delay slot */
1060 i_LA(p, ptr, MODULE_START);
1061 }
1062 i_dsubu(p, bvaddr, bvaddr, ptr);
1063
1064 if (in_compat_space_p(modd) && !rel_lo(modd)) {
1065 il_b(p, r, label_vmalloc_done);
1066 i_lui(p, ptr, rel_hi(modd));
1067 } else {
1068 i_LA_mostly(p, ptr, modd);
1069 il_b(p, r, label_vmalloc_done);
1070 i_daddiu(p, ptr, ptr, rel_lo(modd));
1071 }
1072
1073 l_vmalloc(l, *p);
1074 if (in_compat_space_p(MODULE_START) && !rel_lo(MODULE_START) &&
1075 MODULE_START << 32 == VMALLOC_START)
1076 i_dsll32(p, ptr, ptr, 0); /* typical case */
1077 else
1078 i_LA(p, ptr, VMALLOC_START);
1079#else
1019 l_vmalloc(l, *p); 1080 l_vmalloc(l, *p);
1020 i_LA(p, ptr, VMALLOC_START); 1081 i_LA(p, ptr, VMALLOC_START);
1082#endif
1021 i_dsubu(p, bvaddr, bvaddr, ptr); 1083 i_dsubu(p, bvaddr, bvaddr, ptr);
1022 1084
1023 if (in_compat_space_p(swpd) && !rel_lo(swpd)) { 1085 if (in_compat_space_p(swpd) && !rel_lo(swpd)) {
@@ -1073,7 +1135,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1073 1135
1074static __init void build_adjust_context(u32 **p, unsigned int ctx) 1136static __init void build_adjust_context(u32 **p, unsigned int ctx)
1075{ 1137{
1076 unsigned int shift = 4 - (PTE_T_LOG2 + 1); 1138 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
1077 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 1139 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1078 1140
1079 switch (current_cpu_data.cputype) { 1141 switch (current_cpu_data.cputype) {
diff --git a/arch/mips/momentum/ocelot_3/Makefile b/arch/mips/momentum/ocelot_3/Makefile
index 8bcea64dd27b..d5a090a85a15 100644
--- a/arch/mips/momentum/ocelot_3/Makefile
+++ b/arch/mips/momentum/ocelot_3/Makefile
@@ -5,4 +5,4 @@
5# removes any old dependencies. DON'T put your own dependencies here 5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file). 6# unless it's something special (ie not a .c file).
7# 7#
8obj-y += irq.o prom.o reset.o setup.o 8obj-y += irq.o platform.o prom.o reset.o setup.o
diff --git a/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h b/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
index 227e429fe720..5710a9029f1c 100644
--- a/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
+++ b/arch/mips/momentum/ocelot_3/ocelot_3_fpga.h
@@ -51,7 +51,9 @@
51 51
52extern unsigned long ocelot_fpga_base; 52extern unsigned long ocelot_fpga_base;
53 53
54#define OCELOT_FPGA_WRITE(x, y) writeb(x, ocelot_fpga_base + OCELOT_3_REG_##y) 54#define __FPGA_REG_TO_ADDR(reg) \
55#define OCELOT_FPGA_READ(x) readb(ocelot_fpga_base + OCELOT_3_REG_##x) 55 ((void *) ocelot_fpga_base + OCELOT_3_REG_##reg)
56#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
57#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
56 58
57#endif 59#endif
diff --git a/arch/mips/momentum/ocelot_3/platform.c b/arch/mips/momentum/ocelot_3/platform.c
new file mode 100644
index 000000000000..eefe5841fbb2
--- /dev/null
+++ b/arch/mips/momentum/ocelot_3/platform.c
@@ -0,0 +1,235 @@
1#include <linux/delay.h>
2#include <linux/if_ether.h>
3#include <linux/ioport.h>
4#include <linux/mv643xx.h>
5#include <linux/platform_device.h>
6
7#include "ocelot_3_fpga.h"
8
9#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
10
11static struct resource mv643xx_eth_shared_resources[] = {
12 [0] = {
13 .name = "ethernet shared base",
14 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
15 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
16 MV643XX_ETH_SHARED_REGS_SIZE - 1,
17 .flags = IORESOURCE_MEM,
18 },
19};
20
21static struct platform_device mv643xx_eth_shared_device = {
22 .name = MV643XX_ETH_SHARED_NAME,
23 .id = 0,
24 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
25 .resource = mv643xx_eth_shared_resources,
26};
27
28#define MV_SRAM_BASE 0xfe000000UL
29#define MV_SRAM_SIZE (256 * 1024)
30
31#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
32#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
33
34#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
35#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
36
37#define MV64x60_IRQ_ETH_0 48
38#define MV64x60_IRQ_ETH_1 49
39#define MV64x60_IRQ_ETH_2 50
40
41#ifdef CONFIG_MV643XX_ETH_0
42
43static struct resource mv64x60_eth0_resources[] = {
44 [0] = {
45 .name = "eth0 irq",
46 .start = MV64x60_IRQ_ETH_0,
47 .end = MV64x60_IRQ_ETH_0,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52static char eth0_mac_addr[ETH_ALEN];
53
54static struct mv643xx_eth_platform_data eth0_pd = {
55 .mac_addr = eth0_mac_addr,
56
57 .tx_sram_addr = MV_SRAM_BASE_ETH0,
58 .tx_sram_size = MV_SRAM_TXRING_SIZE,
59 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
60
61 .rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
62 .rx_sram_size = MV_SRAM_RXRING_SIZE,
63 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
64};
65
66static struct platform_device eth0_device = {
67 .name = MV643XX_ETH_NAME,
68 .id = 0,
69 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
70 .resource = mv64x60_eth0_resources,
71 .dev = {
72 .platform_data = &eth0_pd,
73 },
74};
75#endif /* CONFIG_MV643XX_ETH_0 */
76
77#ifdef CONFIG_MV643XX_ETH_1
78
79static struct resource mv64x60_eth1_resources[] = {
80 [0] = {
81 .name = "eth1 irq",
82 .start = MV64x60_IRQ_ETH_1,
83 .end = MV64x60_IRQ_ETH_1,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static char eth1_mac_addr[ETH_ALEN];
89
90static struct mv643xx_eth_platform_data eth1_pd = {
91 .mac_addr = eth1_mac_addr,
92
93 .tx_sram_addr = MV_SRAM_BASE_ETH1,
94 .tx_sram_size = MV_SRAM_TXRING_SIZE,
95 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
96
97 .rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
98 .rx_sram_size = MV_SRAM_RXRING_SIZE,
99 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
100};
101
102static struct platform_device eth1_device = {
103 .name = MV643XX_ETH_NAME,
104 .id = 1,
105 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
106 .resource = mv64x60_eth1_resources,
107 .dev = {
108 .platform_data = &eth1_pd,
109 },
110};
111#endif /* CONFIG_MV643XX_ETH_1 */
112
113#ifdef CONFIG_MV643XX_ETH_2
114
115static struct resource mv64x60_eth2_resources[] = {
116 [0] = {
117 .name = "eth2 irq",
118 .start = MV64x60_IRQ_ETH_2,
119 .end = MV64x60_IRQ_ETH_2,
120 .flags = IORESOURCE_IRQ,
121 },
122};
123
124static char eth2_mac_addr[ETH_ALEN];
125
126static struct mv643xx_eth_platform_data eth2_pd = {
127 .mac_addr = eth2_mac_addr,
128};
129
130static struct platform_device eth2_device = {
131 .name = MV643XX_ETH_NAME,
132 .id = 1,
133 .num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
134 .resource = mv64x60_eth2_resources,
135 .dev = {
136 .platform_data = &eth2_pd,
137 },
138};
139#endif /* CONFIG_MV643XX_ETH_2 */
140
141static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
142 &mv643xx_eth_shared_device,
143#ifdef CONFIG_MV643XX_ETH_0
144 &eth0_device,
145#endif
146#ifdef CONFIG_MV643XX_ETH_1
147 &eth1_device,
148#endif
149#ifdef CONFIG_MV643XX_ETH_2
150 &eth2_device,
151#endif
152};
153
154static u8 __init exchange_bit(u8 val, u8 cs)
155{
156 /* place the data */
157 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
158 udelay(1);
159
160 /* turn the clock on */
161 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
162 udelay(1);
163
164 /* turn the clock off and read-strobe */
165 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
166
167 /* return the data */
168 return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
169}
170
171static void __init get_mac(char dest[6])
172{
173 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
174 int i,j;
175
176 for (i = 0; i < 12; i++)
177 exchange_bit(read_opcode[i], 1);
178
179 for (j = 0; j < 6; j++) {
180 dest[j] = 0;
181 for (i = 0; i < 8; i++) {
182 dest[j] <<= 1;
183 dest[j] |= exchange_bit(0, 1);
184 }
185 }
186
187 /* turn off CS */
188 exchange_bit(0,0);
189}
190
191/*
192 * Copy and increment ethernet MAC address by a small value.
193 *
194 * This is useful for systems where the only one MAC address is stored in
195 * non-volatile memory for multiple ports.
196 */
197static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
198 unsigned int add)
199{
200 int i;
201
202 BUG_ON(add >= 256);
203
204 for (i = ETH_ALEN; i >= 0; i--) {
205 dst[i] = src[i] + add;
206 add = dst[i] < src[i]; /* compute carry */
207 }
208
209 WARN_ON(add);
210}
211
212static int __init mv643xx_eth_add_pds(void)
213{
214 unsigned char mac[ETH_ALEN];
215 int ret;
216
217 get_mac(mac);
218#ifdef CONFIG_MV643XX_ETH_0
219 eth_mac_add(eth1_mac_addr, mac, 0);
220#endif
221#ifdef CONFIG_MV643XX_ETH_1
222 eth_mac_add(eth1_mac_addr, mac, 1);
223#endif
224#ifdef CONFIG_MV643XX_ETH_2
225 eth_mac_add(eth2_mac_addr, mac, 2);
226#endif
227 ret = platform_add_devices(mv643xx_eth_pd_devs,
228 ARRAY_SIZE(mv643xx_eth_pd_devs));
229
230 return ret;
231}
232
233device_initcall(mv643xx_eth_add_pds);
234
235#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
diff --git a/arch/mips/momentum/ocelot_3/prom.c b/arch/mips/momentum/ocelot_3/prom.c
index 296d945bc248..6ce9b7fdb824 100644
--- a/arch/mips/momentum/ocelot_3/prom.c
+++ b/arch/mips/momentum/ocelot_3/prom.c
@@ -34,64 +34,11 @@ struct callvectors* debug_vectors;
34extern unsigned long marvell_base; 34extern unsigned long marvell_base;
35extern unsigned long cpu_clock; 35extern unsigned long cpu_clock;
36 36
37#ifdef CONFIG_MV643XX_ETH
38extern unsigned char prom_mac_addr_base[6];
39#endif
40
41const char *get_system_type(void) 37const char *get_system_type(void)
42{ 38{
43 return "Momentum Ocelot-3"; 39 return "Momentum Ocelot-3";
44} 40}
45 41
46#ifdef CONFIG_MV643XX_ETH
47void burn_clocks(void)
48{
49 int i;
50
51 /* this loop should burn at least 1us -- this should be plenty */
52 for (i = 0; i < 0x10000; i++)
53 ;
54}
55
56u8 exchange_bit(u8 val, u8 cs)
57{
58 /* place the data */
59 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
60 burn_clocks();
61
62 /* turn the clock on */
63 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
64 burn_clocks();
65
66 /* turn the clock off and read-strobe */
67 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
68
69 /* return the data */
70 return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
71}
72
73void get_mac(char dest[6])
74{
75 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
76 int i,j;
77
78 for (i = 0; i < 12; i++)
79 exchange_bit(read_opcode[i], 1);
80
81 for (j = 0; j < 6; j++) {
82 dest[j] = 0;
83 for (i = 0; i < 8; i++) {
84 dest[j] <<= 1;
85 dest[j] |= exchange_bit(0, 1);
86 }
87 }
88
89 /* turn off CS */
90 exchange_bit(0,0);
91}
92#endif
93
94
95#ifdef CONFIG_64BIT 42#ifdef CONFIG_64BIT
96 43
97unsigned long signext(unsigned long addr) 44unsigned long signext(unsigned long addr)
@@ -228,11 +175,6 @@ void __init prom_init(void)
228 mips_machgroup = MACH_GROUP_MOMENCO; 175 mips_machgroup = MACH_GROUP_MOMENCO;
229 mips_machtype = MACH_MOMENCO_OCELOT_3; 176 mips_machtype = MACH_MOMENCO_OCELOT_3;
230 177
231#ifdef CONFIG_MV643XX_ETH
232 /* get the base MAC address for on-board ethernet ports */
233 get_mac(prom_mac_addr_base);
234#endif
235
236#ifndef CONFIG_64BIT 178#ifndef CONFIG_64BIT
237 debug_vectors->printf("Booting Linux kernel...\n"); 179 debug_vectors->printf("Booting Linux kernel...\n");
238#endif 180#endif
diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c
index 7d74f8c54129..ff0829f81116 100644
--- a/arch/mips/momentum/ocelot_3/setup.c
+++ b/arch/mips/momentum/ocelot_3/setup.c
@@ -4,7 +4,7 @@
4 * BRIEF MODULE DESCRIPTION 4 * BRIEF MODULE DESCRIPTION
5 * Momentum Computer Ocelot-3 board dependent boot routines 5 * Momentum Computer Ocelot-3 board dependent boot routines
6 * 6 *
7 * Copyright (C) 1996, 1997, 01, 05 Ralf Baechle 7 * Copyright (C) 1996, 1997, 01, 05 - 06 Ralf Baechle
8 * Copyright (C) 2000 RidgeRun, Inc. 8 * Copyright (C) 2000 RidgeRun, Inc.
9 * Copyright (C) 2001 Red Hat, Inc. 9 * Copyright (C) 2001 Red Hat, Inc.
10 * Copyright (C) 2002 Momentum Computer 10 * Copyright (C) 2002 Momentum Computer
diff --git a/arch/mips/momentum/ocelot_c/Makefile b/arch/mips/momentum/ocelot_c/Makefile
index 94802b4db472..d69161aa1675 100644
--- a/arch/mips/momentum/ocelot_c/Makefile
+++ b/arch/mips/momentum/ocelot_c/Makefile
@@ -2,7 +2,7 @@
2# Makefile for Momentum Computer's Ocelot-C and -CS boards. 2# Makefile for Momentum Computer's Ocelot-C and -CS boards.
3# 3#
4 4
5obj-y += cpci-irq.o irq.o prom.o reset.o \ 5obj-y += cpci-irq.o irq.o platform.o prom.o reset.o \
6 setup.o uart-irq.o 6 setup.o uart-irq.o
7 7
8obj-$(CONFIG_KGDB) += dbg_io.o 8obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index 47e3fa32b075..e5a4a0a8a7f0 100644
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -66,39 +66,6 @@ static inline void unmask_cpci_irq(unsigned int irq)
66} 66}
67 67
68/* 68/*
69 * Enables the IRQ in the FPGA
70 */
71static void enable_cpci_irq(unsigned int irq)
72{
73 unmask_cpci_irq(irq);
74}
75
76/*
77 * Initialize the IRQ in the FPGA
78 */
79static unsigned int startup_cpci_irq(unsigned int irq)
80{
81 unmask_cpci_irq(irq);
82 return 0;
83}
84
85/*
86 * Disables the IRQ in the FPGA
87 */
88static void disable_cpci_irq(unsigned int irq)
89{
90 mask_cpci_irq(irq);
91}
92
93/*
94 * Masks and ACKs an IRQ
95 */
96static void mask_and_ack_cpci_irq(unsigned int irq)
97{
98 mask_cpci_irq(irq);
99}
100
101/*
102 * End IRQ processing 69 * End IRQ processing
103 */ 70 */
104static void end_cpci_irq(unsigned int irq) 71static void end_cpci_irq(unsigned int irq)
@@ -125,15 +92,12 @@ void ll_cpci_irq(void)
125 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE); 92 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
126} 93}
127 94
128#define shutdown_cpci_irq disable_cpci_irq
129
130struct irq_chip cpci_irq_type = { 95struct irq_chip cpci_irq_type = {
131 .typename = "CPCI/FPGA", 96 .typename = "CPCI/FPGA",
132 .startup = startup_cpci_irq, 97 .ack = mask_cpci_irq,
133 .shutdown = shutdown_cpci_irq, 98 .mask = mask_cpci_irq,
134 .enable = enable_cpci_irq, 99 .mask_ack = mask_cpci_irq,
135 .disable = disable_cpci_irq, 100 .unmask = unmask_cpci_irq,
136 .ack = mask_and_ack_cpci_irq,
137 .end = end_cpci_irq, 101 .end = end_cpci_irq,
138}; 102};
139 103
@@ -141,11 +105,6 @@ void cpci_irq_init(void)
141{ 105{
142 int i; 106 int i;
143 107
144 /* Reset irq handlers pointers to NULL */ 108 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
145 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) { 109 set_irq_chip_and_handler(i, &cpci_irq_type, handle_level_irq);
146 irq_desc[i].status = IRQ_DISABLED;
147 irq_desc[i].action = 0;
148 irq_desc[i].depth = 2;
149 irq_desc[i].chip = &cpci_irq_type;
150 }
151} 110}
diff --git a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
index 7228cd19e5ea..f0f5581dcb50 100644
--- a/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
+++ b/arch/mips/momentum/ocelot_c/ocelot_c_fpga.h
@@ -53,7 +53,9 @@
53#define OCELOT_C_REG_INTSET 0xe 53#define OCELOT_C_REG_INTSET 0xe
54#define OCELOT_C_REG_INTCLR 0xf 54#define OCELOT_C_REG_INTCLR 0xf
55 55
56#define OCELOT_FPGA_WRITE(x, y) writeb(x, OCELOT_C_CS0_ADDR + OCELOT_C_REG_##y) 56#define __FPGA_REG_TO_ADDR(reg) \
57#define OCELOT_FPGA_READ(x) readb(OCELOT_C_CS0_ADDR + OCELOT_C_REG_##x) 57 ((void *) OCELOT_C_CS0_ADDR + OCELOT_C_REG_##reg)
58#define OCELOT_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
59#define OCELOT_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
58 60
59#endif 61#endif
diff --git a/arch/mips/momentum/ocelot_c/platform.c b/arch/mips/momentum/ocelot_c/platform.c
new file mode 100644
index 000000000000..6c495b2f1560
--- /dev/null
+++ b/arch/mips/momentum/ocelot_c/platform.c
@@ -0,0 +1,201 @@
1#include <linux/delay.h>
2#include <linux/if_ether.h>
3#include <linux/ioport.h>
4#include <linux/mv643xx.h>
5#include <linux/platform_device.h>
6
7#include "ocelot_c_fpga.h"
8
9#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
10
11static struct resource mv643xx_eth_shared_resources[] = {
12 [0] = {
13 .name = "ethernet shared base",
14 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
15 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
16 MV643XX_ETH_SHARED_REGS_SIZE - 1,
17 .flags = IORESOURCE_MEM,
18 },
19};
20
21static struct platform_device mv643xx_eth_shared_device = {
22 .name = MV643XX_ETH_SHARED_NAME,
23 .id = 0,
24 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
25 .resource = mv643xx_eth_shared_resources,
26};
27
28#define MV_SRAM_BASE 0xfe000000UL
29#define MV_SRAM_SIZE (256 * 1024)
30
31#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
32#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
33
34#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
35#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
36
37#define MV64x60_IRQ_ETH_0 48
38#define MV64x60_IRQ_ETH_1 49
39
40#ifdef CONFIG_MV643XX_ETH_0
41
42static struct resource mv64x60_eth0_resources[] = {
43 [0] = {
44 .name = "eth0 irq",
45 .start = MV64x60_IRQ_ETH_0,
46 .end = MV64x60_IRQ_ETH_0,
47 .flags = IORESOURCE_IRQ,
48 },
49};
50
51static char eth0_mac_addr[ETH_ALEN];
52
53static struct mv643xx_eth_platform_data eth0_pd = {
54 .mac_addr = eth0_mac_addr,
55
56 .tx_sram_addr = MV_SRAM_BASE_ETH0,
57 .tx_sram_size = MV_SRAM_TXRING_SIZE,
58 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
59
60 .rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
61 .rx_sram_size = MV_SRAM_RXRING_SIZE,
62 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
63};
64
65static struct platform_device eth0_device = {
66 .name = MV643XX_ETH_NAME,
67 .id = 0,
68 .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
69 .resource = mv64x60_eth0_resources,
70 .dev = {
71 .platform_data = &eth0_pd,
72 },
73};
74#endif /* CONFIG_MV643XX_ETH_0 */
75
76#ifdef CONFIG_MV643XX_ETH_1
77
78static struct resource mv64x60_eth1_resources[] = {
79 [0] = {
80 .name = "eth1 irq",
81 .start = MV64x60_IRQ_ETH_1,
82 .end = MV64x60_IRQ_ETH_1,
83 .flags = IORESOURCE_IRQ,
84 },
85};
86
87static char eth1_mac_addr[ETH_ALEN];
88
89static struct mv643xx_eth_platform_data eth1_pd = {
90 .mac_addr = eth1_mac_addr,
91
92 .tx_sram_addr = MV_SRAM_BASE_ETH1,
93 .tx_sram_size = MV_SRAM_TXRING_SIZE,
94 .tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
95
96 .rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
97 .rx_sram_size = MV_SRAM_RXRING_SIZE,
98 .rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
99};
100
101static struct platform_device eth1_device = {
102 .name = MV643XX_ETH_NAME,
103 .id = 1,
104 .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
105 .resource = mv64x60_eth1_resources,
106 .dev = {
107 .platform_data = &eth1_pd,
108 },
109};
110#endif /* CONFIG_MV643XX_ETH_1 */
111
112static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
113 &mv643xx_eth_shared_device,
114#ifdef CONFIG_MV643XX_ETH_0
115 &eth0_device,
116#endif
117#ifdef CONFIG_MV643XX_ETH_1
118 &eth1_device,
119#endif
120 /* The third port is not wired up on the Ocelot C */
121};
122
123static u8 __init exchange_bit(u8 val, u8 cs)
124{
125 /* place the data */
126 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
127 udelay(1);
128
129 /* turn the clock on */
130 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
131 udelay(1);
132
133 /* turn the clock off and read-strobe */
134 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
135
136 /* return the data */
137 return (OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
138}
139
140static void __init get_mac(char dest[6])
141{
142 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
143 int i,j;
144
145 for (i = 0; i < 12; i++)
146 exchange_bit(read_opcode[i], 1);
147
148 for (j = 0; j < 6; j++) {
149 dest[j] = 0;
150 for (i = 0; i < 8; i++) {
151 dest[j] <<= 1;
152 dest[j] |= exchange_bit(0, 1);
153 }
154 }
155
156 /* turn off CS */
157 exchange_bit(0,0);
158}
159
160/*
161 * Copy and increment ethernet MAC address by a small value.
162 *
163 * This is useful for systems where the only one MAC address is stored in
164 * non-volatile memory for multiple ports.
165 */
166static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
167 unsigned int add)
168{
169 int i;
170
171 BUG_ON(add >= 256);
172
173 for (i = ETH_ALEN; i >= 0; i--) {
174 dst[i] = src[i] + add;
175 add = dst[i] < src[i]; /* compute carry */
176 }
177
178 WARN_ON(add);
179}
180
181static int __init mv643xx_eth_add_pds(void)
182{
183 unsigned char mac[ETH_ALEN];
184 int ret;
185
186 get_mac(mac);
187#ifdef CONFIG_MV643XX_ETH_0
188 eth_mac_add(eth1_mac_addr, mac, 0);
189#endif
190#ifdef CONFIG_MV643XX_ETH_1
191 eth_mac_add(eth1_mac_addr, mac, 1);
192#endif
193 ret = platform_add_devices(mv643xx_eth_pd_devs,
194 ARRAY_SIZE(mv643xx_eth_pd_devs));
195
196 return ret;
197}
198
199device_initcall(mv643xx_eth_add_pds);
200
201#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
diff --git a/arch/mips/momentum/ocelot_c/prom.c b/arch/mips/momentum/ocelot_c/prom.c
index 4c50a147f429..d0b77e101d74 100644
--- a/arch/mips/momentum/ocelot_c/prom.c
+++ b/arch/mips/momentum/ocelot_c/prom.c
@@ -29,11 +29,7 @@
29struct callvectors* debug_vectors; 29struct callvectors* debug_vectors;
30 30
31extern unsigned long marvell_base; 31extern unsigned long marvell_base;
32extern unsigned long cpu_clock; 32extern unsigned int cpu_clock;
33
34#ifdef CONFIG_MV643XX_ETH
35extern unsigned char prom_mac_addr_base[6];
36#endif
37 33
38const char *get_system_type(void) 34const char *get_system_type(void)
39{ 35{
@@ -44,55 +40,6 @@ const char *get_system_type(void)
44#endif 40#endif
45} 41}
46 42
47#ifdef CONFIG_MV643XX_ETH
48static void burn_clocks(void)
49{
50 int i;
51
52 /* this loop should burn at least 1us -- this should be plenty */
53 for (i = 0; i < 0x10000; i++)
54 ;
55}
56
57static u8 exchange_bit(u8 val, u8 cs)
58{
59 /* place the data */
60 OCELOT_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
61 burn_clocks();
62
63 /* turn the clock on */
64 OCELOT_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
65 burn_clocks();
66
67 /* turn the clock off and read-strobe */
68 OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
69
70 /* return the data */
71 return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
72}
73
74void get_mac(char dest[6])
75{
76 u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
77 int i,j;
78
79 for (i = 0; i < 12; i++)
80 exchange_bit(read_opcode[i], 1);
81
82 for (j = 0; j < 6; j++) {
83 dest[j] = 0;
84 for (i = 0; i < 8; i++) {
85 dest[j] <<= 1;
86 dest[j] |= exchange_bit(0, 1);
87 }
88 }
89
90 /* turn off CS */
91 exchange_bit(0,0);
92}
93#endif
94
95
96#ifdef CONFIG_64BIT 43#ifdef CONFIG_64BIT
97 44
98unsigned long signext(unsigned long addr) 45unsigned long signext(unsigned long addr)
@@ -226,11 +173,6 @@ void __init prom_init(void)
226 mips_machgroup = MACH_GROUP_MOMENCO; 173 mips_machgroup = MACH_GROUP_MOMENCO;
227 mips_machtype = MACH_MOMENCO_OCELOT_C; 174 mips_machtype = MACH_MOMENCO_OCELOT_C;
228 175
229#ifdef CONFIG_MV643XX_ETH
230 /* get the base MAC address for on-board ethernet ports */
231 get_mac(prom_mac_addr_base);
232#endif
233
234#ifndef CONFIG_64BIT 176#ifndef CONFIG_64BIT
235 debug_vectors->printf("Booting Linux kernel...\n"); 177 debug_vectors->printf("Booting Linux kernel...\n");
236#endif 178#endif
diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c
index 9c0c462af650..0b6b2338cfb4 100644
--- a/arch/mips/momentum/ocelot_c/setup.c
+++ b/arch/mips/momentum/ocelot_c/setup.c
@@ -69,8 +69,7 @@
69#include "ocelot_c_fpga.h" 69#include "ocelot_c_fpga.h"
70 70
71unsigned long marvell_base; 71unsigned long marvell_base;
72extern unsigned long mv64340_sram_base; 72unsigned int cpu_clock;
73unsigned long cpu_clock;
74 73
75/* These functions are used for rebooting or halting the machine*/ 74/* These functions are used for rebooting or halting the machine*/
76extern void momenco_ocelot_restart(char *command); 75extern void momenco_ocelot_restart(char *command);
@@ -119,7 +118,6 @@ void PMON_v2_setup(void)
119 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M); 118 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfffffffffe000000, PM_16M);
120 119
121 marvell_base = 0xfffffffff4000000; 120 marvell_base = 0xfffffffff4000000;
122 mv64340_sram_base = 0xfffffffffe000000;
123#else 121#else
124 /* marvell and extra space */ 122 /* marvell and extra space */
125 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K); 123 add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), 0xf4000000, PM_64K);
@@ -129,7 +127,6 @@ void PMON_v2_setup(void)
129 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M); 127 add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000), 0xfe000000, PM_16M);
130 128
131 marvell_base = 0xf4000000; 129 marvell_base = 0xf4000000;
132 mv64340_sram_base = 0xfe000000;
133#endif 130#endif
134} 131}
135 132
@@ -346,22 +343,20 @@ void __init plat_mem_setup(void)
346 } 343 }
347} 344}
348 345
349#ifndef CONFIG_64BIT 346/*
350/* This needs to be one of the first initcalls, because no I/O port access 347 * This needs to be one of the first initcalls, because no I/O port access
351 can work before this */ 348 * can work before this
349 */
352static int io_base_ioremap(void) 350static int io_base_ioremap(void)
353{ 351{
354 /* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */ 352 void __iomem * io_remap_range = ioremap(0xc0000000UL, 0x10000);
355 void *io_remap_range = ioremap(0xc0000000, 0x30000000);
356 353
357 if (!io_remap_range) { 354 if (!io_remap_range)
358 panic("Could not ioremap I/O port range"); 355 panic("Could not ioremap I/O port range");
359 } 356
360 printk("io_remap_range set at 0x%08x\n", (uint32_t)io_remap_range); 357 set_io_port_base((unsigned long) io_remap_range);
361 set_io_port_base(io_remap_range - 0xc0000000);
362 358
363 return 0; 359 return 0;
364} 360}
365 361
366module_init(io_base_ioremap); 362module_init(io_base_ioremap);
367#endif
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index 510257dc205a..0029f0008dea 100644
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -60,39 +60,6 @@ static inline void unmask_uart_irq(unsigned int irq)
60} 60}
61 61
62/* 62/*
63 * Enables the IRQ in the FPGA
64 */
65static void enable_uart_irq(unsigned int irq)
66{
67 unmask_uart_irq(irq);
68}
69
70/*
71 * Initialize the IRQ in the FPGA
72 */
73static unsigned int startup_uart_irq(unsigned int irq)
74{
75 unmask_uart_irq(irq);
76 return 0;
77}
78
79/*
80 * Disables the IRQ in the FPGA
81 */
82static void disable_uart_irq(unsigned int irq)
83{
84 mask_uart_irq(irq);
85}
86
87/*
88 * Masks and ACKs an IRQ
89 */
90static void mask_and_ack_uart_irq(unsigned int irq)
91{
92 mask_uart_irq(irq);
93}
94
95/*
96 * End IRQ processing 63 * End IRQ processing
97 */ 64 */
98static void end_uart_irq(unsigned int irq) 65static void end_uart_irq(unsigned int irq)
@@ -118,28 +85,17 @@ void ll_uart_irq(void)
118 do_IRQ(ls1bit8(irq_src) + 74); 85 do_IRQ(ls1bit8(irq_src) + 74);
119} 86}
120 87
121#define shutdown_uart_irq disable_uart_irq
122
123struct irq_chip uart_irq_type = { 88struct irq_chip uart_irq_type = {
124 .typename = "UART/FPGA", 89 .typename = "UART/FPGA",
125 .startup = startup_uart_irq, 90 .ack = mask_uart_irq,
126 .shutdown = shutdown_uart_irq, 91 .mask = mask_uart_irq,
127 .enable = enable_uart_irq, 92 .mask_ack = mask_uart_irq,
128 .disable = disable_uart_irq, 93 .unmask = unmask_uart_irq,
129 .ack = mask_and_ack_uart_irq,
130 .end = end_uart_irq, 94 .end = end_uart_irq,
131}; 95};
132 96
133void uart_irq_init(void) 97void uart_irq_init(void)
134{ 98{
135 /* Reset irq handlers pointers to NULL */ 99 set_irq_chip_and_handler(80, &uart_irq_type, handle_level_irq);
136 irq_desc[80].status = IRQ_DISABLED; 100 set_irq_chip_and_handler(81, &uart_irq_type, handle_level_irq);
137 irq_desc[80].action = 0;
138 irq_desc[80].depth = 2;
139 irq_desc[80].chip = &uart_irq_type;
140
141 irq_desc[81].status = IRQ_DISABLED;
142 irq_desc[81].action = 0;
143 irq_desc[81].depth = 2;
144 irq_desc[81].chip = &uart_irq_type;
145} 101}
diff --git a/arch/mips/momentum/ocelot_g/gt-irq.c b/arch/mips/momentum/ocelot_g/gt-irq.c
index 7b5cc6648f7e..e5576bd50fa9 100644
--- a/arch/mips/momentum/ocelot_g/gt-irq.c
+++ b/arch/mips/momentum/ocelot_g/gt-irq.c
@@ -27,7 +27,7 @@ unsigned long bus_clock;
27 * be handled and ack'ed differently than other MIPS interrupts. 27 * be handled and ack'ed differently than other MIPS interrupts.
28 */ 28 */
29 29
30#if CURRENTLY_UNUSED 30#if 0
31 31
32struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH]; 32struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH];
33void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr); 33void hook_irq_handler(int int_cause, int bit_num, void *isr_ptr);
@@ -95,7 +95,7 @@ int disable_galileo_irq(int int_cause, int bit_num)
95 return 0; 95 return 0;
96 return 1; 96 return 1;
97} 97}
98#endif /* UNUSED */ 98#endif /* 0 */
99 99
100/* 100/*
101 * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#. 101 * Interrupt handler for interrupts coming from the Galileo chip via P0_INT#.
@@ -196,7 +196,7 @@ void gt64240_time_init(void)
196 196
197void gt64240_irq_init(void) 197void gt64240_irq_init(void)
198{ 198{
199#if CURRENTLY_UNUSED 199#if 0
200 int i, j; 200 int i, j;
201 201
202 /* Reset irq handlers pointers to NULL */ 202 /* Reset irq handlers pointers to NULL */
@@ -208,5 +208,5 @@ void gt64240_irq_init(void)
208 irq_handlers[i][j].data = NULL; 208 irq_handlers[i][j].data = NULL;
209 } 209 }
210 } 210 }
211#endif 211#endif /* 0 */
212} 212}
diff --git a/arch/mips/momentum/ocelot_g/ocelot_pld.h b/arch/mips/momentum/ocelot_g/ocelot_pld.h
index fcb8275e219d..95e0534026d0 100644
--- a/arch/mips/momentum/ocelot_g/ocelot_pld.h
+++ b/arch/mips/momentum/ocelot_g/ocelot_pld.h
@@ -23,8 +23,8 @@
23#define OCELOT_REG_INTSET (12) 23#define OCELOT_REG_INTSET (12)
24#define OCELOT_REG_INTCLR (13) 24#define OCELOT_REG_INTCLR (13)
25 25
26#define OCELOT_PLD_WRITE(x, y) writeb(x, OCELOT_CS0_ADDR + OCELOT_REG_##y) 26#define __PLD_REG_TO_ADDR(reg) ((void *) OCELOT_CS0_ADDR + OCELOT_REG_##reg)
27#define OCELOT_PLD_READ(x) readb(OCELOT_CS0_ADDR + OCELOT_REG_##x) 27#define OCELOT_PLD_WRITE(x, reg) writeb(x, __PLD_REG_TO_ADDR(reg))
28 28#define OCELOT_PLD_READ(reg) readb(__PLD_REG_TO_ADDR(reg))
29 29
30#endif /* __MOMENCO_OCELOT_PLD_H__ */ 30#endif /* __MOMENCO_OCELOT_PLD_H__ */
diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c
index 56ec47039c16..d288f7b01842 100644
--- a/arch/mips/momentum/ocelot_g/setup.c
+++ b/arch/mips/momentum/ocelot_g/setup.c
@@ -57,6 +57,7 @@
57#include <asm/gt64240.h> 57#include <asm/gt64240.h>
58#include <asm/irq.h> 58#include <asm/irq.h>
59#include <asm/pci.h> 59#include <asm/pci.h>
60#include <asm/pgtable.h>
60#include <asm/processor.h> 61#include <asm/processor.h>
61#include <asm/reboot.h> 62#include <asm/reboot.h>
62#include <linux/bootmem.h> 63#include <linux/bootmem.h>
@@ -160,6 +161,10 @@ static void __init setup_l3cache(unsigned long size)
160 printk("Done\n"); 161 printk("Done\n");
161} 162}
162 163
164void __init plat_timer_setup(struct irqaction *irq)
165{
166}
167
163void __init plat_mem_setup(void) 168void __init plat_mem_setup(void)
164{ 169{
165 void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache); 170 void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 0a50aad5bbe4..bf3be6fcf7ff 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -12,5 +12,6 @@ oprofile-y := $(DRIVER_OBJS) common.o
12 12
13oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o 13oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o
14oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o 14oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o
15oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o
15oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o 16oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o
16oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o 17oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 65eb55400d77..4e0a90b3916b 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -83,6 +83,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
83 case CPU_74K: 83 case CPU_74K:
84 case CPU_SB1: 84 case CPU_SB1:
85 case CPU_SB1A: 85 case CPU_SB1A:
86 case CPU_R10000:
87 case CPU_R12000:
88 case CPU_R14000:
86 lmodel = &op_model_mipsxx_ops; 89 lmodel = &op_model_mipsxx_ops;
87 break; 90 break;
88 91
diff --git a/arch/mips/oprofile/op_impl.h b/arch/mips/oprofile/op_impl.h
index 354e54496406..fa6b4aae7523 100644
--- a/arch/mips/oprofile/op_impl.h
+++ b/arch/mips/oprofile/op_impl.h
@@ -10,8 +10,6 @@
10#ifndef OP_IMPL_H 10#ifndef OP_IMPL_H
11#define OP_IMPL_H 1 11#define OP_IMPL_H 1
12 12
13struct pt_regs;
14
15extern int null_perf_irq(void); 13extern int null_perf_irq(void);
16extern int (*perf_irq)(void); 14extern int (*perf_irq)(void);
17 15
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index dd0aec9c3ce1..455d76ad06d8 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -18,7 +18,7 @@
18#define M_PERFCTL_SUPERVISOR (1UL << 2) 18#define M_PERFCTL_SUPERVISOR (1UL << 2)
19#define M_PERFCTL_USER (1UL << 3) 19#define M_PERFCTL_USER (1UL << 3)
20#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) 20#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
21#define M_PERFCTL_EVENT(event) ((event) << 5) 21#define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5)
22#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) 22#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
23#define M_PERFCTL_MT_EN(filter) ((filter) << 20) 23#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
24#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) 24#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
@@ -31,16 +31,18 @@
31#define M_COUNTER_OVERFLOW (1UL << 31) 31#define M_COUNTER_OVERFLOW (1UL << 31)
32 32
33#ifdef CONFIG_MIPS_MT_SMP 33#ifdef CONFIG_MIPS_MT_SMP
34#define WHAT (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id())) 34#define WHAT (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id()))
35#define vpe_id() smp_processor_id()
35#else 36#else
36#define WHAT 0 37#define WHAT 0
38#define vpe_id() smp_processor_id()
37#endif 39#endif
38 40
39#define __define_perf_accessors(r, n, np) \ 41#define __define_perf_accessors(r, n, np) \
40 \ 42 \
41static inline unsigned int r_c0_ ## r ## n(void) \ 43static inline unsigned int r_c0_ ## r ## n(void) \
42{ \ 44{ \
43 unsigned int cpu = smp_processor_id(); \ 45 unsigned int cpu = vpe_id(); \
44 \ 46 \
45 switch (cpu) { \ 47 switch (cpu) { \
46 case 0: \ 48 case 0: \
@@ -55,7 +57,7 @@ static inline unsigned int r_c0_ ## r ## n(void) \
55 \ 57 \
56static inline void w_c0_ ## r ## n(unsigned int value) \ 58static inline void w_c0_ ## r ## n(unsigned int value) \
57{ \ 59{ \
58 unsigned int cpu = smp_processor_id(); \ 60 unsigned int cpu = vpe_id(); \
59 \ 61 \
60 switch (cpu) { \ 62 switch (cpu) { \
61 case 0: \ 63 case 0: \
@@ -216,13 +218,23 @@ static inline int __n_counters(void)
216 218
217static inline int n_counters(void) 219static inline int n_counters(void)
218{ 220{
219 int counters = __n_counters(); 221 int counters;
220 222
221#ifndef CONFIG_SMP 223 switch (current_cpu_data.cputype) {
222 if (current_cpu_data.cputype == CPU_34K) 224 case CPU_R10000:
223 return counters >> 1; 225 counters = 2;
224#endif 226
227 case CPU_R12000:
228 case CPU_R14000:
229 counters = 4;
230
231 default:
232 counters = __n_counters();
233 }
225 234
235#ifdef CONFIG_MIPS_MT_SMP
236 counters >> 1;
237#endif
226 return counters; 238 return counters;
227} 239}
228 240
@@ -282,6 +294,18 @@ static int __init mipsxx_init(void)
282 op_model_mipsxx_ops.cpu_type = "mips/5K"; 294 op_model_mipsxx_ops.cpu_type = "mips/5K";
283 break; 295 break;
284 296
297 case CPU_R10000:
298 if ((current_cpu_data.processor_id & 0xff) == 0x20)
299 op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
300 else
301 op_model_mipsxx_ops.cpu_type = "mips/r10000";
302 break;
303
304 case CPU_R12000:
305 case CPU_R14000:
306 op_model_mipsxx_ops.cpu_type = "mips/r12000";
307 break;
308
285 case CPU_SB1: 309 case CPU_SB1:
286 case CPU_SB1A: 310 case CPU_SB1A:
287 op_model_mipsxx_ops.cpu_type = "mips/sb1"; 311 op_model_mipsxx_ops.cpu_type = "mips/sb1";
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
index b7063fefa65b..7dc9bf6f1321 100644
--- a/arch/mips/oprofile/op_model_rm9000.c
+++ b/arch/mips/oprofile/op_model_rm9000.c
@@ -80,8 +80,7 @@ static void rm9000_cpu_stop(void *args)
80 write_c0_perfcontrol(0); 80 write_c0_perfcontrol(0);
81} 81}
82 82
83static irqreturn_t rm9000_perfcount_handler(int irq, void * dev_id, 83static irqreturn_t rm9000_perfcount_handler(int irq, void * dev_id)
84 struct pt_regs *regs)
85{ 84{
86 unsigned int control = read_c0_perfcontrol(); 85 unsigned int control = read_c0_perfcontrol();
87 uint32_t counter1, counter2; 86 uint32_t counter1, counter2;
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 3cf0dd4ba548..70cb55b89df6 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
26obj-$(CONFIG_LASAT) += pci-lasat.o 26obj-$(CONFIG_LASAT) += pci-lasat.o
27obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o 27obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
28obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 28obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
29obj-$(CONFIG_MIPS_EV64120) += fixup-ev64120.o 29obj-$(CONFIG_MIPS_EV64120) += pci-ev64120.o
30obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 30obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
31obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 31obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
32obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 32obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 75a01e764898..7d5f6bbf7a9d 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -94,22 +94,21 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
94#if 0 94#if 0
95 if (galileo_id >= 0x10) { 95 if (galileo_id >= 0x10) {
96 /* New Galileo, assumes PCI stop line to VIA is connected. */ 96 /* New Galileo, assumes PCI stop line to VIA is connected. */
97 GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS); 97 GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
98 } else if (galileo_id == 0x1 || galileo_id == 0x2) 98 } else if (galileo_id == 0x1 || galileo_id == 0x2)
99#endif 99#endif
100 { 100 {
101 signed int timeo; 101 signed int timeo;
102 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */ 102 /* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
103 timeo = GALILEO_INL(GT_PCI0_TOR_OFS); 103 timeo = GT_READ(GT_PCI0_TOR_OFS);
104 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */ 104 /* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
105 GALILEO_OUTL( 105 GT_WRITE(GT_PCI0_TOR_OFS,
106 (0xff << 16) | /* retry count */ 106 (0xff << 16) | /* retry count */
107 (0xff << 8) | /* timeout 1 */ 107 (0xff << 8) | /* timeout 1 */
108 0xff, /* timeout 0 */ 108 0xff); /* timeout 0 */
109 GT_PCI0_TOR_OFS);
110 109
111 /* enable PCI retry exceeded interrupt */ 110 /* enable PCI retry exceeded interrupt */
112 GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS); 111 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
113 } 112 }
114} 113}
115 114
diff --git a/arch/mips/pci/fixup-ev64120.c b/arch/mips/pci/fixup-ev64120.c
deleted file mode 100644
index 8dbb90d63f0a..000000000000
--- a/arch/mips/pci/fixup-ev64120.c
+++ /dev/null
@@ -1,34 +0,0 @@
1#include <linux/pci.h>
2#include <linux/init.h>
3
4int pci_range_ck(unsigned char bus, unsigned char dev)
5{
6 if (((bus == 0) || (bus == 1)) && (dev >= 6) && (dev <= 8))
7 return 0;
8
9 return -1;
10}
11
12/*
13 * After detecting all agents over the PCI , this function is called
14 * in order to give an interrupt number for each PCI device starting
15 * from IRQ 20. It does also enables master for each device.
16 */
17void __devinit pcibios_fixup_bus(struct pci_bus *bus)
18{
19 unsigned int irq = 20;
20 struct pci_bus *current_bus = bus;
21 struct pci_dev *dev;
22 struct list_head *devices_link;
23
24 list_for_each(devices_link, &(current_bus->devices)) {
25 dev = pci_dev_b(devices_link);
26 if (dev != NULL) {
27 dev->irq = irq++;
28
29 /* Assign an interrupt number for the device */
30 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
31 pcibios_set_master(dev);
32 }
33 }
34}
diff --git a/arch/mips/pci/ops-gt64111.c b/arch/mips/pci/ops-gt64111.c
index 13de45940b19..ecd3991bd0e4 100644
--- a/arch/mips/pci/ops-gt64111.c
+++ b/arch/mips/pci/ops-gt64111.c
@@ -38,18 +38,18 @@ static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
38 switch (size) { 38 switch (size) {
39 case 4: 39 case 4:
40 PCI_CFG_SET(devfn, where); 40 PCI_CFG_SET(devfn, where);
41 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 41 *val = GT_READ(GT_PCI0_CFGDATA_OFS);
42 return PCIBIOS_SUCCESSFUL; 42 return PCIBIOS_SUCCESSFUL;
43 43
44 case 2: 44 case 2:
45 PCI_CFG_SET(devfn, (where & ~0x3)); 45 PCI_CFG_SET(devfn, (where & ~0x3));
46 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) 46 *val = GT_READ(GT_PCI0_CFGDATA_OFS)
47 >> ((where & 3) * 8); 47 >> ((where & 3) * 8);
48 return PCIBIOS_SUCCESSFUL; 48 return PCIBIOS_SUCCESSFUL;
49 49
50 case 1: 50 case 1:
51 PCI_CFG_SET(devfn, (where & ~0x3)); 51 PCI_CFG_SET(devfn, (where & ~0x3));
52 *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS) 52 *val = GT_READ(GT_PCI0_CFGDATA_OFS)
53 >> ((where & 3) * 8); 53 >> ((where & 3) * 8);
54 return PCIBIOS_SUCCESSFUL; 54 return PCIBIOS_SUCCESSFUL;
55 } 55 }
@@ -68,25 +68,25 @@ static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn,
68 switch (size) { 68 switch (size) {
69 case 4: 69 case 4:
70 PCI_CFG_SET(devfn, where); 70 PCI_CFG_SET(devfn, where);
71 GALILEO_OUTL(val, GT_PCI0_CFGDATA_OFS); 71 GT_WRITE(GT_PCI0_CFGDATA_OFS, val);
72 72
73 return PCIBIOS_SUCCESSFUL; 73 return PCIBIOS_SUCCESSFUL;
74 74
75 case 2: 75 case 2:
76 PCI_CFG_SET(devfn, (where & ~0x3)); 76 PCI_CFG_SET(devfn, (where & ~0x3));
77 tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 77 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
78 tmp &= ~(0xffff << ((where & 0x3) * 8)); 78 tmp &= ~(0xffff << ((where & 0x3) * 8));
79 tmp |= (val << ((where & 0x3) * 8)); 79 tmp |= (val << ((where & 0x3) * 8));
80 GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); 80 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
81 81
82 return PCIBIOS_SUCCESSFUL; 82 return PCIBIOS_SUCCESSFUL;
83 83
84 case 1: 84 case 1:
85 PCI_CFG_SET(devfn, (where & ~0x3)); 85 PCI_CFG_SET(devfn, (where & ~0x3));
86 tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS); 86 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
87 tmp &= ~(0xff << ((where & 0x3) * 8)); 87 tmp &= ~(0xff << ((where & 0x3) * 8));
88 tmp |= (val << ((where & 0x3) * 8)); 88 tmp |= (val << ((where & 0x3) * 8));
89 GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS); 89 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
90 90
91 return PCIBIOS_SUCCESSFUL; 91 return PCIBIOS_SUCCESSFUL;
92 } 92 }
diff --git a/arch/mips/pci/pci-ev64120.c b/arch/mips/pci/pci-ev64120.c
new file mode 100644
index 000000000000..9cd859ef1842
--- /dev/null
+++ b/arch/mips/pci/pci-ev64120.c
@@ -0,0 +1,21 @@
1#include <linux/pci.h>
2
3int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
4{
5 int irq;
6
7 if (!pin)
8 return 0;
9
10 irq = allocate_irqno();
11 if (irq < 0)
12 return 0;
13
14 return irq;
15}
16
17/* Do platform specific device initialization at pci_enable_device() time */
18int pcibios_plat_dev_init(struct pci_dev *dev)
19{
20 return 0;
21}
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index 710611615ca2..0dc23930edbd 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -38,8 +38,6 @@
38#include <int.h> 38#include <int.h>
39#include <uart.h> 39#include <uart.h>
40 40
41static DEFINE_SPINLOCK(irq_lock);
42
43/* default prio for interrupts */ 41/* default prio for interrupts */
44/* first one is a no-no so therefore always prio 0 (disabled) */ 42/* first one is a no-no so therefore always prio 0 (disabled) */
45static char gic_prio[PNX8550_INT_GIC_TOTINT] = { 43static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
@@ -149,38 +147,6 @@ static inline void unmask_irq(unsigned int irq_nr)
149 } 147 }
150} 148}
151 149
152#define pnx8550_disable pnx8550_ack
153static void pnx8550_ack(unsigned int irq)
154{
155 unsigned long flags;
156
157 spin_lock_irqsave(&irq_lock, flags);
158 mask_irq(irq);
159 spin_unlock_irqrestore(&irq_lock, flags);
160}
161
162#define pnx8550_enable pnx8550_unmask
163static void pnx8550_unmask(unsigned int irq)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&irq_lock, flags);
168 unmask_irq(irq);
169 spin_unlock_irqrestore(&irq_lock, flags);
170}
171
172static unsigned int startup_irq(unsigned int irq_nr)
173{
174 pnx8550_unmask(irq_nr);
175 return 0;
176}
177
178static void shutdown_irq(unsigned int irq_nr)
179{
180 pnx8550_ack(irq_nr);
181 return;
182}
183
184int pnx8550_set_gic_priority(int irq, int priority) 150int pnx8550_set_gic_priority(int irq, int priority)
185{ 151{
186 int gic_irq = irq-PNX8550_INT_GIC_MIN; 152 int gic_irq = irq-PNX8550_INT_GIC_MIN;
@@ -192,26 +158,19 @@ int pnx8550_set_gic_priority(int irq, int priority)
192 return prev_priority; 158 return prev_priority;
193} 159}
194 160
195static inline void mask_and_ack_level_irq(unsigned int irq)
196{
197 pnx8550_disable(irq);
198 return;
199}
200
201static void end_irq(unsigned int irq) 161static void end_irq(unsigned int irq)
202{ 162{
203 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { 163 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
204 pnx8550_enable(irq); 164 unmask_irq(irq);
205 } 165 }
206} 166}
207 167
208static struct irq_chip level_irq_type = { 168static struct irq_chip level_irq_type = {
209 .typename = "PNX Level IRQ", 169 .typename = "PNX Level IRQ",
210 .startup = startup_irq, 170 .ack = mask_irq,
211 .shutdown = shutdown_irq, 171 .mask = mask_irq,
212 .enable = pnx8550_enable, 172 .mask_ack = mask_irq,
213 .disable = pnx8550_disable, 173 .unmask = unmask_irq,
214 .ack = mask_and_ack_level_irq,
215 .end = end_irq, 174 .end = end_irq,
216}; 175};
217 176
@@ -233,8 +192,8 @@ void __init arch_init_irq(void)
233 int configPR; 192 int configPR;
234 193
235 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { 194 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
236 irq_desc[i].chip = &level_irq_type; 195 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
237 pnx8550_ack(i); /* mask the irq just in case */ 196 mask_irq(i); /* mask the irq just in case */
238 } 197 }
239 198
240 /* init of GIC/IPC interrupts */ 199 /* init of GIC/IPC interrupts */
@@ -270,7 +229,7 @@ void __init arch_init_irq(void)
270 /* mask/priority is still 0 so we will not get any 229 /* mask/priority is still 0 so we will not get any
271 * interrupts until it is unmasked */ 230 * interrupts until it is unmasked */
272 231
273 irq_desc[i].chip = &level_irq_type; 232 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
274 } 233 }
275 234
276 /* Priority level 0 */ 235 /* Priority level 0 */
@@ -279,20 +238,21 @@ void __init arch_init_irq(void)
279 /* Set int vector table address */ 238 /* Set int vector table address */
280 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; 239 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
281 240
282 irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type; 241 set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
242 handle_level_irq);
283 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); 243 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
284 244
285 /* init of Timer interrupts */ 245 /* init of Timer interrupts */
286 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { 246 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
287 irq_desc[i].chip = &level_irq_type; 247 set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
288 }
289 248
290 /* Stop Timer 1-3 */ 249 /* Stop Timer 1-3 */
291 configPR = read_c0_config7(); 250 configPR = read_c0_config7();
292 configPR |= 0x00000038; 251 configPR |= 0x00000038;
293 write_c0_config7(configPR); 252 write_c0_config7(configPR);
294 253
295 irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type; 254 set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
255 handle_level_irq);
296 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); 256 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
297} 257}
298 258
diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c
index 0af655b1f330..65c440e8480b 100644
--- a/arch/mips/philips/pnx8550/common/time.c
+++ b/arch/mips/philips/pnx8550/common/time.c
@@ -41,8 +41,8 @@ extern unsigned int mips_hpt_frequency;
41 * 1) board_time_init() - 41 * 1) board_time_init() -
42 * a) (optional) set up RTC routines, 42 * a) (optional) set up RTC routines,
43 * b) (optional) calibrate and set the mips_hpt_frequency 43 * b) (optional) calibrate and set the mips_hpt_frequency
44 * (only needed if you intended to use fixed_rate_gettimeoffset 44 * (only needed if you intended to use cpu counter as timer interrupt
45 * or use cpu counter as timer interrupt source) 45 * source)
46 */ 46 */
47 47
48void pnx8550_time_init(void) 48void pnx8550_time_init(void)
diff --git a/arch/mips/pmc-sierra/yosemite/i2c-yosemite.c b/arch/mips/pmc-sierra/yosemite/i2c-yosemite.c
index 416da22b3bf4..85b14c73c226 100644
--- a/arch/mips/pmc-sierra/yosemite/i2c-yosemite.c
+++ b/arch/mips/pmc-sierra/yosemite/i2c-yosemite.c
@@ -74,7 +74,7 @@ static int titan_i2c_poll(void)
74int titan_i2c_xfer(unsigned int slave_addr, titan_i2c_command * cmd, 74int titan_i2c_xfer(unsigned int slave_addr, titan_i2c_command * cmd,
75 int size, unsigned int *addr) 75 int size, unsigned int *addr)
76{ 76{
77 int loop = 0, bytes, i; 77 int loop, bytes = 0, i;
78 unsigned int *write_data, data, *read_data; 78 unsigned int *write_data, data, *read_data;
79 unsigned long reg_val, val; 79 unsigned long reg_val, val;
80 80
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index 65fa3a23ea5e..305491e74dbe 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -3,9 +3,7 @@
3 3
4#include <asm/pmon.h> 4#include <asm/pmon.h>
5#include <asm/titan_dep.h> 5#include <asm/titan_dep.h>
6 6#include <asm/time.h>
7extern unsigned int (*mips_hpt_read)(void);
8extern void (*mips_hpt_init)(unsigned int);
9 7
10#define LAUNCHSTACK_SIZE 256 8#define LAUNCHSTACK_SIZE 256
11 9
@@ -101,8 +99,6 @@ void prom_cpus_done(void)
101 */ 99 */
102void prom_init_secondary(void) 100void prom_init_secondary(void)
103{ 101{
104 mips_hpt_init(mips_hpt_read());
105
106 set_c0_status(ST0_CO | ST0_IE | ST0_IM); 102 set_c0_status(ST0_CO | ST0_IE | ST0_IM);
107} 103}
108 104
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 0d18ed47c47a..a1a9af6da7bf 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -95,16 +95,11 @@ static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
95 95
96static void enable_eisa1_irq(unsigned int irq) 96static void enable_eisa1_irq(unsigned int irq)
97{ 97{
98 unsigned long flags;
99 u8 mask; 98 u8 mask;
100 99
101 local_irq_save(flags);
102
103 mask = inb(EISA_INT1_MASK); 100 mask = inb(EISA_INT1_MASK);
104 mask &= ~((u8) (1 << irq)); 101 mask &= ~((u8) (1 << irq));
105 outb(mask, EISA_INT1_MASK); 102 outb(mask, EISA_INT1_MASK);
106
107 local_irq_restore(flags);
108} 103}
109 104
110static unsigned int startup_eisa1_irq(unsigned int irq) 105static unsigned int startup_eisa1_irq(unsigned int irq)
@@ -130,8 +125,6 @@ static void disable_eisa1_irq(unsigned int irq)
130 outb(mask, EISA_INT1_MASK); 125 outb(mask, EISA_INT1_MASK);
131} 126}
132 127
133#define shutdown_eisa1_irq disable_eisa1_irq
134
135static void mask_and_ack_eisa1_irq(unsigned int irq) 128static void mask_and_ack_eisa1_irq(unsigned int irq)
136{ 129{
137 disable_eisa1_irq(irq); 130 disable_eisa1_irq(irq);
@@ -148,25 +141,20 @@ static void end_eisa1_irq(unsigned int irq)
148static struct irq_chip ip22_eisa1_irq_type = { 141static struct irq_chip ip22_eisa1_irq_type = {
149 .typename = "IP22 EISA", 142 .typename = "IP22 EISA",
150 .startup = startup_eisa1_irq, 143 .startup = startup_eisa1_irq,
151 .shutdown = shutdown_eisa1_irq,
152 .enable = enable_eisa1_irq,
153 .disable = disable_eisa1_irq,
154 .ack = mask_and_ack_eisa1_irq, 144 .ack = mask_and_ack_eisa1_irq,
145 .mask = disable_eisa1_irq,
146 .mask_ack = mask_and_ack_eisa1_irq,
147 .unmask = enable_eisa1_irq,
155 .end = end_eisa1_irq, 148 .end = end_eisa1_irq,
156}; 149};
157 150
158static void enable_eisa2_irq(unsigned int irq) 151static void enable_eisa2_irq(unsigned int irq)
159{ 152{
160 unsigned long flags;
161 u8 mask; 153 u8 mask;
162 154
163 local_irq_save(flags);
164
165 mask = inb(EISA_INT2_MASK); 155 mask = inb(EISA_INT2_MASK);
166 mask &= ~((u8) (1 << (irq - 8))); 156 mask &= ~((u8) (1 << (irq - 8)));
167 outb(mask, EISA_INT2_MASK); 157 outb(mask, EISA_INT2_MASK);
168
169 local_irq_restore(flags);
170} 158}
171 159
172static unsigned int startup_eisa2_irq(unsigned int irq) 160static unsigned int startup_eisa2_irq(unsigned int irq)
@@ -192,8 +180,6 @@ static void disable_eisa2_irq(unsigned int irq)
192 outb(mask, EISA_INT2_MASK); 180 outb(mask, EISA_INT2_MASK);
193} 181}
194 182
195#define shutdown_eisa2_irq disable_eisa2_irq
196
197static void mask_and_ack_eisa2_irq(unsigned int irq) 183static void mask_and_ack_eisa2_irq(unsigned int irq)
198{ 184{
199 disable_eisa2_irq(irq); 185 disable_eisa2_irq(irq);
@@ -210,10 +196,10 @@ static void end_eisa2_irq(unsigned int irq)
210static struct irq_chip ip22_eisa2_irq_type = { 196static struct irq_chip ip22_eisa2_irq_type = {
211 .typename = "IP22 EISA", 197 .typename = "IP22 EISA",
212 .startup = startup_eisa2_irq, 198 .startup = startup_eisa2_irq,
213 .shutdown = shutdown_eisa2_irq,
214 .enable = enable_eisa2_irq,
215 .disable = disable_eisa2_irq,
216 .ack = mask_and_ack_eisa2_irq, 199 .ack = mask_and_ack_eisa2_irq,
200 .mask = disable_eisa2_irq,
201 .mask_ack = mask_and_ack_eisa2_irq,
202 .unmask = enable_eisa2_irq,
217 .end = end_eisa2_irq, 203 .end = end_eisa2_irq,
218}; 204};
219 205
@@ -275,13 +261,10 @@ int __init ip22_eisa_init(void)
275 outb(0, EISA_DMA2_WRITE_SINGLE); 261 outb(0, EISA_DMA2_WRITE_SINGLE);
276 262
277 for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) { 263 for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
278 irq_desc[i].status = IRQ_DISABLED;
279 irq_desc[i].action = 0;
280 irq_desc[i].depth = 1;
281 if (i < (SGINT_EISA + 8)) 264 if (i < (SGINT_EISA + 8))
282 irq_desc[i].chip = &ip22_eisa1_irq_type; 265 set_irq_chip(i, &ip22_eisa1_irq_type);
283 else 266 else
284 irq_desc[i].chip = &ip22_eisa2_irq_type; 267 set_irq_chip(i, &ip22_eisa2_irq_type);
285 } 268 }
286 269
287 /* Cannot use request_irq because of kmalloc not being ready at such 270 /* Cannot use request_irq because of kmalloc not being ready at such
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index af518898eaa1..c7b138053159 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -40,34 +40,17 @@ extern int ip22_eisa_init(void);
40 40
41static void enable_local0_irq(unsigned int irq) 41static void enable_local0_irq(unsigned int irq)
42{ 42{
43 unsigned long flags;
44
45 local_irq_save(flags);
46 /* don't allow mappable interrupt to be enabled from setup_irq, 43 /* don't allow mappable interrupt to be enabled from setup_irq,
47 * we have our own way to do so */ 44 * we have our own way to do so */
48 if (irq != SGI_MAP_0_IRQ) 45 if (irq != SGI_MAP_0_IRQ)
49 sgint->imask0 |= (1 << (irq - SGINT_LOCAL0)); 46 sgint->imask0 |= (1 << (irq - SGINT_LOCAL0));
50 local_irq_restore(flags);
51}
52
53static unsigned int startup_local0_irq(unsigned int irq)
54{
55 enable_local0_irq(irq);
56 return 0; /* Never anything pending */
57} 47}
58 48
59static void disable_local0_irq(unsigned int irq) 49static void disable_local0_irq(unsigned int irq)
60{ 50{
61 unsigned long flags;
62
63 local_irq_save(flags);
64 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0)); 51 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
65 local_irq_restore(flags);
66} 52}
67 53
68#define shutdown_local0_irq disable_local0_irq
69#define mask_and_ack_local0_irq disable_local0_irq
70
71static void end_local0_irq (unsigned int irq) 54static void end_local0_irq (unsigned int irq)
72{ 55{
73 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 56 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -76,44 +59,26 @@ static void end_local0_irq (unsigned int irq)
76 59
77static struct irq_chip ip22_local0_irq_type = { 60static struct irq_chip ip22_local0_irq_type = {
78 .typename = "IP22 local 0", 61 .typename = "IP22 local 0",
79 .startup = startup_local0_irq, 62 .ack = disable_local0_irq,
80 .shutdown = shutdown_local0_irq, 63 .mask = disable_local0_irq,
81 .enable = enable_local0_irq, 64 .mask_ack = disable_local0_irq,
82 .disable = disable_local0_irq, 65 .unmask = enable_local0_irq,
83 .ack = mask_and_ack_local0_irq,
84 .end = end_local0_irq, 66 .end = end_local0_irq,
85}; 67};
86 68
87static void enable_local1_irq(unsigned int irq) 69static void enable_local1_irq(unsigned int irq)
88{ 70{
89 unsigned long flags;
90
91 local_irq_save(flags);
92 /* don't allow mappable interrupt to be enabled from setup_irq, 71 /* don't allow mappable interrupt to be enabled from setup_irq,
93 * we have our own way to do so */ 72 * we have our own way to do so */
94 if (irq != SGI_MAP_1_IRQ) 73 if (irq != SGI_MAP_1_IRQ)
95 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1)); 74 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
96 local_irq_restore(flags);
97}
98
99static unsigned int startup_local1_irq(unsigned int irq)
100{
101 enable_local1_irq(irq);
102 return 0; /* Never anything pending */
103} 75}
104 76
105void disable_local1_irq(unsigned int irq) 77void disable_local1_irq(unsigned int irq)
106{ 78{
107 unsigned long flags;
108
109 local_irq_save(flags);
110 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); 79 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
111 local_irq_restore(flags);
112} 80}
113 81
114#define shutdown_local1_irq disable_local1_irq
115#define mask_and_ack_local1_irq disable_local1_irq
116
117static void end_local1_irq (unsigned int irq) 82static void end_local1_irq (unsigned int irq)
118{ 83{
119 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 84 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -122,44 +87,26 @@ static void end_local1_irq (unsigned int irq)
122 87
123static struct irq_chip ip22_local1_irq_type = { 88static struct irq_chip ip22_local1_irq_type = {
124 .typename = "IP22 local 1", 89 .typename = "IP22 local 1",
125 .startup = startup_local1_irq, 90 .ack = disable_local1_irq,
126 .shutdown = shutdown_local1_irq, 91 .mask = disable_local1_irq,
127 .enable = enable_local1_irq, 92 .mask_ack = disable_local1_irq,
128 .disable = disable_local1_irq, 93 .unmask = enable_local1_irq,
129 .ack = mask_and_ack_local1_irq,
130 .end = end_local1_irq, 94 .end = end_local1_irq,
131}; 95};
132 96
133static void enable_local2_irq(unsigned int irq) 97static void enable_local2_irq(unsigned int irq)
134{ 98{
135 unsigned long flags;
136
137 local_irq_save(flags);
138 sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); 99 sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
139 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2)); 100 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
140 local_irq_restore(flags);
141}
142
143static unsigned int startup_local2_irq(unsigned int irq)
144{
145 enable_local2_irq(irq);
146 return 0; /* Never anything pending */
147} 101}
148 102
149void disable_local2_irq(unsigned int irq) 103void disable_local2_irq(unsigned int irq)
150{ 104{
151 unsigned long flags;
152
153 local_irq_save(flags);
154 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2)); 105 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
155 if (!sgint->cmeimask0) 106 if (!sgint->cmeimask0)
156 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); 107 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
157 local_irq_restore(flags);
158} 108}
159 109
160#define shutdown_local2_irq disable_local2_irq
161#define mask_and_ack_local2_irq disable_local2_irq
162
163static void end_local2_irq (unsigned int irq) 110static void end_local2_irq (unsigned int irq)
164{ 111{
165 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 112 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -168,44 +115,26 @@ static void end_local2_irq (unsigned int irq)
168 115
169static struct irq_chip ip22_local2_irq_type = { 116static struct irq_chip ip22_local2_irq_type = {
170 .typename = "IP22 local 2", 117 .typename = "IP22 local 2",
171 .startup = startup_local2_irq, 118 .ack = disable_local2_irq,
172 .shutdown = shutdown_local2_irq, 119 .mask = disable_local2_irq,
173 .enable = enable_local2_irq, 120 .mask_ack = disable_local2_irq,
174 .disable = disable_local2_irq, 121 .unmask = enable_local2_irq,
175 .ack = mask_and_ack_local2_irq,
176 .end = end_local2_irq, 122 .end = end_local2_irq,
177}; 123};
178 124
179static void enable_local3_irq(unsigned int irq) 125static void enable_local3_irq(unsigned int irq)
180{ 126{
181 unsigned long flags;
182
183 local_irq_save(flags);
184 sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); 127 sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
185 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3)); 128 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
186 local_irq_restore(flags);
187}
188
189static unsigned int startup_local3_irq(unsigned int irq)
190{
191 enable_local3_irq(irq);
192 return 0; /* Never anything pending */
193} 129}
194 130
195void disable_local3_irq(unsigned int irq) 131void disable_local3_irq(unsigned int irq)
196{ 132{
197 unsigned long flags;
198
199 local_irq_save(flags);
200 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3)); 133 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
201 if (!sgint->cmeimask1) 134 if (!sgint->cmeimask1)
202 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); 135 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
203 local_irq_restore(flags);
204} 136}
205 137
206#define shutdown_local3_irq disable_local3_irq
207#define mask_and_ack_local3_irq disable_local3_irq
208
209static void end_local3_irq (unsigned int irq) 138static void end_local3_irq (unsigned int irq)
210{ 139{
211 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 140 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -214,11 +143,10 @@ static void end_local3_irq (unsigned int irq)
214 143
215static struct irq_chip ip22_local3_irq_type = { 144static struct irq_chip ip22_local3_irq_type = {
216 .typename = "IP22 local 3", 145 .typename = "IP22 local 3",
217 .startup = startup_local3_irq, 146 .ack = disable_local3_irq,
218 .shutdown = shutdown_local3_irq, 147 .mask = disable_local3_irq,
219 .enable = enable_local3_irq, 148 .mask_ack = disable_local3_irq,
220 .disable = disable_local3_irq, 149 .unmask = enable_local3_irq,
221 .ack = mask_and_ack_local3_irq,
222 .end = end_local3_irq, 150 .end = end_local3_irq,
223}; 151};
224 152
@@ -430,10 +358,7 @@ void __init arch_init_irq(void)
430 else 358 else
431 handler = &ip22_local3_irq_type; 359 handler = &ip22_local3_irq_type;
432 360
433 irq_desc[i].status = IRQ_DISABLED; 361 set_irq_chip_and_handler(i, handler, handle_level_irq);
434 irq_desc[i].action = 0;
435 irq_desc[i].depth = 1;
436 irq_desc[i].chip = handler;
437 } 362 }
438 363
439 /* vector handler. this register the IRQ as non-sharable */ 364 /* vector handler. this register the IRQ as non-sharable */
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index f01ba1f90770..5f8835b4e84a 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -332,11 +332,6 @@ static inline void disable_bridge_irq(unsigned int irq)
332 intr_disconnect_level(cpu, swlevel); 332 intr_disconnect_level(cpu, swlevel);
333} 333}
334 334
335static void mask_and_ack_bridge_irq(unsigned int irq)
336{
337 disable_bridge_irq(irq);
338}
339
340static void end_bridge_irq(unsigned int irq) 335static void end_bridge_irq(unsigned int irq)
341{ 336{
342 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) && 337 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
@@ -348,41 +343,16 @@ static struct irq_chip bridge_irq_type = {
348 .typename = "bridge", 343 .typename = "bridge",
349 .startup = startup_bridge_irq, 344 .startup = startup_bridge_irq,
350 .shutdown = shutdown_bridge_irq, 345 .shutdown = shutdown_bridge_irq,
351 .enable = enable_bridge_irq, 346 .ack = disable_bridge_irq,
352 .disable = disable_bridge_irq, 347 .mask = disable_bridge_irq,
353 .ack = mask_and_ack_bridge_irq, 348 .mask_ack = disable_bridge_irq,
349 .unmask = enable_bridge_irq,
354 .end = end_bridge_irq, 350 .end = end_bridge_irq,
355}; 351};
356 352
357static unsigned long irq_map[NR_IRQS / BITS_PER_LONG];
358
359int allocate_irqno(void)
360{
361 int irq;
362
363again:
364 irq = find_first_zero_bit(irq_map, NR_IRQS);
365
366 if (irq >= NR_IRQS)
367 return -ENOSPC;
368
369 if (test_and_set_bit(irq, irq_map))
370 goto again;
371
372 return irq;
373}
374
375void free_irqno(unsigned int irq)
376{
377 clear_bit(irq, irq_map);
378}
379
380void __devinit register_bridge_irq(unsigned int irq) 353void __devinit register_bridge_irq(unsigned int irq)
381{ 354{
382 irq_desc[irq].status = IRQ_DISABLED; 355 set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
383 irq_desc[irq].action = 0;
384 irq_desc[irq].depth = 1;
385 irq_desc[irq].chip = &bridge_irq_type;
386} 356}
387 357
388int __devinit request_bridge_irq(struct bridge_controller *bc) 358int __devinit request_bridge_irq(struct bridge_controller *bc)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 4e870fc4469b..7d361726bbfb 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -134,13 +134,6 @@ again:
134 irq_exit(); 134 irq_exit();
135} 135}
136 136
137unsigned long ip27_do_gettimeoffset(void)
138{
139 unsigned long ct_cur1;
140 ct_cur1 = REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT) + CYCLES_PER_JIFFY;
141 return (ct_cur1 - ct_cur[0]) * NSEC_PER_CYCLE / 1000;
142}
143
144/* Includes for ioc3_init(). */ 137/* Includes for ioc3_init(). */
145#include <asm/sn/types.h> 138#include <asm/sn/types.h>
146#include <asm/sn/sn0/addrs.h> 139#include <asm/sn/sn0/addrs.h>
@@ -179,15 +172,6 @@ static __init unsigned long get_m48t35_time(void)
179 return mktime(year, month, date, hour, min, sec); 172 return mktime(year, month, date, hour, min, sec);
180} 173}
181 174
182static unsigned int startup_rt_irq(unsigned int irq)
183{
184 return 0;
185}
186
187static void shutdown_rt_irq(unsigned int irq)
188{
189}
190
191static void enable_rt_irq(unsigned int irq) 175static void enable_rt_irq(unsigned int irq)
192{ 176{
193} 177}
@@ -196,21 +180,17 @@ static void disable_rt_irq(unsigned int irq)
196{ 180{
197} 181}
198 182
199static void mask_and_ack_rt(unsigned int irq)
200{
201}
202
203static void end_rt_irq(unsigned int irq) 183static void end_rt_irq(unsigned int irq)
204{ 184{
205} 185}
206 186
207static struct irq_chip rt_irq_type = { 187static struct irq_chip rt_irq_type = {
208 .typename = "SN HUB RT timer", 188 .typename = "SN HUB RT timer",
209 .startup = startup_rt_irq, 189 .ack = disable_rt_irq,
210 .shutdown = shutdown_rt_irq, 190 .mask = disable_rt_irq,
211 .enable = enable_rt_irq, 191 .mask_ack = disable_rt_irq,
212 .disable = disable_rt_irq, 192 .unmask = enable_rt_irq,
213 .ack = mask_and_ack_rt, 193 .eoi = enable_rt_irq,
214 .end = end_rt_irq, 194 .end = end_rt_irq,
215}; 195};
216 196
@@ -221,8 +201,6 @@ static struct irqaction rt_irqaction = {
221 .name = "timer" 201 .name = "timer"
222}; 202};
223 203
224extern int allocate_irqno(void);
225
226void __init plat_timer_setup(struct irqaction *irq) 204void __init plat_timer_setup(struct irqaction *irq)
227{ 205{
228 int irqno = allocate_irqno(); 206 int irqno = allocate_irqno();
@@ -230,10 +208,7 @@ void __init plat_timer_setup(struct irqaction *irq)
230 if (irqno < 0) 208 if (irqno < 0)
231 panic("Can't allocate interrupt number for timer interrupt"); 209 panic("Can't allocate interrupt number for timer interrupt");
232 210
233 irq_desc[irqno].status = IRQ_DISABLED; 211 set_irq_chip_and_handler(irqno, &rt_irq_type, handle_percpu_irq);
234 irq_desc[irqno].action = NULL;
235 irq_desc[irqno].depth = 1;
236 irq_desc[irqno].chip = &rt_irq_type;
237 212
238 /* over-write the handler, we use our own way */ 213 /* over-write the handler, we use our own way */
239 irq->handler = no_action; 214 irq->handler = no_action;
@@ -248,12 +223,17 @@ void __init plat_timer_setup(struct irqaction *irq)
248 setup_irq(irqno, &rt_irqaction); 223 setup_irq(irqno, &rt_irqaction);
249} 224}
250 225
226static cycle_t ip27_hpt_read(void)
227{
228 return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT);
229}
230
251void __init ip27_time_init(void) 231void __init ip27_time_init(void)
252{ 232{
233 clocksource_mips.read = ip27_hpt_read;
234 mips_hpt_frequency = CYCLES_PER_SEC;
253 xtime.tv_sec = get_m48t35_time(); 235 xtime.tv_sec = get_m48t35_time();
254 xtime.tv_nsec = 0; 236 xtime.tv_nsec = 0;
255
256 do_gettimeoffset = ip27_do_gettimeoffset;
257} 237}
258 238
259void __init cpu_time_init(void) 239void __init cpu_time_init(void)
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index c9acadd0846b..ae063864c026 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -113,12 +113,6 @@ static void inline flush_mace_bus(void)
113 * is quite different anyway. 113 * is quite different anyway.
114 */ 114 */
115 115
116/*
117 * IRQ spinlock - Ralf says not to disable CPU interrupts,
118 * and I think he knows better.
119 */
120static DEFINE_SPINLOCK(ip32_irq_lock);
121
122/* Some initial interrupts to set up */ 116/* Some initial interrupts to set up */
123extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); 117extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
124extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); 118extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
@@ -138,12 +132,6 @@ static void enable_cpu_irq(unsigned int irq)
138 set_c0_status(STATUSF_IP7); 132 set_c0_status(STATUSF_IP7);
139} 133}
140 134
141static unsigned int startup_cpu_irq(unsigned int irq)
142{
143 enable_cpu_irq(irq);
144 return 0;
145}
146
147static void disable_cpu_irq(unsigned int irq) 135static void disable_cpu_irq(unsigned int irq)
148{ 136{
149 clear_c0_status(STATUSF_IP7); 137 clear_c0_status(STATUSF_IP7);
@@ -155,16 +143,12 @@ static void end_cpu_irq(unsigned int irq)
155 enable_cpu_irq (irq); 143 enable_cpu_irq (irq);
156} 144}
157 145
158#define shutdown_cpu_irq disable_cpu_irq
159#define mask_and_ack_cpu_irq disable_cpu_irq
160
161static struct irq_chip ip32_cpu_interrupt = { 146static struct irq_chip ip32_cpu_interrupt = {
162 .typename = "IP32 CPU", 147 .typename = "IP32 CPU",
163 .startup = startup_cpu_irq, 148 .ack = disable_cpu_irq,
164 .shutdown = shutdown_cpu_irq, 149 .mask = disable_cpu_irq,
165 .enable = enable_cpu_irq, 150 .mask_ack = disable_cpu_irq,
166 .disable = disable_cpu_irq, 151 .unmask = enable_cpu_irq,
167 .ack = mask_and_ack_cpu_irq,
168 .end = end_cpu_irq, 152 .end = end_cpu_irq,
169}; 153};
170 154
@@ -177,45 +161,27 @@ static uint64_t crime_mask;
177 161
178static void enable_crime_irq(unsigned int irq) 162static void enable_crime_irq(unsigned int irq)
179{ 163{
180 unsigned long flags;
181
182 spin_lock_irqsave(&ip32_irq_lock, flags);
183 crime_mask |= 1 << (irq - 1); 164 crime_mask |= 1 << (irq - 1);
184 crime->imask = crime_mask; 165 crime->imask = crime_mask;
185 spin_unlock_irqrestore(&ip32_irq_lock, flags);
186}
187
188static unsigned int startup_crime_irq(unsigned int irq)
189{
190 enable_crime_irq(irq);
191 return 0; /* This is probably not right; we could have pending irqs */
192} 166}
193 167
194static void disable_crime_irq(unsigned int irq) 168static void disable_crime_irq(unsigned int irq)
195{ 169{
196 unsigned long flags;
197
198 spin_lock_irqsave(&ip32_irq_lock, flags);
199 crime_mask &= ~(1 << (irq - 1)); 170 crime_mask &= ~(1 << (irq - 1));
200 crime->imask = crime_mask; 171 crime->imask = crime_mask;
201 flush_crime_bus(); 172 flush_crime_bus();
202 spin_unlock_irqrestore(&ip32_irq_lock, flags);
203} 173}
204 174
205static void mask_and_ack_crime_irq(unsigned int irq) 175static void mask_and_ack_crime_irq(unsigned int irq)
206{ 176{
207 unsigned long flags;
208
209 /* Edge triggered interrupts must be cleared. */ 177 /* Edge triggered interrupts must be cleared. */
210 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ) 178 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
211 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ) 179 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
212 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) { 180 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
213 uint64_t crime_int; 181 uint64_t crime_int;
214 spin_lock_irqsave(&ip32_irq_lock, flags);
215 crime_int = crime->hard_int; 182 crime_int = crime->hard_int;
216 crime_int &= ~(1 << (irq - 1)); 183 crime_int &= ~(1 << (irq - 1));
217 crime->hard_int = crime_int; 184 crime->hard_int = crime_int;
218 spin_unlock_irqrestore(&ip32_irq_lock, flags);
219 } 185 }
220 disable_crime_irq(irq); 186 disable_crime_irq(irq);
221} 187}
@@ -226,15 +192,12 @@ static void end_crime_irq(unsigned int irq)
226 enable_crime_irq(irq); 192 enable_crime_irq(irq);
227} 193}
228 194
229#define shutdown_crime_irq disable_crime_irq
230
231static struct irq_chip ip32_crime_interrupt = { 195static struct irq_chip ip32_crime_interrupt = {
232 .typename = "IP32 CRIME", 196 .typename = "IP32 CRIME",
233 .startup = startup_crime_irq,
234 .shutdown = shutdown_crime_irq,
235 .enable = enable_crime_irq,
236 .disable = disable_crime_irq,
237 .ack = mask_and_ack_crime_irq, 197 .ack = mask_and_ack_crime_irq,
198 .mask = disable_crime_irq,
199 .mask_ack = mask_and_ack_crime_irq,
200 .unmask = enable_crime_irq,
238 .end = end_crime_irq, 201 .end = end_crime_irq,
239}; 202};
240 203
@@ -248,34 +211,20 @@ static unsigned long macepci_mask;
248 211
249static void enable_macepci_irq(unsigned int irq) 212static void enable_macepci_irq(unsigned int irq)
250{ 213{
251 unsigned long flags;
252
253 spin_lock_irqsave(&ip32_irq_lock, flags);
254 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); 214 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
255 mace->pci.control = macepci_mask; 215 mace->pci.control = macepci_mask;
256 crime_mask |= 1 << (irq - 1); 216 crime_mask |= 1 << (irq - 1);
257 crime->imask = crime_mask; 217 crime->imask = crime_mask;
258 spin_unlock_irqrestore(&ip32_irq_lock, flags);
259}
260
261static unsigned int startup_macepci_irq(unsigned int irq)
262{
263 enable_macepci_irq (irq);
264 return 0;
265} 218}
266 219
267static void disable_macepci_irq(unsigned int irq) 220static void disable_macepci_irq(unsigned int irq)
268{ 221{
269 unsigned long flags;
270
271 spin_lock_irqsave(&ip32_irq_lock, flags);
272 crime_mask &= ~(1 << (irq - 1)); 222 crime_mask &= ~(1 << (irq - 1));
273 crime->imask = crime_mask; 223 crime->imask = crime_mask;
274 flush_crime_bus(); 224 flush_crime_bus();
275 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9); 225 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
276 mace->pci.control = macepci_mask; 226 mace->pci.control = macepci_mask;
277 flush_mace_bus(); 227 flush_mace_bus();
278 spin_unlock_irqrestore(&ip32_irq_lock, flags);
279} 228}
280 229
281static void end_macepci_irq(unsigned int irq) 230static void end_macepci_irq(unsigned int irq)
@@ -284,16 +233,12 @@ static void end_macepci_irq(unsigned int irq)
284 enable_macepci_irq(irq); 233 enable_macepci_irq(irq);
285} 234}
286 235
287#define shutdown_macepci_irq disable_macepci_irq
288#define mask_and_ack_macepci_irq disable_macepci_irq
289
290static struct irq_chip ip32_macepci_interrupt = { 236static struct irq_chip ip32_macepci_interrupt = {
291 .typename = "IP32 MACE PCI", 237 .typename = "IP32 MACE PCI",
292 .startup = startup_macepci_irq, 238 .ack = disable_macepci_irq,
293 .shutdown = shutdown_macepci_irq, 239 .mask = disable_macepci_irq,
294 .enable = enable_macepci_irq, 240 .mask_ack = disable_macepci_irq,
295 .disable = disable_macepci_irq, 241 .unmask = enable_macepci_irq,
296 .ack = mask_and_ack_macepci_irq,
297 .end = end_macepci_irq, 242 .end = end_macepci_irq,
298}; 243};
299 244
@@ -339,7 +284,6 @@ static unsigned long maceisa_mask;
339static void enable_maceisa_irq (unsigned int irq) 284static void enable_maceisa_irq (unsigned int irq)
340{ 285{
341 unsigned int crime_int = 0; 286 unsigned int crime_int = 0;
342 unsigned long flags;
343 287
344 DBG ("maceisa enable: %u\n", irq); 288 DBG ("maceisa enable: %u\n", irq);
345 289
@@ -355,26 +299,16 @@ static void enable_maceisa_irq (unsigned int irq)
355 break; 299 break;
356 } 300 }
357 DBG ("crime_int %08x enabled\n", crime_int); 301 DBG ("crime_int %08x enabled\n", crime_int);
358 spin_lock_irqsave(&ip32_irq_lock, flags);
359 crime_mask |= crime_int; 302 crime_mask |= crime_int;
360 crime->imask = crime_mask; 303 crime->imask = crime_mask;
361 maceisa_mask |= 1 << (irq - 33); 304 maceisa_mask |= 1 << (irq - 33);
362 mace->perif.ctrl.imask = maceisa_mask; 305 mace->perif.ctrl.imask = maceisa_mask;
363 spin_unlock_irqrestore(&ip32_irq_lock, flags);
364}
365
366static unsigned int startup_maceisa_irq(unsigned int irq)
367{
368 enable_maceisa_irq(irq);
369 return 0;
370} 306}
371 307
372static void disable_maceisa_irq(unsigned int irq) 308static void disable_maceisa_irq(unsigned int irq)
373{ 309{
374 unsigned int crime_int = 0; 310 unsigned int crime_int = 0;
375 unsigned long flags;
376 311
377 spin_lock_irqsave(&ip32_irq_lock, flags);
378 maceisa_mask &= ~(1 << (irq - 33)); 312 maceisa_mask &= ~(1 << (irq - 33));
379 if(!(maceisa_mask & MACEISA_AUDIO_INT)) 313 if(!(maceisa_mask & MACEISA_AUDIO_INT))
380 crime_int |= MACE_AUDIO_INT; 314 crime_int |= MACE_AUDIO_INT;
@@ -387,23 +321,20 @@ static void disable_maceisa_irq(unsigned int irq)
387 flush_crime_bus(); 321 flush_crime_bus();
388 mace->perif.ctrl.imask = maceisa_mask; 322 mace->perif.ctrl.imask = maceisa_mask;
389 flush_mace_bus(); 323 flush_mace_bus();
390 spin_unlock_irqrestore(&ip32_irq_lock, flags);
391} 324}
392 325
393static void mask_and_ack_maceisa_irq(unsigned int irq) 326static void mask_and_ack_maceisa_irq(unsigned int irq)
394{ 327{
395 unsigned long mace_int, flags; 328 unsigned long mace_int;
396 329
397 switch (irq) { 330 switch (irq) {
398 case MACEISA_PARALLEL_IRQ: 331 case MACEISA_PARALLEL_IRQ:
399 case MACEISA_SERIAL1_TDMAPR_IRQ: 332 case MACEISA_SERIAL1_TDMAPR_IRQ:
400 case MACEISA_SERIAL2_TDMAPR_IRQ: 333 case MACEISA_SERIAL2_TDMAPR_IRQ:
401 /* edge triggered */ 334 /* edge triggered */
402 spin_lock_irqsave(&ip32_irq_lock, flags);
403 mace_int = mace->perif.ctrl.istat; 335 mace_int = mace->perif.ctrl.istat;
404 mace_int &= ~(1 << (irq - 33)); 336 mace_int &= ~(1 << (irq - 33));
405 mace->perif.ctrl.istat = mace_int; 337 mace->perif.ctrl.istat = mace_int;
406 spin_unlock_irqrestore(&ip32_irq_lock, flags);
407 break; 338 break;
408 } 339 }
409 disable_maceisa_irq(irq); 340 disable_maceisa_irq(irq);
@@ -415,15 +346,12 @@ static void end_maceisa_irq(unsigned irq)
415 enable_maceisa_irq(irq); 346 enable_maceisa_irq(irq);
416} 347}
417 348
418#define shutdown_maceisa_irq disable_maceisa_irq
419
420static struct irq_chip ip32_maceisa_interrupt = { 349static struct irq_chip ip32_maceisa_interrupt = {
421 .typename = "IP32 MACE ISA", 350 .typename = "IP32 MACE ISA",
422 .startup = startup_maceisa_irq,
423 .shutdown = shutdown_maceisa_irq,
424 .enable = enable_maceisa_irq,
425 .disable = disable_maceisa_irq,
426 .ack = mask_and_ack_maceisa_irq, 351 .ack = mask_and_ack_maceisa_irq,
352 .mask = disable_maceisa_irq,
353 .mask_ack = mask_and_ack_maceisa_irq,
354 .unmask = enable_maceisa_irq,
427 .end = end_maceisa_irq, 355 .end = end_maceisa_irq,
428}; 356};
429 357
@@ -433,29 +361,15 @@ static struct irq_chip ip32_maceisa_interrupt = {
433 361
434static void enable_mace_irq(unsigned int irq) 362static void enable_mace_irq(unsigned int irq)
435{ 363{
436 unsigned long flags;
437
438 spin_lock_irqsave(&ip32_irq_lock, flags);
439 crime_mask |= 1 << (irq - 1); 364 crime_mask |= 1 << (irq - 1);
440 crime->imask = crime_mask; 365 crime->imask = crime_mask;
441 spin_unlock_irqrestore(&ip32_irq_lock, flags);
442}
443
444static unsigned int startup_mace_irq(unsigned int irq)
445{
446 enable_mace_irq(irq);
447 return 0;
448} 366}
449 367
450static void disable_mace_irq(unsigned int irq) 368static void disable_mace_irq(unsigned int irq)
451{ 369{
452 unsigned long flags;
453
454 spin_lock_irqsave(&ip32_irq_lock, flags);
455 crime_mask &= ~(1 << (irq - 1)); 370 crime_mask &= ~(1 << (irq - 1));
456 crime->imask = crime_mask; 371 crime->imask = crime_mask;
457 flush_crime_bus(); 372 flush_crime_bus();
458 spin_unlock_irqrestore(&ip32_irq_lock, flags);
459} 373}
460 374
461static void end_mace_irq(unsigned int irq) 375static void end_mace_irq(unsigned int irq)
@@ -464,16 +378,12 @@ static void end_mace_irq(unsigned int irq)
464 enable_mace_irq(irq); 378 enable_mace_irq(irq);
465} 379}
466 380
467#define shutdown_mace_irq disable_mace_irq
468#define mask_and_ack_mace_irq disable_mace_irq
469
470static struct irq_chip ip32_mace_interrupt = { 381static struct irq_chip ip32_mace_interrupt = {
471 .typename = "IP32 MACE", 382 .typename = "IP32 MACE",
472 .startup = startup_mace_irq, 383 .ack = disable_mace_irq,
473 .shutdown = shutdown_mace_irq, 384 .mask = disable_mace_irq,
474 .enable = enable_mace_irq, 385 .mask_ack = disable_mace_irq,
475 .disable = disable_mace_irq, 386 .unmask = enable_mace_irq,
476 .ack = mask_and_ack_mace_irq,
477 .end = end_mace_irq, 387 .end = end_mace_irq,
478}; 388};
479 389
@@ -586,10 +496,7 @@ void __init arch_init_irq(void)
586 else 496 else
587 controller = &ip32_maceisa_interrupt; 497 controller = &ip32_maceisa_interrupt;
588 498
589 irq_desc[irq].status = IRQ_DISABLED; 499 set_irq_chip(irq, controller);
590 irq_desc[irq].action = 0;
591 irq_desc[irq].depth = 0;
592 irq_desc[irq].chip = controller;
593 } 500 }
594 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); 501 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
595 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); 502 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
diff --git a/arch/mips/sgi-ip32/ip32-reset.c b/arch/mips/sgi-ip32/ip32-reset.c
index fd0932b2d521..db8084411538 100644
--- a/arch/mips/sgi-ip32/ip32-reset.c
+++ b/arch/mips/sgi-ip32/ip32-reset.c
@@ -135,7 +135,7 @@ static inline void ip32_power_button(void)
135 add_timer(&power_timer); 135 add_timer(&power_timer);
136} 136}
137 137
138static irqreturn_t ip32_rtc_int(int irq, void *dev_id, struct pt_regs *regs) 138static irqreturn_t ip32_rtc_int(int irq, void *dev_id)
139{ 139{
140 volatile unsigned char reg_c; 140 volatile unsigned char reg_c;
141 141
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 8b1f41484923..2e8f6b2e2420 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -45,11 +45,9 @@
45 */ 45 */
46 46
47 47
48#define shutdown_bcm1480_irq disable_bcm1480_irq
49static void end_bcm1480_irq(unsigned int irq); 48static void end_bcm1480_irq(unsigned int irq);
50static void enable_bcm1480_irq(unsigned int irq); 49static void enable_bcm1480_irq(unsigned int irq);
51static void disable_bcm1480_irq(unsigned int irq); 50static void disable_bcm1480_irq(unsigned int irq);
52static unsigned int startup_bcm1480_irq(unsigned int irq);
53static void ack_bcm1480_irq(unsigned int irq); 51static void ack_bcm1480_irq(unsigned int irq);
54#ifdef CONFIG_SMP 52#ifdef CONFIG_SMP
55static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask); 53static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
@@ -85,11 +83,10 @@ extern char sb1250_duart_present[];
85 83
86static struct irq_chip bcm1480_irq_type = { 84static struct irq_chip bcm1480_irq_type = {
87 .typename = "BCM1480-IMR", 85 .typename = "BCM1480-IMR",
88 .startup = startup_bcm1480_irq,
89 .shutdown = shutdown_bcm1480_irq,
90 .enable = enable_bcm1480_irq,
91 .disable = disable_bcm1480_irq,
92 .ack = ack_bcm1480_irq, 86 .ack = ack_bcm1480_irq,
87 .mask = disable_bcm1480_irq,
88 .mask_ack = ack_bcm1480_irq,
89 .unmask = enable_bcm1480_irq,
93 .end = end_bcm1480_irq, 90 .end = end_bcm1480_irq,
94#ifdef CONFIG_SMP 91#ifdef CONFIG_SMP
95 .set_affinity = bcm1480_set_affinity 92 .set_affinity = bcm1480_set_affinity
@@ -188,14 +185,6 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
188 185
189/*****************************************************************************/ 186/*****************************************************************************/
190 187
191static unsigned int startup_bcm1480_irq(unsigned int irq)
192{
193 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
194
195 return 0; /* never anything pending */
196}
197
198
199static void disable_bcm1480_irq(unsigned int irq) 188static void disable_bcm1480_irq(unsigned int irq)
200{ 189{
201 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 190 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
@@ -270,16 +259,9 @@ void __init init_bcm1480_irqs(void)
270{ 259{
271 int i; 260 int i;
272 261
273 for (i = 0; i < NR_IRQS; i++) { 262 for (i = 0; i < BCM1480_NR_IRQS; i++) {
274 irq_desc[i].status = IRQ_DISABLED; 263 set_irq_chip(i, &bcm1480_irq_type);
275 irq_desc[i].action = 0; 264 bcm1480_irq_owner[i] = 0;
276 irq_desc[i].depth = 1;
277 if (i < BCM1480_NR_IRQS) {
278 irq_desc[i].chip = &bcm1480_irq_type;
279 bcm1480_irq_owner[i] = 0;
280 } else {
281 irq_desc[i].chip = &no_irq_chip;
282 }
283 } 265 }
284} 266}
285 267
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index bf12af46132e..6f3f71bf4244 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -47,6 +47,12 @@
47#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 47#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
48#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 48#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
49 49
50#ifdef CONFIG_SIMULATION
51#define BCM1480_HPT_VALUE 50000
52#else
53#define BCM1480_HPT_VALUE 1000000
54#endif
55
50extern int bcm1480_steal_irq(int irq); 56extern int bcm1480_steal_irq(int irq);
51 57
52void bcm1480_time_init(void) 58void bcm1480_time_init(void)
@@ -59,11 +65,6 @@ void bcm1480_time_init(void)
59 BUG(); 65 BUG();
60 } 66 }
61 67
62 if (!cpu) {
63 /* Use our own gettimeoffset() routine */
64 do_gettimeoffset = bcm1480_gettimeoffset;
65 }
66
67 bcm1480_mask_irq(cpu, irq); 68 bcm1480_mask_irq(cpu, irq);
68 69
69 /* Map the timer interrupt to ip[4] of this cpu */ 70 /* Map the timer interrupt to ip[4] of this cpu */
@@ -74,11 +75,7 @@ void bcm1480_time_init(void)
74 /* Disable the timer and set up the count */ 75 /* Disable the timer and set up the count */
75 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 76 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
76 __raw_writeq( 77 __raw_writeq(
77#ifndef CONFIG_SIMULATION 78 BCM1480_HPT_VALUE/HZ
78 1000000/HZ
79#else
80 50000/HZ
81#endif
82 , IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); 79 , IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
83 80
84 /* Set the timer running */ 81 /* Set the timer running */
@@ -97,8 +94,6 @@ void bcm1480_time_init(void)
97 */ 94 */
98} 95}
99 96
100#include <asm/sibyte/sb1250.h>
101
102void bcm1480_timer_interrupt(void) 97void bcm1480_timer_interrupt(void)
103{ 98{
104 int cpu = smp_processor_id(); 99 int cpu = smp_processor_id();
@@ -122,16 +117,16 @@ void bcm1480_timer_interrupt(void)
122 } 117 }
123} 118}
124 119
125/* 120static cycle_t bcm1480_hpt_read(void)
126 * We use our own do_gettimeoffset() instead of the generic one,
127 * because the generic one does not work for SMP case.
128 * In addition, since we use general timer 0 for system time,
129 * we can get accurate intra-jiffy offset without calibration.
130 */
131unsigned long bcm1480_gettimeoffset(void)
132{ 121{
122 /* We assume this function is called xtime_lock held. */
133 unsigned long count = 123 unsigned long count =
134 __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); 124 __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
125 return (jiffies + 1) * (BCM1480_HPT_VALUE / HZ) - count;
126}
135 127
136 return 1000000/HZ - count; 128void __init bcm1480_hpt_setup(void)
129{
130 clocksource_mips.read = bcm1480_hpt_read;
131 mips_hpt_frequency = BCM1480_HPT_VALUE;
137} 132}
diff --git a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
index 992e0d8dbb67..d1a906e683b2 100644
--- a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
+++ b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
@@ -88,7 +88,7 @@ static void arm_tb(void)
88 sbp.tb_armed = 1; 88 sbp.tb_armed = 1;
89} 89}
90 90
91static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs) 91static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
92{ 92{
93 int i; 93 int i;
94 DBG(printk(DEVNAME ": tb_intr\n")); 94 DBG(printk(DEVNAME ": tb_intr\n"));
@@ -138,7 +138,7 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs)
138 return IRQ_HANDLED; 138 return IRQ_HANDLED;
139} 139}
140 140
141static irqreturn_t sbprof_pc_intr(int irq, void *dev_id, struct pt_regs *regs) 141static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
142{ 142{
143 printk(DEVNAME ": unexpected pc_intr"); 143 printk(DEVNAME ": unexpected pc_intr");
144 return IRQ_NONE; 144 return IRQ_NONE;
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c
index bb90649fbc48..45274bd3cd8b 100644
--- a/arch/mips/sibyte/sb1250/bus_watcher.c
+++ b/arch/mips/sibyte/sb1250/bus_watcher.c
@@ -171,7 +171,7 @@ static void create_proc_decoder(struct bw_stats_struct *stats)
171 * notes: possible re-entry due to multiple sources 171 * notes: possible re-entry due to multiple sources
172 * should check/indicate saturation 172 * should check/indicate saturation
173 */ 173 */
174static irqreturn_t sibyte_bw_int(int irq, void *data, struct pt_regs *regs) 174static irqreturn_t sibyte_bw_int(int irq, void *data)
175{ 175{
176 struct bw_stats_struct *stats = data; 176 struct bw_stats_struct *stats = data;
177 unsigned long cntr; 177 unsigned long cntr;
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index d5d26770daf6..82ce7533053f 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -44,11 +44,9 @@
44 */ 44 */
45 45
46 46
47#define shutdown_sb1250_irq disable_sb1250_irq
48static void end_sb1250_irq(unsigned int irq); 47static void end_sb1250_irq(unsigned int irq);
49static void enable_sb1250_irq(unsigned int irq); 48static void enable_sb1250_irq(unsigned int irq);
50static void disable_sb1250_irq(unsigned int irq); 49static void disable_sb1250_irq(unsigned int irq);
51static unsigned int startup_sb1250_irq(unsigned int irq);
52static void ack_sb1250_irq(unsigned int irq); 50static void ack_sb1250_irq(unsigned int irq);
53#ifdef CONFIG_SMP 51#ifdef CONFIG_SMP
54static void sb1250_set_affinity(unsigned int irq, cpumask_t mask); 52static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
@@ -70,11 +68,10 @@ extern char sb1250_duart_present[];
70 68
71static struct irq_chip sb1250_irq_type = { 69static struct irq_chip sb1250_irq_type = {
72 .typename = "SB1250-IMR", 70 .typename = "SB1250-IMR",
73 .startup = startup_sb1250_irq,
74 .shutdown = shutdown_sb1250_irq,
75 .enable = enable_sb1250_irq,
76 .disable = disable_sb1250_irq,
77 .ack = ack_sb1250_irq, 71 .ack = ack_sb1250_irq,
72 .mask = disable_sb1250_irq,
73 .mask_ack = ack_sb1250_irq,
74 .unmask = enable_sb1250_irq,
78 .end = end_sb1250_irq, 75 .end = end_sb1250_irq,
79#ifdef CONFIG_SMP 76#ifdef CONFIG_SMP
80 .set_affinity = sb1250_set_affinity 77 .set_affinity = sb1250_set_affinity
@@ -163,14 +160,6 @@ static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
163 160
164/*****************************************************************************/ 161/*****************************************************************************/
165 162
166static unsigned int startup_sb1250_irq(unsigned int irq)
167{
168 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
169
170 return 0; /* never anything pending */
171}
172
173
174static void disable_sb1250_irq(unsigned int irq) 163static void disable_sb1250_irq(unsigned int irq)
175{ 164{
176 sb1250_mask_irq(sb1250_irq_owner[irq], irq); 165 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
@@ -239,16 +228,9 @@ void __init init_sb1250_irqs(void)
239{ 228{
240 int i; 229 int i;
241 230
242 for (i = 0; i < NR_IRQS; i++) { 231 for (i = 0; i < SB1250_NR_IRQS; i++) {
243 irq_desc[i].status = IRQ_DISABLED; 232 set_irq_chip(i, &sb1250_irq_type);
244 irq_desc[i].action = 0; 233 sb1250_irq_owner[i] = 0;
245 irq_desc[i].depth = 1;
246 if (i < SB1250_NR_IRQS) {
247 irq_desc[i].chip = &sb1250_irq_type;
248 sb1250_irq_owner[i] = 0;
249 } else {
250 irq_desc[i].chip = &no_irq_chip;
251 }
252 } 234 }
253} 235}
254 236
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 0ccf1796dd78..2efffe15ff23 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -47,15 +47,11 @@
47 47
48#define SB1250_HPT_NUM 3 48#define SB1250_HPT_NUM 3
49#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */ 49#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
50#define SB1250_HPT_SHIFT ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH)
51 50
52 51
53extern int sb1250_steal_irq(int irq); 52extern int sb1250_steal_irq(int irq);
54 53
55static unsigned int sb1250_hpt_read(void); 54static cycle_t sb1250_hpt_read(void);
56static void sb1250_hpt_init(unsigned int);
57
58static unsigned int hpt_offset;
59 55
60void __init sb1250_hpt_setup(void) 56void __init sb1250_hpt_setup(void)
61{ 57{
@@ -69,13 +65,9 @@ void __init sb1250_hpt_setup(void)
69 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, 65 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
70 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); 66 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
71 67
72 /* 68 mips_hpt_frequency = V_SCD_TIMER_FREQ;
73 * we need to fill 32 bits, so just use the upper 23 bits and pretend 69 clocksource_mips.read = sb1250_hpt_read;
74 * the timer is going 512Mhz instead of 1Mhz 70 clocksource_mips.mask = M_SCD_TIMER_INIT;
75 */
76 mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT;
77 mips_hpt_init = sb1250_hpt_init;
78 mips_hpt_read = sb1250_hpt_read;
79 } 71 }
80} 72}
81 73
@@ -149,25 +141,13 @@ void sb1250_timer_interrupt(void)
149 141
150/* 142/*
151 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over 143 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
152 * again. There's no easy way to set to a specific value so store init value 144 * again.
153 * in hpt_offset and subtract each time.
154 *
155 * Note: Timer isn't full 32bits so shift it into the upper part making
156 * it appear to run at a higher frequency.
157 */ 145 */
158static unsigned int sb1250_hpt_read(void) 146static cycle_t sb1250_hpt_read(void)
159{ 147{
160 unsigned int count; 148 unsigned int count;
161 149
162 count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT)))); 150 count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
163 151
164 count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT; 152 return SB1250_HPT_VALUE - count;
165
166 return count - hpt_offset;
167}
168
169static void sb1250_hpt_init(unsigned int count)
170{
171 hpt_offset = count;
172 return;
173} 153}
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 48fb74a7aaec..8511bcc6d99d 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -11,44 +11,25 @@
11#include <linux/interrupt.h> 11#include <linux/interrupt.h>
12#include <linux/irq.h> 12#include <linux/irq.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/spinlock.h>
15 14
16#include <asm/i8259.h> 15#include <asm/i8259.h>
17#include <asm/io.h> 16#include <asm/io.h>
18#include <asm/sni.h> 17#include <asm/sni.h>
19 18
20DEFINE_SPINLOCK(pciasic_lock);
21
22static void enable_pciasic_irq(unsigned int irq) 19static void enable_pciasic_irq(unsigned int irq)
23{ 20{
24 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); 21 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
25 unsigned long flags;
26 22
27 spin_lock_irqsave(&pciasic_lock, flags);
28 *(volatile u8 *) PCIMT_IRQSEL |= mask; 23 *(volatile u8 *) PCIMT_IRQSEL |= mask;
29 spin_unlock_irqrestore(&pciasic_lock, flags);
30}
31
32static unsigned int startup_pciasic_irq(unsigned int irq)
33{
34 enable_pciasic_irq(irq);
35 return 0; /* never anything pending */
36} 24}
37 25
38#define shutdown_pciasic_irq disable_pciasic_irq
39
40void disable_pciasic_irq(unsigned int irq) 26void disable_pciasic_irq(unsigned int irq)
41{ 27{
42 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2)); 28 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
43 unsigned long flags;
44 29
45 spin_lock_irqsave(&pciasic_lock, flags);
46 *(volatile u8 *) PCIMT_IRQSEL &= mask; 30 *(volatile u8 *) PCIMT_IRQSEL &= mask;
47 spin_unlock_irqrestore(&pciasic_lock, flags);
48} 31}
49 32
50#define mask_and_ack_pciasic_irq disable_pciasic_irq
51
52static void end_pciasic_irq(unsigned int irq) 33static void end_pciasic_irq(unsigned int irq)
53{ 34{
54 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 35 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -57,11 +38,10 @@ static void end_pciasic_irq(unsigned int irq)
57 38
58static struct irq_chip pciasic_irq_type = { 39static struct irq_chip pciasic_irq_type = {
59 .typename = "ASIC-PCI", 40 .typename = "ASIC-PCI",
60 .startup = startup_pciasic_irq, 41 .ack = disable_pciasic_irq,
61 .shutdown = shutdown_pciasic_irq, 42 .mask = disable_pciasic_irq,
62 .enable = enable_pciasic_irq, 43 .mask_ack = disable_pciasic_irq,
63 .disable = disable_pciasic_irq, 44 .unmask = enable_pciasic_irq,
64 .ack = mask_and_ack_pciasic_irq,
65 .end = end_pciasic_irq, 45 .end = end_pciasic_irq,
66}; 46};
67 47
@@ -178,12 +158,8 @@ asmlinkage void plat_irq_dispatch(void)
178 158
179void __init init_pciasic(void) 159void __init init_pciasic(void)
180{ 160{
181 unsigned long flags;
182
183 spin_lock_irqsave(&pciasic_lock, flags);
184 * (volatile u8 *) PCIMT_IRQSEL = 161 * (volatile u8 *) PCIMT_IRQSEL =
185 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD; 162 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
186 spin_unlock_irqrestore(&pciasic_lock, flags);
187} 163}
188 164
189/* 165/*
@@ -199,12 +175,8 @@ void __init arch_init_irq(void)
199 init_pciasic(); 175 init_pciasic();
200 176
201 /* Actually we've got more interrupts to handle ... */ 177 /* Actually we've got more interrupts to handle ... */
202 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) { 178 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++)
203 irq_desc[i].status = IRQ_DISABLED; 179 set_irq_chip(i, &pciasic_irq_type);
204 irq_desc[i].action = 0;
205 irq_desc[i].depth = 1;
206 irq_desc[i].chip = &pciasic_irq_type;
207 }
208 180
209 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); 181 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
210} 182}
diff --git a/arch/mips/tx4927/common/smsc_fdc37m81x.c b/arch/mips/tx4927/common/smsc_fdc37m81x.c
new file mode 100644
index 000000000000..33f517bc9a08
--- /dev/null
+++ b/arch/mips/tx4927/common/smsc_fdc37m81x.c
@@ -0,0 +1,172 @@
1/*
2 * Interface for smsc fdc48m81x Super IO chip
3 *
4 * Author: MontaVista Software, Inc. source@mvista.com
5 *
6 * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Copyright 2004 (c) MontaVista Software, Inc.
12 */
13#include <linux/init.h>
14#include <linux/types.h>
15#include <asm/io.h>
16#include <asm/tx4927/smsc_fdc37m81x.h>
17
18#define DEBUG
19
20/* Common Registers */
21#define SMSC_FDC37M81X_CONFIG_INDEX 0x00
22#define SMSC_FDC37M81X_CONFIG_DATA 0x01
23#define SMSC_FDC37M81X_CONF 0x02
24#define SMSC_FDC37M81X_INDEX 0x03
25#define SMSC_FDC37M81X_DNUM 0x07
26#define SMSC_FDC37M81X_DID 0x20
27#define SMSC_FDC37M81X_DREV 0x21
28#define SMSC_FDC37M81X_PCNT 0x22
29#define SMSC_FDC37M81X_PMGT 0x23
30#define SMSC_FDC37M81X_OSC 0x24
31#define SMSC_FDC37M81X_CONFPA0 0x26
32#define SMSC_FDC37M81X_CONFPA1 0x27
33#define SMSC_FDC37M81X_TEST4 0x2B
34#define SMSC_FDC37M81X_TEST5 0x2C
35#define SMSC_FDC37M81X_TEST1 0x2D
36#define SMSC_FDC37M81X_TEST2 0x2E
37#define SMSC_FDC37M81X_TEST3 0x2F
38
39/* Logical device numbers */
40#define SMSC_FDC37M81X_FDD 0x00
41#define SMSC_FDC37M81X_SERIAL1 0x04
42#define SMSC_FDC37M81X_SERIAL2 0x05
43#define SMSC_FDC37M81X_KBD 0x07
44
45/* Logical device Config Registers */
46#define SMSC_FDC37M81X_ACTIVE 0x30
47#define SMSC_FDC37M81X_BASEADDR0 0x60
48#define SMSC_FDC37M81X_BASEADDR1 0x61
49#define SMSC_FDC37M81X_INT 0x70
50#define SMSC_FDC37M81X_INT2 0x72
51#define SMSC_FDC37M81X_MODE 0xF0
52
53/* Chip Config Values */
54#define SMSC_FDC37M81X_CONFIG_ENTER 0x55
55#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
56#define SMSC_FDC37M81X_CHIP_ID 0x4d
57
58static unsigned long g_smsc_fdc37m81x_base = 0;
59
60static inline unsigned char smsc_fdc37m81x_rd(unsigned char index)
61{
62 outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
63
64 return inb(g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA);
65}
66
67static inline void smsc_dc37m81x_wr(unsigned char index, unsigned char data)
68{
69 outb(index, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
70 outb(data, g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_DATA);
71}
72
73void smsc_fdc37m81x_config_beg(void)
74{
75 if (g_smsc_fdc37m81x_base) {
76 outb(SMSC_FDC37M81X_CONFIG_ENTER,
77 g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
78 }
79}
80
81void smsc_fdc37m81x_config_end(void)
82{
83 if (g_smsc_fdc37m81x_base)
84 outb(SMSC_FDC37M81X_CONFIG_EXIT,
85 g_smsc_fdc37m81x_base + SMSC_FDC37M81X_CONFIG_INDEX);
86}
87
88u8 smsc_fdc37m81x_config_get(u8 reg)
89{
90 u8 val = 0;
91
92 if (g_smsc_fdc37m81x_base)
93 val = smsc_fdc37m81x_rd(reg);
94
95 return val;
96}
97
98void smsc_fdc37m81x_config_set(u8 reg, u8 val)
99{
100 if (g_smsc_fdc37m81x_base)
101 smsc_dc37m81x_wr(reg, val);
102}
103
104unsigned long __init smsc_fdc37m81x_init(unsigned long port)
105{
106 const int field = sizeof(unsigned long) * 2;
107 u8 chip_id;
108
109 if (g_smsc_fdc37m81x_base)
110 printk("smsc_fdc37m81x_init() stepping on old base=0x%0*lx\n",
111 field, g_smsc_fdc37m81x_base);
112
113 g_smsc_fdc37m81x_base = port;
114
115 smsc_fdc37m81x_config_beg();
116
117 chip_id = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DID);
118 if (chip_id == SMSC_FDC37M81X_CHIP_ID)
119 smsc_fdc37m81x_config_end();
120 else {
121 printk("smsc_fdc37m81x_init() unknow chip id 0x%02x\n",
122 chip_id);
123 g_smsc_fdc37m81x_base = 0;
124 }
125
126 return g_smsc_fdc37m81x_base;
127}
128
129#ifdef DEBUG
130void smsc_fdc37m81x_config_dump_one(char *key, u8 dev, u8 reg)
131{
132 printk("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg,
133 smsc_fdc37m81x_rd(reg));
134}
135
136void smsc_fdc37m81x_config_dump(void)
137{
138 u8 orig;
139 char *fname = "smsc_fdc37m81x_config_dump()";
140
141 smsc_fdc37m81x_config_beg();
142
143 orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM);
144
145 printk("%s: common\n", fname);
146 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
147 SMSC_FDC37M81X_DNUM);
148 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
149 SMSC_FDC37M81X_DID);
150 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
151 SMSC_FDC37M81X_DREV);
152 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
153 SMSC_FDC37M81X_PCNT);
154 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
155 SMSC_FDC37M81X_PMGT);
156
157 printk("%s: keyboard\n", fname);
158 smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD);
159 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
160 SMSC_FDC37M81X_ACTIVE);
161 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
162 SMSC_FDC37M81X_INT);
163 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
164 SMSC_FDC37M81X_INT2);
165 smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
166 SMSC_FDC37M81X_LDCR_F0);
167
168 smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, orig);
169
170 smsc_fdc37m81x_config_end();
171}
172#endif
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index 8266a88a3f88..21873de49aa8 100644
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -64,19 +64,13 @@
64#define TX4927_IRQ_NEST4 ( 1 << 9 ) 64#define TX4927_IRQ_NEST4 ( 1 << 9 )
65 65
66#define TX4927_IRQ_CP0_INIT ( 1 << 10 ) 66#define TX4927_IRQ_CP0_INIT ( 1 << 10 )
67#define TX4927_IRQ_CP0_STARTUP ( 1 << 11 )
68#define TX4927_IRQ_CP0_SHUTDOWN ( 1 << 12 )
69#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 ) 67#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 )
70#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 ) 68#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 )
71#define TX4927_IRQ_CP0_MASK ( 1 << 15 )
72#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 ) 69#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 )
73 70
74#define TX4927_IRQ_PIC_INIT ( 1 << 20 ) 71#define TX4927_IRQ_PIC_INIT ( 1 << 20 )
75#define TX4927_IRQ_PIC_STARTUP ( 1 << 21 )
76#define TX4927_IRQ_PIC_SHUTDOWN ( 1 << 22 )
77#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 ) 72#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 )
78#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 ) 73#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 )
79#define TX4927_IRQ_PIC_MASK ( 1 << 25 )
80#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 ) 74#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 )
81 75
82#define TX4927_IRQ_ALL 0xffffffff 76#define TX4927_IRQ_ALL 0xffffffff
@@ -87,18 +81,12 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
87 | TX4927_IRQ_INFO 81 | TX4927_IRQ_INFO
88 | TX4927_IRQ_WARN | TX4927_IRQ_EROR 82 | TX4927_IRQ_WARN | TX4927_IRQ_EROR
89// | TX4927_IRQ_CP0_INIT 83// | TX4927_IRQ_CP0_INIT
90// | TX4927_IRQ_CP0_STARTUP
91// | TX4927_IRQ_CP0_SHUTDOWN
92// | TX4927_IRQ_CP0_ENABLE 84// | TX4927_IRQ_CP0_ENABLE
93// | TX4927_IRQ_CP0_DISABLE 85// | TX4927_IRQ_CP0_DISABLE
94// | TX4927_IRQ_CP0_MASK
95// | TX4927_IRQ_CP0_ENDIRQ 86// | TX4927_IRQ_CP0_ENDIRQ
96// | TX4927_IRQ_PIC_INIT 87// | TX4927_IRQ_PIC_INIT
97// | TX4927_IRQ_PIC_STARTUP
98// | TX4927_IRQ_PIC_SHUTDOWN
99// | TX4927_IRQ_PIC_ENABLE 88// | TX4927_IRQ_PIC_ENABLE
100// | TX4927_IRQ_PIC_DISABLE 89// | TX4927_IRQ_PIC_DISABLE
101// | TX4927_IRQ_PIC_MASK
102// | TX4927_IRQ_PIC_ENDIRQ 90// | TX4927_IRQ_PIC_ENDIRQ
103// | TX4927_IRQ_INIT 91// | TX4927_IRQ_INIT
104// | TX4927_IRQ_NEST1 92// | TX4927_IRQ_NEST1
@@ -124,49 +112,36 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
124 * Forwad definitions for all pic's 112 * Forwad definitions for all pic's
125 */ 113 */
126 114
127static unsigned int tx4927_irq_cp0_startup(unsigned int irq);
128static void tx4927_irq_cp0_shutdown(unsigned int irq);
129static void tx4927_irq_cp0_enable(unsigned int irq); 115static void tx4927_irq_cp0_enable(unsigned int irq);
130static void tx4927_irq_cp0_disable(unsigned int irq); 116static void tx4927_irq_cp0_disable(unsigned int irq);
131static void tx4927_irq_cp0_mask_and_ack(unsigned int irq);
132static void tx4927_irq_cp0_end(unsigned int irq); 117static void tx4927_irq_cp0_end(unsigned int irq);
133 118
134static unsigned int tx4927_irq_pic_startup(unsigned int irq);
135static void tx4927_irq_pic_shutdown(unsigned int irq);
136static void tx4927_irq_pic_enable(unsigned int irq); 119static void tx4927_irq_pic_enable(unsigned int irq);
137static void tx4927_irq_pic_disable(unsigned int irq); 120static void tx4927_irq_pic_disable(unsigned int irq);
138static void tx4927_irq_pic_mask_and_ack(unsigned int irq);
139static void tx4927_irq_pic_end(unsigned int irq); 121static void tx4927_irq_pic_end(unsigned int irq);
140 122
141/* 123/*
142 * Kernel structs for all pic's 124 * Kernel structs for all pic's
143 */ 125 */
144 126
145static DEFINE_SPINLOCK(tx4927_cp0_lock);
146static DEFINE_SPINLOCK(tx4927_pic_lock);
147
148#define TX4927_CP0_NAME "TX4927-CP0" 127#define TX4927_CP0_NAME "TX4927-CP0"
149static struct irq_chip tx4927_irq_cp0_type = { 128static struct irq_chip tx4927_irq_cp0_type = {
150 .typename = TX4927_CP0_NAME, 129 .typename = TX4927_CP0_NAME,
151 .startup = tx4927_irq_cp0_startup, 130 .ack = tx4927_irq_cp0_disable,
152 .shutdown = tx4927_irq_cp0_shutdown, 131 .mask = tx4927_irq_cp0_disable,
153 .enable = tx4927_irq_cp0_enable, 132 .mask_ack = tx4927_irq_cp0_disable,
154 .disable = tx4927_irq_cp0_disable, 133 .unmask = tx4927_irq_cp0_enable,
155 .ack = tx4927_irq_cp0_mask_and_ack,
156 .end = tx4927_irq_cp0_end, 134 .end = tx4927_irq_cp0_end,
157 .set_affinity = NULL
158}; 135};
159 136
160#define TX4927_PIC_NAME "TX4927-PIC" 137#define TX4927_PIC_NAME "TX4927-PIC"
161static struct irq_chip tx4927_irq_pic_type = { 138static struct irq_chip tx4927_irq_pic_type = {
162 .typename = TX4927_PIC_NAME, 139 .typename = TX4927_PIC_NAME,
163 .startup = tx4927_irq_pic_startup, 140 .ack = tx4927_irq_pic_disable,
164 .shutdown = tx4927_irq_pic_shutdown, 141 .mask = tx4927_irq_pic_disable,
165 .enable = tx4927_irq_pic_enable, 142 .mask_ack = tx4927_irq_pic_disable,
166 .disable = tx4927_irq_pic_disable, 143 .unmask = tx4927_irq_pic_enable,
167 .ack = tx4927_irq_pic_mask_and_ack,
168 .end = tx4927_irq_pic_end, 144 .end = tx4927_irq_pic_end,
169 .set_affinity = NULL
170}; 145};
171 146
172#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } 147#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
@@ -211,8 +186,6 @@ tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits)
211 break; 186 break;
212 } 187 }
213 } 188 }
214
215 return;
216} 189}
217 190
218static void __init tx4927_irq_cp0_init(void) 191static void __init tx4927_irq_cp0_init(void)
@@ -222,71 +195,23 @@ static void __init tx4927_irq_cp0_init(void)
222 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n", 195 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n",
223 TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END); 196 TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END);
224 197
225 for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) { 198 for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++)
226 irq_desc[i].status = IRQ_DISABLED; 199 set_irq_chip_and_handler(i, &tx4927_irq_cp0_type,
227 irq_desc[i].action = 0; 200 handle_level_irq);
228 irq_desc[i].depth = 1;
229 irq_desc[i].chip = &tx4927_irq_cp0_type;
230 }
231
232 return;
233}
234
235static unsigned int tx4927_irq_cp0_startup(unsigned int irq)
236{
237 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_STARTUP, "irq=%d \n", irq);
238
239 tx4927_irq_cp0_enable(irq);
240
241 return (0);
242}
243
244static void tx4927_irq_cp0_shutdown(unsigned int irq)
245{
246 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_SHUTDOWN, "irq=%d \n", irq);
247
248 tx4927_irq_cp0_disable(irq);
249
250 return;
251} 201}
252 202
253static void tx4927_irq_cp0_enable(unsigned int irq) 203static void tx4927_irq_cp0_enable(unsigned int irq)
254{ 204{
255 unsigned long flags;
256
257 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq); 205 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq);
258 206
259 spin_lock_irqsave(&tx4927_cp0_lock, flags);
260
261 tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq)); 207 tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq));
262
263 spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
264
265 return;
266} 208}
267 209
268static void tx4927_irq_cp0_disable(unsigned int irq) 210static void tx4927_irq_cp0_disable(unsigned int irq)
269{ 211{
270 unsigned long flags;
271
272 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq); 212 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq);
273 213
274 spin_lock_irqsave(&tx4927_cp0_lock, flags);
275
276 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0); 214 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0);
277
278 spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
279
280 return;
281}
282
283static void tx4927_irq_cp0_mask_and_ack(unsigned int irq)
284{
285 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_MASK, "irq=%d \n", irq);
286
287 tx4927_irq_cp0_disable(irq);
288
289 return;
290} 215}
291 216
292static void tx4927_irq_cp0_end(unsigned int irq) 217static void tx4927_irq_cp0_end(unsigned int irq)
@@ -296,8 +221,6 @@ static void tx4927_irq_cp0_end(unsigned int irq)
296 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 221 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
297 tx4927_irq_cp0_enable(irq); 222 tx4927_irq_cp0_enable(irq);
298 } 223 }
299
300 return;
301} 224}
302 225
303/* 226/*
@@ -418,94 +341,39 @@ static void tx4927_irq_pic_modify(unsigned pic_reg, unsigned clr_bits,
418 val &= (~clr_bits); 341 val &= (~clr_bits);
419 val |= (set_bits); 342 val |= (set_bits);
420 TX4927_WR(pic_reg, val); 343 TX4927_WR(pic_reg, val);
421
422 return;
423} 344}
424 345
425static void __init tx4927_irq_pic_init(void) 346static void __init tx4927_irq_pic_init(void)
426{ 347{
427 unsigned long flags;
428 int i; 348 int i;
429 349
430 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n", 350 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n",
431 TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END); 351 TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END);
432 352
433 for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) { 353 for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++)
434 irq_desc[i].status = IRQ_DISABLED; 354 set_irq_chip_and_handler(i, &tx4927_irq_pic_type,
435 irq_desc[i].action = 0; 355 handle_level_irq);
436 irq_desc[i].depth = 2;
437 irq_desc[i].chip = &tx4927_irq_pic_type;
438 }
439 356
440 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); 357 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action);
441 358
442 spin_lock_irqsave(&tx4927_pic_lock, flags);
443
444 TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ 359 TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
445 TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */ 360 TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */
446
447 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
448
449 return;
450}
451
452static unsigned int tx4927_irq_pic_startup(unsigned int irq)
453{
454 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_STARTUP, "irq=%d\n", irq);
455
456 tx4927_irq_pic_enable(irq);
457
458 return (0);
459}
460
461static void tx4927_irq_pic_shutdown(unsigned int irq)
462{
463 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_SHUTDOWN, "irq=%d\n", irq);
464
465 tx4927_irq_pic_disable(irq);
466
467 return;
468} 361}
469 362
470static void tx4927_irq_pic_enable(unsigned int irq) 363static void tx4927_irq_pic_enable(unsigned int irq)
471{ 364{
472 unsigned long flags;
473
474 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq); 365 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq);
475 366
476 spin_lock_irqsave(&tx4927_pic_lock, flags);
477
478 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0, 367 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0,
479 tx4927_irq_pic_mask(irq)); 368 tx4927_irq_pic_mask(irq));
480
481 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
482
483 return;
484} 369}
485 370
486static void tx4927_irq_pic_disable(unsigned int irq) 371static void tx4927_irq_pic_disable(unsigned int irq)
487{ 372{
488 unsigned long flags;
489
490 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq); 373 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq);
491 374
492 spin_lock_irqsave(&tx4927_pic_lock, flags);
493
494 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 375 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq),
495 tx4927_irq_pic_mask(irq), 0); 376 tx4927_irq_pic_mask(irq), 0);
496
497 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
498
499 return;
500}
501
502static void tx4927_irq_pic_mask_and_ack(unsigned int irq)
503{
504 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_MASK, "irq=%d\n", irq);
505
506 tx4927_irq_pic_disable(irq);
507
508 return;
509} 377}
510 378
511static void tx4927_irq_pic_end(unsigned int irq) 379static void tx4927_irq_pic_end(unsigned int irq)
@@ -515,8 +383,6 @@ static void tx4927_irq_pic_end(unsigned int irq)
515 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 383 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
516 tx4927_irq_pic_enable(irq); 384 tx4927_irq_pic_enable(irq);
517 } 385 }
518
519 return;
520} 386}
521 387
522/* 388/*
@@ -533,8 +399,6 @@ void __init tx4927_irq_init(void)
533 tx4927_irq_pic_init(); 399 tx4927_irq_pic_init();
534 400
535 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n"); 401 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n");
536
537 return;
538} 402}
539 403
540static int tx4927_irq_nested(void) 404static int tx4927_irq_nested(void)
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
index 4658b2ae4833..941c441729b0 100644
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -112,8 +112,6 @@ void print_cp0(char *key, int num, char *name, u32 val)
112 return; 112 return;
113} 113}
114 114
115indent: Standard input:25: Error:Unexpected end of file
116
117void 115void
118dump_cp0(char *key) 116dump_cp0(char *key)
119{ 117{
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index 0c3c3f668230..34cdb2a240e9 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -151,16 +151,11 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
151#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 ) 151#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 )
152 152
153#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 ) 153#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
154#define TOSHIBA_RBTX4927_IRQ_IOC_STARTUP ( 1 << 11 )
155#define TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN ( 1 << 12 )
156#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) 154#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
157#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) 155#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
158#define TOSHIBA_RBTX4927_IRQ_IOC_MASK ( 1 << 15 )
159#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 ) 156#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 )
160 157
161#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 ) 158#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
162#define TOSHIBA_RBTX4927_IRQ_ISA_STARTUP ( 1 << 21 )
163#define TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN ( 1 << 22 )
164#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 ) 159#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
165#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 ) 160#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 )
166#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 ) 161#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 )
@@ -175,15 +170,10 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
175 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | 170 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
176 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR 171 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
177// | TOSHIBA_RBTX4927_IRQ_IOC_INIT 172// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
178// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
179// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
180// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE 173// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
181// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE 174// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
182// | TOSHIBA_RBTX4927_IRQ_IOC_MASK
183// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ 175// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
184// | TOSHIBA_RBTX4927_IRQ_ISA_INIT 176// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
185// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
186// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
187// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE 177// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
188// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE 178// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
189// | TOSHIBA_RBTX4927_IRQ_ISA_MASK 179// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
@@ -231,35 +221,25 @@ extern void disable_8259A_irq(unsigned int irq);
231extern void mask_and_ack_8259A(unsigned int irq); 221extern void mask_and_ack_8259A(unsigned int irq);
232#endif 222#endif
233 223
234static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq);
235static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq);
236static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); 224static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
237static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); 225static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
238static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq);
239static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq); 226static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
240 227
241#ifdef CONFIG_TOSHIBA_FPCIB0 228#ifdef CONFIG_TOSHIBA_FPCIB0
242static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq);
243static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq);
244static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq); 229static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
245static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq); 230static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
246static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq); 231static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
247static void toshiba_rbtx4927_irq_isa_end(unsigned int irq); 232static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
248#endif 233#endif
249 234
250static DEFINE_SPINLOCK(toshiba_rbtx4927_ioc_lock);
251
252
253#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" 235#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
254static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { 236static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
255 .typename = TOSHIBA_RBTX4927_IOC_NAME, 237 .typename = TOSHIBA_RBTX4927_IOC_NAME,
256 .startup = toshiba_rbtx4927_irq_ioc_startup, 238 .ack = toshiba_rbtx4927_irq_ioc_disable,
257 .shutdown = toshiba_rbtx4927_irq_ioc_shutdown, 239 .mask = toshiba_rbtx4927_irq_ioc_disable,
258 .enable = toshiba_rbtx4927_irq_ioc_enable, 240 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
259 .disable = toshiba_rbtx4927_irq_ioc_disable, 241 .unmask = toshiba_rbtx4927_irq_ioc_enable,
260 .ack = toshiba_rbtx4927_irq_ioc_mask_and_ack,
261 .end = toshiba_rbtx4927_irq_ioc_end, 242 .end = toshiba_rbtx4927_irq_ioc_end,
262 .set_affinity = NULL
263}; 243};
264#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 244#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
265#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 245#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
@@ -269,13 +249,11 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
269#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA" 249#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
270static struct irq_chip toshiba_rbtx4927_irq_isa_type = { 250static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
271 .typename = TOSHIBA_RBTX4927_ISA_NAME, 251 .typename = TOSHIBA_RBTX4927_ISA_NAME,
272 .startup = toshiba_rbtx4927_irq_isa_startup,
273 .shutdown = toshiba_rbtx4927_irq_isa_shutdown,
274 .enable = toshiba_rbtx4927_irq_isa_enable,
275 .disable = toshiba_rbtx4927_irq_isa_disable,
276 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack, 252 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
253 .mask = toshiba_rbtx4927_irq_isa_disable,
254 .mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
255 .unmask = toshiba_rbtx4927_irq_isa_enable,
277 .end = toshiba_rbtx4927_irq_isa_end, 256 .end = toshiba_rbtx4927_irq_isa_end,
278 .set_affinity = NULL
279}; 257};
280#endif 258#endif
281 259
@@ -363,58 +341,16 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void)
363 TOSHIBA_RBTX4927_IRQ_IOC_END); 341 TOSHIBA_RBTX4927_IRQ_IOC_END);
364 342
365 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; 343 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
366 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) { 344 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
367 irq_desc[i].status = IRQ_DISABLED; 345 set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
368 irq_desc[i].action = 0; 346 handle_level_irq);
369 irq_desc[i].depth = 3;
370 irq_desc[i].chip = &toshiba_rbtx4927_irq_ioc_type;
371 }
372 347
373 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, 348 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
374 &toshiba_rbtx4927_irq_ioc_action); 349 &toshiba_rbtx4927_irq_ioc_action);
375
376 return;
377} 350}
378 351
379static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq)
380{
381 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_STARTUP,
382 "irq=%d\n", irq);
383
384 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
385 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
386 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
387 "bad irq=%d\n", irq);
388 panic("\n");
389 }
390
391 toshiba_rbtx4927_irq_ioc_enable(irq);
392
393 return (0);
394}
395
396
397static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq)
398{
399 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN,
400 "irq=%d\n", irq);
401
402 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
403 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
404 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
405 "bad irq=%d\n", irq);
406 panic("\n");
407 }
408
409 toshiba_rbtx4927_irq_ioc_disable(irq);
410
411 return;
412}
413
414
415static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) 352static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
416{ 353{
417 unsigned long flags;
418 volatile unsigned char v; 354 volatile unsigned char v;
419 355
420 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE, 356 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
@@ -427,21 +363,14 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
427 panic("\n"); 363 panic("\n");
428 } 364 }
429 365
430 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
431
432 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 366 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
433 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 367 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
434 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 368 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
435
436 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
437
438 return;
439} 369}
440 370
441 371
442static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) 372static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
443{ 373{
444 unsigned long flags;
445 volatile unsigned char v; 374 volatile unsigned char v;
446 375
447 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE, 376 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
@@ -454,36 +383,11 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
454 panic("\n"); 383 panic("\n");
455 } 384 }
456 385
457 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
458
459 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 386 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
460 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 387 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
461 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 388 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
462
463 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
464
465 return;
466} 389}
467 390
468
469static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq)
470{
471 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_MASK,
472 "irq=%d\n", irq);
473
474 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
475 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
476 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
477 "bad irq=%d\n", irq);
478 panic("\n");
479 }
480
481 toshiba_rbtx4927_irq_ioc_disable(irq);
482
483 return;
484}
485
486
487static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq) 391static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
488{ 392{
489 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ, 393 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
@@ -499,8 +403,6 @@ static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
499 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 403 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
500 toshiba_rbtx4927_irq_ioc_enable(irq); 404 toshiba_rbtx4927_irq_ioc_enable(irq);
501 } 405 }
502
503 return;
504} 406}
505 407
506 408
@@ -520,13 +422,8 @@ static void __init toshiba_rbtx4927_irq_isa_init(void)
520 TOSHIBA_RBTX4927_IRQ_ISA_END); 422 TOSHIBA_RBTX4927_IRQ_ISA_END);
521 423
522 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG; 424 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
523 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) { 425 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++)
524 irq_desc[i].status = IRQ_DISABLED; 426 set_irq_chip(i, &toshiba_rbtx4927_irq_isa_type);
525 irq_desc[i].action = 0;
526 irq_desc[i].depth =
527 ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5));
528 irq_desc[i].chip = &toshiba_rbtx4927_irq_isa_type;
529 }
530 427
531 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC, 428 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
532 &toshiba_rbtx4927_irq_isa_master); 429 &toshiba_rbtx4927_irq_isa_master);
@@ -536,48 +433,6 @@ static void __init toshiba_rbtx4927_irq_isa_init(void)
536 /* make sure we are looking at IRR (not ISR) */ 433 /* make sure we are looking at IRR (not ISR) */
537 outb(0x0A, 0x20); 434 outb(0x0A, 0x20);
538 outb(0x0A, 0xA0); 435 outb(0x0A, 0xA0);
539
540 return;
541}
542#endif
543
544
545#ifdef CONFIG_TOSHIBA_FPCIB0
546static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq)
547{
548 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_STARTUP,
549 "irq=%d\n", irq);
550
551 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
552 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
553 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
554 "bad irq=%d\n", irq);
555 panic("\n");
556 }
557
558 toshiba_rbtx4927_irq_isa_enable(irq);
559
560 return (0);
561}
562#endif
563
564
565#ifdef CONFIG_TOSHIBA_FPCIB0
566static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq)
567{
568 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN,
569 "irq=%d\n", irq);
570
571 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
572 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
573 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
574 "bad irq=%d\n", irq);
575 panic("\n");
576 }
577
578 toshiba_rbtx4927_irq_isa_disable(irq);
579
580 return;
581} 436}
582#endif 437#endif
583 438
@@ -596,8 +451,6 @@ static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
596 } 451 }
597 452
598 enable_8259A_irq(irq); 453 enable_8259A_irq(irq);
599
600 return;
601} 454}
602#endif 455#endif
603 456
@@ -616,8 +469,6 @@ static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
616 } 469 }
617 470
618 disable_8259A_irq(irq); 471 disable_8259A_irq(irq);
619
620 return;
621} 472}
622#endif 473#endif
623 474
@@ -636,8 +487,6 @@ static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
636 } 487 }
637 488
638 mask_and_ack_8259A(irq); 489 mask_and_ack_8259A(irq);
639
640 return;
641} 490}
642#endif 491#endif
643 492
@@ -658,8 +507,6 @@ static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
658 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 507 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
659 toshiba_rbtx4927_irq_isa_enable(irq); 508 toshiba_rbtx4927_irq_isa_enable(irq);
660 } 509 }
661
662 return;
663} 510}
664#endif 511#endif
665 512
@@ -668,8 +515,6 @@ void __init arch_init_irq(void)
668{ 515{
669 extern void tx4927_irq_init(void); 516 extern void tx4927_irq_init(void);
670 517
671 local_irq_disable();
672
673 tx4927_irq_init(); 518 tx4927_irq_init();
674 toshiba_rbtx4927_irq_ioc_init(); 519 toshiba_rbtx4927_irq_ioc_init();
675#ifdef CONFIG_TOSHIBA_FPCIB0 520#ifdef CONFIG_TOSHIBA_FPCIB0
@@ -681,8 +526,6 @@ void __init arch_init_irq(void)
681#endif 526#endif
682 527
683 wbflush(); 528 wbflush();
684
685 return;
686} 529}
687 530
688void toshiba_rbtx4927_irq_dump(char *key) 531void toshiba_rbtx4927_irq_dump(char *key)
@@ -715,7 +558,6 @@ void toshiba_rbtx4927_irq_dump(char *key)
715 } 558 }
716 } 559 }
717#endif 560#endif
718 return;
719} 561}
720 562
721void toshiba_rbtx4927_irq_dump_pics(char *s) 563void toshiba_rbtx4927_irq_dump_pics(char *s)
@@ -780,6 +622,4 @@ void toshiba_rbtx4927_irq_dump_pics(char *s)
780 level5_s); 622 level5_s);
781 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n", 623 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
782 s); 624 s);
783
784 return;
785} 625}
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
index 77fe2454f5b9..42e127683ae9 100644
--- a/arch/mips/tx4938/common/irq.c
+++ b/arch/mips/tx4938/common/irq.c
@@ -37,48 +37,36 @@
37/* Forwad definitions for all pic's */ 37/* Forwad definitions for all pic's */
38/**********************************************************************************/ 38/**********************************************************************************/
39 39
40static unsigned int tx4938_irq_cp0_startup(unsigned int irq);
41static void tx4938_irq_cp0_shutdown(unsigned int irq);
42static void tx4938_irq_cp0_enable(unsigned int irq); 40static void tx4938_irq_cp0_enable(unsigned int irq);
43static void tx4938_irq_cp0_disable(unsigned int irq); 41static void tx4938_irq_cp0_disable(unsigned int irq);
44static void tx4938_irq_cp0_mask_and_ack(unsigned int irq);
45static void tx4938_irq_cp0_end(unsigned int irq); 42static void tx4938_irq_cp0_end(unsigned int irq);
46 43
47static unsigned int tx4938_irq_pic_startup(unsigned int irq);
48static void tx4938_irq_pic_shutdown(unsigned int irq);
49static void tx4938_irq_pic_enable(unsigned int irq); 44static void tx4938_irq_pic_enable(unsigned int irq);
50static void tx4938_irq_pic_disable(unsigned int irq); 45static void tx4938_irq_pic_disable(unsigned int irq);
51static void tx4938_irq_pic_mask_and_ack(unsigned int irq);
52static void tx4938_irq_pic_end(unsigned int irq); 46static void tx4938_irq_pic_end(unsigned int irq);
53 47
54/**********************************************************************************/ 48/**********************************************************************************/
55/* Kernel structs for all pic's */ 49/* Kernel structs for all pic's */
56/**********************************************************************************/ 50/**********************************************************************************/
57DEFINE_SPINLOCK(tx4938_cp0_lock);
58DEFINE_SPINLOCK(tx4938_pic_lock);
59 51
60#define TX4938_CP0_NAME "TX4938-CP0" 52#define TX4938_CP0_NAME "TX4938-CP0"
61static struct irq_chip tx4938_irq_cp0_type = { 53static struct irq_chip tx4938_irq_cp0_type = {
62 .typename = TX4938_CP0_NAME, 54 .typename = TX4938_CP0_NAME,
63 .startup = tx4938_irq_cp0_startup, 55 .ack = tx4938_irq_cp0_disable,
64 .shutdown = tx4938_irq_cp0_shutdown, 56 .mask = tx4938_irq_cp0_disable,
65 .enable = tx4938_irq_cp0_enable, 57 .mask_ack = tx4938_irq_cp0_disable,
66 .disable = tx4938_irq_cp0_disable, 58 .unmask = tx4938_irq_cp0_enable,
67 .ack = tx4938_irq_cp0_mask_and_ack,
68 .end = tx4938_irq_cp0_end, 59 .end = tx4938_irq_cp0_end,
69 .set_affinity = NULL
70}; 60};
71 61
72#define TX4938_PIC_NAME "TX4938-PIC" 62#define TX4938_PIC_NAME "TX4938-PIC"
73static struct irq_chip tx4938_irq_pic_type = { 63static struct irq_chip tx4938_irq_pic_type = {
74 .typename = TX4938_PIC_NAME, 64 .typename = TX4938_PIC_NAME,
75 .startup = tx4938_irq_pic_startup, 65 .ack = tx4938_irq_pic_disable,
76 .shutdown = tx4938_irq_pic_shutdown, 66 .mask = tx4938_irq_pic_disable,
77 .enable = tx4938_irq_pic_enable, 67 .mask_ack = tx4938_irq_pic_disable,
78 .disable = tx4938_irq_pic_disable, 68 .unmask = tx4938_irq_pic_enable,
79 .ack = tx4938_irq_pic_mask_and_ack,
80 .end = tx4938_irq_pic_end, 69 .end = tx4938_irq_pic_end,
81 .set_affinity = NULL
82}; 70};
83 71
84static struct irqaction tx4938_irq_pic_action = { 72static struct irqaction tx4938_irq_pic_action = {
@@ -99,56 +87,21 @@ tx4938_irq_cp0_init(void)
99{ 87{
100 int i; 88 int i;
101 89
102 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) { 90 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++)
103 irq_desc[i].status = IRQ_DISABLED; 91 set_irq_chip_and_handler(i, &tx4938_irq_cp0_type,
104 irq_desc[i].action = 0; 92 handle_level_irq);
105 irq_desc[i].depth = 1;
106 irq_desc[i].chip = &tx4938_irq_cp0_type;
107 }
108}
109
110static unsigned int
111tx4938_irq_cp0_startup(unsigned int irq)
112{
113 tx4938_irq_cp0_enable(irq);
114
115 return 0;
116}
117
118static void
119tx4938_irq_cp0_shutdown(unsigned int irq)
120{
121 tx4938_irq_cp0_disable(irq);
122} 93}
123 94
124static void 95static void
125tx4938_irq_cp0_enable(unsigned int irq) 96tx4938_irq_cp0_enable(unsigned int irq)
126{ 97{
127 unsigned long flags;
128
129 spin_lock_irqsave(&tx4938_cp0_lock, flags);
130
131 set_c0_status(tx4938_irq_cp0_mask(irq)); 98 set_c0_status(tx4938_irq_cp0_mask(irq));
132
133 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
134} 99}
135 100
136static void 101static void
137tx4938_irq_cp0_disable(unsigned int irq) 102tx4938_irq_cp0_disable(unsigned int irq)
138{ 103{
139 unsigned long flags;
140
141 spin_lock_irqsave(&tx4938_cp0_lock, flags);
142
143 clear_c0_status(tx4938_irq_cp0_mask(irq)); 104 clear_c0_status(tx4938_irq_cp0_mask(irq));
144
145 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
146}
147
148static void
149tx4938_irq_cp0_mask_and_ack(unsigned int irq)
150{
151 tx4938_irq_cp0_disable(irq);
152} 105}
153 106
154static void 107static void
@@ -290,70 +243,30 @@ tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
290static void __init 243static void __init
291tx4938_irq_pic_init(void) 244tx4938_irq_pic_init(void)
292{ 245{
293 unsigned long flags;
294 int i; 246 int i;
295 247
296 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) { 248 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++)
297 irq_desc[i].status = IRQ_DISABLED; 249 set_irq_chip_and_handler(i, &tx4938_irq_pic_type,
298 irq_desc[i].action = 0; 250 handle_level_irq);
299 irq_desc[i].depth = 2;
300 irq_desc[i].chip = &tx4938_irq_pic_type;
301 }
302 251
303 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); 252 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
304 253
305 spin_lock_irqsave(&tx4938_pic_lock, flags);
306
307 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ 254 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
308 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */ 255 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
309
310 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
311}
312
313static unsigned int
314tx4938_irq_pic_startup(unsigned int irq)
315{
316 tx4938_irq_pic_enable(irq);
317
318 return 0;
319}
320
321static void
322tx4938_irq_pic_shutdown(unsigned int irq)
323{
324 tx4938_irq_pic_disable(irq);
325} 256}
326 257
327static void 258static void
328tx4938_irq_pic_enable(unsigned int irq) 259tx4938_irq_pic_enable(unsigned int irq)
329{ 260{
330 unsigned long flags;
331
332 spin_lock_irqsave(&tx4938_pic_lock, flags);
333
334 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0, 261 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
335 tx4938_irq_pic_mask(irq)); 262 tx4938_irq_pic_mask(irq));
336
337 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
338} 263}
339 264
340static void 265static void
341tx4938_irq_pic_disable(unsigned int irq) 266tx4938_irq_pic_disable(unsigned int irq)
342{ 267{
343 unsigned long flags;
344
345 spin_lock_irqsave(&tx4938_pic_lock, flags);
346
347 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 268 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
348 tx4938_irq_pic_mask(irq), 0); 269 tx4938_irq_pic_mask(irq), 0);
349
350 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
351}
352
353static void
354tx4938_irq_pic_mask_and_ack(unsigned int irq)
355{
356 tx4938_irq_pic_disable(irq);
357} 270}
358 271
359static void 272static void
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
index f415a1f18fba..dc87d92bb08d 100644
--- a/arch/mips/tx4938/common/setup.c
+++ b/arch/mips/tx4938/common/setup.c
@@ -31,7 +31,6 @@
31#include <asm/mipsregs.h> 31#include <asm/mipsregs.h>
32#include <asm/system.h> 32#include <asm/system.h>
33#include <asm/time.h> 33#include <asm/time.h>
34#include <asm/time.h>
35#include <asm/tx4938/rbtx4938.h> 34#include <asm/tx4938/rbtx4938.h>
36 35
37extern void toshiba_rbtx4938_setup(void); 36extern void toshiba_rbtx4938_setup(void);
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index 102e473c10a2..8c87a35f3068 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -87,25 +87,18 @@ IRQ Device
87#include <linux/bootmem.h> 87#include <linux/bootmem.h>
88#include <asm/tx4938/rbtx4938.h> 88#include <asm/tx4938/rbtx4938.h>
89 89
90static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq);
91static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq);
92static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); 90static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
93static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); 91static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
94static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq);
95static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq); 92static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq);
96 93
97DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock);
98
99#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" 94#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
100static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { 95static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
101 .typename = TOSHIBA_RBTX4938_IOC_NAME, 96 .typename = TOSHIBA_RBTX4938_IOC_NAME,
102 .startup = toshiba_rbtx4938_irq_ioc_startup, 97 .ack = toshiba_rbtx4938_irq_ioc_disable,
103 .shutdown = toshiba_rbtx4938_irq_ioc_shutdown, 98 .mask = toshiba_rbtx4938_irq_ioc_disable,
104 .enable = toshiba_rbtx4938_irq_ioc_enable, 99 .mask_ack = toshiba_rbtx4938_irq_ioc_disable,
105 .disable = toshiba_rbtx4938_irq_ioc_disable, 100 .unmask = toshiba_rbtx4938_irq_ioc_enable,
106 .ack = toshiba_rbtx4938_irq_ioc_mask_and_ack,
107 .end = toshiba_rbtx4938_irq_ioc_end, 101 .end = toshiba_rbtx4938_irq_ioc_end,
108 .set_affinity = NULL
109}; 102};
110 103
111#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000 104#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
@@ -142,69 +135,36 @@ toshiba_rbtx4938_irq_ioc_init(void)
142 int i; 135 int i;
143 136
144 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; 137 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
145 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) { 138 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++)
146 irq_desc[i].status = IRQ_DISABLED; 139 set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
147 irq_desc[i].action = 0; 140 handle_level_irq);
148 irq_desc[i].depth = 3;
149 irq_desc[i].chip = &toshiba_rbtx4938_irq_ioc_type;
150 }
151 141
152 setup_irq(RBTX4938_IRQ_IOCINT, 142 setup_irq(RBTX4938_IRQ_IOCINT,
153 &toshiba_rbtx4938_irq_ioc_action); 143 &toshiba_rbtx4938_irq_ioc_action);
154} 144}
155 145
156static unsigned int
157toshiba_rbtx4938_irq_ioc_startup(unsigned int irq)
158{
159 toshiba_rbtx4938_irq_ioc_enable(irq);
160
161 return 0;
162}
163
164static void
165toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq)
166{
167 toshiba_rbtx4938_irq_ioc_disable(irq);
168}
169
170static void 146static void
171toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) 147toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
172{ 148{
173 unsigned long flags;
174 volatile unsigned char v; 149 volatile unsigned char v;
175 150
176 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
177
178 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 151 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
179 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); 152 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
180 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); 153 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
181 mmiowb(); 154 mmiowb();
182 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 155 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
183
184 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
185} 156}
186 157
187static void 158static void
188toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) 159toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
189{ 160{
190 unsigned long flags;
191 volatile unsigned char v; 161 volatile unsigned char v;
192 162
193 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
194
195 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 163 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
196 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); 164 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
197 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); 165 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
198 mmiowb(); 166 mmiowb();
199 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 167 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
200
201 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
202}
203
204static void
205toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq)
206{
207 toshiba_rbtx4938_irq_ioc_disable(irq);
208} 168}
209 169
210static void 170static void
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
index b926e6a75c29..08b20cdfd7b3 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
@@ -36,14 +36,18 @@ void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)
36 36
37static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait); 37static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait);
38 38
39static void txx9_spi_interrupt(int irq, void *dev_id) 39static irqreturn_t txx9_spi_interrupt(int irq, void *dev_id)
40{ 40{
41 /* disable rx intr */ 41 /* disable rx intr */
42 tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE; 42 tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE;
43 wake_up(&txx9_spi_wait); 43 wake_up(&txx9_spi_wait);
44
45 return IRQ_HANDLED;
44} 46}
47
45static struct irqaction txx9_spi_action = { 48static struct irqaction txx9_spi_action = {
46 txx9_spi_interrupt, 0, 0, "spi", NULL, NULL, 49 .handler = txx9_spi_interrupt,
50 .name = "spi",
47}; 51};
48 52
49void __init txx9_spi_irqinit(int irc_irq) 53void __init txx9_spi_irqinit(int irc_irq)
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index c215c0d39fae..54b92a74c7ac 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -417,14 +417,7 @@ void vr41xx_disable_bcuint(void)
417 417
418EXPORT_SYMBOL(vr41xx_disable_bcuint); 418EXPORT_SYMBOL(vr41xx_disable_bcuint);
419 419
420static unsigned int startup_sysint1_irq(unsigned int irq) 420static void disable_sysint1_irq(unsigned int irq)
421{
422 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
423
424 return 0; /* never anything pending */
425}
426
427static void shutdown_sysint1_irq(unsigned int irq)
428{ 421{
429 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); 422 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
430} 423}
@@ -434,9 +427,6 @@ static void enable_sysint1_irq(unsigned int irq)
434 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); 427 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
435} 428}
436 429
437#define disable_sysint1_irq shutdown_sysint1_irq
438#define ack_sysint1_irq shutdown_sysint1_irq
439
440static void end_sysint1_irq(unsigned int irq) 430static void end_sysint1_irq(unsigned int irq)
441{ 431{
442 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 432 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -445,22 +435,14 @@ static void end_sysint1_irq(unsigned int irq)
445 435
446static struct irq_chip sysint1_irq_type = { 436static struct irq_chip sysint1_irq_type = {
447 .typename = "SYSINT1", 437 .typename = "SYSINT1",
448 .startup = startup_sysint1_irq, 438 .ack = disable_sysint1_irq,
449 .shutdown = shutdown_sysint1_irq, 439 .mask = disable_sysint1_irq,
450 .enable = enable_sysint1_irq, 440 .mask_ack = disable_sysint1_irq,
451 .disable = disable_sysint1_irq, 441 .unmask = enable_sysint1_irq,
452 .ack = ack_sysint1_irq,
453 .end = end_sysint1_irq, 442 .end = end_sysint1_irq,
454}; 443};
455 444
456static unsigned int startup_sysint2_irq(unsigned int irq) 445static void disable_sysint2_irq(unsigned int irq)
457{
458 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
459
460 return 0; /* never anything pending */
461}
462
463static void shutdown_sysint2_irq(unsigned int irq)
464{ 446{
465 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); 447 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
466} 448}
@@ -470,9 +452,6 @@ static void enable_sysint2_irq(unsigned int irq)
470 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); 452 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
471} 453}
472 454
473#define disable_sysint2_irq shutdown_sysint2_irq
474#define ack_sysint2_irq shutdown_sysint2_irq
475
476static void end_sysint2_irq(unsigned int irq) 455static void end_sysint2_irq(unsigned int irq)
477{ 456{
478 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 457 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -481,11 +460,10 @@ static void end_sysint2_irq(unsigned int irq)
481 460
482static struct irq_chip sysint2_irq_type = { 461static struct irq_chip sysint2_irq_type = {
483 .typename = "SYSINT2", 462 .typename = "SYSINT2",
484 .startup = startup_sysint2_irq, 463 .ack = disable_sysint2_irq,
485 .shutdown = shutdown_sysint2_irq, 464 .mask = disable_sysint2_irq,
486 .enable = enable_sysint2_irq, 465 .mask_ack = disable_sysint2_irq,
487 .disable = disable_sysint2_irq, 466 .unmask = enable_sysint2_irq,
488 .ack = ack_sysint2_irq,
489 .end = end_sysint2_irq, 467 .end = end_sysint2_irq,
490}; 468};
491 469
@@ -723,10 +701,12 @@ static int __init vr41xx_icu_init(void)
723 icu2_write(MGIUINTHREG, 0xffff); 701 icu2_write(MGIUINTHREG, 0xffff);
724 702
725 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) 703 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
726 irq_desc[i].chip = &sysint1_irq_type; 704 set_irq_chip_and_handler(i, &sysint1_irq_type,
705 handle_level_irq);
727 706
728 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) 707 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
729 irq_desc[i].chip = &sysint2_irq_type; 708 set_irq_chip_and_handler(i, &sysint2_irq_type,
709 handle_level_irq);
730 710
731 cascade_irq(INT0_IRQ, icu_get_irq); 711 cascade_irq(INT0_IRQ, icu_get_irq);
732 cascade_irq(INT1_IRQ, icu_get_irq); 712 cascade_irq(INT1_IRQ, icu_get_irq);
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
index 2483487344c2..a039bb7251ff 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
@@ -30,17 +30,6 @@ extern void init_8259A(int hoge);
30 30
31extern int vr4133_rockhopper; 31extern int vr4133_rockhopper;
32 32
33static unsigned int startup_i8259_irq(unsigned int irq)
34{
35 enable_8259A_irq(irq - I8259_IRQ_BASE);
36 return 0;
37}
38
39static void shutdown_i8259_irq(unsigned int irq)
40{
41 disable_8259A_irq(irq - I8259_IRQ_BASE);
42}
43
44static void enable_i8259_irq(unsigned int irq) 33static void enable_i8259_irq(unsigned int irq)
45{ 34{
46 enable_8259A_irq(irq - I8259_IRQ_BASE); 35 enable_8259A_irq(irq - I8259_IRQ_BASE);
@@ -64,11 +53,10 @@ static void end_i8259_irq(unsigned int irq)
64 53
65static struct irq_chip i8259_irq_type = { 54static struct irq_chip i8259_irq_type = {
66 .typename = "XT-PIC", 55 .typename = "XT-PIC",
67 .startup = startup_i8259_irq,
68 .shutdown = shutdown_i8259_irq,
69 .enable = enable_i8259_irq,
70 .disable = disable_i8259_irq,
71 .ack = ack_i8259_irq, 56 .ack = ack_i8259_irq,
57 .mask = disable_i8259_irq,
58 .mask_ack = ack_i8259_irq,
59 .unmask = enable_i8259_irq,
72 .end = end_i8259_irq, 60 .end = end_i8259_irq,
73}; 61};
74 62
@@ -104,7 +92,7 @@ void __init rockhopper_init_irq(void)
104 } 92 }
105 93
106 for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) 94 for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++)
107 irq_desc[i].chip = &i8259_irq_type; 95 set_irq_chip(i, &i8259_irq_type);
108 96
109 setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); 97 setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade);
110 98
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-16 01:52:12 -0500