diff options
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/Kconfig | 1 | ||||
-rw-r--r-- | arch/mips/mm/c-r4k.c | 1 | ||||
-rw-r--r-- | arch/mips/mm/pg-r4k.c | 10 |
3 files changed, 10 insertions, 2 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 97a9769a9046..ac2012f033d6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
@@ -1160,6 +1160,7 @@ config CPU_R4X00 | |||
1160 | config CPU_TX49XX | 1160 | config CPU_TX49XX |
1161 | bool "R49XX" | 1161 | bool "R49XX" |
1162 | depends on SYS_HAS_CPU_TX49XX | 1162 | depends on SYS_HAS_CPU_TX49XX |
1163 | select CPU_HAS_PREFETCH | ||
1163 | select CPU_SUPPORTS_32BIT_KERNEL | 1164 | select CPU_SUPPORTS_32BIT_KERNEL |
1164 | select CPU_SUPPORTS_64BIT_KERNEL | 1165 | select CPU_SUPPORTS_64BIT_KERNEL |
1165 | 1166 | ||
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 9572ed44f0d5..32b7f6aeb983 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c | |||
@@ -786,6 +786,7 @@ static void __init probe_pcache(void) | |||
786 | c->dcache.waybit = 0; | 786 | c->dcache.waybit = 0; |
787 | 787 | ||
788 | c->options |= MIPS_CPU_CACHE_CDEX_P; | 788 | c->options |= MIPS_CPU_CACHE_CDEX_P; |
789 | c->options |= MIPS_CPU_PREFETCH; | ||
789 | break; | 790 | break; |
790 | 791 | ||
791 | case CPU_R4000PC: | 792 | case CPU_R4000PC: |
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c index f51e180072e3..e4390dc3eb48 100644 --- a/arch/mips/mm/pg-r4k.c +++ b/arch/mips/mm/pg-r4k.c | |||
@@ -124,7 +124,7 @@ static inline void build_nop(void) | |||
124 | 124 | ||
125 | static inline void build_src_pref(int advance) | 125 | static inline void build_src_pref(int advance) |
126 | { | 126 | { |
127 | if (!(load_offset & (cpu_dcache_line_size() - 1))) { | 127 | if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) { |
128 | union mips_instruction mi; | 128 | union mips_instruction mi; |
129 | 129 | ||
130 | mi.i_format.opcode = pref_op; | 130 | mi.i_format.opcode = pref_op; |
@@ -166,7 +166,7 @@ static inline void build_load_reg(int reg) | |||
166 | 166 | ||
167 | static inline void build_dst_pref(int advance) | 167 | static inline void build_dst_pref(int advance) |
168 | { | 168 | { |
169 | if (!(store_offset & (cpu_dcache_line_size() - 1))) { | 169 | if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) { |
170 | union mips_instruction mi; | 170 | union mips_instruction mi; |
171 | 171 | ||
172 | mi.i_format.opcode = pref_op; | 172 | mi.i_format.opcode = pref_op; |
@@ -340,6 +340,12 @@ void __init build_clear_page(void) | |||
340 | 340 | ||
341 | if (cpu_has_prefetch) { | 341 | if (cpu_has_prefetch) { |
342 | switch (current_cpu_data.cputype) { | 342 | switch (current_cpu_data.cputype) { |
343 | case CPU_TX49XX: | ||
344 | /* TX49 supports only Pref_Load */ | ||
345 | pref_offset_clear = 0; | ||
346 | pref_offset_copy = 0; | ||
347 | break; | ||
348 | |||
343 | case CPU_RM9000: | 349 | case CPU_RM9000: |
344 | /* | 350 | /* |
345 | * As a workaround for erratum G105 which make the | 351 | * As a workaround for erratum G105 which make the |