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-rw-r--r--arch/mips/Kconfig84
-rw-r--r--arch/mips/Makefile1
-rw-r--r--arch/mips/ar7/gpio.c2
-rw-r--r--arch/mips/ar7/platform.c37
-rw-r--r--arch/mips/ar7/prom.c4
-rw-r--r--arch/mips/ath79/Kconfig38
-rw-r--r--arch/mips/ath79/Makefile5
-rw-r--r--arch/mips/ath79/clock.c55
-rw-r--r--arch/mips/ath79/common.c5
-rw-r--r--arch/mips/ath79/dev-ar913x-wmac.c60
-rw-r--r--arch/mips/ath79/dev-common.c38
-rw-r--r--arch/mips/ath79/dev-usb.c197
-rw-r--r--arch/mips/ath79/dev-usb.h (renamed from arch/mips/ath79/dev-ar913x-wmac.h)10
-rw-r--r--arch/mips/ath79/dev-wmac.c109
-rw-r--r--arch/mips/ath79/dev-wmac.h17
-rw-r--r--arch/mips/ath79/early_printk.c76
-rw-r--r--arch/mips/ath79/gpio.c2
-rw-r--r--arch/mips/ath79/irq.c17
-rw-r--r--arch/mips/ath79/mach-ap121.c92
-rw-r--r--arch/mips/ath79/mach-ap81.c6
-rw-r--r--arch/mips/ath79/mach-pb44.c2
-rw-r--r--arch/mips/ath79/mach-ubnt-xm.c119
-rw-r--r--arch/mips/ath79/machtypes.h2
-rw-r--r--arch/mips/ath79/setup.c20
-rw-r--r--arch/mips/bcm63xx/Kconfig4
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c46
-rw-r--r--arch/mips/bcm63xx/clk.c70
-rw-r--r--arch/mips/bcm63xx/cpu.c261
-rw-r--r--arch/mips/bcm63xx/dev-uart.c2
-rw-r--r--arch/mips/bcm63xx/gpio.c41
-rw-r--r--arch/mips/bcm63xx/irq.c403
-rw-r--r--arch/mips/bcm63xx/prom.c7
-rw-r--r--arch/mips/bcm63xx/setup.c32
-rw-r--r--arch/mips/cavium-octeon/Kconfig4
-rw-r--r--arch/mips/cavium-octeon/dma-octeon.c23
-rw-r--r--arch/mips/cavium-octeon/executive/Makefile7
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c306
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-fpa.c183
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-board.c711
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c243
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-loop.c85
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-npi.c113
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c526
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c554
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-spi.c205
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-util.c433
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c354
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper.c1116
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c371
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c140
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-pko.c506
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-spi.c667
-rw-r--r--arch/mips/cavium-octeon/executive/octeon-model.c119
-rw-r--r--arch/mips/configs/nlm_xlp_defconfig570
-rw-r--r--arch/mips/configs/nlm_xlr_defconfig16
-rw-r--r--arch/mips/include/asm/bmips.h110
-rw-r--r--arch/mips/include/asm/branch.h5
-rw-r--r--arch/mips/include/asm/cpu.h5
-rw-r--r--arch/mips/include/asm/hazards.h7
-rw-r--r--arch/mips/include/asm/kprobes.h5
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h81
-rw-r--r--arch/mips/include/asm/mach-ath79/ar933x_uart.h67
-rw-r--r--arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h18
-rw-r--r--arch/mips/include/asm/mach-ath79/ath79.h11
-rw-r--r--arch/mips/include/asm/mach-ath79/irq.h8
-rw-r--r--arch/mips/include/asm/mach-ath79/pci-ath724x.h21
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h597
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h231
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h42
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/irq.h7
-rw-r--r--arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h23
-rw-r--r--arch/mips/include/asm/mipsregs.h9
-rw-r--r--arch/mips/include/asm/module.h6
-rw-r--r--arch/mips/include/asm/netlogic/common.h76
-rw-r--r--arch/mips/include/asm/netlogic/haldefs.h163
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/bridge.h187
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h83
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h153
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h411
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/sys.h129
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/uart.h191
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h (renamed from arch/mips/netlogic/xlr/xlr_console.c)25
-rw-r--r--arch/mips/include/asm/netlogic/xlr/iomap.h22
-rw-r--r--arch/mips/include/asm/netlogic/xlr/msidef.h84
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h69
-rw-r--r--arch/mips/include/asm/netlogic/xlr/xlr.h13
-rw-r--r--arch/mips/include/asm/octeon/cvmx-address.h274
-rw-r--r--arch/mips/include/asm/octeon/cvmx-asxx-defs.h475
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h82
-rw-r--r--arch/mips/include/asm/octeon/cvmx-cmd-queue.h617
-rw-r--r--arch/mips/include/asm/octeon/cvmx-config.h168
-rw-r--r--arch/mips/include/asm/octeon/cvmx-dbg-defs.h72
-rw-r--r--arch/mips/include/asm/octeon/cvmx-dpi-defs.h643
-rw-r--r--arch/mips/include/asm/octeon/cvmx-fau.h597
-rw-r--r--arch/mips/include/asm/octeon/cvmx-fpa-defs.h403
-rw-r--r--arch/mips/include/asm/octeon/cvmx-fpa.h299
-rw-r--r--arch/mips/include/asm/octeon/cvmx-gmxx-defs.h2529
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-board.h157
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-fpa.h64
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-loop.h60
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-npi.h61
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-rgmii.h111
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-sgmii.h105
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-spi.h85
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-util.h215
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-xaui.h104
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper.h228
-rw-r--r--arch/mips/include/asm/octeon/cvmx-ipd.h338
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mdio.h506
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mio-defs.h1033
-rw-r--r--arch/mips/include/asm/octeon/cvmx-npei-defs.h4
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pciercx-defs.h609
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pcsx-defs.h370
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h316
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pemx-defs.h509
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pexp-defs.h19
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pip-defs.h1267
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pip.h524
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pko-defs.h1133
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pko.h610
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pow.h1982
-rw-r--r--arch/mips/include/asm/octeon/cvmx-scratch.h139
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sli-defs.h2172
-rw-r--r--arch/mips/include/asm/octeon/cvmx-spi.h269
-rw-r--r--arch/mips/include/asm/octeon/cvmx-spxx-defs.h347
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sriox-defs.h1036
-rw-r--r--arch/mips/include/asm/octeon/cvmx-srxx-defs.h126
-rw-r--r--arch/mips/include/asm/octeon/cvmx-stxx-defs.h292
-rw-r--r--arch/mips/include/asm/octeon/cvmx-wqe.h397
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h42
-rw-r--r--arch/mips/include/asm/octeon/octeon-feature.h114
-rw-r--r--arch/mips/include/asm/octeon/octeon-model.h215
-rw-r--r--arch/mips/include/asm/octeon/pci-octeon.h3
-rw-r--r--arch/mips/include/asm/traps.h13
-rw-r--r--arch/mips/kernel/Makefile2
-rw-r--r--arch/mips/kernel/bmips_vec.S255
-rw-r--r--arch/mips/kernel/branch.c128
-rw-r--r--arch/mips/kernel/cpu-probe.c21
-rw-r--r--arch/mips/kernel/kprobes.c177
-rw-r--r--arch/mips/kernel/perf_event_mipsxx.c72
-rw-r--r--arch/mips/kernel/smp-bmips.c458
-rw-r--r--arch/mips/kernel/traps.c12
-rw-r--r--arch/mips/lib/Makefile1
-rw-r--r--arch/mips/math-emu/cp1emu.c2
-rw-r--r--arch/mips/mm/Makefile1
-rw-r--r--arch/mips/mm/c-r4k.c3
-rw-r--r--arch/mips/netlogic/Kconfig3
-rw-r--r--arch/mips/netlogic/Makefile3
-rw-r--r--arch/mips/netlogic/Platform13
-rw-r--r--arch/mips/netlogic/common/Makefile3
-rw-r--r--arch/mips/netlogic/common/earlycons.c60
-rw-r--r--arch/mips/netlogic/common/irq.c238
-rw-r--r--arch/mips/netlogic/common/smp.c (renamed from arch/mips/netlogic/xlr/smp.c)152
-rw-r--r--arch/mips/netlogic/common/smpboot.S272
-rw-r--r--arch/mips/netlogic/common/time.c (renamed from arch/mips/netlogic/xlr/time.c)6
-rw-r--r--arch/mips/netlogic/xlp/Makefile2
-rw-r--r--arch/mips/netlogic/xlp/nlm_hal.c111
-rw-r--r--arch/mips/netlogic/xlp/platform.c108
-rw-r--r--arch/mips/netlogic/xlp/setup.c105
-rw-r--r--arch/mips/netlogic/xlp/wakeup.c102
-rw-r--r--arch/mips/netlogic/xlr/Makefile7
-rw-r--r--arch/mips/netlogic/xlr/irq.c300
-rw-r--r--arch/mips/netlogic/xlr/platform.c31
-rw-r--r--arch/mips/netlogic/xlr/setup.c31
-rw-r--r--arch/mips/netlogic/xlr/wakeup.c (renamed from arch/mips/netlogic/xlr/smpboot.S)80
-rw-r--r--arch/mips/pci/Makefile3
-rw-r--r--arch/mips/pci/pci-ath724x.c174
-rw-r--r--arch/mips/pci/pci-bcm63xx.c4
-rw-r--r--arch/mips/pci/pci-octeon.c16
-rw-r--r--arch/mips/pci/pci-xlr.c128
-rw-r--r--arch/mips/pci/pcie-octeon.c1349
174 files changed, 36201 insertions, 1957 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index d46f1da18a3c..0c55582a49c3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -716,7 +716,6 @@ config CAVIUM_OCTEON_SIMULATOR
716 select DMA_COHERENT 716 select DMA_COHERENT
717 select SYS_SUPPORTS_64BIT_KERNEL 717 select SYS_SUPPORTS_64BIT_KERNEL
718 select SYS_SUPPORTS_BIG_ENDIAN 718 select SYS_SUPPORTS_BIG_ENDIAN
719 select SYS_SUPPORTS_HIGHMEM
720 select SYS_SUPPORTS_HOTPLUG_CPU 719 select SYS_SUPPORTS_HOTPLUG_CPU
721 select SYS_HAS_CPU_CAVIUM_OCTEON 720 select SYS_HAS_CPU_CAVIUM_OCTEON
722 select HOLES_IN_ZONE 721 select HOLES_IN_ZONE
@@ -732,7 +731,6 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
732 select DMA_COHERENT 731 select DMA_COHERENT
733 select SYS_SUPPORTS_64BIT_KERNEL 732 select SYS_SUPPORTS_64BIT_KERNEL
734 select SYS_SUPPORTS_BIG_ENDIAN 733 select SYS_SUPPORTS_BIG_ENDIAN
735 select SYS_SUPPORTS_HIGHMEM
736 select SYS_SUPPORTS_HOTPLUG_CPU 734 select SYS_SUPPORTS_HOTPLUG_CPU
737 select SYS_HAS_EARLY_PRINTK 735 select SYS_HAS_EARLY_PRINTK
738 select SYS_HAS_CPU_CAVIUM_OCTEON 736 select SYS_HAS_CPU_CAVIUM_OCTEON
@@ -761,7 +759,6 @@ config NLM_XLR_BOARD
761 depends on EXPERIMENTAL 759 depends on EXPERIMENTAL
762 select BOOT_ELF32 760 select BOOT_ELF32
763 select NLM_COMMON 761 select NLM_COMMON
764 select NLM_XLR
765 select SYS_HAS_CPU_XLR 762 select SYS_HAS_CPU_XLR
766 select SYS_SUPPORTS_SMP 763 select SYS_SUPPORTS_SMP
767 select HW_HAS_PCI 764 select HW_HAS_PCI
@@ -776,6 +773,7 @@ config NLM_XLR_BOARD
776 select CEVT_R4K 773 select CEVT_R4K
777 select CSRC_R4K 774 select CSRC_R4K
778 select IRQ_CPU 775 select IRQ_CPU
776 select ARCH_SUPPORTS_MSI
779 select ZONE_DMA if 64BIT 777 select ZONE_DMA if 64BIT
780 select SYNC_R4K 778 select SYNC_R4K
781 select SYS_HAS_EARLY_PRINTK 779 select SYS_HAS_EARLY_PRINTK
@@ -783,6 +781,33 @@ config NLM_XLR_BOARD
783 Support for systems based on Netlogic XLR and XLS processors. 781 Support for systems based on Netlogic XLR and XLS processors.
784 Say Y here if you have a XLR or XLS based board. 782 Say Y here if you have a XLR or XLS based board.
785 783
784config NLM_XLP_BOARD
785 bool "Netlogic XLP based systems"
786 depends on EXPERIMENTAL
787 select BOOT_ELF32
788 select NLM_COMMON
789 select SYS_HAS_CPU_XLP
790 select SYS_SUPPORTS_SMP
791 select HW_HAS_PCI
792 select SWAP_IO_SPACE
793 select SYS_SUPPORTS_32BIT_KERNEL
794 select SYS_SUPPORTS_64BIT_KERNEL
795 select 64BIT_PHYS_ADDR
796 select SYS_SUPPORTS_BIG_ENDIAN
797 select SYS_SUPPORTS_LITTLE_ENDIAN
798 select SYS_SUPPORTS_HIGHMEM
799 select DMA_COHERENT
800 select NR_CPUS_DEFAULT_32
801 select CEVT_R4K
802 select CSRC_R4K
803 select IRQ_CPU
804 select ZONE_DMA if 64BIT
805 select SYNC_R4K
806 select SYS_HAS_EARLY_PRINTK
807 help
808 This board is based on Netlogic XLP Processor.
809 Say Y here if you have a XLP based board.
810
786endchoice 811endchoice
787 812
788source "arch/mips/alchemy/Kconfig" 813source "arch/mips/alchemy/Kconfig"
@@ -1413,51 +1438,36 @@ config CPU_CAVIUM_OCTEON
1413config CPU_BMIPS3300 1438config CPU_BMIPS3300
1414 bool "BMIPS3300" 1439 bool "BMIPS3300"
1415 depends on SYS_HAS_CPU_BMIPS3300 1440 depends on SYS_HAS_CPU_BMIPS3300
1416 select DMA_NONCOHERENT 1441 select CPU_BMIPS
1417 select IRQ_CPU
1418 select SWAP_IO_SPACE
1419 select SYS_SUPPORTS_32BIT_KERNEL
1420 select WEAK_ORDERING
1421 help 1442 help
1422 Broadcom BMIPS3300 processors. 1443 Broadcom BMIPS3300 processors.
1423 1444
1424config CPU_BMIPS4350 1445config CPU_BMIPS4350
1425 bool "BMIPS4350" 1446 bool "BMIPS4350"
1426 depends on SYS_HAS_CPU_BMIPS4350 1447 depends on SYS_HAS_CPU_BMIPS4350
1427 select CPU_SUPPORTS_32BIT_KERNEL 1448 select CPU_BMIPS
1428 select DMA_NONCOHERENT
1429 select IRQ_CPU
1430 select SWAP_IO_SPACE
1431 select SYS_SUPPORTS_SMP 1449 select SYS_SUPPORTS_SMP
1432 select SYS_SUPPORTS_HOTPLUG_CPU 1450 select SYS_SUPPORTS_HOTPLUG_CPU
1433 select WEAK_ORDERING
1434 help 1451 help
1435 Broadcom BMIPS4350 ("VIPER") processors. 1452 Broadcom BMIPS4350 ("VIPER") processors.
1436 1453
1437config CPU_BMIPS4380 1454config CPU_BMIPS4380
1438 bool "BMIPS4380" 1455 bool "BMIPS4380"
1439 depends on SYS_HAS_CPU_BMIPS4380 1456 depends on SYS_HAS_CPU_BMIPS4380
1440 select CPU_SUPPORTS_32BIT_KERNEL 1457 select CPU_BMIPS
1441 select DMA_NONCOHERENT
1442 select IRQ_CPU
1443 select SWAP_IO_SPACE
1444 select SYS_SUPPORTS_SMP 1458 select SYS_SUPPORTS_SMP
1445 select SYS_SUPPORTS_HOTPLUG_CPU 1459 select SYS_SUPPORTS_HOTPLUG_CPU
1446 select WEAK_ORDERING
1447 help 1460 help
1448 Broadcom BMIPS4380 processors. 1461 Broadcom BMIPS4380 processors.
1449 1462
1450config CPU_BMIPS5000 1463config CPU_BMIPS5000
1451 bool "BMIPS5000" 1464 bool "BMIPS5000"
1452 depends on SYS_HAS_CPU_BMIPS5000 1465 depends on SYS_HAS_CPU_BMIPS5000
1453 select CPU_SUPPORTS_32BIT_KERNEL 1466 select CPU_BMIPS
1454 select CPU_SUPPORTS_HIGHMEM 1467 select CPU_SUPPORTS_HIGHMEM
1455 select DMA_NONCOHERENT 1468 select MIPS_CPU_SCACHE
1456 select IRQ_CPU
1457 select SWAP_IO_SPACE
1458 select SYS_SUPPORTS_SMP 1469 select SYS_SUPPORTS_SMP
1459 select SYS_SUPPORTS_HOTPLUG_CPU 1470 select SYS_SUPPORTS_HOTPLUG_CPU
1460 select WEAK_ORDERING
1461 help 1471 help
1462 Broadcom BMIPS5000 processors. 1472 Broadcom BMIPS5000 processors.
1463 1473
@@ -1472,6 +1482,19 @@ config CPU_XLR
1472 select CPU_SUPPORTS_HUGEPAGES 1482 select CPU_SUPPORTS_HUGEPAGES
1473 help 1483 help
1474 Netlogic Microsystems XLR/XLS processors. 1484 Netlogic Microsystems XLR/XLS processors.
1485
1486config CPU_XLP
1487 bool "Netlogic XLP SoC"
1488 depends on SYS_HAS_CPU_XLP
1489 select CPU_SUPPORTS_32BIT_KERNEL
1490 select CPU_SUPPORTS_64BIT_KERNEL
1491 select CPU_SUPPORTS_HIGHMEM
1492 select CPU_HAS_LLSC
1493 select WEAK_ORDERING
1494 select WEAK_REORDERING_BEYOND_LLSC
1495 select CPU_HAS_PREFETCH
1496 help
1497 Netlogic Microsystems XLP processors.
1475endchoice 1498endchoice
1476 1499
1477if CPU_LOONGSON2F 1500if CPU_LOONGSON2F
@@ -1518,6 +1541,15 @@ config CPU_LOONGSON2
1518 select CPU_SUPPORTS_64BIT_KERNEL 1541 select CPU_SUPPORTS_64BIT_KERNEL
1519 select CPU_SUPPORTS_HIGHMEM 1542 select CPU_SUPPORTS_HIGHMEM
1520 1543
1544config CPU_BMIPS
1545 bool
1546 select CPU_MIPS32
1547 select CPU_SUPPORTS_32BIT_KERNEL
1548 select DMA_NONCOHERENT
1549 select IRQ_CPU
1550 select SWAP_IO_SPACE
1551 select WEAK_ORDERING
1552
1521config SYS_HAS_CPU_LOONGSON2E 1553config SYS_HAS_CPU_LOONGSON2E
1522 bool 1554 bool
1523 1555
@@ -1605,6 +1637,9 @@ config SYS_HAS_CPU_BMIPS5000
1605config SYS_HAS_CPU_XLR 1637config SYS_HAS_CPU_XLR
1606 bool 1638 bool
1607 1639
1640config SYS_HAS_CPU_XLP
1641 bool
1642
1608# 1643#
1609# CPU may reorder R->R, R->W, W->R, W->W 1644# CPU may reorder R->R, R->W, W->R, W->W
1610# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC 1645# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@@ -1992,6 +2027,9 @@ config CPU_HAS_SMARTMIPS
1992config CPU_HAS_WB 2027config CPU_HAS_WB
1993 bool 2028 bool
1994 2029
2030config XKS01
2031 bool
2032
1995# 2033#
1996# Vectored interrupt mode is an R2 feature 2034# Vectored interrupt mode is an R2 feature
1997# 2035#
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 0be318609fc6..4fedf5a51d96 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -157,6 +157,7 @@ ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
157cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon 157cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
158endif 158endif
159cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 159cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
160cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap
160 161
161cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) 162cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
162cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) 163cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c
index bb571bcdb8f2..d8dbd8f0c1d2 100644
--- a/arch/mips/ar7/gpio.c
+++ b/arch/mips/ar7/gpio.c
@@ -217,7 +217,7 @@ struct titan_gpio_cfg {
217 u32 func; 217 u32 func;
218}; 218};
219 219
220static struct titan_gpio_cfg titan_gpio_table[] = { 220static const struct titan_gpio_cfg titan_gpio_table[] = {
221 /* reg, start bit, mux value */ 221 /* reg, start bit, mux value */
222 {4, 24, 1}, 222 {4, 24, 1},
223 {4, 26, 1}, 223 {4, 26, 1},
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 60102392af01..1a24d317e7a3 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -462,6 +462,40 @@ static struct gpio_led fb_fon_leds[] = {
462 }, 462 },
463}; 463};
464 464
465static struct gpio_led gt701_leds[] = {
466 {
467 .name = "inet:green",
468 .gpio = 13,
469 .active_low = 1,
470 },
471 {
472 .name = "usb",
473 .gpio = 12,
474 .active_low = 1,
475 },
476 {
477 .name = "inet:red",
478 .gpio = 9,
479 .active_low = 1,
480 },
481 {
482 .name = "power:red",
483 .gpio = 7,
484 .active_low = 1,
485 },
486 {
487 .name = "power:green",
488 .gpio = 8,
489 .active_low = 1,
490 .default_trigger = "default-on",
491 },
492 {
493 .name = "ethernet",
494 .gpio = 10,
495 .active_low = 1,
496 },
497};
498
465static struct gpio_led_platform_data ar7_led_data; 499static struct gpio_led_platform_data ar7_led_data;
466 500
467static struct platform_device ar7_gpio_leds = { 501static struct platform_device ar7_gpio_leds = {
@@ -503,6 +537,9 @@ static void __init detect_leds(void)
503 } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) { 537 } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
504 ar7_led_data.num_leds = ARRAY_SIZE(titan_leds); 538 ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
505 ar7_led_data.leds = titan_leds; 539 ar7_led_data.leds = titan_leds;
540 } else if (strstr(prid, "GT701")) {
541 ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds);
542 ar7_led_data.leds = gt701_leds;
506 } 543 }
507} 544}
508 545
diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c
index 8088c6fdb83e..a23adc49d50f 100644
--- a/arch/mips/ar7/prom.c
+++ b/arch/mips/ar7/prom.c
@@ -69,7 +69,7 @@ struct psbl_rec {
69 u32 ffs_size; 69 u32 ffs_size;
70}; 70};
71 71
72static __initdata char psp_env_version[] = "TIENV0.8"; 72static const char psp_env_version[] __initconst = "TIENV0.8";
73 73
74struct psp_env_chunk { 74struct psp_env_chunk {
75 u8 num; 75 u8 num;
@@ -84,7 +84,7 @@ struct psp_var_map_entry {
84 char *value; 84 char *value;
85}; 85};
86 86
87static struct psp_var_map_entry psp_var_map[] = { 87static const struct psp_var_map_entry psp_var_map[] = {
88 { 1, "cpufrequency" }, 88 { 1, "cpufrequency" },
89 { 2, "memsize" }, 89 { 2, "memsize" },
90 { 3, "flashsize" }, 90 { 3, "flashsize" },
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index 47707410582c..e0fae8f4442b 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -2,13 +2,26 @@ if ATH79
2 2
3menu "Atheros AR71XX/AR724X/AR913X machine selection" 3menu "Atheros AR71XX/AR724X/AR913X machine selection"
4 4
5config ATH79_MACH_AP121
6 bool "Atheros AP121 reference board"
7 select SOC_AR933X
8 select ATH79_DEV_GPIO_BUTTONS
9 select ATH79_DEV_LEDS_GPIO
10 select ATH79_DEV_SPI
11 select ATH79_DEV_USB
12 select ATH79_DEV_WMAC
13 help
14 Say 'Y' here if you want your kernel to support the
15 Atheros AP121 reference board.
16
5config ATH79_MACH_AP81 17config ATH79_MACH_AP81
6 bool "Atheros AP81 reference board" 18 bool "Atheros AP81 reference board"
7 select SOC_AR913X 19 select SOC_AR913X
8 select ATH79_DEV_AR913X_WMAC
9 select ATH79_DEV_GPIO_BUTTONS 20 select ATH79_DEV_GPIO_BUTTONS
10 select ATH79_DEV_LEDS_GPIO 21 select ATH79_DEV_LEDS_GPIO
11 select ATH79_DEV_SPI 22 select ATH79_DEV_SPI
23 select ATH79_DEV_USB
24 select ATH79_DEV_WMAC
12 help 25 help
13 Say 'Y' here if you want your kernel to support the 26 Say 'Y' here if you want your kernel to support the
14 Atheros AP81 reference board. 27 Atheros AP81 reference board.
@@ -19,10 +32,21 @@ config ATH79_MACH_PB44
19 select ATH79_DEV_GPIO_BUTTONS 32 select ATH79_DEV_GPIO_BUTTONS
20 select ATH79_DEV_LEDS_GPIO 33 select ATH79_DEV_LEDS_GPIO
21 select ATH79_DEV_SPI 34 select ATH79_DEV_SPI
35 select ATH79_DEV_USB
22 help 36 help
23 Say 'Y' here if you want your kernel to support the 37 Say 'Y' here if you want your kernel to support the
24 Atheros PB44 reference board. 38 Atheros PB44 reference board.
25 39
40config ATH79_MACH_UBNT_XM
41 bool "Ubiquiti Networks XM (rev 1.0) board"
42 select SOC_AR724X
43 select ATH79_DEV_GPIO_BUTTONS
44 select ATH79_DEV_LEDS_GPIO
45 select ATH79_DEV_SPI
46 help
47 Say 'Y' here if you want your kernel to support the
48 Ubiquiti Networks XM (rev 1.0) board.
49
26endmenu 50endmenu
27 51
28config SOC_AR71XX 52config SOC_AR71XX
@@ -33,14 +57,15 @@ config SOC_AR71XX
33config SOC_AR724X 57config SOC_AR724X
34 select USB_ARCH_HAS_EHCI 58 select USB_ARCH_HAS_EHCI
35 select USB_ARCH_HAS_OHCI 59 select USB_ARCH_HAS_OHCI
60 select HW_HAS_PCI
36 def_bool n 61 def_bool n
37 62
38config SOC_AR913X 63config SOC_AR913X
39 select USB_ARCH_HAS_EHCI 64 select USB_ARCH_HAS_EHCI
40 def_bool n 65 def_bool n
41 66
42config ATH79_DEV_AR913X_WMAC 67config SOC_AR933X
43 depends on SOC_AR913X 68 select USB_ARCH_HAS_EHCI
44 def_bool n 69 def_bool n
45 70
46config ATH79_DEV_GPIO_BUTTONS 71config ATH79_DEV_GPIO_BUTTONS
@@ -52,4 +77,11 @@ config ATH79_DEV_LEDS_GPIO
52config ATH79_DEV_SPI 77config ATH79_DEV_SPI
53 def_bool n 78 def_bool n
54 79
80config ATH79_DEV_USB
81 def_bool n
82
83config ATH79_DEV_WMAC
84 depends on (SOC_AR913X || SOC_AR933X)
85 def_bool n
86
55endif 87endif
diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile
index c33d4653007c..3b911e09dbec 100644
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -16,13 +16,16 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
16# Devices 16# Devices
17# 17#
18obj-y += dev-common.o 18obj-y += dev-common.o
19obj-$(CONFIG_ATH79_DEV_AR913X_WMAC) += dev-ar913x-wmac.o
20obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o 19obj-$(CONFIG_ATH79_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o
21obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o 20obj-$(CONFIG_ATH79_DEV_LEDS_GPIO) += dev-leds-gpio.o
22obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o 21obj-$(CONFIG_ATH79_DEV_SPI) += dev-spi.o
22obj-$(CONFIG_ATH79_DEV_USB) += dev-usb.o
23obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
23 24
24# 25#
25# Machines 26# Machines
26# 27#
28obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
27obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o 29obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
28obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o 30obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
31obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 680bde99a26c..54d0eb4db987 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -110,6 +110,59 @@ static void __init ar913x_clocks_init(void)
110 ath79_uart_clk.rate = ath79_ahb_clk.rate; 110 ath79_uart_clk.rate = ath79_ahb_clk.rate;
111} 111}
112 112
113static void __init ar933x_clocks_init(void)
114{
115 u32 clock_ctrl;
116 u32 cpu_config;
117 u32 freq;
118 u32 t;
119
120 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
121 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
122 ath79_ref_clk.rate = (40 * 1000 * 1000);
123 else
124 ath79_ref_clk.rate = (25 * 1000 * 1000);
125
126 clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
127 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
128 ath79_cpu_clk.rate = ath79_ref_clk.rate;
129 ath79_ahb_clk.rate = ath79_ref_clk.rate;
130 ath79_ddr_clk.rate = ath79_ref_clk.rate;
131 } else {
132 cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
133
134 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
135 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
136 freq = ath79_ref_clk.rate / t;
137
138 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
139 AR933X_PLL_CPU_CONFIG_NINT_MASK;
140 freq *= t;
141
142 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
143 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
144 if (t == 0)
145 t = 1;
146
147 freq >>= t;
148
149 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
150 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
151 ath79_cpu_clk.rate = freq / t;
152
153 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
154 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
155 ath79_ddr_clk.rate = freq / t;
156
157 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
158 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
159 ath79_ahb_clk.rate = freq / t;
160 }
161
162 ath79_wdt_clk.rate = ath79_ref_clk.rate;
163 ath79_uart_clk.rate = ath79_ref_clk.rate;
164}
165
113void __init ath79_clocks_init(void) 166void __init ath79_clocks_init(void)
114{ 167{
115 if (soc_is_ar71xx()) 168 if (soc_is_ar71xx())
@@ -118,6 +171,8 @@ void __init ath79_clocks_init(void)
118 ar724x_clocks_init(); 171 ar724x_clocks_init();
119 else if (soc_is_ar913x()) 172 else if (soc_is_ar913x())
120 ar913x_clocks_init(); 173 ar913x_clocks_init();
174 else if (soc_is_ar933x())
175 ar933x_clocks_init();
121 else 176 else
122 BUG(); 177 BUG();
123 178
diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
index 58f60e722a03..f0fda982b965 100644
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -30,6 +30,7 @@ u32 ath79_ddr_freq;
30EXPORT_SYMBOL_GPL(ath79_ddr_freq); 30EXPORT_SYMBOL_GPL(ath79_ddr_freq);
31 31
32enum ath79_soc_type ath79_soc; 32enum ath79_soc_type ath79_soc;
33unsigned int ath79_soc_rev;
33 34
34void __iomem *ath79_pll_base; 35void __iomem *ath79_pll_base;
35void __iomem *ath79_reset_base; 36void __iomem *ath79_reset_base;
@@ -64,6 +65,8 @@ void ath79_device_reset_set(u32 mask)
64 reg = AR724X_RESET_REG_RESET_MODULE; 65 reg = AR724X_RESET_REG_RESET_MODULE;
65 else if (soc_is_ar913x()) 66 else if (soc_is_ar913x())
66 reg = AR913X_RESET_REG_RESET_MODULE; 67 reg = AR913X_RESET_REG_RESET_MODULE;
68 else if (soc_is_ar933x())
69 reg = AR933X_RESET_REG_RESET_MODULE;
67 else 70 else
68 BUG(); 71 BUG();
69 72
@@ -86,6 +89,8 @@ void ath79_device_reset_clear(u32 mask)
86 reg = AR724X_RESET_REG_RESET_MODULE; 89 reg = AR724X_RESET_REG_RESET_MODULE;
87 else if (soc_is_ar913x()) 90 else if (soc_is_ar913x())
88 reg = AR913X_RESET_REG_RESET_MODULE; 91 reg = AR913X_RESET_REG_RESET_MODULE;
92 else if (soc_is_ar933x())
93 reg = AR933X_RESET_REG_RESET_MODULE;
89 else 94 else
90 BUG(); 95 BUG();
91 96
diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c
deleted file mode 100644
index 48f425a5ba28..000000000000
--- a/arch/mips/ath79/dev-ar913x-wmac.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Atheros AR913X SoC built-in WMAC device support
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/irq.h>
15#include <linux/platform_device.h>
16#include <linux/ath9k_platform.h>
17
18#include <asm/mach-ath79/ath79.h>
19#include <asm/mach-ath79/ar71xx_regs.h>
20#include "dev-ar913x-wmac.h"
21
22static struct ath9k_platform_data ar913x_wmac_data;
23
24static struct resource ar913x_wmac_resources[] = {
25 {
26 .start = AR913X_WMAC_BASE,
27 .end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1,
28 .flags = IORESOURCE_MEM,
29 }, {
30 .start = ATH79_CPU_IRQ_IP2,
31 .end = ATH79_CPU_IRQ_IP2,
32 .flags = IORESOURCE_IRQ,
33 },
34};
35
36static struct platform_device ar913x_wmac_device = {
37 .name = "ath9k",
38 .id = -1,
39 .resource = ar913x_wmac_resources,
40 .num_resources = ARRAY_SIZE(ar913x_wmac_resources),
41 .dev = {
42 .platform_data = &ar913x_wmac_data,
43 },
44};
45
46void __init ath79_register_ar913x_wmac(u8 *cal_data)
47{
48 if (cal_data)
49 memcpy(ar913x_wmac_data.eeprom_data, cal_data,
50 sizeof(ar913x_wmac_data.eeprom_data));
51
52 /* reset the WMAC */
53 ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
54 mdelay(10);
55
56 ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
57 mdelay(10);
58
59 platform_device_register(&ar913x_wmac_device);
60}
diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
index 3b82e325bebf..f4956f809072 100644
--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
@@ -20,6 +20,7 @@
20 20
21#include <asm/mach-ath79/ath79.h> 21#include <asm/mach-ath79/ath79.h>
22#include <asm/mach-ath79/ar71xx_regs.h> 22#include <asm/mach-ath79/ar71xx_regs.h>
23#include <asm/mach-ath79/ar933x_uart_platform.h>
23#include "common.h" 24#include "common.h"
24#include "dev-common.h" 25#include "dev-common.h"
25 26
@@ -54,6 +55,30 @@ static struct platform_device ath79_uart_device = {
54 }, 55 },
55}; 56};
56 57
58static struct resource ar933x_uart_resources[] = {
59 {
60 .start = AR933X_UART_BASE,
61 .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
62 .flags = IORESOURCE_MEM,
63 },
64 {
65 .start = ATH79_MISC_IRQ_UART,
66 .end = ATH79_MISC_IRQ_UART,
67 .flags = IORESOURCE_IRQ,
68 },
69};
70
71static struct ar933x_uart_platform_data ar933x_uart_data;
72static struct platform_device ar933x_uart_device = {
73 .name = "ar933x-uart",
74 .id = -1,
75 .resource = ar933x_uart_resources,
76 .num_resources = ARRAY_SIZE(ar933x_uart_resources),
77 .dev = {
78 .platform_data = &ar933x_uart_data,
79 },
80};
81
57void __init ath79_register_uart(void) 82void __init ath79_register_uart(void)
58{ 83{
59 struct clk *clk; 84 struct clk *clk;
@@ -62,8 +87,17 @@ void __init ath79_register_uart(void)
62 if (IS_ERR(clk)) 87 if (IS_ERR(clk))
63 panic("unable to get UART clock, err=%ld", PTR_ERR(clk)); 88 panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
64 89
65 ath79_uart_data[0].uartclk = clk_get_rate(clk); 90 if (soc_is_ar71xx() ||
66 platform_device_register(&ath79_uart_device); 91 soc_is_ar724x() ||
92 soc_is_ar913x()) {
93 ath79_uart_data[0].uartclk = clk_get_rate(clk);
94 platform_device_register(&ath79_uart_device);
95 } else if (soc_is_ar933x()) {
96 ar933x_uart_data.uartclk = clk_get_rate(clk);
97 platform_device_register(&ar933x_uart_device);
98 } else {
99 BUG();
100 }
67} 101}
68 102
69static struct platform_device ath79_wdt_device = { 103static struct platform_device ath79_wdt_device = {
diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c
new file mode 100644
index 000000000000..002d6d2afe04
--- /dev/null
+++ b/arch/mips/ath79/dev-usb.c
@@ -0,0 +1,197 @@
1/*
2 * Atheros AR7XXX/AR9XXX USB Host Controller device
3 *
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/irq.h>
18#include <linux/dma-mapping.h>
19#include <linux/platform_device.h>
20
21#include <asm/mach-ath79/ath79.h>
22#include <asm/mach-ath79/ar71xx_regs.h>
23#include "common.h"
24#include "dev-usb.h"
25
26static struct resource ath79_ohci_resources[] = {
27 [0] = {
28 /* .start and .end fields are filled dynamically */
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .start = ATH79_MISC_IRQ_OHCI,
33 .end = ATH79_MISC_IRQ_OHCI,
34 .flags = IORESOURCE_IRQ,
35 },
36};
37
38static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
39static struct platform_device ath79_ohci_device = {
40 .name = "ath79-ohci",
41 .id = -1,
42 .resource = ath79_ohci_resources,
43 .num_resources = ARRAY_SIZE(ath79_ohci_resources),
44 .dev = {
45 .dma_mask = &ath79_ohci_dmamask,
46 .coherent_dma_mask = DMA_BIT_MASK(32),
47 },
48};
49
50static struct resource ath79_ehci_resources[] = {
51 [0] = {
52 /* .start and .end fields are filled dynamically */
53 .flags = IORESOURCE_MEM,
54 },
55 [1] = {
56 .start = ATH79_CPU_IRQ_USB,
57 .end = ATH79_CPU_IRQ_USB,
58 .flags = IORESOURCE_IRQ,
59 },
60};
61
62static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
63static struct platform_device ath79_ehci_device = {
64 .name = "ath79-ehci",
65 .id = -1,
66 .resource = ath79_ehci_resources,
67 .num_resources = ARRAY_SIZE(ath79_ehci_resources),
68 .dev = {
69 .dma_mask = &ath79_ehci_dmamask,
70 .coherent_dma_mask = DMA_BIT_MASK(32),
71 },
72};
73
74#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
75 AR71XX_RESET_USB_PHY | \
76 AR71XX_RESET_USB_OHCI_DLL)
77
78static void __init ath79_usb_setup(void)
79{
80 void __iomem *usb_ctrl_base;
81
82 ath79_device_reset_set(AR71XX_USB_RESET_MASK);
83 mdelay(1000);
84 ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
85
86 usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
87
88 /* Turning on the Buff and Desc swap bits */
89 __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
90
91 /* WAR for HW bug. Here it adjusts the duration between two SOFS */
92 __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
93
94 iounmap(usb_ctrl_base);
95
96 mdelay(900);
97
98 ath79_ohci_resources[0].start = AR71XX_OHCI_BASE;
99 ath79_ohci_resources[0].end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1;
100 platform_device_register(&ath79_ohci_device);
101
102 ath79_ehci_resources[0].start = AR71XX_EHCI_BASE;
103 ath79_ehci_resources[0].end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1;
104 ath79_ehci_device.name = "ar71xx-ehci";
105 platform_device_register(&ath79_ehci_device);
106}
107
108static void __init ar7240_usb_setup(void)
109{
110 void __iomem *usb_ctrl_base;
111
112 ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
113 ath79_device_reset_set(AR7240_RESET_USB_HOST);
114
115 mdelay(1000);
116
117 ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
118 ath79_device_reset_clear(AR7240_RESET_USB_HOST);
119
120 usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
121
122 /* WAR for HW bug. Here it adjusts the duration between two SOFS */
123 __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
124
125 iounmap(usb_ctrl_base);
126
127 ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
128 ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
129 platform_device_register(&ath79_ohci_device);
130}
131
132static void __init ar724x_usb_setup(void)
133{
134 ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
135 mdelay(10);
136
137 ath79_device_reset_clear(AR724X_RESET_USB_HOST);
138 mdelay(10);
139
140 ath79_device_reset_clear(AR724X_RESET_USB_PHY);
141 mdelay(10);
142
143 ath79_ehci_resources[0].start = AR724X_EHCI_BASE;
144 ath79_ehci_resources[0].end = AR724X_EHCI_BASE + AR724X_EHCI_SIZE - 1;
145 ath79_ehci_device.name = "ar724x-ehci";
146 platform_device_register(&ath79_ehci_device);
147}
148
149static void __init ar913x_usb_setup(void)
150{
151 ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
152 mdelay(10);
153
154 ath79_device_reset_clear(AR913X_RESET_USB_HOST);
155 mdelay(10);
156
157 ath79_device_reset_clear(AR913X_RESET_USB_PHY);
158 mdelay(10);
159
160 ath79_ehci_resources[0].start = AR913X_EHCI_BASE;
161 ath79_ehci_resources[0].end = AR913X_EHCI_BASE + AR913X_EHCI_SIZE - 1;
162 ath79_ehci_device.name = "ar913x-ehci";
163 platform_device_register(&ath79_ehci_device);
164}
165
166static void __init ar933x_usb_setup(void)
167{
168 ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
169 mdelay(10);
170
171 ath79_device_reset_clear(AR933X_RESET_USB_HOST);
172 mdelay(10);
173
174 ath79_device_reset_clear(AR933X_RESET_USB_PHY);
175 mdelay(10);
176
177 ath79_ehci_resources[0].start = AR933X_EHCI_BASE;
178 ath79_ehci_resources[0].end = AR933X_EHCI_BASE + AR933X_EHCI_SIZE - 1;
179 ath79_ehci_device.name = "ar933x-ehci";
180 platform_device_register(&ath79_ehci_device);
181}
182
183void __init ath79_register_usb(void)
184{
185 if (soc_is_ar71xx())
186 ath79_usb_setup();
187 else if (soc_is_ar7240())
188 ar7240_usb_setup();
189 else if (soc_is_ar7241() || soc_is_ar7242())
190 ar724x_usb_setup();
191 else if (soc_is_ar913x())
192 ar913x_usb_setup();
193 else if (soc_is_ar933x())
194 ar933x_usb_setup();
195 else
196 BUG();
197}
diff --git a/arch/mips/ath79/dev-ar913x-wmac.h b/arch/mips/ath79/dev-usb.h
index 579d562bbda8..4b86a69ca080 100644
--- a/arch/mips/ath79/dev-ar913x-wmac.h
+++ b/arch/mips/ath79/dev-usb.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Atheros AR913X SoC built-in WMAC device support 2 * Atheros AR71XX/AR724X/AR913X USB Host Controller support
3 * 3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
@@ -9,9 +9,9 @@
9 * by the Free Software Foundation. 9 * by the Free Software Foundation.
10 */ 10 */
11 11
12#ifndef _ATH79_DEV_AR913X_WMAC_H 12#ifndef _ATH79_DEV_USB_H
13#define _ATH79_DEV_AR913X_WMAC_H 13#define _ATH79_DEV_USB_H
14 14
15void ath79_register_ar913x_wmac(u8 *cal_data); 15void ath79_register_usb(void);
16 16
17#endif /* _ATH79_DEV_AR913X_WMAC_H */ 17#endif /* _ATH79_DEV_USB_H */
diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c
new file mode 100644
index 000000000000..24f546985b69
--- /dev/null
+++ b/arch/mips/ath79/dev-wmac.c
@@ -0,0 +1,109 @@
1/*
2 * Atheros AR913X/AR933X SoC built-in WMAC device support
3 *
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/irq.h>
15#include <linux/platform_device.h>
16#include <linux/ath9k_platform.h>
17
18#include <asm/mach-ath79/ath79.h>
19#include <asm/mach-ath79/ar71xx_regs.h>
20#include "dev-wmac.h"
21
22static struct ath9k_platform_data ath79_wmac_data;
23
24static struct resource ath79_wmac_resources[] = {
25 {
26 /* .start and .end fields are filled dynamically */
27 .flags = IORESOURCE_MEM,
28 }, {
29 .start = ATH79_CPU_IRQ_IP2,
30 .end = ATH79_CPU_IRQ_IP2,
31 .flags = IORESOURCE_IRQ,
32 },
33};
34
35static struct platform_device ath79_wmac_device = {
36 .name = "ath9k",
37 .id = -1,
38 .resource = ath79_wmac_resources,
39 .num_resources = ARRAY_SIZE(ath79_wmac_resources),
40 .dev = {
41 .platform_data = &ath79_wmac_data,
42 },
43};
44
45static void __init ar913x_wmac_setup(void)
46{
47 /* reset the WMAC */
48 ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
49 mdelay(10);
50
51 ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
52 mdelay(10);
53
54 ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
55 ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
56}
57
58
59static int ar933x_wmac_reset(void)
60{
61 ath79_device_reset_clear(AR933X_RESET_WMAC);
62 ath79_device_reset_set(AR933X_RESET_WMAC);
63
64 return 0;
65}
66
67static int ar933x_r1_get_wmac_revision(void)
68{
69 return ath79_soc_rev;
70}
71
72static void __init ar933x_wmac_setup(void)
73{
74 u32 t;
75
76 ar933x_wmac_reset();
77
78 ath79_wmac_device.name = "ar933x_wmac";
79
80 ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
81 ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
82
83 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
84 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
85 ath79_wmac_data.is_clk_25mhz = false;
86 else
87 ath79_wmac_data.is_clk_25mhz = true;
88
89 if (ath79_soc_rev == 1)
90 ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
91
92 ath79_wmac_data.external_reset = ar933x_wmac_reset;
93}
94
95void __init ath79_register_wmac(u8 *cal_data)
96{
97 if (soc_is_ar913x())
98 ar913x_wmac_setup();
99 if (soc_is_ar933x())
100 ar933x_wmac_setup();
101 else
102 BUG();
103
104 if (cal_data)
105 memcpy(ath79_wmac_data.eeprom_data, cal_data,
106 sizeof(ath79_wmac_data.eeprom_data));
107
108 platform_device_register(&ath79_wmac_device);
109}
diff --git a/arch/mips/ath79/dev-wmac.h b/arch/mips/ath79/dev-wmac.h
new file mode 100644
index 000000000000..c9cd8709f090
--- /dev/null
+++ b/arch/mips/ath79/dev-wmac.h
@@ -0,0 +1,17 @@
1/*
2 * Atheros AR913X/AR933X SoC built-in WMAC device support
3 *
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12#ifndef _ATH79_DEV_WMAC_H
13#define _ATH79_DEV_WMAC_H
14
15void ath79_register_wmac(u8 *cal_data);
16
17#endif /* _ATH79_DEV_WMAC_H */
diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
index 7499b0e9df26..6a51ced7a293 100644
--- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Atheros AR71XX/AR724X/AR913X SoC early printk support 2 * Atheros AR7XXX/AR9XXX SoC early printk support
3 * 3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> 4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
@@ -10,27 +10,85 @@
10 */ 10 */
11 11
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/errno.h>
13#include <linux/serial_reg.h> 14#include <linux/serial_reg.h>
14#include <asm/addrspace.h> 15#include <asm/addrspace.h>
15 16
17#include <asm/mach-ath79/ath79.h>
16#include <asm/mach-ath79/ar71xx_regs.h> 18#include <asm/mach-ath79/ar71xx_regs.h>
19#include <asm/mach-ath79/ar933x_uart.h>
17 20
18static inline void prom_wait_thre(void __iomem *base) 21static void (*_prom_putchar) (unsigned char);
22
23static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
19{ 24{
20 u32 lsr; 25 u32 t;
21 26
22 do { 27 do {
23 lsr = __raw_readl(base + UART_LSR * 4); 28 t = __raw_readl(reg);
24 if (lsr & UART_LSR_THRE) 29 if ((t & mask) == val)
25 break; 30 break;
26 } while (1); 31 } while (1);
27} 32}
28 33
29void prom_putchar(unsigned char ch) 34static void prom_putchar_ar71xx(unsigned char ch)
30{ 35{
31 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); 36 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
32 37
33 prom_wait_thre(base); 38 prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
34 __raw_writel(ch, base + UART_TX * 4); 39 __raw_writel(ch, base + UART_TX * 4);
35 prom_wait_thre(base); 40 prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
41}
42
43static void prom_putchar_ar933x(unsigned char ch)
44{
45 void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
46
47 prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
48 AR933X_UART_DATA_TX_CSR);
49 __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
50 prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
51 AR933X_UART_DATA_TX_CSR);
52}
53
54static void prom_putchar_dummy(unsigned char ch)
55{
56 /* nothing to do */
57}
58
59static void prom_putchar_init(void)
60{
61 void __iomem *base;
62 u32 id;
63
64 base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
65 id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
66 id &= REV_ID_MAJOR_MASK;
67
68 switch (id) {
69 case REV_ID_MAJOR_AR71XX:
70 case REV_ID_MAJOR_AR7240:
71 case REV_ID_MAJOR_AR7241:
72 case REV_ID_MAJOR_AR7242:
73 case REV_ID_MAJOR_AR913X:
74 _prom_putchar = prom_putchar_ar71xx;
75 break;
76
77 case REV_ID_MAJOR_AR9330:
78 case REV_ID_MAJOR_AR9331:
79 _prom_putchar = prom_putchar_ar933x;
80 break;
81
82 default:
83 _prom_putchar = prom_putchar_dummy;
84 break;
85 }
86}
87
88void prom_putchar(unsigned char ch)
89{
90 if (!_prom_putchar)
91 prom_putchar_init();
92
93 _prom_putchar(ch);
36} 94}
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c
index a0c426b82123..a2f8ca630ed6 100644
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
@@ -153,6 +153,8 @@ void __init ath79_gpio_init(void)
153 ath79_gpio_count = AR724X_GPIO_COUNT; 153 ath79_gpio_count = AR724X_GPIO_COUNT;
154 else if (soc_is_ar913x()) 154 else if (soc_is_ar913x())
155 ath79_gpio_count = AR913X_GPIO_COUNT; 155 ath79_gpio_count = AR913X_GPIO_COUNT;
156 else if (soc_is_ar933x())
157 ath79_gpio_count = AR933X_GPIO_COUNT;
156 else 158 else
157 BUG(); 159 BUG();
158 160
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index ac610d5fe3ba..1b073de44680 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
46 else if (pending & MISC_INT_TIMER) 46 else if (pending & MISC_INT_TIMER)
47 generic_handle_irq(ATH79_MISC_IRQ_TIMER); 47 generic_handle_irq(ATH79_MISC_IRQ_TIMER);
48 48
49 else if (pending & MISC_INT_TIMER2)
50 generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
51
52 else if (pending & MISC_INT_TIMER3)
53 generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
54
55 else if (pending & MISC_INT_TIMER4)
56 generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
57
49 else if (pending & MISC_INT_OHCI) 58 else if (pending & MISC_INT_OHCI)
50 generic_handle_irq(ATH79_MISC_IRQ_OHCI); 59 generic_handle_irq(ATH79_MISC_IRQ_OHCI);
51 60
@@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
58 else if (pending & MISC_INT_WDOG) 67 else if (pending & MISC_INT_WDOG)
59 generic_handle_irq(ATH79_MISC_IRQ_WDOG); 68 generic_handle_irq(ATH79_MISC_IRQ_WDOG);
60 69
70 else if (pending & MISC_INT_ETHSW)
71 generic_handle_irq(ATH79_MISC_IRQ_ETHSW);
72
61 else 73 else
62 spurious_interrupt(); 74 spurious_interrupt();
63} 75}
@@ -117,7 +129,7 @@ static void __init ath79_misc_irq_init(void)
117 129
118 if (soc_is_ar71xx() || soc_is_ar913x()) 130 if (soc_is_ar71xx() || soc_is_ar913x())
119 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; 131 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
120 else if (soc_is_ar724x()) 132 else if (soc_is_ar724x() || soc_is_ar933x())
121 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; 133 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
122 else 134 else
123 BUG(); 135 BUG();
@@ -174,6 +186,9 @@ void __init arch_init_irq(void)
174 } else if (soc_is_ar913x()) { 186 } else if (soc_is_ar913x()) {
175 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; 187 ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
176 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; 188 ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
189 } else if (soc_is_ar933x()) {
190 ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
191 ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
177 } else 192 } else
178 BUG(); 193 BUG();
179 194
diff --git a/arch/mips/ath79/mach-ap121.c b/arch/mips/ath79/mach-ap121.c
new file mode 100644
index 000000000000..4c20200d7c72
--- /dev/null
+++ b/arch/mips/ath79/mach-ap121.c
@@ -0,0 +1,92 @@
1/*
2 * Atheros AP121 board support
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#include "machtypes.h"
12#include "dev-gpio-buttons.h"
13#include "dev-leds-gpio.h"
14#include "dev-spi.h"
15#include "dev-usb.h"
16#include "dev-wmac.h"
17
18#define AP121_GPIO_LED_WLAN 0
19#define AP121_GPIO_LED_USB 1
20
21#define AP121_GPIO_BTN_JUMPSTART 11
22#define AP121_GPIO_BTN_RESET 12
23
24#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */
25#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL)
26
27#define AP121_CAL_DATA_ADDR 0x1fff1000
28
29static struct gpio_led ap121_leds_gpio[] __initdata = {
30 {
31 .name = "ap121:green:usb",
32 .gpio = AP121_GPIO_LED_USB,
33 .active_low = 0,
34 },
35 {
36 .name = "ap121:green:wlan",
37 .gpio = AP121_GPIO_LED_WLAN,
38 .active_low = 0,
39 },
40};
41
42static struct gpio_keys_button ap121_gpio_keys[] __initdata = {
43 {
44 .desc = "jumpstart button",
45 .type = EV_KEY,
46 .code = KEY_WPS_BUTTON,
47 .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
48 .gpio = AP121_GPIO_BTN_JUMPSTART,
49 .active_low = 1,
50 },
51 {
52 .desc = "reset button",
53 .type = EV_KEY,
54 .code = KEY_RESTART,
55 .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL,
56 .gpio = AP121_GPIO_BTN_RESET,
57 .active_low = 1,
58 }
59};
60
61static struct spi_board_info ap121_spi_info[] = {
62 {
63 .bus_num = 0,
64 .chip_select = 0,
65 .max_speed_hz = 25000000,
66 .modalias = "mx25l1606e",
67 }
68};
69
70static struct ath79_spi_platform_data ap121_spi_data = {
71 .bus_num = 0,
72 .num_chipselect = 1,
73};
74
75static void __init ap121_setup(void)
76{
77 u8 *cal_data = (u8 *) KSEG1ADDR(AP121_CAL_DATA_ADDR);
78
79 ath79_register_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio),
80 ap121_leds_gpio);
81 ath79_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL,
82 ARRAY_SIZE(ap121_gpio_keys),
83 ap121_gpio_keys);
84
85 ath79_register_spi(&ap121_spi_data, ap121_spi_info,
86 ARRAY_SIZE(ap121_spi_info));
87 ath79_register_usb();
88 ath79_register_wmac(cal_data);
89}
90
91MIPS_MACHINE(ATH79_MACH_AP121, "AP121", "Atheros AP121 reference board",
92 ap121_setup);
diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c
index eee4c121deb4..abe19836331c 100644
--- a/arch/mips/ath79/mach-ap81.c
+++ b/arch/mips/ath79/mach-ap81.c
@@ -10,10 +10,11 @@
10 */ 10 */
11 11
12#include "machtypes.h" 12#include "machtypes.h"
13#include "dev-ar913x-wmac.h" 13#include "dev-wmac.h"
14#include "dev-gpio-buttons.h" 14#include "dev-gpio-buttons.h"
15#include "dev-leds-gpio.h" 15#include "dev-leds-gpio.h"
16#include "dev-spi.h" 16#include "dev-spi.h"
17#include "dev-usb.h"
17 18
18#define AP81_GPIO_LED_STATUS 1 19#define AP81_GPIO_LED_STATUS 1
19#define AP81_GPIO_LED_AOSS 3 20#define AP81_GPIO_LED_AOSS 3
@@ -91,7 +92,8 @@ static void __init ap81_setup(void)
91 ap81_gpio_keys); 92 ap81_gpio_keys);
92 ath79_register_spi(&ap81_spi_data, ap81_spi_info, 93 ath79_register_spi(&ap81_spi_data, ap81_spi_info,
93 ARRAY_SIZE(ap81_spi_info)); 94 ARRAY_SIZE(ap81_spi_info));
94 ath79_register_ar913x_wmac(cal_data); 95 ath79_register_wmac(cal_data);
96 ath79_register_usb();
95} 97}
96 98
97MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board", 99MIPS_MACHINE(ATH79_MACH_AP81, "AP81", "Atheros AP81 reference board",
diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c
index ec7b7a135d53..fe9701a32291 100644
--- a/arch/mips/ath79/mach-pb44.c
+++ b/arch/mips/ath79/mach-pb44.c
@@ -18,6 +18,7 @@
18#include "dev-gpio-buttons.h" 18#include "dev-gpio-buttons.h"
19#include "dev-leds-gpio.h" 19#include "dev-leds-gpio.h"
20#include "dev-spi.h" 20#include "dev-spi.h"
21#include "dev-usb.h"
21 22
22#define PB44_GPIO_I2C_SCL 0 23#define PB44_GPIO_I2C_SCL 0
23#define PB44_GPIO_I2C_SDA 1 24#define PB44_GPIO_I2C_SDA 1
@@ -112,6 +113,7 @@ static void __init pb44_init(void)
112 pb44_gpio_keys); 113 pb44_gpio_keys);
113 ath79_register_spi(&pb44_spi_data, pb44_spi_info, 114 ath79_register_spi(&pb44_spi_data, pb44_spi_info,
114 ARRAY_SIZE(pb44_spi_info)); 115 ARRAY_SIZE(pb44_spi_info));
116 ath79_register_usb();
115} 117}
116 118
117MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board", 119MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
diff --git a/arch/mips/ath79/mach-ubnt-xm.c b/arch/mips/ath79/mach-ubnt-xm.c
new file mode 100644
index 000000000000..3c311a539347
--- /dev/null
+++ b/arch/mips/ath79/mach-ubnt-xm.c
@@ -0,0 +1,119 @@
1/*
2 * Ubiquiti Networks XM (rev 1.0) board support
3 *
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 *
6 * Derived from: mach-pb44.c
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/pci.h>
15
16#ifdef CONFIG_PCI
17#include <linux/ath9k_platform.h>
18#include <asm/mach-ath79/pci-ath724x.h>
19#endif /* CONFIG_PCI */
20
21#include "machtypes.h"
22#include "dev-gpio-buttons.h"
23#include "dev-leds-gpio.h"
24#include "dev-spi.h"
25
26#define UBNT_XM_GPIO_LED_L1 0
27#define UBNT_XM_GPIO_LED_L2 1
28#define UBNT_XM_GPIO_LED_L3 11
29#define UBNT_XM_GPIO_LED_L4 7
30
31#define UBNT_XM_GPIO_BTN_RESET 12
32
33#define UBNT_XM_KEYS_POLL_INTERVAL 20
34#define UBNT_XM_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_XM_KEYS_POLL_INTERVAL)
35
36#define UBNT_XM_PCI_IRQ 48
37#define UBNT_XM_EEPROM_ADDR (u8 *) KSEG1ADDR(0x1fff1000)
38
39static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
40 {
41 .name = "ubnt-xm:red:link1",
42 .gpio = UBNT_XM_GPIO_LED_L1,
43 .active_low = 0,
44 }, {
45 .name = "ubnt-xm:orange:link2",
46 .gpio = UBNT_XM_GPIO_LED_L2,
47 .active_low = 0,
48 }, {
49 .name = "ubnt-xm:green:link3",
50 .gpio = UBNT_XM_GPIO_LED_L3,
51 .active_low = 0,
52 }, {
53 .name = "ubnt-xm:green:link4",
54 .gpio = UBNT_XM_GPIO_LED_L4,
55 .active_low = 0,
56 },
57};
58
59static struct gpio_keys_button ubnt_xm_gpio_keys[] __initdata = {
60 {
61 .desc = "reset",
62 .type = EV_KEY,
63 .code = KEY_RESTART,
64 .debounce_interval = UBNT_XM_KEYS_DEBOUNCE_INTERVAL,
65 .gpio = UBNT_XM_GPIO_BTN_RESET,
66 .active_low = 1,
67 }
68};
69
70static struct spi_board_info ubnt_xm_spi_info[] = {
71 {
72 .bus_num = 0,
73 .chip_select = 0,
74 .max_speed_hz = 25000000,
75 .modalias = "mx25l6405d",
76 }
77};
78
79static struct ath79_spi_platform_data ubnt_xm_spi_data = {
80 .bus_num = 0,
81 .num_chipselect = 1,
82};
83
84#ifdef CONFIG_PCI
85static struct ath9k_platform_data ubnt_xm_eeprom_data;
86
87static struct ath724x_pci_data ubnt_xm_pci_data[] = {
88 {
89 .irq = UBNT_XM_PCI_IRQ,
90 .pdata = &ubnt_xm_eeprom_data,
91 },
92};
93#endif /* CONFIG_PCI */
94
95static void __init ubnt_xm_init(void)
96{
97 ath79_register_leds_gpio(-1, ARRAY_SIZE(ubnt_xm_leds_gpio),
98 ubnt_xm_leds_gpio);
99
100 ath79_register_gpio_keys_polled(-1, UBNT_XM_KEYS_POLL_INTERVAL,
101 ARRAY_SIZE(ubnt_xm_gpio_keys),
102 ubnt_xm_gpio_keys);
103
104 ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
105 ARRAY_SIZE(ubnt_xm_spi_info));
106
107#ifdef CONFIG_PCI
108 memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
109 sizeof(ubnt_xm_eeprom_data.eeprom_data));
110
111 ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
112#endif /* CONFIG_PCI */
113
114}
115
116MIPS_MACHINE(ATH79_MACH_UBNT_XM,
117 "UBNT-XM",
118 "Ubiquiti Networks XM (rev 1.0) board",
119 ubnt_xm_init);
diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h
index 3940fe470b2d..9a1f3826626e 100644
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -16,8 +16,10 @@
16 16
17enum ath79_mach_type { 17enum ath79_mach_type {
18 ATH79_MACH_GENERIC = 0, 18 ATH79_MACH_GENERIC = 0,
19 ATH79_MACH_AP121, /* Atheros AP121 reference board */
19 ATH79_MACH_AP81, /* Atheros AP81 reference board */ 20 ATH79_MACH_AP81, /* Atheros AP81 reference board */
20 ATH79_MACH_PB44, /* Atheros PB44 reference board */ 21 ATH79_MACH_PB44, /* Atheros PB44 reference board */
22 ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
21}; 23};
22 24
23#endif /* _ATH79_MACHTYPE_H */ 25#endif /* _ATH79_MACHTYPE_H */
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 1cf60e1d9dd3..80a7d4023d7f 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -101,19 +101,31 @@ static void __init ath79_detect_sys_type(void)
101 case REV_ID_MAJOR_AR7240: 101 case REV_ID_MAJOR_AR7240:
102 ath79_soc = ATH79_SOC_AR7240; 102 ath79_soc = ATH79_SOC_AR7240;
103 chip = "7240"; 103 chip = "7240";
104 rev = (id & AR724X_REV_ID_REVISION_MASK); 104 rev = id & AR724X_REV_ID_REVISION_MASK;
105 break; 105 break;
106 106
107 case REV_ID_MAJOR_AR7241: 107 case REV_ID_MAJOR_AR7241:
108 ath79_soc = ATH79_SOC_AR7241; 108 ath79_soc = ATH79_SOC_AR7241;
109 chip = "7241"; 109 chip = "7241";
110 rev = (id & AR724X_REV_ID_REVISION_MASK); 110 rev = id & AR724X_REV_ID_REVISION_MASK;
111 break; 111 break;
112 112
113 case REV_ID_MAJOR_AR7242: 113 case REV_ID_MAJOR_AR7242:
114 ath79_soc = ATH79_SOC_AR7242; 114 ath79_soc = ATH79_SOC_AR7242;
115 chip = "7242"; 115 chip = "7242";
116 rev = (id & AR724X_REV_ID_REVISION_MASK); 116 rev = id & AR724X_REV_ID_REVISION_MASK;
117 break;
118
119 case REV_ID_MAJOR_AR9330:
120 ath79_soc = ATH79_SOC_AR9330;
121 chip = "9330";
122 rev = id & AR933X_REV_ID_REVISION_MASK;
123 break;
124
125 case REV_ID_MAJOR_AR9331:
126 ath79_soc = ATH79_SOC_AR9331;
127 chip = "9331";
128 rev = id & AR933X_REV_ID_REVISION_MASK;
117 break; 129 break;
118 130
119 case REV_ID_MAJOR_AR913X: 131 case REV_ID_MAJOR_AR913X:
@@ -137,6 +149,8 @@ static void __init ath79_detect_sys_type(void)
137 panic("ath79: unknown SoC, id:0x%08x", id); 149 panic("ath79: unknown SoC, id:0x%08x", id);
138 } 150 }
139 151
152 ath79_soc_rev = rev;
153
140 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); 154 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
141 pr_info("SoC: %s\n", ath79_sys_type); 155 pr_info("SoC: %s\n", ath79_sys_type);
142} 156}
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index fb177d6df066..6b1b9ad8d857 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -20,6 +20,10 @@ config BCM63XX_CPU_6348
20config BCM63XX_CPU_6358 20config BCM63XX_CPU_6358
21 bool "support 6358 CPU" 21 bool "support 6358 CPU"
22 select HW_HAS_PCI 22 select HW_HAS_PCI
23
24config BCM63XX_CPU_6368
25 bool "support 6368 CPU"
26 select HW_HAS_PCI
23endmenu 27endmenu
24 28
25source "arch/mips/bcm63xx/boards/Kconfig" 29source "arch/mips/bcm63xx/boards/Kconfig"
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 40b223b603be..e62461f817d7 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -709,15 +709,9 @@ void __init board_prom_init(void)
709 char cfe_version[32]; 709 char cfe_version[32];
710 u32 val; 710 u32 val;
711 711
712 /* read base address of boot chip select (0) 712 /* read base address of boot chip select (0) */
713 * 6345 does not have MPI but boots from standard 713 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
714 * MIPS Flash address */ 714 val &= MPI_CSBASE_BASE_MASK;
715 if (BCMCPU_IS_6345())
716 val = 0x1fc00000;
717 else {
718 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
719 val &= MPI_CSBASE_BASE_MASK;
720 }
721 boot_addr = (u8 *)KSEG1ADDR(val); 715 boot_addr = (u8 *)KSEG1ADDR(val);
722 716
723 /* dump cfe version */ 717 /* dump cfe version */
@@ -797,18 +791,6 @@ void __init board_prom_init(void)
797 } 791 }
798 792
799 bcm_gpio_writel(val, GPIO_MODE_REG); 793 bcm_gpio_writel(val, GPIO_MODE_REG);
800
801 /* Generate MAC address for WLAN and
802 * register our SPROM */
803#ifdef CONFIG_SSB_PCIHOST
804 if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
805 memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
806 memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
807 if (ssb_arch_register_fallback_sprom(
808 &bcm63xx_get_fallback_sprom) < 0)
809 printk(KERN_ERR PFX "failed to register fallback SPROM\n");
810 }
811#endif
812} 794}
813 795
814/* 796/*
@@ -892,13 +874,23 @@ int __init board_register_devices(void)
892 if (board.has_dsp) 874 if (board.has_dsp)
893 bcm63xx_dsp_register(&board.dsp); 875 bcm63xx_dsp_register(&board.dsp);
894 876
895 /* read base address of boot chip select (0) */ 877 /* Generate MAC address for WLAN and register our SPROM,
896 if (BCMCPU_IS_6345()) 878 * do this after registering enet devices
897 val = 0x1fc00000; 879 */
898 else { 880#ifdef CONFIG_SSB_PCIHOST
899 val = bcm_mpi_readl(MPI_CSBASE_REG(0)); 881 if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
900 val &= MPI_CSBASE_BASE_MASK; 882 memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
883 memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
884 if (ssb_arch_register_fallback_sprom(
885 &bcm63xx_get_fallback_sprom) < 0)
886 pr_err(PFX "failed to register fallback SPROM\n");
901 } 887 }
888#endif
889
890 /* read base address of boot chip select (0) */
891 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
892 val &= MPI_CSBASE_BASE_MASK;
893
902 mtd_resources[0].start = val; 894 mtd_resources[0].start = val;
903 mtd_resources[0].end = 0x1FFFFFFF; 895 mtd_resources[0].end = 0x1FFFFFFF;
904 896
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 2c68ee9ccee2..9d57c71b7b58 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -10,6 +10,7 @@
10#include <linux/mutex.h> 10#include <linux/mutex.h>
11#include <linux/err.h> 11#include <linux/err.h>
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/delay.h>
13#include <bcm63xx_cpu.h> 14#include <bcm63xx_cpu.h>
14#include <bcm63xx_io.h> 15#include <bcm63xx_io.h>
15#include <bcm63xx_regs.h> 16#include <bcm63xx_regs.h>
@@ -113,6 +114,34 @@ static struct clk clk_ephy = {
113}; 114};
114 115
115/* 116/*
117 * Ethernet switch clock
118 */
119static void enetsw_set(struct clk *clk, int enable)
120{
121 if (!BCMCPU_IS_6368())
122 return;
123 bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
124 CKCTL_6368_SWPKT_USB_EN |
125 CKCTL_6368_SWPKT_SAR_EN, enable);
126 if (enable) {
127 u32 val;
128
129 /* reset switch core afer clock change */
130 val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
131 val &= ~SOFTRESET_6368_ENETSW_MASK;
132 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
133 msleep(10);
134 val |= SOFTRESET_6368_ENETSW_MASK;
135 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
136 msleep(10);
137 }
138}
139
140static struct clk clk_enetsw = {
141 .set = enetsw_set,
142};
143
144/*
116 * PCM clock 145 * PCM clock
117 */ 146 */
118static void pcm_set(struct clk *clk, int enable) 147static void pcm_set(struct clk *clk, int enable)
@@ -131,9 +160,10 @@ static struct clk clk_pcm = {
131 */ 160 */
132static void usbh_set(struct clk *clk, int enable) 161static void usbh_set(struct clk *clk, int enable)
133{ 162{
134 if (!BCMCPU_IS_6348()) 163 if (BCMCPU_IS_6348())
135 return; 164 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
136 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); 165 else if (BCMCPU_IS_6368())
166 bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
137} 167}
138 168
139static struct clk clk_usbh = { 169static struct clk clk_usbh = {
@@ -162,6 +192,36 @@ static struct clk clk_spi = {
162}; 192};
163 193
164/* 194/*
195 * XTM clock
196 */
197static void xtm_set(struct clk *clk, int enable)
198{
199 if (!BCMCPU_IS_6368())
200 return;
201
202 bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
203 CKCTL_6368_SWPKT_SAR_EN, enable);
204
205 if (enable) {
206 u32 val;
207
208 /* reset sar core afer clock change */
209 val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
210 val &= ~SOFTRESET_6368_SAR_MASK;
211 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
212 mdelay(1);
213 val |= SOFTRESET_6368_SAR_MASK;
214 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
215 mdelay(1);
216 }
217}
218
219
220static struct clk clk_xtm = {
221 .set = xtm_set,
222};
223
224/*
165 * Internal peripheral clock 225 * Internal peripheral clock
166 */ 226 */
167static struct clk clk_periph = { 227static struct clk clk_periph = {
@@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id)
204 return &clk_enet0; 264 return &clk_enet0;
205 if (!strcmp(id, "enet1")) 265 if (!strcmp(id, "enet1"))
206 return &clk_enet1; 266 return &clk_enet1;
267 if (!strcmp(id, "enetsw"))
268 return &clk_enetsw;
207 if (!strcmp(id, "ephy")) 269 if (!strcmp(id, "ephy"))
208 return &clk_ephy; 270 return &clk_ephy;
209 if (!strcmp(id, "usbh")) 271 if (!strcmp(id, "usbh"))
210 return &clk_usbh; 272 return &clk_usbh;
211 if (!strcmp(id, "spi")) 273 if (!strcmp(id, "spi"))
212 return &clk_spi; 274 return &clk_spi;
275 if (!strcmp(id, "xtm"))
276 return &clk_xtm;
213 if (!strcmp(id, "periph")) 277 if (!strcmp(id, "periph"))
214 return &clk_periph; 278 return &clk_periph;
215 if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) 279 if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 7c7e4d4486ce..8f0d6c7725ea 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,166 +29,47 @@ static u16 bcm63xx_cpu_rev;
29static unsigned int bcm63xx_cpu_freq; 29static unsigned int bcm63xx_cpu_freq;
30static unsigned int bcm63xx_memory_size; 30static unsigned int bcm63xx_memory_size;
31 31
32/* 32static const unsigned long bcm6338_regs_base[] = {
33 * 6338 register sets and irqs 33 __GEN_CPU_REGS_TABLE(6338)
34 */
35static const unsigned long bcm96338_regs_base[] = {
36 [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE,
37 [RSET_PERF] = BCM_6338_PERF_BASE,
38 [RSET_TIMER] = BCM_6338_TIMER_BASE,
39 [RSET_WDT] = BCM_6338_WDT_BASE,
40 [RSET_UART0] = BCM_6338_UART0_BASE,
41 [RSET_UART1] = BCM_6338_UART1_BASE,
42 [RSET_GPIO] = BCM_6338_GPIO_BASE,
43 [RSET_SPI] = BCM_6338_SPI_BASE,
44 [RSET_OHCI0] = BCM_6338_OHCI0_BASE,
45 [RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE,
46 [RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE,
47 [RSET_UDC0] = BCM_6338_UDC0_BASE,
48 [RSET_MPI] = BCM_6338_MPI_BASE,
49 [RSET_PCMCIA] = BCM_6338_PCMCIA_BASE,
50 [RSET_SDRAM] = BCM_6338_SDRAM_BASE,
51 [RSET_DSL] = BCM_6338_DSL_BASE,
52 [RSET_ENET0] = BCM_6338_ENET0_BASE,
53 [RSET_ENET1] = BCM_6338_ENET1_BASE,
54 [RSET_ENETDMA] = BCM_6338_ENETDMA_BASE,
55 [RSET_MEMC] = BCM_6338_MEMC_BASE,
56 [RSET_DDR] = BCM_6338_DDR_BASE,
57}; 34};
58 35
59static const int bcm96338_irqs[] = { 36static const int bcm6338_irqs[] = {
60 [IRQ_TIMER] = BCM_6338_TIMER_IRQ, 37 __GEN_CPU_IRQ_TABLE(6338)
61 [IRQ_UART0] = BCM_6338_UART0_IRQ,
62 [IRQ_DSL] = BCM_6338_DSL_IRQ,
63 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
64 [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
65 [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
66 [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
67}; 38};
68 39
69/* 40static const unsigned long bcm6345_regs_base[] = {
70 * 6345 register sets and irqs 41 __GEN_CPU_REGS_TABLE(6345)
71 */
72static const unsigned long bcm96345_regs_base[] = {
73 [RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE,
74 [RSET_PERF] = BCM_6345_PERF_BASE,
75 [RSET_TIMER] = BCM_6345_TIMER_BASE,
76 [RSET_WDT] = BCM_6345_WDT_BASE,
77 [RSET_UART0] = BCM_6345_UART0_BASE,
78 [RSET_UART1] = BCM_6345_UART1_BASE,
79 [RSET_GPIO] = BCM_6345_GPIO_BASE,
80 [RSET_SPI] = BCM_6345_SPI_BASE,
81 [RSET_UDC0] = BCM_6345_UDC0_BASE,
82 [RSET_OHCI0] = BCM_6345_OHCI0_BASE,
83 [RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE,
84 [RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE,
85 [RSET_MPI] = BCM_6345_MPI_BASE,
86 [RSET_PCMCIA] = BCM_6345_PCMCIA_BASE,
87 [RSET_DSL] = BCM_6345_DSL_BASE,
88 [RSET_ENET0] = BCM_6345_ENET0_BASE,
89 [RSET_ENET1] = BCM_6345_ENET1_BASE,
90 [RSET_ENETDMA] = BCM_6345_ENETDMA_BASE,
91 [RSET_EHCI0] = BCM_6345_EHCI0_BASE,
92 [RSET_SDRAM] = BCM_6345_SDRAM_BASE,
93 [RSET_MEMC] = BCM_6345_MEMC_BASE,
94 [RSET_DDR] = BCM_6345_DDR_BASE,
95}; 42};
96 43
97static const int bcm96345_irqs[] = { 44static const int bcm6345_irqs[] = {
98 [IRQ_TIMER] = BCM_6345_TIMER_IRQ, 45 __GEN_CPU_IRQ_TABLE(6345)
99 [IRQ_UART0] = BCM_6345_UART0_IRQ,
100 [IRQ_DSL] = BCM_6345_DSL_IRQ,
101 [IRQ_ENET0] = BCM_6345_ENET0_IRQ,
102 [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
103 [IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ,
104 [IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ,
105}; 46};
106 47
107/* 48static const unsigned long bcm6348_regs_base[] = {
108 * 6348 register sets and irqs 49 __GEN_CPU_REGS_TABLE(6348)
109 */
110static const unsigned long bcm96348_regs_base[] = {
111 [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE,
112 [RSET_PERF] = BCM_6348_PERF_BASE,
113 [RSET_TIMER] = BCM_6348_TIMER_BASE,
114 [RSET_WDT] = BCM_6348_WDT_BASE,
115 [RSET_UART0] = BCM_6348_UART0_BASE,
116 [RSET_UART1] = BCM_6348_UART1_BASE,
117 [RSET_GPIO] = BCM_6348_GPIO_BASE,
118 [RSET_SPI] = BCM_6348_SPI_BASE,
119 [RSET_OHCI0] = BCM_6348_OHCI0_BASE,
120 [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
121 [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
122 [RSET_MPI] = BCM_6348_MPI_BASE,
123 [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
124 [RSET_SDRAM] = BCM_6348_SDRAM_BASE,
125 [RSET_DSL] = BCM_6348_DSL_BASE,
126 [RSET_ENET0] = BCM_6348_ENET0_BASE,
127 [RSET_ENET1] = BCM_6348_ENET1_BASE,
128 [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE,
129 [RSET_MEMC] = BCM_6348_MEMC_BASE,
130 [RSET_DDR] = BCM_6348_DDR_BASE,
131}; 50};
132 51
133static const int bcm96348_irqs[] = { 52static const int bcm6348_irqs[] = {
134 [IRQ_TIMER] = BCM_6348_TIMER_IRQ, 53 __GEN_CPU_IRQ_TABLE(6348)
135 [IRQ_UART0] = BCM_6348_UART0_IRQ, 54
136 [IRQ_DSL] = BCM_6348_DSL_IRQ,
137 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
138 [IRQ_ENET1] = BCM_6348_ENET1_IRQ,
139 [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
140 [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ,
141 [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ,
142 [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ,
143 [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ,
144 [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ,
145 [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ,
146 [IRQ_PCI] = BCM_6348_PCI_IRQ,
147}; 55};
148 56
149/* 57static const unsigned long bcm6358_regs_base[] = {
150 * 6358 register sets and irqs 58 __GEN_CPU_REGS_TABLE(6358)
151 */ 59};
152static const unsigned long bcm96358_regs_base[] = { 60
153 [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE, 61static const int bcm6358_irqs[] = {
154 [RSET_PERF] = BCM_6358_PERF_BASE, 62 __GEN_CPU_IRQ_TABLE(6358)
155 [RSET_TIMER] = BCM_6358_TIMER_BASE, 63
156 [RSET_WDT] = BCM_6358_WDT_BASE,
157 [RSET_UART0] = BCM_6358_UART0_BASE,
158 [RSET_UART1] = BCM_6358_UART1_BASE,
159 [RSET_GPIO] = BCM_6358_GPIO_BASE,
160 [RSET_SPI] = BCM_6358_SPI_BASE,
161 [RSET_OHCI0] = BCM_6358_OHCI0_BASE,
162 [RSET_EHCI0] = BCM_6358_EHCI0_BASE,
163 [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE,
164 [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE,
165 [RSET_MPI] = BCM_6358_MPI_BASE,
166 [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE,
167 [RSET_SDRAM] = BCM_6358_SDRAM_BASE,
168 [RSET_DSL] = BCM_6358_DSL_BASE,
169 [RSET_ENET0] = BCM_6358_ENET0_BASE,
170 [RSET_ENET1] = BCM_6358_ENET1_BASE,
171 [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE,
172 [RSET_MEMC] = BCM_6358_MEMC_BASE,
173 [RSET_DDR] = BCM_6358_DDR_BASE,
174}; 64};
175 65
176static const int bcm96358_irqs[] = { 66static const unsigned long bcm6368_regs_base[] = {
177 [IRQ_TIMER] = BCM_6358_TIMER_IRQ, 67 __GEN_CPU_REGS_TABLE(6368)
178 [IRQ_UART0] = BCM_6358_UART0_IRQ, 68};
179 [IRQ_UART1] = BCM_6358_UART1_IRQ, 69
180 [IRQ_DSL] = BCM_6358_DSL_IRQ, 70static const int bcm6368_irqs[] = {
181 [IRQ_ENET0] = BCM_6358_ENET0_IRQ, 71 __GEN_CPU_IRQ_TABLE(6368)
182 [IRQ_ENET1] = BCM_6358_ENET1_IRQ, 72
183 [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ,
184 [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ,
185 [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ,
186 [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ,
187 [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ,
188 [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ,
189 [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ,
190 [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ,
191 [IRQ_PCI] = BCM_6358_PCI_IRQ,
192}; 73};
193 74
194u16 __bcm63xx_get_cpu_id(void) 75u16 __bcm63xx_get_cpu_id(void)
@@ -217,20 +98,19 @@ unsigned int bcm63xx_get_memory_size(void)
217 98
218static unsigned int detect_cpu_clock(void) 99static unsigned int detect_cpu_clock(void)
219{ 100{
220 unsigned int tmp, n1 = 0, n2 = 0, m1 = 0; 101 switch (bcm63xx_get_cpu_id()) {
221 102 case BCM6338_CPU_ID:
222 /* BCM6338 has a fixed 240 Mhz frequency */ 103 /* BCM6338 has a fixed 240 Mhz frequency */
223 if (BCMCPU_IS_6338())
224 return 240000000; 104 return 240000000;
225 105
226 /* BCM6345 has a fixed 140Mhz frequency */ 106 case BCM6345_CPU_ID:
227 if (BCMCPU_IS_6345()) 107 /* BCM6345 has a fixed 140Mhz frequency */
228 return 140000000; 108 return 140000000;
229 109
230 /* 110 case BCM6348_CPU_ID:
231 * frequency depends on PLL configuration: 111 {
232 */ 112 unsigned int tmp, n1, n2, m1;
233 if (BCMCPU_IS_6348()) { 113
234 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */ 114 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
235 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); 115 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
236 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; 116 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
@@ -239,17 +119,47 @@ static unsigned int detect_cpu_clock(void)
239 n1 += 1; 119 n1 += 1;
240 n2 += 2; 120 n2 += 2;
241 m1 += 1; 121 m1 += 1;
122 return (16 * 1000000 * n1 * n2) / m1;
242 } 123 }
243 124
244 if (BCMCPU_IS_6358()) { 125 case BCM6358_CPU_ID:
126 {
127 unsigned int tmp, n1, n2, m1;
128
245 /* 16MHz * N1 * N2 / M1_CPU */ 129 /* 16MHz * N1 * N2 / M1_CPU */
246 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); 130 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
247 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT; 131 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
248 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT; 132 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
249 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT; 133 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
134 return (16 * 1000000 * n1 * n2) / m1;
250 } 135 }
251 136
252 return (16 * 1000000 * n1 * n2) / m1; 137 case BCM6368_CPU_ID:
138 {
139 unsigned int tmp, p1, p2, ndiv, m1;
140
141 /* (64MHz / P1) * P2 * NDIV / M1_CPU */
142 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
143
144 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
145 DMIPSPLLCFG_6368_P1_SHIFT;
146
147 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
148 DMIPSPLLCFG_6368_P2_SHIFT;
149
150 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
151 DMIPSPLLCFG_6368_NDIV_SHIFT;
152
153 tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
154 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
155 DMIPSPLLDIV_6368_MDIV_SHIFT;
156
157 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
158 }
159
160 default:
161 BUG();
162 }
253} 163}
254 164
255/* 165/*
@@ -260,8 +170,10 @@ static unsigned int detect_memory_size(void)
260 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; 170 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
261 u32 val; 171 u32 val;
262 172
263 if (BCMCPU_IS_6345()) 173 if (BCMCPU_IS_6345()) {
264 return (8 * 1024 * 1024); 174 val = bcm_sdram_readl(SDRAM_MBASE_REG);
175 return (val * 8 * 1024 * 1024);
176 }
265 177
266 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { 178 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
267 val = bcm_sdram_readl(SDRAM_CFG_REG); 179 val = bcm_sdram_readl(SDRAM_CFG_REG);
@@ -271,7 +183,7 @@ static unsigned int detect_memory_size(void)
271 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; 183 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
272 } 184 }
273 185
274 if (BCMCPU_IS_6358()) { 186 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
275 val = bcm_memc_readl(MEMC_CFG_REG); 187 val = bcm_memc_readl(MEMC_CFG_REG);
276 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; 188 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
277 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; 189 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -301,24 +213,33 @@ void __init bcm63xx_cpu_init(void)
301 case CPU_BMIPS3300: 213 case CPU_BMIPS3300:
302 if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) { 214 if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
303 expected_cpu_id = BCM6348_CPU_ID; 215 expected_cpu_id = BCM6348_CPU_ID;
304 bcm63xx_regs_base = bcm96348_regs_base; 216 bcm63xx_regs_base = bcm6348_regs_base;
305 bcm63xx_irqs = bcm96348_irqs; 217 bcm63xx_irqs = bcm6348_irqs;
306 } else { 218 } else {
307 __cpu_name[cpu] = "Broadcom BCM6338"; 219 __cpu_name[cpu] = "Broadcom BCM6338";
308 expected_cpu_id = BCM6338_CPU_ID; 220 expected_cpu_id = BCM6338_CPU_ID;
309 bcm63xx_regs_base = bcm96338_regs_base; 221 bcm63xx_regs_base = bcm6338_regs_base;
310 bcm63xx_irqs = bcm96338_irqs; 222 bcm63xx_irqs = bcm6338_irqs;
311 } 223 }
312 break; 224 break;
313 case CPU_BMIPS32: 225 case CPU_BMIPS32:
314 expected_cpu_id = BCM6345_CPU_ID; 226 expected_cpu_id = BCM6345_CPU_ID;
315 bcm63xx_regs_base = bcm96345_regs_base; 227 bcm63xx_regs_base = bcm6345_regs_base;
316 bcm63xx_irqs = bcm96345_irqs; 228 bcm63xx_irqs = bcm6345_irqs;
317 break; 229 break;
318 case CPU_BMIPS4350: 230 case CPU_BMIPS4350:
319 expected_cpu_id = BCM6358_CPU_ID; 231 switch (read_c0_prid() & 0xf0) {
320 bcm63xx_regs_base = bcm96358_regs_base; 232 case 0x10:
321 bcm63xx_irqs = bcm96358_irqs; 233 expected_cpu_id = BCM6358_CPU_ID;
234 bcm63xx_regs_base = bcm6358_regs_base;
235 bcm63xx_irqs = bcm6358_irqs;
236 break;
237 case 0x30:
238 expected_cpu_id = BCM6368_CPU_ID;
239 bcm63xx_regs_base = bcm6368_regs_base;
240 bcm63xx_irqs = bcm6368_irqs;
241 break;
242 }
322 break; 243 break;
323 } 244 }
324 245
diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
index c2963da0253e..d6e42c608325 100644
--- a/arch/mips/bcm63xx/dev-uart.c
+++ b/arch/mips/bcm63xx/dev-uart.c
@@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices)) 54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
55 return -ENODEV; 55 return -ENODEV;
56 56
57 if (id == 1 && !BCMCPU_IS_6358()) 57 if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
58 return -ENODEV; 58 return -ENODEV;
59 59
60 if (id == 0) { 60 if (id == 0) {
diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c
index f560fe7d38dd..a6c2135dbf38 100644
--- a/arch/mips/bcm63xx/gpio.c
+++ b/arch/mips/bcm63xx/gpio.c
@@ -4,7 +4,7 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> 7 * Copyright (C) 2008-2011 Florian Fainelli <florian@openwrt.org>
8 */ 8 */
9 9
10#include <linux/kernel.h> 10#include <linux/kernel.h>
@@ -18,6 +18,34 @@
18#include <bcm63xx_io.h> 18#include <bcm63xx_io.h>
19#include <bcm63xx_regs.h> 19#include <bcm63xx_regs.h>
20 20
21#ifndef BCMCPU_RUNTIME_DETECT
22#define gpio_out_low_reg GPIO_DATA_LO_REG
23#ifdef CONFIG_BCM63XX_CPU_6345
24#ifdef gpio_out_low_reg
25#undef gpio_out_low_reg
26#define gpio_out_low_reg GPIO_DATA_LO_REG_6345
27#endif /* gpio_out_low_reg */
28#endif /* CONFIG_BCM63XX_CPU_6345 */
29
30static inline void bcm63xx_gpio_out_low_reg_init(void)
31{
32}
33#else /* ! BCMCPU_RUNTIME_DETECT */
34static u32 gpio_out_low_reg;
35
36static void bcm63xx_gpio_out_low_reg_init(void)
37{
38 switch (bcm63xx_get_cpu_id()) {
39 case BCM6345_CPU_ID:
40 gpio_out_low_reg = GPIO_DATA_LO_REG_6345;
41 break;
42 default:
43 gpio_out_low_reg = GPIO_DATA_LO_REG;
44 break;
45 }
46}
47#endif /* ! BCMCPU_RUNTIME_DETECT */
48
21static DEFINE_SPINLOCK(bcm63xx_gpio_lock); 49static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
22static u32 gpio_out_low, gpio_out_high; 50static u32 gpio_out_low, gpio_out_high;
23 51
@@ -33,7 +61,7 @@ static void bcm63xx_gpio_set(struct gpio_chip *chip,
33 BUG(); 61 BUG();
34 62
35 if (gpio < 32) { 63 if (gpio < 32) {
36 reg = GPIO_DATA_LO_REG; 64 reg = gpio_out_low_reg;
37 mask = 1 << gpio; 65 mask = 1 << gpio;
38 v = &gpio_out_low; 66 v = &gpio_out_low;
39 } else { 67 } else {
@@ -60,7 +88,7 @@ static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
60 BUG(); 88 BUG();
61 89
62 if (gpio < 32) { 90 if (gpio < 32) {
63 reg = GPIO_DATA_LO_REG; 91 reg = gpio_out_low_reg;
64 mask = 1 << gpio; 92 mask = 1 << gpio;
65 } else { 93 } else {
66 reg = GPIO_DATA_HI_REG; 94 reg = GPIO_DATA_HI_REG;
@@ -125,8 +153,11 @@ static struct gpio_chip bcm63xx_gpio_chip = {
125 153
126int __init bcm63xx_gpio_init(void) 154int __init bcm63xx_gpio_init(void)
127{ 155{
128 gpio_out_low = bcm_gpio_readl(GPIO_DATA_LO_REG); 156 bcm63xx_gpio_out_low_reg_init();
129 gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG); 157
158 gpio_out_low = bcm_gpio_readl(gpio_out_low_reg);
159 if (!BCMCPU_IS_6345())
160 gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
130 bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count(); 161 bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
131 pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio); 162 pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
132 163
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 162e11b4ed75..9a216a451d92 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -19,19 +19,187 @@
19#include <bcm63xx_io.h> 19#include <bcm63xx_io.h>
20#include <bcm63xx_irq.h> 20#include <bcm63xx_irq.h>
21 21
22static void __dispatch_internal(void) __maybe_unused;
23static void __dispatch_internal_64(void) __maybe_unused;
24static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
25static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
26static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
27static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
28
29#ifndef BCMCPU_RUNTIME_DETECT
30#ifdef CONFIG_BCM63XX_CPU_6338
31#define irq_stat_reg PERF_IRQSTAT_6338_REG
32#define irq_mask_reg PERF_IRQMASK_6338_REG
33#define irq_bits 32
34#define is_ext_irq_cascaded 0
35#define ext_irq_start 0
36#define ext_irq_end 0
37#define ext_irq_count 4
38#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6338
39#define ext_irq_cfg_reg2 0
40#endif
41#ifdef CONFIG_BCM63XX_CPU_6345
42#define irq_stat_reg PERF_IRQSTAT_6345_REG
43#define irq_mask_reg PERF_IRQMASK_6345_REG
44#define irq_bits 32
45#define is_ext_irq_cascaded 0
46#define ext_irq_start 0
47#define ext_irq_end 0
48#define ext_irq_count 0
49#define ext_irq_cfg_reg1 0
50#define ext_irq_cfg_reg2 0
51#endif
52#ifdef CONFIG_BCM63XX_CPU_6348
53#define irq_stat_reg PERF_IRQSTAT_6348_REG
54#define irq_mask_reg PERF_IRQMASK_6348_REG
55#define irq_bits 32
56#define is_ext_irq_cascaded 0
57#define ext_irq_start 0
58#define ext_irq_end 0
59#define ext_irq_count 4
60#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6348
61#define ext_irq_cfg_reg2 0
62#endif
63#ifdef CONFIG_BCM63XX_CPU_6358
64#define irq_stat_reg PERF_IRQSTAT_6358_REG
65#define irq_mask_reg PERF_IRQMASK_6358_REG
66#define irq_bits 32
67#define is_ext_irq_cascaded 1
68#define ext_irq_start (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
69#define ext_irq_end (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
70#define ext_irq_count 4
71#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
72#define ext_irq_cfg_reg2 0
73#endif
74#ifdef CONFIG_BCM63XX_CPU_6368
75#define irq_stat_reg PERF_IRQSTAT_6368_REG
76#define irq_mask_reg PERF_IRQMASK_6368_REG
77#define irq_bits 64
78#define is_ext_irq_cascaded 1
79#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
80#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
81#define ext_irq_count 6
82#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368
83#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368
84#endif
85
86#if irq_bits == 32
87#define dispatch_internal __dispatch_internal
88#define internal_irq_mask __internal_irq_mask_32
89#define internal_irq_unmask __internal_irq_unmask_32
90#else
91#define dispatch_internal __dispatch_internal_64
92#define internal_irq_mask __internal_irq_mask_64
93#define internal_irq_unmask __internal_irq_unmask_64
94#endif
95
96#define irq_stat_addr (bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
97#define irq_mask_addr (bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
98
99static inline void bcm63xx_init_irq(void)
100{
101}
102#else /* ! BCMCPU_RUNTIME_DETECT */
103
104static u32 irq_stat_addr, irq_mask_addr;
105static void (*dispatch_internal)(void);
106static int is_ext_irq_cascaded;
107static unsigned int ext_irq_count;
108static unsigned int ext_irq_start, ext_irq_end;
109static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
110static void (*internal_irq_mask)(unsigned int irq);
111static void (*internal_irq_unmask)(unsigned int irq);
112
113static void bcm63xx_init_irq(void)
114{
115 int irq_bits;
116
117 irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
118 irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
119
120 switch (bcm63xx_get_cpu_id()) {
121 case BCM6338_CPU_ID:
122 irq_stat_addr += PERF_IRQSTAT_6338_REG;
123 irq_mask_addr += PERF_IRQMASK_6338_REG;
124 irq_bits = 32;
125 break;
126 case BCM6345_CPU_ID:
127 irq_stat_addr += PERF_IRQSTAT_6345_REG;
128 irq_mask_addr += PERF_IRQMASK_6345_REG;
129 irq_bits = 32;
130 break;
131 case BCM6348_CPU_ID:
132 irq_stat_addr += PERF_IRQSTAT_6348_REG;
133 irq_mask_addr += PERF_IRQMASK_6348_REG;
134 irq_bits = 32;
135 ext_irq_count = 4;
136 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
137 break;
138 case BCM6358_CPU_ID:
139 irq_stat_addr += PERF_IRQSTAT_6358_REG;
140 irq_mask_addr += PERF_IRQMASK_6358_REG;
141 irq_bits = 32;
142 ext_irq_count = 4;
143 is_ext_irq_cascaded = 1;
144 ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
145 ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
146 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
147 break;
148 case BCM6368_CPU_ID:
149 irq_stat_addr += PERF_IRQSTAT_6368_REG;
150 irq_mask_addr += PERF_IRQMASK_6368_REG;
151 irq_bits = 64;
152 ext_irq_count = 6;
153 is_ext_irq_cascaded = 1;
154 ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
155 ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
156 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
157 ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
158 break;
159 default:
160 BUG();
161 }
162
163 if (irq_bits == 32) {
164 dispatch_internal = __dispatch_internal;
165 internal_irq_mask = __internal_irq_mask_32;
166 internal_irq_unmask = __internal_irq_unmask_32;
167 } else {
168 dispatch_internal = __dispatch_internal_64;
169 internal_irq_mask = __internal_irq_mask_64;
170 internal_irq_unmask = __internal_irq_unmask_64;
171 }
172}
173#endif /* ! BCMCPU_RUNTIME_DETECT */
174
175static inline u32 get_ext_irq_perf_reg(int irq)
176{
177 if (irq < 4)
178 return ext_irq_cfg_reg1;
179 return ext_irq_cfg_reg2;
180}
181
182static inline void handle_internal(int intbit)
183{
184 if (is_ext_irq_cascaded &&
185 intbit >= ext_irq_start && intbit <= ext_irq_end)
186 do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
187 else
188 do_IRQ(intbit + IRQ_INTERNAL_BASE);
189}
190
22/* 191/*
23 * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not 192 * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
24 * prioritize any interrupt relatively to another. the static counter 193 * prioritize any interrupt relatively to another. the static counter
25 * will resume the loop where it ended the last time we left this 194 * will resume the loop where it ended the last time we left this
26 * function. 195 * function.
27 */ 196 */
28static void bcm63xx_irq_dispatch_internal(void) 197static void __dispatch_internal(void)
29{ 198{
30 u32 pending; 199 u32 pending;
31 static int i; 200 static int i;
32 201
33 pending = bcm_perf_readl(PERF_IRQMASK_REG) & 202 pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);
34 bcm_perf_readl(PERF_IRQSTAT_REG);
35 203
36 if (!pending) 204 if (!pending)
37 return ; 205 return ;
@@ -41,7 +209,28 @@ static void bcm63xx_irq_dispatch_internal(void)
41 209
42 i = (i + 1) & 0x1f; 210 i = (i + 1) & 0x1f;
43 if (pending & (1 << to_call)) { 211 if (pending & (1 << to_call)) {
44 do_IRQ(to_call + IRQ_INTERNAL_BASE); 212 handle_internal(to_call);
213 break;
214 }
215 }
216}
217
218static void __dispatch_internal_64(void)
219{
220 u64 pending;
221 static int i;
222
223 pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr);
224
225 if (!pending)
226 return ;
227
228 while (1) {
229 int to_call = i;
230
231 i = (i + 1) & 0x3f;
232 if (pending & (1ull << to_call)) {
233 handle_internal(to_call);
45 break; 234 break;
46 } 235 }
47 } 236 }
@@ -60,15 +249,17 @@ asmlinkage void plat_irq_dispatch(void)
60 if (cause & CAUSEF_IP7) 249 if (cause & CAUSEF_IP7)
61 do_IRQ(7); 250 do_IRQ(7);
62 if (cause & CAUSEF_IP2) 251 if (cause & CAUSEF_IP2)
63 bcm63xx_irq_dispatch_internal(); 252 dispatch_internal();
64 if (cause & CAUSEF_IP3) 253 if (!is_ext_irq_cascaded) {
65 do_IRQ(IRQ_EXT_0); 254 if (cause & CAUSEF_IP3)
66 if (cause & CAUSEF_IP4) 255 do_IRQ(IRQ_EXT_0);
67 do_IRQ(IRQ_EXT_1); 256 if (cause & CAUSEF_IP4)
68 if (cause & CAUSEF_IP5) 257 do_IRQ(IRQ_EXT_1);
69 do_IRQ(IRQ_EXT_2); 258 if (cause & CAUSEF_IP5)
70 if (cause & CAUSEF_IP6) 259 do_IRQ(IRQ_EXT_2);
71 do_IRQ(IRQ_EXT_3); 260 if (cause & CAUSEF_IP6)
261 do_IRQ(IRQ_EXT_3);
262 }
72 } while (1); 263 } while (1);
73} 264}
74 265
@@ -76,24 +267,50 @@ asmlinkage void plat_irq_dispatch(void)
76 * internal IRQs operations: only mask/unmask on PERF irq mask 267 * internal IRQs operations: only mask/unmask on PERF irq mask
77 * register. 268 * register.
78 */ 269 */
79static inline void bcm63xx_internal_irq_mask(struct irq_data *d) 270static void __internal_irq_mask_32(unsigned int irq)
80{ 271{
81 unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
82 u32 mask; 272 u32 mask;
83 273
84 mask = bcm_perf_readl(PERF_IRQMASK_REG); 274 mask = bcm_readl(irq_mask_addr);
85 mask &= ~(1 << irq); 275 mask &= ~(1 << irq);
86 bcm_perf_writel(mask, PERF_IRQMASK_REG); 276 bcm_writel(mask, irq_mask_addr);
87} 277}
88 278
89static void bcm63xx_internal_irq_unmask(struct irq_data *d) 279static void __internal_irq_mask_64(unsigned int irq)
280{
281 u64 mask;
282
283 mask = bcm_readq(irq_mask_addr);
284 mask &= ~(1ull << irq);
285 bcm_writeq(mask, irq_mask_addr);
286}
287
288static void __internal_irq_unmask_32(unsigned int irq)
90{ 289{
91 unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
92 u32 mask; 290 u32 mask;
93 291
94 mask = bcm_perf_readl(PERF_IRQMASK_REG); 292 mask = bcm_readl(irq_mask_addr);
95 mask |= (1 << irq); 293 mask |= (1 << irq);
96 bcm_perf_writel(mask, PERF_IRQMASK_REG); 294 bcm_writel(mask, irq_mask_addr);
295}
296
297static void __internal_irq_unmask_64(unsigned int irq)
298{
299 u64 mask;
300
301 mask = bcm_readq(irq_mask_addr);
302 mask |= (1ull << irq);
303 bcm_writeq(mask, irq_mask_addr);
304}
305
306static void bcm63xx_internal_irq_mask(struct irq_data *d)
307{
308 internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
309}
310
311static void bcm63xx_internal_irq_unmask(struct irq_data *d)
312{
313 internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
97} 314}
98 315
99/* 316/*
@@ -102,94 +319,131 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
102 */ 319 */
103static void bcm63xx_external_irq_mask(struct irq_data *d) 320static void bcm63xx_external_irq_mask(struct irq_data *d)
104{ 321{
105 unsigned int irq = d->irq - IRQ_EXT_BASE; 322 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
106 u32 reg; 323 u32 reg, regaddr;
107 324
108 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 325 regaddr = get_ext_irq_perf_reg(irq);
109 reg &= ~EXTIRQ_CFG_MASK(irq); 326 reg = bcm_perf_readl(regaddr);
110 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 327
328 if (BCMCPU_IS_6348())
329 reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
330 else
331 reg &= ~EXTIRQ_CFG_MASK(irq % 4);
332
333 bcm_perf_writel(reg, regaddr);
334 if (is_ext_irq_cascaded)
335 internal_irq_mask(irq + ext_irq_start);
111} 336}
112 337
113static void bcm63xx_external_irq_unmask(struct irq_data *d) 338static void bcm63xx_external_irq_unmask(struct irq_data *d)
114{ 339{
115 unsigned int irq = d->irq - IRQ_EXT_BASE; 340 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
116 u32 reg; 341 u32 reg, regaddr;
117 342
118 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 343 regaddr = get_ext_irq_perf_reg(irq);
119 reg |= EXTIRQ_CFG_MASK(irq); 344 reg = bcm_perf_readl(regaddr);
120 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 345
346 if (BCMCPU_IS_6348())
347 reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
348 else
349 reg |= EXTIRQ_CFG_MASK(irq % 4);
350
351 bcm_perf_writel(reg, regaddr);
352
353 if (is_ext_irq_cascaded)
354 internal_irq_unmask(irq + ext_irq_start);
121} 355}
122 356
123static void bcm63xx_external_irq_clear(struct irq_data *d) 357static void bcm63xx_external_irq_clear(struct irq_data *d)
124{ 358{
125 unsigned int irq = d->irq - IRQ_EXT_BASE; 359 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
126 u32 reg; 360 u32 reg, regaddr;
127 361
128 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 362 regaddr = get_ext_irq_perf_reg(irq);
129 reg |= EXTIRQ_CFG_CLEAR(irq); 363 reg = bcm_perf_readl(regaddr);
130 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
131}
132 364
133static unsigned int bcm63xx_external_irq_startup(struct irq_data *d) 365 if (BCMCPU_IS_6348())
134{ 366 reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
135 set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE)); 367 else
136 irq_enable_hazard(); 368 reg |= EXTIRQ_CFG_CLEAR(irq % 4);
137 bcm63xx_external_irq_unmask(d);
138 return 0;
139}
140 369
141static void bcm63xx_external_irq_shutdown(struct irq_data *d) 370 bcm_perf_writel(reg, regaddr);
142{
143 bcm63xx_external_irq_mask(d);
144 clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
145 irq_disable_hazard();
146} 371}
147 372
148static int bcm63xx_external_irq_set_type(struct irq_data *d, 373static int bcm63xx_external_irq_set_type(struct irq_data *d,
149 unsigned int flow_type) 374 unsigned int flow_type)
150{ 375{
151 unsigned int irq = d->irq - IRQ_EXT_BASE; 376 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
152 u32 reg; 377 u32 reg, regaddr;
378 int levelsense, sense, bothedge;
153 379
154 flow_type &= IRQ_TYPE_SENSE_MASK; 380 flow_type &= IRQ_TYPE_SENSE_MASK;
155 381
156 if (flow_type == IRQ_TYPE_NONE) 382 if (flow_type == IRQ_TYPE_NONE)
157 flow_type = IRQ_TYPE_LEVEL_LOW; 383 flow_type = IRQ_TYPE_LEVEL_LOW;
158 384
159 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 385 levelsense = sense = bothedge = 0;
160 switch (flow_type) { 386 switch (flow_type) {
161 case IRQ_TYPE_EDGE_BOTH: 387 case IRQ_TYPE_EDGE_BOTH:
162 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); 388 bothedge = 1;
163 reg |= EXTIRQ_CFG_BOTHEDGE(irq);
164 break; 389 break;
165 390
166 case IRQ_TYPE_EDGE_RISING: 391 case IRQ_TYPE_EDGE_RISING:
167 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); 392 sense = 1;
168 reg |= EXTIRQ_CFG_SENSE(irq);
169 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
170 break; 393 break;
171 394
172 case IRQ_TYPE_EDGE_FALLING: 395 case IRQ_TYPE_EDGE_FALLING:
173 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
174 reg &= ~EXTIRQ_CFG_SENSE(irq);
175 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
176 break; 396 break;
177 397
178 case IRQ_TYPE_LEVEL_HIGH: 398 case IRQ_TYPE_LEVEL_HIGH:
179 reg |= EXTIRQ_CFG_LEVELSENSE(irq); 399 levelsense = 1;
180 reg |= EXTIRQ_CFG_SENSE(irq); 400 sense = 1;
181 break; 401 break;
182 402
183 case IRQ_TYPE_LEVEL_LOW: 403 case IRQ_TYPE_LEVEL_LOW:
184 reg |= EXTIRQ_CFG_LEVELSENSE(irq); 404 levelsense = 1;
185 reg &= ~EXTIRQ_CFG_SENSE(irq);
186 break; 405 break;
187 406
188 default: 407 default:
189 printk(KERN_ERR "bogus flow type combination given !\n"); 408 printk(KERN_ERR "bogus flow type combination given !\n");
190 return -EINVAL; 409 return -EINVAL;
191 } 410 }
192 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 411
412 regaddr = get_ext_irq_perf_reg(irq);
413 reg = bcm_perf_readl(regaddr);
414 irq %= 4;
415
416 if (BCMCPU_IS_6348()) {
417 if (levelsense)
418 reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
419 else
420 reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
421 if (sense)
422 reg |= EXTIRQ_CFG_SENSE_6348(irq);
423 else
424 reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
425 if (bothedge)
426 reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
427 else
428 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
429 }
430
431 if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
432 if (levelsense)
433 reg |= EXTIRQ_CFG_LEVELSENSE(irq);
434 else
435 reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
436 if (sense)
437 reg |= EXTIRQ_CFG_SENSE(irq);
438 else
439 reg &= ~EXTIRQ_CFG_SENSE(irq);
440 if (bothedge)
441 reg |= EXTIRQ_CFG_BOTHEDGE(irq);
442 else
443 reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
444 }
445
446 bcm_perf_writel(reg, regaddr);
193 447
194 irqd_set_trigger_type(d, flow_type); 448 irqd_set_trigger_type(d, flow_type);
195 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 449 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@@ -208,9 +462,6 @@ static struct irq_chip bcm63xx_internal_irq_chip = {
208 462
209static struct irq_chip bcm63xx_external_irq_chip = { 463static struct irq_chip bcm63xx_external_irq_chip = {
210 .name = "bcm63xx_epic", 464 .name = "bcm63xx_epic",
211 .irq_startup = bcm63xx_external_irq_startup,
212 .irq_shutdown = bcm63xx_external_irq_shutdown,
213
214 .irq_ack = bcm63xx_external_irq_clear, 465 .irq_ack = bcm63xx_external_irq_clear,
215 466
216 .irq_mask = bcm63xx_external_irq_mask, 467 .irq_mask = bcm63xx_external_irq_mask,
@@ -225,18 +476,30 @@ static struct irqaction cpu_ip2_cascade_action = {
225 .flags = IRQF_NO_THREAD, 476 .flags = IRQF_NO_THREAD,
226}; 477};
227 478
479static struct irqaction cpu_ext_cascade_action = {
480 .handler = no_action,
481 .name = "cascade_extirq",
482 .flags = IRQF_NO_THREAD,
483};
484
228void __init arch_init_irq(void) 485void __init arch_init_irq(void)
229{ 486{
230 int i; 487 int i;
231 488
489 bcm63xx_init_irq();
232 mips_cpu_irq_init(); 490 mips_cpu_irq_init();
233 for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) 491 for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
234 irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip, 492 irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
235 handle_level_irq); 493 handle_level_irq);
236 494
237 for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i) 495 for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
238 irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip, 496 irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
239 handle_edge_irq); 497 handle_edge_irq);
240 498
241 setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action); 499 if (!is_ext_irq_cascaded) {
500 for (i = 3; i < 3 + ext_irq_count; ++i)
501 setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
502 }
503
504 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
242} 505}
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index be252efa0757..99d7f405cbeb 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -32,9 +32,12 @@ void __init prom_init(void)
32 mask = CKCTL_6345_ALL_SAFE_EN; 32 mask = CKCTL_6345_ALL_SAFE_EN;
33 else if (BCMCPU_IS_6348()) 33 else if (BCMCPU_IS_6348())
34 mask = CKCTL_6348_ALL_SAFE_EN; 34 mask = CKCTL_6348_ALL_SAFE_EN;
35 else 35 else if (BCMCPU_IS_6358())
36 /* BCMCPU_IS_6358() */
37 mask = CKCTL_6358_ALL_SAFE_EN; 36 mask = CKCTL_6358_ALL_SAFE_EN;
37 else if (BCMCPU_IS_6368())
38 mask = CKCTL_6368_ALL_SAFE_EN;
39 else
40 mask = 0;
38 41
39 reg = bcm_perf_readl(PERF_CKCTL_REG); 42 reg = bcm_perf_readl(PERF_CKCTL_REG);
40 reg &= ~mask; 43 reg &= ~mask;
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index d0056598fbfc..d209f85d87bb 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -63,13 +63,33 @@ static void bcm6348_a1_reboot(void)
63 63
64void bcm63xx_machine_reboot(void) 64void bcm63xx_machine_reboot(void)
65{ 65{
66 u32 reg; 66 u32 reg, perf_regs[2] = { 0, 0 };
67 unsigned int i;
67 68
68 /* mask and clear all external irq */ 69 /* mask and clear all external irq */
69 reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); 70 switch (bcm63xx_get_cpu_id()) {
70 reg &= ~EXTIRQ_CFG_MASK_ALL; 71 case BCM6338_CPU_ID:
71 reg |= EXTIRQ_CFG_CLEAR_ALL; 72 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
72 bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); 73 break;
74 case BCM6348_CPU_ID:
75 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
76 break;
77 case BCM6358_CPU_ID:
78 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
79 break;
80 }
81
82 for (i = 0; i < 2; i++) {
83 reg = bcm_perf_readl(perf_regs[i]);
84 if (BCMCPU_IS_6348()) {
85 reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
86 reg |= EXTIRQ_CFG_CLEAR_ALL_6348;
87 } else {
88 reg &= ~EXTIRQ_CFG_MASK_ALL;
89 reg |= EXTIRQ_CFG_CLEAR_ALL;
90 }
91 bcm_perf_writel(reg, perf_regs[i]);
92 }
73 93
74 if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1)) 94 if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
75 bcm6348_a1_reboot(); 95 bcm6348_a1_reboot();
@@ -124,4 +144,4 @@ int __init bcm63xx_register_devices(void)
124 return board_register_devices(); 144 return board_register_devices();
125} 145}
126 146
127arch_initcall(bcm63xx_register_devices); 147device_initcall(bcm63xx_register_devices);
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index cad555ebeca3..f9e275a50d98 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -86,10 +86,6 @@ config ARCH_SPARSEMEM_ENABLE
86 def_bool y 86 def_bool y
87 select SPARSEMEM_STATIC 87 select SPARSEMEM_STATIC
88 88
89config CAVIUM_OCTEON_HELPER
90 def_bool y
91 depends on OCTEON_ETHERNET || PCI
92
93config IOMMU_HELPER 89config IOMMU_HELPER
94 bool 90 bool
95 91
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index ea4febaa4bb1..b6bb92c16a47 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -61,6 +61,16 @@ static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
61 return daddr; 61 return daddr;
62} 62}
63 63
64static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
65{
66 return octeon_hole_phys_to_dma(paddr);
67}
68
69static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
70{
71 return octeon_hole_dma_to_phys(daddr);
72}
73
64static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr) 74static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
65{ 75{
66 if (paddr >= 0x410000000ull && paddr < 0x420000000ull) 76 if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
@@ -262,11 +272,11 @@ void __init plat_swiotlb_setup(void)
262 272
263 for (i = 0 ; i < boot_mem_map.nr_map; i++) { 273 for (i = 0 ; i < boot_mem_map.nr_map; i++) {
264 struct boot_mem_map_entry *e = &boot_mem_map.map[i]; 274 struct boot_mem_map_entry *e = &boot_mem_map.map[i];
265 if (e->type != BOOT_MEM_RAM) 275 if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM)
266 continue; 276 continue;
267 277
268 /* These addresses map low for PCI. */ 278 /* These addresses map low for PCI. */
269 if (e->addr > 0x410000000ull) 279 if (e->addr > 0x410000000ull && !OCTEON_IS_MODEL(OCTEON_CN6XXX))
270 continue; 280 continue;
271 281
272 addr_size += e->size; 282 addr_size += e->size;
@@ -296,6 +306,11 @@ void __init plat_swiotlb_setup(void)
296 swiotlbsize = 64 * (1<<20); 306 swiotlbsize = 64 * (1<<20);
297 } 307 }
298#endif 308#endif
309#ifdef CONFIG_USB_OCTEON_OHCI
310 /* OCTEON II ohci is only 32-bit. */
311 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && max_addr >= 0x100000000ul)
312 swiotlbsize = 64 * (1<<20);
313#endif
299 swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT; 314 swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
300 swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE); 315 swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
301 swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT; 316 swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
@@ -330,6 +345,10 @@ struct dma_map_ops *octeon_pci_dma_map_ops;
330void __init octeon_pci_dma_init(void) 345void __init octeon_pci_dma_init(void)
331{ 346{
332 switch (octeon_dma_bar_type) { 347 switch (octeon_dma_bar_type) {
348 case OCTEON_DMA_BAR_TYPE_PCIE2:
349 _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma;
350 _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys;
351 break;
333 case OCTEON_DMA_BAR_TYPE_PCIE: 352 case OCTEON_DMA_BAR_TYPE_PCIE:
334 _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma; 353 _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
335 _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys; 354 _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
index 7f41c5be2190..b6d6e841a984 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -10,5 +10,10 @@
10# 10#
11 11
12obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o 12obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
13obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
14 cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \
15 cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \
16 cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
17 cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
13 18
14obj-$(CONFIG_CAVIUM_OCTEON_HELPER) += cvmx-helper-errata.o cvmx-helper-jtag.o 19obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o
diff --git a/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
new file mode 100644
index 000000000000..132bccc66a93
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
@@ -0,0 +1,306 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Support functions for managing command queues used for
30 * various hardware blocks.
31 */
32
33#include <linux/kernel.h>
34
35#include <asm/octeon/octeon.h>
36
37#include <asm/octeon/cvmx-config.h>
38#include <asm/octeon/cvmx-fpa.h>
39#include <asm/octeon/cvmx-cmd-queue.h>
40
41#include <asm/octeon/cvmx-npei-defs.h>
42#include <asm/octeon/cvmx-pexp-defs.h>
43#include <asm/octeon/cvmx-pko-defs.h>
44
45/**
46 * This application uses this pointer to access the global queue
47 * state. It points to a bootmem named block.
48 */
49__cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr;
50
51/**
52 * Initialize the Global queue state pointer.
53 *
54 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
55 */
56static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void)
57{
58 char *alloc_name = "cvmx_cmd_queues";
59#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32
60 extern uint64_t octeon_reserve32_memory;
61#endif
62
63 if (likely(__cvmx_cmd_queue_state_ptr))
64 return CVMX_CMD_QUEUE_SUCCESS;
65
66#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32
67 if (octeon_reserve32_memory)
68 __cvmx_cmd_queue_state_ptr =
69 cvmx_bootmem_alloc_named_range(sizeof(*__cvmx_cmd_queue_state_ptr),
70 octeon_reserve32_memory,
71 octeon_reserve32_memory +
72 (CONFIG_CAVIUM_RESERVE32 <<
73 20) - 1, 128, alloc_name);
74 else
75#endif
76 __cvmx_cmd_queue_state_ptr =
77 cvmx_bootmem_alloc_named(sizeof(*__cvmx_cmd_queue_state_ptr),
78 128,
79 alloc_name);
80 if (__cvmx_cmd_queue_state_ptr)
81 memset(__cvmx_cmd_queue_state_ptr, 0,
82 sizeof(*__cvmx_cmd_queue_state_ptr));
83 else {
84 struct cvmx_bootmem_named_block_desc *block_desc =
85 cvmx_bootmem_find_named_block(alloc_name);
86 if (block_desc)
87 __cvmx_cmd_queue_state_ptr =
88 cvmx_phys_to_ptr(block_desc->base_addr);
89 else {
90 cvmx_dprintf
91 ("ERROR: cvmx_cmd_queue_initialize: Unable to get named block %s.\n",
92 alloc_name);
93 return CVMX_CMD_QUEUE_NO_MEMORY;
94 }
95 }
96 return CVMX_CMD_QUEUE_SUCCESS;
97}
98
99/**
100 * Initialize a command queue for use. The initial FPA buffer is
101 * allocated and the hardware unit is configured to point to the
102 * new command queue.
103 *
104 * @queue_id: Hardware command queue to initialize.
105 * @max_depth: Maximum outstanding commands that can be queued.
106 * @fpa_pool: FPA pool the command queues should come from.
107 * @pool_size: Size of each buffer in the FPA pool (bytes)
108 *
109 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
110 */
111cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
112 int max_depth, int fpa_pool,
113 int pool_size)
114{
115 __cvmx_cmd_queue_state_t *qstate;
116 cvmx_cmd_queue_result_t result = __cvmx_cmd_queue_init_state_ptr();
117 if (result != CVMX_CMD_QUEUE_SUCCESS)
118 return result;
119
120 qstate = __cvmx_cmd_queue_get_state(queue_id);
121 if (qstate == NULL)
122 return CVMX_CMD_QUEUE_INVALID_PARAM;
123
124 /*
125 * We artificially limit max_depth to 1<<20 words. It is an
126 * arbitrary limit.
127 */
128 if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH) {
129 if ((max_depth < 0) || (max_depth > 1 << 20))
130 return CVMX_CMD_QUEUE_INVALID_PARAM;
131 } else if (max_depth != 0)
132 return CVMX_CMD_QUEUE_INVALID_PARAM;
133
134 if ((fpa_pool < 0) || (fpa_pool > 7))
135 return CVMX_CMD_QUEUE_INVALID_PARAM;
136 if ((pool_size < 128) || (pool_size > 65536))
137 return CVMX_CMD_QUEUE_INVALID_PARAM;
138
139 /* See if someone else has already initialized the queue */
140 if (qstate->base_ptr_div128) {
141 if (max_depth != (int)qstate->max_depth) {
142 cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
143 "Queue already initialized with different "
144 "max_depth (%d).\n",
145 (int)qstate->max_depth);
146 return CVMX_CMD_QUEUE_INVALID_PARAM;
147 }
148 if (fpa_pool != qstate->fpa_pool) {
149 cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
150 "Queue already initialized with different "
151 "FPA pool (%u).\n",
152 qstate->fpa_pool);
153 return CVMX_CMD_QUEUE_INVALID_PARAM;
154 }
155 if ((pool_size >> 3) - 1 != qstate->pool_size_m1) {
156 cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
157 "Queue already initialized with different "
158 "FPA pool size (%u).\n",
159 (qstate->pool_size_m1 + 1) << 3);
160 return CVMX_CMD_QUEUE_INVALID_PARAM;
161 }
162 CVMX_SYNCWS;
163 return CVMX_CMD_QUEUE_ALREADY_SETUP;
164 } else {
165 union cvmx_fpa_ctl_status status;
166 void *buffer;
167
168 status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
169 if (!status.s.enb) {
170 cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
171 "FPA is not enabled.\n");
172 return CVMX_CMD_QUEUE_NO_MEMORY;
173 }
174 buffer = cvmx_fpa_alloc(fpa_pool);
175 if (buffer == NULL) {
176 cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
177 "Unable to allocate initial buffer.\n");
178 return CVMX_CMD_QUEUE_NO_MEMORY;
179 }
180
181 memset(qstate, 0, sizeof(*qstate));
182 qstate->max_depth = max_depth;
183 qstate->fpa_pool = fpa_pool;
184 qstate->pool_size_m1 = (pool_size >> 3) - 1;
185 qstate->base_ptr_div128 = cvmx_ptr_to_phys(buffer) / 128;
186 /*
187 * We zeroed the now serving field so we need to also
188 * zero the ticket.
189 */
190 __cvmx_cmd_queue_state_ptr->
191 ticket[__cvmx_cmd_queue_get_index(queue_id)] = 0;
192 CVMX_SYNCWS;
193 return CVMX_CMD_QUEUE_SUCCESS;
194 }
195}
196
197/**
198 * Shutdown a queue a free it's command buffers to the FPA. The
199 * hardware connected to the queue must be stopped before this
200 * function is called.
201 *
202 * @queue_id: Queue to shutdown
203 *
204 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
205 */
206cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id)
207{
208 __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
209 if (qptr == NULL) {
210 cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Unable to "
211 "get queue information.\n");
212 return CVMX_CMD_QUEUE_INVALID_PARAM;
213 }
214
215 if (cvmx_cmd_queue_length(queue_id) > 0) {
216 cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Queue still "
217 "has data in it.\n");
218 return CVMX_CMD_QUEUE_FULL;
219 }
220
221 __cvmx_cmd_queue_lock(queue_id, qptr);
222 if (qptr->base_ptr_div128) {
223 cvmx_fpa_free(cvmx_phys_to_ptr
224 ((uint64_t) qptr->base_ptr_div128 << 7),
225 qptr->fpa_pool, 0);
226 qptr->base_ptr_div128 = 0;
227 }
228 __cvmx_cmd_queue_unlock(qptr);
229
230 return CVMX_CMD_QUEUE_SUCCESS;
231}
232
233/**
234 * Return the number of command words pending in the queue. This
235 * function may be relatively slow for some hardware units.
236 *
237 * @queue_id: Hardware command queue to query
238 *
239 * Returns Number of outstanding commands
240 */
241int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
242{
243 if (CVMX_ENABLE_PARAMETER_CHECKING) {
244 if (__cvmx_cmd_queue_get_state(queue_id) == NULL)
245 return CVMX_CMD_QUEUE_INVALID_PARAM;
246 }
247
248 /*
249 * The cast is here so gcc with check that all values in the
250 * cvmx_cmd_queue_id_t enumeration are here.
251 */
252 switch ((cvmx_cmd_queue_id_t) (queue_id & 0xff0000)) {
253 case CVMX_CMD_QUEUE_PKO_BASE:
254 /*
255 * FIXME: Need atomic lock on
256 * CVMX_PKO_REG_READ_IDX. Right now we are normally
257 * called with the queue lock, so that is a SLIGHT
258 * amount of protection.
259 */
260 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue_id & 0xffff);
261 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
262 union cvmx_pko_mem_debug9 debug9;
263 debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
264 return debug9.cn38xx.doorbell;
265 } else {
266 union cvmx_pko_mem_debug8 debug8;
267 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
268 return debug8.cn58xx.doorbell;
269 }
270 case CVMX_CMD_QUEUE_ZIP:
271 case CVMX_CMD_QUEUE_DFA:
272 case CVMX_CMD_QUEUE_RAID:
273 /* FIXME: Implement other lengths */
274 return 0;
275 case CVMX_CMD_QUEUE_DMA_BASE:
276 {
277 union cvmx_npei_dmax_counts dmax_counts;
278 dmax_counts.u64 =
279 cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS
280 (queue_id & 0x7));
281 return dmax_counts.s.dbell;
282 }
283 case CVMX_CMD_QUEUE_END:
284 return CVMX_CMD_QUEUE_INVALID_PARAM;
285 }
286 return CVMX_CMD_QUEUE_INVALID_PARAM;
287}
288
289/**
290 * Return the command buffer to be written to. The purpose of this
291 * function is to allow CVMX routine access t othe low level buffer
292 * for initial hardware setup. User applications should not call this
293 * function directly.
294 *
295 * @queue_id: Command queue to query
296 *
297 * Returns Command buffer or NULL on failure
298 */
299void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id)
300{
301 __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
302 if (qptr && qptr->base_ptr_div128)
303 return cvmx_phys_to_ptr((uint64_t) qptr->base_ptr_div128 << 7);
304 else
305 return NULL;
306}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-fpa.c
new file mode 100644
index 000000000000..ad44b8bd8057
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-fpa.c
@@ -0,0 +1,183 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Support library for the hardware Free Pool Allocator.
32 *
33 *
34 */
35
36#include "cvmx-config.h"
37#include "cvmx.h"
38#include "cvmx-fpa.h"
39#include "cvmx-ipd.h"
40
41/**
42 * Current state of all the pools. Use access functions
43 * instead of using it directly.
44 */
45CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
46
47/**
48 * Setup a FPA pool to control a new block of memory. The
49 * buffer pointer must be a physical address.
50 *
51 * @pool: Pool to initialize
52 * 0 <= pool < 8
53 * @name: Constant character string to name this pool.
54 * String is not copied.
55 * @buffer: Pointer to the block of memory to use. This must be
56 * accessible by all processors and external hardware.
57 * @block_size: Size for each block controlled by the FPA
58 * @num_blocks: Number of blocks
59 *
60 * Returns 0 on Success,
61 * -1 on failure
62 */
63int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
64 uint64_t block_size, uint64_t num_blocks)
65{
66 char *ptr;
67 if (!buffer) {
68 cvmx_dprintf
69 ("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n");
70 return -1;
71 }
72 if (pool >= CVMX_FPA_NUM_POOLS) {
73 cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n");
74 return -1;
75 }
76
77 if (block_size < CVMX_FPA_MIN_BLOCK_SIZE) {
78 cvmx_dprintf
79 ("ERROR: cvmx_fpa_setup_pool: Block size too small.\n");
80 return -1;
81 }
82
83 if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT - 1)) != 0) {
84 cvmx_dprintf
85 ("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n");
86 return -1;
87 }
88
89 cvmx_fpa_pool_info[pool].name = name;
90 cvmx_fpa_pool_info[pool].size = block_size;
91 cvmx_fpa_pool_info[pool].starting_element_count = num_blocks;
92 cvmx_fpa_pool_info[pool].base = buffer;
93
94 ptr = (char *)buffer;
95 while (num_blocks--) {
96 cvmx_fpa_free(ptr, pool, 0);
97 ptr += block_size;
98 }
99 return 0;
100}
101
102/**
103 * Shutdown a Memory pool and validate that it had all of
104 * the buffers originally placed in it.
105 *
106 * @pool: Pool to shutdown
107 * Returns Zero on success
108 * - Positive is count of missing buffers
109 * - Negative is too many buffers or corrupted pointers
110 */
111uint64_t cvmx_fpa_shutdown_pool(uint64_t pool)
112{
113 uint64_t errors = 0;
114 uint64_t count = 0;
115 uint64_t base = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base);
116 uint64_t finish =
117 base +
118 cvmx_fpa_pool_info[pool].size *
119 cvmx_fpa_pool_info[pool].starting_element_count;
120 void *ptr;
121 uint64_t address;
122
123 count = 0;
124 do {
125 ptr = cvmx_fpa_alloc(pool);
126 if (ptr)
127 address = cvmx_ptr_to_phys(ptr);
128 else
129 address = 0;
130 if (address) {
131 if ((address >= base) && (address < finish) &&
132 (((address -
133 base) % cvmx_fpa_pool_info[pool].size) == 0)) {
134 count++;
135 } else {
136 cvmx_dprintf
137 ("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n",
138 (unsigned long long)address,
139 cvmx_fpa_pool_info[pool].name, (int)pool);
140 errors++;
141 }
142 }
143 } while (address);
144
145#ifdef CVMX_ENABLE_PKO_FUNCTIONS
146 if (pool == 0)
147 cvmx_ipd_free_ptr();
148#endif
149
150 if (errors) {
151 cvmx_dprintf
152 ("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n",
153 cvmx_fpa_pool_info[pool].name, (int)pool,
154 (unsigned long long)base, (unsigned long long)finish,
155 (unsigned long long)cvmx_fpa_pool_info[pool].size);
156 return -errors;
157 } else
158 return 0;
159}
160
161uint64_t cvmx_fpa_get_block_size(uint64_t pool)
162{
163 switch (pool) {
164 case 0:
165 return CVMX_FPA_POOL_0_SIZE;
166 case 1:
167 return CVMX_FPA_POOL_1_SIZE;
168 case 2:
169 return CVMX_FPA_POOL_2_SIZE;
170 case 3:
171 return CVMX_FPA_POOL_3_SIZE;
172 case 4:
173 return CVMX_FPA_POOL_4_SIZE;
174 case 5:
175 return CVMX_FPA_POOL_5_SIZE;
176 case 6:
177 return CVMX_FPA_POOL_6_SIZE;
178 case 7:
179 return CVMX_FPA_POOL_7_SIZE;
180 default:
181 return 0;
182 }
183}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
new file mode 100644
index 000000000000..fd2015331a20
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -0,0 +1,711 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Helper functions to abstract board specific data about
31 * network ports from the rest of the cvmx-helper files.
32 */
33
34#include <asm/octeon/octeon.h>
35#include <asm/octeon/cvmx-bootinfo.h>
36
37#include <asm/octeon/cvmx-config.h>
38
39#include <asm/octeon/cvmx-mdio.h>
40
41#include <asm/octeon/cvmx-helper.h>
42#include <asm/octeon/cvmx-helper-util.h>
43#include <asm/octeon/cvmx-helper-board.h>
44
45#include <asm/octeon/cvmx-gmxx-defs.h>
46#include <asm/octeon/cvmx-asxx-defs.h>
47
48/**
49 * cvmx_override_board_link_get(int ipd_port) is a function
50 * pointer. It is meant to allow customization of the process of
51 * talking to a PHY to determine link speed. It is called every
52 * time a PHY must be polled for link status. Users should set
53 * this pointer to a function before calling any cvmx-helper
54 * operations.
55 */
56cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) =
57 NULL;
58
59/**
60 * Return the MII PHY address associated with the given IPD
61 * port. A result of -1 means there isn't a MII capable PHY
62 * connected to this port. On chips supporting multiple MII
63 * busses the bus number is encoded in bits <15:8>.
64 *
65 * This function must be modified for every new Octeon board.
66 * Internally it uses switch statements based on the cvmx_sysinfo
67 * data to determine board types and revisions. It replies on the
68 * fact that every Octeon board receives a unique board type
69 * enumeration from the bootloader.
70 *
71 * @ipd_port: Octeon IPD port to get the MII address for.
72 *
73 * Returns MII PHY address and bus number or -1.
74 */
75int cvmx_helper_board_get_mii_address(int ipd_port)
76{
77 switch (cvmx_sysinfo_get()->board_type) {
78 case CVMX_BOARD_TYPE_SIM:
79 /* Simulator doesn't have MII */
80 return -1;
81 case CVMX_BOARD_TYPE_EBT3000:
82 case CVMX_BOARD_TYPE_EBT5800:
83 case CVMX_BOARD_TYPE_THUNDER:
84 case CVMX_BOARD_TYPE_NICPRO2:
85 /* Interface 0 is SPI4, interface 1 is RGMII */
86 if ((ipd_port >= 16) && (ipd_port < 20))
87 return ipd_port - 16;
88 else
89 return -1;
90 case CVMX_BOARD_TYPE_KODAMA:
91 case CVMX_BOARD_TYPE_EBH3100:
92 case CVMX_BOARD_TYPE_HIKARI:
93 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
94 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
95 case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
96 /*
97 * Port 0 is WAN connected to a PHY, Port 1 is GMII
98 * connected to a switch
99 */
100 if (ipd_port == 0)
101 return 4;
102 else if (ipd_port == 1)
103 return 9;
104 else
105 return -1;
106 case CVMX_BOARD_TYPE_NAC38:
107 /* Board has 8 RGMII ports PHYs are 0-7 */
108 if ((ipd_port >= 0) && (ipd_port < 4))
109 return ipd_port;
110 else if ((ipd_port >= 16) && (ipd_port < 20))
111 return ipd_port - 16 + 4;
112 else
113 return -1;
114 case CVMX_BOARD_TYPE_EBH3000:
115 /* Board has dual SPI4 and no PHYs */
116 return -1;
117 case CVMX_BOARD_TYPE_EBH5200:
118 case CVMX_BOARD_TYPE_EBH5201:
119 case CVMX_BOARD_TYPE_EBT5200:
120 /* Board has 2 management ports */
121 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
122 (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
123 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
124 /*
125 * Board has 4 SGMII ports. The PHYs start right after the MII
126 * ports MII0 = 0, MII1 = 1, SGMII = 2-5.
127 */
128 if ((ipd_port >= 0) && (ipd_port < 4))
129 return ipd_port + 2;
130 else
131 return -1;
132 case CVMX_BOARD_TYPE_EBH5600:
133 case CVMX_BOARD_TYPE_EBH5601:
134 case CVMX_BOARD_TYPE_EBH5610:
135 /* Board has 1 management port */
136 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
137 return 0;
138 /*
139 * Board has 8 SGMII ports. 4 connect out, two connect
140 * to a switch, and 2 loop to each other
141 */
142 if ((ipd_port >= 0) && (ipd_port < 4))
143 return ipd_port + 1;
144 else
145 return -1;
146 case CVMX_BOARD_TYPE_CUST_NB5:
147 if (ipd_port == 2)
148 return 4;
149 else
150 return -1;
151 case CVMX_BOARD_TYPE_NIC_XLE_4G:
152 /* Board has 4 SGMII ports. connected QLM3(interface 1) */
153 if ((ipd_port >= 16) && (ipd_port < 20))
154 return ipd_port - 16 + 1;
155 else
156 return -1;
157 case CVMX_BOARD_TYPE_NIC_XLE_10G:
158 case CVMX_BOARD_TYPE_NIC10E:
159 return -1;
160 case CVMX_BOARD_TYPE_NIC4E:
161 if (ipd_port >= 0 && ipd_port <= 3)
162 return (ipd_port + 0x1f) & 0x1f;
163 else
164 return -1;
165 case CVMX_BOARD_TYPE_NIC2E:
166 if (ipd_port >= 0 && ipd_port <= 1)
167 return ipd_port + 1;
168 else
169 return -1;
170 case CVMX_BOARD_TYPE_BBGW_REF:
171 /*
172 * No PHYs are connected to Octeon, everything is
173 * through switch.
174 */
175 return -1;
176
177 case CVMX_BOARD_TYPE_CUST_WSX16:
178 if (ipd_port >= 0 && ipd_port <= 3)
179 return ipd_port;
180 else if (ipd_port >= 16 && ipd_port <= 19)
181 return ipd_port - 16 + 4;
182 else
183 return -1;
184 }
185
186 /* Some unknown board. Somebody forgot to update this function... */
187 cvmx_dprintf
188 ("cvmx_helper_board_get_mii_address: Unknown board type %d\n",
189 cvmx_sysinfo_get()->board_type);
190 return -1;
191}
192
193/**
194 * This function is the board specific method of determining an
195 * ethernet ports link speed. Most Octeon boards have Marvell PHYs
196 * and are handled by the fall through case. This function must be
197 * updated for boards that don't have the normal Marvell PHYs.
198 *
199 * This function must be modified for every new Octeon board.
200 * Internally it uses switch statements based on the cvmx_sysinfo
201 * data to determine board types and revisions. It relies on the
202 * fact that every Octeon board receives a unique board type
203 * enumeration from the bootloader.
204 *
205 * @ipd_port: IPD input port associated with the port we want to get link
206 * status for.
207 *
208 * Returns The ports link status. If the link isn't fully resolved, this must
209 * return zero.
210 */
211cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
212{
213 cvmx_helper_link_info_t result;
214 int phy_addr;
215 int is_broadcom_phy = 0;
216
217 /* Give the user a chance to override the processing of this function */
218 if (cvmx_override_board_link_get)
219 return cvmx_override_board_link_get(ipd_port);
220
221 /* Unless we fix it later, all links are defaulted to down */
222 result.u64 = 0;
223
224 /*
225 * This switch statement should handle all ports that either don't use
226 * Marvell PHYS, or don't support in-band status.
227 */
228 switch (cvmx_sysinfo_get()->board_type) {
229 case CVMX_BOARD_TYPE_SIM:
230 /* The simulator gives you a simulated 1Gbps full duplex link */
231 result.s.link_up = 1;
232 result.s.full_duplex = 1;
233 result.s.speed = 1000;
234 return result;
235 case CVMX_BOARD_TYPE_EBH3100:
236 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
237 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
238 case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
239 /* Port 1 on these boards is always Gigabit */
240 if (ipd_port == 1) {
241 result.s.link_up = 1;
242 result.s.full_duplex = 1;
243 result.s.speed = 1000;
244 return result;
245 }
246 /* Fall through to the generic code below */
247 break;
248 case CVMX_BOARD_TYPE_CUST_NB5:
249 /* Port 1 on these boards is always Gigabit */
250 if (ipd_port == 1) {
251 result.s.link_up = 1;
252 result.s.full_duplex = 1;
253 result.s.speed = 1000;
254 return result;
255 } else /* The other port uses a broadcom PHY */
256 is_broadcom_phy = 1;
257 break;
258 case CVMX_BOARD_TYPE_BBGW_REF:
259 /* Port 1 on these boards is always Gigabit */
260 if (ipd_port == 2) {
261 /* Port 2 is not hooked up */
262 result.u64 = 0;
263 return result;
264 } else {
265 /* Ports 0 and 1 connect to the switch */
266 result.s.link_up = 1;
267 result.s.full_duplex = 1;
268 result.s.speed = 1000;
269 return result;
270 }
271 break;
272 }
273
274 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
275 if (phy_addr != -1) {
276 if (is_broadcom_phy) {
277 /*
278 * Below we are going to read SMI/MDIO
279 * register 0x19 which works on Broadcom
280 * parts
281 */
282 int phy_status =
283 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
284 0x19);
285 switch ((phy_status >> 8) & 0x7) {
286 case 0:
287 result.u64 = 0;
288 break;
289 case 1:
290 result.s.link_up = 1;
291 result.s.full_duplex = 0;
292 result.s.speed = 10;
293 break;
294 case 2:
295 result.s.link_up = 1;
296 result.s.full_duplex = 1;
297 result.s.speed = 10;
298 break;
299 case 3:
300 result.s.link_up = 1;
301 result.s.full_duplex = 0;
302 result.s.speed = 100;
303 break;
304 case 4:
305 result.s.link_up = 1;
306 result.s.full_duplex = 1;
307 result.s.speed = 100;
308 break;
309 case 5:
310 result.s.link_up = 1;
311 result.s.full_duplex = 1;
312 result.s.speed = 100;
313 break;
314 case 6:
315 result.s.link_up = 1;
316 result.s.full_duplex = 0;
317 result.s.speed = 1000;
318 break;
319 case 7:
320 result.s.link_up = 1;
321 result.s.full_duplex = 1;
322 result.s.speed = 1000;
323 break;
324 }
325 } else {
326 /*
327 * This code assumes we are using a Marvell
328 * Gigabit PHY. All the speed information can
329 * be read from register 17 in one
330 * go. Somebody using a different PHY will
331 * need to handle it above in the board
332 * specific area.
333 */
334 int phy_status =
335 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
336
337 /*
338 * If the resolve bit 11 isn't set, see if
339 * autoneg is turned off (bit 12, reg 0). The
340 * resolve bit doesn't get set properly when
341 * autoneg is off, so force it.
342 */
343 if ((phy_status & (1 << 11)) == 0) {
344 int auto_status =
345 cvmx_mdio_read(phy_addr >> 8,
346 phy_addr & 0xff, 0);
347 if ((auto_status & (1 << 12)) == 0)
348 phy_status |= 1 << 11;
349 }
350
351 /*
352 * Only return a link if the PHY has finished
353 * auto negotiation and set the resolved bit
354 * (bit 11)
355 */
356 if (phy_status & (1 << 11)) {
357 result.s.link_up = 1;
358 result.s.full_duplex = ((phy_status >> 13) & 1);
359 switch ((phy_status >> 14) & 3) {
360 case 0: /* 10 Mbps */
361 result.s.speed = 10;
362 break;
363 case 1: /* 100 Mbps */
364 result.s.speed = 100;
365 break;
366 case 2: /* 1 Gbps */
367 result.s.speed = 1000;
368 break;
369 case 3: /* Illegal */
370 result.u64 = 0;
371 break;
372 }
373 }
374 }
375 } else if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
376 || OCTEON_IS_MODEL(OCTEON_CN58XX)
377 || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
378 /*
379 * We don't have a PHY address, so attempt to use
380 * in-band status. It is really important that boards
381 * not supporting in-band status never get
382 * here. Reading broken in-band status tends to do bad
383 * things
384 */
385 union cvmx_gmxx_rxx_rx_inbnd inband_status;
386 int interface = cvmx_helper_get_interface_num(ipd_port);
387 int index = cvmx_helper_get_interface_index_num(ipd_port);
388 inband_status.u64 =
389 cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
390
391 result.s.link_up = inband_status.s.status;
392 result.s.full_duplex = inband_status.s.duplex;
393 switch (inband_status.s.speed) {
394 case 0: /* 10 Mbps */
395 result.s.speed = 10;
396 break;
397 case 1: /* 100 Mbps */
398 result.s.speed = 100;
399 break;
400 case 2: /* 1 Gbps */
401 result.s.speed = 1000;
402 break;
403 case 3: /* Illegal */
404 result.u64 = 0;
405 break;
406 }
407 } else {
408 /*
409 * We don't have a PHY address and we don't have
410 * in-band status. There is no way to determine the
411 * link speed. Return down assuming this port isn't
412 * wired
413 */
414 result.u64 = 0;
415 }
416
417 /* If link is down, return all fields as zero. */
418 if (!result.s.link_up)
419 result.u64 = 0;
420
421 return result;
422}
423
424/**
425 * This function as a board specific method of changing the PHY
426 * speed, duplex, and auto-negotiation. This programs the PHY and
427 * not Octeon. This can be used to force Octeon's links to
428 * specific settings.
429 *
430 * @phy_addr: The address of the PHY to program
431 * @enable_autoneg:
432 * Non zero if you want to enable auto-negotiation.
433 * @link_info: Link speed to program. If the speed is zero and auto-negotiation
434 * is enabled, all possible negotiation speeds are advertised.
435 *
436 * Returns Zero on success, negative on failure
437 */
438int cvmx_helper_board_link_set_phy(int phy_addr,
439 cvmx_helper_board_set_phy_link_flags_types_t
440 link_flags,
441 cvmx_helper_link_info_t link_info)
442{
443
444 /* Set the flow control settings based on link_flags */
445 if ((link_flags & set_phy_link_flags_flow_control_mask) !=
446 set_phy_link_flags_flow_control_dont_touch) {
447 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
448 reg_autoneg_adver.u16 =
449 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
450 CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
451 reg_autoneg_adver.s.asymmetric_pause =
452 (link_flags & set_phy_link_flags_flow_control_mask) ==
453 set_phy_link_flags_flow_control_enable;
454 reg_autoneg_adver.s.pause =
455 (link_flags & set_phy_link_flags_flow_control_mask) ==
456 set_phy_link_flags_flow_control_enable;
457 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
458 CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
459 reg_autoneg_adver.u16);
460 }
461
462 /* If speed isn't set and autoneg is on advertise all supported modes */
463 if ((link_flags & set_phy_link_flags_autoneg)
464 && (link_info.s.speed == 0)) {
465 cvmx_mdio_phy_reg_control_t reg_control;
466 cvmx_mdio_phy_reg_status_t reg_status;
467 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
468 cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
469 cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
470
471 reg_status.u16 =
472 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
473 CVMX_MDIO_PHY_REG_STATUS);
474 reg_autoneg_adver.u16 =
475 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
476 CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
477 reg_autoneg_adver.s.advert_100base_t4 =
478 reg_status.s.capable_100base_t4;
479 reg_autoneg_adver.s.advert_10base_tx_full =
480 reg_status.s.capable_10_full;
481 reg_autoneg_adver.s.advert_10base_tx_half =
482 reg_status.s.capable_10_half;
483 reg_autoneg_adver.s.advert_100base_tx_full =
484 reg_status.s.capable_100base_x_full;
485 reg_autoneg_adver.s.advert_100base_tx_half =
486 reg_status.s.capable_100base_x_half;
487 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
488 CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
489 reg_autoneg_adver.u16);
490 if (reg_status.s.capable_extended_status) {
491 reg_extended_status.u16 =
492 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
493 CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
494 reg_control_1000.u16 =
495 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
496 CVMX_MDIO_PHY_REG_CONTROL_1000);
497 reg_control_1000.s.advert_1000base_t_full =
498 reg_extended_status.s.capable_1000base_t_full;
499 reg_control_1000.s.advert_1000base_t_half =
500 reg_extended_status.s.capable_1000base_t_half;
501 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
502 CVMX_MDIO_PHY_REG_CONTROL_1000,
503 reg_control_1000.u16);
504 }
505 reg_control.u16 =
506 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
507 CVMX_MDIO_PHY_REG_CONTROL);
508 reg_control.s.autoneg_enable = 1;
509 reg_control.s.restart_autoneg = 1;
510 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
511 CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
512 } else if ((link_flags & set_phy_link_flags_autoneg)) {
513 cvmx_mdio_phy_reg_control_t reg_control;
514 cvmx_mdio_phy_reg_status_t reg_status;
515 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
516 cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
517
518 reg_status.u16 =
519 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
520 CVMX_MDIO_PHY_REG_STATUS);
521 reg_autoneg_adver.u16 =
522 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
523 CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
524 reg_autoneg_adver.s.advert_100base_t4 = 0;
525 reg_autoneg_adver.s.advert_10base_tx_full = 0;
526 reg_autoneg_adver.s.advert_10base_tx_half = 0;
527 reg_autoneg_adver.s.advert_100base_tx_full = 0;
528 reg_autoneg_adver.s.advert_100base_tx_half = 0;
529 if (reg_status.s.capable_extended_status) {
530 reg_control_1000.u16 =
531 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
532 CVMX_MDIO_PHY_REG_CONTROL_1000);
533 reg_control_1000.s.advert_1000base_t_full = 0;
534 reg_control_1000.s.advert_1000base_t_half = 0;
535 }
536 switch (link_info.s.speed) {
537 case 10:
538 reg_autoneg_adver.s.advert_10base_tx_full =
539 link_info.s.full_duplex;
540 reg_autoneg_adver.s.advert_10base_tx_half =
541 !link_info.s.full_duplex;
542 break;
543 case 100:
544 reg_autoneg_adver.s.advert_100base_tx_full =
545 link_info.s.full_duplex;
546 reg_autoneg_adver.s.advert_100base_tx_half =
547 !link_info.s.full_duplex;
548 break;
549 case 1000:
550 reg_control_1000.s.advert_1000base_t_full =
551 link_info.s.full_duplex;
552 reg_control_1000.s.advert_1000base_t_half =
553 !link_info.s.full_duplex;
554 break;
555 }
556 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
557 CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
558 reg_autoneg_adver.u16);
559 if (reg_status.s.capable_extended_status)
560 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
561 CVMX_MDIO_PHY_REG_CONTROL_1000,
562 reg_control_1000.u16);
563 reg_control.u16 =
564 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
565 CVMX_MDIO_PHY_REG_CONTROL);
566 reg_control.s.autoneg_enable = 1;
567 reg_control.s.restart_autoneg = 1;
568 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
569 CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
570 } else {
571 cvmx_mdio_phy_reg_control_t reg_control;
572 reg_control.u16 =
573 cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
574 CVMX_MDIO_PHY_REG_CONTROL);
575 reg_control.s.autoneg_enable = 0;
576 reg_control.s.restart_autoneg = 1;
577 reg_control.s.duplex = link_info.s.full_duplex;
578 if (link_info.s.speed == 1000) {
579 reg_control.s.speed_msb = 1;
580 reg_control.s.speed_lsb = 0;
581 } else if (link_info.s.speed == 100) {
582 reg_control.s.speed_msb = 0;
583 reg_control.s.speed_lsb = 1;
584 } else if (link_info.s.speed == 10) {
585 reg_control.s.speed_msb = 0;
586 reg_control.s.speed_lsb = 0;
587 }
588 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
589 CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
590 }
591 return 0;
592}
593
594/**
595 * This function is called by cvmx_helper_interface_probe() after it
596 * determines the number of ports Octeon can support on a specific
597 * interface. This function is the per board location to override
598 * this value. It is called with the number of ports Octeon might
599 * support and should return the number of actual ports on the
600 * board.
601 *
602 * This function must be modifed for every new Octeon board.
603 * Internally it uses switch statements based on the cvmx_sysinfo
604 * data to determine board types and revisions. It relys on the
605 * fact that every Octeon board receives a unique board type
606 * enumeration from the bootloader.
607 *
608 * @interface: Interface to probe
609 * @supported_ports:
610 * Number of ports Octeon supports.
611 *
612 * Returns Number of ports the actual board supports. Many times this will
613 * simple be "support_ports".
614 */
615int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
616{
617 switch (cvmx_sysinfo_get()->board_type) {
618 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
619 if (interface == 0)
620 return 2;
621 break;
622 case CVMX_BOARD_TYPE_BBGW_REF:
623 if (interface == 0)
624 return 2;
625 break;
626 case CVMX_BOARD_TYPE_NIC_XLE_4G:
627 if (interface == 0)
628 return 0;
629 break;
630 /* The 2nd interface on the EBH5600 is connected to the Marvel switch,
631 which we don't support. Disable ports connected to it */
632 case CVMX_BOARD_TYPE_EBH5600:
633 if (interface == 1)
634 return 0;
635 break;
636 }
637 return supported_ports;
638}
639
640/**
641 * Enable packet input/output from the hardware. This function is
642 * called after by cvmx_helper_packet_hardware_enable() to
643 * perform board specific initialization. For most boards
644 * nothing is needed.
645 *
646 * @interface: Interface to enable
647 *
648 * Returns Zero on success, negative on failure
649 */
650int __cvmx_helper_board_hardware_enable(int interface)
651{
652 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) {
653 if (interface == 0) {
654 /* Different config for switch port */
655 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0);
656 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
657 /*
658 * Boards with gigabit WAN ports need a
659 * different setting that is compatible with
660 * 100 Mbit settings
661 */
662 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface),
663 0xc);
664 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface),
665 0xc);
666 }
667 } else if (cvmx_sysinfo_get()->board_type ==
668 CVMX_BOARD_TYPE_CN3010_EVB_HS5) {
669 /*
670 * Broadcom PHYs require differnet ASX
671 * clocks. Unfortunately many boards don't define a
672 * new board Id and simply mangle the
673 * CN3010_EVB_HS5
674 */
675 if (interface == 0) {
676 /*
677 * Some boards use a hacked up bootloader that
678 * identifies them as CN3010_EVB_HS5
679 * evaluation boards. This leads to all kinds
680 * of configuration problems. Detect one
681 * case, and print warning, while trying to do
682 * the right thing.
683 */
684 int phy_addr = cvmx_helper_board_get_mii_address(0);
685 if (phy_addr != -1) {
686 int phy_identifier =
687 cvmx_mdio_read(phy_addr >> 8,
688 phy_addr & 0xff, 0x2);
689 /* Is it a Broadcom PHY? */
690 if (phy_identifier == 0x0143) {
691 cvmx_dprintf("\n");
692 cvmx_dprintf("ERROR:\n");
693 cvmx_dprintf
694 ("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n");
695 cvmx_dprintf
696 ("ERROR: The board type is mis-configured, and software malfunctions are likely.\n");
697 cvmx_dprintf
698 ("ERROR: All boards require a unique board type to identify them.\n");
699 cvmx_dprintf("ERROR:\n");
700 cvmx_dprintf("\n");
701 cvmx_wait(1000000000);
702 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX
703 (0, interface), 5);
704 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX
705 (0, interface), 5);
706 }
707 }
708 }
709 }
710 return 0;
711}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
new file mode 100644
index 000000000000..c239e5f4ab9a
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
@@ -0,0 +1,243 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Helper functions for FPA setup.
32 *
33 */
34#include "executive-config.h"
35#include "cvmx-config.h"
36#include "cvmx.h"
37#include "cvmx-bootmem.h"
38#include "cvmx-fpa.h"
39#include "cvmx-helper-fpa.h"
40
41/**
42 * Allocate memory for and initialize a single FPA pool.
43 *
44 * @pool: Pool to initialize
45 * @buffer_size: Size of buffers to allocate in bytes
46 * @buffers: Number of buffers to put in the pool. Zero is allowed
47 * @name: String name of the pool for debugging purposes
48 * Returns Zero on success, non-zero on failure
49 */
50static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size,
51 uint64_t buffers, const char *name)
52{
53 uint64_t current_num;
54 void *memory;
55 uint64_t align = CVMX_CACHE_LINE_SIZE;
56
57 /*
58 * Align the allocation so that power of 2 size buffers are
59 * naturally aligned.
60 */
61 while (align < buffer_size)
62 align = align << 1;
63
64 if (buffers == 0)
65 return 0;
66
67 current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool));
68 if (current_num) {
69 cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. "
70 "Skipping setup.\n",
71 pool, name, (unsigned long long)current_num);
72 return 0;
73 }
74
75 memory = cvmx_bootmem_alloc(buffer_size * buffers, align);
76 if (memory == NULL) {
77 cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n",
78 pool, name);
79 return -1;
80 }
81 cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers);
82 return 0;
83}
84
85/**
86 * Allocate memory and initialize the FPA pools using memory
87 * from cvmx-bootmem. Specifying zero for the number of
88 * buffers will cause that FPA pool to not be setup. This is
89 * useful if you aren't using some of the hardware and want
90 * to save memory. Use cvmx_helper_initialize_fpa instead of
91 * this function directly.
92 *
93 * @pip_pool: Should always be CVMX_FPA_PACKET_POOL
94 * @pip_size: Should always be CVMX_FPA_PACKET_POOL_SIZE
95 * @pip_buffers:
96 * Number of packet buffers.
97 * @wqe_pool: Should always be CVMX_FPA_WQE_POOL
98 * @wqe_size: Should always be CVMX_FPA_WQE_POOL_SIZE
99 * @wqe_entries:
100 * Number of work queue entries
101 * @pko_pool: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL
102 * @pko_size: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE
103 * @pko_buffers:
104 * PKO Command buffers. You should at minimum have two per
105 * each PKO queue.
106 * @tim_pool: Should always be CVMX_FPA_TIMER_POOL
107 * @tim_size: Should always be CVMX_FPA_TIMER_POOL_SIZE
108 * @tim_buffers:
109 * TIM ring buffer command queues. At least two per timer bucket
110 * is recommened.
111 * @dfa_pool: Should always be CVMX_FPA_DFA_POOL
112 * @dfa_size: Should always be CVMX_FPA_DFA_POOL_SIZE
113 * @dfa_buffers:
114 * DFA command buffer. A relatively small (32 for example)
115 * number should work.
116 * Returns Zero on success, non-zero if out of memory
117 */
118static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size,
119 int pip_buffers, int wqe_pool,
120 int wqe_size, int wqe_entries,
121 int pko_pool, int pko_size,
122 int pko_buffers, int tim_pool,
123 int tim_size, int tim_buffers,
124 int dfa_pool, int dfa_size,
125 int dfa_buffers)
126{
127 int status;
128
129 cvmx_fpa_enable();
130
131 if ((pip_buffers > 0) && (pip_buffers <= 64))
132 cvmx_dprintf
133 ("Warning: %d packet buffers may not be enough for hardware"
134 " prefetch. 65 or more is recommended.\n", pip_buffers);
135
136 if (pip_pool >= 0) {
137 status =
138 __cvmx_helper_initialize_fpa_pool(pip_pool, pip_size,
139 pip_buffers,
140 "Packet Buffers");
141 if (status)
142 return status;
143 }
144
145 if (wqe_pool >= 0) {
146 status =
147 __cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size,
148 wqe_entries,
149 "Work Queue Entries");
150 if (status)
151 return status;
152 }
153
154 if (pko_pool >= 0) {
155 status =
156 __cvmx_helper_initialize_fpa_pool(pko_pool, pko_size,
157 pko_buffers,
158 "PKO Command Buffers");
159 if (status)
160 return status;
161 }
162
163 if (tim_pool >= 0) {
164 status =
165 __cvmx_helper_initialize_fpa_pool(tim_pool, tim_size,
166 tim_buffers,
167 "TIM Command Buffers");
168 if (status)
169 return status;
170 }
171
172 if (dfa_pool >= 0) {
173 status =
174 __cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size,
175 dfa_buffers,
176 "DFA Command Buffers");
177 if (status)
178 return status;
179 }
180
181 return 0;
182}
183
184/**
185 * Allocate memory and initialize the FPA pools using memory
186 * from cvmx-bootmem. Sizes of each element in the pools is
187 * controlled by the cvmx-config.h header file. Specifying
188 * zero for any parameter will cause that FPA pool to not be
189 * setup. This is useful if you aren't using some of the
190 * hardware and want to save memory.
191 *
192 * @packet_buffers:
193 * Number of packet buffers to allocate
194 * @work_queue_entries:
195 * Number of work queue entries
196 * @pko_buffers:
197 * PKO Command buffers. You should at minimum have two per
198 * each PKO queue.
199 * @tim_buffers:
200 * TIM ring buffer command queues. At least two per timer bucket
201 * is recommened.
202 * @dfa_buffers:
203 * DFA command buffer. A relatively small (32 for example)
204 * number should work.
205 * Returns Zero on success, non-zero if out of memory
206 */
207int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries,
208 int pko_buffers, int tim_buffers,
209 int dfa_buffers)
210{
211#ifndef CVMX_FPA_PACKET_POOL
212#define CVMX_FPA_PACKET_POOL -1
213#define CVMX_FPA_PACKET_POOL_SIZE 0
214#endif
215#ifndef CVMX_FPA_WQE_POOL
216#define CVMX_FPA_WQE_POOL -1
217#define CVMX_FPA_WQE_POOL_SIZE 0
218#endif
219#ifndef CVMX_FPA_OUTPUT_BUFFER_POOL
220#define CVMX_FPA_OUTPUT_BUFFER_POOL -1
221#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0
222#endif
223#ifndef CVMX_FPA_TIMER_POOL
224#define CVMX_FPA_TIMER_POOL -1
225#define CVMX_FPA_TIMER_POOL_SIZE 0
226#endif
227#ifndef CVMX_FPA_DFA_POOL
228#define CVMX_FPA_DFA_POOL -1
229#define CVMX_FPA_DFA_POOL_SIZE 0
230#endif
231 return __cvmx_helper_initialize_fpa(CVMX_FPA_PACKET_POOL,
232 CVMX_FPA_PACKET_POOL_SIZE,
233 packet_buffers, CVMX_FPA_WQE_POOL,
234 CVMX_FPA_WQE_POOL_SIZE,
235 work_queue_entries,
236 CVMX_FPA_OUTPUT_BUFFER_POOL,
237 CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE,
238 pko_buffers, CVMX_FPA_TIMER_POOL,
239 CVMX_FPA_TIMER_POOL_SIZE,
240 tim_buffers, CVMX_FPA_DFA_POOL,
241 CVMX_FPA_DFA_POOL_SIZE,
242 dfa_buffers);
243}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c
new file mode 100644
index 000000000000..bfbd46115e71
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-loop.c
@@ -0,0 +1,85 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Functions for LOOP initialization, configuration,
30 * and monitoring.
31 */
32#include <asm/octeon/octeon.h>
33
34#include <asm/octeon/cvmx-config.h>
35
36#include <asm/octeon/cvmx-helper.h>
37#include <asm/octeon/cvmx-pip-defs.h>
38
39/**
40 * Probe a LOOP interface and determine the number of ports
41 * connected to it. The LOOP interface should still be down
42 * after this call.
43 *
44 * @interface: Interface to probe
45 *
46 * Returns Number of ports on the interface. Zero to disable.
47 */
48int __cvmx_helper_loop_probe(int interface)
49{
50 union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
51 int num_ports = 4;
52 int port;
53
54 /* We need to disable length checking so packet < 64 bytes and jumbo
55 frames don't get errors */
56 for (port = 0; port < num_ports; port++) {
57 union cvmx_pip_prt_cfgx port_cfg;
58 int ipd_port = cvmx_helper_get_ipd_port(interface, port);
59 port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
60 port_cfg.s.maxerr_en = 0;
61 port_cfg.s.minerr_en = 0;
62 cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64);
63 }
64
65 /* Disable FCS stripping for loopback ports */
66 ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
67 ipd_sub_port_fcs.s.port_bit2 = 0;
68 cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
69 return num_ports;
70}
71
72/**
73 * Bringup and enable a LOOP interface. After this call packet
74 * I/O should be fully functional. This is called with IPD
75 * enabled but PKO disabled.
76 *
77 * @interface: Interface to bring up
78 *
79 * Returns Zero on success, negative on failure
80 */
81int __cvmx_helper_loop_enable(int interface)
82{
83 /* Do nothing. */
84 return 0;
85}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
new file mode 100644
index 000000000000..cc94cfa545b4
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-npi.c
@@ -0,0 +1,113 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Functions for NPI initialization, configuration,
30 * and monitoring.
31 */
32#include <asm/octeon/octeon.h>
33
34#include <asm/octeon/cvmx-config.h>
35
36#include <asm/octeon/cvmx-helper.h>
37
38#include <asm/octeon/cvmx-pip-defs.h>
39
40/**
41 * Probe a NPI interface and determine the number of ports
42 * connected to it. The NPI interface should still be down
43 * after this call.
44 *
45 * @interface: Interface to probe
46 *
47 * Returns Number of ports on the interface. Zero to disable.
48 */
49int __cvmx_helper_npi_probe(int interface)
50{
51#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0
52 if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
53 return 4;
54 else if (OCTEON_IS_MODEL(OCTEON_CN56XX)
55 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
56 /* The packet engines didn't exist before pass 2 */
57 return 4;
58 else if (OCTEON_IS_MODEL(OCTEON_CN52XX)
59 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
60 /* The packet engines didn't exist before pass 2 */
61 return 4;
62#if 0
63 /*
64 * Technically CN30XX, CN31XX, and CN50XX contain packet
65 * engines, but nobody ever uses them. Since this is the case,
66 * we disable them here.
67 */
68 else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
69 || OCTEON_IS_MODEL(OCTEON_CN50XX))
70 return 2;
71 else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
72 return 1;
73#endif
74#endif
75 return 0;
76}
77
78/**
79 * Bringup and enable a NPI interface. After this call packet
80 * I/O should be fully functional. This is called with IPD
81 * enabled but PKO disabled.
82 *
83 * @interface: Interface to bring up
84 *
85 * Returns Zero on success, negative on failure
86 */
87int __cvmx_helper_npi_enable(int interface)
88{
89 /*
90 * On CN50XX, CN52XX, and CN56XX we need to disable length
91 * checking so packet < 64 bytes and jumbo frames don't get
92 * errors.
93 */
94 if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) &&
95 !OCTEON_IS_MODEL(OCTEON_CN58XX)) {
96 int num_ports = cvmx_helper_ports_on_interface(interface);
97 int port;
98 for (port = 0; port < num_ports; port++) {
99 union cvmx_pip_prt_cfgx port_cfg;
100 int ipd_port =
101 cvmx_helper_get_ipd_port(interface, port);
102 port_cfg.u64 =
103 cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
104 port_cfg.s.maxerr_en = 0;
105 port_cfg.s.minerr_en = 0;
106 cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port),
107 port_cfg.u64);
108 }
109 }
110
111 /* Enables are controlled by the remote host, so nothing to do here */
112 return 0;
113}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
new file mode 100644
index 000000000000..82b21843421c
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
@@ -0,0 +1,526 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Functions for RGMII/GMII/MII initialization, configuration,
30 * and monitoring.
31 */
32#include <asm/octeon/octeon.h>
33
34#include <asm/octeon/cvmx-config.h>
35
36
37#include <asm/octeon/cvmx-mdio.h>
38#include <asm/octeon/cvmx-pko.h>
39#include <asm/octeon/cvmx-helper.h>
40#include <asm/octeon/cvmx-helper-board.h>
41
42#include <asm/octeon/cvmx-npi-defs.h>
43#include <asm/octeon/cvmx-gmxx-defs.h>
44#include <asm/octeon/cvmx-asxx-defs.h>
45#include <asm/octeon/cvmx-dbg-defs.h>
46
47void __cvmx_interrupt_gmxx_enable(int interface);
48void __cvmx_interrupt_asxx_enable(int block);
49
50/**
51 * Probe RGMII ports and determine the number present
52 *
53 * @interface: Interface to probe
54 *
55 * Returns Number of RGMII/GMII/MII ports (0-4).
56 */
57int __cvmx_helper_rgmii_probe(int interface)
58{
59 int num_ports = 0;
60 union cvmx_gmxx_inf_mode mode;
61 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
62
63 if (mode.s.type) {
64 if (OCTEON_IS_MODEL(OCTEON_CN38XX)
65 || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
66 cvmx_dprintf("ERROR: RGMII initialize called in "
67 "SPI interface\n");
68 } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
69 || OCTEON_IS_MODEL(OCTEON_CN30XX)
70 || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
71 /*
72 * On these chips "type" says we're in
73 * GMII/MII mode. This limits us to 2 ports
74 */
75 num_ports = 2;
76 } else {
77 cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
78 __func__);
79 }
80 } else {
81 if (OCTEON_IS_MODEL(OCTEON_CN38XX)
82 || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
83 num_ports = 4;
84 } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
85 || OCTEON_IS_MODEL(OCTEON_CN30XX)
86 || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
87 num_ports = 3;
88 } else {
89 cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
90 __func__);
91 }
92 }
93 return num_ports;
94}
95
96/**
97 * Put an RGMII interface in loopback mode. Internal packets sent
98 * out will be received back again on the same port. Externally
99 * received packets will echo back out.
100 *
101 * @port: IPD port number to loop.
102 */
103void cvmx_helper_rgmii_internal_loopback(int port)
104{
105 int interface = (port >> 4) & 1;
106 int index = port & 0xf;
107 uint64_t tmp;
108
109 union cvmx_gmxx_prtx_cfg gmx_cfg;
110 gmx_cfg.u64 = 0;
111 gmx_cfg.s.duplex = 1;
112 gmx_cfg.s.slottime = 1;
113 gmx_cfg.s.speed = 1;
114 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
115 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
116 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
117 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
118 tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
119 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp);
120 tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
121 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp);
122 tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
123 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp);
124 gmx_cfg.s.en = 1;
125 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
126}
127
128/**
129 * Workaround ASX setup errata with CN38XX pass1
130 *
131 * @interface: Interface to setup
132 * @port: Port to setup (0..3)
133 * @cpu_clock_hz:
134 * Chip frequency in Hertz
135 *
136 * Returns Zero on success, negative on failure
137 */
138static int __cvmx_helper_errata_asx_pass1(int interface, int port,
139 int cpu_clock_hz)
140{
141 /* Set hi water mark as per errata GMX-4 */
142 if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000)
143 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);
144 else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000)
145 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);
146 else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000)
147 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);
148 else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000)
149 cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);
150 else
151 cvmx_dprintf("Illegal clock frequency (%d). "
152 "CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz);
153 return 0;
154}
155
156/**
157 * Configure all of the ASX, GMX, and PKO regsiters required
158 * to get RGMII to function on the supplied interface.
159 *
160 * @interface: PKO Interface to configure (0 or 1)
161 *
162 * Returns Zero on success
163 */
164int __cvmx_helper_rgmii_enable(int interface)
165{
166 int num_ports = cvmx_helper_ports_on_interface(interface);
167 int port;
168 struct cvmx_sysinfo *sys_info_ptr = cvmx_sysinfo_get();
169 union cvmx_gmxx_inf_mode mode;
170 union cvmx_asxx_tx_prt_en asx_tx;
171 union cvmx_asxx_rx_prt_en asx_rx;
172
173 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
174
175 if (mode.s.en == 0)
176 return -1;
177 if ((OCTEON_IS_MODEL(OCTEON_CN38XX) ||
178 OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1)
179 /* Ignore SPI interfaces */
180 return -1;
181
182 /* Configure the ASX registers needed to use the RGMII ports */
183 asx_tx.u64 = 0;
184 asx_tx.s.prt_en = cvmx_build_mask(num_ports);
185 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64);
186
187 asx_rx.u64 = 0;
188 asx_rx.s.prt_en = cvmx_build_mask(num_ports);
189 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64);
190
191 /* Configure the GMX registers needed to use the RGMII ports */
192 for (port = 0; port < num_ports; port++) {
193 /* Setting of CVMX_GMXX_TXX_THRESH has been moved to
194 __cvmx_helper_setup_gmx() */
195
196 if (cvmx_octeon_is_pass1())
197 __cvmx_helper_errata_asx_pass1(interface, port,
198 sys_info_ptr->
199 cpu_clock_hz);
200 else {
201 /*
202 * Configure more flexible RGMII preamble
203 * checking. Pass 1 doesn't support this
204 * feature.
205 */
206 union cvmx_gmxx_rxx_frm_ctl frm_ctl;
207 frm_ctl.u64 =
208 cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL
209 (port, interface));
210 /* New field, so must be compile time */
211 frm_ctl.s.pre_free = 1;
212 cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface),
213 frm_ctl.u64);
214 }
215
216 /*
217 * Each pause frame transmitted will ask for about 10M
218 * bit times before resume. If buffer space comes
219 * available before that time has expired, an XON
220 * pause frame (0 time) will be transmitted to restart
221 * the flow.
222 */
223 cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface),
224 20000);
225 cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL
226 (port, interface), 19000);
227
228 if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
229 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
230 16);
231 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
232 16);
233 } else {
234 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
235 24);
236 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
237 24);
238 }
239 }
240
241 __cvmx_helper_setup_gmx(interface, num_ports);
242
243 /* enable the ports now */
244 for (port = 0; port < num_ports; port++) {
245 union cvmx_gmxx_prtx_cfg gmx_cfg;
246 cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port
247 (interface, port));
248 gmx_cfg.u64 =
249 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface));
250 gmx_cfg.s.en = 1;
251 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface),
252 gmx_cfg.u64);
253 }
254 __cvmx_interrupt_asxx_enable(interface);
255 __cvmx_interrupt_gmxx_enable(interface);
256
257 return 0;
258}
259
260/**
261 * Return the link state of an IPD/PKO port as returned by
262 * auto negotiation. The result of this function may not match
263 * Octeon's link config if auto negotiation has changed since
264 * the last call to cvmx_helper_link_set().
265 *
266 * @ipd_port: IPD/PKO port to query
267 *
268 * Returns Link state
269 */
270cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port)
271{
272 int interface = cvmx_helper_get_interface_num(ipd_port);
273 int index = cvmx_helper_get_interface_index_num(ipd_port);
274 union cvmx_asxx_prt_loop asxx_prt_loop;
275
276 asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
277 if (asxx_prt_loop.s.int_loop & (1 << index)) {
278 /* Force 1Gbps full duplex on internal loopback */
279 cvmx_helper_link_info_t result;
280 result.u64 = 0;
281 result.s.full_duplex = 1;
282 result.s.link_up = 1;
283 result.s.speed = 1000;
284 return result;
285 } else
286 return __cvmx_helper_board_link_get(ipd_port);
287}
288
289/**
290 * Configure an IPD/PKO port for the specified link state. This
291 * function does not influence auto negotiation at the PHY level.
292 * The passed link state must always match the link state returned
293 * by cvmx_helper_link_get(). It is normally best to use
294 * cvmx_helper_link_autoconf() instead.
295 *
296 * @ipd_port: IPD/PKO port to configure
297 * @link_info: The new link state
298 *
299 * Returns Zero on success, negative on failure
300 */
301int __cvmx_helper_rgmii_link_set(int ipd_port,
302 cvmx_helper_link_info_t link_info)
303{
304 int result = 0;
305 int interface = cvmx_helper_get_interface_num(ipd_port);
306 int index = cvmx_helper_get_interface_index_num(ipd_port);
307 union cvmx_gmxx_prtx_cfg original_gmx_cfg;
308 union cvmx_gmxx_prtx_cfg new_gmx_cfg;
309 union cvmx_pko_mem_queue_qos pko_mem_queue_qos;
310 union cvmx_pko_mem_queue_qos pko_mem_queue_qos_save[16];
311 union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp;
312 union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp_save;
313 int i;
314
315 /* Ignore speed sets in the simulator */
316 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
317 return 0;
318
319 /* Read the current settings so we know the current enable state */
320 original_gmx_cfg.u64 =
321 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
322 new_gmx_cfg = original_gmx_cfg;
323
324 /* Disable the lowest level RX */
325 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
326 cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) &
327 ~(1 << index));
328
329 memset(pko_mem_queue_qos_save, 0, sizeof(pko_mem_queue_qos_save));
330 /* Disable all queues so that TX should become idle */
331 for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
332 int queue = cvmx_pko_get_base_queue(ipd_port) + i;
333 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
334 pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS);
335 pko_mem_queue_qos.s.pid = ipd_port;
336 pko_mem_queue_qos.s.qid = queue;
337 pko_mem_queue_qos_save[i] = pko_mem_queue_qos;
338 pko_mem_queue_qos.s.qos_mask = 0;
339 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64);
340 }
341
342 /* Disable backpressure */
343 gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
344 gmx_tx_ovr_bp_save = gmx_tx_ovr_bp;
345 gmx_tx_ovr_bp.s.bp &= ~(1 << index);
346 gmx_tx_ovr_bp.s.en |= 1 << index;
347 cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);
348 cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
349
350 /*
351 * Poll the GMX state machine waiting for it to become
352 * idle. Preferably we should only change speed when it is
353 * idle. If it doesn't become idle we will still do the speed
354 * change, but there is a slight chance that GMX will
355 * lockup.
356 */
357 cvmx_write_csr(CVMX_NPI_DBG_SELECT,
358 interface * 0x800 + index * 0x100 + 0x880);
359 CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7,
360 ==, 0, 10000);
361 CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 0xf,
362 ==, 0, 10000);
363
364 /* Disable the port before we make any changes */
365 new_gmx_cfg.s.en = 0;
366 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
367 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
368
369 /* Set full/half duplex */
370 if (cvmx_octeon_is_pass1())
371 /* Half duplex is broken for 38XX Pass 1 */
372 new_gmx_cfg.s.duplex = 1;
373 else if (!link_info.s.link_up)
374 /* Force full duplex on down links */
375 new_gmx_cfg.s.duplex = 1;
376 else
377 new_gmx_cfg.s.duplex = link_info.s.full_duplex;
378
379 /* Set the link speed. Anything unknown is set to 1Gbps */
380 if (link_info.s.speed == 10) {
381 new_gmx_cfg.s.slottime = 0;
382 new_gmx_cfg.s.speed = 0;
383 } else if (link_info.s.speed == 100) {
384 new_gmx_cfg.s.slottime = 0;
385 new_gmx_cfg.s.speed = 0;
386 } else {
387 new_gmx_cfg.s.slottime = 1;
388 new_gmx_cfg.s.speed = 1;
389 }
390
391 /* Adjust the clocks */
392 if (link_info.s.speed == 10) {
393 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50);
394 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
395 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
396 } else if (link_info.s.speed == 100) {
397 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5);
398 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
399 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
400 } else {
401 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
402 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
403 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
404 }
405
406 if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
407 if ((link_info.s.speed == 10) || (link_info.s.speed == 100)) {
408 union cvmx_gmxx_inf_mode mode;
409 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
410
411 /*
412 * Port .en .type .p0mii Configuration
413 * ---- --- ----- ------ -----------------------------------------
414 * X 0 X X All links are disabled.
415 * 0 1 X 0 Port 0 is RGMII
416 * 0 1 X 1 Port 0 is MII
417 * 1 1 0 X Ports 1 and 2 are configured as RGMII ports.
418 * 1 1 1 X Port 1: GMII/MII; Port 2: disabled. GMII or
419 * MII port is selected by GMX_PRT1_CFG[SPEED].
420 */
421
422 /* In MII mode, CLK_CNT = 1. */
423 if (((index == 0) && (mode.s.p0mii == 1))
424 || ((index != 0) && (mode.s.type == 1))) {
425 cvmx_write_csr(CVMX_GMXX_TXX_CLK
426 (index, interface), 1);
427 }
428 }
429 }
430
431 /* Do a read to make sure all setup stuff is complete */
432 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
433
434 /* Save the new GMX setting without enabling the port */
435 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
436
437 /* Enable the lowest level RX */
438 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
439 cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1 <<
440 index));
441
442 /* Re-enable the TX path */
443 for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
444 int queue = cvmx_pko_get_base_queue(ipd_port) + i;
445 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
446 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS,
447 pko_mem_queue_qos_save[i].u64);
448 }
449
450 /* Restore backpressure */
451 cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64);
452
453 /* Restore the GMX enable state. Port config is complete */
454 new_gmx_cfg.s.en = original_gmx_cfg.s.en;
455 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
456
457 return result;
458}
459
460/**
461 * Configure a port for internal and/or external loopback. Internal loopback
462 * causes packets sent by the port to be received by Octeon. External loopback
463 * causes packets received from the wire to sent out again.
464 *
465 * @ipd_port: IPD/PKO port to loopback.
466 * @enable_internal:
467 * Non zero if you want internal loopback
468 * @enable_external:
469 * Non zero if you want external loopback
470 *
471 * Returns Zero on success, negative on failure.
472 */
473int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal,
474 int enable_external)
475{
476 int interface = cvmx_helper_get_interface_num(ipd_port);
477 int index = cvmx_helper_get_interface_index_num(ipd_port);
478 int original_enable;
479 union cvmx_gmxx_prtx_cfg gmx_cfg;
480 union cvmx_asxx_prt_loop asxx_prt_loop;
481
482 /* Read the current enable state and save it */
483 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
484 original_enable = gmx_cfg.s.en;
485 /* Force port to be disabled */
486 gmx_cfg.s.en = 0;
487 if (enable_internal) {
488 /* Force speed if we're doing internal loopback */
489 gmx_cfg.s.duplex = 1;
490 gmx_cfg.s.slottime = 1;
491 gmx_cfg.s.speed = 1;
492 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
493 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
494 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
495 }
496 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
497
498 /* Set the loopback bits */
499 asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
500 if (enable_internal)
501 asxx_prt_loop.s.int_loop |= 1 << index;
502 else
503 asxx_prt_loop.s.int_loop &= ~(1 << index);
504 if (enable_external)
505 asxx_prt_loop.s.ext_loop |= 1 << index;
506 else
507 asxx_prt_loop.s.ext_loop &= ~(1 << index);
508 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), asxx_prt_loop.u64);
509
510 /* Force enables in internal loopback */
511 if (enable_internal) {
512 uint64_t tmp;
513 tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
514 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface),
515 (1 << index) | tmp);
516 tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
517 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
518 (1 << index) | tmp);
519 original_enable = 1;
520 }
521
522 /* Restore the enable state */
523 gmx_cfg.s.en = original_enable;
524 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
525 return 0;
526}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
new file mode 100644
index 000000000000..0c0bf5d30e70
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
@@ -0,0 +1,554 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Functions for SGMII initialization, configuration,
30 * and monitoring.
31 */
32
33#include <asm/octeon/octeon.h>
34
35#include <asm/octeon/cvmx-config.h>
36
37#include <asm/octeon/cvmx-mdio.h>
38#include <asm/octeon/cvmx-helper.h>
39#include <asm/octeon/cvmx-helper-board.h>
40
41#include <asm/octeon/cvmx-gmxx-defs.h>
42#include <asm/octeon/cvmx-pcsx-defs.h>
43
44void __cvmx_interrupt_gmxx_enable(int interface);
45void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
46void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
47
48/**
49 * Perform initialization required only once for an SGMII port.
50 *
51 * @interface: Interface to init
52 * @index: Index of prot on the interface
53 *
54 * Returns Zero on success, negative on failure
55 */
56static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
57{
58 const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
59 union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg;
60 union cvmx_pcsx_linkx_timer_count_reg pcsx_linkx_timer_count_reg;
61 union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
62
63 /* Disable GMX */
64 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
65 gmxx_prtx_cfg.s.en = 0;
66 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
67
68 /*
69 * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the
70 * appropriate value. 1000BASE-X specifies a 10ms
71 * interval. SGMII specifies a 1.6ms interval.
72 */
73 pcs_misc_ctl_reg.u64 =
74 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
75 pcsx_linkx_timer_count_reg.u64 =
76 cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface));
77 if (pcs_misc_ctl_reg.s.mode) {
78 /* 1000BASE-X */
79 pcsx_linkx_timer_count_reg.s.count =
80 (10000ull * clock_mhz) >> 10;
81 } else {
82 /* SGMII */
83 pcsx_linkx_timer_count_reg.s.count =
84 (1600ull * clock_mhz) >> 10;
85 }
86 cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface),
87 pcsx_linkx_timer_count_reg.u64);
88
89 /*
90 * Write the advertisement register to be used as the
91 * tx_Config_Reg<D15:D0> of the autonegotiation. In
92 * 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG.
93 * In SGMII PHY mode, tx_Config_Reg<D15:D0> is
94 * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode,
95 * tx_Config_Reg<D15:D0> is the fixed value 0x4001, so this
96 * step can be skipped.
97 */
98 if (pcs_misc_ctl_reg.s.mode) {
99 /* 1000BASE-X */
100 union cvmx_pcsx_anx_adv_reg pcsx_anx_adv_reg;
101 pcsx_anx_adv_reg.u64 =
102 cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface));
103 pcsx_anx_adv_reg.s.rem_flt = 0;
104 pcsx_anx_adv_reg.s.pause = 3;
105 pcsx_anx_adv_reg.s.hfd = 1;
106 pcsx_anx_adv_reg.s.fd = 1;
107 cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface),
108 pcsx_anx_adv_reg.u64);
109 } else {
110 union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
111 pcsx_miscx_ctl_reg.u64 =
112 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
113 if (pcsx_miscx_ctl_reg.s.mac_phy) {
114 /* PHY Mode */
115 union cvmx_pcsx_sgmx_an_adv_reg pcsx_sgmx_an_adv_reg;
116 pcsx_sgmx_an_adv_reg.u64 =
117 cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG
118 (index, interface));
119 pcsx_sgmx_an_adv_reg.s.link = 1;
120 pcsx_sgmx_an_adv_reg.s.dup = 1;
121 pcsx_sgmx_an_adv_reg.s.speed = 2;
122 cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG
123 (index, interface),
124 pcsx_sgmx_an_adv_reg.u64);
125 } else {
126 /* MAC Mode - Nothing to do */
127 }
128 }
129 return 0;
130}
131
132/**
133 * Initialize the SERTES link for the first time or after a loss
134 * of link.
135 *
136 * @interface: Interface to init
137 * @index: Index of prot on the interface
138 *
139 * Returns Zero on success, negative on failure
140 */
141static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index)
142{
143 union cvmx_pcsx_mrx_control_reg control_reg;
144
145 /*
146 * Take PCS through a reset sequence.
147 * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero.
148 * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the
149 * value of the other PCS*_MR*_CONTROL_REG bits). Read
150 * PCS*_MR*_CONTROL_REG[RESET] until it changes value to
151 * zero.
152 */
153 control_reg.u64 =
154 cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
155 if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
156 control_reg.s.reset = 1;
157 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
158 control_reg.u64);
159 if (CVMX_WAIT_FOR_FIELD64
160 (CVMX_PCSX_MRX_CONTROL_REG(index, interface),
161 union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) {
162 cvmx_dprintf("SGMII%d: Timeout waiting for port %d "
163 "to finish reset\n",
164 interface, index);
165 return -1;
166 }
167 }
168
169 /*
170 * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh
171 * sgmii negotiation starts.
172 */
173 control_reg.s.rst_an = 1;
174 control_reg.s.an_en = 1;
175 control_reg.s.pwr_dn = 0;
176 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
177 control_reg.u64);
178
179 /*
180 * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating
181 * that sgmii autonegotiation is complete. In MAC mode this
182 * isn't an ethernet link, but a link between Octeon and the
183 * PHY.
184 */
185 if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
186 CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface),
187 union cvmx_pcsx_mrx_status_reg, an_cpt, ==, 1,
188 10000)) {
189 /* cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); */
190 return -1;
191 }
192 return 0;
193}
194
195/**
196 * Configure an SGMII link to the specified speed after the SERTES
197 * link is up.
198 *
199 * @interface: Interface to init
200 * @index: Index of prot on the interface
201 * @link_info: Link state to configure
202 *
203 * Returns Zero on success, negative on failure
204 */
205static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface,
206 int index,
207 cvmx_helper_link_info_t
208 link_info)
209{
210 int is_enabled;
211 union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
212 union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
213
214 /* Disable GMX before we make any changes. Remember the enable state */
215 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
216 is_enabled = gmxx_prtx_cfg.s.en;
217 gmxx_prtx_cfg.s.en = 0;
218 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
219
220 /* Wait for GMX to be idle */
221 if (CVMX_WAIT_FOR_FIELD64
222 (CVMX_GMXX_PRTX_CFG(index, interface), union cvmx_gmxx_prtx_cfg,
223 rx_idle, ==, 1, 10000)
224 || CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface),
225 union cvmx_gmxx_prtx_cfg, tx_idle, ==, 1,
226 10000)) {
227 cvmx_dprintf
228 ("SGMII%d: Timeout waiting for port %d to be idle\n",
229 interface, index);
230 return -1;
231 }
232
233 /* Read GMX CFG again to make sure the disable completed */
234 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
235
236 /*
237 * Get the misc control for PCS. We will need to set the
238 * duplication amount.
239 */
240 pcsx_miscx_ctl_reg.u64 =
241 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
242
243 /*
244 * Use GMXENO to force the link down if the status we get says
245 * it should be down.
246 */
247 pcsx_miscx_ctl_reg.s.gmxeno = !link_info.s.link_up;
248
249 /* Only change the duplex setting if the link is up */
250 if (link_info.s.link_up)
251 gmxx_prtx_cfg.s.duplex = link_info.s.full_duplex;
252
253 /* Do speed based setting for GMX */
254 switch (link_info.s.speed) {
255 case 10:
256 gmxx_prtx_cfg.s.speed = 0;
257 gmxx_prtx_cfg.s.speed_msb = 1;
258 gmxx_prtx_cfg.s.slottime = 0;
259 /* Setting from GMX-603 */
260 pcsx_miscx_ctl_reg.s.samp_pt = 25;
261 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
262 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
263 break;
264 case 100:
265 gmxx_prtx_cfg.s.speed = 0;
266 gmxx_prtx_cfg.s.speed_msb = 0;
267 gmxx_prtx_cfg.s.slottime = 0;
268 pcsx_miscx_ctl_reg.s.samp_pt = 0x5;
269 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
270 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
271 break;
272 case 1000:
273 gmxx_prtx_cfg.s.speed = 1;
274 gmxx_prtx_cfg.s.speed_msb = 0;
275 gmxx_prtx_cfg.s.slottime = 1;
276 pcsx_miscx_ctl_reg.s.samp_pt = 1;
277 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512);
278 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192);
279 break;
280 default:
281 break;
282 }
283
284 /* Write the new misc control for PCS */
285 cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
286 pcsx_miscx_ctl_reg.u64);
287
288 /* Write the new GMX settings with the port still disabled */
289 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
290
291 /* Read GMX CFG again to make sure the config completed */
292 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
293
294 /* Restore the enabled / disabled state */
295 gmxx_prtx_cfg.s.en = is_enabled;
296 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
297
298 return 0;
299}
300
301/**
302 * Bring up the SGMII interface to be ready for packet I/O but
303 * leave I/O disabled using the GMX override. This function
304 * follows the bringup documented in 10.6.3 of the manual.
305 *
306 * @interface: Interface to bringup
307 * @num_ports: Number of ports on the interface
308 *
309 * Returns Zero on success, negative on failure
310 */
311static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports)
312{
313 int index;
314
315 __cvmx_helper_setup_gmx(interface, num_ports);
316
317 for (index = 0; index < num_ports; index++) {
318 int ipd_port = cvmx_helper_get_ipd_port(interface, index);
319 __cvmx_helper_sgmii_hardware_init_one_time(interface, index);
320 __cvmx_helper_sgmii_link_set(ipd_port,
321 __cvmx_helper_sgmii_link_get
322 (ipd_port));
323
324 }
325
326 return 0;
327}
328
329int __cvmx_helper_sgmii_enumerate(int interface)
330{
331 return 4;
332}
333/**
334 * Probe a SGMII interface and determine the number of ports
335 * connected to it. The SGMII interface should still be down after
336 * this call.
337 *
338 * @interface: Interface to probe
339 *
340 * Returns Number of ports on the interface. Zero to disable.
341 */
342int __cvmx_helper_sgmii_probe(int interface)
343{
344 union cvmx_gmxx_inf_mode mode;
345
346 /*
347 * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
348 * interface needs to be enabled before IPD otherwise per port
349 * backpressure may not work properly
350 */
351 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
352 mode.s.en = 1;
353 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
354 return __cvmx_helper_sgmii_enumerate(interface);
355}
356
357/**
358 * Bringup and enable a SGMII interface. After this call packet
359 * I/O should be fully functional. This is called with IPD
360 * enabled but PKO disabled.
361 *
362 * @interface: Interface to bring up
363 *
364 * Returns Zero on success, negative on failure
365 */
366int __cvmx_helper_sgmii_enable(int interface)
367{
368 int num_ports = cvmx_helper_ports_on_interface(interface);
369 int index;
370
371 __cvmx_helper_sgmii_hardware_init(interface, num_ports);
372
373 for (index = 0; index < num_ports; index++) {
374 union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
375 gmxx_prtx_cfg.u64 =
376 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
377 gmxx_prtx_cfg.s.en = 1;
378 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
379 gmxx_prtx_cfg.u64);
380 __cvmx_interrupt_pcsx_intx_en_reg_enable(index, interface);
381 }
382 __cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
383 __cvmx_interrupt_gmxx_enable(interface);
384 return 0;
385}
386
387/**
388 * Return the link state of an IPD/PKO port as returned by
389 * auto negotiation. The result of this function may not match
390 * Octeon's link config if auto negotiation has changed since
391 * the last call to cvmx_helper_link_set().
392 *
393 * @ipd_port: IPD/PKO port to query
394 *
395 * Returns Link state
396 */
397cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port)
398{
399 cvmx_helper_link_info_t result;
400 union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg;
401 int interface = cvmx_helper_get_interface_num(ipd_port);
402 int index = cvmx_helper_get_interface_index_num(ipd_port);
403 union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg;
404
405 result.u64 = 0;
406
407 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) {
408 /* The simulator gives you a simulated 1Gbps full duplex link */
409 result.s.link_up = 1;
410 result.s.full_duplex = 1;
411 result.s.speed = 1000;
412 return result;
413 }
414
415 pcsx_mrx_control_reg.u64 =
416 cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
417 if (pcsx_mrx_control_reg.s.loopbck1) {
418 /* Force 1Gbps full duplex link for internal loopback */
419 result.s.link_up = 1;
420 result.s.full_duplex = 1;
421 result.s.speed = 1000;
422 return result;
423 }
424
425 pcs_misc_ctl_reg.u64 =
426 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
427 if (pcs_misc_ctl_reg.s.mode) {
428 /* 1000BASE-X */
429 /* FIXME */
430 } else {
431 union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
432 pcsx_miscx_ctl_reg.u64 =
433 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
434 if (pcsx_miscx_ctl_reg.s.mac_phy) {
435 /* PHY Mode */
436 union cvmx_pcsx_mrx_status_reg pcsx_mrx_status_reg;
437 union cvmx_pcsx_anx_results_reg pcsx_anx_results_reg;
438
439 /*
440 * Don't bother continuing if the SERTES low
441 * level link is down
442 */
443 pcsx_mrx_status_reg.u64 =
444 cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG
445 (index, interface));
446 if (pcsx_mrx_status_reg.s.lnk_st == 0) {
447 if (__cvmx_helper_sgmii_hardware_init_link
448 (interface, index) != 0)
449 return result;
450 }
451
452 /* Read the autoneg results */
453 pcsx_anx_results_reg.u64 =
454 cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG
455 (index, interface));
456 if (pcsx_anx_results_reg.s.an_cpt) {
457 /*
458 * Auto negotiation is complete. Set
459 * status accordingly.
460 */
461 result.s.full_duplex =
462 pcsx_anx_results_reg.s.dup;
463 result.s.link_up =
464 pcsx_anx_results_reg.s.link_ok;
465 switch (pcsx_anx_results_reg.s.spd) {
466 case 0:
467 result.s.speed = 10;
468 break;
469 case 1:
470 result.s.speed = 100;
471 break;
472 case 2:
473 result.s.speed = 1000;
474 break;
475 default:
476 result.s.speed = 0;
477 result.s.link_up = 0;
478 break;
479 }
480 } else {
481 /*
482 * Auto negotiation isn't
483 * complete. Return link down.
484 */
485 result.s.speed = 0;
486 result.s.link_up = 0;
487 }
488 } else { /* MAC Mode */
489
490 result = __cvmx_helper_board_link_get(ipd_port);
491 }
492 }
493 return result;
494}
495
496/**
497 * Configure an IPD/PKO port for the specified link state. This
498 * function does not influence auto negotiation at the PHY level.
499 * The passed link state must always match the link state returned
500 * by cvmx_helper_link_get(). It is normally best to use
501 * cvmx_helper_link_autoconf() instead.
502 *
503 * @ipd_port: IPD/PKO port to configure
504 * @link_info: The new link state
505 *
506 * Returns Zero on success, negative on failure
507 */
508int __cvmx_helper_sgmii_link_set(int ipd_port,
509 cvmx_helper_link_info_t link_info)
510{
511 int interface = cvmx_helper_get_interface_num(ipd_port);
512 int index = cvmx_helper_get_interface_index_num(ipd_port);
513 __cvmx_helper_sgmii_hardware_init_link(interface, index);
514 return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index,
515 link_info);
516}
517
518/**
519 * Configure a port for internal and/or external loopback. Internal
520 * loopback causes packets sent by the port to be received by
521 * Octeon. External loopback causes packets received from the wire to
522 * sent out again.
523 *
524 * @ipd_port: IPD/PKO port to loopback.
525 * @enable_internal:
526 * Non zero if you want internal loopback
527 * @enable_external:
528 * Non zero if you want external loopback
529 *
530 * Returns Zero on success, negative on failure.
531 */
532int __cvmx_helper_sgmii_configure_loopback(int ipd_port, int enable_internal,
533 int enable_external)
534{
535 int interface = cvmx_helper_get_interface_num(ipd_port);
536 int index = cvmx_helper_get_interface_index_num(ipd_port);
537 union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg;
538 union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
539
540 pcsx_mrx_control_reg.u64 =
541 cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
542 pcsx_mrx_control_reg.s.loopbck1 = enable_internal;
543 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
544 pcsx_mrx_control_reg.u64);
545
546 pcsx_miscx_ctl_reg.u64 =
547 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
548 pcsx_miscx_ctl_reg.s.loopbck2 = enable_external;
549 cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
550 pcsx_miscx_ctl_reg.u64);
551
552 __cvmx_helper_sgmii_hardware_init_link(interface, index);
553 return 0;
554}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
new file mode 100644
index 000000000000..2830e4bdf7f3
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
@@ -0,0 +1,205 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28void __cvmx_interrupt_gmxx_enable(int interface);
29void __cvmx_interrupt_spxx_int_msk_enable(int index);
30void __cvmx_interrupt_stxx_int_msk_enable(int index);
31
32/*
33 * Functions for SPI initialization, configuration,
34 * and monitoring.
35 */
36#include <asm/octeon/octeon.h>
37
38#include <asm/octeon/cvmx-config.h>
39#include <asm/octeon/cvmx-spi.h>
40#include <asm/octeon/cvmx-helper.h>
41
42#include <asm/octeon/cvmx-pip-defs.h>
43#include <asm/octeon/cvmx-pko-defs.h>
44
45/*
46 * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI
47 * initialization routines wait for SPI training. You can override the
48 * value using executive-config.h if necessary.
49 */
50#ifndef CVMX_HELPER_SPI_TIMEOUT
51#define CVMX_HELPER_SPI_TIMEOUT 10
52#endif
53
54int __cvmx_helper_spi_enumerate(int interface)
55{
56 if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
57 cvmx_spi4000_is_present(interface)) {
58 return 10;
59 } else {
60 return 16;
61 }
62}
63
64/**
65 * Probe a SPI interface and determine the number of ports
66 * connected to it. The SPI interface should still be down after
67 * this call.
68 *
69 * @interface: Interface to probe
70 *
71 * Returns Number of ports on the interface. Zero to disable.
72 */
73int __cvmx_helper_spi_probe(int interface)
74{
75 int num_ports = 0;
76
77 if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
78 cvmx_spi4000_is_present(interface)) {
79 num_ports = 10;
80 } else {
81 union cvmx_pko_reg_crc_enable enable;
82 num_ports = 16;
83 /*
84 * Unlike the SPI4000, most SPI devices don't
85 * automatically put on the L2 CRC. For everything
86 * except for the SPI4000 have PKO append the L2 CRC
87 * to the packet.
88 */
89 enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE);
90 enable.s.enable |= 0xffff << (interface * 16);
91 cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64);
92 }
93 __cvmx_helper_setup_gmx(interface, num_ports);
94 return num_ports;
95}
96
97/**
98 * Bringup and enable a SPI interface. After this call packet I/O
99 * should be fully functional. This is called with IPD enabled but
100 * PKO disabled.
101 *
102 * @interface: Interface to bring up
103 *
104 * Returns Zero on success, negative on failure
105 */
106int __cvmx_helper_spi_enable(int interface)
107{
108 /*
109 * Normally the ethernet L2 CRC is checked and stripped in the
110 * GMX block. When you are using SPI, this isn' the case and
111 * IPD needs to check the L2 CRC.
112 */
113 int num_ports = cvmx_helper_ports_on_interface(interface);
114 int ipd_port;
115 for (ipd_port = interface * 16; ipd_port < interface * 16 + num_ports;
116 ipd_port++) {
117 union cvmx_pip_prt_cfgx port_config;
118 port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
119 port_config.s.crc_en = 1;
120 cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64);
121 }
122
123 if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
124 cvmx_spi_start_interface(interface, CVMX_SPI_MODE_DUPLEX,
125 CVMX_HELPER_SPI_TIMEOUT, num_ports);
126 if (cvmx_spi4000_is_present(interface))
127 cvmx_spi4000_initialize(interface);
128 }
129 __cvmx_interrupt_spxx_int_msk_enable(interface);
130 __cvmx_interrupt_stxx_int_msk_enable(interface);
131 __cvmx_interrupt_gmxx_enable(interface);
132 return 0;
133}
134
135/**
136 * Return the link state of an IPD/PKO port as returned by
137 * auto negotiation. The result of this function may not match
138 * Octeon's link config if auto negotiation has changed since
139 * the last call to cvmx_helper_link_set().
140 *
141 * @ipd_port: IPD/PKO port to query
142 *
143 * Returns Link state
144 */
145cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port)
146{
147 cvmx_helper_link_info_t result;
148 int interface = cvmx_helper_get_interface_num(ipd_port);
149 int index = cvmx_helper_get_interface_index_num(ipd_port);
150 result.u64 = 0;
151
152 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) {
153 /* The simulator gives you a simulated full duplex link */
154 result.s.link_up = 1;
155 result.s.full_duplex = 1;
156 result.s.speed = 10000;
157 } else if (cvmx_spi4000_is_present(interface)) {
158 union cvmx_gmxx_rxx_rx_inbnd inband =
159 cvmx_spi4000_check_speed(interface, index);
160 result.s.link_up = inband.s.status;
161 result.s.full_duplex = inband.s.duplex;
162 switch (inband.s.speed) {
163 case 0: /* 10 Mbps */
164 result.s.speed = 10;
165 break;
166 case 1: /* 100 Mbps */
167 result.s.speed = 100;
168 break;
169 case 2: /* 1 Gbps */
170 result.s.speed = 1000;
171 break;
172 case 3: /* Illegal */
173 result.s.speed = 0;
174 result.s.link_up = 0;
175 break;
176 }
177 } else {
178 /* For generic SPI we can't determine the link, just return some
179 sane results */
180 result.s.link_up = 1;
181 result.s.full_duplex = 1;
182 result.s.speed = 10000;
183 }
184 return result;
185}
186
187/**
188 * Configure an IPD/PKO port for the specified link state. This
189 * function does not influence auto negotiation at the PHY level.
190 * The passed link state must always match the link state returned
191 * by cvmx_helper_link_get(). It is normally best to use
192 * cvmx_helper_link_autoconf() instead.
193 *
194 * @ipd_port: IPD/PKO port to configure
195 * @link_info: The new link state
196 *
197 * Returns Zero on success, negative on failure
198 */
199int __cvmx_helper_spi_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
200{
201 /* Nothing to do. If we have a SPI4000 then the setup was already performed
202 by cvmx_spi4000_check_speed(). If not then there isn't any link
203 info */
204 return 0;
205}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
new file mode 100644
index 000000000000..116dea17acf5
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
@@ -0,0 +1,433 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Small helper utilities.
30 */
31#include <linux/kernel.h>
32
33#include <asm/octeon/octeon.h>
34
35#include <asm/octeon/cvmx-config.h>
36
37#include <asm/octeon/cvmx-fpa.h>
38#include <asm/octeon/cvmx-pip.h>
39#include <asm/octeon/cvmx-pko.h>
40#include <asm/octeon/cvmx-ipd.h>
41#include <asm/octeon/cvmx-spi.h>
42
43#include <asm/octeon/cvmx-helper.h>
44#include <asm/octeon/cvmx-helper-util.h>
45
46#include <asm/octeon/cvmx-ipd-defs.h>
47
48/**
49 * Convert a interface mode into a human readable string
50 *
51 * @mode: Mode to convert
52 *
53 * Returns String
54 */
55const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t
56 mode)
57{
58 switch (mode) {
59 case CVMX_HELPER_INTERFACE_MODE_DISABLED:
60 return "DISABLED";
61 case CVMX_HELPER_INTERFACE_MODE_RGMII:
62 return "RGMII";
63 case CVMX_HELPER_INTERFACE_MODE_GMII:
64 return "GMII";
65 case CVMX_HELPER_INTERFACE_MODE_SPI:
66 return "SPI";
67 case CVMX_HELPER_INTERFACE_MODE_PCIE:
68 return "PCIE";
69 case CVMX_HELPER_INTERFACE_MODE_XAUI:
70 return "XAUI";
71 case CVMX_HELPER_INTERFACE_MODE_SGMII:
72 return "SGMII";
73 case CVMX_HELPER_INTERFACE_MODE_PICMG:
74 return "PICMG";
75 case CVMX_HELPER_INTERFACE_MODE_NPI:
76 return "NPI";
77 case CVMX_HELPER_INTERFACE_MODE_LOOP:
78 return "LOOP";
79 }
80 return "UNKNOWN";
81}
82
83/**
84 * Debug routine to dump the packet structure to the console
85 *
86 * @work: Work queue entry containing the packet to dump
87 * Returns
88 */
89int cvmx_helper_dump_packet(cvmx_wqe_t *work)
90{
91 uint64_t count;
92 uint64_t remaining_bytes;
93 union cvmx_buf_ptr buffer_ptr;
94 uint64_t start_of_buffer;
95 uint8_t *data_address;
96 uint8_t *end_of_data;
97
98 cvmx_dprintf("Packet Length: %u\n", work->len);
99 cvmx_dprintf(" Input Port: %u\n", work->ipprt);
100 cvmx_dprintf(" QoS: %u\n", work->qos);
101 cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs);
102
103 if (work->word2.s.bufs == 0) {
104 union cvmx_ipd_wqe_fpa_queue wqe_pool;
105 wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE);
106 buffer_ptr.u64 = 0;
107 buffer_ptr.s.pool = wqe_pool.s.wqe_pool;
108 buffer_ptr.s.size = 128;
109 buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data);
110 if (likely(!work->word2.s.not_IP)) {
111 union cvmx_pip_ip_offset pip_ip_offset;
112 pip_ip_offset.u64 = cvmx_read_csr(CVMX_PIP_IP_OFFSET);
113 buffer_ptr.s.addr +=
114 (pip_ip_offset.s.offset << 3) -
115 work->word2.s.ip_offset;
116 buffer_ptr.s.addr += (work->word2.s.is_v6 ^ 1) << 2;
117 } else {
118 /*
119 * WARNING: This code assumes that the packet
120 * is not RAW. If it was, we would use
121 * PIP_GBL_CFG[RAW_SHF] instead of
122 * PIP_GBL_CFG[NIP_SHF].
123 */
124 union cvmx_pip_gbl_cfg pip_gbl_cfg;
125 pip_gbl_cfg.u64 = cvmx_read_csr(CVMX_PIP_GBL_CFG);
126 buffer_ptr.s.addr += pip_gbl_cfg.s.nip_shf;
127 }
128 } else
129 buffer_ptr = work->packet_ptr;
130 remaining_bytes = work->len;
131
132 while (remaining_bytes) {
133 start_of_buffer =
134 ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
135 cvmx_dprintf(" Buffer Start:%llx\n",
136 (unsigned long long)start_of_buffer);
137 cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i);
138 cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back);
139 cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool);
140 cvmx_dprintf(" Buffer Data: %llx\n",
141 (unsigned long long)buffer_ptr.s.addr);
142 cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size);
143
144 cvmx_dprintf("\t\t");
145 data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr);
146 end_of_data = data_address + buffer_ptr.s.size;
147 count = 0;
148 while (data_address < end_of_data) {
149 if (remaining_bytes == 0)
150 break;
151 else
152 remaining_bytes--;
153 cvmx_dprintf("%02x", (unsigned int)*data_address);
154 data_address++;
155 if (remaining_bytes && (count == 7)) {
156 cvmx_dprintf("\n\t\t");
157 count = 0;
158 } else
159 count++;
160 }
161 cvmx_dprintf("\n");
162
163 if (remaining_bytes)
164 buffer_ptr = *(union cvmx_buf_ptr *)
165 cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
166 }
167 return 0;
168}
169
170/**
171 * Setup Random Early Drop on a specific input queue
172 *
173 * @queue: Input queue to setup RED on (0-7)
174 * @pass_thresh:
175 * Packets will begin slowly dropping when there are less than
176 * this many packet buffers free in FPA 0.
177 * @drop_thresh:
178 * All incomming packets will be dropped when there are less
179 * than this many free packet buffers in FPA 0.
180 * Returns Zero on success. Negative on failure
181 */
182int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
183{
184 union cvmx_ipd_qosx_red_marks red_marks;
185 union cvmx_ipd_red_quex_param red_param;
186
187 /* Set RED to begin dropping packets when there are pass_thresh buffers
188 left. It will linearly drop more packets until reaching drop_thresh
189 buffers */
190 red_marks.u64 = 0;
191 red_marks.s.drop = drop_thresh;
192 red_marks.s.pass = pass_thresh;
193 cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64);
194
195 /* Use the actual queue 0 counter, not the average */
196 red_param.u64 = 0;
197 red_param.s.prb_con =
198 (255ul << 24) / (red_marks.s.pass - red_marks.s.drop);
199 red_param.s.avg_con = 1;
200 red_param.s.new_con = 255;
201 red_param.s.use_pcnt = 1;
202 cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64);
203 return 0;
204}
205
206/**
207 * Setup Random Early Drop to automatically begin dropping packets.
208 *
209 * @pass_thresh:
210 * Packets will begin slowly dropping when there are less than
211 * this many packet buffers free in FPA 0.
212 * @drop_thresh:
213 * All incomming packets will be dropped when there are less
214 * than this many free packet buffers in FPA 0.
215 * Returns Zero on success. Negative on failure
216 */
217int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
218{
219 union cvmx_ipd_portx_bp_page_cnt page_cnt;
220 union cvmx_ipd_bp_prt_red_end ipd_bp_prt_red_end;
221 union cvmx_ipd_red_port_enable red_port_enable;
222 int queue;
223 int interface;
224 int port;
225
226 /* Disable backpressure based on queued buffers. It needs SW support */
227 page_cnt.u64 = 0;
228 page_cnt.s.bp_enb = 0;
229 page_cnt.s.page_cnt = 100;
230 for (interface = 0; interface < 2; interface++) {
231 for (port = cvmx_helper_get_first_ipd_port(interface);
232 port < cvmx_helper_get_last_ipd_port(interface); port++)
233 cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port),
234 page_cnt.u64);
235 }
236
237 for (queue = 0; queue < 8; queue++)
238 cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh);
239
240 /* Shutoff the dropping based on the per port page count. SW isn't
241 decrementing it right now */
242 ipd_bp_prt_red_end.u64 = 0;
243 ipd_bp_prt_red_end.s.prt_enb = 0;
244 cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64);
245
246 red_port_enable.u64 = 0;
247 red_port_enable.s.prt_enb = 0xfffffffffull;
248 red_port_enable.s.avg_dly = 10000;
249 red_port_enable.s.prb_dly = 10000;
250 cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);
251
252 return 0;
253}
254
255/**
256 * Setup the common GMX settings that determine the number of
257 * ports. These setting apply to almost all configurations of all
258 * chips.
259 *
260 * @interface: Interface to configure
261 * @num_ports: Number of ports on the interface
262 *
263 * Returns Zero on success, negative on failure
264 */
265int __cvmx_helper_setup_gmx(int interface, int num_ports)
266{
267 union cvmx_gmxx_tx_prts gmx_tx_prts;
268 union cvmx_gmxx_rx_prts gmx_rx_prts;
269 union cvmx_pko_reg_gmx_port_mode pko_mode;
270 union cvmx_gmxx_txx_thresh gmx_tx_thresh;
271 int index;
272
273 /* Tell GMX the number of TX ports on this interface */
274 gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface));
275 gmx_tx_prts.s.prts = num_ports;
276 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64);
277
278 /* Tell GMX the number of RX ports on this interface. This only
279 ** applies to *GMII and XAUI ports */
280 if (cvmx_helper_interface_get_mode(interface) ==
281 CVMX_HELPER_INTERFACE_MODE_RGMII
282 || cvmx_helper_interface_get_mode(interface) ==
283 CVMX_HELPER_INTERFACE_MODE_SGMII
284 || cvmx_helper_interface_get_mode(interface) ==
285 CVMX_HELPER_INTERFACE_MODE_GMII
286 || cvmx_helper_interface_get_mode(interface) ==
287 CVMX_HELPER_INTERFACE_MODE_XAUI) {
288 if (num_ports > 4) {
289 cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal "
290 "num_ports\n");
291 return -1;
292 }
293
294 gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface));
295 gmx_rx_prts.s.prts = num_ports;
296 cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64);
297 }
298
299 /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */
300 if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX)
301 && !OCTEON_IS_MODEL(OCTEON_CN50XX)) {
302 /* Tell PKO the number of ports on this interface */
303 pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE);
304 if (interface == 0) {
305 if (num_ports == 1)
306 pko_mode.s.mode0 = 4;
307 else if (num_ports == 2)
308 pko_mode.s.mode0 = 3;
309 else if (num_ports <= 4)
310 pko_mode.s.mode0 = 2;
311 else if (num_ports <= 8)
312 pko_mode.s.mode0 = 1;
313 else
314 pko_mode.s.mode0 = 0;
315 } else {
316 if (num_ports == 1)
317 pko_mode.s.mode1 = 4;
318 else if (num_ports == 2)
319 pko_mode.s.mode1 = 3;
320 else if (num_ports <= 4)
321 pko_mode.s.mode1 = 2;
322 else if (num_ports <= 8)
323 pko_mode.s.mode1 = 1;
324 else
325 pko_mode.s.mode1 = 0;
326 }
327 cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64);
328 }
329
330 /*
331 * Set GMX to buffer as much data as possible before starting
332 * transmit. This reduces the chances that we have a TX under
333 * run due to memory contention. Any packet that fits entirely
334 * in the GMX FIFO can never have an under run regardless of
335 * memory load.
336 */
337 gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface));
338 if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)
339 || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
340 /* These chips have a fixed max threshold of 0x40 */
341 gmx_tx_thresh.s.cnt = 0x40;
342 } else {
343 /* Choose the max value for the number of ports */
344 if (num_ports <= 1)
345 gmx_tx_thresh.s.cnt = 0x100 / 1;
346 else if (num_ports == 2)
347 gmx_tx_thresh.s.cnt = 0x100 / 2;
348 else
349 gmx_tx_thresh.s.cnt = 0x100 / 4;
350 }
351 /*
352 * SPI and XAUI can have lots of ports but the GMX hardware
353 * only ever has a max of 4.
354 */
355 if (num_ports > 4)
356 num_ports = 4;
357 for (index = 0; index < num_ports; index++)
358 cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface),
359 gmx_tx_thresh.u64);
360
361 return 0;
362}
363
364/**
365 * Returns the IPD/PKO port number for a port on the given
366 * interface.
367 *
368 * @interface: Interface to use
369 * @port: Port on the interface
370 *
371 * Returns IPD/PKO port number
372 */
373int cvmx_helper_get_ipd_port(int interface, int port)
374{
375 switch (interface) {
376 case 0:
377 return port;
378 case 1:
379 return port + 16;
380 case 2:
381 return port + 32;
382 case 3:
383 return port + 36;
384 }
385 return -1;
386}
387
388/**
389 * Returns the interface number for an IPD/PKO port number.
390 *
391 * @ipd_port: IPD/PKO port number
392 *
393 * Returns Interface number
394 */
395int cvmx_helper_get_interface_num(int ipd_port)
396{
397 if (ipd_port < 16)
398 return 0;
399 else if (ipd_port < 32)
400 return 1;
401 else if (ipd_port < 36)
402 return 2;
403 else if (ipd_port < 40)
404 return 3;
405 else
406 cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD "
407 "port number\n");
408
409 return -1;
410}
411
412/**
413 * Returns the interface index number for an IPD/PKO port
414 * number.
415 *
416 * @ipd_port: IPD/PKO port number
417 *
418 * Returns Interface index number
419 */
420int cvmx_helper_get_interface_index_num(int ipd_port)
421{
422 if (ipd_port < 32)
423 return ipd_port & 15;
424 else if (ipd_port < 36)
425 return ipd_port & 3;
426 else if (ipd_port < 40)
427 return ipd_port & 3;
428 else
429 cvmx_dprintf("cvmx_helper_get_interface_index_num: "
430 "Illegal IPD port number\n");
431
432 return -1;
433}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
new file mode 100644
index 000000000000..1723248e987d
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
@@ -0,0 +1,354 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Functions for XAUI initialization, configuration,
30 * and monitoring.
31 *
32 */
33
34#include <asm/octeon/octeon.h>
35
36#include <asm/octeon/cvmx-config.h>
37
38#include <asm/octeon/cvmx-helper.h>
39
40#include <asm/octeon/cvmx-pko-defs.h>
41#include <asm/octeon/cvmx-gmxx-defs.h>
42#include <asm/octeon/cvmx-pcsxx-defs.h>
43
44void __cvmx_interrupt_gmxx_enable(int interface);
45void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
46void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
47
48int __cvmx_helper_xaui_enumerate(int interface)
49{
50 union cvmx_gmxx_hg2_control gmx_hg2_control;
51
52 /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
53 gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
54 if (gmx_hg2_control.s.hg2tx_en)
55 return 16;
56 else
57 return 1;
58}
59
60/**
61 * Probe a XAUI interface and determine the number of ports
62 * connected to it. The XAUI interface should still be down
63 * after this call.
64 *
65 * @interface: Interface to probe
66 *
67 * Returns Number of ports on the interface. Zero to disable.
68 */
69int __cvmx_helper_xaui_probe(int interface)
70{
71 int i;
72 union cvmx_gmxx_inf_mode mode;
73
74 /*
75 * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
76 * interface needs to be enabled before IPD otherwise per port
77 * backpressure may not work properly.
78 */
79 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
80 mode.s.en = 1;
81 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
82
83 __cvmx_helper_setup_gmx(interface, 1);
84
85 /*
86 * Setup PKO to support 16 ports for HiGig2 virtual
87 * ports. We're pointing all of the PKO packet ports for this
88 * interface to the XAUI. This allows us to use HiGig2
89 * backpressure per port.
90 */
91 for (i = 0; i < 16; i++) {
92 union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs;
93 pko_mem_port_ptrs.u64 = 0;
94 /*
95 * We set each PKO port to have equal priority in a
96 * round robin fashion.
97 */
98 pko_mem_port_ptrs.s.static_p = 0;
99 pko_mem_port_ptrs.s.qos_mask = 0xff;
100 /* All PKO ports map to the same XAUI hardware port */
101 pko_mem_port_ptrs.s.eid = interface * 4;
102 pko_mem_port_ptrs.s.pid = interface * 16 + i;
103 cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
104 }
105 return __cvmx_helper_xaui_enumerate(interface);
106}
107
108/**
109 * Bringup and enable a XAUI interface. After this call packet
110 * I/O should be fully functional. This is called with IPD
111 * enabled but PKO disabled.
112 *
113 * @interface: Interface to bring up
114 *
115 * Returns Zero on success, negative on failure
116 */
117int __cvmx_helper_xaui_enable(int interface)
118{
119 union cvmx_gmxx_prtx_cfg gmx_cfg;
120 union cvmx_pcsxx_control1_reg xauiCtl;
121 union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl;
122 union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl;
123 union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
124 union cvmx_gmxx_tx_int_en gmx_tx_int_en;
125 union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
126
127 /* (1) Interface has already been enabled. */
128
129 /* (2) Disable GMX. */
130 xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
131 xauiMiscCtl.s.gmxeno = 1;
132 cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
133
134 /* (3) Disable GMX and PCSX interrupts. */
135 gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
136 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
137 gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
138 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
139 pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
140 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
141
142 /* (4) Bring up the PCSX and GMX reconciliation layer. */
143 /* (4)a Set polarity and lane swapping. */
144 /* (4)b */
145 gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
146 /* Enable better IFG packing and improves performance */
147 gmxXauiTxCtl.s.dic_en = 1;
148 gmxXauiTxCtl.s.uni_en = 0;
149 cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
150
151 /* (4)c Aply reset sequence */
152 xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
153 xauiCtl.s.lo_pwr = 0;
154 xauiCtl.s.reset = 1;
155 cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
156
157 /* Wait for PCS to come out of reset */
158 if (CVMX_WAIT_FOR_FIELD64
159 (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
160 reset, ==, 0, 10000))
161 return -1;
162 /* Wait for PCS to be aligned */
163 if (CVMX_WAIT_FOR_FIELD64
164 (CVMX_PCSXX_10GBX_STATUS_REG(interface),
165 union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000))
166 return -1;
167 /* Wait for RX to be ready */
168 if (CVMX_WAIT_FOR_FIELD64
169 (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
170 status, ==, 0, 10000))
171 return -1;
172
173 /* (6) Configure GMX */
174 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
175 gmx_cfg.s.en = 0;
176 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
177
178 /* Wait for GMX RX to be idle */
179 if (CVMX_WAIT_FOR_FIELD64
180 (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
181 rx_idle, ==, 1, 10000))
182 return -1;
183 /* Wait for GMX TX to be idle */
184 if (CVMX_WAIT_FOR_FIELD64
185 (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
186 tx_idle, ==, 1, 10000))
187 return -1;
188
189 /* GMX configure */
190 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
191 gmx_cfg.s.speed = 1;
192 gmx_cfg.s.speed_msb = 0;
193 gmx_cfg.s.slottime = 1;
194 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
195 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
196 cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
197 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
198
199 /* (7) Clear out any error state */
200 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
201 cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
202 cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
203 cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
204 cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
205 cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
206
207 /* Wait for receive link */
208 if (CVMX_WAIT_FOR_FIELD64
209 (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
210 rcv_lnk, ==, 1, 10000))
211 return -1;
212 if (CVMX_WAIT_FOR_FIELD64
213 (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
214 xmtflt, ==, 0, 10000))
215 return -1;
216 if (CVMX_WAIT_FOR_FIELD64
217 (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
218 rcvflt, ==, 0, 10000))
219 return -1;
220
221 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
222 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
223 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
224
225 cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0));
226
227 /* (8) Enable packet reception */
228 xauiMiscCtl.s.gmxeno = 0;
229 cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
230
231 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
232 gmx_cfg.s.en = 1;
233 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
234
235 __cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
236 __cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
237 __cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
238 __cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
239 __cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
240 __cvmx_interrupt_gmxx_enable(interface);
241
242 return 0;
243}
244
245/**
246 * Return the link state of an IPD/PKO port as returned by
247 * auto negotiation. The result of this function may not match
248 * Octeon's link config if auto negotiation has changed since
249 * the last call to cvmx_helper_link_set().
250 *
251 * @ipd_port: IPD/PKO port to query
252 *
253 * Returns Link state
254 */
255cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
256{
257 int interface = cvmx_helper_get_interface_num(ipd_port);
258 union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
259 union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
260 union cvmx_pcsxx_status1_reg pcsxx_status1_reg;
261 cvmx_helper_link_info_t result;
262
263 gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
264 gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
265 pcsxx_status1_reg.u64 =
266 cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
267 result.u64 = 0;
268
269 /* Only return a link if both RX and TX are happy */
270 if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
271 (pcsxx_status1_reg.s.rcv_lnk == 1)) {
272 result.s.link_up = 1;
273 result.s.full_duplex = 1;
274 result.s.speed = 10000;
275 } else {
276 /* Disable GMX and PCSX interrupts. */
277 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
278 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
279 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
280 }
281 return result;
282}
283
284/**
285 * Configure an IPD/PKO port for the specified link state. This
286 * function does not influence auto negotiation at the PHY level.
287 * The passed link state must always match the link state returned
288 * by cvmx_helper_link_get(). It is normally best to use
289 * cvmx_helper_link_autoconf() instead.
290 *
291 * @ipd_port: IPD/PKO port to configure
292 * @link_info: The new link state
293 *
294 * Returns Zero on success, negative on failure
295 */
296int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
297{
298 int interface = cvmx_helper_get_interface_num(ipd_port);
299 union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
300 union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
301
302 gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
303 gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
304
305 /* If the link shouldn't be up, then just return */
306 if (!link_info.s.link_up)
307 return 0;
308
309 /* Do nothing if both RX and TX are happy */
310 if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
311 return 0;
312
313 /* Bring the link up */
314 return __cvmx_helper_xaui_enable(interface);
315}
316
317/**
318 * Configure a port for internal and/or external loopback. Internal loopback
319 * causes packets sent by the port to be received by Octeon. External loopback
320 * causes packets received from the wire to sent out again.
321 *
322 * @ipd_port: IPD/PKO port to loopback.
323 * @enable_internal:
324 * Non zero if you want internal loopback
325 * @enable_external:
326 * Non zero if you want external loopback
327 *
328 * Returns Zero on success, negative on failure.
329 */
330extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
331 int enable_internal,
332 int enable_external)
333{
334 int interface = cvmx_helper_get_interface_num(ipd_port);
335 union cvmx_pcsxx_control1_reg pcsxx_control1_reg;
336 union cvmx_gmxx_xaui_ext_loopback gmxx_xaui_ext_loopback;
337
338 /* Set the internal loop */
339 pcsxx_control1_reg.u64 =
340 cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
341 pcsxx_control1_reg.s.loopbck1 = enable_internal;
342 cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface),
343 pcsxx_control1_reg.u64);
344
345 /* Set the external loop */
346 gmxx_xaui_ext_loopback.u64 =
347 cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
348 gmxx_xaui_ext_loopback.s.en = enable_external;
349 cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface),
350 gmxx_xaui_ext_loopback.u64);
351
352 /* Take the link through a reset */
353 return __cvmx_helper_xaui_enable(interface);
354}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
new file mode 100644
index 000000000000..fa4963856353
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -0,0 +1,1116 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Helper functions for common, but complicated tasks.
31 *
32 */
33#include <asm/octeon/octeon.h>
34
35#include <asm/octeon/cvmx-config.h>
36
37#include <asm/octeon/cvmx-fpa.h>
38#include <asm/octeon/cvmx-pip.h>
39#include <asm/octeon/cvmx-pko.h>
40#include <asm/octeon/cvmx-ipd.h>
41#include <asm/octeon/cvmx-spi.h>
42#include <asm/octeon/cvmx-helper.h>
43#include <asm/octeon/cvmx-helper-board.h>
44
45#include <asm/octeon/cvmx-pip-defs.h>
46#include <asm/octeon/cvmx-smix-defs.h>
47#include <asm/octeon/cvmx-asxx-defs.h>
48
49/**
50 * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
51 * priorities[16]) is a function pointer. It is meant to allow
52 * customization of the PKO queue priorities based on the port
53 * number. Users should set this pointer to a function before
54 * calling any cvmx-helper operations.
55 */
56void (*cvmx_override_pko_queue_priority) (int pko_port,
57 uint64_t priorities[16]);
58
59/**
60 * cvmx_override_ipd_port_setup(int ipd_port) is a function
61 * pointer. It is meant to allow customization of the IPD port
62 * setup before packet input/output comes online. It is called
63 * after cvmx-helper does the default IPD configuration, but
64 * before IPD is enabled. Users should set this pointer to a
65 * function before calling any cvmx-helper operations.
66 */
67void (*cvmx_override_ipd_port_setup) (int ipd_port);
68
69/* Port count per interface */
70static int interface_port_count[4] = { 0, 0, 0, 0 };
71
72/* Port last configured link info index by IPD/PKO port */
73static cvmx_helper_link_info_t
74 port_link_info[CVMX_PIP_NUM_INPUT_PORTS];
75
76/**
77 * Return the number of interfaces the chip has. Each interface
78 * may have multiple ports. Most chips support two interfaces,
79 * but the CNX0XX and CNX1XX are exceptions. These only support
80 * one interface.
81 *
82 * Returns Number of interfaces on chip
83 */
84int cvmx_helper_get_number_of_interfaces(void)
85{
86 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
87 return 4;
88 else
89 return 3;
90}
91
92/**
93 * Return the number of ports on an interface. Depending on the
94 * chip and configuration, this can be 1-16. A value of 0
95 * specifies that the interface doesn't exist or isn't usable.
96 *
97 * @interface: Interface to get the port count for
98 *
99 * Returns Number of ports on interface. Can be Zero.
100 */
101int cvmx_helper_ports_on_interface(int interface)
102{
103 return interface_port_count[interface];
104}
105
106/**
107 * Get the operating mode of an interface. Depending on the Octeon
108 * chip and configuration, this function returns an enumeration
109 * of the type of packet I/O supported by an interface.
110 *
111 * @interface: Interface to probe
112 *
113 * Returns Mode of the interface. Unknown or unsupported interfaces return
114 * DISABLED.
115 */
116cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
117{
118 union cvmx_gmxx_inf_mode mode;
119 if (interface == 2)
120 return CVMX_HELPER_INTERFACE_MODE_NPI;
121
122 if (interface == 3) {
123 if (OCTEON_IS_MODEL(OCTEON_CN56XX)
124 || OCTEON_IS_MODEL(OCTEON_CN52XX))
125 return CVMX_HELPER_INTERFACE_MODE_LOOP;
126 else
127 return CVMX_HELPER_INTERFACE_MODE_DISABLED;
128 }
129
130 if (interface == 0
131 && cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5
132 && cvmx_sysinfo_get()->board_rev_major == 1) {
133 /*
134 * Lie about interface type of CN3005 board. This
135 * board has a switch on port 1 like the other
136 * evaluation boards, but it is connected over RGMII
137 * instead of GMII. Report GMII mode so that the
138 * speed is forced to 1 Gbit full duplex. Other than
139 * some initial configuration (which does not use the
140 * output of this function) there is no difference in
141 * setup between GMII and RGMII modes.
142 */
143 return CVMX_HELPER_INTERFACE_MODE_GMII;
144 }
145
146 /* Interface 1 is always disabled on CN31XX and CN30XX */
147 if ((interface == 1)
148 && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX)
149 || OCTEON_IS_MODEL(OCTEON_CN50XX)
150 || OCTEON_IS_MODEL(OCTEON_CN52XX)))
151 return CVMX_HELPER_INTERFACE_MODE_DISABLED;
152
153 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
154
155 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
156 switch (mode.cn56xx.mode) {
157 case 0:
158 return CVMX_HELPER_INTERFACE_MODE_DISABLED;
159 case 1:
160 return CVMX_HELPER_INTERFACE_MODE_XAUI;
161 case 2:
162 return CVMX_HELPER_INTERFACE_MODE_SGMII;
163 case 3:
164 return CVMX_HELPER_INTERFACE_MODE_PICMG;
165 default:
166 return CVMX_HELPER_INTERFACE_MODE_DISABLED;
167 }
168 } else {
169 if (!mode.s.en)
170 return CVMX_HELPER_INTERFACE_MODE_DISABLED;
171
172 if (mode.s.type) {
173 if (OCTEON_IS_MODEL(OCTEON_CN38XX)
174 || OCTEON_IS_MODEL(OCTEON_CN58XX))
175 return CVMX_HELPER_INTERFACE_MODE_SPI;
176 else
177 return CVMX_HELPER_INTERFACE_MODE_GMII;
178 } else
179 return CVMX_HELPER_INTERFACE_MODE_RGMII;
180 }
181}
182
183/**
184 * Configure the IPD/PIP tagging and QoS options for a specific
185 * port. This function determines the POW work queue entry
186 * contents for a port. The setup performed here is controlled by
187 * the defines in executive-config.h.
188 *
189 * @ipd_port: Port to configure. This follows the IPD numbering, not the
190 * per interface numbering
191 *
192 * Returns Zero on success, negative on failure
193 */
194static int __cvmx_helper_port_setup_ipd(int ipd_port)
195{
196 union cvmx_pip_prt_cfgx port_config;
197 union cvmx_pip_prt_tagx tag_config;
198
199 port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
200 tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port));
201
202 /* Have each port go to a different POW queue */
203 port_config.s.qos = ipd_port & 0x7;
204
205 /* Process the headers and place the IP header in the work queue */
206 port_config.s.mode = CVMX_HELPER_INPUT_PORT_SKIP_MODE;
207
208 tag_config.s.ip6_src_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP;
209 tag_config.s.ip6_dst_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_IP;
210 tag_config.s.ip6_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT;
211 tag_config.s.ip6_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT;
212 tag_config.s.ip6_nxth_flag = CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER;
213 tag_config.s.ip4_src_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP;
214 tag_config.s.ip4_dst_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_IP;
215 tag_config.s.ip4_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT;
216 tag_config.s.ip4_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT;
217 tag_config.s.ip4_pctl_flag = CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL;
218 tag_config.s.inc_prt_flag = CVMX_HELPER_INPUT_TAG_INPUT_PORT;
219 tag_config.s.tcp6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
220 tag_config.s.tcp4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
221 tag_config.s.ip6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
222 tag_config.s.ip4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
223 tag_config.s.non_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
224 /* Put all packets in group 0. Other groups can be used by the app */
225 tag_config.s.grp = 0;
226
227 cvmx_pip_config_port(ipd_port, port_config, tag_config);
228
229 /* Give the user a chance to override our setting for each port */
230 if (cvmx_override_ipd_port_setup)
231 cvmx_override_ipd_port_setup(ipd_port);
232
233 return 0;
234}
235
236/**
237 * This function sets the interface_port_count[interface] correctly,
238 * without modifying any hardware configuration. Hardware setup of
239 * the ports will be performed later.
240 *
241 * @interface: Interface to probe
242 *
243 * Returns Zero on success, negative on failure
244 */
245int cvmx_helper_interface_enumerate(int interface)
246{
247 switch (cvmx_helper_interface_get_mode(interface)) {
248 /* These types don't support ports to IPD/PKO */
249 case CVMX_HELPER_INTERFACE_MODE_DISABLED:
250 case CVMX_HELPER_INTERFACE_MODE_PCIE:
251 interface_port_count[interface] = 0;
252 break;
253 /* XAUI is a single high speed port */
254 case CVMX_HELPER_INTERFACE_MODE_XAUI:
255 interface_port_count[interface] =
256 __cvmx_helper_xaui_enumerate(interface);
257 break;
258 /*
259 * RGMII/GMII/MII are all treated about the same. Most
260 * functions refer to these ports as RGMII.
261 */
262 case CVMX_HELPER_INTERFACE_MODE_RGMII:
263 case CVMX_HELPER_INTERFACE_MODE_GMII:
264 interface_port_count[interface] =
265 __cvmx_helper_rgmii_enumerate(interface);
266 break;
267 /*
268 * SPI4 can have 1-16 ports depending on the device at
269 * the other end.
270 */
271 case CVMX_HELPER_INTERFACE_MODE_SPI:
272 interface_port_count[interface] =
273 __cvmx_helper_spi_enumerate(interface);
274 break;
275 /*
276 * SGMII can have 1-4 ports depending on how many are
277 * hooked up.
278 */
279 case CVMX_HELPER_INTERFACE_MODE_SGMII:
280 case CVMX_HELPER_INTERFACE_MODE_PICMG:
281 interface_port_count[interface] =
282 __cvmx_helper_sgmii_enumerate(interface);
283 break;
284 /* PCI target Network Packet Interface */
285 case CVMX_HELPER_INTERFACE_MODE_NPI:
286 interface_port_count[interface] =
287 __cvmx_helper_npi_enumerate(interface);
288 break;
289 /*
290 * Special loopback only ports. These are not the same
291 * as other ports in loopback mode.
292 */
293 case CVMX_HELPER_INTERFACE_MODE_LOOP:
294 interface_port_count[interface] =
295 __cvmx_helper_loop_enumerate(interface);
296 break;
297 }
298
299 interface_port_count[interface] =
300 __cvmx_helper_board_interface_probe(interface,
301 interface_port_count
302 [interface]);
303
304 /* Make sure all global variables propagate to other cores */
305 CVMX_SYNCWS;
306
307 return 0;
308}
309
310/**
311 * This function probes an interface to determine the actual
312 * number of hardware ports connected to it. It doesn't setup the
313 * ports or enable them. The main goal here is to set the global
314 * interface_port_count[interface] correctly. Hardware setup of the
315 * ports will be performed later.
316 *
317 * @interface: Interface to probe
318 *
319 * Returns Zero on success, negative on failure
320 */
321int cvmx_helper_interface_probe(int interface)
322{
323 cvmx_helper_interface_enumerate(interface);
324 /* At this stage in the game we don't want packets to be moving yet.
325 The following probe calls should perform hardware setup
326 needed to determine port counts. Receive must still be disabled */
327 switch (cvmx_helper_interface_get_mode(interface)) {
328 /* These types don't support ports to IPD/PKO */
329 case CVMX_HELPER_INTERFACE_MODE_DISABLED:
330 case CVMX_HELPER_INTERFACE_MODE_PCIE:
331 break;
332 /* XAUI is a single high speed port */
333 case CVMX_HELPER_INTERFACE_MODE_XAUI:
334 __cvmx_helper_xaui_probe(interface);
335 break;
336 /*
337 * RGMII/GMII/MII are all treated about the same. Most
338 * functions refer to these ports as RGMII.
339 */
340 case CVMX_HELPER_INTERFACE_MODE_RGMII:
341 case CVMX_HELPER_INTERFACE_MODE_GMII:
342 __cvmx_helper_rgmii_probe(interface);
343 break;
344 /*
345 * SPI4 can have 1-16 ports depending on the device at
346 * the other end.
347 */
348 case CVMX_HELPER_INTERFACE_MODE_SPI:
349 __cvmx_helper_spi_probe(interface);
350 break;
351 /*
352 * SGMII can have 1-4 ports depending on how many are
353 * hooked up.
354 */
355 case CVMX_HELPER_INTERFACE_MODE_SGMII:
356 case CVMX_HELPER_INTERFACE_MODE_PICMG:
357 __cvmx_helper_sgmii_probe(interface);
358 break;
359 /* PCI target Network Packet Interface */
360 case CVMX_HELPER_INTERFACE_MODE_NPI:
361 __cvmx_helper_npi_probe(interface);
362 break;
363 /*
364 * Special loopback only ports. These are not the same
365 * as other ports in loopback mode.
366 */
367 case CVMX_HELPER_INTERFACE_MODE_LOOP:
368 __cvmx_helper_loop_probe(interface);
369 break;
370 }
371
372 /* Make sure all global variables propagate to other cores */
373 CVMX_SYNCWS;
374
375 return 0;
376}
377
378/**
379 * Setup the IPD/PIP for the ports on an interface. Packet
380 * classification and tagging are set for every port on the
381 * interface. The number of ports on the interface must already
382 * have been probed.
383 *
384 * @interface: Interface to setup IPD/PIP for
385 *
386 * Returns Zero on success, negative on failure
387 */
388static int __cvmx_helper_interface_setup_ipd(int interface)
389{
390 int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
391 int num_ports = interface_port_count[interface];
392
393 while (num_ports--) {
394 __cvmx_helper_port_setup_ipd(ipd_port);
395 ipd_port++;
396 }
397 return 0;
398}
399
400/**
401 * Setup global setting for IPD/PIP not related to a specific
402 * interface or port. This must be called before IPD is enabled.
403 *
404 * Returns Zero on success, negative on failure.
405 */
406static int __cvmx_helper_global_setup_ipd(void)
407{
408 /* Setup the global packet input options */
409 cvmx_ipd_config(CVMX_FPA_PACKET_POOL_SIZE / 8,
410 CVMX_HELPER_FIRST_MBUFF_SKIP / 8,
411 CVMX_HELPER_NOT_FIRST_MBUFF_SKIP / 8,
412 /* The +8 is to account for the next ptr */
413 (CVMX_HELPER_FIRST_MBUFF_SKIP + 8) / 128,
414 /* The +8 is to account for the next ptr */
415 (CVMX_HELPER_NOT_FIRST_MBUFF_SKIP + 8) / 128,
416 CVMX_FPA_WQE_POOL,
417 CVMX_IPD_OPC_MODE_STT,
418 CVMX_HELPER_ENABLE_BACK_PRESSURE);
419 return 0;
420}
421
422/**
423 * Setup the PKO for the ports on an interface. The number of
424 * queues per port and the priority of each PKO output queue
425 * is set here. PKO must be disabled when this function is called.
426 *
427 * @interface: Interface to setup PKO for
428 *
429 * Returns Zero on success, negative on failure
430 */
431static int __cvmx_helper_interface_setup_pko(int interface)
432{
433 /*
434 * Each packet output queue has an associated priority. The
435 * higher the priority, the more often it can send a packet. A
436 * priority of 8 means it can send in all 8 rounds of
437 * contention. We're going to make each queue one less than
438 * the last. The vector of priorities has been extended to
439 * support CN5xxx CPUs, where up to 16 queues can be
440 * associated to a port. To keep backward compatibility we
441 * don't change the initial 8 priorities and replicate them in
442 * the second half. With per-core PKO queues (PKO lockless
443 * operation) all queues have the same priority.
444 */
445 uint64_t priorities[16] =
446 { 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1 };
447
448 /*
449 * Setup the IPD/PIP and PKO for the ports discovered
450 * above. Here packet classification, tagging and output
451 * priorities are set.
452 */
453 int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
454 int num_ports = interface_port_count[interface];
455 while (num_ports--) {
456 /*
457 * Give the user a chance to override the per queue
458 * priorities.
459 */
460 if (cvmx_override_pko_queue_priority)
461 cvmx_override_pko_queue_priority(ipd_port, priorities);
462
463 cvmx_pko_config_port(ipd_port,
464 cvmx_pko_get_base_queue_per_core(ipd_port,
465 0),
466 cvmx_pko_get_num_queues(ipd_port),
467 priorities);
468 ipd_port++;
469 }
470 return 0;
471}
472
473/**
474 * Setup global setting for PKO not related to a specific
475 * interface or port. This must be called before PKO is enabled.
476 *
477 * Returns Zero on success, negative on failure.
478 */
479static int __cvmx_helper_global_setup_pko(void)
480{
481 /*
482 * Disable tagwait FAU timeout. This needs to be done before
483 * anyone might start packet output using tags.
484 */
485 union cvmx_iob_fau_timeout fau_to;
486 fau_to.u64 = 0;
487 fau_to.s.tout_val = 0xfff;
488 fau_to.s.tout_enb = 0;
489 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64);
490 return 0;
491}
492
493/**
494 * Setup global backpressure setting.
495 *
496 * Returns Zero on success, negative on failure
497 */
498static int __cvmx_helper_global_setup_backpressure(void)
499{
500#if CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE
501 /* Disable backpressure if configured to do so */
502 /* Disable backpressure (pause frame) generation */
503 int num_interfaces = cvmx_helper_get_number_of_interfaces();
504 int interface;
505 for (interface = 0; interface < num_interfaces; interface++) {
506 switch (cvmx_helper_interface_get_mode(interface)) {
507 case CVMX_HELPER_INTERFACE_MODE_DISABLED:
508 case CVMX_HELPER_INTERFACE_MODE_PCIE:
509 case CVMX_HELPER_INTERFACE_MODE_NPI:
510 case CVMX_HELPER_INTERFACE_MODE_LOOP:
511 case CVMX_HELPER_INTERFACE_MODE_XAUI:
512 break;
513 case CVMX_HELPER_INTERFACE_MODE_RGMII:
514 case CVMX_HELPER_INTERFACE_MODE_GMII:
515 case CVMX_HELPER_INTERFACE_MODE_SPI:
516 case CVMX_HELPER_INTERFACE_MODE_SGMII:
517 case CVMX_HELPER_INTERFACE_MODE_PICMG:
518 cvmx_gmx_set_backpressure_override(interface, 0xf);
519 break;
520 }
521 }
522#endif
523
524 return 0;
525}
526
527/**
528 * Enable packet input/output from the hardware. This function is
529 * called after all internal setup is complete and IPD is enabled.
530 * After this function completes, packets will be accepted from the
531 * hardware ports. PKO should still be disabled to make sure packets
532 * aren't sent out partially setup hardware.
533 *
534 * @interface: Interface to enable
535 *
536 * Returns Zero on success, negative on failure
537 */
538static int __cvmx_helper_packet_hardware_enable(int interface)
539{
540 int result = 0;
541 switch (cvmx_helper_interface_get_mode(interface)) {
542 /* These types don't support ports to IPD/PKO */
543 case CVMX_HELPER_INTERFACE_MODE_DISABLED:
544 case CVMX_HELPER_INTERFACE_MODE_PCIE:
545 /* Nothing to do */
546 break;
547 /* XAUI is a single high speed port */
548 case CVMX_HELPER_INTERFACE_MODE_XAUI:
549 result = __cvmx_helper_xaui_enable(interface);
550 break;
551 /*
552 * RGMII/GMII/MII are all treated about the same. Most
553 * functions refer to these ports as RGMII
554 */
555 case CVMX_HELPER_INTERFACE_MODE_RGMII:
556 case CVMX_HELPER_INTERFACE_MODE_GMII:
557 result = __cvmx_helper_rgmii_enable(interface);
558 break;
559 /*
560 * SPI4 can have 1-16 ports depending on the device at
561 * the other end
562 */
563 case CVMX_HELPER_INTERFACE_MODE_SPI:
564 result = __cvmx_helper_spi_enable(interface);
565 break;
566 /*
567 * SGMII can have 1-4 ports depending on how many are
568 * hooked up
569 */
570 case CVMX_HELPER_INTERFACE_MODE_SGMII:
571 case CVMX_HELPER_INTERFACE_MODE_PICMG:
572 result = __cvmx_helper_sgmii_enable(interface);
573 break;
574 /* PCI target Network Packet Interface */
575 case CVMX_HELPER_INTERFACE_MODE_NPI:
576 result = __cvmx_helper_npi_enable(interface);
577 break;
578 /*
579 * Special loopback only ports. These are not the same
580 * as other ports in loopback mode
581 */
582 case CVMX_HELPER_INTERFACE_MODE_LOOP:
583 result = __cvmx_helper_loop_enable(interface);
584 break;
585 }
586 result |= __cvmx_helper_board_hardware_enable(interface);
587 return result;
588}
589
590/**
591 * Function to adjust internal IPD pointer alignments
592 *
593 * Returns 0 on success
594 * !0 on failure
595 */
596int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
597{
598#define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES \
599 (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_FIRST_MBUFF_SKIP)
600#define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES \
601 (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_NOT_FIRST_MBUFF_SKIP)
602#define FIX_IPD_OUTPORT 0
603 /* Ports 0-15 are interface 0, 16-31 are interface 1 */
604#define INTERFACE(port) (port >> 4)
605#define INDEX(port) (port & 0xf)
606 uint64_t *p64;
607 cvmx_pko_command_word0_t pko_command;
608 union cvmx_buf_ptr g_buffer, pkt_buffer;
609 cvmx_wqe_t *work;
610 int size, num_segs = 0, wqe_pcnt, pkt_pcnt;
611 union cvmx_gmxx_prtx_cfg gmx_cfg;
612 int retry_cnt;
613 int retry_loop_cnt;
614 int i;
615 cvmx_helper_link_info_t link_info;
616
617 /* Save values for restore at end */
618 uint64_t prtx_cfg =
619 cvmx_read_csr(CVMX_GMXX_PRTX_CFG
620 (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
621 uint64_t tx_ptr_en =
622 cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
623 uint64_t rx_ptr_en =
624 cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
625 uint64_t rxx_jabber =
626 cvmx_read_csr(CVMX_GMXX_RXX_JABBER
627 (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
628 uint64_t frame_max =
629 cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX
630 (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
631
632 /* Configure port to gig FDX as required for loopback mode */
633 cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT);
634
635 /*
636 * Disable reception on all ports so if traffic is present it
637 * will not interfere.
638 */
639 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
640
641 cvmx_wait(100000000ull);
642
643 for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) {
644 retry_cnt = 100000;
645 wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
646 pkt_pcnt = (wqe_pcnt >> 7) & 0x7f;
647 wqe_pcnt &= 0x7f;
648
649 num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3;
650
651 if (num_segs == 0)
652 goto fix_ipd_exit;
653
654 num_segs += 1;
655
656 size =
657 FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES +
658 ((num_segs - 1) * FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) -
659 (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2);
660
661 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)),
662 1 << INDEX(FIX_IPD_OUTPORT));
663 CVMX_SYNC;
664
665 g_buffer.u64 = 0;
666 g_buffer.s.addr =
667 cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL));
668 if (g_buffer.s.addr == 0) {
669 cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT "
670 "buffer allocation failure.\n");
671 goto fix_ipd_exit;
672 }
673
674 g_buffer.s.pool = CVMX_FPA_WQE_POOL;
675 g_buffer.s.size = num_segs;
676
677 pkt_buffer.u64 = 0;
678 pkt_buffer.s.addr =
679 cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL));
680 if (pkt_buffer.s.addr == 0) {
681 cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT "
682 "buffer allocation failure.\n");
683 goto fix_ipd_exit;
684 }
685 pkt_buffer.s.i = 1;
686 pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL;
687 pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES;
688
689 p64 = (uint64_t *) cvmx_phys_to_ptr(pkt_buffer.s.addr);
690 p64[0] = 0xffffffffffff0000ull;
691 p64[1] = 0x08004510ull;
692 p64[2] = ((uint64_t) (size - 14) << 48) | 0x5ae740004000ull;
693 p64[3] = 0x3a5fc0a81073c0a8ull;
694
695 for (i = 0; i < num_segs; i++) {
696 if (i > 0)
697 pkt_buffer.s.size =
698 FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES;
699
700 if (i == (num_segs - 1))
701 pkt_buffer.s.i = 0;
702
703 *(uint64_t *) cvmx_phys_to_ptr(g_buffer.s.addr +
704 8 * i) = pkt_buffer.u64;
705 }
706
707 /* Build the PKO command */
708 pko_command.u64 = 0;
709 pko_command.s.segs = num_segs;
710 pko_command.s.total_bytes = size;
711 pko_command.s.dontfree = 0;
712 pko_command.s.gather = 1;
713
714 gmx_cfg.u64 =
715 cvmx_read_csr(CVMX_GMXX_PRTX_CFG
716 (INDEX(FIX_IPD_OUTPORT),
717 INTERFACE(FIX_IPD_OUTPORT)));
718 gmx_cfg.s.en = 1;
719 cvmx_write_csr(CVMX_GMXX_PRTX_CFG
720 (INDEX(FIX_IPD_OUTPORT),
721 INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64);
722 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
723 1 << INDEX(FIX_IPD_OUTPORT));
724 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
725 1 << INDEX(FIX_IPD_OUTPORT));
726
727 cvmx_write_csr(CVMX_GMXX_RXX_JABBER
728 (INDEX(FIX_IPD_OUTPORT),
729 INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
730 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX
731 (INDEX(FIX_IPD_OUTPORT),
732 INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
733
734 cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT,
735 cvmx_pko_get_base_queue
736 (FIX_IPD_OUTPORT),
737 CVMX_PKO_LOCK_CMD_QUEUE);
738 cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT,
739 cvmx_pko_get_base_queue
740 (FIX_IPD_OUTPORT), pko_command,
741 g_buffer, CVMX_PKO_LOCK_CMD_QUEUE);
742
743 CVMX_SYNC;
744
745 do {
746 work = cvmx_pow_work_request_sync(CVMX_POW_WAIT);
747 retry_cnt--;
748 } while ((work == NULL) && (retry_cnt > 0));
749
750 if (!retry_cnt)
751 cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT "
752 "get_work() timeout occurred.\n");
753
754 /* Free packet */
755 if (work)
756 cvmx_helper_free_packet_data(work);
757 }
758
759fix_ipd_exit:
760
761 /* Return CSR configs to saved values */
762 cvmx_write_csr(CVMX_GMXX_PRTX_CFG
763 (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
764 prtx_cfg);
765 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
766 tx_ptr_en);
767 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
768 rx_ptr_en);
769 cvmx_write_csr(CVMX_GMXX_RXX_JABBER
770 (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
771 rxx_jabber);
772 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX
773 (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
774 frame_max);
775 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0);
776 /* Set link to down so autonegotiation will set it up again */
777 link_info.u64 = 0;
778 cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info);
779
780 /*
781 * Bring the link back up as autonegotiation is not done in
782 * user applications.
783 */
784 cvmx_helper_link_autoconf(FIX_IPD_OUTPORT);
785
786 CVMX_SYNC;
787 if (num_segs)
788 cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n");
789
790 return !!num_segs;
791
792}
793
794/**
795 * Called after all internal packet IO paths are setup. This
796 * function enables IPD/PIP and begins packet input and output.
797 *
798 * Returns Zero on success, negative on failure
799 */
800int cvmx_helper_ipd_and_packet_input_enable(void)
801{
802 int num_interfaces;
803 int interface;
804
805 /* Enable IPD */
806 cvmx_ipd_enable();
807
808 /*
809 * Time to enable hardware ports packet input and output. Note
810 * that at this point IPD/PIP must be fully functional and PKO
811 * must be disabled
812 */
813 num_interfaces = cvmx_helper_get_number_of_interfaces();
814 for (interface = 0; interface < num_interfaces; interface++) {
815 if (cvmx_helper_ports_on_interface(interface) > 0)
816 __cvmx_helper_packet_hardware_enable(interface);
817 }
818
819 /* Finally enable PKO now that the entire path is up and running */
820 cvmx_pko_enable();
821
822 if ((OCTEON_IS_MODEL(OCTEON_CN31XX_PASS1)
823 || OCTEON_IS_MODEL(OCTEON_CN30XX_PASS1))
824 && (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM))
825 __cvmx_helper_errata_fix_ipd_ptr_alignment();
826 return 0;
827}
828
829/**
830 * Initialize the PIP, IPD, and PKO hardware to support
831 * simple priority based queues for the ethernet ports. Each
832 * port is configured with a number of priority queues based
833 * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower
834 * priority than the previous.
835 *
836 * Returns Zero on success, non-zero on failure
837 */
838int cvmx_helper_initialize_packet_io_global(void)
839{
840 int result = 0;
841 int interface;
842 union cvmx_l2c_cfg l2c_cfg;
843 union cvmx_smix_en smix_en;
844 const int num_interfaces = cvmx_helper_get_number_of_interfaces();
845
846 /*
847 * CN52XX pass 1: Due to a bug in 2nd order CDR, it needs to
848 * be disabled.
849 */
850 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
851 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(1);
852
853 /*
854 * Tell L2 to give the IOB statically higher priority compared
855 * to the cores. This avoids conditions where IO blocks might
856 * be starved under very high L2 loads.
857 */
858 l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
859 l2c_cfg.s.lrf_arb_mode = 0;
860 l2c_cfg.s.rfb_arb_mode = 0;
861 cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
862
863 /* Make sure SMI/MDIO is enabled so we can query PHYs */
864 smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0));
865 if (!smix_en.s.en) {
866 smix_en.s.en = 1;
867 cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64);
868 }
869
870 /* Newer chips actually have two SMI/MDIO interfaces */
871 if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) &&
872 !OCTEON_IS_MODEL(OCTEON_CN58XX) &&
873 !OCTEON_IS_MODEL(OCTEON_CN50XX)) {
874 smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1));
875 if (!smix_en.s.en) {
876 smix_en.s.en = 1;
877 cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64);
878 }
879 }
880
881 cvmx_pko_initialize_global();
882 for (interface = 0; interface < num_interfaces; interface++) {
883 result |= cvmx_helper_interface_probe(interface);
884 if (cvmx_helper_ports_on_interface(interface) > 0)
885 cvmx_dprintf("Interface %d has %d ports (%s)\n",
886 interface,
887 cvmx_helper_ports_on_interface(interface),
888 cvmx_helper_interface_mode_to_string
889 (cvmx_helper_interface_get_mode
890 (interface)));
891 result |= __cvmx_helper_interface_setup_ipd(interface);
892 result |= __cvmx_helper_interface_setup_pko(interface);
893 }
894
895 result |= __cvmx_helper_global_setup_ipd();
896 result |= __cvmx_helper_global_setup_pko();
897
898 /* Enable any flow control and backpressure */
899 result |= __cvmx_helper_global_setup_backpressure();
900
901#if CVMX_HELPER_ENABLE_IPD
902 result |= cvmx_helper_ipd_and_packet_input_enable();
903#endif
904 return result;
905}
906
907/**
908 * Does core local initialization for packet io
909 *
910 * Returns Zero on success, non-zero on failure
911 */
912int cvmx_helper_initialize_packet_io_local(void)
913{
914 return cvmx_pko_initialize_local();
915}
916
917/**
918 * Auto configure an IPD/PKO port link state and speed. This
919 * function basically does the equivalent of:
920 * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
921 *
922 * @ipd_port: IPD/PKO port to auto configure
923 *
924 * Returns Link state after configure
925 */
926cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
927{
928 cvmx_helper_link_info_t link_info;
929 int interface = cvmx_helper_get_interface_num(ipd_port);
930 int index = cvmx_helper_get_interface_index_num(ipd_port);
931
932 if (index >= cvmx_helper_ports_on_interface(interface)) {
933 link_info.u64 = 0;
934 return link_info;
935 }
936
937 link_info = cvmx_helper_link_get(ipd_port);
938 if (link_info.u64 == port_link_info[ipd_port].u64)
939 return link_info;
940
941 /* If we fail to set the link speed, port_link_info will not change */
942 cvmx_helper_link_set(ipd_port, link_info);
943
944 /*
945 * port_link_info should be the current value, which will be
946 * different than expect if cvmx_helper_link_set() failed.
947 */
948 return port_link_info[ipd_port];
949}
950
951/**
952 * Return the link state of an IPD/PKO port as returned by
953 * auto negotiation. The result of this function may not match
954 * Octeon's link config if auto negotiation has changed since
955 * the last call to cvmx_helper_link_set().
956 *
957 * @ipd_port: IPD/PKO port to query
958 *
959 * Returns Link state
960 */
961cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
962{
963 cvmx_helper_link_info_t result;
964 int interface = cvmx_helper_get_interface_num(ipd_port);
965 int index = cvmx_helper_get_interface_index_num(ipd_port);
966
967 /* The default result will be a down link unless the code below
968 changes it */
969 result.u64 = 0;
970
971 if (index >= cvmx_helper_ports_on_interface(interface))
972 return result;
973
974 switch (cvmx_helper_interface_get_mode(interface)) {
975 case CVMX_HELPER_INTERFACE_MODE_DISABLED:
976 case CVMX_HELPER_INTERFACE_MODE_PCIE:
977 /* Network links are not supported */
978 break;
979 case CVMX_HELPER_INTERFACE_MODE_XAUI:
980 result = __cvmx_helper_xaui_link_get(ipd_port);
981 break;
982 case CVMX_HELPER_INTERFACE_MODE_GMII:
983 if (index == 0)
984 result = __cvmx_helper_rgmii_link_get(ipd_port);
985 else {
986 result.s.full_duplex = 1;
987 result.s.link_up = 1;
988 result.s.speed = 1000;
989 }
990 break;
991 case CVMX_HELPER_INTERFACE_MODE_RGMII:
992 result = __cvmx_helper_rgmii_link_get(ipd_port);
993 break;
994 case CVMX_HELPER_INTERFACE_MODE_SPI:
995 result = __cvmx_helper_spi_link_get(ipd_port);
996 break;
997 case CVMX_HELPER_INTERFACE_MODE_SGMII:
998 case CVMX_HELPER_INTERFACE_MODE_PICMG:
999 result = __cvmx_helper_sgmii_link_get(ipd_port);
1000 break;
1001 case CVMX_HELPER_INTERFACE_MODE_NPI:
1002 case CVMX_HELPER_INTERFACE_MODE_LOOP:
1003 /* Network links are not supported */
1004 break;
1005 }
1006 return result;
1007}
1008
1009/**
1010 * Configure an IPD/PKO port for the specified link state. This
1011 * function does not influence auto negotiation at the PHY level.
1012 * The passed link state must always match the link state returned
1013 * by cvmx_helper_link_get(). It is normally best to use
1014 * cvmx_helper_link_autoconf() instead.
1015 *
1016 * @ipd_port: IPD/PKO port to configure
1017 * @link_info: The new link state
1018 *
1019 * Returns Zero on success, negative on failure
1020 */
1021int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
1022{
1023 int result = -1;
1024 int interface = cvmx_helper_get_interface_num(ipd_port);
1025 int index = cvmx_helper_get_interface_index_num(ipd_port);
1026
1027 if (index >= cvmx_helper_ports_on_interface(interface))
1028 return -1;
1029
1030 switch (cvmx_helper_interface_get_mode(interface)) {
1031 case CVMX_HELPER_INTERFACE_MODE_DISABLED:
1032 case CVMX_HELPER_INTERFACE_MODE_PCIE:
1033 break;
1034 case CVMX_HELPER_INTERFACE_MODE_XAUI:
1035 result = __cvmx_helper_xaui_link_set(ipd_port, link_info);
1036 break;
1037 /*
1038 * RGMII/GMII/MII are all treated about the same. Most
1039 * functions refer to these ports as RGMII.
1040 */
1041 case CVMX_HELPER_INTERFACE_MODE_RGMII:
1042 case CVMX_HELPER_INTERFACE_MODE_GMII:
1043 result = __cvmx_helper_rgmii_link_set(ipd_port, link_info);
1044 break;
1045 case CVMX_HELPER_INTERFACE_MODE_SPI:
1046 result = __cvmx_helper_spi_link_set(ipd_port, link_info);
1047 break;
1048 case CVMX_HELPER_INTERFACE_MODE_SGMII:
1049 case CVMX_HELPER_INTERFACE_MODE_PICMG:
1050 result = __cvmx_helper_sgmii_link_set(ipd_port, link_info);
1051 break;
1052 case CVMX_HELPER_INTERFACE_MODE_NPI:
1053 case CVMX_HELPER_INTERFACE_MODE_LOOP:
1054 break;
1055 }
1056 /* Set the port_link_info here so that the link status is updated
1057 no matter how cvmx_helper_link_set is called. We don't change
1058 the value if link_set failed */
1059 if (result == 0)
1060 port_link_info[ipd_port].u64 = link_info.u64;
1061 return result;
1062}
1063
1064/**
1065 * Configure a port for internal and/or external loopback. Internal loopback
1066 * causes packets sent by the port to be received by Octeon. External loopback
1067 * causes packets received from the wire to sent out again.
1068 *
1069 * @ipd_port: IPD/PKO port to loopback.
1070 * @enable_internal:
1071 * Non zero if you want internal loopback
1072 * @enable_external:
1073 * Non zero if you want external loopback
1074 *
1075 * Returns Zero on success, negative on failure.
1076 */
1077int cvmx_helper_configure_loopback(int ipd_port, int enable_internal,
1078 int enable_external)
1079{
1080 int result = -1;
1081 int interface = cvmx_helper_get_interface_num(ipd_port);
1082 int index = cvmx_helper_get_interface_index_num(ipd_port);
1083
1084 if (index >= cvmx_helper_ports_on_interface(interface))
1085 return -1;
1086
1087 switch (cvmx_helper_interface_get_mode(interface)) {
1088 case CVMX_HELPER_INTERFACE_MODE_DISABLED:
1089 case CVMX_HELPER_INTERFACE_MODE_PCIE:
1090 case CVMX_HELPER_INTERFACE_MODE_SPI:
1091 case CVMX_HELPER_INTERFACE_MODE_NPI:
1092 case CVMX_HELPER_INTERFACE_MODE_LOOP:
1093 break;
1094 case CVMX_HELPER_INTERFACE_MODE_XAUI:
1095 result =
1096 __cvmx_helper_xaui_configure_loopback(ipd_port,
1097 enable_internal,
1098 enable_external);
1099 break;
1100 case CVMX_HELPER_INTERFACE_MODE_RGMII:
1101 case CVMX_HELPER_INTERFACE_MODE_GMII:
1102 result =
1103 __cvmx_helper_rgmii_configure_loopback(ipd_port,
1104 enable_internal,
1105 enable_external);
1106 break;
1107 case CVMX_HELPER_INTERFACE_MODE_SGMII:
1108 case CVMX_HELPER_INTERFACE_MODE_PICMG:
1109 result =
1110 __cvmx_helper_sgmii_configure_loopback(ipd_port,
1111 enable_internal,
1112 enable_external);
1113 break;
1114 }
1115 return result;
1116}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
new file mode 100644
index 000000000000..e59d1b79f24c
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
@@ -0,0 +1,371 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2009 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Automatically generated functions useful for enabling
31 * and decoding RSL_INT_BLOCKS interrupts.
32 *
33 */
34
35#include <asm/octeon/octeon.h>
36
37#include <asm/octeon/cvmx-gmxx-defs.h>
38#include <asm/octeon/cvmx-pcsx-defs.h>
39#include <asm/octeon/cvmx-pcsxx-defs.h>
40#include <asm/octeon/cvmx-spxx-defs.h>
41#include <asm/octeon/cvmx-stxx-defs.h>
42
43#ifndef PRINT_ERROR
44#define PRINT_ERROR(format, ...)
45#endif
46
47
48/**
49 * __cvmx_interrupt_gmxx_rxx_int_en_enable enables all interrupt bits in cvmx_gmxx_rxx_int_en_t
50 */
51void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
52{
53 union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
54 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block),
55 cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block)));
56 gmx_rx_int_en.u64 = 0;
57 if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
58 /* Skipping gmx_rx_int_en.s.reserved_29_63 */
59 gmx_rx_int_en.s.hg2cc = 1;
60 gmx_rx_int_en.s.hg2fld = 1;
61 gmx_rx_int_en.s.undat = 1;
62 gmx_rx_int_en.s.uneop = 1;
63 gmx_rx_int_en.s.unsop = 1;
64 gmx_rx_int_en.s.bad_term = 1;
65 gmx_rx_int_en.s.bad_seq = 1;
66 gmx_rx_int_en.s.rem_fault = 1;
67 gmx_rx_int_en.s.loc_fault = 1;
68 gmx_rx_int_en.s.pause_drp = 1;
69 /* Skipping gmx_rx_int_en.s.reserved_16_18 */
70 /*gmx_rx_int_en.s.ifgerr = 1; */
71 /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
72 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
73 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
74 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
75 gmx_rx_int_en.s.ovrerr = 1;
76 /* Skipping gmx_rx_int_en.s.reserved_9_9 */
77 gmx_rx_int_en.s.skperr = 1;
78 gmx_rx_int_en.s.rcverr = 1;
79 /* Skipping gmx_rx_int_en.s.reserved_5_6 */
80 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
81 gmx_rx_int_en.s.jabber = 1;
82 /* Skipping gmx_rx_int_en.s.reserved_2_2 */
83 gmx_rx_int_en.s.carext = 1;
84 /* Skipping gmx_rx_int_en.s.reserved_0_0 */
85 }
86 if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
87 /* Skipping gmx_rx_int_en.s.reserved_19_63 */
88 /*gmx_rx_int_en.s.phy_dupx = 1; */
89 /*gmx_rx_int_en.s.phy_spd = 1; */
90 /*gmx_rx_int_en.s.phy_link = 1; */
91 /*gmx_rx_int_en.s.ifgerr = 1; */
92 /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
93 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
94 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
95 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
96 gmx_rx_int_en.s.ovrerr = 1;
97 gmx_rx_int_en.s.niberr = 1;
98 gmx_rx_int_en.s.skperr = 1;
99 gmx_rx_int_en.s.rcverr = 1;
100 /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
101 gmx_rx_int_en.s.alnerr = 1;
102 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
103 gmx_rx_int_en.s.jabber = 1;
104 gmx_rx_int_en.s.maxerr = 1;
105 gmx_rx_int_en.s.carext = 1;
106 gmx_rx_int_en.s.minerr = 1;
107 }
108 if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
109 /* Skipping gmx_rx_int_en.s.reserved_20_63 */
110 gmx_rx_int_en.s.pause_drp = 1;
111 /*gmx_rx_int_en.s.phy_dupx = 1; */
112 /*gmx_rx_int_en.s.phy_spd = 1; */
113 /*gmx_rx_int_en.s.phy_link = 1; */
114 /*gmx_rx_int_en.s.ifgerr = 1; */
115 /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
116 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
117 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
118 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
119 gmx_rx_int_en.s.ovrerr = 1;
120 gmx_rx_int_en.s.niberr = 1;
121 gmx_rx_int_en.s.skperr = 1;
122 gmx_rx_int_en.s.rcverr = 1;
123 /* Skipping gmx_rx_int_en.s.reserved_6_6 */
124 gmx_rx_int_en.s.alnerr = 1;
125 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
126 gmx_rx_int_en.s.jabber = 1;
127 /* Skipping gmx_rx_int_en.s.reserved_2_2 */
128 gmx_rx_int_en.s.carext = 1;
129 /* Skipping gmx_rx_int_en.s.reserved_0_0 */
130 }
131 if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
132 /* Skipping gmx_rx_int_en.s.reserved_19_63 */
133 /*gmx_rx_int_en.s.phy_dupx = 1; */
134 /*gmx_rx_int_en.s.phy_spd = 1; */
135 /*gmx_rx_int_en.s.phy_link = 1; */
136 /*gmx_rx_int_en.s.ifgerr = 1; */
137 /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
138 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
139 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
140 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
141 gmx_rx_int_en.s.ovrerr = 1;
142 gmx_rx_int_en.s.niberr = 1;
143 gmx_rx_int_en.s.skperr = 1;
144 gmx_rx_int_en.s.rcverr = 1;
145 /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
146 gmx_rx_int_en.s.alnerr = 1;
147 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
148 gmx_rx_int_en.s.jabber = 1;
149 gmx_rx_int_en.s.maxerr = 1;
150 gmx_rx_int_en.s.carext = 1;
151 gmx_rx_int_en.s.minerr = 1;
152 }
153 if (OCTEON_IS_MODEL(OCTEON_CN31XX)) {
154 /* Skipping gmx_rx_int_en.s.reserved_19_63 */
155 /*gmx_rx_int_en.s.phy_dupx = 1; */
156 /*gmx_rx_int_en.s.phy_spd = 1; */
157 /*gmx_rx_int_en.s.phy_link = 1; */
158 /*gmx_rx_int_en.s.ifgerr = 1; */
159 /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
160 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
161 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
162 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
163 gmx_rx_int_en.s.ovrerr = 1;
164 gmx_rx_int_en.s.niberr = 1;
165 gmx_rx_int_en.s.skperr = 1;
166 gmx_rx_int_en.s.rcverr = 1;
167 /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
168 gmx_rx_int_en.s.alnerr = 1;
169 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
170 gmx_rx_int_en.s.jabber = 1;
171 gmx_rx_int_en.s.maxerr = 1;
172 gmx_rx_int_en.s.carext = 1;
173 gmx_rx_int_en.s.minerr = 1;
174 }
175 if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
176 /* Skipping gmx_rx_int_en.s.reserved_20_63 */
177 gmx_rx_int_en.s.pause_drp = 1;
178 /*gmx_rx_int_en.s.phy_dupx = 1; */
179 /*gmx_rx_int_en.s.phy_spd = 1; */
180 /*gmx_rx_int_en.s.phy_link = 1; */
181 /*gmx_rx_int_en.s.ifgerr = 1; */
182 /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
183 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
184 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
185 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
186 gmx_rx_int_en.s.ovrerr = 1;
187 gmx_rx_int_en.s.niberr = 1;
188 gmx_rx_int_en.s.skperr = 1;
189 gmx_rx_int_en.s.rcverr = 1;
190 /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
191 gmx_rx_int_en.s.alnerr = 1;
192 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
193 gmx_rx_int_en.s.jabber = 1;
194 gmx_rx_int_en.s.maxerr = 1;
195 gmx_rx_int_en.s.carext = 1;
196 gmx_rx_int_en.s.minerr = 1;
197 }
198 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
199 /* Skipping gmx_rx_int_en.s.reserved_29_63 */
200 gmx_rx_int_en.s.hg2cc = 1;
201 gmx_rx_int_en.s.hg2fld = 1;
202 gmx_rx_int_en.s.undat = 1;
203 gmx_rx_int_en.s.uneop = 1;
204 gmx_rx_int_en.s.unsop = 1;
205 gmx_rx_int_en.s.bad_term = 1;
206 gmx_rx_int_en.s.bad_seq = 0;
207 gmx_rx_int_en.s.rem_fault = 1;
208 gmx_rx_int_en.s.loc_fault = 0;
209 gmx_rx_int_en.s.pause_drp = 1;
210 /* Skipping gmx_rx_int_en.s.reserved_16_18 */
211 /*gmx_rx_int_en.s.ifgerr = 1; */
212 /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
213 /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
214 /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
215 /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
216 gmx_rx_int_en.s.ovrerr = 1;
217 /* Skipping gmx_rx_int_en.s.reserved_9_9 */
218 gmx_rx_int_en.s.skperr = 1;
219 gmx_rx_int_en.s.rcverr = 1;
220 /* Skipping gmx_rx_int_en.s.reserved_5_6 */
221 /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
222 gmx_rx_int_en.s.jabber = 1;
223 /* Skipping gmx_rx_int_en.s.reserved_2_2 */
224 gmx_rx_int_en.s.carext = 1;
225 /* Skipping gmx_rx_int_en.s.reserved_0_0 */
226 }
227 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64);
228}
229/**
230 * __cvmx_interrupt_pcsx_intx_en_reg_enable enables all interrupt bits in cvmx_pcsx_intx_en_reg_t
231 */
232void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block)
233{
234 union cvmx_pcsx_intx_en_reg pcs_int_en_reg;
235 cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block),
236 cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block)));
237 pcs_int_en_reg.u64 = 0;
238 if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
239 /* Skipping pcs_int_en_reg.s.reserved_12_63 */
240 /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */
241 pcs_int_en_reg.s.sync_bad_en = 1;
242 pcs_int_en_reg.s.an_bad_en = 1;
243 pcs_int_en_reg.s.rxlock_en = 1;
244 pcs_int_en_reg.s.rxbad_en = 1;
245 /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */
246 pcs_int_en_reg.s.txbad_en = 1;
247 pcs_int_en_reg.s.txfifo_en = 1;
248 pcs_int_en_reg.s.txfifu_en = 1;
249 pcs_int_en_reg.s.an_err_en = 1;
250 /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */
251 /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */
252 }
253 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
254 /* Skipping pcs_int_en_reg.s.reserved_12_63 */
255 /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */
256 pcs_int_en_reg.s.sync_bad_en = 1;
257 pcs_int_en_reg.s.an_bad_en = 1;
258 pcs_int_en_reg.s.rxlock_en = 1;
259 pcs_int_en_reg.s.rxbad_en = 1;
260 /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */
261 pcs_int_en_reg.s.txbad_en = 1;
262 pcs_int_en_reg.s.txfifo_en = 1;
263 pcs_int_en_reg.s.txfifu_en = 1;
264 pcs_int_en_reg.s.an_err_en = 1;
265 /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */
266 /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */
267 }
268 cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64);
269}
270/**
271 * __cvmx_interrupt_pcsxx_int_en_reg_enable enables all interrupt bits in cvmx_pcsxx_int_en_reg_t
272 */
273void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index)
274{
275 union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
276 cvmx_write_csr(CVMX_PCSXX_INT_REG(index),
277 cvmx_read_csr(CVMX_PCSXX_INT_REG(index)));
278 pcsx_int_en_reg.u64 = 0;
279 if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
280 /* Skipping pcsx_int_en_reg.s.reserved_6_63 */
281 pcsx_int_en_reg.s.algnlos_en = 1;
282 pcsx_int_en_reg.s.synlos_en = 1;
283 pcsx_int_en_reg.s.bitlckls_en = 1;
284 pcsx_int_en_reg.s.rxsynbad_en = 1;
285 pcsx_int_en_reg.s.rxbad_en = 1;
286 pcsx_int_en_reg.s.txflt_en = 1;
287 }
288 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
289 /* Skipping pcsx_int_en_reg.s.reserved_6_63 */
290 pcsx_int_en_reg.s.algnlos_en = 1;
291 pcsx_int_en_reg.s.synlos_en = 1;
292 pcsx_int_en_reg.s.bitlckls_en = 0; /* Happens if XAUI module is not installed */
293 pcsx_int_en_reg.s.rxsynbad_en = 1;
294 pcsx_int_en_reg.s.rxbad_en = 1;
295 pcsx_int_en_reg.s.txflt_en = 1;
296 }
297 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64);
298}
299
300/**
301 * __cvmx_interrupt_spxx_int_msk_enable enables all interrupt bits in cvmx_spxx_int_msk_t
302 */
303void __cvmx_interrupt_spxx_int_msk_enable(int index)
304{
305 union cvmx_spxx_int_msk spx_int_msk;
306 cvmx_write_csr(CVMX_SPXX_INT_REG(index),
307 cvmx_read_csr(CVMX_SPXX_INT_REG(index)));
308 spx_int_msk.u64 = 0;
309 if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
310 /* Skipping spx_int_msk.s.reserved_12_63 */
311 spx_int_msk.s.calerr = 1;
312 spx_int_msk.s.syncerr = 1;
313 spx_int_msk.s.diperr = 1;
314 spx_int_msk.s.tpaovr = 1;
315 spx_int_msk.s.rsverr = 1;
316 spx_int_msk.s.drwnng = 1;
317 spx_int_msk.s.clserr = 1;
318 spx_int_msk.s.spiovr = 1;
319 /* Skipping spx_int_msk.s.reserved_2_3 */
320 spx_int_msk.s.abnorm = 1;
321 spx_int_msk.s.prtnxa = 1;
322 }
323 if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
324 /* Skipping spx_int_msk.s.reserved_12_63 */
325 spx_int_msk.s.calerr = 1;
326 spx_int_msk.s.syncerr = 1;
327 spx_int_msk.s.diperr = 1;
328 spx_int_msk.s.tpaovr = 1;
329 spx_int_msk.s.rsverr = 1;
330 spx_int_msk.s.drwnng = 1;
331 spx_int_msk.s.clserr = 1;
332 spx_int_msk.s.spiovr = 1;
333 /* Skipping spx_int_msk.s.reserved_2_3 */
334 spx_int_msk.s.abnorm = 1;
335 spx_int_msk.s.prtnxa = 1;
336 }
337 cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64);
338}
339/**
340 * __cvmx_interrupt_stxx_int_msk_enable enables all interrupt bits in cvmx_stxx_int_msk_t
341 */
342void __cvmx_interrupt_stxx_int_msk_enable(int index)
343{
344 union cvmx_stxx_int_msk stx_int_msk;
345 cvmx_write_csr(CVMX_STXX_INT_REG(index),
346 cvmx_read_csr(CVMX_STXX_INT_REG(index)));
347 stx_int_msk.u64 = 0;
348 if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
349 /* Skipping stx_int_msk.s.reserved_8_63 */
350 stx_int_msk.s.frmerr = 1;
351 stx_int_msk.s.unxfrm = 1;
352 stx_int_msk.s.nosync = 1;
353 stx_int_msk.s.diperr = 1;
354 stx_int_msk.s.datovr = 1;
355 stx_int_msk.s.ovrbst = 1;
356 stx_int_msk.s.calpar1 = 1;
357 stx_int_msk.s.calpar0 = 1;
358 }
359 if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
360 /* Skipping stx_int_msk.s.reserved_8_63 */
361 stx_int_msk.s.frmerr = 1;
362 stx_int_msk.s.unxfrm = 1;
363 stx_int_msk.s.nosync = 1;
364 stx_int_msk.s.diperr = 1;
365 stx_int_msk.s.datovr = 1;
366 stx_int_msk.s.ovrbst = 1;
367 stx_int_msk.s.calpar1 = 1;
368 stx_int_msk.s.calpar0 = 1;
369 }
370 cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64);
371}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
new file mode 100644
index 000000000000..bea7538ea4e9
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
@@ -0,0 +1,140 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Utility functions to decode Octeon's RSL_INT_BLOCKS
30 * interrupts into error messages.
31 */
32
33#include <asm/octeon/octeon.h>
34
35#include <asm/octeon/cvmx-asxx-defs.h>
36#include <asm/octeon/cvmx-gmxx-defs.h>
37
38#ifndef PRINT_ERROR
39#define PRINT_ERROR(format, ...)
40#endif
41
42void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block);
43
44/**
45 * Enable ASX error interrupts that exist on CN3XXX, CN50XX, and
46 * CN58XX.
47 *
48 * @block: Interface to enable 0-1
49 */
50void __cvmx_interrupt_asxx_enable(int block)
51{
52 int mask;
53 union cvmx_asxx_int_en csr;
54 /*
55 * CN38XX and CN58XX have two interfaces with 4 ports per
56 * interface. All other chips have a max of 3 ports on
57 * interface 0
58 */
59 if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
60 mask = 0xf; /* Set enables for 4 ports */
61 else
62 mask = 0x7; /* Set enables for 3 ports */
63
64 /* Enable interface interrupts */
65 csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block));
66 csr.s.txpsh = mask;
67 csr.s.txpop = mask;
68 csr.s.ovrflw = mask;
69 cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64);
70}
71/**
72 * Enable GMX error reporting for the supplied interface
73 *
74 * @interface: Interface to enable
75 */
76void __cvmx_interrupt_gmxx_enable(int interface)
77{
78 union cvmx_gmxx_inf_mode mode;
79 union cvmx_gmxx_tx_int_en gmx_tx_int_en;
80 int num_ports;
81 int index;
82
83 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
84
85 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
86 if (mode.s.en) {
87 switch (mode.cn56xx.mode) {
88 case 1: /* XAUI */
89 num_ports = 1;
90 break;
91 case 2: /* SGMII */
92 case 3: /* PICMG */
93 num_ports = 4;
94 break;
95 default: /* Disabled */
96 num_ports = 0;
97 break;
98 }
99 } else
100 num_ports = 0;
101 } else {
102 if (mode.s.en) {
103 if (OCTEON_IS_MODEL(OCTEON_CN38XX)
104 || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
105 /*
106 * SPI on CN38XX and CN58XX report all
107 * errors through port 0. RGMII needs
108 * to check all 4 ports
109 */
110 if (mode.s.type)
111 num_ports = 1;
112 else
113 num_ports = 4;
114 } else {
115 /*
116 * CN30XX, CN31XX, and CN50XX have two
117 * or three ports. GMII and MII has 2,
118 * RGMII has three
119 */
120 if (mode.s.type)
121 num_ports = 2;
122 else
123 num_ports = 3;
124 }
125 } else
126 num_ports = 0;
127 }
128
129 gmx_tx_int_en.u64 = 0;
130 if (num_ports) {
131 if (OCTEON_IS_MODEL(OCTEON_CN38XX)
132 || OCTEON_IS_MODEL(OCTEON_CN58XX))
133 gmx_tx_int_en.s.ncb_nxa = 1;
134 gmx_tx_int_en.s.pko_nxa = 1;
135 }
136 gmx_tx_int_en.s.undflw = (1 << num_ports) - 1;
137 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
138 for (index = 0; index < num_ports; index++)
139 __cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface);
140}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c
new file mode 100644
index 000000000000..f557084b1092
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c
@@ -0,0 +1,506 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Support library for the hardware Packet Output unit.
30 */
31
32#include <asm/octeon/octeon.h>
33
34#include <asm/octeon/cvmx-config.h>
35#include <asm/octeon/cvmx-pko.h>
36#include <asm/octeon/cvmx-helper.h>
37
38/**
39 * Internal state of packet output
40 */
41
42/**
43 * Call before any other calls to initialize the packet
44 * output system. This does chip global config, and should only be
45 * done by one core.
46 */
47
48void cvmx_pko_initialize_global(void)
49{
50 int i;
51 uint64_t priority = 8;
52 union cvmx_pko_reg_cmd_buf config;
53
54 /*
55 * Set the size of the PKO command buffers to an odd number of
56 * 64bit words. This allows the normal two word send to stay
57 * aligned and never span a comamnd word buffer.
58 */
59 config.u64 = 0;
60 config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
61 config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1;
62
63 cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);
64
65 for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++)
66 cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1,
67 &priority);
68
69 /*
70 * If we aren't using all of the queues optimize PKO's
71 * internal memory.
72 */
73 if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)
74 || OCTEON_IS_MODEL(OCTEON_CN56XX)
75 || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
76 int num_interfaces = cvmx_helper_get_number_of_interfaces();
77 int last_port =
78 cvmx_helper_get_last_ipd_port(num_interfaces - 1);
79 int max_queues =
80 cvmx_pko_get_base_queue(last_port) +
81 cvmx_pko_get_num_queues(last_port);
82 if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
83 if (max_queues <= 32)
84 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
85 else if (max_queues <= 64)
86 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
87 } else {
88 if (max_queues <= 64)
89 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
90 else if (max_queues <= 128)
91 cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
92 }
93 }
94}
95
96/**
97 * This function does per-core initialization required by the PKO routines.
98 * This must be called on all cores that will do packet output, and must
99 * be called after the FPA has been initialized and filled with pages.
100 *
101 * Returns 0 on success
102 * !0 on failure
103 */
104int cvmx_pko_initialize_local(void)
105{
106 /* Nothing to do */
107 return 0;
108}
109
110/**
111 * Enables the packet output hardware. It must already be
112 * configured.
113 */
114void cvmx_pko_enable(void)
115{
116 union cvmx_pko_reg_flags flags;
117
118 flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
119 if (flags.s.ena_pko)
120 cvmx_dprintf
121 ("Warning: Enabling PKO when PKO already enabled.\n");
122
123 flags.s.ena_dwb = 1;
124 flags.s.ena_pko = 1;
125 /*
126 * always enable big endian for 3-word command. Does nothing
127 * for 2-word.
128 */
129 flags.s.store_be = 1;
130 cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64);
131}
132
133/**
134 * Disables the packet output. Does not affect any configuration.
135 */
136void cvmx_pko_disable(void)
137{
138 union cvmx_pko_reg_flags pko_reg_flags;
139 pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
140 pko_reg_flags.s.ena_pko = 0;
141 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
142}
143
144
145/**
146 * Reset the packet output.
147 */
148static void __cvmx_pko_reset(void)
149{
150 union cvmx_pko_reg_flags pko_reg_flags;
151 pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
152 pko_reg_flags.s.reset = 1;
153 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
154}
155
156/**
157 * Shutdown and free resources required by packet output.
158 */
159void cvmx_pko_shutdown(void)
160{
161 union cvmx_pko_mem_queue_ptrs config;
162 int queue;
163
164 cvmx_pko_disable();
165
166 for (queue = 0; queue < CVMX_PKO_MAX_OUTPUT_QUEUES; queue++) {
167 config.u64 = 0;
168 config.s.tail = 1;
169 config.s.index = 0;
170 config.s.port = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID;
171 config.s.queue = queue & 0x7f;
172 config.s.qos_mask = 0;
173 config.s.buf_ptr = 0;
174 if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
175 union cvmx_pko_reg_queue_ptrs1 config1;
176 config1.u64 = 0;
177 config1.s.qid7 = queue >> 7;
178 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
179 }
180 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
181 cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue));
182 }
183 __cvmx_pko_reset();
184}
185
186/**
187 * Configure a output port and the associated queues for use.
188 *
189 * @port: Port to configure.
190 * @base_queue: First queue number to associate with this port.
191 * @num_queues: Number of queues to associate with this port
192 * @priority: Array of priority levels for each queue. Values are
193 * allowed to be 0-8. A value of 8 get 8 times the traffic
194 * of a value of 1. A value of 0 indicates that no rounds
195 * will be participated in. These priorities can be changed
196 * on the fly while the pko is enabled. A priority of 9
197 * indicates that static priority should be used. If static
198 * priority is used all queues with static priority must be
199 * contiguous starting at the base_queue, and lower numbered
200 * queues have higher priority than higher numbered queues.
201 * There must be num_queues elements in the array.
202 */
203cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
204 uint64_t num_queues,
205 const uint64_t priority[])
206{
207 cvmx_pko_status_t result_code;
208 uint64_t queue;
209 union cvmx_pko_mem_queue_ptrs config;
210 union cvmx_pko_reg_queue_ptrs1 config1;
211 int static_priority_base = -1;
212 int static_priority_end = -1;
213
214 if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS)
215 && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) {
216 cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n",
217 (unsigned long long)port);
218 return CVMX_PKO_INVALID_PORT;
219 }
220
221 if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES) {
222 cvmx_dprintf
223 ("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n",
224 (unsigned long long)(base_queue + num_queues));
225 return CVMX_PKO_INVALID_QUEUE;
226 }
227
228 if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) {
229 /*
230 * Validate the static queue priority setup and set
231 * static_priority_base and static_priority_end
232 * accordingly.
233 */
234 for (queue = 0; queue < num_queues; queue++) {
235 /* Find first queue of static priority */
236 if (static_priority_base == -1
237 && priority[queue] ==
238 CVMX_PKO_QUEUE_STATIC_PRIORITY)
239 static_priority_base = queue;
240 /* Find last queue of static priority */
241 if (static_priority_base != -1
242 && static_priority_end == -1
243 && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY
244 && queue)
245 static_priority_end = queue - 1;
246 else if (static_priority_base != -1
247 && static_priority_end == -1
248 && queue == num_queues - 1)
249 /* all queues are static priority */
250 static_priority_end = queue;
251 /*
252 * Check to make sure all static priority
253 * queues are contiguous. Also catches some
254 * cases of static priorites not starting at
255 * queue 0.
256 */
257 if (static_priority_end != -1
258 && (int)queue > static_priority_end
259 && priority[queue] ==
260 CVMX_PKO_QUEUE_STATIC_PRIORITY) {
261 cvmx_dprintf("ERROR: cvmx_pko_config_port: "
262 "Static priority queues aren't "
263 "contiguous or don't start at "
264 "base queue. q: %d, eq: %d\n",
265 (int)queue, static_priority_end);
266 return CVMX_PKO_INVALID_PRIORITY;
267 }
268 }
269 if (static_priority_base > 0) {
270 cvmx_dprintf("ERROR: cvmx_pko_config_port: Static "
271 "priority queues don't start at base "
272 "queue. sq: %d\n",
273 static_priority_base);
274 return CVMX_PKO_INVALID_PRIORITY;
275 }
276#if 0
277 cvmx_dprintf("Port %d: Static priority queue base: %d, "
278 "end: %d\n", port,
279 static_priority_base, static_priority_end);
280#endif
281 }
282 /*
283 * At this point, static_priority_base and static_priority_end
284 * are either both -1, or are valid start/end queue
285 * numbers.
286 */
287
288 result_code = CVMX_PKO_SUCCESS;
289
290#ifdef PKO_DEBUG
291 cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues,
292 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0,
293 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1);
294#endif
295
296 for (queue = 0; queue < num_queues; queue++) {
297 uint64_t *buf_ptr = NULL;
298
299 config1.u64 = 0;
300 config1.s.idx3 = queue >> 3;
301 config1.s.qid7 = (base_queue + queue) >> 7;
302
303 config.u64 = 0;
304 config.s.tail = queue == (num_queues - 1);
305 config.s.index = queue;
306 config.s.port = port;
307 config.s.queue = base_queue + queue;
308
309 if (!cvmx_octeon_is_pass1()) {
310 config.s.static_p = static_priority_base >= 0;
311 config.s.static_q = (int)queue <= static_priority_end;
312 config.s.s_tail = (int)queue == static_priority_end;
313 }
314 /*
315 * Convert the priority into an enable bit field. Try
316 * to space the bits out evenly so the packet don't
317 * get grouped up
318 */
319 switch ((int)priority[queue]) {
320 case 0:
321 config.s.qos_mask = 0x00;
322 break;
323 case 1:
324 config.s.qos_mask = 0x01;
325 break;
326 case 2:
327 config.s.qos_mask = 0x11;
328 break;
329 case 3:
330 config.s.qos_mask = 0x49;
331 break;
332 case 4:
333 config.s.qos_mask = 0x55;
334 break;
335 case 5:
336 config.s.qos_mask = 0x57;
337 break;
338 case 6:
339 config.s.qos_mask = 0x77;
340 break;
341 case 7:
342 config.s.qos_mask = 0x7f;
343 break;
344 case 8:
345 config.s.qos_mask = 0xff;
346 break;
347 case CVMX_PKO_QUEUE_STATIC_PRIORITY:
348 /* Pass 1 will fall through to the error case */
349 if (!cvmx_octeon_is_pass1()) {
350 config.s.qos_mask = 0xff;
351 break;
352 }
353 default:
354 cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid "
355 "priority %llu\n",
356 (unsigned long long)priority[queue]);
357 config.s.qos_mask = 0xff;
358 result_code = CVMX_PKO_INVALID_PRIORITY;
359 break;
360 }
361
362 if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) {
363 cvmx_cmd_queue_result_t cmd_res =
364 cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO
365 (base_queue + queue),
366 CVMX_PKO_MAX_QUEUE_DEPTH,
367 CVMX_FPA_OUTPUT_BUFFER_POOL,
368 CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE
369 -
370 CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST
371 * 8);
372 if (cmd_res != CVMX_CMD_QUEUE_SUCCESS) {
373 switch (cmd_res) {
374 case CVMX_CMD_QUEUE_NO_MEMORY:
375 cvmx_dprintf("ERROR: "
376 "cvmx_pko_config_port: "
377 "Unable to allocate "
378 "output buffer.\n");
379 return CVMX_PKO_NO_MEMORY;
380 case CVMX_CMD_QUEUE_ALREADY_SETUP:
381 cvmx_dprintf
382 ("ERROR: cvmx_pko_config_port: Port already setup.\n");
383 return CVMX_PKO_PORT_ALREADY_SETUP;
384 case CVMX_CMD_QUEUE_INVALID_PARAM:
385 default:
386 cvmx_dprintf
387 ("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n");
388 return CVMX_PKO_CMD_QUEUE_INIT_ERROR;
389 }
390 }
391
392 buf_ptr =
393 (uint64_t *)
394 cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO
395 (base_queue + queue));
396 config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr);
397 } else
398 config.s.buf_ptr = 0;
399
400 CVMX_SYNCWS;
401
402 if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
403 cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
404 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
405 }
406
407 return result_code;
408}
409
410#ifdef PKO_DEBUG
411/**
412 * Show map of ports -> queues for different cores.
413 */
414void cvmx_pko_show_queue_map()
415{
416 int core, port;
417 int pko_output_ports = 36;
418
419 cvmx_dprintf("port");
420 for (port = 0; port < pko_output_ports; port++)
421 cvmx_dprintf("%3d ", port);
422 cvmx_dprintf("\n");
423
424 for (core = 0; core < CVMX_MAX_CORES; core++) {
425 cvmx_dprintf("\n%2d: ", core);
426 for (port = 0; port < pko_output_ports; port++) {
427 cvmx_dprintf("%3d ",
428 cvmx_pko_get_base_queue_per_core(port,
429 core));
430 }
431 }
432 cvmx_dprintf("\n");
433}
434#endif
435
436/**
437 * Rate limit a PKO port to a max packets/sec. This function is only
438 * supported on CN51XX and higher, excluding CN58XX.
439 *
440 * @port: Port to rate limit
441 * @packets_s: Maximum packet/sec
442 * @burst: Maximum number of packets to burst in a row before rate
443 * limiting cuts in.
444 *
445 * Returns Zero on success, negative on failure
446 */
447int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst)
448{
449 union cvmx_pko_mem_port_rate0 pko_mem_port_rate0;
450 union cvmx_pko_mem_port_rate1 pko_mem_port_rate1;
451
452 pko_mem_port_rate0.u64 = 0;
453 pko_mem_port_rate0.s.pid = port;
454 pko_mem_port_rate0.s.rate_pkt =
455 cvmx_sysinfo_get()->cpu_clock_hz / packets_s / 16;
456 /* No cost per word since we are limited by packets/sec, not bits/sec */
457 pko_mem_port_rate0.s.rate_word = 0;
458
459 pko_mem_port_rate1.u64 = 0;
460 pko_mem_port_rate1.s.pid = port;
461 pko_mem_port_rate1.s.rate_lim =
462 ((uint64_t) pko_mem_port_rate0.s.rate_pkt * burst) >> 8;
463
464 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
465 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
466 return 0;
467}
468
469/**
470 * Rate limit a PKO port to a max bits/sec. This function is only
471 * supported on CN51XX and higher, excluding CN58XX.
472 *
473 * @port: Port to rate limit
474 * @bits_s: PKO rate limit in bits/sec
475 * @burst: Maximum number of bits to burst before rate
476 * limiting cuts in.
477 *
478 * Returns Zero on success, negative on failure
479 */
480int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
481{
482 union cvmx_pko_mem_port_rate0 pko_mem_port_rate0;
483 union cvmx_pko_mem_port_rate1 pko_mem_port_rate1;
484 uint64_t clock_rate = cvmx_sysinfo_get()->cpu_clock_hz;
485 uint64_t tokens_per_bit = clock_rate * 16 / bits_s;
486
487 pko_mem_port_rate0.u64 = 0;
488 pko_mem_port_rate0.s.pid = port;
489 /*
490 * Each packet has a 12 bytes of interframe gap, an 8 byte
491 * preamble, and a 4 byte CRC. These are not included in the
492 * per word count. Multiply by 8 to covert to bits and divide
493 * by 256 for limit granularity.
494 */
495 pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256;
496 /* Each 8 byte word has 64bits */
497 pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit;
498
499 pko_mem_port_rate1.u64 = 0;
500 pko_mem_port_rate1.s.pid = port;
501 pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256;
502
503 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
504 cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
505 return 0;
506}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c
new file mode 100644
index 000000000000..74afb1710cd9
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c
@@ -0,0 +1,667 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Support library for the SPI
31 */
32#include <asm/octeon/octeon.h>
33
34#include <asm/octeon/cvmx-config.h>
35
36#include <asm/octeon/cvmx-pko.h>
37#include <asm/octeon/cvmx-spi.h>
38
39#include <asm/octeon/cvmx-spxx-defs.h>
40#include <asm/octeon/cvmx-stxx-defs.h>
41#include <asm/octeon/cvmx-srxx-defs.h>
42
43#define INVOKE_CB(function_p, args...) \
44 do { \
45 if (function_p) { \
46 res = function_p(args); \
47 if (res) \
48 return res; \
49 } \
50 } while (0)
51
52#if CVMX_ENABLE_DEBUG_PRINTS
53static const char *modes[] =
54 { "UNKNOWN", "TX Halfplex", "Rx Halfplex", "Duplex" };
55#endif
56
57/* Default callbacks, can be overridden
58 * using cvmx_spi_get_callbacks/cvmx_spi_set_callbacks
59 */
60static cvmx_spi_callbacks_t cvmx_spi_callbacks = {
61 .reset_cb = cvmx_spi_reset_cb,
62 .calendar_setup_cb = cvmx_spi_calendar_setup_cb,
63 .clock_detect_cb = cvmx_spi_clock_detect_cb,
64 .training_cb = cvmx_spi_training_cb,
65 .calendar_sync_cb = cvmx_spi_calendar_sync_cb,
66 .interface_up_cb = cvmx_spi_interface_up_cb
67};
68
69/**
70 * Get current SPI4 initialization callbacks
71 *
72 * @callbacks: Pointer to the callbacks structure.to fill
73 *
74 * Returns Pointer to cvmx_spi_callbacks_t structure.
75 */
76void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks)
77{
78 memcpy(callbacks, &cvmx_spi_callbacks, sizeof(cvmx_spi_callbacks));
79}
80
81/**
82 * Set new SPI4 initialization callbacks
83 *
84 * @new_callbacks: Pointer to an updated callbacks structure.
85 */
86void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks)
87{
88 memcpy(&cvmx_spi_callbacks, new_callbacks, sizeof(cvmx_spi_callbacks));
89}
90
91/**
92 * Initialize and start the SPI interface.
93 *
94 * @interface: The identifier of the packet interface to configure and
95 * use as a SPI interface.
96 * @mode: The operating mode for the SPI interface. The interface
97 * can operate as a full duplex (both Tx and Rx data paths
98 * active) or as a halfplex (either the Tx data path is
99 * active or the Rx data path is active, but not both).
100 * @timeout: Timeout to wait for clock synchronization in seconds
101 * @num_ports: Number of SPI ports to configure
102 *
103 * Returns Zero on success, negative of failure.
104 */
105int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout,
106 int num_ports)
107{
108 int res = -1;
109
110 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
111 return res;
112
113 /* Callback to perform SPI4 reset */
114 INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode);
115
116 /* Callback to perform calendar setup */
117 INVOKE_CB(cvmx_spi_callbacks.calendar_setup_cb, interface, mode,
118 num_ports);
119
120 /* Callback to perform clock detection */
121 INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
122
123 /* Callback to perform SPI4 link training */
124 INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout);
125
126 /* Callback to perform calendar sync */
127 INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode,
128 timeout);
129
130 /* Callback to handle interface coming up */
131 INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode);
132
133 return res;
134}
135
136/**
137 * This routine restarts the SPI interface after it has lost synchronization
138 * with its correspondent system.
139 *
140 * @interface: The identifier of the packet interface to configure and
141 * use as a SPI interface.
142 * @mode: The operating mode for the SPI interface. The interface
143 * can operate as a full duplex (both Tx and Rx data paths
144 * active) or as a halfplex (either the Tx data path is
145 * active or the Rx data path is active, but not both).
146 * @timeout: Timeout to wait for clock synchronization in seconds
147 *
148 * Returns Zero on success, negative of failure.
149 */
150int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
151{
152 int res = -1;
153
154 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
155 return res;
156
157 cvmx_dprintf("SPI%d: Restart %s\n", interface, modes[mode]);
158
159 /* Callback to perform SPI4 reset */
160 INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode);
161
162 /* NOTE: Calendar setup is not performed during restart */
163 /* Refer to cvmx_spi_start_interface() for the full sequence */
164
165 /* Callback to perform clock detection */
166 INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
167
168 /* Callback to perform SPI4 link training */
169 INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout);
170
171 /* Callback to perform calendar sync */
172 INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode,
173 timeout);
174
175 /* Callback to handle interface coming up */
176 INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode);
177
178 return res;
179}
180
181/**
182 * Callback to perform SPI4 reset
183 *
184 * @interface: The identifier of the packet interface to configure and
185 * use as a SPI interface.
186 * @mode: The operating mode for the SPI interface. The interface
187 * can operate as a full duplex (both Tx and Rx data paths
188 * active) or as a halfplex (either the Tx data path is
189 * active or the Rx data path is active, but not both).
190 *
191 * Returns Zero on success, non-zero error code on failure (will cause
192 * SPI initialization to abort)
193 */
194int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
195{
196 union cvmx_spxx_dbg_deskew_ctl spxx_dbg_deskew_ctl;
197 union cvmx_spxx_clk_ctl spxx_clk_ctl;
198 union cvmx_spxx_bist_stat spxx_bist_stat;
199 union cvmx_spxx_int_msk spxx_int_msk;
200 union cvmx_stxx_int_msk stxx_int_msk;
201 union cvmx_spxx_trn4_ctl spxx_trn4_ctl;
202 int index;
203 uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
204
205 /* Disable SPI error events while we run BIST */
206 spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));
207 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0);
208 stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));
209 cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0);
210
211 /* Run BIST in the SPI interface */
212 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0);
213 cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0);
214 spxx_clk_ctl.u64 = 0;
215 spxx_clk_ctl.s.runbist = 1;
216 cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
217 cvmx_wait(10 * MS);
218 spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));
219 if (spxx_bist_stat.s.stat0)
220 cvmx_dprintf
221 ("ERROR SPI%d: BIST failed on receive datapath FIFO\n",
222 interface);
223 if (spxx_bist_stat.s.stat1)
224 cvmx_dprintf("ERROR SPI%d: BIST failed on RX calendar table\n",
225 interface);
226 if (spxx_bist_stat.s.stat2)
227 cvmx_dprintf("ERROR SPI%d: BIST failed on TX calendar table\n",
228 interface);
229
230 /* Clear the calendar table after BIST to fix parity errors */
231 for (index = 0; index < 32; index++) {
232 union cvmx_srxx_spi4_calx srxx_spi4_calx;
233 union cvmx_stxx_spi4_calx stxx_spi4_calx;
234
235 srxx_spi4_calx.u64 = 0;
236 srxx_spi4_calx.s.oddpar = 1;
237 cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface),
238 srxx_spi4_calx.u64);
239
240 stxx_spi4_calx.u64 = 0;
241 stxx_spi4_calx.s.oddpar = 1;
242 cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface),
243 stxx_spi4_calx.u64);
244 }
245
246 /* Re enable reporting of error interrupts */
247 cvmx_write_csr(CVMX_SPXX_INT_REG(interface),
248 cvmx_read_csr(CVMX_SPXX_INT_REG(interface)));
249 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);
250 cvmx_write_csr(CVMX_STXX_INT_REG(interface),
251 cvmx_read_csr(CVMX_STXX_INT_REG(interface)));
252 cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);
253
254 /* Setup the CLKDLY right in the middle */
255 spxx_clk_ctl.u64 = 0;
256 spxx_clk_ctl.s.seetrn = 0;
257 spxx_clk_ctl.s.clkdly = 0x10;
258 spxx_clk_ctl.s.runbist = 0;
259 spxx_clk_ctl.s.statdrv = 0;
260 /* This should always be on the opposite edge as statdrv */
261 spxx_clk_ctl.s.statrcv = 1;
262 spxx_clk_ctl.s.sndtrn = 0;
263 spxx_clk_ctl.s.drptrn = 0;
264 spxx_clk_ctl.s.rcvtrn = 0;
265 spxx_clk_ctl.s.srxdlck = 0;
266 cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
267 cvmx_wait(100 * MS);
268
269 /* Reset SRX0 DLL */
270 spxx_clk_ctl.s.srxdlck = 1;
271 cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
272
273 /* Waiting for Inf0 Spi4 RX DLL to lock */
274 cvmx_wait(100 * MS);
275
276 /* Enable dynamic alignment */
277 spxx_trn4_ctl.s.trntest = 0;
278 spxx_trn4_ctl.s.jitter = 1;
279 spxx_trn4_ctl.s.clr_boot = 1;
280 spxx_trn4_ctl.s.set_boot = 0;
281 if (OCTEON_IS_MODEL(OCTEON_CN58XX))
282 spxx_trn4_ctl.s.maxdist = 3;
283 else
284 spxx_trn4_ctl.s.maxdist = 8;
285 spxx_trn4_ctl.s.macro_en = 1;
286 spxx_trn4_ctl.s.mux_en = 1;
287 cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);
288
289 spxx_dbg_deskew_ctl.u64 = 0;
290 cvmx_write_csr(CVMX_SPXX_DBG_DESKEW_CTL(interface),
291 spxx_dbg_deskew_ctl.u64);
292
293 return 0;
294}
295
296/**
297 * Callback to setup calendar and miscellaneous settings before clock detection
298 *
299 * @interface: The identifier of the packet interface to configure and
300 * use as a SPI interface.
301 * @mode: The operating mode for the SPI interface. The interface
302 * can operate as a full duplex (both Tx and Rx data paths
303 * active) or as a halfplex (either the Tx data path is
304 * active or the Rx data path is active, but not both).
305 * @num_ports: Number of ports to configure on SPI
306 *
307 * Returns Zero on success, non-zero error code on failure (will cause
308 * SPI initialization to abort)
309 */
310int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
311 int num_ports)
312{
313 int port;
314 int index;
315 if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
316 union cvmx_srxx_com_ctl srxx_com_ctl;
317 union cvmx_srxx_spi4_stat srxx_spi4_stat;
318
319 /* SRX0 number of Ports */
320 srxx_com_ctl.u64 = 0;
321 srxx_com_ctl.s.prts = num_ports - 1;
322 srxx_com_ctl.s.st_en = 0;
323 srxx_com_ctl.s.inf_en = 0;
324 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
325
326 /* SRX0 Calendar Table. This round robbins through all ports */
327 port = 0;
328 index = 0;
329 while (port < num_ports) {
330 union cvmx_srxx_spi4_calx srxx_spi4_calx;
331 srxx_spi4_calx.u64 = 0;
332 srxx_spi4_calx.s.prt0 = port++;
333 srxx_spi4_calx.s.prt1 = port++;
334 srxx_spi4_calx.s.prt2 = port++;
335 srxx_spi4_calx.s.prt3 = port++;
336 srxx_spi4_calx.s.oddpar =
337 ~(cvmx_dpop(srxx_spi4_calx.u64) & 1);
338 cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface),
339 srxx_spi4_calx.u64);
340 index++;
341 }
342 srxx_spi4_stat.u64 = 0;
343 srxx_spi4_stat.s.len = num_ports;
344 srxx_spi4_stat.s.m = 1;
345 cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface),
346 srxx_spi4_stat.u64);
347 }
348
349 if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
350 union cvmx_stxx_arb_ctl stxx_arb_ctl;
351 union cvmx_gmxx_tx_spi_max gmxx_tx_spi_max;
352 union cvmx_gmxx_tx_spi_thresh gmxx_tx_spi_thresh;
353 union cvmx_gmxx_tx_spi_ctl gmxx_tx_spi_ctl;
354 union cvmx_stxx_spi4_stat stxx_spi4_stat;
355 union cvmx_stxx_spi4_dat stxx_spi4_dat;
356
357 /* STX0 Config */
358 stxx_arb_ctl.u64 = 0;
359 stxx_arb_ctl.s.igntpa = 0;
360 stxx_arb_ctl.s.mintrn = 0;
361 cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64);
362
363 gmxx_tx_spi_max.u64 = 0;
364 gmxx_tx_spi_max.s.max1 = 8;
365 gmxx_tx_spi_max.s.max2 = 4;
366 gmxx_tx_spi_max.s.slice = 0;
367 cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface),
368 gmxx_tx_spi_max.u64);
369
370 gmxx_tx_spi_thresh.u64 = 0;
371 gmxx_tx_spi_thresh.s.thresh = 4;
372 cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface),
373 gmxx_tx_spi_thresh.u64);
374
375 gmxx_tx_spi_ctl.u64 = 0;
376 gmxx_tx_spi_ctl.s.tpa_clr = 0;
377 gmxx_tx_spi_ctl.s.cont_pkt = 0;
378 cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface),
379 gmxx_tx_spi_ctl.u64);
380
381 /* STX0 Training Control */
382 stxx_spi4_dat.u64 = 0;
383 /*Minimum needed by dynamic alignment */
384 stxx_spi4_dat.s.alpha = 32;
385 stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */
386 cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface),
387 stxx_spi4_dat.u64);
388
389 /* STX0 Calendar Table. This round robbins through all ports */
390 port = 0;
391 index = 0;
392 while (port < num_ports) {
393 union cvmx_stxx_spi4_calx stxx_spi4_calx;
394 stxx_spi4_calx.u64 = 0;
395 stxx_spi4_calx.s.prt0 = port++;
396 stxx_spi4_calx.s.prt1 = port++;
397 stxx_spi4_calx.s.prt2 = port++;
398 stxx_spi4_calx.s.prt3 = port++;
399 stxx_spi4_calx.s.oddpar =
400 ~(cvmx_dpop(stxx_spi4_calx.u64) & 1);
401 cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface),
402 stxx_spi4_calx.u64);
403 index++;
404 }
405 stxx_spi4_stat.u64 = 0;
406 stxx_spi4_stat.s.len = num_ports;
407 stxx_spi4_stat.s.m = 1;
408 cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface),
409 stxx_spi4_stat.u64);
410 }
411
412 return 0;
413}
414
415/**
416 * Callback to perform clock detection
417 *
418 * @interface: The identifier of the packet interface to configure and
419 * use as a SPI interface.
420 * @mode: The operating mode for the SPI interface. The interface
421 * can operate as a full duplex (both Tx and Rx data paths
422 * active) or as a halfplex (either the Tx data path is
423 * active or the Rx data path is active, but not both).
424 * @timeout: Timeout to wait for clock synchronization in seconds
425 *
426 * Returns Zero on success, non-zero error code on failure (will cause
427 * SPI initialization to abort)
428 */
429int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout)
430{
431 int clock_transitions;
432 union cvmx_spxx_clk_stat stat;
433 uint64_t timeout_time;
434 uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
435
436 /*
437 * Regardless of operating mode, both Tx and Rx clocks must be
438 * present for the SPI interface to operate.
439 */
440 cvmx_dprintf("SPI%d: Waiting to see TsClk...\n", interface);
441 timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
442 /*
443 * Require 100 clock transitions in order to avoid any noise
444 * in the beginning.
445 */
446 clock_transitions = 100;
447 do {
448 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
449 if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) {
450 /*
451 * We've seen a clock transition, so decrement
452 * the number we still need.
453 */
454 clock_transitions--;
455 cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
456 stat.s.s4clk0 = 0;
457 stat.s.s4clk1 = 0;
458 }
459 if (cvmx_get_cycle() > timeout_time) {
460 cvmx_dprintf("SPI%d: Timeout\n", interface);
461 return -1;
462 }
463 } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0);
464
465 cvmx_dprintf("SPI%d: Waiting to see RsClk...\n", interface);
466 timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
467 /*
468 * Require 100 clock transitions in order to avoid any noise in the
469 * beginning.
470 */
471 clock_transitions = 100;
472 do {
473 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
474 if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) {
475 /*
476 * We've seen a clock transition, so decrement
477 * the number we still need
478 */
479 clock_transitions--;
480 cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
481 stat.s.d4clk0 = 0;
482 stat.s.d4clk1 = 0;
483 }
484 if (cvmx_get_cycle() > timeout_time) {
485 cvmx_dprintf("SPI%d: Timeout\n", interface);
486 return -1;
487 }
488 } while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0);
489
490 return 0;
491}
492
493/**
494 * Callback to perform link training
495 *
496 * @interface: The identifier of the packet interface to configure and
497 * use as a SPI interface.
498 * @mode: The operating mode for the SPI interface. The interface
499 * can operate as a full duplex (both Tx and Rx data paths
500 * active) or as a halfplex (either the Tx data path is
501 * active or the Rx data path is active, but not both).
502 * @timeout: Timeout to wait for link to be trained (in seconds)
503 *
504 * Returns Zero on success, non-zero error code on failure (will cause
505 * SPI initialization to abort)
506 */
507int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
508{
509 union cvmx_spxx_trn4_ctl spxx_trn4_ctl;
510 union cvmx_spxx_clk_stat stat;
511 uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
512 uint64_t timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
513 int rx_training_needed;
514
515 /* SRX0 & STX0 Inf0 Links are configured - begin training */
516 union cvmx_spxx_clk_ctl spxx_clk_ctl;
517 spxx_clk_ctl.u64 = 0;
518 spxx_clk_ctl.s.seetrn = 0;
519 spxx_clk_ctl.s.clkdly = 0x10;
520 spxx_clk_ctl.s.runbist = 0;
521 spxx_clk_ctl.s.statdrv = 0;
522 /* This should always be on the opposite edge as statdrv */
523 spxx_clk_ctl.s.statrcv = 1;
524 spxx_clk_ctl.s.sndtrn = 1;
525 spxx_clk_ctl.s.drptrn = 1;
526 spxx_clk_ctl.s.rcvtrn = 1;
527 spxx_clk_ctl.s.srxdlck = 1;
528 cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
529 cvmx_wait(1000 * MS);
530
531 /* SRX0 clear the boot bit */
532 spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));
533 spxx_trn4_ctl.s.clr_boot = 1;
534 cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);
535
536 /* Wait for the training sequence to complete */
537 cvmx_dprintf("SPI%d: Waiting for training\n", interface);
538 cvmx_wait(1000 * MS);
539 /* Wait a really long time here */
540 timeout_time = cvmx_get_cycle() + 1000ull * MS * 600;
541 /*
542 * The HRM says we must wait for 34 + 16 * MAXDIST training sequences.
543 * We'll be pessimistic and wait for a lot more.
544 */
545 rx_training_needed = 500;
546 do {
547 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
548 if (stat.s.srxtrn && rx_training_needed) {
549 rx_training_needed--;
550 cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
551 stat.s.srxtrn = 0;
552 }
553 if (cvmx_get_cycle() > timeout_time) {
554 cvmx_dprintf("SPI%d: Timeout\n", interface);
555 return -1;
556 }
557 } while (stat.s.srxtrn == 0);
558
559 return 0;
560}
561
562/**
563 * Callback to perform calendar data synchronization
564 *
565 * @interface: The identifier of the packet interface to configure and
566 * use as a SPI interface.
567 * @mode: The operating mode for the SPI interface. The interface
568 * can operate as a full duplex (both Tx and Rx data paths
569 * active) or as a halfplex (either the Tx data path is
570 * active or the Rx data path is active, but not both).
571 * @timeout: Timeout to wait for calendar data in seconds
572 *
573 * Returns Zero on success, non-zero error code on failure (will cause
574 * SPI initialization to abort)
575 */
576int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout)
577{
578 uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
579 if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
580 /* SRX0 interface should be good, send calendar data */
581 union cvmx_srxx_com_ctl srxx_com_ctl;
582 cvmx_dprintf
583 ("SPI%d: Rx is synchronized, start sending calendar data\n",
584 interface);
585 srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
586 srxx_com_ctl.s.inf_en = 1;
587 srxx_com_ctl.s.st_en = 1;
588 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
589 }
590
591 if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
592 /* STX0 has achieved sync */
593 /* The corespondant board should be sending calendar data */
594 /* Enable the STX0 STAT receiver. */
595 union cvmx_spxx_clk_stat stat;
596 uint64_t timeout_time;
597 union cvmx_stxx_com_ctl stxx_com_ctl;
598 stxx_com_ctl.u64 = 0;
599 stxx_com_ctl.s.st_en = 1;
600 cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);
601
602 /* Waiting for calendar sync on STX0 STAT */
603 cvmx_dprintf("SPI%d: Waiting to sync on STX[%d] STAT\n",
604 interface, interface);
605 timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
606 /* SPX0_CLK_STAT - SPX0_CLK_STAT[STXCAL] should be 1 (bit10) */
607 do {
608 stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
609 if (cvmx_get_cycle() > timeout_time) {
610 cvmx_dprintf("SPI%d: Timeout\n", interface);
611 return -1;
612 }
613 } while (stat.s.stxcal == 0);
614 }
615
616 return 0;
617}
618
619/**
620 * Callback to handle interface up
621 *
622 * @interface: The identifier of the packet interface to configure and
623 * use as a SPI interface.
624 * @mode: The operating mode for the SPI interface. The interface
625 * can operate as a full duplex (both Tx and Rx data paths
626 * active) or as a halfplex (either the Tx data path is
627 * active or the Rx data path is active, but not both).
628 *
629 * Returns Zero on success, non-zero error code on failure (will cause
630 * SPI initialization to abort)
631 */
632int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode)
633{
634 union cvmx_gmxx_rxx_frm_min gmxx_rxx_frm_min;
635 union cvmx_gmxx_rxx_frm_max gmxx_rxx_frm_max;
636 union cvmx_gmxx_rxx_jabber gmxx_rxx_jabber;
637
638 if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
639 union cvmx_srxx_com_ctl srxx_com_ctl;
640 srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
641 srxx_com_ctl.s.inf_en = 1;
642 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
643 cvmx_dprintf("SPI%d: Rx is now up\n", interface);
644 }
645
646 if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
647 union cvmx_stxx_com_ctl stxx_com_ctl;
648 stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface));
649 stxx_com_ctl.s.inf_en = 1;
650 cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);
651 cvmx_dprintf("SPI%d: Tx is now up\n", interface);
652 }
653
654 gmxx_rxx_frm_min.u64 = 0;
655 gmxx_rxx_frm_min.s.len = 64;
656 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0, interface),
657 gmxx_rxx_frm_min.u64);
658 gmxx_rxx_frm_max.u64 = 0;
659 gmxx_rxx_frm_max.s.len = 64 * 1024 - 4;
660 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0, interface),
661 gmxx_rxx_frm_max.u64);
662 gmxx_rxx_jabber.u64 = 0;
663 gmxx_rxx_jabber.s.cnt = 64 * 1024 - 4;
664 cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0, interface), gmxx_rxx_jabber.u64);
665
666 return 0;
667}
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c
index c8d35684504e..f4c1b36fdf65 100644
--- a/arch/mips/cavium-octeon/executive/octeon-model.c
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -25,10 +25,6 @@
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/ 26 ***********************license end**************************************/
27 27
28/*
29 * File defining functions for working with different Octeon
30 * models.
31 */
32#include <asm/octeon/octeon.h> 28#include <asm/octeon/octeon.h>
33 29
34/** 30/**
@@ -69,11 +65,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
69 char fuse_model[10]; 65 char fuse_model[10];
70 uint32_t fuse_data = 0; 66 uint32_t fuse_data = 0;
71 67
72 fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3); 68 fus3.u64 = 0;
69 if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
70 fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
73 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); 71 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
74 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3); 72 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
75 73 num_cores = cvmx_pop(cvmx_read_csr(CVMX_CIU_FUSE));
76 num_cores = cvmx_octeon_num_cores();
77 74
78 /* Make sure the non existent devices look disabled */ 75 /* Make sure the non existent devices look disabled */
79 switch ((chip_id >> 8) & 0xff) { 76 switch ((chip_id >> 8) & 0xff) {
@@ -108,7 +105,7 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
108 * Assume pass number is encoded using <5:3><2:0>. Exceptions 105 * Assume pass number is encoded using <5:3><2:0>. Exceptions
109 * will be fixed later. 106 * will be fixed later.
110 */ 107 */
111 sprintf(pass, "%u.%u", ((chip_id >> 3) & 7) + 1, chip_id & 7); 108 sprintf(pass, "%d.%d", (int)((chip_id >> 3) & 7) + 1, (int)chip_id & 7);
112 109
113 /* 110 /*
114 * Use the number of cores to determine the last 2 digits of 111 * Use the number of cores to determine the last 2 digits of
@@ -116,6 +113,12 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
116 * later. 113 * later.
117 */ 114 */
118 switch (num_cores) { 115 switch (num_cores) {
116 case 32:
117 core_model = "80";
118 break;
119 case 24:
120 core_model = "70";
121 break;
119 case 16: 122 case 16:
120 core_model = "60"; 123 core_model = "60";
121 break; 124 break;
@@ -246,8 +249,8 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
246 break; 249 break;
247 case 3: /* CN58XX */ 250 case 3: /* CN58XX */
248 family = "58"; 251 family = "58";
249 /* Special case. 4 core, no crypto */ 252 /* Special case. 4 core, half cache (CP with half cache) */
250 if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto) 253 if ((num_cores == 4) && fus3.cn58xx.crip_1024k && !strncmp(suffix, "CP", 2))
251 core_model = "29"; 254 core_model = "29";
252 255
253 /* Pass 1 uses different encodings for pass numbers */ 256 /* Pass 1 uses different encodings for pass numbers */
@@ -285,6 +288,9 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
285 suffix = "NSP"; 288 suffix = "NSP";
286 if (fus_dat3.s.nozip) 289 if (fus_dat3.s.nozip)
287 suffix = "SCP"; 290 suffix = "SCP";
291
292 if (fus_dat3.s.bar2_en)
293 suffix = "NSPB2";
288 } 294 }
289 if (fus3.cn56xx.crip_1024k) 295 if (fus3.cn56xx.crip_1024k)
290 family = "54"; 296 family = "54";
@@ -301,6 +307,60 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
301 else 307 else
302 family = "52"; 308 family = "52";
303 break; 309 break;
310 case 0x93: /* CN61XX */
311 family = "61";
312 if (fus_dat2.cn61xx.nocrypto && fus_dat2.cn61xx.dorm_crypto)
313 suffix = "AP";
314 if (fus_dat2.cn61xx.nocrypto)
315 suffix = "CP";
316 else if (fus_dat2.cn61xx.dorm_crypto)
317 suffix = "DAP";
318 else if (fus_dat3.cn61xx.nozip)
319 suffix = "SCP";
320 break;
321 case 0x90: /* CN63XX */
322 family = "63";
323 if (fus_dat3.s.l2c_crip == 2)
324 family = "62";
325 if (num_cores == 6) /* Other core counts match generic */
326 core_model = "35";
327 if (fus_dat2.cn63xx.nocrypto)
328 suffix = "CP";
329 else if (fus_dat2.cn63xx.dorm_crypto)
330 suffix = "DAP";
331 else if (fus_dat3.cn63xx.nozip)
332 suffix = "SCP";
333 else
334 suffix = "AAP";
335 break;
336 case 0x92: /* CN66XX */
337 family = "66";
338 if (num_cores == 6) /* Other core counts match generic */
339 core_model = "35";
340 if (fus_dat2.cn66xx.nocrypto && fus_dat2.cn66xx.dorm_crypto)
341 suffix = "AP";
342 if (fus_dat2.cn66xx.nocrypto)
343 suffix = "CP";
344 else if (fus_dat2.cn66xx.dorm_crypto)
345 suffix = "DAP";
346 else if (fus_dat3.cn66xx.nozip)
347 suffix = "SCP";
348 else
349 suffix = "AAP";
350 break;
351 case 0x91: /* CN68XX */
352 family = "68";
353 if (fus_dat2.cn68xx.nocrypto && fus_dat3.cn68xx.nozip)
354 suffix = "CP";
355 else if (fus_dat2.cn68xx.dorm_crypto)
356 suffix = "DAP";
357 else if (fus_dat3.cn68xx.nozip)
358 suffix = "SCP";
359 else if (fus_dat2.cn68xx.nocrypto)
360 suffix = "SP";
361 else
362 suffix = "AAP";
363 break;
304 default: 364 default:
305 family = "XX"; 365 family = "XX";
306 core_model = "XX"; 366 core_model = "XX";
@@ -310,49 +370,40 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
310 } 370 }
311 371
312 clock_mhz = octeon_get_clock_rate() / 1000000; 372 clock_mhz = octeon_get_clock_rate() / 1000000;
313
314 if (family[0] != '3') { 373 if (family[0] != '3') {
374 int fuse_base = 384 / 8;
375 if (family[0] == '6')
376 fuse_base = 832 / 8;
377
315 /* Check for model in fuses, overrides normal decode */ 378 /* Check for model in fuses, overrides normal decode */
316 /* This is _not_ valid for Octeon CN3XXX models */ 379 /* This is _not_ valid for Octeon CN3XXX models */
317 fuse_data |= cvmx_fuse_read_byte(51); 380 fuse_data |= cvmx_fuse_read_byte(fuse_base + 3);
318 fuse_data = fuse_data << 8; 381 fuse_data = fuse_data << 8;
319 fuse_data |= cvmx_fuse_read_byte(50); 382 fuse_data |= cvmx_fuse_read_byte(fuse_base + 2);
320 fuse_data = fuse_data << 8; 383 fuse_data = fuse_data << 8;
321 fuse_data |= cvmx_fuse_read_byte(49); 384 fuse_data |= cvmx_fuse_read_byte(fuse_base + 1);
322 fuse_data = fuse_data << 8; 385 fuse_data = fuse_data << 8;
323 fuse_data |= cvmx_fuse_read_byte(48); 386 fuse_data |= cvmx_fuse_read_byte(fuse_base);
324 if (fuse_data & 0x7ffff) { 387 if (fuse_data & 0x7ffff) {
325 int model = fuse_data & 0x3fff; 388 int model = fuse_data & 0x3fff;
326 int suffix = (fuse_data >> 14) & 0x1f; 389 int suffix = (fuse_data >> 14) & 0x1f;
327 if (suffix && model) { 390 if (suffix && model) {
328 /* 391 /* Have both number and suffix in fuses, so both */
329 * Have both number and suffix in 392 sprintf(fuse_model, "%d%c", model, 'A' + suffix - 1);
330 * fuses, so both
331 */
332 sprintf(fuse_model, "%d%c",
333 model, 'A' + suffix - 1);
334 core_model = ""; 393 core_model = "";
335 family = fuse_model; 394 family = fuse_model;
336 } else if (suffix && !model) { 395 } else if (suffix && !model) {
337 /* 396 /* Only have suffix, so add suffix to 'normal' model number */
338 * Only have suffix, so add suffix to 397 sprintf(fuse_model, "%s%c", core_model, 'A' + suffix - 1);
339 * 'normal' model number.
340 */
341 sprintf(fuse_model, "%s%c", core_model,
342 'A' + suffix - 1);
343 core_model = fuse_model; 398 core_model = fuse_model;
344 } else { 399 } else {
345 /* 400 /* Don't have suffix, so just use model from fuses */
346 * Don't have suffix, so just use
347 * model from fuses.
348 */
349 sprintf(fuse_model, "%d", model); 401 sprintf(fuse_model, "%d", model);
350 core_model = ""; 402 core_model = "";
351 family = fuse_model; 403 family = fuse_model;
352 } 404 }
353 } 405 }
354 } 406 }
355 sprintf(buffer, "CN%s%sp%s-%d-%s", 407 sprintf(buffer, "CN%s%sp%s-%d-%s", family, core_model, pass, clock_mhz, suffix);
356 family, core_model, pass, clock_mhz, suffix);
357 return buffer; 408 return buffer;
358} 409}
diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig
new file mode 100644
index 000000000000..4479fd669ac1
--- /dev/null
+++ b/arch/mips/configs/nlm_xlp_defconfig
@@ -0,0 +1,570 @@
1CONFIG_NLM_XLP_BOARD=y
2CONFIG_64BIT=y
3CONFIG_KSM=y
4CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
5CONFIG_SMP=y
6CONFIG_NO_HZ=y
7CONFIG_HIGH_RES_TIMERS=y
8# CONFIG_SECCOMP is not set
9CONFIG_USE_OF=y
10CONFIG_EXPERIMENTAL=y
11CONFIG_CROSS_COMPILE="mips-linux-gnu-"
12# CONFIG_LOCALVERSION_AUTO is not set
13CONFIG_SYSVIPC=y
14CONFIG_POSIX_MQUEUE=y
15CONFIG_BSD_PROCESS_ACCT=y
16CONFIG_BSD_PROCESS_ACCT_V3=y
17CONFIG_TASKSTATS=y
18CONFIG_TASK_DELAY_ACCT=y
19CONFIG_TASK_XACCT=y
20CONFIG_TASK_IO_ACCOUNTING=y
21CONFIG_AUDIT=y
22CONFIG_CGROUPS=y
23CONFIG_NAMESPACES=y
24CONFIG_BLK_DEV_INITRD=y
25CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlp"
26CONFIG_RD_BZIP2=y
27CONFIG_RD_LZMA=y
28CONFIG_INITRAMFS_COMPRESSION_LZMA=y
29CONFIG_KALLSYMS_ALL=y
30CONFIG_EMBEDDED=y
31# CONFIG_COMPAT_BRK is not set
32CONFIG_PROFILING=y
33CONFIG_MODULES=y
34CONFIG_MODULE_UNLOAD=y
35CONFIG_MODVERSIONS=y
36CONFIG_MODULE_SRCVERSION_ALL=y
37CONFIG_BLK_DEV_INTEGRITY=y
38# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
39CONFIG_BINFMT_MISC=y
40CONFIG_MIPS32_COMPAT=y
41CONFIG_MIPS32_O32=y
42CONFIG_MIPS32_N32=y
43CONFIG_PM_RUNTIME=y
44CONFIG_PM_DEBUG=y
45CONFIG_PACKET=y
46CONFIG_UNIX=y
47CONFIG_XFRM_USER=m
48CONFIG_NET_KEY=m
49CONFIG_INET=y
50CONFIG_IP_MULTICAST=y
51CONFIG_IP_ADVANCED_ROUTER=y
52CONFIG_IP_MULTIPLE_TABLES=y
53CONFIG_IP_ROUTE_MULTIPATH=y
54CONFIG_IP_ROUTE_VERBOSE=y
55CONFIG_NET_IPIP=m
56CONFIG_IP_MROUTE=y
57CONFIG_IP_PIMSM_V1=y
58CONFIG_IP_PIMSM_V2=y
59CONFIG_SYN_COOKIES=y
60CONFIG_INET_AH=m
61CONFIG_INET_ESP=m
62CONFIG_INET_IPCOMP=m
63CONFIG_INET_XFRM_MODE_TRANSPORT=m
64CONFIG_INET_XFRM_MODE_TUNNEL=m
65CONFIG_INET_XFRM_MODE_BEET=m
66CONFIG_TCP_CONG_ADVANCED=y
67CONFIG_TCP_CONG_HSTCP=m
68CONFIG_TCP_CONG_HYBLA=m
69CONFIG_TCP_CONG_SCALABLE=m
70CONFIG_TCP_CONG_LP=m
71CONFIG_TCP_CONG_VENO=m
72CONFIG_TCP_CONG_YEAH=m
73CONFIG_TCP_CONG_ILLINOIS=m
74CONFIG_TCP_MD5SIG=y
75CONFIG_IPV6=y
76CONFIG_IPV6_PRIVACY=y
77CONFIG_INET6_AH=m
78CONFIG_INET6_ESP=m
79CONFIG_INET6_IPCOMP=m
80CONFIG_INET6_XFRM_MODE_TRANSPORT=m
81CONFIG_INET6_XFRM_MODE_TUNNEL=m
82CONFIG_INET6_XFRM_MODE_BEET=m
83CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
84CONFIG_IPV6_SIT=m
85CONFIG_IPV6_TUNNEL=m
86CONFIG_IPV6_MULTIPLE_TABLES=y
87CONFIG_NETLABEL=y
88CONFIG_NETFILTER=y
89CONFIG_NF_CONNTRACK=m
90CONFIG_NF_CONNTRACK_SECMARK=y
91CONFIG_NF_CONNTRACK_EVENTS=y
92CONFIG_NF_CT_PROTO_UDPLITE=m
93CONFIG_NF_CONNTRACK_AMANDA=m
94CONFIG_NF_CONNTRACK_FTP=m
95CONFIG_NF_CONNTRACK_H323=m
96CONFIG_NF_CONNTRACK_IRC=m
97CONFIG_NF_CONNTRACK_NETBIOS_NS=m
98CONFIG_NF_CONNTRACK_PPTP=m
99CONFIG_NF_CONNTRACK_SANE=m
100CONFIG_NF_CONNTRACK_SIP=m
101CONFIG_NF_CONNTRACK_TFTP=m
102CONFIG_NF_CT_NETLINK=m
103CONFIG_NETFILTER_TPROXY=m
104CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
105CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
106CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
107CONFIG_NETFILTER_XT_TARGET_DSCP=m
108CONFIG_NETFILTER_XT_TARGET_MARK=m
109CONFIG_NETFILTER_XT_TARGET_NFLOG=m
110CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
111CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
112CONFIG_NETFILTER_XT_TARGET_TPROXY=m
113CONFIG_NETFILTER_XT_TARGET_TRACE=m
114CONFIG_NETFILTER_XT_TARGET_SECMARK=m
115CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
116CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
117CONFIG_NETFILTER_XT_MATCH_COMMENT=m
118CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
119CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
120CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
121CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
122CONFIG_NETFILTER_XT_MATCH_DSCP=m
123CONFIG_NETFILTER_XT_MATCH_ESP=m
124CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
125CONFIG_NETFILTER_XT_MATCH_HELPER=m
126CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
127CONFIG_NETFILTER_XT_MATCH_LENGTH=m
128CONFIG_NETFILTER_XT_MATCH_LIMIT=m
129CONFIG_NETFILTER_XT_MATCH_MAC=m
130CONFIG_NETFILTER_XT_MATCH_MARK=m
131CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
132CONFIG_NETFILTER_XT_MATCH_OSF=m
133CONFIG_NETFILTER_XT_MATCH_OWNER=m
134CONFIG_NETFILTER_XT_MATCH_POLICY=m
135CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
136CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
137CONFIG_NETFILTER_XT_MATCH_QUOTA=m
138CONFIG_NETFILTER_XT_MATCH_RATEEST=m
139CONFIG_NETFILTER_XT_MATCH_REALM=m
140CONFIG_NETFILTER_XT_MATCH_RECENT=m
141CONFIG_NETFILTER_XT_MATCH_SOCKET=m
142CONFIG_NETFILTER_XT_MATCH_STATE=m
143CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
144CONFIG_NETFILTER_XT_MATCH_STRING=m
145CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
146CONFIG_NETFILTER_XT_MATCH_TIME=m
147CONFIG_NETFILTER_XT_MATCH_U32=m
148CONFIG_IP_VS=m
149CONFIG_IP_VS_IPV6=y
150CONFIG_IP_VS_PROTO_TCP=y
151CONFIG_IP_VS_PROTO_UDP=y
152CONFIG_IP_VS_PROTO_ESP=y
153CONFIG_IP_VS_PROTO_AH=y
154CONFIG_IP_VS_RR=m
155CONFIG_IP_VS_WRR=m
156CONFIG_IP_VS_LC=m
157CONFIG_IP_VS_WLC=m
158CONFIG_IP_VS_LBLC=m
159CONFIG_IP_VS_LBLCR=m
160CONFIG_IP_VS_DH=m
161CONFIG_IP_VS_SH=m
162CONFIG_IP_VS_SED=m
163CONFIG_IP_VS_NQ=m
164CONFIG_IP_VS_FTP=m
165CONFIG_NF_CONNTRACK_IPV4=m
166CONFIG_IP_NF_QUEUE=m
167CONFIG_IP_NF_IPTABLES=m
168CONFIG_IP_NF_MATCH_AH=m
169CONFIG_IP_NF_MATCH_ECN=m
170CONFIG_IP_NF_MATCH_TTL=m
171CONFIG_IP_NF_FILTER=m
172CONFIG_IP_NF_TARGET_REJECT=m
173CONFIG_IP_NF_TARGET_LOG=m
174CONFIG_IP_NF_TARGET_ULOG=m
175CONFIG_NF_NAT=m
176CONFIG_IP_NF_TARGET_MASQUERADE=m
177CONFIG_IP_NF_TARGET_NETMAP=m
178CONFIG_IP_NF_TARGET_REDIRECT=m
179CONFIG_IP_NF_MANGLE=m
180CONFIG_IP_NF_TARGET_CLUSTERIP=m
181CONFIG_IP_NF_TARGET_ECN=m
182CONFIG_IP_NF_TARGET_TTL=m
183CONFIG_IP_NF_RAW=m
184CONFIG_IP_NF_SECURITY=m
185CONFIG_IP_NF_ARPTABLES=m
186CONFIG_IP_NF_ARPFILTER=m
187CONFIG_IP_NF_ARP_MANGLE=m
188CONFIG_NF_CONNTRACK_IPV6=m
189CONFIG_IP6_NF_QUEUE=m
190CONFIG_IP6_NF_IPTABLES=m
191CONFIG_IP6_NF_MATCH_AH=m
192CONFIG_IP6_NF_MATCH_EUI64=m
193CONFIG_IP6_NF_MATCH_FRAG=m
194CONFIG_IP6_NF_MATCH_OPTS=m
195CONFIG_IP6_NF_MATCH_HL=m
196CONFIG_IP6_NF_MATCH_IPV6HEADER=m
197CONFIG_IP6_NF_MATCH_MH=m
198CONFIG_IP6_NF_MATCH_RT=m
199CONFIG_IP6_NF_TARGET_HL=m
200CONFIG_IP6_NF_TARGET_LOG=m
201CONFIG_IP6_NF_FILTER=m
202CONFIG_IP6_NF_TARGET_REJECT=m
203CONFIG_IP6_NF_MANGLE=m
204CONFIG_IP6_NF_RAW=m
205CONFIG_IP6_NF_SECURITY=m
206CONFIG_DECNET_NF_GRABULATOR=m
207CONFIG_BRIDGE_NF_EBTABLES=m
208CONFIG_BRIDGE_EBT_BROUTE=m
209CONFIG_BRIDGE_EBT_T_FILTER=m
210CONFIG_BRIDGE_EBT_T_NAT=m
211CONFIG_BRIDGE_EBT_802_3=m
212CONFIG_BRIDGE_EBT_AMONG=m
213CONFIG_BRIDGE_EBT_ARP=m
214CONFIG_BRIDGE_EBT_IP=m
215CONFIG_BRIDGE_EBT_IP6=m
216CONFIG_BRIDGE_EBT_LIMIT=m
217CONFIG_BRIDGE_EBT_MARK=m
218CONFIG_BRIDGE_EBT_PKTTYPE=m
219CONFIG_BRIDGE_EBT_STP=m
220CONFIG_BRIDGE_EBT_VLAN=m
221CONFIG_BRIDGE_EBT_ARPREPLY=m
222CONFIG_BRIDGE_EBT_DNAT=m
223CONFIG_BRIDGE_EBT_MARK_T=m
224CONFIG_BRIDGE_EBT_REDIRECT=m
225CONFIG_BRIDGE_EBT_SNAT=m
226CONFIG_BRIDGE_EBT_LOG=m
227CONFIG_BRIDGE_EBT_ULOG=m
228CONFIG_BRIDGE_EBT_NFLOG=m
229CONFIG_IP_DCCP=m
230CONFIG_RDS=m
231CONFIG_RDS_TCP=m
232CONFIG_TIPC=m
233CONFIG_ATM=m
234CONFIG_ATM_CLIP=m
235CONFIG_ATM_LANE=m
236CONFIG_ATM_MPOA=m
237CONFIG_ATM_BR2684=m
238CONFIG_BRIDGE=m
239CONFIG_VLAN_8021Q=m
240CONFIG_VLAN_8021Q_GVRP=y
241CONFIG_DECNET=m
242CONFIG_LLC2=m
243CONFIG_IPX=m
244CONFIG_ATALK=m
245CONFIG_DEV_APPLETALK=m
246CONFIG_IPDDP=m
247CONFIG_IPDDP_ENCAP=y
248CONFIG_IPDDP_DECAP=y
249CONFIG_X25=m
250CONFIG_LAPB=m
251CONFIG_ECONET=m
252CONFIG_ECONET_AUNUDP=y
253CONFIG_ECONET_NATIVE=y
254CONFIG_WAN_ROUTER=m
255CONFIG_PHONET=m
256CONFIG_IEEE802154=m
257CONFIG_NET_SCHED=y
258CONFIG_NET_SCH_CBQ=m
259CONFIG_NET_SCH_HTB=m
260CONFIG_NET_SCH_HFSC=m
261CONFIG_NET_SCH_ATM=m
262CONFIG_NET_SCH_PRIO=m
263CONFIG_NET_SCH_MULTIQ=m
264CONFIG_NET_SCH_RED=m
265CONFIG_NET_SCH_SFQ=m
266CONFIG_NET_SCH_TEQL=m
267CONFIG_NET_SCH_TBF=m
268CONFIG_NET_SCH_GRED=m
269CONFIG_NET_SCH_DSMARK=m
270CONFIG_NET_SCH_NETEM=m
271CONFIG_NET_SCH_DRR=m
272CONFIG_NET_SCH_INGRESS=m
273CONFIG_NET_CLS_BASIC=m
274CONFIG_NET_CLS_TCINDEX=m
275CONFIG_NET_CLS_ROUTE4=m
276CONFIG_NET_CLS_FW=m
277CONFIG_NET_CLS_U32=m
278CONFIG_CLS_U32_MARK=y
279CONFIG_NET_CLS_RSVP=m
280CONFIG_NET_CLS_RSVP6=m
281CONFIG_NET_CLS_FLOW=m
282CONFIG_NET_EMATCH=y
283CONFIG_NET_EMATCH_CMP=m
284CONFIG_NET_EMATCH_NBYTE=m
285CONFIG_NET_EMATCH_U32=m
286CONFIG_NET_EMATCH_META=m
287CONFIG_NET_EMATCH_TEXT=m
288CONFIG_NET_CLS_ACT=y
289CONFIG_NET_ACT_POLICE=m
290CONFIG_NET_ACT_GACT=m
291CONFIG_GACT_PROB=y
292CONFIG_NET_ACT_MIRRED=m
293CONFIG_NET_ACT_IPT=m
294CONFIG_NET_ACT_NAT=m
295CONFIG_NET_ACT_PEDIT=m
296CONFIG_NET_ACT_SIMP=m
297CONFIG_NET_ACT_SKBEDIT=m
298CONFIG_DCB=y
299CONFIG_NET_PKTGEN=m
300# CONFIG_WIRELESS is not set
301CONFIG_DEVTMPFS=y
302CONFIG_DEVTMPFS_MOUNT=y
303# CONFIG_STANDALONE is not set
304CONFIG_CONNECTOR=y
305CONFIG_BLK_DEV_LOOP=y
306CONFIG_BLK_DEV_CRYPTOLOOP=m
307CONFIG_BLK_DEV_NBD=m
308CONFIG_BLK_DEV_OSD=m
309CONFIG_BLK_DEV_RAM=y
310CONFIG_BLK_DEV_RAM_SIZE=65536
311CONFIG_CDROM_PKTCDVD=y
312CONFIG_RAID_ATTRS=m
313CONFIG_SCSI=y
314CONFIG_SCSI_TGT=m
315CONFIG_BLK_DEV_SD=y
316CONFIG_CHR_DEV_ST=m
317CONFIG_CHR_DEV_OSST=m
318CONFIG_BLK_DEV_SR=y
319CONFIG_CHR_DEV_SG=y
320CONFIG_CHR_DEV_SCH=m
321CONFIG_SCSI_MULTI_LUN=y
322CONFIG_SCSI_CONSTANTS=y
323CONFIG_SCSI_LOGGING=y
324CONFIG_SCSI_SCAN_ASYNC=y
325CONFIG_SCSI_SPI_ATTRS=m
326CONFIG_SCSI_FC_TGT_ATTRS=y
327CONFIG_SCSI_SAS_LIBSAS=m
328CONFIG_SCSI_SRP_ATTRS=m
329CONFIG_SCSI_SRP_TGT_ATTRS=y
330CONFIG_ISCSI_TCP=m
331CONFIG_LIBFCOE=m
332CONFIG_SCSI_DEBUG=m
333CONFIG_SCSI_DH=y
334CONFIG_SCSI_DH_RDAC=m
335CONFIG_SCSI_DH_HP_SW=m
336CONFIG_SCSI_DH_EMC=m
337CONFIG_SCSI_DH_ALUA=m
338CONFIG_SCSI_OSD_INITIATOR=m
339CONFIG_SCSI_OSD_ULD=m
340# CONFIG_INPUT_MOUSEDEV is not set
341CONFIG_INPUT_EVDEV=y
342CONFIG_INPUT_EVBUG=m
343# CONFIG_INPUT_KEYBOARD is not set
344# CONFIG_INPUT_MOUSE is not set
345# CONFIG_SERIO_I8042 is not set
346CONFIG_SERIO_SERPORT=m
347CONFIG_SERIO_LIBPS2=y
348CONFIG_SERIO_RAW=m
349CONFIG_VT_HW_CONSOLE_BINDING=y
350CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
351CONFIG_LEGACY_PTY_COUNT=0
352CONFIG_SERIAL_NONSTANDARD=y
353CONFIG_N_HDLC=m
354# CONFIG_DEVKMEM is not set
355CONFIG_STALDRV=y
356CONFIG_SERIAL_8250=y
357CONFIG_SERIAL_8250_CONSOLE=y
358CONFIG_SERIAL_8250_NR_UARTS=48
359CONFIG_SERIAL_8250_EXTENDED=y
360CONFIG_SERIAL_8250_MANY_PORTS=y
361CONFIG_SERIAL_8250_SHARE_IRQ=y
362CONFIG_SERIAL_8250_RSA=y
363CONFIG_HW_RANDOM=y
364CONFIG_HW_RANDOM_TIMERIOMEM=m
365CONFIG_RAW_DRIVER=m
366# CONFIG_HWMON is not set
367# CONFIG_VGA_CONSOLE is not set
368# CONFIG_HID_SUPPORT is not set
369# CONFIG_USB_SUPPORT is not set
370CONFIG_UIO=y
371CONFIG_UIO_PDRV=m
372CONFIG_UIO_PDRV_GENIRQ=m
373CONFIG_EXT2_FS=y
374CONFIG_EXT2_FS_XATTR=y
375CONFIG_EXT2_FS_POSIX_ACL=y
376CONFIG_EXT2_FS_SECURITY=y
377CONFIG_EXT3_FS=y
378CONFIG_EXT3_FS_POSIX_ACL=y
379CONFIG_EXT3_FS_SECURITY=y
380CONFIG_EXT4_FS=y
381CONFIG_EXT4_FS_POSIX_ACL=y
382CONFIG_EXT4_FS_SECURITY=y
383CONFIG_GFS2_FS=m
384CONFIG_GFS2_FS_LOCKING_DLM=y
385CONFIG_OCFS2_FS=m
386CONFIG_BTRFS_FS=m
387CONFIG_BTRFS_FS_POSIX_ACL=y
388CONFIG_NILFS2_FS=m
389CONFIG_QUOTA_NETLINK_INTERFACE=y
390# CONFIG_PRINT_QUOTA_WARNING is not set
391CONFIG_QFMT_V1=m
392CONFIG_QFMT_V2=m
393CONFIG_AUTOFS4_FS=m
394CONFIG_FUSE_FS=y
395CONFIG_CUSE=m
396CONFIG_FSCACHE=m
397CONFIG_FSCACHE_STATS=y
398CONFIG_FSCACHE_HISTOGRAM=y
399CONFIG_CACHEFILES=m
400CONFIG_ISO9660_FS=m
401CONFIG_JOLIET=y
402CONFIG_ZISOFS=y
403CONFIG_UDF_FS=m
404CONFIG_MSDOS_FS=m
405CONFIG_VFAT_FS=m
406CONFIG_NTFS_FS=m
407CONFIG_PROC_KCORE=y
408CONFIG_TMPFS=y
409CONFIG_TMPFS_POSIX_ACL=y
410CONFIG_ADFS_FS=m
411CONFIG_AFFS_FS=m
412CONFIG_ECRYPT_FS=y
413CONFIG_HFS_FS=m
414CONFIG_HFSPLUS_FS=m
415CONFIG_BEFS_FS=m
416CONFIG_BFS_FS=m
417CONFIG_EFS_FS=m
418CONFIG_CRAMFS=m
419CONFIG_SQUASHFS=m
420CONFIG_VXFS_FS=m
421CONFIG_MINIX_FS=m
422CONFIG_OMFS_FS=m
423CONFIG_HPFS_FS=m
424CONFIG_QNX4FS_FS=m
425CONFIG_ROMFS_FS=m
426CONFIG_SYSV_FS=m
427CONFIG_UFS_FS=m
428CONFIG_EXOFS_FS=m
429CONFIG_NFS_FS=m
430CONFIG_NFS_V3=y
431CONFIG_NFS_V3_ACL=y
432CONFIG_NFS_V4=y
433CONFIG_NFS_FSCACHE=y
434CONFIG_NFSD=m
435CONFIG_NFSD_V3_ACL=y
436CONFIG_NFSD_V4=y
437CONFIG_CIFS=m
438CONFIG_CIFS_WEAK_PW_HASH=y
439CONFIG_CIFS_UPCALL=y
440CONFIG_CIFS_XATTR=y
441CONFIG_CIFS_POSIX=y
442CONFIG_CIFS_DFS_UPCALL=y
443CONFIG_NCP_FS=m
444CONFIG_NCPFS_PACKET_SIGNING=y
445CONFIG_NCPFS_IOCTL_LOCKING=y
446CONFIG_NCPFS_STRONG=y
447CONFIG_NCPFS_NFS_NS=y
448CONFIG_NCPFS_OS2_NS=y
449CONFIG_NCPFS_NLS=y
450CONFIG_NCPFS_EXTRAS=y
451CONFIG_CODA_FS=m
452CONFIG_AFS_FS=m
453CONFIG_PARTITION_ADVANCED=y
454CONFIG_ACORN_PARTITION=y
455CONFIG_ACORN_PARTITION_ICS=y
456CONFIG_ACORN_PARTITION_RISCIX=y
457CONFIG_OSF_PARTITION=y
458CONFIG_AMIGA_PARTITION=y
459CONFIG_ATARI_PARTITION=y
460CONFIG_MAC_PARTITION=y
461CONFIG_BSD_DISKLABEL=y
462CONFIG_MINIX_SUBPARTITION=y
463CONFIG_SOLARIS_X86_PARTITION=y
464CONFIG_UNIXWARE_DISKLABEL=y
465CONFIG_LDM_PARTITION=y
466CONFIG_SGI_PARTITION=y
467CONFIG_ULTRIX_PARTITION=y
468CONFIG_SUN_PARTITION=y
469CONFIG_KARMA_PARTITION=y
470CONFIG_EFI_PARTITION=y
471CONFIG_SYSV68_PARTITION=y
472CONFIG_NLS=y
473CONFIG_NLS_DEFAULT="cp437"
474CONFIG_NLS_CODEPAGE_437=m
475CONFIG_NLS_CODEPAGE_737=m
476CONFIG_NLS_CODEPAGE_775=m
477CONFIG_NLS_CODEPAGE_850=m
478CONFIG_NLS_CODEPAGE_852=m
479CONFIG_NLS_CODEPAGE_855=m
480CONFIG_NLS_CODEPAGE_857=m
481CONFIG_NLS_CODEPAGE_860=m
482CONFIG_NLS_CODEPAGE_861=m
483CONFIG_NLS_CODEPAGE_862=m
484CONFIG_NLS_CODEPAGE_863=m
485CONFIG_NLS_CODEPAGE_864=m
486CONFIG_NLS_CODEPAGE_865=m
487CONFIG_NLS_CODEPAGE_866=m
488CONFIG_NLS_CODEPAGE_869=m
489CONFIG_NLS_CODEPAGE_936=m
490CONFIG_NLS_CODEPAGE_950=m
491CONFIG_NLS_CODEPAGE_932=m
492CONFIG_NLS_CODEPAGE_949=m
493CONFIG_NLS_CODEPAGE_874=m
494CONFIG_NLS_ISO8859_8=m
495CONFIG_NLS_CODEPAGE_1250=m
496CONFIG_NLS_CODEPAGE_1251=m
497CONFIG_NLS_ASCII=m
498CONFIG_NLS_ISO8859_1=m
499CONFIG_NLS_ISO8859_2=m
500CONFIG_NLS_ISO8859_3=m
501CONFIG_NLS_ISO8859_4=m
502CONFIG_NLS_ISO8859_5=m
503CONFIG_NLS_ISO8859_6=m
504CONFIG_NLS_ISO8859_7=m
505CONFIG_NLS_ISO8859_9=m
506CONFIG_NLS_ISO8859_13=m
507CONFIG_NLS_ISO8859_14=m
508CONFIG_NLS_ISO8859_15=m
509CONFIG_NLS_KOI8_R=m
510CONFIG_NLS_KOI8_U=m
511CONFIG_PRINTK_TIME=y
512# CONFIG_ENABLE_WARN_DEPRECATED is not set
513# CONFIG_ENABLE_MUST_CHECK is not set
514CONFIG_FRAME_WARN=1024
515CONFIG_UNUSED_SYMBOLS=y
516CONFIG_DETECT_HUNG_TASK=y
517CONFIG_SCHEDSTATS=y
518CONFIG_TIMER_STATS=y
519CONFIG_DEBUG_INFO=y
520CONFIG_DEBUG_MEMORY_INIT=y
521CONFIG_SYSCTL_SYSCALL_CHECK=y
522CONFIG_SCHED_TRACER=y
523CONFIG_BLK_DEV_IO_TRACE=y
524CONFIG_KGDB=y
525CONFIG_SECURITY=y
526CONFIG_SECURITY_NETWORK=y
527CONFIG_LSM_MMAP_MIN_ADDR=0
528CONFIG_SECURITY_SELINUX=y
529CONFIG_SECURITY_SELINUX_BOOTPARAM=y
530CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
531CONFIG_SECURITY_SELINUX_DISABLE=y
532CONFIG_SECURITY_SMACK=y
533CONFIG_SECURITY_TOMOYO=y
534CONFIG_CRYPTO_NULL=m
535CONFIG_CRYPTO_CRYPTD=m
536CONFIG_CRYPTO_TEST=m
537CONFIG_CRYPTO_CCM=m
538CONFIG_CRYPTO_GCM=m
539CONFIG_CRYPTO_CTS=m
540CONFIG_CRYPTO_LRW=m
541CONFIG_CRYPTO_PCBC=m
542CONFIG_CRYPTO_XTS=m
543CONFIG_CRYPTO_HMAC=y
544CONFIG_CRYPTO_XCBC=m
545CONFIG_CRYPTO_VMAC=m
546CONFIG_CRYPTO_MICHAEL_MIC=m
547CONFIG_CRYPTO_RMD128=m
548CONFIG_CRYPTO_RMD160=m
549CONFIG_CRYPTO_RMD256=m
550CONFIG_CRYPTO_RMD320=m
551CONFIG_CRYPTO_SHA256=m
552CONFIG_CRYPTO_SHA512=m
553CONFIG_CRYPTO_TGR192=m
554CONFIG_CRYPTO_WP512=m
555CONFIG_CRYPTO_ANUBIS=m
556CONFIG_CRYPTO_BLOWFISH=m
557CONFIG_CRYPTO_CAMELLIA=m
558CONFIG_CRYPTO_CAST5=m
559CONFIG_CRYPTO_CAST6=m
560CONFIG_CRYPTO_FCRYPT=m
561CONFIG_CRYPTO_KHAZAD=m
562CONFIG_CRYPTO_SALSA20=m
563CONFIG_CRYPTO_SEED=m
564CONFIG_CRYPTO_SERPENT=m
565CONFIG_CRYPTO_TEA=m
566CONFIG_CRYPTO_TWOFISH=m
567CONFIG_CRYPTO_ZLIB=m
568CONFIG_CRYPTO_LZO=m
569CONFIG_CRC_CCITT=m
570CONFIG_CRC7=m
diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig
index e4b399fdaa61..7c68666fdd64 100644
--- a/arch/mips/configs/nlm_xlr_defconfig
+++ b/arch/mips/configs/nlm_xlr_defconfig
@@ -8,7 +8,7 @@ CONFIG_HIGH_RES_TIMERS=y
8CONFIG_PREEMPT_VOLUNTARY=y 8CONFIG_PREEMPT_VOLUNTARY=y
9CONFIG_KEXEC=y 9CONFIG_KEXEC=y
10CONFIG_EXPERIMENTAL=y 10CONFIG_EXPERIMENTAL=y
11CONFIG_CROSS_COMPILE="mips64-unknown-linux-gnu-" 11CONFIG_CROSS_COMPILE="mips-linux-gnu-"
12# CONFIG_LOCALVERSION_AUTO is not set 12# CONFIG_LOCALVERSION_AUTO is not set
13CONFIG_SYSVIPC=y 13CONFIG_SYSVIPC=y
14CONFIG_POSIX_MQUEUE=y 14CONFIG_POSIX_MQUEUE=y
@@ -22,15 +22,13 @@ CONFIG_AUDIT=y
22CONFIG_NAMESPACES=y 22CONFIG_NAMESPACES=y
23CONFIG_SCHED_AUTOGROUP=y 23CONFIG_SCHED_AUTOGROUP=y
24CONFIG_BLK_DEV_INITRD=y 24CONFIG_BLK_DEV_INITRD=y
25CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs" 25CONFIG_INITRAMFS_SOURCE="usr/dev_file_list usr/rootfs.xlr"
26CONFIG_RD_BZIP2=y 26CONFIG_RD_BZIP2=y
27CONFIG_RD_LZMA=y 27CONFIG_RD_LZMA=y
28CONFIG_INITRAMFS_COMPRESSION_GZIP=y 28CONFIG_INITRAMFS_COMPRESSION_GZIP=y
29# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
30CONFIG_EXPERT=y 29CONFIG_EXPERT=y
31CONFIG_KALLSYMS_ALL=y 30CONFIG_KALLSYMS_ALL=y
32# CONFIG_ELF_CORE is not set 31# CONFIG_ELF_CORE is not set
33# CONFIG_PCSPKR_PLATFORM is not set
34# CONFIG_PERF_EVENTS is not set 32# CONFIG_PERF_EVENTS is not set
35# CONFIG_COMPAT_BRK is not set 33# CONFIG_COMPAT_BRK is not set
36CONFIG_PROFILING=y 34CONFIG_PROFILING=y
@@ -39,6 +37,9 @@ CONFIG_MODULE_UNLOAD=y
39CONFIG_MODVERSIONS=y 37CONFIG_MODVERSIONS=y
40CONFIG_MODULE_SRCVERSION_ALL=y 38CONFIG_MODULE_SRCVERSION_ALL=y
41CONFIG_BLK_DEV_INTEGRITY=y 39CONFIG_BLK_DEV_INTEGRITY=y
40CONFIG_PCI=y
41CONFIG_PCI_MSI=y
42CONFIG_PCI_DEBUG=y
42CONFIG_BINFMT_MISC=m 43CONFIG_BINFMT_MISC=m
43CONFIG_PM_RUNTIME=y 44CONFIG_PM_RUNTIME=y
44CONFIG_PM_DEBUG=y 45CONFIG_PM_DEBUG=y
@@ -297,12 +298,10 @@ CONFIG_NET_ACT_SIMP=m
297CONFIG_NET_ACT_SKBEDIT=m 298CONFIG_NET_ACT_SKBEDIT=m
298CONFIG_DCB=y 299CONFIG_DCB=y
299CONFIG_NET_PKTGEN=m 300CONFIG_NET_PKTGEN=m
300# CONFIG_WIRELESS is not set
301CONFIG_DEVTMPFS=y 301CONFIG_DEVTMPFS=y
302CONFIG_DEVTMPFS_MOUNT=y 302CONFIG_DEVTMPFS_MOUNT=y
303# CONFIG_STANDALONE is not set 303# CONFIG_STANDALONE is not set
304CONFIG_CONNECTOR=y 304CONFIG_CONNECTOR=y
305CONFIG_MTD=m
306CONFIG_BLK_DEV_LOOP=y 305CONFIG_BLK_DEV_LOOP=y
307CONFIG_BLK_DEV_CRYPTOLOOP=m 306CONFIG_BLK_DEV_CRYPTOLOOP=m
308CONFIG_BLK_DEV_NBD=m 307CONFIG_BLK_DEV_NBD=m
@@ -339,6 +338,9 @@ CONFIG_SCSI_DH_EMC=m
339CONFIG_SCSI_DH_ALUA=m 338CONFIG_SCSI_DH_ALUA=m
340CONFIG_SCSI_OSD_INITIATOR=m 339CONFIG_SCSI_OSD_INITIATOR=m
341CONFIG_SCSI_OSD_ULD=m 340CONFIG_SCSI_OSD_ULD=m
341CONFIG_NETDEVICES=y
342CONFIG_E1000E=y
343CONFIG_SKY2=y
342# CONFIG_INPUT_MOUSEDEV is not set 344# CONFIG_INPUT_MOUSEDEV is not set
343CONFIG_INPUT_EVDEV=y 345CONFIG_INPUT_EVDEV=y
344CONFIG_INPUT_EVBUG=m 346CONFIG_INPUT_EVBUG=m
@@ -443,7 +445,6 @@ CONFIG_CIFS_UPCALL=y
443CONFIG_CIFS_XATTR=y 445CONFIG_CIFS_XATTR=y
444CONFIG_CIFS_POSIX=y 446CONFIG_CIFS_POSIX=y
445CONFIG_CIFS_DFS_UPCALL=y 447CONFIG_CIFS_DFS_UPCALL=y
446CONFIG_CIFS_EXPERIMENTAL=y
447CONFIG_NCP_FS=m 448CONFIG_NCP_FS=m
448CONFIG_NCPFS_PACKET_SIGNING=y 449CONFIG_NCPFS_PACKET_SIGNING=y
449CONFIG_NCPFS_IOCTL_LOCKING=y 450CONFIG_NCPFS_IOCTL_LOCKING=y
@@ -516,7 +517,6 @@ CONFIG_PRINTK_TIME=y
516# CONFIG_ENABLE_WARN_DEPRECATED is not set 517# CONFIG_ENABLE_WARN_DEPRECATED is not set
517# CONFIG_ENABLE_MUST_CHECK is not set 518# CONFIG_ENABLE_MUST_CHECK is not set
518CONFIG_UNUSED_SYMBOLS=y 519CONFIG_UNUSED_SYMBOLS=y
519CONFIG_DEBUG_KERNEL=y
520CONFIG_DETECT_HUNG_TASK=y 520CONFIG_DETECT_HUNG_TASK=y
521CONFIG_SCHEDSTATS=y 521CONFIG_SCHEDSTATS=y
522CONFIG_TIMER_STATS=y 522CONFIG_TIMER_STATS=y
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
new file mode 100644
index 000000000000..552a65a0cf2b
--- /dev/null
+++ b/arch/mips/include/asm/bmips.h
@@ -0,0 +1,110 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * Definitions for BMIPS processors
9 */
10#ifndef _ASM_BMIPS_H
11#define _ASM_BMIPS_H
12
13#include <linux/compiler.h>
14#include <linux/linkage.h>
15#include <asm/addrspace.h>
16#include <asm/mipsregs.h>
17#include <asm/hazards.h>
18
19/* NOTE: the CBR register returns a PA, and it can be above 0xff00_0000 */
20#define BMIPS_GET_CBR() ((void __iomem *)(CKSEG1 | \
21 (unsigned long) \
22 ((read_c0_brcm_cbr() >> 18) << 18)))
23
24#define BMIPS_RAC_CONFIG 0x00000000
25#define BMIPS_RAC_ADDRESS_RANGE 0x00000004
26#define BMIPS_RAC_CONFIG_1 0x00000008
27#define BMIPS_L2_CONFIG 0x0000000c
28#define BMIPS_LMB_CONTROL 0x0000001c
29#define BMIPS_SYSTEM_BASE 0x00000020
30#define BMIPS_PERF_GLOBAL_CONTROL 0x00020000
31#define BMIPS_PERF_CONTROL_0 0x00020004
32#define BMIPS_PERF_CONTROL_1 0x00020008
33#define BMIPS_PERF_COUNTER_0 0x00020010
34#define BMIPS_PERF_COUNTER_1 0x00020014
35#define BMIPS_PERF_COUNTER_2 0x00020018
36#define BMIPS_PERF_COUNTER_3 0x0002001c
37#define BMIPS_RELO_VECTOR_CONTROL_0 0x00030000
38#define BMIPS_RELO_VECTOR_CONTROL_1 0x00038000
39
40#define BMIPS_NMI_RESET_VEC 0x80000000
41#define BMIPS_WARM_RESTART_VEC 0x80000380
42
43#define ZSCM_REG_BASE 0x97000000
44
45#if !defined(__ASSEMBLY__)
46
47#include <linux/cpumask.h>
48#include <asm/r4kcache.h>
49
50extern struct plat_smp_ops bmips_smp_ops;
51extern char bmips_reset_nmi_vec;
52extern char bmips_reset_nmi_vec_end;
53extern char bmips_smp_movevec;
54extern char bmips_smp_int_vec;
55extern char bmips_smp_int_vec_end;
56
57extern int bmips_smp_enabled;
58extern int bmips_cpu_offset;
59extern cpumask_t bmips_booted_mask;
60
61extern void bmips_ebase_setup(void);
62extern asmlinkage void plat_wired_tlb_setup(void);
63
64static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
65{
66 unsigned long ret;
67
68 __asm__ __volatile__(
69 ".set push\n"
70 ".set noreorder\n"
71 "cache %1, 0(%2)\n"
72 "sync\n"
73 "_ssnop\n"
74 "_ssnop\n"
75 "_ssnop\n"
76 "_ssnop\n"
77 "_ssnop\n"
78 "_ssnop\n"
79 "_ssnop\n"
80 "mfc0 %0, $28, 3\n"
81 "_ssnop\n"
82 ".set pop\n"
83 : "=&r" (ret)
84 : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
85 : "memory");
86 return ret;
87}
88
89static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
90{
91 __asm__ __volatile__(
92 ".set push\n"
93 ".set noreorder\n"
94 "mtc0 %0, $28, 3\n"
95 "_ssnop\n"
96 "_ssnop\n"
97 "_ssnop\n"
98 "cache %1, 0(%2)\n"
99 "_ssnop\n"
100 "_ssnop\n"
101 "_ssnop\n"
102 : /* no outputs */
103 : "r" (data),
104 "i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
105 : "memory");
106}
107
108#endif /* !defined(__ASSEMBLY__) */
109
110#endif /* _ASM_BMIPS_H */
diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
index 37c6857c8d4a..888766ae1f85 100644
--- a/arch/mips/include/asm/branch.h
+++ b/arch/mips/include/asm/branch.h
@@ -9,6 +9,7 @@
9#define _ASM_BRANCH_H 9#define _ASM_BRANCH_H
10 10
11#include <asm/ptrace.h> 11#include <asm/ptrace.h>
12#include <asm/inst.h>
12 13
13static inline int delay_slot(struct pt_regs *regs) 14static inline int delay_slot(struct pt_regs *regs)
14{ 15{
@@ -23,7 +24,11 @@ static inline unsigned long exception_epc(struct pt_regs *regs)
23 return regs->cp0_epc + 4; 24 return regs->cp0_epc + 4;
24} 25}
25 26
27#define BRANCH_LIKELY_TAKEN 0x0001
28
26extern int __compute_return_epc(struct pt_regs *regs); 29extern int __compute_return_epc(struct pt_regs *regs);
30extern int __compute_return_epc_for_insn(struct pt_regs *regs,
31 union mips_instruction insn);
27 32
28static inline int compute_return_epc(struct pt_regs *regs) 33static inline int compute_return_epc(struct pt_regs *regs)
29{ 34{
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 79e4a0dad0d9..f9fa2a479dd0 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -171,6 +171,9 @@
171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 171#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
172#define PRID_IMP_NETLOGIC_AU13XX 0x8000 172#define PRID_IMP_NETLOGIC_AU13XX 0x8000
173 173
174#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
175#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
176
174/* 177/*
175 * Definitions for 7:0 on legacy processors 178 * Definitions for 7:0 on legacy processors
176 */ 179 */
@@ -264,7 +267,7 @@ enum cpu_type_enum {
264 */ 267 */
265 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 268 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
266 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, 269 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
267 CPU_XLR, 270 CPU_XLR, CPU_XLP,
268 271
269 CPU_LAST 272 CPU_LAST
270}; 273};
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 4e332165d7b7..b4c20e4f87cd 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,8 @@ do { \
87 : "=r" (tmp)); \ 87 : "=r" (tmp)); \
88} while (0) 88} while (0)
89 89
90#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY) 90#elif (defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MIPS_ALCHEMY)) || \
91 defined(CONFIG_CPU_BMIPS)
91 92
92/* 93/*
93 * These are slightly complicated by the fact that we guarantee R1 kernels to 94 * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -139,8 +140,8 @@ do { \
139} while (0) 140} while (0)
140 141
141#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 142#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
142 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ 143 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
143 defined(CONFIG_CPU_R5500) 144 defined(CONFIG_CPU_R5500)
144 145
145/* 146/*
146 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 147 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
index e6ea4d4d7205..1fbbca01e681 100644
--- a/arch/mips/include/asm/kprobes.h
+++ b/arch/mips/include/asm/kprobes.h
@@ -74,6 +74,8 @@ struct prev_kprobe {
74 : MAX_JPROBES_STACK_SIZE) 74 : MAX_JPROBES_STACK_SIZE)
75 75
76 76
77#define SKIP_DELAYSLOT 0x0001
78
77/* per-cpu kprobe control block */ 79/* per-cpu kprobe control block */
78struct kprobe_ctlblk { 80struct kprobe_ctlblk {
79 unsigned long kprobe_status; 81 unsigned long kprobe_status;
@@ -82,6 +84,9 @@ struct kprobe_ctlblk {
82 unsigned long kprobe_saved_epc; 84 unsigned long kprobe_saved_epc;
83 unsigned long jprobe_saved_sp; 85 unsigned long jprobe_saved_sp;
84 struct pt_regs jprobe_saved_regs; 86 struct pt_regs jprobe_saved_regs;
87 /* Per-thread fields, used while emulating branches */
88 unsigned long flags;
89 unsigned long target_epc;
85 u8 jprobes_stack[MAX_JPROBES_STACK_SIZE]; 90 u8 jprobes_stack[MAX_JPROBES_STACK_SIZE];
86 struct prev_kprobe prev_kprobe; 91 struct prev_kprobe prev_kprobe;
87}; 92};
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index cda1c8070b27..2f0becb4ec8f 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -20,6 +20,10 @@
20#include <linux/bitops.h> 20#include <linux/bitops.h>
21 21
22#define AR71XX_APB_BASE 0x18000000 22#define AR71XX_APB_BASE 0x18000000
23#define AR71XX_EHCI_BASE 0x1b000000
24#define AR71XX_EHCI_SIZE 0x1000
25#define AR71XX_OHCI_BASE 0x1c000000
26#define AR71XX_OHCI_SIZE 0x1000
23#define AR71XX_SPI_BASE 0x1f000000 27#define AR71XX_SPI_BASE 0x1f000000
24#define AR71XX_SPI_SIZE 0x01000000 28#define AR71XX_SPI_SIZE 0x01000000
25 29
@@ -27,6 +31,8 @@
27#define AR71XX_DDR_CTRL_SIZE 0x100 31#define AR71XX_DDR_CTRL_SIZE 0x100
28#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) 32#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
29#define AR71XX_UART_SIZE 0x100 33#define AR71XX_UART_SIZE 0x100
34#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
35#define AR71XX_USB_CTRL_SIZE 0x100
30#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) 36#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
31#define AR71XX_GPIO_SIZE 0x100 37#define AR71XX_GPIO_SIZE 0x100
32#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) 38#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
@@ -34,9 +40,26 @@
34#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) 40#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
35#define AR71XX_RESET_SIZE 0x100 41#define AR71XX_RESET_SIZE 0x100
36 42
43#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
44#define AR7240_USB_CTRL_SIZE 0x100
45#define AR7240_OHCI_BASE 0x1b000000
46#define AR7240_OHCI_SIZE 0x1000
47
48#define AR724X_EHCI_BASE 0x1b000000
49#define AR724X_EHCI_SIZE 0x1000
50
51#define AR913X_EHCI_BASE 0x1b000000
52#define AR913X_EHCI_SIZE 0x1000
37#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) 53#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
38#define AR913X_WMAC_SIZE 0x30000 54#define AR913X_WMAC_SIZE 0x30000
39 55
56#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
57#define AR933X_UART_SIZE 0x14
58#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
59#define AR933X_WMAC_SIZE 0x20000
60#define AR933X_EHCI_BASE 0x1b000000
61#define AR933X_EHCI_SIZE 0x1000
62
40/* 63/*
41 * DDR_CTRL block 64 * DDR_CTRL block
42 */ 65 */
@@ -63,6 +86,11 @@
63#define AR913X_DDR_REG_FLUSH_USB 0x84 86#define AR913X_DDR_REG_FLUSH_USB 0x84
64#define AR913X_DDR_REG_FLUSH_WMAC 0x88 87#define AR913X_DDR_REG_FLUSH_WMAC 0x88
65 88
89#define AR933X_DDR_REG_FLUSH_GE0 0x7c
90#define AR933X_DDR_REG_FLUSH_GE1 0x80
91#define AR933X_DDR_REG_FLUSH_USB 0x84
92#define AR933X_DDR_REG_FLUSH_WMAC 0x88
93
66/* 94/*
67 * PLL block 95 * PLL block
68 */ 96 */
@@ -104,6 +132,30 @@
104#define AR913X_AHB_DIV_SHIFT 19 132#define AR913X_AHB_DIV_SHIFT 19
105#define AR913X_AHB_DIV_MASK 0x1 133#define AR913X_AHB_DIV_MASK 0x1
106 134
135#define AR933X_PLL_CPU_CONFIG_REG 0x00
136#define AR933X_PLL_CLOCK_CTRL_REG 0x08
137
138#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
139#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
140#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
141#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
142#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
143#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
144
145#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
146#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
147#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
148#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
149#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
150#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
151#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
152
153/*
154 * USB_CONFIG block
155 */
156#define AR71XX_USB_CTRL_REG_FLADJ 0x00
157#define AR71XX_USB_CTRL_REG_CONFIG 0x04
158
107/* 159/*
108 * RESET block 160 * RESET block
109 */ 161 */
@@ -130,6 +182,13 @@
130 182
131#define AR724X_RESET_REG_RESET_MODULE 0x1c 183#define AR724X_RESET_REG_RESET_MODULE 0x1c
132 184
185#define AR933X_RESET_REG_RESET_MODULE 0x1c
186#define AR933X_RESET_REG_BOOTSTRAP 0xac
187
188#define MISC_INT_ETHSW BIT(12)
189#define MISC_INT_TIMER4 BIT(10)
190#define MISC_INT_TIMER3 BIT(9)
191#define MISC_INT_TIMER2 BIT(8)
133#define MISC_INT_DMA BIT(7) 192#define MISC_INT_DMA BIT(7)
134#define MISC_INT_OHCI BIT(6) 193#define MISC_INT_OHCI BIT(6)
135#define MISC_INT_PERFC BIT(5) 194#define MISC_INT_PERFC BIT(5)
@@ -158,14 +217,29 @@
158#define AR71XX_RESET_PCI_BUS BIT(1) 217#define AR71XX_RESET_PCI_BUS BIT(1)
159#define AR71XX_RESET_PCI_CORE BIT(0) 218#define AR71XX_RESET_PCI_CORE BIT(0)
160 219
220#define AR7240_RESET_USB_HOST BIT(5)
221#define AR7240_RESET_OHCI_DLL BIT(3)
222
161#define AR724X_RESET_GE1_MDIO BIT(23) 223#define AR724X_RESET_GE1_MDIO BIT(23)
162#define AR724X_RESET_GE0_MDIO BIT(22) 224#define AR724X_RESET_GE0_MDIO BIT(22)
163#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) 225#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
164#define AR724X_RESET_PCIE_PHY BIT(7) 226#define AR724X_RESET_PCIE_PHY BIT(7)
165#define AR724X_RESET_PCIE BIT(6) 227#define AR724X_RESET_PCIE BIT(6)
166#define AR724X_RESET_OHCI_DLL BIT(3) 228#define AR724X_RESET_USB_HOST BIT(5)
229#define AR724X_RESET_USB_PHY BIT(4)
230#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
167 231
168#define AR913X_RESET_AMBA2WMAC BIT(22) 232#define AR913X_RESET_AMBA2WMAC BIT(22)
233#define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
234#define AR913X_RESET_USB_HOST BIT(5)
235#define AR913X_RESET_USB_PHY BIT(4)
236
237#define AR933X_RESET_WMAC BIT(11)
238#define AR933X_RESET_USB_HOST BIT(5)
239#define AR933X_RESET_USB_PHY BIT(4)
240#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
241
242#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
169 243
170#define REV_ID_MAJOR_MASK 0xfff0 244#define REV_ID_MAJOR_MASK 0xfff0
171#define REV_ID_MAJOR_AR71XX 0x00a0 245#define REV_ID_MAJOR_AR71XX 0x00a0
@@ -173,6 +247,8 @@
173#define REV_ID_MAJOR_AR7240 0x00c0 247#define REV_ID_MAJOR_AR7240 0x00c0
174#define REV_ID_MAJOR_AR7241 0x0100 248#define REV_ID_MAJOR_AR7241 0x0100
175#define REV_ID_MAJOR_AR7242 0x1100 249#define REV_ID_MAJOR_AR7242 0x1100
250#define REV_ID_MAJOR_AR9330 0x0110
251#define REV_ID_MAJOR_AR9331 0x1110
176 252
177#define AR71XX_REV_ID_MINOR_MASK 0x3 253#define AR71XX_REV_ID_MINOR_MASK 0x3
178#define AR71XX_REV_ID_MINOR_AR7130 0x0 254#define AR71XX_REV_ID_MINOR_AR7130 0x0
@@ -187,6 +263,8 @@
187#define AR913X_REV_ID_REVISION_MASK 0x3 263#define AR913X_REV_ID_REVISION_MASK 0x3
188#define AR913X_REV_ID_REVISION_SHIFT 2 264#define AR913X_REV_ID_REVISION_SHIFT 2
189 265
266#define AR933X_REV_ID_REVISION_MASK 0x3
267
190#define AR724X_REV_ID_REVISION_MASK 0x3 268#define AR724X_REV_ID_REVISION_MASK 0x3
191 269
192/* 270/*
@@ -229,5 +307,6 @@
229#define AR71XX_GPIO_COUNT 16 307#define AR71XX_GPIO_COUNT 16
230#define AR724X_GPIO_COUNT 18 308#define AR724X_GPIO_COUNT 18
231#define AR913X_GPIO_COUNT 22 309#define AR913X_GPIO_COUNT 22
310#define AR933X_GPIO_COUNT 30
232 311
233#endif /* __ASM_MACH_AR71XX_REGS_H */ 312#endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
new file mode 100644
index 000000000000..52730555937f
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
@@ -0,0 +1,67 @@
1/*
2 * Atheros AR933X UART defines
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef __AR933X_UART_H
12#define __AR933X_UART_H
13
14#define AR933X_UART_REGS_SIZE 20
15#define AR933X_UART_FIFO_SIZE 16
16
17#define AR933X_UART_DATA_REG 0x00
18#define AR933X_UART_CS_REG 0x04
19#define AR933X_UART_CLOCK_REG 0x08
20#define AR933X_UART_INT_REG 0x0c
21#define AR933X_UART_INT_EN_REG 0x10
22
23#define AR933X_UART_DATA_TX_RX_MASK 0xff
24#define AR933X_UART_DATA_RX_CSR BIT(8)
25#define AR933X_UART_DATA_TX_CSR BIT(9)
26
27#define AR933X_UART_CS_PARITY_S 0
28#define AR933X_UART_CS_PARITY_M 0x3
29#define AR933X_UART_CS_PARITY_NONE 0
30#define AR933X_UART_CS_PARITY_ODD 1
31#define AR933X_UART_CS_PARITY_EVEN 2
32#define AR933X_UART_CS_IF_MODE_S 2
33#define AR933X_UART_CS_IF_MODE_M 0x3
34#define AR933X_UART_CS_IF_MODE_NONE 0
35#define AR933X_UART_CS_IF_MODE_DTE 1
36#define AR933X_UART_CS_IF_MODE_DCE 2
37#define AR933X_UART_CS_FLOW_CTRL_S 4
38#define AR933X_UART_CS_FLOW_CTRL_M 0x3
39#define AR933X_UART_CS_DMA_EN BIT(6)
40#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
41#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
42#define AR933X_UART_CS_TX_READY BIT(9)
43#define AR933X_UART_CS_RX_BREAK BIT(10)
44#define AR933X_UART_CS_TX_BREAK BIT(11)
45#define AR933X_UART_CS_HOST_INT BIT(12)
46#define AR933X_UART_CS_HOST_INT_EN BIT(13)
47#define AR933X_UART_CS_TX_BUSY BIT(14)
48#define AR933X_UART_CS_RX_BUSY BIT(15)
49
50#define AR933X_UART_CLOCK_STEP_M 0xffff
51#define AR933X_UART_CLOCK_SCALE_M 0xfff
52#define AR933X_UART_CLOCK_SCALE_S 16
53#define AR933X_UART_CLOCK_STEP_M 0xffff
54
55#define AR933X_UART_INT_RX_VALID BIT(0)
56#define AR933X_UART_INT_TX_READY BIT(1)
57#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
58#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
59#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
60#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
61#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
62#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
63#define AR933X_UART_INT_RX_FULL BIT(8)
64#define AR933X_UART_INT_TX_EMPTY BIT(9)
65#define AR933X_UART_INT_ALLINTS 0x3ff
66
67#endif /* __AR933X_UART_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
new file mode 100644
index 000000000000..6cb30f2b7198
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart_platform.h
@@ -0,0 +1,18 @@
1/*
2 * Platform data definition for Atheros AR933X UART
3 *
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef _AR933X_UART_PLATFORM_H
12#define _AR933X_UART_PLATFORM_H
13
14struct ar933x_uart_platform_data {
15 unsigned uartclk;
16};
17
18#endif /* _AR933X_UART_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 6a9f168506fe..6d0c6c9d5622 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -26,10 +26,13 @@ enum ath79_soc_type {
26 ATH79_SOC_AR7241, 26 ATH79_SOC_AR7241,
27 ATH79_SOC_AR7242, 27 ATH79_SOC_AR7242,
28 ATH79_SOC_AR9130, 28 ATH79_SOC_AR9130,
29 ATH79_SOC_AR9132 29 ATH79_SOC_AR9132,
30 ATH79_SOC_AR9330,
31 ATH79_SOC_AR9331,
30}; 32};
31 33
32extern enum ath79_soc_type ath79_soc; 34extern enum ath79_soc_type ath79_soc;
35extern unsigned int ath79_soc_rev;
33 36
34static inline int soc_is_ar71xx(void) 37static inline int soc_is_ar71xx(void)
35{ 38{
@@ -66,6 +69,12 @@ static inline int soc_is_ar913x(void)
66 ath79_soc == ATH79_SOC_AR9132); 69 ath79_soc == ATH79_SOC_AR9132);
67} 70}
68 71
72static inline int soc_is_ar933x(void)
73{
74 return (ath79_soc == ATH79_SOC_AR9330 ||
75 ath79_soc == ATH79_SOC_AR9331);
76}
77
69extern void __iomem *ath79_ddr_base; 78extern void __iomem *ath79_ddr_base;
70extern void __iomem *ath79_pll_base; 79extern void __iomem *ath79_pll_base;
71extern void __iomem *ath79_reset_base; 80extern void __iomem *ath79_reset_base;
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 189bc6eb9c10..519958fe4e3c 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,10 +10,10 @@
10#define __ASM_MACH_ATH79_IRQ_H 10#define __ASM_MACH_ATH79_IRQ_H
11 11
12#define MIPS_CPU_IRQ_BASE 0 12#define MIPS_CPU_IRQ_BASE 0
13#define NR_IRQS 16 13#define NR_IRQS 40
14 14
15#define ATH79_MISC_IRQ_BASE 8 15#define ATH79_MISC_IRQ_BASE 8
16#define ATH79_MISC_IRQ_COUNT 8 16#define ATH79_MISC_IRQ_COUNT 32
17 17
18#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) 18#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
19#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) 19#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
@@ -30,6 +30,10 @@
30#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5) 30#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
31#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6) 31#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
32#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7) 32#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
33#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
34#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
35#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
36#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
33 37
34#include_next <irq.h> 38#include_next <irq.h>
35 39
diff --git a/arch/mips/include/asm/mach-ath79/pci-ath724x.h b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
new file mode 100644
index 000000000000..454885fa30c3
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath79/pci-ath724x.h
@@ -0,0 +1,21 @@
1/*
2 * Atheros 724x PCI support
3 *
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
12#define __ASM_MACH_ATH79_PCI_ATH724X_H
13
14struct ath724x_pci_data {
15 int irq;
16 void *pdata;
17};
18
19void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
20
21#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 96a2391ad85b..5b8d15bb5fe8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -13,6 +13,7 @@
13#define BCM6345_CPU_ID 0x6345 13#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348 14#define BCM6348_CPU_ID 0x6348
15#define BCM6358_CPU_ID 0x6358 15#define BCM6358_CPU_ID 0x6358
16#define BCM6368_CPU_ID 0x6368
16 17
17void __init bcm63xx_cpu_init(void); 18void __init bcm63xx_cpu_init(void);
18u16 __bcm63xx_get_cpu_id(void); 19u16 __bcm63xx_get_cpu_id(void);
@@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
71# define BCMCPU_IS_6358() (0) 72# define BCMCPU_IS_6358() (0)
72#endif 73#endif
73 74
75#ifdef CONFIG_BCM63XX_CPU_6368
76# ifdef bcm63xx_get_cpu_id
77# undef bcm63xx_get_cpu_id
78# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
79# define BCMCPU_RUNTIME_DETECT
80# else
81# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
82# endif
83# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
84#else
85# define BCMCPU_IS_6368() (0)
86#endif
87
74#ifndef bcm63xx_get_cpu_id 88#ifndef bcm63xx_get_cpu_id
75#error "No CPU support configured" 89#error "No CPU support configured"
76#endif 90#endif
@@ -88,6 +102,7 @@ enum bcm63xx_regs_set {
88 RSET_UART1, 102 RSET_UART1,
89 RSET_GPIO, 103 RSET_GPIO,
90 RSET_SPI, 104 RSET_SPI,
105 RSET_SPI2,
91 RSET_UDC0, 106 RSET_UDC0,
92 RSET_OHCI0, 107 RSET_OHCI0,
93 RSET_OHCI_PRIV, 108 RSET_OHCI_PRIV,
@@ -98,10 +113,23 @@ enum bcm63xx_regs_set {
98 RSET_ENET0, 113 RSET_ENET0,
99 RSET_ENET1, 114 RSET_ENET1,
100 RSET_ENETDMA, 115 RSET_ENETDMA,
116 RSET_ENETDMAC,
117 RSET_ENETDMAS,
118 RSET_ENETSW,
101 RSET_EHCI0, 119 RSET_EHCI0,
102 RSET_SDRAM, 120 RSET_SDRAM,
103 RSET_MEMC, 121 RSET_MEMC,
104 RSET_DDR, 122 RSET_DDR,
123 RSET_M2M,
124 RSET_ATM,
125 RSET_XTM,
126 RSET_XTMDMA,
127 RSET_XTMDMAC,
128 RSET_XTMDMAS,
129 RSET_PCM,
130 RSET_PCMDMA,
131 RSET_PCMDMAC,
132 RSET_PCMDMAS,
105}; 133};
106 134
107#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 135#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
@@ -109,11 +137,18 @@ enum bcm63xx_regs_set {
109#define RSET_WDT_SIZE 12 137#define RSET_WDT_SIZE 12
110#define RSET_ENET_SIZE 2048 138#define RSET_ENET_SIZE 2048
111#define RSET_ENETDMA_SIZE 2048 139#define RSET_ENETDMA_SIZE 2048
140#define RSET_ENETSW_SIZE 65536
112#define RSET_UART_SIZE 24 141#define RSET_UART_SIZE 24
113#define RSET_UDC_SIZE 256 142#define RSET_UDC_SIZE 256
114#define RSET_OHCI_SIZE 256 143#define RSET_OHCI_SIZE 256
115#define RSET_EHCI_SIZE 256 144#define RSET_EHCI_SIZE 256
116#define RSET_PCMCIA_SIZE 12 145#define RSET_PCMCIA_SIZE 12
146#define RSET_M2M_SIZE 256
147#define RSET_ATM_SIZE 4096
148#define RSET_XTM_SIZE 10240
149#define RSET_XTMDMA_SIZE 256
150#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
151#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
117 152
118/* 153/*
119 * 6338 register sets base address 154 * 6338 register sets base address
@@ -127,6 +162,7 @@ enum bcm63xx_regs_set {
127#define BCM_6338_UART1_BASE (0xdeadbeef) 162#define BCM_6338_UART1_BASE (0xdeadbeef)
128#define BCM_6338_GPIO_BASE (0xfffe0400) 163#define BCM_6338_GPIO_BASE (0xfffe0400)
129#define BCM_6338_SPI_BASE (0xfffe0c00) 164#define BCM_6338_SPI_BASE (0xfffe0c00)
165#define BCM_6338_SPI2_BASE (0xdeadbeef)
130#define BCM_6338_UDC0_BASE (0xdeadbeef) 166#define BCM_6338_UDC0_BASE (0xdeadbeef)
131#define BCM_6338_USBDMA_BASE (0xfffe2400) 167#define BCM_6338_USBDMA_BASE (0xfffe2400)
132#define BCM_6338_OHCI0_BASE (0xdeadbeef) 168#define BCM_6338_OHCI0_BASE (0xdeadbeef)
@@ -136,15 +172,27 @@ enum bcm63xx_regs_set {
136#define BCM_6338_PCMCIA_BASE (0xdeadbeef) 172#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
137#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 173#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
138#define BCM_6338_DSL_BASE (0xfffe1000) 174#define BCM_6338_DSL_BASE (0xfffe1000)
139#define BCM_6338_SAR_BASE (0xfffe2000)
140#define BCM_6338_UBUS_BASE (0xdeadbeef) 175#define BCM_6338_UBUS_BASE (0xdeadbeef)
141#define BCM_6338_ENET0_BASE (0xfffe2800) 176#define BCM_6338_ENET0_BASE (0xfffe2800)
142#define BCM_6338_ENET1_BASE (0xdeadbeef) 177#define BCM_6338_ENET1_BASE (0xdeadbeef)
143#define BCM_6338_ENETDMA_BASE (0xfffe2400) 178#define BCM_6338_ENETDMA_BASE (0xfffe2400)
179#define BCM_6338_ENETDMAC_BASE (0xfffe2500)
180#define BCM_6338_ENETDMAS_BASE (0xfffe2600)
181#define BCM_6338_ENETSW_BASE (0xdeadbeef)
144#define BCM_6338_EHCI0_BASE (0xdeadbeef) 182#define BCM_6338_EHCI0_BASE (0xdeadbeef)
145#define BCM_6338_SDRAM_BASE (0xfffe3100) 183#define BCM_6338_SDRAM_BASE (0xfffe3100)
146#define BCM_6338_MEMC_BASE (0xdeadbeef) 184#define BCM_6338_MEMC_BASE (0xdeadbeef)
147#define BCM_6338_DDR_BASE (0xdeadbeef) 185#define BCM_6338_DDR_BASE (0xdeadbeef)
186#define BCM_6338_M2M_BASE (0xdeadbeef)
187#define BCM_6338_ATM_BASE (0xfffe2000)
188#define BCM_6338_XTM_BASE (0xdeadbeef)
189#define BCM_6338_XTMDMA_BASE (0xdeadbeef)
190#define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
191#define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
192#define BCM_6338_PCM_BASE (0xdeadbeef)
193#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
194#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
195#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
148 196
149/* 197/*
150 * 6345 register sets base address 198 * 6345 register sets base address
@@ -158,24 +206,37 @@ enum bcm63xx_regs_set {
158#define BCM_6345_UART1_BASE (0xdeadbeef) 206#define BCM_6345_UART1_BASE (0xdeadbeef)
159#define BCM_6345_GPIO_BASE (0xfffe0400) 207#define BCM_6345_GPIO_BASE (0xfffe0400)
160#define BCM_6345_SPI_BASE (0xdeadbeef) 208#define BCM_6345_SPI_BASE (0xdeadbeef)
209#define BCM_6345_SPI2_BASE (0xdeadbeef)
161#define BCM_6345_UDC0_BASE (0xdeadbeef) 210#define BCM_6345_UDC0_BASE (0xdeadbeef)
162#define BCM_6345_USBDMA_BASE (0xfffe2800) 211#define BCM_6345_USBDMA_BASE (0xfffe2800)
163#define BCM_6345_ENET0_BASE (0xfffe1800) 212#define BCM_6345_ENET0_BASE (0xfffe1800)
164#define BCM_6345_ENETDMA_BASE (0xfffe2800) 213#define BCM_6345_ENETDMA_BASE (0xfffe2800)
214#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
215#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
216#define BCM_6345_ENETSW_BASE (0xdeadbeef)
165#define BCM_6345_PCMCIA_BASE (0xfffe2028) 217#define BCM_6345_PCMCIA_BASE (0xfffe2028)
166#define BCM_6345_MPI_BASE (0xdeadbeef) 218#define BCM_6345_MPI_BASE (0xfffe2000)
167#define BCM_6345_OHCI0_BASE (0xfffe2100) 219#define BCM_6345_OHCI0_BASE (0xfffe2100)
168#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 220#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
169#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 221#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
170#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 222#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
171#define BCM_6345_DSL_BASE (0xdeadbeef) 223#define BCM_6345_DSL_BASE (0xdeadbeef)
172#define BCM_6345_SAR_BASE (0xdeadbeef)
173#define BCM_6345_UBUS_BASE (0xdeadbeef) 224#define BCM_6345_UBUS_BASE (0xdeadbeef)
174#define BCM_6345_ENET1_BASE (0xdeadbeef) 225#define BCM_6345_ENET1_BASE (0xdeadbeef)
175#define BCM_6345_EHCI0_BASE (0xdeadbeef) 226#define BCM_6345_EHCI0_BASE (0xdeadbeef)
176#define BCM_6345_SDRAM_BASE (0xfffe2300) 227#define BCM_6345_SDRAM_BASE (0xfffe2300)
177#define BCM_6345_MEMC_BASE (0xdeadbeef) 228#define BCM_6345_MEMC_BASE (0xdeadbeef)
178#define BCM_6345_DDR_BASE (0xdeadbeef) 229#define BCM_6345_DDR_BASE (0xdeadbeef)
230#define BCM_6345_M2M_BASE (0xdeadbeef)
231#define BCM_6345_ATM_BASE (0xfffe4000)
232#define BCM_6345_XTM_BASE (0xdeadbeef)
233#define BCM_6345_XTMDMA_BASE (0xdeadbeef)
234#define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
235#define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
236#define BCM_6345_PCM_BASE (0xdeadbeef)
237#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
238#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
239#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
179 240
180/* 241/*
181 * 6348 register sets base address 242 * 6348 register sets base address
@@ -188,6 +249,7 @@ enum bcm63xx_regs_set {
188#define BCM_6348_UART1_BASE (0xdeadbeef) 249#define BCM_6348_UART1_BASE (0xdeadbeef)
189#define BCM_6348_GPIO_BASE (0xfffe0400) 250#define BCM_6348_GPIO_BASE (0xfffe0400)
190#define BCM_6348_SPI_BASE (0xfffe0c00) 251#define BCM_6348_SPI_BASE (0xfffe0c00)
252#define BCM_6348_SPI2_BASE (0xdeadbeef)
191#define BCM_6348_UDC0_BASE (0xfffe1000) 253#define BCM_6348_UDC0_BASE (0xfffe1000)
192#define BCM_6348_OHCI0_BASE (0xfffe1b00) 254#define BCM_6348_OHCI0_BASE (0xfffe1b00)
193#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 255#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
@@ -195,14 +257,27 @@ enum bcm63xx_regs_set {
195#define BCM_6348_MPI_BASE (0xfffe2000) 257#define BCM_6348_MPI_BASE (0xfffe2000)
196#define BCM_6348_PCMCIA_BASE (0xfffe2054) 258#define BCM_6348_PCMCIA_BASE (0xfffe2054)
197#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 259#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
260#define BCM_6348_M2M_BASE (0xfffe2800)
198#define BCM_6348_DSL_BASE (0xfffe3000) 261#define BCM_6348_DSL_BASE (0xfffe3000)
199#define BCM_6348_ENET0_BASE (0xfffe6000) 262#define BCM_6348_ENET0_BASE (0xfffe6000)
200#define BCM_6348_ENET1_BASE (0xfffe6800) 263#define BCM_6348_ENET1_BASE (0xfffe6800)
201#define BCM_6348_ENETDMA_BASE (0xfffe7000) 264#define BCM_6348_ENETDMA_BASE (0xfffe7000)
265#define BCM_6348_ENETDMAC_BASE (0xfffe7100)
266#define BCM_6348_ENETDMAS_BASE (0xfffe7200)
267#define BCM_6348_ENETSW_BASE (0xdeadbeef)
202#define BCM_6348_EHCI0_BASE (0xdeadbeef) 268#define BCM_6348_EHCI0_BASE (0xdeadbeef)
203#define BCM_6348_SDRAM_BASE (0xfffe2300) 269#define BCM_6348_SDRAM_BASE (0xfffe2300)
204#define BCM_6348_MEMC_BASE (0xdeadbeef) 270#define BCM_6348_MEMC_BASE (0xdeadbeef)
205#define BCM_6348_DDR_BASE (0xdeadbeef) 271#define BCM_6348_DDR_BASE (0xdeadbeef)
272#define BCM_6348_ATM_BASE (0xfffe4000)
273#define BCM_6348_XTM_BASE (0xdeadbeef)
274#define BCM_6348_XTMDMA_BASE (0xdeadbeef)
275#define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
276#define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
277#define BCM_6348_PCM_BASE (0xdeadbeef)
278#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
279#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
280#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
206 281
207/* 282/*
208 * 6358 register sets base address 283 * 6358 register sets base address
@@ -215,6 +290,7 @@ enum bcm63xx_regs_set {
215#define BCM_6358_UART1_BASE (0xfffe0120) 290#define BCM_6358_UART1_BASE (0xfffe0120)
216#define BCM_6358_GPIO_BASE (0xfffe0080) 291#define BCM_6358_GPIO_BASE (0xfffe0080)
217#define BCM_6358_SPI_BASE (0xdeadbeef) 292#define BCM_6358_SPI_BASE (0xdeadbeef)
293#define BCM_6358_SPI2_BASE (0xfffe0800)
218#define BCM_6358_UDC0_BASE (0xfffe0800) 294#define BCM_6358_UDC0_BASE (0xfffe0800)
219#define BCM_6358_OHCI0_BASE (0xfffe1400) 295#define BCM_6358_OHCI0_BASE (0xfffe1400)
220#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 296#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
@@ -222,214 +298,175 @@ enum bcm63xx_regs_set {
222#define BCM_6358_MPI_BASE (0xfffe1000) 298#define BCM_6358_MPI_BASE (0xfffe1000)
223#define BCM_6358_PCMCIA_BASE (0xfffe1054) 299#define BCM_6358_PCMCIA_BASE (0xfffe1054)
224#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 300#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
301#define BCM_6358_M2M_BASE (0xdeadbeef)
225#define BCM_6358_DSL_BASE (0xfffe3000) 302#define BCM_6358_DSL_BASE (0xfffe3000)
226#define BCM_6358_ENET0_BASE (0xfffe4000) 303#define BCM_6358_ENET0_BASE (0xfffe4000)
227#define BCM_6358_ENET1_BASE (0xfffe4800) 304#define BCM_6358_ENET1_BASE (0xfffe4800)
228#define BCM_6358_ENETDMA_BASE (0xfffe5000) 305#define BCM_6358_ENETDMA_BASE (0xfffe5000)
306#define BCM_6358_ENETDMAC_BASE (0xfffe5100)
307#define BCM_6358_ENETDMAS_BASE (0xfffe5200)
308#define BCM_6358_ENETSW_BASE (0xdeadbeef)
229#define BCM_6358_EHCI0_BASE (0xfffe1300) 309#define BCM_6358_EHCI0_BASE (0xfffe1300)
230#define BCM_6358_SDRAM_BASE (0xdeadbeef) 310#define BCM_6358_SDRAM_BASE (0xdeadbeef)
231#define BCM_6358_MEMC_BASE (0xfffe1200) 311#define BCM_6358_MEMC_BASE (0xfffe1200)
232#define BCM_6358_DDR_BASE (0xfffe12a0) 312#define BCM_6358_DDR_BASE (0xfffe12a0)
313#define BCM_6358_ATM_BASE (0xfffe2000)
314#define BCM_6358_XTM_BASE (0xdeadbeef)
315#define BCM_6358_XTMDMA_BASE (0xdeadbeef)
316#define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
317#define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
318#define BCM_6358_PCM_BASE (0xfffe1600)
319#define BCM_6358_PCMDMA_BASE (0xfffe1800)
320#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
321#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
322
323
324/*
325 * 6368 register sets base address
326 */
327#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
328#define BCM_6368_PERF_BASE (0xb0000000)
329#define BCM_6368_TIMER_BASE (0xb0000040)
330#define BCM_6368_WDT_BASE (0xb000005c)
331#define BCM_6368_UART0_BASE (0xb0000100)
332#define BCM_6368_UART1_BASE (0xb0000120)
333#define BCM_6368_GPIO_BASE (0xb0000080)
334#define BCM_6368_SPI_BASE (0xdeadbeef)
335#define BCM_6368_SPI2_BASE (0xb0000800)
336#define BCM_6368_UDC0_BASE (0xdeadbeef)
337#define BCM_6368_OHCI0_BASE (0xb0001600)
338#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
339#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
340#define BCM_6368_MPI_BASE (0xb0001000)
341#define BCM_6368_PCMCIA_BASE (0xb0001054)
342#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
343#define BCM_6368_M2M_BASE (0xdeadbeef)
344#define BCM_6368_DSL_BASE (0xdeadbeef)
345#define BCM_6368_ENET0_BASE (0xdeadbeef)
346#define BCM_6368_ENET1_BASE (0xdeadbeef)
347#define BCM_6368_ENETDMA_BASE (0xb0006800)
348#define BCM_6368_ENETDMAC_BASE (0xb0006a00)
349#define BCM_6368_ENETDMAS_BASE (0xb0006c00)
350#define BCM_6368_ENETSW_BASE (0xb0f00000)
351#define BCM_6368_EHCI0_BASE (0xb0001500)
352#define BCM_6368_SDRAM_BASE (0xdeadbeef)
353#define BCM_6368_MEMC_BASE (0xb0001200)
354#define BCM_6368_DDR_BASE (0xb0001280)
355#define BCM_6368_ATM_BASE (0xdeadbeef)
356#define BCM_6368_XTM_BASE (0xb0001800)
357#define BCM_6368_XTMDMA_BASE (0xb0005000)
358#define BCM_6368_XTMDMAC_BASE (0xb0005200)
359#define BCM_6368_XTMDMAS_BASE (0xb0005400)
360#define BCM_6368_PCM_BASE (0xb0004000)
361#define BCM_6368_PCMDMA_BASE (0xb0005800)
362#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
363#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
233 364
234 365
235extern const unsigned long *bcm63xx_regs_base; 366extern const unsigned long *bcm63xx_regs_base;
236 367
368#define __GEN_RSET_BASE(__cpu, __rset) \
369 case RSET_## __rset : \
370 return BCM_## __cpu ##_## __rset ##_BASE;
371
372#define __GEN_RSET(__cpu) \
373 switch (set) { \
374 __GEN_RSET_BASE(__cpu, DSL_LMEM) \
375 __GEN_RSET_BASE(__cpu, PERF) \
376 __GEN_RSET_BASE(__cpu, TIMER) \
377 __GEN_RSET_BASE(__cpu, WDT) \
378 __GEN_RSET_BASE(__cpu, UART0) \
379 __GEN_RSET_BASE(__cpu, UART1) \
380 __GEN_RSET_BASE(__cpu, GPIO) \
381 __GEN_RSET_BASE(__cpu, SPI) \
382 __GEN_RSET_BASE(__cpu, SPI2) \
383 __GEN_RSET_BASE(__cpu, UDC0) \
384 __GEN_RSET_BASE(__cpu, OHCI0) \
385 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
386 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
387 __GEN_RSET_BASE(__cpu, MPI) \
388 __GEN_RSET_BASE(__cpu, PCMCIA) \
389 __GEN_RSET_BASE(__cpu, DSL) \
390 __GEN_RSET_BASE(__cpu, ENET0) \
391 __GEN_RSET_BASE(__cpu, ENET1) \
392 __GEN_RSET_BASE(__cpu, ENETDMA) \
393 __GEN_RSET_BASE(__cpu, ENETDMAC) \
394 __GEN_RSET_BASE(__cpu, ENETDMAS) \
395 __GEN_RSET_BASE(__cpu, ENETSW) \
396 __GEN_RSET_BASE(__cpu, EHCI0) \
397 __GEN_RSET_BASE(__cpu, SDRAM) \
398 __GEN_RSET_BASE(__cpu, MEMC) \
399 __GEN_RSET_BASE(__cpu, DDR) \
400 __GEN_RSET_BASE(__cpu, M2M) \
401 __GEN_RSET_BASE(__cpu, ATM) \
402 __GEN_RSET_BASE(__cpu, XTM) \
403 __GEN_RSET_BASE(__cpu, XTMDMA) \
404 __GEN_RSET_BASE(__cpu, XTMDMAC) \
405 __GEN_RSET_BASE(__cpu, XTMDMAS) \
406 __GEN_RSET_BASE(__cpu, PCM) \
407 __GEN_RSET_BASE(__cpu, PCMDMA) \
408 __GEN_RSET_BASE(__cpu, PCMDMAC) \
409 __GEN_RSET_BASE(__cpu, PCMDMAS) \
410 }
411
412#define __GEN_CPU_REGS_TABLE(__cpu) \
413 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
414 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
415 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
416 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
417 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
418 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
419 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
420 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
421 [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
422 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
423 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
424 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
425 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
426 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
427 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
428 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
429 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
430 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
431 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
432 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \
433 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \
434 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \
435 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
436 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
437 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
438 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
439 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \
440 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \
441 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \
442 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \
443 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \
444 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \
445 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \
446 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
447 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
448 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
449
450
237static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 451static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
238{ 452{
239#ifdef BCMCPU_RUNTIME_DETECT 453#ifdef BCMCPU_RUNTIME_DETECT
240 return bcm63xx_regs_base[set]; 454 return bcm63xx_regs_base[set];
241#else 455#else
242#ifdef CONFIG_BCM63XX_CPU_6338 456#ifdef CONFIG_BCM63XX_CPU_6338
243 switch (set) { 457 __GEN_RSET(6338)
244 case RSET_DSL_LMEM:
245 return BCM_6338_DSL_LMEM_BASE;
246 case RSET_PERF:
247 return BCM_6338_PERF_BASE;
248 case RSET_TIMER:
249 return BCM_6338_TIMER_BASE;
250 case RSET_WDT:
251 return BCM_6338_WDT_BASE;
252 case RSET_UART0:
253 return BCM_6338_UART0_BASE;
254 case RSET_UART1:
255 return BCM_6338_UART1_BASE;
256 case RSET_GPIO:
257 return BCM_6338_GPIO_BASE;
258 case RSET_SPI:
259 return BCM_6338_SPI_BASE;
260 case RSET_UDC0:
261 return BCM_6338_UDC0_BASE;
262 case RSET_OHCI0:
263 return BCM_6338_OHCI0_BASE;
264 case RSET_OHCI_PRIV:
265 return BCM_6338_OHCI_PRIV_BASE;
266 case RSET_USBH_PRIV:
267 return BCM_6338_USBH_PRIV_BASE;
268 case RSET_MPI:
269 return BCM_6338_MPI_BASE;
270 case RSET_PCMCIA:
271 return BCM_6338_PCMCIA_BASE;
272 case RSET_DSL:
273 return BCM_6338_DSL_BASE;
274 case RSET_ENET0:
275 return BCM_6338_ENET0_BASE;
276 case RSET_ENET1:
277 return BCM_6338_ENET1_BASE;
278 case RSET_ENETDMA:
279 return BCM_6338_ENETDMA_BASE;
280 case RSET_EHCI0:
281 return BCM_6338_EHCI0_BASE;
282 case RSET_SDRAM:
283 return BCM_6338_SDRAM_BASE;
284 case RSET_MEMC:
285 return BCM_6338_MEMC_BASE;
286 case RSET_DDR:
287 return BCM_6338_DDR_BASE;
288 }
289#endif 458#endif
290#ifdef CONFIG_BCM63XX_CPU_6345 459#ifdef CONFIG_BCM63XX_CPU_6345
291 switch (set) { 460 __GEN_RSET(6345)
292 case RSET_DSL_LMEM:
293 return BCM_6345_DSL_LMEM_BASE;
294 case RSET_PERF:
295 return BCM_6345_PERF_BASE;
296 case RSET_TIMER:
297 return BCM_6345_TIMER_BASE;
298 case RSET_WDT:
299 return BCM_6345_WDT_BASE;
300 case RSET_UART0:
301 return BCM_6345_UART0_BASE;
302 case RSET_UART1:
303 return BCM_6345_UART1_BASE;
304 case RSET_GPIO:
305 return BCM_6345_GPIO_BASE;
306 case RSET_SPI:
307 return BCM_6345_SPI_BASE;
308 case RSET_UDC0:
309 return BCM_6345_UDC0_BASE;
310 case RSET_OHCI0:
311 return BCM_6345_OHCI0_BASE;
312 case RSET_OHCI_PRIV:
313 return BCM_6345_OHCI_PRIV_BASE;
314 case RSET_USBH_PRIV:
315 return BCM_6345_USBH_PRIV_BASE;
316 case RSET_MPI:
317 return BCM_6345_MPI_BASE;
318 case RSET_PCMCIA:
319 return BCM_6345_PCMCIA_BASE;
320 case RSET_DSL:
321 return BCM_6345_DSL_BASE;
322 case RSET_ENET0:
323 return BCM_6345_ENET0_BASE;
324 case RSET_ENET1:
325 return BCM_6345_ENET1_BASE;
326 case RSET_ENETDMA:
327 return BCM_6345_ENETDMA_BASE;
328 case RSET_EHCI0:
329 return BCM_6345_EHCI0_BASE;
330 case RSET_SDRAM:
331 return BCM_6345_SDRAM_BASE;
332 case RSET_MEMC:
333 return BCM_6345_MEMC_BASE;
334 case RSET_DDR:
335 return BCM_6345_DDR_BASE;
336 }
337#endif 461#endif
338#ifdef CONFIG_BCM63XX_CPU_6348 462#ifdef CONFIG_BCM63XX_CPU_6348
339 switch (set) { 463 __GEN_RSET(6348)
340 case RSET_DSL_LMEM:
341 return BCM_6348_DSL_LMEM_BASE;
342 case RSET_PERF:
343 return BCM_6348_PERF_BASE;
344 case RSET_TIMER:
345 return BCM_6348_TIMER_BASE;
346 case RSET_WDT:
347 return BCM_6348_WDT_BASE;
348 case RSET_UART0:
349 return BCM_6348_UART0_BASE;
350 case RSET_UART1:
351 return BCM_6348_UART1_BASE;
352 case RSET_GPIO:
353 return BCM_6348_GPIO_BASE;
354 case RSET_SPI:
355 return BCM_6348_SPI_BASE;
356 case RSET_UDC0:
357 return BCM_6348_UDC0_BASE;
358 case RSET_OHCI0:
359 return BCM_6348_OHCI0_BASE;
360 case RSET_OHCI_PRIV:
361 return BCM_6348_OHCI_PRIV_BASE;
362 case RSET_USBH_PRIV:
363 return BCM_6348_USBH_PRIV_BASE;
364 case RSET_MPI:
365 return BCM_6348_MPI_BASE;
366 case RSET_PCMCIA:
367 return BCM_6348_PCMCIA_BASE;
368 case RSET_DSL:
369 return BCM_6348_DSL_BASE;
370 case RSET_ENET0:
371 return BCM_6348_ENET0_BASE;
372 case RSET_ENET1:
373 return BCM_6348_ENET1_BASE;
374 case RSET_ENETDMA:
375 return BCM_6348_ENETDMA_BASE;
376 case RSET_EHCI0:
377 return BCM_6348_EHCI0_BASE;
378 case RSET_SDRAM:
379 return BCM_6348_SDRAM_BASE;
380 case RSET_MEMC:
381 return BCM_6348_MEMC_BASE;
382 case RSET_DDR:
383 return BCM_6348_DDR_BASE;
384 }
385#endif 464#endif
386#ifdef CONFIG_BCM63XX_CPU_6358 465#ifdef CONFIG_BCM63XX_CPU_6358
387 switch (set) { 466 __GEN_RSET(6358)
388 case RSET_DSL_LMEM: 467#endif
389 return BCM_6358_DSL_LMEM_BASE; 468#ifdef CONFIG_BCM63XX_CPU_6368
390 case RSET_PERF: 469 __GEN_RSET(6368)
391 return BCM_6358_PERF_BASE;
392 case RSET_TIMER:
393 return BCM_6358_TIMER_BASE;
394 case RSET_WDT:
395 return BCM_6358_WDT_BASE;
396 case RSET_UART0:
397 return BCM_6358_UART0_BASE;
398 case RSET_UART1:
399 return BCM_6358_UART1_BASE;
400 case RSET_GPIO:
401 return BCM_6358_GPIO_BASE;
402 case RSET_SPI:
403 return BCM_6358_SPI_BASE;
404 case RSET_UDC0:
405 return BCM_6358_UDC0_BASE;
406 case RSET_OHCI0:
407 return BCM_6358_OHCI0_BASE;
408 case RSET_OHCI_PRIV:
409 return BCM_6358_OHCI_PRIV_BASE;
410 case RSET_USBH_PRIV:
411 return BCM_6358_USBH_PRIV_BASE;
412 case RSET_MPI:
413 return BCM_6358_MPI_BASE;
414 case RSET_PCMCIA:
415 return BCM_6358_PCMCIA_BASE;
416 case RSET_ENET0:
417 return BCM_6358_ENET0_BASE;
418 case RSET_ENET1:
419 return BCM_6358_ENET1_BASE;
420 case RSET_ENETDMA:
421 return BCM_6358_ENETDMA_BASE;
422 case RSET_DSL:
423 return BCM_6358_DSL_BASE;
424 case RSET_EHCI0:
425 return BCM_6358_EHCI0_BASE;
426 case RSET_SDRAM:
427 return BCM_6358_SDRAM_BASE;
428 case RSET_MEMC:
429 return BCM_6358_MEMC_BASE;
430 case RSET_DDR:
431 return BCM_6358_DDR_BASE;
432 }
433#endif 470#endif
434#endif 471#endif
435 /* unreached */ 472 /* unreached */
@@ -449,75 +486,114 @@ enum bcm63xx_irq {
449 IRQ_ENET_PHY, 486 IRQ_ENET_PHY,
450 IRQ_OHCI0, 487 IRQ_OHCI0,
451 IRQ_EHCI0, 488 IRQ_EHCI0,
452 IRQ_PCMCIA0,
453 IRQ_ENET0_RXDMA, 489 IRQ_ENET0_RXDMA,
454 IRQ_ENET0_TXDMA, 490 IRQ_ENET0_TXDMA,
455 IRQ_ENET1_RXDMA, 491 IRQ_ENET1_RXDMA,
456 IRQ_ENET1_TXDMA, 492 IRQ_ENET1_TXDMA,
457 IRQ_PCI, 493 IRQ_PCI,
458 IRQ_PCMCIA, 494 IRQ_PCMCIA,
495 IRQ_ATM,
496 IRQ_ENETSW_RXDMA0,
497 IRQ_ENETSW_RXDMA1,
498 IRQ_ENETSW_RXDMA2,
499 IRQ_ENETSW_RXDMA3,
500 IRQ_ENETSW_TXDMA0,
501 IRQ_ENETSW_TXDMA1,
502 IRQ_ENETSW_TXDMA2,
503 IRQ_ENETSW_TXDMA3,
504 IRQ_XTM,
505 IRQ_XTM_DMA0,
459}; 506};
460 507
461/* 508/*
462 * 6338 irqs 509 * 6338 irqs
463 */ 510 */
464#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 511#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
465#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
466#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 512#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
467#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4) 513#define BCM_6338_UART1_IRQ 0
468#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 514#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
469#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
470#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
471#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 515#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
516#define BCM_6338_ENET1_IRQ 0
472#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 517#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
473#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10) 518#define BCM_6338_OHCI0_IRQ 0
474#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11) 519#define BCM_6338_EHCI0_IRQ 0
475#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
476#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
477#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
478#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 520#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
479#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 521#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
480#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) 522#define BCM_6338_ENET1_RXDMA_IRQ 0
523#define BCM_6338_ENET1_TXDMA_IRQ 0
524#define BCM_6338_PCI_IRQ 0
525#define BCM_6338_PCMCIA_IRQ 0
526#define BCM_6338_ATM_IRQ 0
527#define BCM_6338_ENETSW_RXDMA0_IRQ 0
528#define BCM_6338_ENETSW_RXDMA1_IRQ 0
529#define BCM_6338_ENETSW_RXDMA2_IRQ 0
530#define BCM_6338_ENETSW_RXDMA3_IRQ 0
531#define BCM_6338_ENETSW_TXDMA0_IRQ 0
532#define BCM_6338_ENETSW_TXDMA1_IRQ 0
533#define BCM_6338_ENETSW_TXDMA2_IRQ 0
534#define BCM_6338_ENETSW_TXDMA3_IRQ 0
535#define BCM_6338_XTM_IRQ 0
536#define BCM_6338_XTM_DMA0_IRQ 0
481 537
482/* 538/*
483 * 6345 irqs 539 * 6345 irqs
484 */ 540 */
485#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 541#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
486#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 542#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
543#define BCM_6345_UART1_IRQ 0
487#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 544#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
488#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
489#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
490#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 545#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
546#define BCM_6345_ENET1_IRQ 0
491#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 547#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
548#define BCM_6345_OHCI0_IRQ 0
549#define BCM_6345_EHCI0_IRQ 0
492#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 550#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
493#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 551#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
494#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5) 552#define BCM_6345_ENET1_RXDMA_IRQ 0
495#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6) 553#define BCM_6345_ENET1_TXDMA_IRQ 0
496#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9) 554#define BCM_6345_PCI_IRQ 0
497#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10) 555#define BCM_6345_PCMCIA_IRQ 0
498#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13) 556#define BCM_6345_ATM_IRQ 0
499#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14) 557#define BCM_6345_ENETSW_RXDMA0_IRQ 0
500#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15) 558#define BCM_6345_ENETSW_RXDMA1_IRQ 0
501#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16) 559#define BCM_6345_ENETSW_RXDMA2_IRQ 0
502#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17) 560#define BCM_6345_ENETSW_RXDMA3_IRQ 0
503#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18) 561#define BCM_6345_ENETSW_TXDMA0_IRQ 0
562#define BCM_6345_ENETSW_TXDMA1_IRQ 0
563#define BCM_6345_ENETSW_TXDMA2_IRQ 0
564#define BCM_6345_ENETSW_TXDMA3_IRQ 0
565#define BCM_6345_XTM_IRQ 0
566#define BCM_6345_XTM_DMA0_IRQ 0
504 567
505/* 568/*
506 * 6348 irqs 569 * 6348 irqs
507 */ 570 */
508#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 571#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
509#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 572#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
573#define BCM_6348_UART1_IRQ 0
510#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 574#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
511#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
512#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 575#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
576#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
513#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 577#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
514#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 578#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
579#define BCM_6348_EHCI0_IRQ 0
515#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 580#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
516#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 581#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
517#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 582#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
518#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 583#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
519#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
520#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 584#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
585#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
586#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5)
587#define BCM_6348_ENETSW_RXDMA0_IRQ 0
588#define BCM_6348_ENETSW_RXDMA1_IRQ 0
589#define BCM_6348_ENETSW_RXDMA2_IRQ 0
590#define BCM_6348_ENETSW_RXDMA3_IRQ 0
591#define BCM_6348_ENETSW_TXDMA0_IRQ 0
592#define BCM_6348_ENETSW_TXDMA1_IRQ 0
593#define BCM_6348_ENETSW_TXDMA2_IRQ 0
594#define BCM_6348_ENETSW_TXDMA3_IRQ 0
595#define BCM_6348_XTM_IRQ 0
596#define BCM_6348_XTM_DMA0_IRQ 0
521 597
522/* 598/*
523 * 6358 irqs 599 * 6358 irqs
@@ -525,21 +601,108 @@ enum bcm63xx_irq {
525#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 601#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
526#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 602#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
527#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 603#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
528#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 604#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
529#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
530#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 605#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
606#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
531#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 607#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
608#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
532#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 609#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
533#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 610#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
534#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 611#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
535#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 612#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
536#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 613#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
537#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
538#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 614#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
539#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 615#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
616#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
617#define BCM_6358_ENETSW_RXDMA0_IRQ 0
618#define BCM_6358_ENETSW_RXDMA1_IRQ 0
619#define BCM_6358_ENETSW_RXDMA2_IRQ 0
620#define BCM_6358_ENETSW_RXDMA3_IRQ 0
621#define BCM_6358_ENETSW_TXDMA0_IRQ 0
622#define BCM_6358_ENETSW_TXDMA1_IRQ 0
623#define BCM_6358_ENETSW_TXDMA2_IRQ 0
624#define BCM_6358_ENETSW_TXDMA3_IRQ 0
625#define BCM_6358_XTM_IRQ 0
626#define BCM_6358_XTM_DMA0_IRQ 0
627
628#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
629#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
630#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
631#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
632#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
633#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
634
635/*
636 * 6368 irqs
637 */
638#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
639
640#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
641#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
642#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
643#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
644#define BCM_6368_ENET0_IRQ 0
645#define BCM_6368_ENET1_IRQ 0
646#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
647#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
648#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
649#define BCM_6368_PCMCIA_IRQ 0
650#define BCM_6368_ENET0_RXDMA_IRQ 0
651#define BCM_6368_ENET0_TXDMA_IRQ 0
652#define BCM_6368_ENET1_RXDMA_IRQ 0
653#define BCM_6368_ENET1_TXDMA_IRQ 0
654#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
655#define BCM_6368_ATM_IRQ 0
656#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
657#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
658#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
659#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
660#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
661#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
662#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
663#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
664#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
665#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
666
667#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
668#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
669#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
670#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
671#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
672#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
673#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
674#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
540 675
541extern const int *bcm63xx_irqs; 676extern const int *bcm63xx_irqs;
542 677
678#define __GEN_CPU_IRQ_TABLE(__cpu) \
679 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
680 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
681 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
682 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
683 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
684 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
685 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
686 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
687 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
688 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
689 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
690 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
691 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
692 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
693 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
694 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \
695 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \
696 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \
697 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \
698 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \
699 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \
700 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \
701 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \
702 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \
703 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \
704 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \
705
543static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 706static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
544{ 707{
545 return bcm63xx_irqs[irq]; 708 return bcm63xx_irqs[irq];
@@ -550,4 +713,8 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
550 */ 713 */
551unsigned int bcm63xx_get_memory_size(void); 714unsigned int bcm63xx_get_memory_size(void);
552 715
716void bcm63xx_machine_halt(void);
717
718void bcm63xx_machine_reboot(void);
719
553#endif /* !BCM63XX_CPU_H_ */ 720#endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 3999ec0aa7f5..3d5de96d4036 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
14 return 8; 14 return 8;
15 case BCM6345_CPU_ID: 15 case BCM6345_CPU_ID:
16 return 16; 16 return 16;
17 case BCM6368_CPU_ID:
18 return 38;
17 case BCM6348_CPU_ID: 19 case BCM6348_CPU_ID:
18 default: 20 default:
19 return 37; 21 return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 91180fac6ed9..72477a6441dd 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -49,9 +49,11 @@
49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a)) 49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a))
50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a)) 50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a))
51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a)) 51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a))
52#define bcm_readq(a) (*(volatile u64 *) BCM_REGS_VA(a))
52#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v)) 53#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
53#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v)) 54#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
54#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v)) 55#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
56#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
55 57
56/* 58/*
57 * IO helpers to access register set for current CPU 59 * IO helpers to access register set for current CPU
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
index 5f95577c8213..0c3074b871b8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -3,13 +3,11 @@
3 3
4#include <bcm63xx_cpu.h> 4#include <bcm63xx_cpu.h>
5 5
6#define IRQ_MIPS_BASE 0
7#define IRQ_INTERNAL_BASE 8 6#define IRQ_INTERNAL_BASE 8
8 7#define IRQ_EXTERNAL_BASE 100
9#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3) 8#define IRQ_EXT_0 (IRQ_EXTERNAL_BASE + 0)
10#define IRQ_EXT_0 (IRQ_EXT_BASE + 0) 9#define IRQ_EXT_1 (IRQ_EXTERNAL_BASE + 1)
11#define IRQ_EXT_1 (IRQ_EXT_BASE + 1) 10#define IRQ_EXT_2 (IRQ_EXTERNAL_BASE + 2)
12#define IRQ_EXT_2 (IRQ_EXT_BASE + 2) 11#define IRQ_EXT_3 (IRQ_EXTERNAL_BASE + 3)
13#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
14 12
15#endif /* ! BCM63XX_IRQ_H_ */ 13#endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 0ed5230243c9..94d4faad29a1 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -83,30 +83,86 @@
83 CKCTL_6358_USBSU_EN | \ 83 CKCTL_6358_USBSU_EN | \
84 CKCTL_6358_EPHY_EN) 84 CKCTL_6358_EPHY_EN)
85 85
86#define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
87#define CKCTL_6368_VDSL_AFE_EN (1 << 3)
88#define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
89#define CKCTL_6368_VDSL_EN (1 << 5)
90#define CKCTL_6368_PHYMIPS_EN (1 << 6)
91#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
92#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
93#define CKCTL_6368_SPI_CLK_EN (1 << 9)
94#define CKCTL_6368_USBD_CLK_EN (1 << 10)
95#define CKCTL_6368_SAR_CLK_EN (1 << 11)
96#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12)
97#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13)
98#define CKCTL_6368_PCM_CLK_EN (1 << 14)
99#define CKCTL_6368_USBH_CLK_EN (1 << 15)
100#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
101#define CKCTL_6368_NAND_CLK_EN (1 << 17)
102#define CKCTL_6368_IPSEC_CLK_EN (1 << 17)
103
104#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
105 CKCTL_6368_SWPKT_SAR_EN | \
106 CKCTL_6368_SPI_CLK_EN | \
107 CKCTL_6368_USBD_CLK_EN | \
108 CKCTL_6368_SAR_CLK_EN | \
109 CKCTL_6368_ROBOSW_CLK_EN | \
110 CKCTL_6368_UTOPIA_CLK_EN | \
111 CKCTL_6368_PCM_CLK_EN | \
112 CKCTL_6368_USBH_CLK_EN | \
113 CKCTL_6368_DISABLE_GLESS_EN | \
114 CKCTL_6368_NAND_CLK_EN | \
115 CKCTL_6368_IPSEC_CLK_EN)
116
86/* System PLL Control register */ 117/* System PLL Control register */
87#define PERF_SYS_PLL_CTL_REG 0x8 118#define PERF_SYS_PLL_CTL_REG 0x8
88#define SYS_PLL_SOFT_RESET 0x1 119#define SYS_PLL_SOFT_RESET 0x1
89 120
90/* Interrupt Mask register */ 121/* Interrupt Mask register */
91#define PERF_IRQMASK_REG 0xc 122#define PERF_IRQMASK_6338_REG 0xc
123#define PERF_IRQMASK_6345_REG 0xc
124#define PERF_IRQMASK_6348_REG 0xc
125#define PERF_IRQMASK_6358_REG 0xc
126#define PERF_IRQMASK_6368_REG 0x20
92 127
93/* Interrupt Status register */ 128/* Interrupt Status register */
94#define PERF_IRQSTAT_REG 0x10 129#define PERF_IRQSTAT_6338_REG 0x10
130#define PERF_IRQSTAT_6345_REG 0x10
131#define PERF_IRQSTAT_6348_REG 0x10
132#define PERF_IRQSTAT_6358_REG 0x10
133#define PERF_IRQSTAT_6368_REG 0x28
95 134
96/* External Interrupt Configuration register */ 135/* External Interrupt Configuration register */
97#define PERF_EXTIRQ_CFG_REG 0x14 136#define PERF_EXTIRQ_CFG_REG_6338 0x14
137#define PERF_EXTIRQ_CFG_REG_6348 0x14
138#define PERF_EXTIRQ_CFG_REG_6358 0x14
139#define PERF_EXTIRQ_CFG_REG_6368 0x18
140
141#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
142
143/* for 6348 only */
144#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
145#define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
146#define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
147#define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
148#define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
149#define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
150#define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
151#define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
152
153/* for all others */
98#define EXTIRQ_CFG_SENSE(x) (1 << (x)) 154#define EXTIRQ_CFG_SENSE(x) (1 << (x))
99#define EXTIRQ_CFG_STAT(x) (1 << (x + 5)) 155#define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
100#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10)) 156#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
101#define EXTIRQ_CFG_MASK(x) (1 << (x + 15)) 157#define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
102#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20)) 158#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
103#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25)) 159#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
104 160#define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
105#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10) 161#define EXTIRQ_CFG_MASK_ALL (0xf << 12)
106#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
107 162
108/* Soft Reset register */ 163/* Soft Reset register */
109#define PERF_SOFTRESET_REG 0x28 164#define PERF_SOFTRESET_REG 0x28
165#define PERF_SOFTRESET_6368_REG 0x10
110 166
111#define SOFTRESET_6338_SPI_MASK (1 << 0) 167#define SOFTRESET_6338_SPI_MASK (1 << 0)
112#define SOFTRESET_6338_ENET_MASK (1 << 2) 168#define SOFTRESET_6338_ENET_MASK (1 << 2)
@@ -147,6 +203,15 @@
147 SOFTRESET_6348_ACLC_MASK | \ 203 SOFTRESET_6348_ACLC_MASK | \
148 SOFTRESET_6348_ADSLMIPSPLL_MASK) 204 SOFTRESET_6348_ADSLMIPSPLL_MASK)
149 205
206#define SOFTRESET_6368_SPI_MASK (1 << 0)
207#define SOFTRESET_6368_MPI_MASK (1 << 3)
208#define SOFTRESET_6368_EPHY_MASK (1 << 6)
209#define SOFTRESET_6368_SAR_MASK (1 << 7)
210#define SOFTRESET_6368_ENETSW_MASK (1 << 10)
211#define SOFTRESET_6368_USBS_MASK (1 << 11)
212#define SOFTRESET_6368_USBH_MASK (1 << 12)
213#define SOFTRESET_6368_PCM_MASK (1 << 13)
214
150/* MIPS PLL control register */ 215/* MIPS PLL control register */
151#define PERF_MIPSPLLCTL_REG 0x34 216#define PERF_MIPSPLLCTL_REG 0x34
152#define MIPSPLLCTL_N1_SHIFT 20 217#define MIPSPLLCTL_N1_SHIFT 20
@@ -372,6 +437,7 @@
372#define GPIO_CTL_LO_REG 0x4 437#define GPIO_CTL_LO_REG 0x4
373#define GPIO_DATA_HI_REG 0x8 438#define GPIO_DATA_HI_REG 0x8
374#define GPIO_DATA_LO_REG 0xC 439#define GPIO_DATA_LO_REG 0xC
440#define GPIO_DATA_LO_REG_6345 0x8
375 441
376/* GPIO mux registers and constants */ 442/* GPIO mux registers and constants */
377#define GPIO_MODE_REG 0x18 443#define GPIO_MODE_REG 0x18
@@ -402,6 +468,44 @@
402#define GPIO_MODE_6358_SERIAL_LED (1 << 10) 468#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
403#define GPIO_MODE_6358_UTOPIA (1 << 12) 469#define GPIO_MODE_6358_UTOPIA (1 << 12)
404 470
471#define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
472#define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
473#define GPIO_MODE_6368_SYS_IRQ (1 << 2)
474#define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
475#define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
476#define GPIO_MODE_6368_INET_LED (1 << 5)
477#define GPIO_MODE_6368_EPHY0_LED (1 << 6)
478#define GPIO_MODE_6368_EPHY1_LED (1 << 7)
479#define GPIO_MODE_6368_EPHY2_LED (1 << 8)
480#define GPIO_MODE_6368_EPHY3_LED (1 << 9)
481#define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
482#define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
483#define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
484#define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
485#define GPIO_MODE_6368_USBD_LED (1 << 14)
486#define GPIO_MODE_6368_NTR_PULSE (1 << 15)
487#define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
488#define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
489#define GPIO_MODE_6368_PCI_INTB (1 << 18)
490#define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
491#define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
492#define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
493#define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
494#define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
495#define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
496#define GPIO_MODE_6368_EBI_CS2 (1 << 26)
497#define GPIO_MODE_6368_EBI_CS3 (1 << 27)
498#define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
499#define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
500#define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
501#define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
502
503
504#define GPIO_BASEMODE_6368_REG 0x38
505#define GPIO_BASEMODE_6368_UART2 0x1
506#define GPIO_BASEMODE_6368_GPIO 0x0
507#define GPIO_BASEMODE_6368_MASK 0x7
508/* those bits must be kept as read in gpio basemode register*/
405 509
406/************************************************************************* 510/*************************************************************************
407 * _REG relative to RSET_ENET 511 * _REG relative to RSET_ENET
@@ -548,6 +652,56 @@
548 652
549 653
550/************************************************************************* 654/*************************************************************************
655 * _REG relative to RSET_ENETDMAC
656 *************************************************************************/
657
658/* Channel Configuration register */
659#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
660#define ENETDMAC_CHANCFG_EN_SHIFT 0
661#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
662#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
663#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
664
665/* Interrupt Control/Status register */
666#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
667#define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
668#define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
669#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
670
671/* Interrupt Mask register */
672#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
673
674/* Maximum Burst Length */
675#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
676
677
678/*************************************************************************
679 * _REG relative to RSET_ENETDMAS
680 *************************************************************************/
681
682/* Ring Start Address register */
683#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
684
685/* State Ram Word 2 */
686#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
687
688/* State Ram Word 3 */
689#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
690
691/* State Ram Word 4 */
692#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
693
694
695/*************************************************************************
696 * _REG relative to RSET_ENETSW
697 *************************************************************************/
698
699/* MIB register */
700#define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
701#define ENETSW_MIB_REG_COUNT 47
702
703
704/*************************************************************************
551 * _REG relative to RSET_OHCI_PRIV 705 * _REG relative to RSET_OHCI_PRIV
552 *************************************************************************/ 706 *************************************************************************/
553 707
@@ -562,7 +716,9 @@
562 * _REG relative to RSET_USBH_PRIV 716 * _REG relative to RSET_USBH_PRIV
563 *************************************************************************/ 717 *************************************************************************/
564 718
565#define USBH_PRIV_SWAP_REG 0x0 719#define USBH_PRIV_SWAP_6358_REG 0x0
720#define USBH_PRIV_SWAP_6368_REG 0x1c
721
566#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 722#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
567#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) 723#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
568#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 724#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
@@ -572,7 +728,13 @@
572#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 728#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
573#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) 729#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
574 730
575#define USBH_PRIV_TEST_REG 0x24 731#define USBH_PRIV_TEST_6358_REG 0x24
732#define USBH_PRIV_TEST_6368_REG 0x14
733
734#define USBH_PRIV_SETUP_6368_REG 0x28
735#define USBH_PRIV_SETUP_IOC_SHIFT 4
736#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
737
576 738
577 739
578/************************************************************************* 740/*************************************************************************
@@ -734,6 +896,8 @@
734#define SDRAM_CFG_BANK_SHIFT 13 896#define SDRAM_CFG_BANK_SHIFT 13
735#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) 897#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
736 898
899#define SDRAM_MBASE_REG 0xc
900
737#define SDRAM_PRIO_REG 0x2C 901#define SDRAM_PRIO_REG 0x2C
738#define SDRAM_PRIO_MIPS_SHIFT 29 902#define SDRAM_PRIO_MIPS_SHIFT 29
739#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) 903#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
@@ -768,4 +932,45 @@
768#define DMIPSPLLCFG_N2_SHIFT 29 932#define DMIPSPLLCFG_N2_SHIFT 29
769#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 933#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
770 934
935#define DDR_DMIPSPLLCFG_6368_REG 0x20
936#define DMIPSPLLCFG_6368_P1_SHIFT 0
937#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
938#define DMIPSPLLCFG_6368_P2_SHIFT 4
939#define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
940#define DMIPSPLLCFG_6368_NDIV_SHIFT 16
941#define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
942
943#define DDR_DMIPSPLLDIV_6368_REG 0x24
944#define DMIPSPLLDIV_6368_MDIV_SHIFT 0
945#define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
946
947
948/*************************************************************************
949 * _REG relative to RSET_M2M
950 *************************************************************************/
951
952#define M2M_RX 0
953#define M2M_TX 1
954
955#define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
956#define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
957#define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
958
959#define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
960#define M2M_CTRL_ENABLE_MASK (1 << 0)
961#define M2M_CTRL_IRQEN_MASK (1 << 1)
962#define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
963#define M2M_CTRL_DONE_CLR_MASK (1 << 7)
964#define M2M_CTRL_NOINC_MASK (1 << 8)
965#define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
966#define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
967#define M2M_CTRL_ENDIAN_MASK (1 << 11)
968
969#define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
970#define M2M_STAT_DONE (1 << 0)
971#define M2M_STAT_ERROR (1 << 1)
972
973#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
974#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
975
771#endif /* BCM63XX_REGS_H_ */ 976#endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
new file mode 100644
index 000000000000..ef94ba73646e
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -0,0 +1,42 @@
1#ifndef BCM63XX_IOREMAP_H_
2#define BCM63XX_IOREMAP_H_
3
4#include <bcm63xx_cpu.h>
5
6static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
7{
8 return phys_addr;
9}
10
11static inline int is_bcm63xx_internal_registers(phys_t offset)
12{
13 switch (bcm63xx_get_cpu_id()) {
14 case BCM6338_CPU_ID:
15 case BCM6345_CPU_ID:
16 case BCM6348_CPU_ID:
17 case BCM6358_CPU_ID:
18 if (offset >= 0xfff00000)
19 return 1;
20 break;
21 case BCM6368_CPU_ID:
22 if (offset >= 0xb0000000 && offset < 0xb1000000)
23 return 1;
24 break;
25 }
26 return 0;
27}
28
29static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
30 unsigned long flags)
31{
32 if (is_bcm63xx_internal_registers(offset))
33 return (void __iomem *)offset;
34 return NULL;
35}
36
37static inline int plat_iounmap(const volatile void __iomem *addr)
38{
39 return is_bcm63xx_internal_registers((unsigned long)addr);
40}
41
42#endif /* BCM63XX_IOREMAP_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h
new file mode 100644
index 000000000000..9332e788a5c9
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/irq.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_BCM63XX_IRQ_H
2#define __ASM_MACH_BCM63XX_IRQ_H
3
4#define NR_IRQS 128
5#define MIPS_CPU_IRQ_BASE 0
6
7#endif
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3b728275b9b0..d193fb68cf27 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -24,24 +24,33 @@
24 24
25#define cpu_has_llsc 1 25#define cpu_has_llsc 1
26#define cpu_has_vtag_icache 0 26#define cpu_has_vtag_icache 0
27#define cpu_has_dc_aliases 0 27#define cpu_has_ic_fills_f_dc 1
28#define cpu_has_ic_fills_f_dc 0
29#define cpu_has_dsp 0 28#define cpu_has_dsp 0
30#define cpu_has_mipsmt 0 29#define cpu_has_mipsmt 0
31#define cpu_has_userlocal 0 30#define cpu_icache_snoops_remote_store 1
32#define cpu_icache_snoops_remote_store 0
33 31
34#define cpu_has_nofpuex 0
35#define cpu_has_64bits 1 32#define cpu_has_64bits 1
36 33
37#define cpu_has_mips32r1 1 34#define cpu_has_mips32r1 1
38#define cpu_has_mips32r2 0
39#define cpu_has_mips64r1 1 35#define cpu_has_mips64r1 1
40#define cpu_has_mips64r2 0
41 36
42#define cpu_has_inclusive_pcaches 0 37#define cpu_has_inclusive_pcaches 0
43 38
44#define cpu_dcache_line_size() 32 39#define cpu_dcache_line_size() 32
45#define cpu_icache_line_size() 32 40#define cpu_icache_line_size() 32
46 41
42#if defined(CONFIG_CPU_XLR)
43#define cpu_has_userlocal 0
44#define cpu_has_dc_aliases 0
45#define cpu_has_mips32r2 0
46#define cpu_has_mips64r2 0
47#elif defined(CONFIG_CPU_XLP)
48#define cpu_has_userlocal 1
49#define cpu_has_mips32r2 1
50#define cpu_has_mips64r2 1
51#define cpu_has_dc_aliases 1
52#else
53#error "Unknown Netlogic CPU"
54#endif
55
47#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */ 56#endif /* __ASM_MACH_NETLOGIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 2ea7b817feb8..7f87d824eeb0 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1106,7 +1106,7 @@ do { \
1106#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1106#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1107#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1107#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1108 1108
1109/* BMIPS4380 */ 1109/* BMIPS43xx */
1110#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1110#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1111#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1111#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1112 1112
@@ -1667,6 +1667,13 @@ __BUILD_SET_C0(config)
1667__BUILD_SET_C0(intcontrol) 1667__BUILD_SET_C0(intcontrol)
1668__BUILD_SET_C0(intctl) 1668__BUILD_SET_C0(intctl)
1669__BUILD_SET_C0(srsmap) 1669__BUILD_SET_C0(srsmap)
1670__BUILD_SET_C0(brcm_config_0)
1671__BUILD_SET_C0(brcm_bus_pll)
1672__BUILD_SET_C0(brcm_reset)
1673__BUILD_SET_C0(brcm_cmt_intr)
1674__BUILD_SET_C0(brcm_cmt_ctrl)
1675__BUILD_SET_C0(brcm_config)
1676__BUILD_SET_C0(brcm_mode)
1670 1677
1671#endif /* !__ASSEMBLY__ */ 1678#endif /* !__ASSEMBLY__ */
1672 1679
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index bc01a02cacd8..7467d1d933d5 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -74,7 +74,9 @@ search_module_dbetables(unsigned long addr)
74} 74}
75#endif 75#endif
76 76
77#ifdef CONFIG_CPU_MIPS32_R1 77#ifdef CONFIG_CPU_BMIPS
78#define MODULE_PROC_FAMILY "BMIPS "
79#elif defined CONFIG_CPU_MIPS32_R1
78#define MODULE_PROC_FAMILY "MIPS32_R1 " 80#define MODULE_PROC_FAMILY "MIPS32_R1 "
79#elif defined CONFIG_CPU_MIPS32_R2 81#elif defined CONFIG_CPU_MIPS32_R2
80#define MODULE_PROC_FAMILY "MIPS32_R2 " 82#define MODULE_PROC_FAMILY "MIPS32_R2 "
@@ -120,6 +122,8 @@ search_module_dbetables(unsigned long addr)
120#define MODULE_PROC_FAMILY "OCTEON " 122#define MODULE_PROC_FAMILY "OCTEON "
121#elif defined CONFIG_CPU_XLR 123#elif defined CONFIG_CPU_XLR
122#define MODULE_PROC_FAMILY "XLR " 124#define MODULE_PROC_FAMILY "XLR "
125#elif defined CONFIG_CPU_XLP
126#define MODULE_PROC_FAMILY "XLP "
123#else 127#else
124#error MODULE_PROC_FAMILY undefined for your processor configuration 128#error MODULE_PROC_FAMILY undefined for your processor configuration
125#endif 129#endif
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
new file mode 100644
index 000000000000..fdd2f44c7b59
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -0,0 +1,76 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NETLOGIC_COMMON_H_
36#define _NETLOGIC_COMMON_H_
37
38/*
39 * Common SMP definitions
40 */
41#define RESET_VEC_PHYS 0x1fc00000
42#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
43#define BOOT_THREAD_MODE 0
44#define BOOT_NMI_LOCK 4
45#define BOOT_NMI_HANDLER 8
46
47#ifndef __ASSEMBLY__
48struct irq_desc;
49extern struct plat_smp_ops nlm_smp_ops;
50extern char nlm_reset_entry[], nlm_reset_entry_end[];
51void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
52void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
53void nlm_smp_irq_init(void);
54void nlm_boot_secondary_cpus(void);
55int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
56void nlm_rmiboot_preboot(void);
57
58static inline void
59nlm_set_nmi_handler(void *handler)
60{
61 char *reset_data;
62
63 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
64 *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
65}
66
67/*
68 * Misc.
69 */
70unsigned int nlm_get_cpu_frequency(void);
71
72extern unsigned long nlm_common_ebase;
73extern int nlm_threads_per_core;
74extern uint32_t nlm_cpumask, nlm_coremask;
75#endif
76#endif /* _NETLOGIC_COMMON_H_ */
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
new file mode 100644
index 000000000000..72a0c788b472
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/haldefs.h
@@ -0,0 +1,163 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_HALDEFS_H__
36#define __NLM_HAL_HALDEFS_H__
37
38/*
39 * This file contains platform specific memory mapped IO implementation
40 * and will provide a way to read 32/64 bit memory mapped registers in
41 * all ABIs
42 */
43#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
44#error "o32 compile not supported on XLP yet"
45#endif
46/*
47 * For o32 compilation, we have to disable interrupts and enable KX bit to
48 * access 64 bit addresses or data.
49 *
50 * We need to disable interrupts because we save just the lower 32 bits of
51 * registers in interrupt handling. So if we get hit by an interrupt while
52 * using the upper 32 bits of a register, we lose.
53 */
54static inline uint32_t nlm_save_flags_kx(void)
55{
56 return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
57}
58
59static inline uint32_t nlm_save_flags_cop2(void)
60{
61 return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
62}
63
64static inline void nlm_restore_flags(uint32_t sr)
65{
66 write_c0_status(sr);
67}
68
69/*
70 * The n64 implementations are simple, the o32 implementations when they
71 * are added, will have to disable interrupts and enable KX before doing
72 * 64 bit ops.
73 */
74static inline uint32_t
75nlm_read_reg(uint64_t base, uint32_t reg)
76{
77 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
78
79 return *addr;
80}
81
82static inline void
83nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
84{
85 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
86
87 *addr = val;
88}
89
90static inline uint64_t
91nlm_read_reg64(uint64_t base, uint32_t reg)
92{
93 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
94 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
95
96 return *ptr;
97}
98
99static inline void
100nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
101{
102 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
103 volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
104
105 *ptr = val;
106}
107
108/*
109 * Routines to store 32/64 bit values to 64 bit addresses,
110 * used when going thru XKPHYS to access registers
111 */
112static inline uint32_t
113nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
114{
115 return nlm_read_reg(base, reg);
116}
117
118static inline void
119nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
120{
121 nlm_write_reg(base, reg, val);
122}
123
124static inline uint64_t
125nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
126{
127 return nlm_read_reg64(base, reg);
128}
129
130static inline void
131nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
132{
133 nlm_write_reg64(base, reg, val);
134}
135
136/* Location where IO base is mapped */
137extern uint64_t nlm_io_base;
138
139#if defined(CONFIG_CPU_XLP)
140static inline uint64_t
141nlm_pcicfg_base(uint32_t devoffset)
142{
143 return nlm_io_base + devoffset;
144}
145
146static inline uint64_t
147nlm_xkphys_map_pcibar0(uint64_t pcibase)
148{
149 uint64_t paddr;
150
151 paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
152 return (uint64_t)0x9000000000000000 | paddr;
153}
154#elif defined(CONFIG_CPU_XLR)
155
156static inline uint64_t
157nlm_mmio_base(uint32_t devoffset)
158{
159 return nlm_io_base + devoffset;
160}
161#endif
162
163#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
new file mode 100644
index 000000000000..ca95133f1ad1
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -0,0 +1,187 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_BRIDGE_H__
36#define __NLM_HAL_BRIDGE_H__
37
38/**
39* @file_name mio.h
40* @author Netlogic Microsystems
41* @brief Basic definitions of XLP memory and io subsystem
42*/
43
44/*
45 * BRIDGE specific registers
46 *
47 * These registers start after the PCIe header, which has 0x40
48 * standard entries
49 */
50#define BRIDGE_MODE 0x00
51#define BRIDGE_PCI_CFG_BASE 0x01
52#define BRIDGE_PCI_CFG_LIMIT 0x02
53#define BRIDGE_PCIE_CFG_BASE 0x03
54#define BRIDGE_PCIE_CFG_LIMIT 0x04
55#define BRIDGE_BUSNUM_BAR0 0x05
56#define BRIDGE_BUSNUM_BAR1 0x06
57#define BRIDGE_BUSNUM_BAR2 0x07
58#define BRIDGE_BUSNUM_BAR3 0x08
59#define BRIDGE_BUSNUM_BAR4 0x09
60#define BRIDGE_BUSNUM_BAR5 0x0a
61#define BRIDGE_BUSNUM_BAR6 0x0b
62#define BRIDGE_FLASH_BAR0 0x0c
63#define BRIDGE_FLASH_BAR1 0x0d
64#define BRIDGE_FLASH_BAR2 0x0e
65#define BRIDGE_FLASH_BAR3 0x0f
66#define BRIDGE_FLASH_LIMIT0 0x10
67#define BRIDGE_FLASH_LIMIT1 0x11
68#define BRIDGE_FLASH_LIMIT2 0x12
69#define BRIDGE_FLASH_LIMIT3 0x13
70
71#define BRIDGE_DRAM_BAR(i) (0x14 + (i))
72#define BRIDGE_DRAM_BAR0 0x14
73#define BRIDGE_DRAM_BAR1 0x15
74#define BRIDGE_DRAM_BAR2 0x16
75#define BRIDGE_DRAM_BAR3 0x17
76#define BRIDGE_DRAM_BAR4 0x18
77#define BRIDGE_DRAM_BAR5 0x19
78#define BRIDGE_DRAM_BAR6 0x1a
79#define BRIDGE_DRAM_BAR7 0x1b
80
81#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i))
82#define BRIDGE_DRAM_LIMIT0 0x1c
83#define BRIDGE_DRAM_LIMIT1 0x1d
84#define BRIDGE_DRAM_LIMIT2 0x1e
85#define BRIDGE_DRAM_LIMIT3 0x1f
86#define BRIDGE_DRAM_LIMIT4 0x20
87#define BRIDGE_DRAM_LIMIT5 0x21
88#define BRIDGE_DRAM_LIMIT6 0x22
89#define BRIDGE_DRAM_LIMIT7 0x23
90
91#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
92#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
93#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
94#define BRIDGE_DRAM_NODE_TRANSLN3 0x27
95#define BRIDGE_DRAM_NODE_TRANSLN4 0x28
96#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
97#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
98#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
99#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
100#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
101#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
102#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f
103#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30
104#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
105#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
106#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
107#define BRIDGE_PCIEMEM_BASE0 0x34
108#define BRIDGE_PCIEMEM_BASE1 0x35
109#define BRIDGE_PCIEMEM_BASE2 0x36
110#define BRIDGE_PCIEMEM_BASE3 0x37
111#define BRIDGE_PCIEMEM_LIMIT0 0x38
112#define BRIDGE_PCIEMEM_LIMIT1 0x39
113#define BRIDGE_PCIEMEM_LIMIT2 0x3a
114#define BRIDGE_PCIEMEM_LIMIT3 0x3b
115#define BRIDGE_PCIEIO_BASE0 0x3c
116#define BRIDGE_PCIEIO_BASE1 0x3d
117#define BRIDGE_PCIEIO_BASE2 0x3e
118#define BRIDGE_PCIEIO_BASE3 0x3f
119#define BRIDGE_PCIEIO_LIMIT0 0x40
120#define BRIDGE_PCIEIO_LIMIT1 0x41
121#define BRIDGE_PCIEIO_LIMIT2 0x42
122#define BRIDGE_PCIEIO_LIMIT3 0x43
123#define BRIDGE_PCIEMEM_BASE4 0x44
124#define BRIDGE_PCIEMEM_BASE5 0x45
125#define BRIDGE_PCIEMEM_BASE6 0x46
126#define BRIDGE_PCIEMEM_LIMIT4 0x47
127#define BRIDGE_PCIEMEM_LIMIT5 0x48
128#define BRIDGE_PCIEMEM_LIMIT6 0x49
129#define BRIDGE_PCIEIO_BASE4 0x4a
130#define BRIDGE_PCIEIO_BASE5 0x4b
131#define BRIDGE_PCIEIO_BASE6 0x4c
132#define BRIDGE_PCIEIO_LIMIT4 0x4d
133#define BRIDGE_PCIEIO_LIMIT5 0x4e
134#define BRIDGE_PCIEIO_LIMIT6 0x4f
135#define BRIDGE_NBU_EVENT_CNT_CTL 0x50
136#define BRIDGE_EVNTCTR1_LOW 0x51
137#define BRIDGE_EVNTCTR1_HI 0x52
138#define BRIDGE_EVNT_CNT_CTL2 0x53
139#define BRIDGE_EVNTCTR2_LOW 0x54
140#define BRIDGE_EVNTCTR2_HI 0x55
141#define BRIDGE_TRACEBUF_MATCH0 0x56
142#define BRIDGE_TRACEBUF_MATCH1 0x57
143#define BRIDGE_TRACEBUF_MATCH_LOW 0x58
144#define BRIDGE_TRACEBUF_MATCH_HI 0x59
145#define BRIDGE_TRACEBUF_CTRL 0x5a
146#define BRIDGE_TRACEBUF_INIT 0x5b
147#define BRIDGE_TRACEBUF_ACCESS 0x5c
148#define BRIDGE_TRACEBUF_READ_DATA0 0x5d
149#define BRIDGE_TRACEBUF_READ_DATA1 0x5d
150#define BRIDGE_TRACEBUF_READ_DATA2 0x5f
151#define BRIDGE_TRACEBUF_READ_DATA3 0x60
152#define BRIDGE_TRACEBUF_STATUS 0x61
153#define BRIDGE_ADDRESS_ERROR0 0x62
154#define BRIDGE_ADDRESS_ERROR1 0x63
155#define BRIDGE_ADDRESS_ERROR2 0x64
156#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65
157#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66
158#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67
159#define BRIDGE_LINE_FLUSH0 0x68
160#define BRIDGE_LINE_FLUSH1 0x69
161#define BRIDGE_NODE_ID 0x6a
162#define BRIDGE_ERROR_INTERRUPT_EN 0x6b
163#define BRIDGE_PCIE0_WEIGHT 0x2c0
164#define BRIDGE_PCIE1_WEIGHT 0x2c1
165#define BRIDGE_PCIE2_WEIGHT 0x2c2
166#define BRIDGE_PCIE3_WEIGHT 0x2c3
167#define BRIDGE_USB_WEIGHT 0x2c4
168#define BRIDGE_NET_WEIGHT 0x2c5
169#define BRIDGE_POE_WEIGHT 0x2c6
170#define BRIDGE_CMS_WEIGHT 0x2c7
171#define BRIDGE_DMAENG_WEIGHT 0x2c8
172#define BRIDGE_SEC_WEIGHT 0x2c9
173#define BRIDGE_COMP_WEIGHT 0x2ca
174#define BRIDGE_GIO_WEIGHT 0x2cb
175#define BRIDGE_FLASH_WEIGHT 0x2cc
176
177#ifndef __ASSEMBLY__
178
179#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r)
180#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v)
181#define nlm_get_bridge_pcibase(node) \
182 nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
183#define nlm_get_bridge_regbase(node) \
184 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
185
186#endif /* __ASSEMBLY__ */
187#endif /* __NLM_HAL_BRIDGE_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
new file mode 100644
index 000000000000..bf7d41deb9be
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -0,0 +1,83 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_CPUCONTROL_H__
36#define __NLM_HAL_CPUCONTROL_H__
37
38#define CPU_BLOCKID_IFU 0
39#define CPU_BLOCKID_ICU 1
40#define CPU_BLOCKID_IEU 2
41#define CPU_BLOCKID_LSU 3
42#define CPU_BLOCKID_MMU 4
43#define CPU_BLOCKID_PRF 5
44#define CPU_BLOCKID_SCH 7
45#define CPU_BLOCKID_SCU 8
46#define CPU_BLOCKID_FPU 9
47#define CPU_BLOCKID_MAP 10
48
49#define LSU_DEFEATURE 0x304
50#define LSU_CERRLOG_REGID 0x09
51#define SCHED_DEFEATURE 0x700
52
53/* Offsets of interest from the 'MAP' Block */
54#define MAP_THREADMODE 0x00
55#define MAP_EXT_EBASE_ENABLE 0x04
56#define MAP_CCDI_CONFIG 0x08
57#define MAP_THRD0_CCDI_STATUS 0x0c
58#define MAP_THRD1_CCDI_STATUS 0x10
59#define MAP_THRD2_CCDI_STATUS 0x14
60#define MAP_THRD3_CCDI_STATUS 0x18
61#define MAP_THRD0_DEBUG_MODE 0x1c
62#define MAP_THRD1_DEBUG_MODE 0x20
63#define MAP_THRD2_DEBUG_MODE 0x24
64#define MAP_THRD3_DEBUG_MODE 0x28
65#define MAP_MISC_STATE 0x60
66#define MAP_DEBUG_READ_CTL 0x64
67#define MAP_DEBUG_READ_REG0 0x68
68#define MAP_DEBUG_READ_REG1 0x6c
69
70#define MMU_SETUP 0x400
71#define MMU_LFSRSEED 0x401
72#define MMU_HPW_NUM_PAGE_LVL 0x410
73#define MMU_PGWKR_PGDBASE 0x411
74#define MMU_PGWKR_PGDSHFT 0x412
75#define MMU_PGWKR_PGDMASK 0x413
76#define MMU_PGWKR_PUDSHFT 0x414
77#define MMU_PGWKR_PUDMASK 0x415
78#define MMU_PGWKR_PMDSHFT 0x416
79#define MMU_PGWKR_PMDMASK 0x417
80#define MMU_PGWKR_PTESHFT 0x418
81#define MMU_PGWKR_PTEMASK 0x419
82
83#endif /* __NLM_CPUCONTROL_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
new file mode 100644
index 000000000000..86cc3391e50c
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -0,0 +1,153 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_IOMAP_H__
36#define __NLM_HAL_IOMAP_H__
37
38#define XLP_DEFAULT_IO_BASE 0x18000000
39#define NMI_BASE 0xbfc00000
40#define XLP_IO_CLK 133333333
41
42#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */
43#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE)
44#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE)
45#define XLP_IO_SIZE (64 << 20) /* ECFG space size */
46#define XLP_IO_PCI_HDRSZ 0x100
47#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8)
48#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \
49 ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12))
50
51#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0)
52/* coherent inter chip */
53#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1)
54#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2)
55#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3)
56#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4)
57
58#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i)
59#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0)
60#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1)
61#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2)
62#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3)
63
64#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i)
65#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0)
66#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1)
67#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2)
68#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3)
69#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4)
70#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5)
71
72#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0)
73#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1)
74
75#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0)
76
77#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1)
78#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2)
79#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3)
80
81#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i)
82#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0)
83#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1)
84#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i)
85#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2)
86#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3)
87#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4)
88/* system management */
89#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5)
90#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6)
91
92#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0)
93#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1)
94#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2)
95/* SD flash */
96#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3)
97#define XLP_IO_MMC_OFFSET(node, slot) \
98 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
99
100/* PCI config header register id's */
101#define XLP_PCI_CFGREG0 0x00
102#define XLP_PCI_CFGREG1 0x01
103#define XLP_PCI_CFGREG2 0x02
104#define XLP_PCI_CFGREG3 0x03
105#define XLP_PCI_CFGREG4 0x04
106#define XLP_PCI_CFGREG5 0x05
107#define XLP_PCI_DEVINFO_REG0 0x30
108#define XLP_PCI_DEVINFO_REG1 0x31
109#define XLP_PCI_DEVINFO_REG2 0x32
110#define XLP_PCI_DEVINFO_REG3 0x33
111#define XLP_PCI_DEVINFO_REG4 0x34
112#define XLP_PCI_DEVINFO_REG5 0x35
113#define XLP_PCI_DEVINFO_REG6 0x36
114#define XLP_PCI_DEVINFO_REG7 0x37
115#define XLP_PCI_DEVSCRATCH_REG0 0x38
116#define XLP_PCI_DEVSCRATCH_REG1 0x39
117#define XLP_PCI_DEVSCRATCH_REG2 0x3a
118#define XLP_PCI_DEVSCRATCH_REG3 0x3b
119#define XLP_PCI_MSGSTN_REG 0x3c
120#define XLP_PCI_IRTINFO_REG 0x3d
121#define XLP_PCI_UCODEINFO_REG 0x3e
122#define XLP_PCI_SBB_WT_REG 0x3f
123
124/* PCI IDs for SoC device */
125#define PCI_VENDOR_NETLOGIC 0x184e
126
127#define PCI_DEVICE_ID_NLM_ROOT 0x1001
128#define PCI_DEVICE_ID_NLM_ICI 0x1002
129#define PCI_DEVICE_ID_NLM_PIC 0x1003
130#define PCI_DEVICE_ID_NLM_PCIE 0x1004
131#define PCI_DEVICE_ID_NLM_EHCI 0x1007
132#define PCI_DEVICE_ID_NLM_ILK 0x1008
133#define PCI_DEVICE_ID_NLM_NAE 0x1009
134#define PCI_DEVICE_ID_NLM_POE 0x100A
135#define PCI_DEVICE_ID_NLM_FMN 0x100B
136#define PCI_DEVICE_ID_NLM_RAID 0x100D
137#define PCI_DEVICE_ID_NLM_SAE 0x100D
138#define PCI_DEVICE_ID_NLM_RSA 0x100E
139#define PCI_DEVICE_ID_NLM_CMP 0x100F
140#define PCI_DEVICE_ID_NLM_UART 0x1010
141#define PCI_DEVICE_ID_NLM_I2C 0x1011
142#define PCI_DEVICE_ID_NLM_NOR 0x1015
143#define PCI_DEVICE_ID_NLM_NAND 0x1016
144#define PCI_DEVICE_ID_NLM_MMC 0x1018
145
146#ifndef __ASSEMBLY__
147
148#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r)
149#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v)
150
151#endif /* !__ASSEMBLY */
152
153#endif /* __NLM_HAL_IOMAP_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
new file mode 100644
index 000000000000..b6628f7ccf74
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -0,0 +1,411 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _NLM_HAL_PIC_H
36#define _NLM_HAL_PIC_H
37
38/* PIC Specific registers */
39#define PIC_CTRL 0x00
40
41/* PIC control register defines */
42#define PIC_CTRL_ITV 32 /* interrupt timeout value */
43#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */
44#define PIC_CTRL_ITE 18 /* interrupt timeout enable */
45#define PIC_CTRL_STE 10 /* system timer interrupt enable */
46#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
47#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
48#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
49#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
50#define PIC_CTRL_WTE 0 /* watchdog timer enable */
51
52/* PIC Status register defines */
53#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */
54#define PIC_ITE_STATUS 32 /* interrupt timeout status */
55#define PIC_STS_STATUS 4 /* System timer interrupt status */
56#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
57#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
58
59/* PIC IPI control register offsets */
60#define PIC_IPICTRL_NMI 32
61#define PIC_IPICTRL_RIV 20 /* received interrupt vector */
62#define PIC_IPICTRL_IDB 16 /* interrupt destination base */
63#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */
64
65/* PIC IRT register offsets */
66#define PIC_IRT_ENABLE 31
67#define PIC_IRT_NMI 29
68#define PIC_IRT_SCH 28 /* Scheduling scheme */
69#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
70#define PIC_IRT_DT 19 /* Destination type */
71#define PIC_IRT_DB 16 /* Destination base */
72#define PIC_IRT_DTE 0 /* Destination thread enables */
73
74#define PIC_BYTESWAP 0x02
75#define PIC_STATUS 0x04
76#define PIC_INTR_TIMEOUT 0x06
77#define PIC_ICI0_INTR_TIMEOUT 0x08
78#define PIC_ICI1_INTR_TIMEOUT 0x0a
79#define PIC_ICI2_INTR_TIMEOUT 0x0c
80#define PIC_IPI_CTL 0x0e
81#define PIC_INT_ACK 0x10
82#define PIC_INT_PENDING0 0x12
83#define PIC_INT_PENDING1 0x14
84#define PIC_INT_PENDING2 0x16
85
86#define PIC_WDOG0_MAXVAL 0x18
87#define PIC_WDOG0_COUNT 0x1a
88#define PIC_WDOG0_ENABLE0 0x1c
89#define PIC_WDOG0_ENABLE1 0x1e
90#define PIC_WDOG0_BEATCMD 0x20
91#define PIC_WDOG0_BEAT0 0x22
92#define PIC_WDOG0_BEAT1 0x24
93
94#define PIC_WDOG1_MAXVAL 0x26
95#define PIC_WDOG1_COUNT 0x28
96#define PIC_WDOG1_ENABLE0 0x2a
97#define PIC_WDOG1_ENABLE1 0x2c
98#define PIC_WDOG1_BEATCMD 0x2e
99#define PIC_WDOG1_BEAT0 0x30
100#define PIC_WDOG1_BEAT1 0x32
101
102#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
103#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
104#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
105#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
106#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
107#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
108#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
109
110#define PIC_TIMER0_MAXVAL 0x34
111#define PIC_TIMER1_MAXVAL 0x36
112#define PIC_TIMER2_MAXVAL 0x38
113#define PIC_TIMER3_MAXVAL 0x3a
114#define PIC_TIMER4_MAXVAL 0x3c
115#define PIC_TIMER5_MAXVAL 0x3e
116#define PIC_TIMER6_MAXVAL 0x40
117#define PIC_TIMER7_MAXVAL 0x42
118#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2))
119
120#define PIC_TIMER0_COUNT 0x44
121#define PIC_TIMER1_COUNT 0x46
122#define PIC_TIMER2_COUNT 0x48
123#define PIC_TIMER3_COUNT 0x4a
124#define PIC_TIMER4_COUNT 0x4c
125#define PIC_TIMER5_COUNT 0x4e
126#define PIC_TIMER6_COUNT 0x50
127#define PIC_TIMER7_COUNT 0x52
128#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
129
130#define PIC_ITE0_N0_N1 0x54
131#define PIC_ITE1_N0_N1 0x58
132#define PIC_ITE2_N0_N1 0x5c
133#define PIC_ITE3_N0_N1 0x60
134#define PIC_ITE4_N0_N1 0x64
135#define PIC_ITE5_N0_N1 0x68
136#define PIC_ITE6_N0_N1 0x6c
137#define PIC_ITE7_N0_N1 0x70
138#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
139
140#define PIC_ITE0_N2_N3 0x56
141#define PIC_ITE1_N2_N3 0x5a
142#define PIC_ITE2_N2_N3 0x5e
143#define PIC_ITE3_N2_N3 0x62
144#define PIC_ITE4_N2_N3 0x66
145#define PIC_ITE5_N2_N3 0x6a
146#define PIC_ITE6_N2_N3 0x6e
147#define PIC_ITE7_N2_N3 0x72
148#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
149
150#define PIC_IRT0 0x74
151#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
152
153#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL
154
155/*
156 * IRT Map
157 */
158#define PIC_NUM_IRTS 160
159
160#define PIC_IRT_WD_0_INDEX 0
161#define PIC_IRT_WD_1_INDEX 1
162#define PIC_IRT_WD_NMI_0_INDEX 2
163#define PIC_IRT_WD_NMI_1_INDEX 3
164#define PIC_IRT_TIMER_0_INDEX 4
165#define PIC_IRT_TIMER_1_INDEX 5
166#define PIC_IRT_TIMER_2_INDEX 6
167#define PIC_IRT_TIMER_3_INDEX 7
168#define PIC_IRT_TIMER_4_INDEX 8
169#define PIC_IRT_TIMER_5_INDEX 9
170#define PIC_IRT_TIMER_6_INDEX 10
171#define PIC_IRT_TIMER_7_INDEX 11
172#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
173#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX)
174
175
176/* 11 and 12 */
177#define PIC_NUM_MSG_Q_IRTS 32
178#define PIC_IRT_MSG_Q0_INDEX 12
179#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX)
180/* 12 to 43 */
181#define PIC_IRT_MSG_0_INDEX 44
182#define PIC_IRT_MSG_1_INDEX 45
183/* 44 and 45 */
184#define PIC_NUM_PCIE_MSIX_IRTS 32
185#define PIC_IRT_PCIE_MSIX_0_INDEX 46
186#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX)
187/* 46 to 77 */
188#define PIC_NUM_PCIE_LINK_IRTS 4
189#define PIC_IRT_PCIE_LINK_0_INDEX 78
190#define PIC_IRT_PCIE_LINK_1_INDEX 79
191#define PIC_IRT_PCIE_LINK_2_INDEX 80
192#define PIC_IRT_PCIE_LINK_3_INDEX 81
193#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
194/* 78 to 81 */
195#define PIC_NUM_NA_IRTS 32
196/* 82 to 113 */
197#define PIC_IRT_NA_0_INDEX 82
198#define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX)
199#define PIC_IRT_POE_INDEX 114
200
201#define PIC_NUM_USB_IRTS 6
202#define PIC_IRT_USB_0_INDEX 115
203#define PIC_IRT_EHCI_0_INDEX 115
204#define PIC_IRT_EHCI_1_INDEX 118
205#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX)
206/* 115 to 120 */
207#define PIC_IRT_GDX_INDEX 121
208#define PIC_IRT_SEC_INDEX 122
209#define PIC_IRT_RSA_INDEX 123
210
211#define PIC_NUM_COMP_IRTS 4
212#define PIC_IRT_COMP_0_INDEX 124
213#define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX)
214/* 124 to 127 */
215#define PIC_IRT_GBU_INDEX 128
216#define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */
217#define PIC_IRT_ICC_1_INDEX 130
218#define PIC_IRT_ICC_2_INDEX 131
219#define PIC_IRT_CAM_INDEX 132
220#define PIC_IRT_UART_0_INDEX 133
221#define PIC_IRT_UART_1_INDEX 134
222#define PIC_IRT_I2C_0_INDEX 135
223#define PIC_IRT_I2C_1_INDEX 136
224#define PIC_IRT_SYS_0_INDEX 137
225#define PIC_IRT_SYS_1_INDEX 138
226#define PIC_IRT_JTAG_INDEX 139
227#define PIC_IRT_PIC_INDEX 140
228#define PIC_IRT_NBU_INDEX 141
229#define PIC_IRT_TCU_INDEX 142
230#define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */
231#define PIC_IRT_DMC_0_INDEX 144
232#define PIC_IRT_DMC_1_INDEX 145
233
234#define PIC_NUM_GPIO_IRTS 4
235#define PIC_IRT_GPIO_0_INDEX 146
236#define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX)
237
238/* 146 to 149 */
239#define PIC_IRT_NOR_INDEX 150
240#define PIC_IRT_NAND_INDEX 151
241#define PIC_IRT_SPI_INDEX 152
242#define PIC_IRT_MMC_INDEX 153
243
244#define PIC_CLOCK_TIMER 7
245#define PIC_IRQ_BASE 8
246
247#if !defined(LOCORE) && !defined(__ASSEMBLY__)
248
249#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE)
250#define PIC_IRT_LAST_IRQ 63
251#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ)
252
253/*
254 * Misc
255 */
256#define PIC_IRT_VALID 1
257#define PIC_LOCAL_SCHEDULING 1
258#define PIC_GLOBAL_SCHEDULING 0
259
260#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
261#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
262#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
263#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
264
265/* IRT and h/w interrupt routines */
266static inline int
267nlm_pic_read_irt(uint64_t base, int irt_index)
268{
269 return nlm_read_pic_reg(base, PIC_IRT(irt_index));
270}
271
272static inline uint64_t
273nlm_pic_read_control(uint64_t base)
274{
275 return nlm_read_pic_reg(base, PIC_CTRL);
276}
277
278static inline void
279nlm_pic_write_control(uint64_t base, uint64_t control)
280{
281 nlm_write_pic_reg(base, PIC_CTRL, control);
282}
283
284static inline void
285nlm_pic_update_control(uint64_t base, uint64_t control)
286{
287 uint64_t val;
288
289 val = nlm_read_pic_reg(base, PIC_CTRL);
290 nlm_write_pic_reg(base, PIC_CTRL, control | val);
291}
292
293static inline void
294nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
295{
296 uint64_t val;
297
298 val = nlm_read_pic_reg(base, PIC_IRT(irt));
299 val |= cpu & 0xf;
300 if (cpu > 15)
301 val |= 1 << 16;
302 nlm_write_pic_reg(base, PIC_IRT(irt), val);
303}
304
305static inline void
306nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
307 int sch, int vec, int dt, int db, int dte)
308{
309 uint64_t val;
310
311 val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
312 ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
313 ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
314 (dte & 0xffff);
315
316 nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
317}
318
319static inline void
320nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
321 int sch, int vec, int cpu)
322{
323 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
324 (cpu >> 4), /* thread group */
325 1 << (cpu & 0xf)); /* thread mask */
326}
327
328static inline uint64_t
329nlm_pic_read_timer(uint64_t base, int timer)
330{
331 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
332}
333
334static inline void
335nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
336{
337 nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
338}
339
340static inline void
341nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
342{
343 uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
344 int en;
345
346 en = (irq > 0);
347 nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
348 nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
349 en, 0, 0, irq, cpu);
350
351 /* enable the timer */
352 pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
353 nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
354}
355
356static inline void
357nlm_pic_enable_irt(uint64_t base, int irt)
358{
359 uint64_t reg;
360
361 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
362 nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31));
363}
364
365static inline void
366nlm_pic_disable_irt(uint64_t base, int irt)
367{
368 uint32_t reg;
369
370 reg = nlm_read_pic_reg(base, PIC_IRT(irt));
371 nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31));
372}
373
374static inline void
375nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
376{
377 uint64_t ipi;
378 int node, ncpu;
379
380 node = hwt / 32;
381 ncpu = hwt & 0x1f;
382 ipi = ((uint64_t)nmi << 31) | (irq << 20) | (node << 17) |
383 (1 << (ncpu & 0xf));
384 if (ncpu > 15)
385 ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
386
387 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
388}
389
390static inline void
391nlm_pic_ack(uint64_t base, int irt_num)
392{
393 nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
394
395 /* Ack the Status register for Watchdog & System timers */
396 if (irt_num < 12)
397 nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
398}
399
400static inline void
401nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
402{
403 nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, 0);
404}
405
406extern uint64_t nlm_pic_base;
407int nlm_irq_to_irt(int irq);
408int nlm_irt_to_irq(int irt);
409
410#endif /* __ASSEMBLY__ */
411#endif /* _NLM_HAL_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
new file mode 100644
index 000000000000..21432f7d89b9
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -0,0 +1,129 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_SYS_H__
36#define __NLM_HAL_SYS_H__
37
38/**
39* @file_name sys.h
40* @author Netlogic Microsystems
41* @brief HAL for System configuration registers
42*/
43#define SYS_CHIP_RESET 0x00
44#define SYS_POWER_ON_RESET_CFG 0x01
45#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02
46#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03
47#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04
48#define SYS_EFUSE_DEVICE_CFG3 0x05
49#define SYS_EFUSE_DEVICE_CFG4 0x06
50#define SYS_EFUSE_DEVICE_CFG5 0x07
51#define SYS_EFUSE_DEVICE_CFG6 0x08
52#define SYS_EFUSE_DEVICE_CFG7 0x09
53#define SYS_PLL_CTRL 0x0a
54#define SYS_CPU_RESET 0x0b
55#define SYS_CPU_NONCOHERENT_MODE 0x0d
56#define SYS_CORE_DFS_DIS_CTRL 0x0e
57#define SYS_CORE_DFS_RST_CTRL 0x0f
58#define SYS_CORE_DFS_BYP_CTRL 0x10
59#define SYS_CORE_DFS_PHA_CTRL 0x11
60#define SYS_CORE_DFS_DIV_INC_CTRL 0x12
61#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13
62#define SYS_CORE_DFS_DIV_VALUE 0x14
63#define SYS_RESET 0x15
64#define SYS_DFS_DIS_CTRL 0x16
65#define SYS_DFS_RST_CTRL 0x17
66#define SYS_DFS_BYP_CTRL 0x18
67#define SYS_DFS_DIV_INC_CTRL 0x19
68#define SYS_DFS_DIV_DEC_CTRL 0x1a
69#define SYS_DFS_DIV_VALUE0 0x1b
70#define SYS_DFS_DIV_VALUE1 0x1c
71#define SYS_SENSE_AMP_DLY 0x1d
72#define SYS_SOC_SENSE_AMP_DLY 0x1e
73#define SYS_CTRL0 0x1f
74#define SYS_CTRL1 0x20
75#define SYS_TIMEOUT_BS1 0x21
76#define SYS_BYTE_SWAP 0x22
77#define SYS_VRM_VID 0x23
78#define SYS_PWR_RAM_CMD 0x24
79#define SYS_PWR_RAM_ADDR 0x25
80#define SYS_PWR_RAM_DATA0 0x26
81#define SYS_PWR_RAM_DATA1 0x27
82#define SYS_PWR_RAM_DATA2 0x28
83#define SYS_PWR_UCODE 0x29
84#define SYS_CPU0_PWR_STATUS 0x2a
85#define SYS_CPU1_PWR_STATUS 0x2b
86#define SYS_CPU2_PWR_STATUS 0x2c
87#define SYS_CPU3_PWR_STATUS 0x2d
88#define SYS_CPU4_PWR_STATUS 0x2e
89#define SYS_CPU5_PWR_STATUS 0x2f
90#define SYS_CPU6_PWR_STATUS 0x30
91#define SYS_CPU7_PWR_STATUS 0x31
92#define SYS_STATUS 0x32
93#define SYS_INT_POL 0x33
94#define SYS_INT_TYPE 0x34
95#define SYS_INT_STATUS 0x35
96#define SYS_INT_MASK0 0x36
97#define SYS_INT_MASK1 0x37
98#define SYS_UCO_S_ECC 0x38
99#define SYS_UCO_M_ECC 0x39
100#define SYS_UCO_ADDR 0x3a
101#define SYS_UCO_INSTR 0x3b
102#define SYS_MEM_BIST0 0x3c
103#define SYS_MEM_BIST1 0x3d
104#define SYS_MEM_BIST2 0x3e
105#define SYS_MEM_BIST3 0x3f
106#define SYS_MEM_BIST4 0x40
107#define SYS_MEM_BIST5 0x41
108#define SYS_MEM_BIST6 0x42
109#define SYS_MEM_BIST7 0x43
110#define SYS_MEM_BIST8 0x44
111#define SYS_MEM_BIST9 0x45
112#define SYS_MEM_BIST10 0x46
113#define SYS_MEM_BIST11 0x47
114#define SYS_MEM_BIST12 0x48
115#define SYS_SCRTCH0 0x49
116#define SYS_SCRTCH1 0x4a
117#define SYS_SCRTCH2 0x4b
118#define SYS_SCRTCH3 0x4c
119
120#ifndef __ASSEMBLY__
121
122#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r)
123#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v)
124#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
125#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
126
127extern uint64_t nlm_sys_base;
128#endif
129#endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
new file mode 100644
index 000000000000..6a7046ca094d
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -0,0 +1,191 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __XLP_HAL_UART_H__
36#define __XLP_HAL_UART_H__
37
38/* UART Specific registers */
39#define UART_RX_DATA 0x00
40#define UART_TX_DATA 0x00
41
42#define UART_INT_EN 0x01
43#define UART_INT_ID 0x02
44#define UART_FIFO_CTL 0x02
45#define UART_LINE_CTL 0x03
46#define UART_MODEM_CTL 0x04
47#define UART_LINE_STS 0x05
48#define UART_MODEM_STS 0x06
49
50#define UART_DIVISOR0 0x00
51#define UART_DIVISOR1 0x01
52
53#define BASE_BAUD (XLP_IO_CLK/16)
54#define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
55
56/* LCR mask values */
57#define LCR_5BITS 0x00
58#define LCR_6BITS 0x01
59#define LCR_7BITS 0x02
60#define LCR_8BITS 0x03
61#define LCR_STOPB 0x04
62#define LCR_PENAB 0x08
63#define LCR_PODD 0x00
64#define LCR_PEVEN 0x10
65#define LCR_PONE 0x20
66#define LCR_PZERO 0x30
67#define LCR_SBREAK 0x40
68#define LCR_EFR_ENABLE 0xbf
69#define LCR_DLAB 0x80
70
71/* MCR mask values */
72#define MCR_DTR 0x01
73#define MCR_RTS 0x02
74#define MCR_DRS 0x04
75#define MCR_IE 0x08
76#define MCR_LOOPBACK 0x10
77
78/* FCR mask values */
79#define FCR_RCV_RST 0x02
80#define FCR_XMT_RST 0x04
81#define FCR_RX_LOW 0x00
82#define FCR_RX_MEDL 0x40
83#define FCR_RX_MEDH 0x80
84#define FCR_RX_HIGH 0xc0
85
86/* IER mask values */
87#define IER_ERXRDY 0x1
88#define IER_ETXRDY 0x2
89#define IER_ERLS 0x4
90#define IER_EMSC 0x8
91
92#if !defined(LOCORE) && !defined(__ASSEMBLY__)
93
94#define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
95#define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
96#define nlm_get_uart_pcibase(node, inst) \
97 nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
98#define nlm_get_uart_regbase(node, inst) \
99 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
100
101static inline void
102nlm_uart_set_baudrate(uint64_t base, int baud)
103{
104 uint32_t lcr;
105
106 lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
107
108 /* enable divisor register, and write baud values */
109 nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
110 nlm_write_uart_reg(base, UART_DIVISOR0,
111 (BAUD_DIVISOR(baud) & 0xff));
112 nlm_write_uart_reg(base, UART_DIVISOR1,
113 ((BAUD_DIVISOR(baud) >> 8) & 0xff));
114
115 /* restore default lcr */
116 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
117}
118
119static inline void
120nlm_uart_outbyte(uint64_t base, char c)
121{
122 uint32_t lsr;
123
124 for (;;) {
125 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
126 if (lsr & 0x20)
127 break;
128 }
129
130 nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
131}
132
133static inline char
134nlm_uart_inbyte(uint64_t base)
135{
136 int data, lsr;
137
138 for (;;) {
139 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
140 if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
141 data = 0;
142 break;
143 }
144 if (lsr & 0x01) { /* Rx data */
145 data = nlm_read_uart_reg(base, UART_RX_DATA);
146 break;
147 }
148 }
149
150 return (char)data;
151}
152
153static inline int
154nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
155 int parity, int int_en, int loopback)
156{
157 uint32_t lcr;
158
159 lcr = 0;
160 if (databits >= 8)
161 lcr |= LCR_8BITS;
162 else if (databits == 7)
163 lcr |= LCR_7BITS;
164 else if (databits == 6)
165 lcr |= LCR_6BITS;
166 else
167 lcr |= LCR_5BITS;
168
169 if (stopbits > 1)
170 lcr |= LCR_STOPB;
171
172 lcr |= parity << 3;
173
174 /* setup default lcr */
175 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
176
177 /* Reset the FIFOs */
178 nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
179
180 nlm_uart_set_baudrate(base, baud);
181
182 if (loopback)
183 nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
184
185 if (int_en)
186 nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
187
188 return 0;
189}
190#endif /* !LOCORE && !__ASSEMBLY__ */
191#endif /* __XLP_HAL_UART_H__ */
diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 759df0692201..1540588e396d 100644
--- a/arch/mips/netlogic/xlr/xlr_console.c
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -32,15 +32,20 @@
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35#include <linux/types.h> 35#ifndef _NLM_HAL_XLP_H
36#include <asm/netlogic/xlr/iomap.h> 36#define _NLM_HAL_XLP_H
37 37
38void prom_putchar(char c) 38#define PIC_UART_0_IRQ 17
39{ 39#define PIC_UART_1_IRQ 18
40 nlm_reg_t *mmio;
41 40
42 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 41#ifndef __ASSEMBLY__
43 while (netlogic_read_reg(mmio, 0x5) == 0) 42
44 ; 43/* SMP support functions */
45 netlogic_write_reg(mmio, 0x0, c); 44void xlp_boot_core0_siblings(void);
46} 45void xlp_wakeup_secondary_cpus(void);
46
47void xlp_mmu_init(void);
48void nlm_hal_init(void);
49
50#endif /* !__ASSEMBLY__ */
51#endif /* _ASM_NLM_XLP_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
index 2e3a4dd53045..2e768f032e83 100644
--- a/arch/mips/include/asm/netlogic/xlr/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -106,26 +106,4 @@
106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 106#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 107#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
108 108
109#ifndef __ASSEMBLY__
110#include <linux/types.h>
111#include <asm/byteorder.h>
112
113typedef volatile __u32 nlm_reg_t;
114extern unsigned long netlogic_io_base;
115
116/* FIXME read once in write_reg */
117#ifdef CONFIG_CPU_LITTLE_ENDIAN
118#define netlogic_read_reg(base, offset) ((base)[(offset)])
119#define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value))
120#else
121#define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)]))
122#define netlogic_write_reg(base, offset, value) \
123 ((base)[(offset)] = cpu_to_be32((value)))
124#endif
125
126#define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)]))
127#define netlogic_write_reg_le32(base, offset, value) \
128 ((base)[(offset)] = cpu_to_le32((value)))
129#define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset)))
130#endif /* __ASSEMBLY__ */
131#endif 109#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h
new file mode 100644
index 000000000000..7e39d40be4f5
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/msidef.h
@@ -0,0 +1,84 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef ASM_RMI_MSIDEF_H
36#define ASM_RMI_MSIDEF_H
37
38/*
39 * Constants for Intel APIC based MSI messages.
40 * Adapted for the RMI XLR using identical defines
41 */
42
43/*
44 * Shifts for MSI data
45 */
46
47#define MSI_DATA_VECTOR_SHIFT 0
48#define MSI_DATA_VECTOR_MASK 0x000000ff
49#define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \
50 MSI_DATA_VECTOR_MASK)
51
52#define MSI_DATA_DELIVERY_MODE_SHIFT 8
53#define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
54#define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
55
56#define MSI_DATA_LEVEL_SHIFT 14
57#define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT)
58#define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT)
59
60#define MSI_DATA_TRIGGER_SHIFT 15
61#define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT)
62#define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT)
63
64/*
65 * Shift/mask fields for msi address
66 */
67
68#define MSI_ADDR_BASE_HI 0
69#define MSI_ADDR_BASE_LO 0xfee00000
70
71#define MSI_ADDR_DEST_MODE_SHIFT 2
72#define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT)
73#define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT)
74
75#define MSI_ADDR_REDIRECTION_SHIFT 3
76#define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT)
77#define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT)
78
79#define MSI_ADDR_DEST_ID_SHIFT 12
80#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
81#define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
82 MSI_ADDR_DEST_ID_MASK)
83
84#endif /* ASM_RMI_MSIDEF_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 5cceb746f080..868013e62f32 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -193,39 +193,72 @@
193/* end XLS */ 193/* end XLS */
194 194
195#ifndef __ASSEMBLY__ 195#ifndef __ASSEMBLY__
196static inline void pic_send_ipi(u32 ipi) 196
197#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \
198 ((irq) <= PIC_TIMER_7_IRQ))
199#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \
200 ((irq) <= PIC_IRT_LAST_IRQ))
201
202static inline int
203nlm_irq_to_irt(int irq)
197{ 204{
198 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 205 if (PIC_IRQ_IS_IRT(irq) == 0)
206 return -1;
199 207
200 netlogic_write_reg(mmio, PIC_IPI, ipi); 208 return PIC_IRQ_TO_INTR(irq);
201} 209}
202 210
203static inline u32 pic_read_control(void) 211static inline int
212nlm_irt_to_irq(int irt)
204{ 213{
205 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
206 214
207 return netlogic_read_reg(mmio, PIC_CTRL); 215 return PIC_INTR_TO_IRQ(irt);
208} 216}
209 217
210static inline void pic_write_control(u32 control) 218static inline void
219nlm_pic_enable_irt(uint64_t base, int irt)
211{ 220{
212 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 221 uint32_t reg;
213 222
214 netlogic_write_reg(mmio, PIC_CTRL, control); 223 reg = nlm_read_reg(base, PIC_IRT_1(irt));
224 nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31));
215} 225}
216 226
217static inline void pic_update_control(u32 control) 227static inline void
228nlm_pic_disable_irt(uint64_t base, int irt)
218{ 229{
219 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); 230 uint32_t reg;
220 231
221 netlogic_write_reg(mmio, PIC_CTRL, 232 reg = nlm_read_reg(base, PIC_IRT_1(irt));
222 (control | netlogic_read_reg(mmio, PIC_CTRL))); 233 nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31));
223} 234}
224 235
225#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ 236static inline void
226 ((irq) <= PIC_TIMER_7_IRQ)) 237nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi)
227#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ 238{
228 ((irq) <= PIC_IRT_LAST_IRQ)) 239 unsigned int tid, pid;
229#endif 240
241 tid = hwt & 0x3;
242 pid = (hwt >> 2) & 0x07;
243 nlm_write_reg(base, PIC_IPI,
244 (pid << 20) | (tid << 16) | (nmi << 8) | irq);
245}
246
247static inline void
248nlm_pic_ack(uint64_t base, int irt)
249{
250 nlm_write_reg(base, PIC_INT_ACK, 1u << irt);
251}
230 252
253static inline void
254nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt)
255{
256 nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
257 /* local scheduling, invalid, level by default */
258 nlm_write_reg(base, PIC_IRT_1(irt),
259 (1 << 30) | (1 << 6) | irq);
260}
261
262extern uint64_t nlm_pic_base;
263#endif
231#endif /* _ASM_NLM_XLR_PIC_H */ 264#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h
index 3e6372692a04..ff4a17b0bf78 100644
--- a/arch/mips/include/asm/netlogic/xlr/xlr.h
+++ b/arch/mips/include/asm/netlogic/xlr/xlr.h
@@ -40,17 +40,8 @@ struct uart_port;
40unsigned int nlm_xlr_uart_in(struct uart_port *, int); 40unsigned int nlm_xlr_uart_in(struct uart_port *, int);
41void nlm_xlr_uart_out(struct uart_port *, int, int); 41void nlm_xlr_uart_out(struct uart_port *, int, int);
42 42
43/* SMP support functions */ 43/* SMP helpers */
44struct irq_desc; 44void xlr_wakeup_secondary_cpus(void);
45void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
46void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
47int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
48void nlm_smp_irq_init(void);
49void nlm_boot_smp_nmi(void);
50void prom_pre_boot_secondary_cpus(void);
51
52extern struct plat_smp_ops nlm_smp_ops;
53extern unsigned long nlm_common_ebase;
54 45
55/* XLS B silicon "Rook" */ 46/* XLS B silicon "Rook" */
56static inline unsigned int nlm_chip_is_xls_b(void) 47static inline unsigned int nlm_chip_is_xls_b(void)
diff --git a/arch/mips/include/asm/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h
new file mode 100644
index 000000000000..3c74d826e2e6
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-address.h
@@ -0,0 +1,274 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2009 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * Typedefs and defines for working with Octeon physical addresses.
30 *
31 */
32#ifndef __CVMX_ADDRESS_H__
33#define __CVMX_ADDRESS_H__
34
35#if 0
36typedef enum {
37 CVMX_MIPS_SPACE_XKSEG = 3LL,
38 CVMX_MIPS_SPACE_XKPHYS = 2LL,
39 CVMX_MIPS_SPACE_XSSEG = 1LL,
40 CVMX_MIPS_SPACE_XUSEG = 0LL
41} cvmx_mips_space_t;
42#endif
43
44typedef enum {
45 CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
46 CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
47 CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
48 CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
49} cvmx_mips_xkseg_space_t;
50
51/* decodes <14:13> of a kseg3 window address */
52typedef enum {
53 CVMX_ADD_WIN_SCR = 0L,
54 /* see cvmx_add_win_dma_dec_t for further decode */
55 CVMX_ADD_WIN_DMA = 1L,
56 CVMX_ADD_WIN_UNUSED = 2L,
57 CVMX_ADD_WIN_UNUSED2 = 3L
58} cvmx_add_win_dec_t;
59
60/* decode within DMA space */
61typedef enum {
62 /*
63 * Add store data to the write buffer entry, allocating it if
64 * necessary.
65 */
66 CVMX_ADD_WIN_DMA_ADD = 0L,
67 /* send out the write buffer entry to DRAM */
68 CVMX_ADD_WIN_DMA_SENDMEM = 1L,
69 /* store data must be normal DRAM memory space address in this case */
70 /* send out the write buffer entry as an IOBDMA command */
71 CVMX_ADD_WIN_DMA_SENDDMA = 2L,
72 /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
73 /* send out the write buffer entry as an IO write */
74 CVMX_ADD_WIN_DMA_SENDIO = 3L,
75 /* store data must be normal IO space address in this case */
76 /* send out a single-tick command on the NCB bus */
77 CVMX_ADD_WIN_DMA_SENDSINGLE = 4L,
78 /* no write buffer data needed/used */
79} cvmx_add_win_dma_dec_t;
80
81/*
82 * Physical Address Decode
83 *
84 * Octeon-I HW never interprets this X (<39:36> reserved
85 * for future expansion), software should set to 0.
86 *
87 * - 0x0 XXX0 0000 0000 to DRAM Cached
88 * - 0x0 XXX0 0FFF FFFF
89 *
90 * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000
91 * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF)
92 *
93 * - 0x0 XXX0 2000 0000 to DRAM Cached
94 * - 0x0 XXXF FFFF FFFF
95 *
96 * - 0x1 00X0 0000 0000 to Boot Bus Uncached
97 * - 0x1 00XF FFFF FFFF
98 *
99 * - 0x1 01X0 0000 0000 to Other NCB Uncached
100 * - 0x1 FFXF FFFF FFFF devices
101 *
102 * Decode of all Octeon addresses
103 */
104typedef union {
105
106 uint64_t u64;
107 /* mapped or unmapped virtual address */
108 struct {
109 uint64_t R:2;
110 uint64_t offset:62;
111 } sva;
112
113 /* mapped USEG virtual addresses (typically) */
114 struct {
115 uint64_t zeroes:33;
116 uint64_t offset:31;
117 } suseg;
118
119 /* mapped or unmapped virtual address */
120 struct {
121 uint64_t ones:33;
122 uint64_t sp:2;
123 uint64_t offset:29;
124 } sxkseg;
125
126 /*
127 * physical address accessed through xkphys unmapped virtual
128 * address.
129 */
130 struct {
131 uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */
132 uint64_t cca:3; /* ignored by octeon */
133 uint64_t mbz:10;
134 uint64_t pa:49; /* physical address */
135 } sxkphys;
136
137 /* physical address */
138 struct {
139 uint64_t mbz:15;
140 /* if set, the address is uncached and resides on MCB bus */
141 uint64_t is_io:1;
142 /*
143 * the hardware ignores this field when is_io==0, else
144 * device ID.
145 */
146 uint64_t did:8;
147 /* the hardware ignores <39:36> in Octeon I */
148 uint64_t unaddr:4;
149 uint64_t offset:36;
150 } sphys;
151
152 /* physical mem address */
153 struct {
154 /* techically, <47:40> are dont-cares */
155 uint64_t zeroes:24;
156 /* the hardware ignores <39:36> in Octeon I */
157 uint64_t unaddr:4;
158 uint64_t offset:36;
159 } smem;
160
161 /* physical IO address */
162 struct {
163 uint64_t mem_region:2;
164 uint64_t mbz:13;
165 /* 1 in this case */
166 uint64_t is_io:1;
167 /*
168 * The hardware ignores this field when is_io==0, else
169 * device ID.
170 */
171 uint64_t did:8;
172 /* the hardware ignores <39:36> in Octeon I */
173 uint64_t unaddr:4;
174 uint64_t offset:36;
175 } sio;
176
177 /*
178 * Scratchpad virtual address - accessed through a window at
179 * the end of kseg3
180 */
181 struct {
182 uint64_t ones:49;
183 /* CVMX_ADD_WIN_SCR (0) in this case */
184 cvmx_add_win_dec_t csrdec:2;
185 uint64_t addr:13;
186 } sscr;
187
188 /* there should only be stores to IOBDMA space, no loads */
189 /*
190 * IOBDMA virtual address - accessed through a window at the
191 * end of kseg3
192 */
193 struct {
194 uint64_t ones:49;
195 uint64_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */
196 uint64_t unused2:3;
197 uint64_t type:3;
198 uint64_t addr:7;
199 } sdma;
200
201 struct {
202 uint64_t didspace:24;
203 uint64_t unused:40;
204 } sfilldidspace;
205
206} cvmx_addr_t;
207
208/* These macros for used by 32 bit applications */
209
210#define CVMX_MIPS32_SPACE_KSEG0 1l
211#define CVMX_ADD_SEG32(segment, add) \
212 (((int32_t)segment << 31) | (int32_t)(add))
213
214/*
215 * Currently all IOs are performed using XKPHYS addressing. Linux uses
216 * the CvmMemCtl register to enable XKPHYS addressing to IO space from
217 * user mode. Future OSes may need to change the upper bits of IO
218 * addresses. The following define controls the upper two bits for all
219 * IO addresses generated by the simple executive library.
220 */
221#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
222
223/* These macros simplify the process of creating common IO addresses */
224#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
225#ifndef CVMX_ADD_IO_SEG
226#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
227#endif
228#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
229#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
230#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid))
231
232 /* from include/ncb_rsl_id.v */
233#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
234#define CVMX_OCT_DID_GMX0 1ULL
235#define CVMX_OCT_DID_GMX1 2ULL
236#define CVMX_OCT_DID_PCI 3ULL
237#define CVMX_OCT_DID_KEY 4ULL
238#define CVMX_OCT_DID_FPA 5ULL
239#define CVMX_OCT_DID_DFA 6ULL
240#define CVMX_OCT_DID_ZIP 7ULL
241#define CVMX_OCT_DID_RNG 8ULL
242#define CVMX_OCT_DID_IPD 9ULL
243#define CVMX_OCT_DID_PKT 10ULL
244#define CVMX_OCT_DID_TIM 11ULL
245#define CVMX_OCT_DID_TAG 12ULL
246 /* the rest are not on the IO bus */
247#define CVMX_OCT_DID_L2C 16ULL
248#define CVMX_OCT_DID_LMC 17ULL
249#define CVMX_OCT_DID_SPX0 18ULL
250#define CVMX_OCT_DID_SPX1 19ULL
251#define CVMX_OCT_DID_PIP 20ULL
252#define CVMX_OCT_DID_ASX0 22ULL
253#define CVMX_OCT_DID_ASX1 23ULL
254#define CVMX_OCT_DID_IOB 30ULL
255
256#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
257#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
258#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
259#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
260#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
261#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
262#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
263#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
264#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
265#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
266#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
267#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
268#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
269#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
270#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
271#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
272#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
273
274#endif /* __CVMX_ADDRESS_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-asxx-defs.h b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
new file mode 100644
index 000000000000..91415a85e8d2
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-asxx-defs.h
@@ -0,0 +1,475 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_ASXX_DEFS_H__
29#define __CVMX_ASXX_DEFS_H__
30
31#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \
32 CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull))
33#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \
34 CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull))
35#define CVMX_ASXX_INT_EN(block_id) \
36 CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_ASXX_INT_REG(block_id) \
38 CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \
40 CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull))
41#define CVMX_ASXX_PRT_LOOP(block_id) \
42 CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_ASXX_RLD_BYPASS(block_id) \
44 CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \
46 CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_ASXX_RLD_COMP(block_id) \
48 CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_ASXX_RLD_DATA_DRV(block_id) \
50 CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \
52 CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \
54 CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \
56 CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \
58 CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \
60 CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_ASXX_RLD_SETTING(block_id) \
62 CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull))
63#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \
64 CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
65#define CVMX_ASXX_RX_PRT_EN(block_id) \
66 CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull))
67#define CVMX_ASXX_RX_WOL(block_id) \
68 CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull))
69#define CVMX_ASXX_RX_WOL_MSK(block_id) \
70 CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull))
71#define CVMX_ASXX_RX_WOL_POWOK(block_id) \
72 CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull))
73#define CVMX_ASXX_RX_WOL_SIG(block_id) \
74 CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull))
75#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \
76 CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
77#define CVMX_ASXX_TX_COMP_BYP(block_id) \
78 CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull))
79#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \
80 CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
81#define CVMX_ASXX_TX_PRT_EN(block_id) \
82 CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull))
83
84union cvmx_asxx_gmii_rx_clk_set {
85 uint64_t u64;
86 struct cvmx_asxx_gmii_rx_clk_set_s {
87 uint64_t reserved_5_63:59;
88 uint64_t setting:5;
89 } s;
90 struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
91 struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
92 struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
93};
94
95union cvmx_asxx_gmii_rx_dat_set {
96 uint64_t u64;
97 struct cvmx_asxx_gmii_rx_dat_set_s {
98 uint64_t reserved_5_63:59;
99 uint64_t setting:5;
100 } s;
101 struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
102 struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
103 struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
104};
105
106union cvmx_asxx_int_en {
107 uint64_t u64;
108 struct cvmx_asxx_int_en_s {
109 uint64_t reserved_12_63:52;
110 uint64_t txpsh:4;
111 uint64_t txpop:4;
112 uint64_t ovrflw:4;
113 } s;
114 struct cvmx_asxx_int_en_cn30xx {
115 uint64_t reserved_11_63:53;
116 uint64_t txpsh:3;
117 uint64_t reserved_7_7:1;
118 uint64_t txpop:3;
119 uint64_t reserved_3_3:1;
120 uint64_t ovrflw:3;
121 } cn30xx;
122 struct cvmx_asxx_int_en_cn30xx cn31xx;
123 struct cvmx_asxx_int_en_s cn38xx;
124 struct cvmx_asxx_int_en_s cn38xxp2;
125 struct cvmx_asxx_int_en_cn30xx cn50xx;
126 struct cvmx_asxx_int_en_s cn58xx;
127 struct cvmx_asxx_int_en_s cn58xxp1;
128};
129
130union cvmx_asxx_int_reg {
131 uint64_t u64;
132 struct cvmx_asxx_int_reg_s {
133 uint64_t reserved_12_63:52;
134 uint64_t txpsh:4;
135 uint64_t txpop:4;
136 uint64_t ovrflw:4;
137 } s;
138 struct cvmx_asxx_int_reg_cn30xx {
139 uint64_t reserved_11_63:53;
140 uint64_t txpsh:3;
141 uint64_t reserved_7_7:1;
142 uint64_t txpop:3;
143 uint64_t reserved_3_3:1;
144 uint64_t ovrflw:3;
145 } cn30xx;
146 struct cvmx_asxx_int_reg_cn30xx cn31xx;
147 struct cvmx_asxx_int_reg_s cn38xx;
148 struct cvmx_asxx_int_reg_s cn38xxp2;
149 struct cvmx_asxx_int_reg_cn30xx cn50xx;
150 struct cvmx_asxx_int_reg_s cn58xx;
151 struct cvmx_asxx_int_reg_s cn58xxp1;
152};
153
154union cvmx_asxx_mii_rx_dat_set {
155 uint64_t u64;
156 struct cvmx_asxx_mii_rx_dat_set_s {
157 uint64_t reserved_5_63:59;
158 uint64_t setting:5;
159 } s;
160 struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
161 struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
162};
163
164union cvmx_asxx_prt_loop {
165 uint64_t u64;
166 struct cvmx_asxx_prt_loop_s {
167 uint64_t reserved_8_63:56;
168 uint64_t ext_loop:4;
169 uint64_t int_loop:4;
170 } s;
171 struct cvmx_asxx_prt_loop_cn30xx {
172 uint64_t reserved_7_63:57;
173 uint64_t ext_loop:3;
174 uint64_t reserved_3_3:1;
175 uint64_t int_loop:3;
176 } cn30xx;
177 struct cvmx_asxx_prt_loop_cn30xx cn31xx;
178 struct cvmx_asxx_prt_loop_s cn38xx;
179 struct cvmx_asxx_prt_loop_s cn38xxp2;
180 struct cvmx_asxx_prt_loop_cn30xx cn50xx;
181 struct cvmx_asxx_prt_loop_s cn58xx;
182 struct cvmx_asxx_prt_loop_s cn58xxp1;
183};
184
185union cvmx_asxx_rld_bypass {
186 uint64_t u64;
187 struct cvmx_asxx_rld_bypass_s {
188 uint64_t reserved_1_63:63;
189 uint64_t bypass:1;
190 } s;
191 struct cvmx_asxx_rld_bypass_s cn38xx;
192 struct cvmx_asxx_rld_bypass_s cn38xxp2;
193 struct cvmx_asxx_rld_bypass_s cn58xx;
194 struct cvmx_asxx_rld_bypass_s cn58xxp1;
195};
196
197union cvmx_asxx_rld_bypass_setting {
198 uint64_t u64;
199 struct cvmx_asxx_rld_bypass_setting_s {
200 uint64_t reserved_5_63:59;
201 uint64_t setting:5;
202 } s;
203 struct cvmx_asxx_rld_bypass_setting_s cn38xx;
204 struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
205 struct cvmx_asxx_rld_bypass_setting_s cn58xx;
206 struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
207};
208
209union cvmx_asxx_rld_comp {
210 uint64_t u64;
211 struct cvmx_asxx_rld_comp_s {
212 uint64_t reserved_9_63:55;
213 uint64_t pctl:5;
214 uint64_t nctl:4;
215 } s;
216 struct cvmx_asxx_rld_comp_cn38xx {
217 uint64_t reserved_8_63:56;
218 uint64_t pctl:4;
219 uint64_t nctl:4;
220 } cn38xx;
221 struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
222 struct cvmx_asxx_rld_comp_s cn58xx;
223 struct cvmx_asxx_rld_comp_s cn58xxp1;
224};
225
226union cvmx_asxx_rld_data_drv {
227 uint64_t u64;
228 struct cvmx_asxx_rld_data_drv_s {
229 uint64_t reserved_8_63:56;
230 uint64_t pctl:4;
231 uint64_t nctl:4;
232 } s;
233 struct cvmx_asxx_rld_data_drv_s cn38xx;
234 struct cvmx_asxx_rld_data_drv_s cn38xxp2;
235 struct cvmx_asxx_rld_data_drv_s cn58xx;
236 struct cvmx_asxx_rld_data_drv_s cn58xxp1;
237};
238
239union cvmx_asxx_rld_fcram_mode {
240 uint64_t u64;
241 struct cvmx_asxx_rld_fcram_mode_s {
242 uint64_t reserved_1_63:63;
243 uint64_t mode:1;
244 } s;
245 struct cvmx_asxx_rld_fcram_mode_s cn38xx;
246 struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
247};
248
249union cvmx_asxx_rld_nctl_strong {
250 uint64_t u64;
251 struct cvmx_asxx_rld_nctl_strong_s {
252 uint64_t reserved_5_63:59;
253 uint64_t nctl:5;
254 } s;
255 struct cvmx_asxx_rld_nctl_strong_s cn38xx;
256 struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
257 struct cvmx_asxx_rld_nctl_strong_s cn58xx;
258 struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
259};
260
261union cvmx_asxx_rld_nctl_weak {
262 uint64_t u64;
263 struct cvmx_asxx_rld_nctl_weak_s {
264 uint64_t reserved_5_63:59;
265 uint64_t nctl:5;
266 } s;
267 struct cvmx_asxx_rld_nctl_weak_s cn38xx;
268 struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
269 struct cvmx_asxx_rld_nctl_weak_s cn58xx;
270 struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
271};
272
273union cvmx_asxx_rld_pctl_strong {
274 uint64_t u64;
275 struct cvmx_asxx_rld_pctl_strong_s {
276 uint64_t reserved_5_63:59;
277 uint64_t pctl:5;
278 } s;
279 struct cvmx_asxx_rld_pctl_strong_s cn38xx;
280 struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
281 struct cvmx_asxx_rld_pctl_strong_s cn58xx;
282 struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
283};
284
285union cvmx_asxx_rld_pctl_weak {
286 uint64_t u64;
287 struct cvmx_asxx_rld_pctl_weak_s {
288 uint64_t reserved_5_63:59;
289 uint64_t pctl:5;
290 } s;
291 struct cvmx_asxx_rld_pctl_weak_s cn38xx;
292 struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
293 struct cvmx_asxx_rld_pctl_weak_s cn58xx;
294 struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
295};
296
297union cvmx_asxx_rld_setting {
298 uint64_t u64;
299 struct cvmx_asxx_rld_setting_s {
300 uint64_t reserved_13_63:51;
301 uint64_t dfaset:5;
302 uint64_t dfalag:1;
303 uint64_t dfalead:1;
304 uint64_t dfalock:1;
305 uint64_t setting:5;
306 } s;
307 struct cvmx_asxx_rld_setting_cn38xx {
308 uint64_t reserved_5_63:59;
309 uint64_t setting:5;
310 } cn38xx;
311 struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
312 struct cvmx_asxx_rld_setting_s cn58xx;
313 struct cvmx_asxx_rld_setting_s cn58xxp1;
314};
315
316union cvmx_asxx_rx_clk_setx {
317 uint64_t u64;
318 struct cvmx_asxx_rx_clk_setx_s {
319 uint64_t reserved_5_63:59;
320 uint64_t setting:5;
321 } s;
322 struct cvmx_asxx_rx_clk_setx_s cn30xx;
323 struct cvmx_asxx_rx_clk_setx_s cn31xx;
324 struct cvmx_asxx_rx_clk_setx_s cn38xx;
325 struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
326 struct cvmx_asxx_rx_clk_setx_s cn50xx;
327 struct cvmx_asxx_rx_clk_setx_s cn58xx;
328 struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
329};
330
331union cvmx_asxx_rx_prt_en {
332 uint64_t u64;
333 struct cvmx_asxx_rx_prt_en_s {
334 uint64_t reserved_4_63:60;
335 uint64_t prt_en:4;
336 } s;
337 struct cvmx_asxx_rx_prt_en_cn30xx {
338 uint64_t reserved_3_63:61;
339 uint64_t prt_en:3;
340 } cn30xx;
341 struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
342 struct cvmx_asxx_rx_prt_en_s cn38xx;
343 struct cvmx_asxx_rx_prt_en_s cn38xxp2;
344 struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
345 struct cvmx_asxx_rx_prt_en_s cn58xx;
346 struct cvmx_asxx_rx_prt_en_s cn58xxp1;
347};
348
349union cvmx_asxx_rx_wol {
350 uint64_t u64;
351 struct cvmx_asxx_rx_wol_s {
352 uint64_t reserved_2_63:62;
353 uint64_t status:1;
354 uint64_t enable:1;
355 } s;
356 struct cvmx_asxx_rx_wol_s cn38xx;
357 struct cvmx_asxx_rx_wol_s cn38xxp2;
358};
359
360union cvmx_asxx_rx_wol_msk {
361 uint64_t u64;
362 struct cvmx_asxx_rx_wol_msk_s {
363 uint64_t msk:64;
364 } s;
365 struct cvmx_asxx_rx_wol_msk_s cn38xx;
366 struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
367};
368
369union cvmx_asxx_rx_wol_powok {
370 uint64_t u64;
371 struct cvmx_asxx_rx_wol_powok_s {
372 uint64_t reserved_1_63:63;
373 uint64_t powerok:1;
374 } s;
375 struct cvmx_asxx_rx_wol_powok_s cn38xx;
376 struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
377};
378
379union cvmx_asxx_rx_wol_sig {
380 uint64_t u64;
381 struct cvmx_asxx_rx_wol_sig_s {
382 uint64_t reserved_32_63:32;
383 uint64_t sig:32;
384 } s;
385 struct cvmx_asxx_rx_wol_sig_s cn38xx;
386 struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
387};
388
389union cvmx_asxx_tx_clk_setx {
390 uint64_t u64;
391 struct cvmx_asxx_tx_clk_setx_s {
392 uint64_t reserved_5_63:59;
393 uint64_t setting:5;
394 } s;
395 struct cvmx_asxx_tx_clk_setx_s cn30xx;
396 struct cvmx_asxx_tx_clk_setx_s cn31xx;
397 struct cvmx_asxx_tx_clk_setx_s cn38xx;
398 struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
399 struct cvmx_asxx_tx_clk_setx_s cn50xx;
400 struct cvmx_asxx_tx_clk_setx_s cn58xx;
401 struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
402};
403
404union cvmx_asxx_tx_comp_byp {
405 uint64_t u64;
406 struct cvmx_asxx_tx_comp_byp_s {
407 uint64_t reserved_0_63:64;
408 } s;
409 struct cvmx_asxx_tx_comp_byp_cn30xx {
410 uint64_t reserved_9_63:55;
411 uint64_t bypass:1;
412 uint64_t pctl:4;
413 uint64_t nctl:4;
414 } cn30xx;
415 struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
416 struct cvmx_asxx_tx_comp_byp_cn38xx {
417 uint64_t reserved_8_63:56;
418 uint64_t pctl:4;
419 uint64_t nctl:4;
420 } cn38xx;
421 struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
422 struct cvmx_asxx_tx_comp_byp_cn50xx {
423 uint64_t reserved_17_63:47;
424 uint64_t bypass:1;
425 uint64_t reserved_13_15:3;
426 uint64_t pctl:5;
427 uint64_t reserved_5_7:3;
428 uint64_t nctl:5;
429 } cn50xx;
430 struct cvmx_asxx_tx_comp_byp_cn58xx {
431 uint64_t reserved_13_63:51;
432 uint64_t pctl:5;
433 uint64_t reserved_5_7:3;
434 uint64_t nctl:5;
435 } cn58xx;
436 struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
437};
438
439union cvmx_asxx_tx_hi_waterx {
440 uint64_t u64;
441 struct cvmx_asxx_tx_hi_waterx_s {
442 uint64_t reserved_4_63:60;
443 uint64_t mark:4;
444 } s;
445 struct cvmx_asxx_tx_hi_waterx_cn30xx {
446 uint64_t reserved_3_63:61;
447 uint64_t mark:3;
448 } cn30xx;
449 struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
450 struct cvmx_asxx_tx_hi_waterx_s cn38xx;
451 struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
452 struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
453 struct cvmx_asxx_tx_hi_waterx_s cn58xx;
454 struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
455};
456
457union cvmx_asxx_tx_prt_en {
458 uint64_t u64;
459 struct cvmx_asxx_tx_prt_en_s {
460 uint64_t reserved_4_63:60;
461 uint64_t prt_en:4;
462 } s;
463 struct cvmx_asxx_tx_prt_en_cn30xx {
464 uint64_t reserved_3_63:61;
465 uint64_t prt_en:3;
466 } cn30xx;
467 struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
468 struct cvmx_asxx_tx_prt_en_s cn38xx;
469 struct cvmx_asxx_tx_prt_en_s cn38xxp2;
470 struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
471 struct cvmx_asxx_tx_prt_en_s cn58xx;
472 struct cvmx_asxx_tx_prt_en_s cn58xxp1;
473};
474
475#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 4e4c3a8282d6..1db1dc2724cb 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -39,7 +39,7 @@
39 * versions. 39 * versions.
40 */ 40 */
41#define CVMX_BOOTINFO_MAJ_VER 1 41#define CVMX_BOOTINFO_MAJ_VER 1
42#define CVMX_BOOTINFO_MIN_VER 2 42#define CVMX_BOOTINFO_MIN_VER 3
43 43
44#if (CVMX_BOOTINFO_MAJ_VER == 1) 44#if (CVMX_BOOTINFO_MAJ_VER == 1)
45#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20 45#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
@@ -116,7 +116,13 @@ struct cvmx_bootinfo {
116 */ 116 */
117 uint32_t config_flags; 117 uint32_t config_flags;
118#endif 118#endif
119 119#if (CVMX_BOOTINFO_MIN_VER >= 3)
120 /*
121 * Address of the OF Flattened Device Tree structure
122 * describing the board.
123 */
124 uint64_t fdt_addr;
125#endif
120}; 126};
121 127
122#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0) 128#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0)
@@ -164,6 +170,22 @@ enum cvmx_board_types_enum {
164 /* Special 'generic' board type, supports many boards */ 170 /* Special 'generic' board type, supports many boards */
165 CVMX_BOARD_TYPE_GENERIC = 28, 171 CVMX_BOARD_TYPE_GENERIC = 28,
166 CVMX_BOARD_TYPE_EBH5610 = 29, 172 CVMX_BOARD_TYPE_EBH5610 = 29,
173 CVMX_BOARD_TYPE_LANAI2_A = 30,
174 CVMX_BOARD_TYPE_LANAI2_U = 31,
175 CVMX_BOARD_TYPE_EBB5600 = 32,
176 CVMX_BOARD_TYPE_EBB6300 = 33,
177 CVMX_BOARD_TYPE_NIC_XLE_10G = 34,
178 CVMX_BOARD_TYPE_LANAI2_G = 35,
179 CVMX_BOARD_TYPE_EBT5810 = 36,
180 CVMX_BOARD_TYPE_NIC10E = 37,
181 CVMX_BOARD_TYPE_EP6300C = 38,
182 CVMX_BOARD_TYPE_EBB6800 = 39,
183 CVMX_BOARD_TYPE_NIC4E = 40,
184 CVMX_BOARD_TYPE_NIC2E = 41,
185 CVMX_BOARD_TYPE_EBB6600 = 42,
186 CVMX_BOARD_TYPE_REDWING = 43,
187 CVMX_BOARD_TYPE_NIC68_4 = 44,
188 CVMX_BOARD_TYPE_NIC10E_66 = 45,
167 CVMX_BOARD_TYPE_MAX, 189 CVMX_BOARD_TYPE_MAX,
168 190
169 /* 191 /*
@@ -181,6 +203,23 @@ enum cvmx_board_types_enum {
181 CVMX_BOARD_TYPE_CUST_NS0216 = 10002, 203 CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
182 CVMX_BOARD_TYPE_CUST_NB5 = 10003, 204 CVMX_BOARD_TYPE_CUST_NB5 = 10003,
183 CVMX_BOARD_TYPE_CUST_WMR500 = 10004, 205 CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
206 CVMX_BOARD_TYPE_CUST_ITB101 = 10005,
207 CVMX_BOARD_TYPE_CUST_NTE102 = 10006,
208 CVMX_BOARD_TYPE_CUST_AGS103 = 10007,
209 CVMX_BOARD_TYPE_CUST_GST104 = 10008,
210 CVMX_BOARD_TYPE_CUST_GCT105 = 10009,
211 CVMX_BOARD_TYPE_CUST_AGS106 = 10010,
212 CVMX_BOARD_TYPE_CUST_SGM107 = 10011,
213 CVMX_BOARD_TYPE_CUST_GCT108 = 10012,
214 CVMX_BOARD_TYPE_CUST_AGS109 = 10013,
215 CVMX_BOARD_TYPE_CUST_GCT110 = 10014,
216 CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER = 10015,
217 CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER = 10016,
218 CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX = 10017,
219 CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX = 10018,
220 CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX = 10019,
221 CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX = 10020,
222 CVMX_BOARD_TYPE_CUST_L2_ZINWELL = 10021,
184 CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000, 223 CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
185 224
186 /* 225 /*
@@ -241,6 +280,22 @@ static inline const char *cvmx_board_type_to_string(enum
241 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200) 280 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
242 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC) 281 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
243 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610) 282 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
283 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_A)
284 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_U)
285 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB5600)
286 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6300)
287 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_10G)
288 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_LANAI2_G)
289 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5810)
290 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E)
291 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EP6300C)
292 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6800)
293 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC4E)
294 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC2E)
295 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBB6600)
296 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_REDWING)
297 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC68_4)
298 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC10E_66)
244 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX) 299 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
245 300
246 /* Customer boards listed here */ 301 /* Customer boards listed here */
@@ -249,6 +304,23 @@ static inline const char *cvmx_board_type_to_string(enum
249 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216) 304 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
250 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5) 305 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
251 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500) 306 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
307 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_ITB101)
308 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NTE102)
309 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS103)
310 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GST104)
311 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT105)
312 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS106)
313 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_SGM107)
314 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT108)
315 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_AGS109)
316 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_GCT110)
317 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_SENDER)
318 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_AIR_RECEIVER)
319 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_TX)
320 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ACCTON2_RX)
321 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_TX)
322 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_WSTRNSNIC_RX)
323 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_L2_ZINWELL)
252 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX) 324 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
253 325
254 /* Customer private range */ 326 /* Customer private range */
@@ -265,9 +337,9 @@ static inline const char *cvmx_chip_type_to_string(enum
265{ 337{
266 switch (type) { 338 switch (type) {
267 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL) 339 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
268 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED) 340 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
269 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE) 341 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
270 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX) 342 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
271 } 343 }
272 return "Unsupported Chip"; 344 return "Unsupported Chip";
273} 345}
diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
new file mode 100644
index 000000000000..614653b686a0
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
@@ -0,0 +1,617 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Support functions for managing command queues used for
31 * various hardware blocks.
32 *
33 * The common command queue infrastructure abstracts out the
34 * software necessary for adding to Octeon's chained queue
35 * structures. These structures are used for commands to the
36 * PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each
37 * hardware unit takes commands and CSRs of different types,
38 * they all use basic linked command buffers to store the
39 * pending request. In general, users of the CVMX API don't
40 * call cvmx-cmd-queue functions directly. Instead the hardware
41 * unit specific wrapper should be used. The wrappers perform
42 * unit specific validation and CSR writes to submit the
43 * commands.
44 *
45 * Even though most software will never directly interact with
46 * cvmx-cmd-queue, knowledge of its internal working can help
47 * in diagnosing performance problems and help with debugging.
48 *
49 * Command queue pointers are stored in a global named block
50 * called "cvmx_cmd_queues". Except for the PKO queues, each
51 * hardware queue is stored in its own cache line to reduce SMP
52 * contention on spin locks. The PKO queues are stored such that
53 * every 16th queue is next to each other in memory. This scheme
54 * allows for queues being in separate cache lines when there
55 * are low number of queues per port. With 16 queues per port,
56 * the first queue for each port is in the same cache area. The
57 * second queues for each port are in another area, etc. This
58 * allows software to implement very efficient lockless PKO with
59 * 16 queues per port using a minimum of cache lines per core.
60 * All queues for a given core will be isolated in the same
61 * cache area.
62 *
63 * In addition to the memory pointer layout, cvmx-cmd-queue
64 * provides an optimized fair ll/sc locking mechanism for the
65 * queues. The lock uses a "ticket / now serving" model to
66 * maintain fair order on contended locks. In addition, it uses
67 * predicted locking time to limit cache contention. When a core
68 * know it must wait in line for a lock, it spins on the
69 * internal cycle counter to completely eliminate any causes of
70 * bus traffic.
71 *
72 */
73
74#ifndef __CVMX_CMD_QUEUE_H__
75#define __CVMX_CMD_QUEUE_H__
76
77#include <linux/prefetch.h>
78
79#include "cvmx-fpa.h"
80/**
81 * By default we disable the max depth support. Most programs
82 * don't use it and it slows down the command queue processing
83 * significantly.
84 */
85#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH
86#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0
87#endif
88
89/**
90 * Enumeration representing all hardware blocks that use command
91 * queues. Each hardware block has up to 65536 sub identifiers for
92 * multiple command queues. Not all chips support all hardware
93 * units.
94 */
95typedef enum {
96 CVMX_CMD_QUEUE_PKO_BASE = 0x00000,
97
98#define CVMX_CMD_QUEUE_PKO(queue) \
99 ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue))))
100
101 CVMX_CMD_QUEUE_ZIP = 0x10000,
102 CVMX_CMD_QUEUE_DFA = 0x20000,
103 CVMX_CMD_QUEUE_RAID = 0x30000,
104 CVMX_CMD_QUEUE_DMA_BASE = 0x40000,
105
106#define CVMX_CMD_QUEUE_DMA(queue) \
107 ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff&(queue))))
108
109 CVMX_CMD_QUEUE_END = 0x50000,
110} cvmx_cmd_queue_id_t;
111
112/**
113 * Command write operations can fail if the command queue needs
114 * a new buffer and the associated FPA pool is empty. It can also
115 * fail if the number of queued command words reaches the maximum
116 * set at initialization.
117 */
118typedef enum {
119 CVMX_CMD_QUEUE_SUCCESS = 0,
120 CVMX_CMD_QUEUE_NO_MEMORY = -1,
121 CVMX_CMD_QUEUE_FULL = -2,
122 CVMX_CMD_QUEUE_INVALID_PARAM = -3,
123 CVMX_CMD_QUEUE_ALREADY_SETUP = -4,
124} cvmx_cmd_queue_result_t;
125
126typedef struct {
127 /* You have lock when this is your ticket */
128 uint8_t now_serving;
129 uint64_t unused1:24;
130 /* Maximum outstanding command words */
131 uint32_t max_depth;
132 /* FPA pool buffers come from */
133 uint64_t fpa_pool:3;
134 /* Top of command buffer pointer shifted 7 */
135 uint64_t base_ptr_div128:29;
136 uint64_t unused2:6;
137 /* FPA buffer size in 64bit words minus 1 */
138 uint64_t pool_size_m1:13;
139 /* Number of commands already used in buffer */
140 uint64_t index:13;
141} __cvmx_cmd_queue_state_t;
142
143/**
144 * This structure contains the global state of all command queues.
145 * It is stored in a bootmem named block and shared by all
146 * applications running on Octeon. Tickets are stored in a differnet
147 * cahce line that queue information to reduce the contention on the
148 * ll/sc used to get a ticket. If this is not the case, the update
149 * of queue state causes the ll/sc to fail quite often.
150 */
151typedef struct {
152 uint64_t ticket[(CVMX_CMD_QUEUE_END >> 16) * 256];
153 __cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END >> 16) * 256];
154} __cvmx_cmd_queue_all_state_t;
155
156/**
157 * Initialize a command queue for use. The initial FPA buffer is
158 * allocated and the hardware unit is configured to point to the
159 * new command queue.
160 *
161 * @queue_id: Hardware command queue to initialize.
162 * @max_depth: Maximum outstanding commands that can be queued.
163 * @fpa_pool: FPA pool the command queues should come from.
164 * @pool_size: Size of each buffer in the FPA pool (bytes)
165 *
166 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
167 */
168cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
169 int max_depth, int fpa_pool,
170 int pool_size);
171
172/**
173 * Shutdown a queue a free it's command buffers to the FPA. The
174 * hardware connected to the queue must be stopped before this
175 * function is called.
176 *
177 * @queue_id: Queue to shutdown
178 *
179 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
180 */
181cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id);
182
183/**
184 * Return the number of command words pending in the queue. This
185 * function may be relatively slow for some hardware units.
186 *
187 * @queue_id: Hardware command queue to query
188 *
189 * Returns Number of outstanding commands
190 */
191int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
192
193/**
194 * Return the command buffer to be written to. The purpose of this
195 * function is to allow CVMX routine access t othe low level buffer
196 * for initial hardware setup. User applications should not call this
197 * function directly.
198 *
199 * @queue_id: Command queue to query
200 *
201 * Returns Command buffer or NULL on failure
202 */
203void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id);
204
205/**
206 * Get the index into the state arrays for the supplied queue id.
207 *
208 * @queue_id: Queue ID to get an index for
209 *
210 * Returns Index into the state arrays
211 */
212static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id)
213{
214 /*
215 * Warning: This code currently only works with devices that
216 * have 256 queues or less. Devices with more than 16 queues
217 * are laid out in memory to allow cores quick access to
218 * every 16th queue. This reduces cache thrashing when you are
219 * running 16 queues per port to support lockless operation.
220 */
221 int unit = queue_id >> 16;
222 int q = (queue_id >> 4) & 0xf;
223 int core = queue_id & 0xf;
224 return unit * 256 + core * 16 + q;
225}
226
227/**
228 * Lock the supplied queue so nobody else is updating it at the same
229 * time as us.
230 *
231 * @queue_id: Queue ID to lock
232 * @qptr: Pointer to the queue's global state
233 */
234static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id,
235 __cvmx_cmd_queue_state_t *qptr)
236{
237 extern __cvmx_cmd_queue_all_state_t
238 *__cvmx_cmd_queue_state_ptr;
239 int tmp;
240 int my_ticket;
241 prefetch(qptr);
242 asm volatile (
243 ".set push\n"
244 ".set noreorder\n"
245 "1:\n"
246 /* Atomic add one to ticket_ptr */
247 "ll %[my_ticket], %[ticket_ptr]\n"
248 /* and store the original value */
249 "li %[ticket], 1\n"
250 /* in my_ticket */
251 "baddu %[ticket], %[my_ticket]\n"
252 "sc %[ticket], %[ticket_ptr]\n"
253 "beqz %[ticket], 1b\n"
254 " nop\n"
255 /* Load the current now_serving ticket */
256 "lbu %[ticket], %[now_serving]\n"
257 "2:\n"
258 /* Jump out if now_serving == my_ticket */
259 "beq %[ticket], %[my_ticket], 4f\n"
260 /* Find out how many tickets are in front of me */
261 " subu %[ticket], %[my_ticket], %[ticket]\n"
262 /* Use tickets in front of me minus one to delay */
263 "subu %[ticket], 1\n"
264 /* Delay will be ((tickets in front)-1)*32 loops */
265 "cins %[ticket], %[ticket], 5, 7\n"
266 "3:\n"
267 /* Loop here until our ticket might be up */
268 "bnez %[ticket], 3b\n"
269 " subu %[ticket], 1\n"
270 /* Jump back up to check out ticket again */
271 "b 2b\n"
272 /* Load the current now_serving ticket */
273 " lbu %[ticket], %[now_serving]\n"
274 "4:\n"
275 ".set pop\n" :
276 [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
277 [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp),
278 [my_ticket] "=r"(my_ticket)
279 );
280}
281
282/**
283 * Unlock the queue, flushing all writes.
284 *
285 * @qptr: Queue to unlock
286 */
287static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr)
288{
289 qptr->now_serving++;
290 CVMX_SYNCWS;
291}
292
293/**
294 * Get the queue state structure for the given queue id
295 *
296 * @queue_id: Queue id to get
297 *
298 * Returns Queue structure or NULL on failure
299 */
300static inline __cvmx_cmd_queue_state_t
301 *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id)
302{
303 extern __cvmx_cmd_queue_all_state_t
304 *__cvmx_cmd_queue_state_ptr;
305 return &__cvmx_cmd_queue_state_ptr->
306 state[__cvmx_cmd_queue_get_index(queue_id)];
307}
308
309/**
310 * Write an arbitrary number of command words to a command queue.
311 * This is a generic function; the fixed number of command word
312 * functions yield higher performance.
313 *
314 * @queue_id: Hardware command queue to write to
315 * @use_locking:
316 * Use internal locking to ensure exclusive access for queue
317 * updates. If you don't use this locking you must ensure
318 * exclusivity some other way. Locking is strongly recommended.
319 * @cmd_count: Number of command words to write
320 * @cmds: Array of commands to write
321 *
322 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
323 */
324static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t
325 queue_id,
326 int use_locking,
327 int cmd_count,
328 uint64_t *cmds)
329{
330 __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
331
332 /* Make sure nobody else is updating the same queue */
333 if (likely(use_locking))
334 __cvmx_cmd_queue_lock(queue_id, qptr);
335
336 /*
337 * If a max queue length was specified then make sure we don't
338 * exceed it. If any part of the command would be below the
339 * limit we allow it.
340 */
341 if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
342 if (unlikely
343 (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
344 if (likely(use_locking))
345 __cvmx_cmd_queue_unlock(qptr);
346 return CVMX_CMD_QUEUE_FULL;
347 }
348 }
349
350 /*
351 * Normally there is plenty of room in the current buffer for
352 * the command.
353 */
354 if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) {
355 uint64_t *ptr =
356 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
357 base_ptr_div128 << 7);
358 ptr += qptr->index;
359 qptr->index += cmd_count;
360 while (cmd_count--)
361 *ptr++ = *cmds++;
362 } else {
363 uint64_t *ptr;
364 int count;
365 /*
366 * We need a new command buffer. Fail if there isn't
367 * one available.
368 */
369 uint64_t *new_buffer =
370 (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
371 if (unlikely(new_buffer == NULL)) {
372 if (likely(use_locking))
373 __cvmx_cmd_queue_unlock(qptr);
374 return CVMX_CMD_QUEUE_NO_MEMORY;
375 }
376 ptr =
377 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
378 base_ptr_div128 << 7);
379 /*
380 * Figure out how many command words will fit in this
381 * buffer. One location will be needed for the next
382 * buffer pointer.
383 */
384 count = qptr->pool_size_m1 - qptr->index;
385 ptr += qptr->index;
386 cmd_count -= count;
387 while (count--)
388 *ptr++ = *cmds++;
389 *ptr = cvmx_ptr_to_phys(new_buffer);
390 /*
391 * The current buffer is full and has a link to the
392 * next buffer. Time to write the rest of the commands
393 * into the new buffer.
394 */
395 qptr->base_ptr_div128 = *ptr >> 7;
396 qptr->index = cmd_count;
397 ptr = new_buffer;
398 while (cmd_count--)
399 *ptr++ = *cmds++;
400 }
401
402 /* All updates are complete. Release the lock and return */
403 if (likely(use_locking))
404 __cvmx_cmd_queue_unlock(qptr);
405 return CVMX_CMD_QUEUE_SUCCESS;
406}
407
408/**
409 * Simple function to write two command words to a command
410 * queue.
411 *
412 * @queue_id: Hardware command queue to write to
413 * @use_locking:
414 * Use internal locking to ensure exclusive access for queue
415 * updates. If you don't use this locking you must ensure
416 * exclusivity some other way. Locking is strongly recommended.
417 * @cmd1: Command
418 * @cmd2: Command
419 *
420 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
421 */
422static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t
423 queue_id,
424 int use_locking,
425 uint64_t cmd1,
426 uint64_t cmd2)
427{
428 __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
429
430 /* Make sure nobody else is updating the same queue */
431 if (likely(use_locking))
432 __cvmx_cmd_queue_lock(queue_id, qptr);
433
434 /*
435 * If a max queue length was specified then make sure we don't
436 * exceed it. If any part of the command would be below the
437 * limit we allow it.
438 */
439 if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
440 if (unlikely
441 (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
442 if (likely(use_locking))
443 __cvmx_cmd_queue_unlock(qptr);
444 return CVMX_CMD_QUEUE_FULL;
445 }
446 }
447
448 /*
449 * Normally there is plenty of room in the current buffer for
450 * the command.
451 */
452 if (likely(qptr->index + 2 < qptr->pool_size_m1)) {
453 uint64_t *ptr =
454 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
455 base_ptr_div128 << 7);
456 ptr += qptr->index;
457 qptr->index += 2;
458 ptr[0] = cmd1;
459 ptr[1] = cmd2;
460 } else {
461 uint64_t *ptr;
462 /*
463 * Figure out how many command words will fit in this
464 * buffer. One location will be needed for the next
465 * buffer pointer.
466 */
467 int count = qptr->pool_size_m1 - qptr->index;
468 /*
469 * We need a new command buffer. Fail if there isn't
470 * one available.
471 */
472 uint64_t *new_buffer =
473 (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
474 if (unlikely(new_buffer == NULL)) {
475 if (likely(use_locking))
476 __cvmx_cmd_queue_unlock(qptr);
477 return CVMX_CMD_QUEUE_NO_MEMORY;
478 }
479 count--;
480 ptr =
481 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
482 base_ptr_div128 << 7);
483 ptr += qptr->index;
484 *ptr++ = cmd1;
485 if (likely(count))
486 *ptr++ = cmd2;
487 *ptr = cvmx_ptr_to_phys(new_buffer);
488 /*
489 * The current buffer is full and has a link to the
490 * next buffer. Time to write the rest of the commands
491 * into the new buffer.
492 */
493 qptr->base_ptr_div128 = *ptr >> 7;
494 qptr->index = 0;
495 if (unlikely(count == 0)) {
496 qptr->index = 1;
497 new_buffer[0] = cmd2;
498 }
499 }
500
501 /* All updates are complete. Release the lock and return */
502 if (likely(use_locking))
503 __cvmx_cmd_queue_unlock(qptr);
504 return CVMX_CMD_QUEUE_SUCCESS;
505}
506
507/**
508 * Simple function to write three command words to a command
509 * queue.
510 *
511 * @queue_id: Hardware command queue to write to
512 * @use_locking:
513 * Use internal locking to ensure exclusive access for queue
514 * updates. If you don't use this locking you must ensure
515 * exclusivity some other way. Locking is strongly recommended.
516 * @cmd1: Command
517 * @cmd2: Command
518 * @cmd3: Command
519 *
520 * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
521 */
522static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t
523 queue_id,
524 int use_locking,
525 uint64_t cmd1,
526 uint64_t cmd2,
527 uint64_t cmd3)
528{
529 __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
530
531 /* Make sure nobody else is updating the same queue */
532 if (likely(use_locking))
533 __cvmx_cmd_queue_lock(queue_id, qptr);
534
535 /*
536 * If a max queue length was specified then make sure we don't
537 * exceed it. If any part of the command would be below the
538 * limit we allow it.
539 */
540 if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
541 if (unlikely
542 (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
543 if (likely(use_locking))
544 __cvmx_cmd_queue_unlock(qptr);
545 return CVMX_CMD_QUEUE_FULL;
546 }
547 }
548
549 /*
550 * Normally there is plenty of room in the current buffer for
551 * the command.
552 */
553 if (likely(qptr->index + 3 < qptr->pool_size_m1)) {
554 uint64_t *ptr =
555 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
556 base_ptr_div128 << 7);
557 ptr += qptr->index;
558 qptr->index += 3;
559 ptr[0] = cmd1;
560 ptr[1] = cmd2;
561 ptr[2] = cmd3;
562 } else {
563 uint64_t *ptr;
564 /*
565 * Figure out how many command words will fit in this
566 * buffer. One location will be needed for the next
567 * buffer pointer
568 */
569 int count = qptr->pool_size_m1 - qptr->index;
570 /*
571 * We need a new command buffer. Fail if there isn't
572 * one available
573 */
574 uint64_t *new_buffer =
575 (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
576 if (unlikely(new_buffer == NULL)) {
577 if (likely(use_locking))
578 __cvmx_cmd_queue_unlock(qptr);
579 return CVMX_CMD_QUEUE_NO_MEMORY;
580 }
581 count--;
582 ptr =
583 (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
584 base_ptr_div128 << 7);
585 ptr += qptr->index;
586 *ptr++ = cmd1;
587 if (count) {
588 *ptr++ = cmd2;
589 if (count > 1)
590 *ptr++ = cmd3;
591 }
592 *ptr = cvmx_ptr_to_phys(new_buffer);
593 /*
594 * The current buffer is full and has a link to the
595 * next buffer. Time to write the rest of the commands
596 * into the new buffer.
597 */
598 qptr->base_ptr_div128 = *ptr >> 7;
599 qptr->index = 0;
600 ptr = new_buffer;
601 if (count == 0) {
602 *ptr++ = cmd2;
603 qptr->index++;
604 }
605 if (count < 2) {
606 *ptr++ = cmd3;
607 qptr->index++;
608 }
609 }
610
611 /* All updates are complete. Release the lock and return */
612 if (likely(use_locking))
613 __cvmx_cmd_queue_unlock(qptr);
614 return CVMX_CMD_QUEUE_SUCCESS;
615}
616
617#endif /* __CVMX_CMD_QUEUE_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h
new file mode 100644
index 000000000000..26835d1b43b8
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-config.h
@@ -0,0 +1,168 @@
1#ifndef __CVMX_CONFIG_H__
2#define __CVMX_CONFIG_H__
3
4/************************* Config Specific Defines ************************/
5#define CVMX_LLM_NUM_PORTS 1
6#define CVMX_NULL_POINTER_PROTECT 1
7#define CVMX_ENABLE_DEBUG_PRINTS 1
8/* PKO queues per port for interface 0 (ports 0-15) */
9#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
10/* PKO queues per port for interface 1 (ports 16-31) */
11#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
12/* Limit on the number of PKO ports enabled for interface 0 */
13#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
14/* Limit on the number of PKO ports enabled for interface 1 */
15#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
16/* PKO queues per port for PCI (ports 32-35) */
17#define CVMX_PKO_QUEUES_PER_PORT_PCI 1
18/* PKO queues per port for Loop devices (ports 36-39) */
19#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1
20
21/************************* FPA allocation *********************************/
22/* Pool sizes in bytes, must be multiple of a cache line */
23#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
24#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
25#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
26#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
27#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
28#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
29#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
30#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
31
32/* Pools in use */
33/* Packet buffers */
34#define CVMX_FPA_PACKET_POOL (0)
35#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE
36/* Work queue entrys */
37#define CVMX_FPA_WQE_POOL (1)
38#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE
39/* PKO queue command buffers */
40#define CVMX_FPA_OUTPUT_BUFFER_POOL (2)
41#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE
42
43/************************* FAU allocation ********************************/
44/* The fetch and add registers are allocated here. They are arranged
45 * in order of descending size so that all alignment constraints are
46 * automatically met. The enums are linked so that the following enum
47 * continues allocating where the previous one left off, so the
48 * numbering within each enum always starts with zero. The macros
49 * take care of the address increment size, so the values entered
50 * always increase by 1. FAU registers are accessed with byte
51 * addresses.
52 */
53
54#define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START)
55typedef enum {
56 CVMX_FAU_REG_64_START = 0,
57 CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(0),
58} cvmx_fau_reg_64_t;
59
60#define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START)
61typedef enum {
62 CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END,
63 CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0),
64} cvmx_fau_reg_32_t;
65
66#define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START)
67typedef enum {
68 CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END,
69 CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0),
70} cvmx_fau_reg_16_t;
71
72#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START)
73typedef enum {
74 CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END,
75 CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0),
76} cvmx_fau_reg_8_t;
77
78/*
79 * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first
80 * available FAU address that is not allocated in cvmx-config.h. This
81 * is 64 bit aligned.
82 */
83#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL))
84#define CVMX_FAU_REG_END (2048)
85
86/********************** scratch memory allocation *************************/
87/* Scratchpad memory allocation. Note that these are byte memory
88 * addresses. Some uses of scratchpad (IOBDMA for example) require
89 * the use of 8-byte aligned addresses, so proper alignment needs to
90 * be taken into account.
91 */
92/* Generic scratch iobdma area */
93#define CVMX_SCR_SCRATCH (0)
94/* First location available after cvmx-config.h allocated region. */
95#define CVMX_SCR_REG_AVAIL_BASE (8)
96
97/*
98 * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve
99 * before the beginning of the packet. If necessary, override the
100 * default here. See the IPD section of the hardware manual for MBUFF
101 * SKIP details.
102 */
103#define CVMX_HELPER_FIRST_MBUFF_SKIP 184
104
105/*
106 * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve
107 * in each chained packet element. If necessary, override the default
108 * here.
109 */
110#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
111
112/*
113 * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is
114 * enabled for all input ports. This controls if IPD sends
115 * backpressure to all ports if Octeon's FPA pools don't have enough
116 * packet or work queue entries. Even when this is off, it is still
117 * possible to get backpressure from individual hardware ports. When
118 * configuring backpressure, also check
119 * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override
120 * the default here.
121 */
122#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
123
124/*
125 * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
126 * function. Once it is enabled the hardware starts accepting
127 * packets. You might want to skip the IPD enable if configuration
128 * changes are need from the default helper setup. If necessary,
129 * override the default here.
130 */
131#define CVMX_HELPER_ENABLE_IPD 0
132
133/*
134 * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
135 * to incoming packets.
136 */
137#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
138
139#define CVMX_ENABLE_PARAMETER_CHECKING 0
140
141/*
142 * The following select which fields are used by the PIP to generate
143 * the tag on INPUT
144 * 0: don't include
145 * 1: include
146 */
147#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0
148#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0
149#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0
150#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0
151#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0
152#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0
153#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0
154#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0
155#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0
156#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0
157#define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1
158
159/* Select skip mode for input ports */
160#define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2
161
162/*
163 * Force backpressure to be disabled. This overrides all other
164 * backpressure configuration.
165 */
166#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
167
168#endif /* __CVMX_CONFIG_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-dbg-defs.h b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
new file mode 100644
index 000000000000..abbf42d05e5a
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-dbg-defs.h
@@ -0,0 +1,72 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_DBG_DEFS_H__
29#define __CVMX_DBG_DEFS_H__
30
31#define CVMX_DBG_DATA \
32 CVMX_ADD_IO_SEG(0x00011F00000001E8ull)
33
34union cvmx_dbg_data {
35 uint64_t u64;
36 struct cvmx_dbg_data_s {
37 uint64_t reserved_23_63:41;
38 uint64_t c_mul:5;
39 uint64_t dsel_ext:1;
40 uint64_t data:17;
41 } s;
42 struct cvmx_dbg_data_cn30xx {
43 uint64_t reserved_31_63:33;
44 uint64_t pll_mul:3;
45 uint64_t reserved_23_27:5;
46 uint64_t c_mul:5;
47 uint64_t dsel_ext:1;
48 uint64_t data:17;
49 } cn30xx;
50 struct cvmx_dbg_data_cn30xx cn31xx;
51 struct cvmx_dbg_data_cn38xx {
52 uint64_t reserved_29_63:35;
53 uint64_t d_mul:4;
54 uint64_t dclk_mul2:1;
55 uint64_t cclk_div2:1;
56 uint64_t c_mul:5;
57 uint64_t dsel_ext:1;
58 uint64_t data:17;
59 } cn38xx;
60 struct cvmx_dbg_data_cn38xx cn38xxp2;
61 struct cvmx_dbg_data_cn30xx cn50xx;
62 struct cvmx_dbg_data_cn58xx {
63 uint64_t reserved_29_63:35;
64 uint64_t rem:6;
65 uint64_t c_mul:5;
66 uint64_t dsel_ext:1;
67 uint64_t data:17;
68 } cn58xx;
69 struct cvmx_dbg_data_cn58xx cn58xxp1;
70};
71
72#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
new file mode 100644
index 000000000000..c34ad04789ce
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
@@ -0,0 +1,643 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_DPI_DEFS_H__
29#define __CVMX_DPI_DEFS_H__
30
31#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
32#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
33#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
34#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
35#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
36#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
37#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
38#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
39#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
40#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
41#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
42#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
43#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
44#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
45#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
46#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
47#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
48#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
49#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
50#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
51#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
52#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
53#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
54#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
55#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
56#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
57#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
58#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
59
60union cvmx_dpi_bist_status {
61 uint64_t u64;
62 struct cvmx_dpi_bist_status_s {
63 uint64_t reserved_47_63:17;
64 uint64_t bist:47;
65 } s;
66 struct cvmx_dpi_bist_status_s cn61xx;
67 struct cvmx_dpi_bist_status_cn63xx {
68 uint64_t reserved_45_63:19;
69 uint64_t bist:45;
70 } cn63xx;
71 struct cvmx_dpi_bist_status_cn63xxp1 {
72 uint64_t reserved_37_63:27;
73 uint64_t bist:37;
74 } cn63xxp1;
75 struct cvmx_dpi_bist_status_s cn66xx;
76 struct cvmx_dpi_bist_status_cn63xx cn68xx;
77 struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
78};
79
80union cvmx_dpi_ctl {
81 uint64_t u64;
82 struct cvmx_dpi_ctl_s {
83 uint64_t reserved_2_63:62;
84 uint64_t clk:1;
85 uint64_t en:1;
86 } s;
87 struct cvmx_dpi_ctl_cn61xx {
88 uint64_t reserved_1_63:63;
89 uint64_t en:1;
90 } cn61xx;
91 struct cvmx_dpi_ctl_s cn63xx;
92 struct cvmx_dpi_ctl_s cn63xxp1;
93 struct cvmx_dpi_ctl_s cn66xx;
94 struct cvmx_dpi_ctl_s cn68xx;
95 struct cvmx_dpi_ctl_s cn68xxp1;
96};
97
98union cvmx_dpi_dmax_counts {
99 uint64_t u64;
100 struct cvmx_dpi_dmax_counts_s {
101 uint64_t reserved_39_63:25;
102 uint64_t fcnt:7;
103 uint64_t dbell:32;
104 } s;
105 struct cvmx_dpi_dmax_counts_s cn61xx;
106 struct cvmx_dpi_dmax_counts_s cn63xx;
107 struct cvmx_dpi_dmax_counts_s cn63xxp1;
108 struct cvmx_dpi_dmax_counts_s cn66xx;
109 struct cvmx_dpi_dmax_counts_s cn68xx;
110 struct cvmx_dpi_dmax_counts_s cn68xxp1;
111};
112
113union cvmx_dpi_dmax_dbell {
114 uint64_t u64;
115 struct cvmx_dpi_dmax_dbell_s {
116 uint64_t reserved_16_63:48;
117 uint64_t dbell:16;
118 } s;
119 struct cvmx_dpi_dmax_dbell_s cn61xx;
120 struct cvmx_dpi_dmax_dbell_s cn63xx;
121 struct cvmx_dpi_dmax_dbell_s cn63xxp1;
122 struct cvmx_dpi_dmax_dbell_s cn66xx;
123 struct cvmx_dpi_dmax_dbell_s cn68xx;
124 struct cvmx_dpi_dmax_dbell_s cn68xxp1;
125};
126
127union cvmx_dpi_dmax_err_rsp_status {
128 uint64_t u64;
129 struct cvmx_dpi_dmax_err_rsp_status_s {
130 uint64_t reserved_6_63:58;
131 uint64_t status:6;
132 } s;
133 struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
134 struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
135 struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
136 struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
137};
138
139union cvmx_dpi_dmax_ibuff_saddr {
140 uint64_t u64;
141 struct cvmx_dpi_dmax_ibuff_saddr_s {
142 uint64_t reserved_62_63:2;
143 uint64_t csize:14;
144 uint64_t reserved_41_47:7;
145 uint64_t idle:1;
146 uint64_t saddr:33;
147 uint64_t reserved_0_6:7;
148 } s;
149 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
150 uint64_t reserved_62_63:2;
151 uint64_t csize:14;
152 uint64_t reserved_41_47:7;
153 uint64_t idle:1;
154 uint64_t reserved_36_39:4;
155 uint64_t saddr:29;
156 uint64_t reserved_0_6:7;
157 } cn61xx;
158 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
159 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
160 struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
161 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
162 struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
163};
164
165union cvmx_dpi_dmax_iflight {
166 uint64_t u64;
167 struct cvmx_dpi_dmax_iflight_s {
168 uint64_t reserved_3_63:61;
169 uint64_t cnt:3;
170 } s;
171 struct cvmx_dpi_dmax_iflight_s cn61xx;
172 struct cvmx_dpi_dmax_iflight_s cn66xx;
173 struct cvmx_dpi_dmax_iflight_s cn68xx;
174 struct cvmx_dpi_dmax_iflight_s cn68xxp1;
175};
176
177union cvmx_dpi_dmax_naddr {
178 uint64_t u64;
179 struct cvmx_dpi_dmax_naddr_s {
180 uint64_t reserved_40_63:24;
181 uint64_t addr:40;
182 } s;
183 struct cvmx_dpi_dmax_naddr_cn61xx {
184 uint64_t reserved_36_63:28;
185 uint64_t addr:36;
186 } cn61xx;
187 struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
188 struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
189 struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
190 struct cvmx_dpi_dmax_naddr_s cn68xx;
191 struct cvmx_dpi_dmax_naddr_s cn68xxp1;
192};
193
194union cvmx_dpi_dmax_reqbnk0 {
195 uint64_t u64;
196 struct cvmx_dpi_dmax_reqbnk0_s {
197 uint64_t state:64;
198 } s;
199 struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
200 struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
201 struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
202 struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
203 struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
204 struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
205};
206
207union cvmx_dpi_dmax_reqbnk1 {
208 uint64_t u64;
209 struct cvmx_dpi_dmax_reqbnk1_s {
210 uint64_t state:64;
211 } s;
212 struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
213 struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
214 struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
215 struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
216 struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
217 struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
218};
219
220union cvmx_dpi_dma_control {
221 uint64_t u64;
222 struct cvmx_dpi_dma_control_s {
223 uint64_t reserved_62_63:2;
224 uint64_t dici_mode:1;
225 uint64_t pkt_en1:1;
226 uint64_t ffp_dis:1;
227 uint64_t commit_mode:1;
228 uint64_t pkt_hp:1;
229 uint64_t pkt_en:1;
230 uint64_t reserved_54_55:2;
231 uint64_t dma_enb:6;
232 uint64_t reserved_34_47:14;
233 uint64_t b0_lend:1;
234 uint64_t dwb_denb:1;
235 uint64_t dwb_ichk:9;
236 uint64_t fpa_que:3;
237 uint64_t o_add1:1;
238 uint64_t o_ro:1;
239 uint64_t o_ns:1;
240 uint64_t o_es:2;
241 uint64_t o_mode:1;
242 uint64_t reserved_0_13:14;
243 } s;
244 struct cvmx_dpi_dma_control_s cn61xx;
245 struct cvmx_dpi_dma_control_cn63xx {
246 uint64_t reserved_61_63:3;
247 uint64_t pkt_en1:1;
248 uint64_t ffp_dis:1;
249 uint64_t commit_mode:1;
250 uint64_t pkt_hp:1;
251 uint64_t pkt_en:1;
252 uint64_t reserved_54_55:2;
253 uint64_t dma_enb:6;
254 uint64_t reserved_34_47:14;
255 uint64_t b0_lend:1;
256 uint64_t dwb_denb:1;
257 uint64_t dwb_ichk:9;
258 uint64_t fpa_que:3;
259 uint64_t o_add1:1;
260 uint64_t o_ro:1;
261 uint64_t o_ns:1;
262 uint64_t o_es:2;
263 uint64_t o_mode:1;
264 uint64_t reserved_0_13:14;
265 } cn63xx;
266 struct cvmx_dpi_dma_control_cn63xxp1 {
267 uint64_t reserved_59_63:5;
268 uint64_t commit_mode:1;
269 uint64_t pkt_hp:1;
270 uint64_t pkt_en:1;
271 uint64_t reserved_54_55:2;
272 uint64_t dma_enb:6;
273 uint64_t reserved_34_47:14;
274 uint64_t b0_lend:1;
275 uint64_t dwb_denb:1;
276 uint64_t dwb_ichk:9;
277 uint64_t fpa_que:3;
278 uint64_t o_add1:1;
279 uint64_t o_ro:1;
280 uint64_t o_ns:1;
281 uint64_t o_es:2;
282 uint64_t o_mode:1;
283 uint64_t reserved_0_13:14;
284 } cn63xxp1;
285 struct cvmx_dpi_dma_control_cn63xx cn66xx;
286 struct cvmx_dpi_dma_control_s cn68xx;
287 struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
288};
289
290union cvmx_dpi_dma_engx_en {
291 uint64_t u64;
292 struct cvmx_dpi_dma_engx_en_s {
293 uint64_t reserved_8_63:56;
294 uint64_t qen:8;
295 } s;
296 struct cvmx_dpi_dma_engx_en_s cn61xx;
297 struct cvmx_dpi_dma_engx_en_s cn63xx;
298 struct cvmx_dpi_dma_engx_en_s cn63xxp1;
299 struct cvmx_dpi_dma_engx_en_s cn66xx;
300 struct cvmx_dpi_dma_engx_en_s cn68xx;
301 struct cvmx_dpi_dma_engx_en_s cn68xxp1;
302};
303
304union cvmx_dpi_dma_ppx_cnt {
305 uint64_t u64;
306 struct cvmx_dpi_dma_ppx_cnt_s {
307 uint64_t reserved_16_63:48;
308 uint64_t cnt:16;
309 } s;
310 struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
311 struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
312};
313
314union cvmx_dpi_engx_buf {
315 uint64_t u64;
316 struct cvmx_dpi_engx_buf_s {
317 uint64_t reserved_37_63:27;
318 uint64_t compblks:5;
319 uint64_t reserved_9_31:23;
320 uint64_t base:5;
321 uint64_t blks:4;
322 } s;
323 struct cvmx_dpi_engx_buf_s cn61xx;
324 struct cvmx_dpi_engx_buf_cn63xx {
325 uint64_t reserved_8_63:56;
326 uint64_t base:4;
327 uint64_t blks:4;
328 } cn63xx;
329 struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
330 struct cvmx_dpi_engx_buf_s cn66xx;
331 struct cvmx_dpi_engx_buf_s cn68xx;
332 struct cvmx_dpi_engx_buf_s cn68xxp1;
333};
334
335union cvmx_dpi_info_reg {
336 uint64_t u64;
337 struct cvmx_dpi_info_reg_s {
338 uint64_t reserved_8_63:56;
339 uint64_t ffp:4;
340 uint64_t reserved_2_3:2;
341 uint64_t ncb:1;
342 uint64_t rsl:1;
343 } s;
344 struct cvmx_dpi_info_reg_s cn61xx;
345 struct cvmx_dpi_info_reg_s cn63xx;
346 struct cvmx_dpi_info_reg_cn63xxp1 {
347 uint64_t reserved_2_63:62;
348 uint64_t ncb:1;
349 uint64_t rsl:1;
350 } cn63xxp1;
351 struct cvmx_dpi_info_reg_s cn66xx;
352 struct cvmx_dpi_info_reg_s cn68xx;
353 struct cvmx_dpi_info_reg_s cn68xxp1;
354};
355
356union cvmx_dpi_int_en {
357 uint64_t u64;
358 struct cvmx_dpi_int_en_s {
359 uint64_t reserved_28_63:36;
360 uint64_t sprt3_rst:1;
361 uint64_t sprt2_rst:1;
362 uint64_t sprt1_rst:1;
363 uint64_t sprt0_rst:1;
364 uint64_t reserved_23_23:1;
365 uint64_t req_badfil:1;
366 uint64_t req_inull:1;
367 uint64_t req_anull:1;
368 uint64_t req_undflw:1;
369 uint64_t req_ovrflw:1;
370 uint64_t req_badlen:1;
371 uint64_t req_badadr:1;
372 uint64_t dmadbo:8;
373 uint64_t reserved_2_7:6;
374 uint64_t nfovr:1;
375 uint64_t nderr:1;
376 } s;
377 struct cvmx_dpi_int_en_s cn61xx;
378 struct cvmx_dpi_int_en_cn63xx {
379 uint64_t reserved_26_63:38;
380 uint64_t sprt1_rst:1;
381 uint64_t sprt0_rst:1;
382 uint64_t reserved_23_23:1;
383 uint64_t req_badfil:1;
384 uint64_t req_inull:1;
385 uint64_t req_anull:1;
386 uint64_t req_undflw:1;
387 uint64_t req_ovrflw:1;
388 uint64_t req_badlen:1;
389 uint64_t req_badadr:1;
390 uint64_t dmadbo:8;
391 uint64_t reserved_2_7:6;
392 uint64_t nfovr:1;
393 uint64_t nderr:1;
394 } cn63xx;
395 struct cvmx_dpi_int_en_cn63xx cn63xxp1;
396 struct cvmx_dpi_int_en_s cn66xx;
397 struct cvmx_dpi_int_en_cn63xx cn68xx;
398 struct cvmx_dpi_int_en_cn63xx cn68xxp1;
399};
400
401union cvmx_dpi_int_reg {
402 uint64_t u64;
403 struct cvmx_dpi_int_reg_s {
404 uint64_t reserved_28_63:36;
405 uint64_t sprt3_rst:1;
406 uint64_t sprt2_rst:1;
407 uint64_t sprt1_rst:1;
408 uint64_t sprt0_rst:1;
409 uint64_t reserved_23_23:1;
410 uint64_t req_badfil:1;
411 uint64_t req_inull:1;
412 uint64_t req_anull:1;
413 uint64_t req_undflw:1;
414 uint64_t req_ovrflw:1;
415 uint64_t req_badlen:1;
416 uint64_t req_badadr:1;
417 uint64_t dmadbo:8;
418 uint64_t reserved_2_7:6;
419 uint64_t nfovr:1;
420 uint64_t nderr:1;
421 } s;
422 struct cvmx_dpi_int_reg_s cn61xx;
423 struct cvmx_dpi_int_reg_cn63xx {
424 uint64_t reserved_26_63:38;
425 uint64_t sprt1_rst:1;
426 uint64_t sprt0_rst:1;
427 uint64_t reserved_23_23:1;
428 uint64_t req_badfil:1;
429 uint64_t req_inull:1;
430 uint64_t req_anull:1;
431 uint64_t req_undflw:1;
432 uint64_t req_ovrflw:1;
433 uint64_t req_badlen:1;
434 uint64_t req_badadr:1;
435 uint64_t dmadbo:8;
436 uint64_t reserved_2_7:6;
437 uint64_t nfovr:1;
438 uint64_t nderr:1;
439 } cn63xx;
440 struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
441 struct cvmx_dpi_int_reg_s cn66xx;
442 struct cvmx_dpi_int_reg_cn63xx cn68xx;
443 struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
444};
445
446union cvmx_dpi_ncbx_cfg {
447 uint64_t u64;
448 struct cvmx_dpi_ncbx_cfg_s {
449 uint64_t reserved_6_63:58;
450 uint64_t molr:6;
451 } s;
452 struct cvmx_dpi_ncbx_cfg_s cn61xx;
453 struct cvmx_dpi_ncbx_cfg_s cn66xx;
454 struct cvmx_dpi_ncbx_cfg_s cn68xx;
455};
456
457union cvmx_dpi_pint_info {
458 uint64_t u64;
459 struct cvmx_dpi_pint_info_s {
460 uint64_t reserved_14_63:50;
461 uint64_t iinfo:6;
462 uint64_t reserved_6_7:2;
463 uint64_t sinfo:6;
464 } s;
465 struct cvmx_dpi_pint_info_s cn61xx;
466 struct cvmx_dpi_pint_info_s cn63xx;
467 struct cvmx_dpi_pint_info_s cn63xxp1;
468 struct cvmx_dpi_pint_info_s cn66xx;
469 struct cvmx_dpi_pint_info_s cn68xx;
470 struct cvmx_dpi_pint_info_s cn68xxp1;
471};
472
473union cvmx_dpi_pkt_err_rsp {
474 uint64_t u64;
475 struct cvmx_dpi_pkt_err_rsp_s {
476 uint64_t reserved_1_63:63;
477 uint64_t pkterr:1;
478 } s;
479 struct cvmx_dpi_pkt_err_rsp_s cn61xx;
480 struct cvmx_dpi_pkt_err_rsp_s cn63xx;
481 struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
482 struct cvmx_dpi_pkt_err_rsp_s cn66xx;
483 struct cvmx_dpi_pkt_err_rsp_s cn68xx;
484 struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
485};
486
487union cvmx_dpi_req_err_rsp {
488 uint64_t u64;
489 struct cvmx_dpi_req_err_rsp_s {
490 uint64_t reserved_8_63:56;
491 uint64_t qerr:8;
492 } s;
493 struct cvmx_dpi_req_err_rsp_s cn61xx;
494 struct cvmx_dpi_req_err_rsp_s cn63xx;
495 struct cvmx_dpi_req_err_rsp_s cn63xxp1;
496 struct cvmx_dpi_req_err_rsp_s cn66xx;
497 struct cvmx_dpi_req_err_rsp_s cn68xx;
498 struct cvmx_dpi_req_err_rsp_s cn68xxp1;
499};
500
501union cvmx_dpi_req_err_rsp_en {
502 uint64_t u64;
503 struct cvmx_dpi_req_err_rsp_en_s {
504 uint64_t reserved_8_63:56;
505 uint64_t en:8;
506 } s;
507 struct cvmx_dpi_req_err_rsp_en_s cn61xx;
508 struct cvmx_dpi_req_err_rsp_en_s cn63xx;
509 struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
510 struct cvmx_dpi_req_err_rsp_en_s cn66xx;
511 struct cvmx_dpi_req_err_rsp_en_s cn68xx;
512 struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
513};
514
515union cvmx_dpi_req_err_rst {
516 uint64_t u64;
517 struct cvmx_dpi_req_err_rst_s {
518 uint64_t reserved_8_63:56;
519 uint64_t qerr:8;
520 } s;
521 struct cvmx_dpi_req_err_rst_s cn61xx;
522 struct cvmx_dpi_req_err_rst_s cn63xx;
523 struct cvmx_dpi_req_err_rst_s cn63xxp1;
524 struct cvmx_dpi_req_err_rst_s cn66xx;
525 struct cvmx_dpi_req_err_rst_s cn68xx;
526 struct cvmx_dpi_req_err_rst_s cn68xxp1;
527};
528
529union cvmx_dpi_req_err_rst_en {
530 uint64_t u64;
531 struct cvmx_dpi_req_err_rst_en_s {
532 uint64_t reserved_8_63:56;
533 uint64_t en:8;
534 } s;
535 struct cvmx_dpi_req_err_rst_en_s cn61xx;
536 struct cvmx_dpi_req_err_rst_en_s cn63xx;
537 struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
538 struct cvmx_dpi_req_err_rst_en_s cn66xx;
539 struct cvmx_dpi_req_err_rst_en_s cn68xx;
540 struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
541};
542
543union cvmx_dpi_req_err_skip_comp {
544 uint64_t u64;
545 struct cvmx_dpi_req_err_skip_comp_s {
546 uint64_t reserved_24_63:40;
547 uint64_t en_rst:8;
548 uint64_t reserved_8_15:8;
549 uint64_t en_rsp:8;
550 } s;
551 struct cvmx_dpi_req_err_skip_comp_s cn61xx;
552 struct cvmx_dpi_req_err_skip_comp_s cn66xx;
553 struct cvmx_dpi_req_err_skip_comp_s cn68xx;
554 struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
555};
556
557union cvmx_dpi_req_gbl_en {
558 uint64_t u64;
559 struct cvmx_dpi_req_gbl_en_s {
560 uint64_t reserved_8_63:56;
561 uint64_t qen:8;
562 } s;
563 struct cvmx_dpi_req_gbl_en_s cn61xx;
564 struct cvmx_dpi_req_gbl_en_s cn63xx;
565 struct cvmx_dpi_req_gbl_en_s cn63xxp1;
566 struct cvmx_dpi_req_gbl_en_s cn66xx;
567 struct cvmx_dpi_req_gbl_en_s cn68xx;
568 struct cvmx_dpi_req_gbl_en_s cn68xxp1;
569};
570
571union cvmx_dpi_sli_prtx_cfg {
572 uint64_t u64;
573 struct cvmx_dpi_sli_prtx_cfg_s {
574 uint64_t reserved_25_63:39;
575 uint64_t halt:1;
576 uint64_t qlm_cfg:4;
577 uint64_t reserved_17_19:3;
578 uint64_t rd_mode:1;
579 uint64_t reserved_14_15:2;
580 uint64_t molr:6;
581 uint64_t mps_lim:1;
582 uint64_t reserved_5_6:2;
583 uint64_t mps:1;
584 uint64_t mrrs_lim:1;
585 uint64_t reserved_2_2:1;
586 uint64_t mrrs:2;
587 } s;
588 struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
589 struct cvmx_dpi_sli_prtx_cfg_cn63xx {
590 uint64_t reserved_25_63:39;
591 uint64_t halt:1;
592 uint64_t reserved_21_23:3;
593 uint64_t qlm_cfg:1;
594 uint64_t reserved_17_19:3;
595 uint64_t rd_mode:1;
596 uint64_t reserved_14_15:2;
597 uint64_t molr:6;
598 uint64_t mps_lim:1;
599 uint64_t reserved_5_6:2;
600 uint64_t mps:1;
601 uint64_t mrrs_lim:1;
602 uint64_t reserved_2_2:1;
603 uint64_t mrrs:2;
604 } cn63xx;
605 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
606 struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
607 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
608 struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
609};
610
611union cvmx_dpi_sli_prtx_err {
612 uint64_t u64;
613 struct cvmx_dpi_sli_prtx_err_s {
614 uint64_t addr:61;
615 uint64_t reserved_0_2:3;
616 } s;
617 struct cvmx_dpi_sli_prtx_err_s cn61xx;
618 struct cvmx_dpi_sli_prtx_err_s cn63xx;
619 struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
620 struct cvmx_dpi_sli_prtx_err_s cn66xx;
621 struct cvmx_dpi_sli_prtx_err_s cn68xx;
622 struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
623};
624
625union cvmx_dpi_sli_prtx_err_info {
626 uint64_t u64;
627 struct cvmx_dpi_sli_prtx_err_info_s {
628 uint64_t reserved_9_63:55;
629 uint64_t lock:1;
630 uint64_t reserved_5_7:3;
631 uint64_t type:1;
632 uint64_t reserved_3_3:1;
633 uint64_t reqq:3;
634 } s;
635 struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
636 struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
637 struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
638 struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
639 struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
640 struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
641};
642
643#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h
new file mode 100644
index 000000000000..a6939fc8ba18
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-fau.h
@@ -0,0 +1,597 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Interface to the hardware Fetch and Add Unit.
30 */
31
32#ifndef __CVMX_FAU_H__
33#define __CVMX_FAU_H__
34
35/*
36 * Octeon Fetch and Add Unit (FAU)
37 */
38
39#define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0)
40#define CVMX_FAU_BITS_SCRADDR 63, 56
41#define CVMX_FAU_BITS_LEN 55, 48
42#define CVMX_FAU_BITS_INEVAL 35, 14
43#define CVMX_FAU_BITS_TAGWAIT 13, 13
44#define CVMX_FAU_BITS_NOADD 13, 13
45#define CVMX_FAU_BITS_SIZE 12, 11
46#define CVMX_FAU_BITS_REGISTER 10, 0
47
48typedef enum {
49 CVMX_FAU_OP_SIZE_8 = 0,
50 CVMX_FAU_OP_SIZE_16 = 1,
51 CVMX_FAU_OP_SIZE_32 = 2,
52 CVMX_FAU_OP_SIZE_64 = 3
53} cvmx_fau_op_size_t;
54
55/**
56 * Tagwait return definition. If a timeout occurs, the error
57 * bit will be set. Otherwise the value of the register before
58 * the update will be returned.
59 */
60typedef struct {
61 uint64_t error:1;
62 int64_t value:63;
63} cvmx_fau_tagwait64_t;
64
65/**
66 * Tagwait return definition. If a timeout occurs, the error
67 * bit will be set. Otherwise the value of the register before
68 * the update will be returned.
69 */
70typedef struct {
71 uint64_t error:1;
72 int32_t value:31;
73} cvmx_fau_tagwait32_t;
74
75/**
76 * Tagwait return definition. If a timeout occurs, the error
77 * bit will be set. Otherwise the value of the register before
78 * the update will be returned.
79 */
80typedef struct {
81 uint64_t error:1;
82 int16_t value:15;
83} cvmx_fau_tagwait16_t;
84
85/**
86 * Tagwait return definition. If a timeout occurs, the error
87 * bit will be set. Otherwise the value of the register before
88 * the update will be returned.
89 */
90typedef struct {
91 uint64_t error:1;
92 int8_t value:7;
93} cvmx_fau_tagwait8_t;
94
95/**
96 * Asynchronous tagwait return definition. If a timeout occurs,
97 * the error bit will be set. Otherwise the value of the
98 * register before the update will be returned.
99 */
100typedef union {
101 uint64_t u64;
102 struct {
103 uint64_t invalid:1;
104 uint64_t data:63; /* unpredictable if invalid is set */
105 } s;
106} cvmx_fau_async_tagwait_result_t;
107
108/**
109 * Builds a store I/O address for writing to the FAU
110 *
111 * @noadd: 0 = Store value is atomically added to the current value
112 * 1 = Store value is atomically written over the current value
113 * @reg: FAU atomic register to access. 0 <= reg < 2048.
114 * - Step by 2 for 16 bit access.
115 * - Step by 4 for 32 bit access.
116 * - Step by 8 for 64 bit access.
117 * Returns Address to store for atomic update
118 */
119static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
120{
121 return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
122 cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) |
123 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
124}
125
126/**
127 * Builds a I/O address for accessing the FAU
128 *
129 * @tagwait: Should the atomic add wait for the current tag switch
130 * operation to complete.
131 * - 0 = Don't wait
132 * - 1 = Wait for tag switch to complete
133 * @reg: FAU atomic register to access. 0 <= reg < 2048.
134 * - Step by 2 for 16 bit access.
135 * - Step by 4 for 32 bit access.
136 * - Step by 8 for 64 bit access.
137 * @value: Signed value to add.
138 * Note: When performing 32 and 64 bit access, only the low
139 * 22 bits are available.
140 * Returns Address to read from for atomic update
141 */
142static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg,
143 int64_t value)
144{
145 return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
146 cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
147 cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
148 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
149}
150
151/**
152 * Perform an atomic 64 bit add
153 *
154 * @reg: FAU atomic register to access. 0 <= reg < 2048.
155 * - Step by 8 for 64 bit access.
156 * @value: Signed value to add.
157 * Note: Only the low 22 bits are available.
158 * Returns Value of the register before the update
159 */
160static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
161 int64_t value)
162{
163 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value));
164}
165
166/**
167 * Perform an atomic 32 bit add
168 *
169 * @reg: FAU atomic register to access. 0 <= reg < 2048.
170 * - Step by 4 for 32 bit access.
171 * @value: Signed value to add.
172 * Note: Only the low 22 bits are available.
173 * Returns Value of the register before the update
174 */
175static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
176 int32_t value)
177{
178 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
179}
180
181/**
182 * Perform an atomic 16 bit add
183 *
184 * @reg: FAU atomic register to access. 0 <= reg < 2048.
185 * - Step by 2 for 16 bit access.
186 * @value: Signed value to add.
187 * Returns Value of the register before the update
188 */
189static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
190 int16_t value)
191{
192 return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
193}
194
195/**
196 * Perform an atomic 8 bit add
197 *
198 * @reg: FAU atomic register to access. 0 <= reg < 2048.
199 * @value: Signed value to add.
200 * Returns Value of the register before the update
201 */
202static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
203{
204 return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
205}
206
207/**
208 * Perform an atomic 64 bit add after the current tag switch
209 * completes
210 *
211 * @reg: FAU atomic register to access. 0 <= reg < 2048.
212 * - Step by 8 for 64 bit access.
213 * @value: Signed value to add.
214 * Note: Only the low 22 bits are available.
215 * Returns If a timeout occurs, the error bit will be set. Otherwise
216 * the value of the register before the update will be
217 * returned
218 */
219static inline cvmx_fau_tagwait64_t
220cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
221{
222 union {
223 uint64_t i64;
224 cvmx_fau_tagwait64_t t;
225 } result;
226 result.i64 =
227 cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value));
228 return result.t;
229}
230
231/**
232 * Perform an atomic 32 bit add after the current tag switch
233 * completes
234 *
235 * @reg: FAU atomic register to access. 0 <= reg < 2048.
236 * - Step by 4 for 32 bit access.
237 * @value: Signed value to add.
238 * Note: Only the low 22 bits are available.
239 * Returns If a timeout occurs, the error bit will be set. Otherwise
240 * the value of the register before the update will be
241 * returned
242 */
243static inline cvmx_fau_tagwait32_t
244cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
245{
246 union {
247 uint64_t i32;
248 cvmx_fau_tagwait32_t t;
249 } result;
250 result.i32 =
251 cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
252 return result.t;
253}
254
255/**
256 * Perform an atomic 16 bit add after the current tag switch
257 * completes
258 *
259 * @reg: FAU atomic register to access. 0 <= reg < 2048.
260 * - Step by 2 for 16 bit access.
261 * @value: Signed value to add.
262 * Returns If a timeout occurs, the error bit will be set. Otherwise
263 * the value of the register before the update will be
264 * returned
265 */
266static inline cvmx_fau_tagwait16_t
267cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
268{
269 union {
270 uint64_t i16;
271 cvmx_fau_tagwait16_t t;
272 } result;
273 result.i16 =
274 cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
275 return result.t;
276}
277
278/**
279 * Perform an atomic 8 bit add after the current tag switch
280 * completes
281 *
282 * @reg: FAU atomic register to access. 0 <= reg < 2048.
283 * @value: Signed value to add.
284 * Returns If a timeout occurs, the error bit will be set. Otherwise
285 * the value of the register before the update will be
286 * returned
287 */
288static inline cvmx_fau_tagwait8_t
289cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
290{
291 union {
292 uint64_t i8;
293 cvmx_fau_tagwait8_t t;
294 } result;
295 result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
296 return result.t;
297}
298
299/**
300 * Builds I/O data for async operations
301 *
302 * @scraddr: Scratch pad byte address to write to. Must be 8 byte aligned
303 * @value: Signed value to add.
304 * Note: When performing 32 and 64 bit access, only the low
305 * 22 bits are available.
306 * @tagwait: Should the atomic add wait for the current tag switch
307 * operation to complete.
308 * - 0 = Don't wait
309 * - 1 = Wait for tag switch to complete
310 * @size: The size of the operation:
311 * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits
312 * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
313 * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
314 * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
315 * @reg: FAU atomic register to access. 0 <= reg < 2048.
316 * - Step by 2 for 16 bit access.
317 * - Step by 4 for 32 bit access.
318 * - Step by 8 for 64 bit access.
319 * Returns Data to write using cvmx_send_single
320 */
321static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value,
322 uint64_t tagwait,
323 cvmx_fau_op_size_t size,
324 uint64_t reg)
325{
326 return CVMX_FAU_LOAD_IO_ADDRESS |
327 cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) |
328 cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) |
329 cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
330 cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
331 cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) |
332 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
333}
334
335/**
336 * Perform an async atomic 64 bit add. The old value is
337 * placed in the scratch memory at byte address scraddr.
338 *
339 * @scraddr: Scratch memory byte address to put response in.
340 * Must be 8 byte aligned.
341 * @reg: FAU atomic register to access. 0 <= reg < 2048.
342 * - Step by 8 for 64 bit access.
343 * @value: Signed value to add.
344 * Note: Only the low 22 bits are available.
345 * Returns Placed in the scratch pad register
346 */
347static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr,
348 cvmx_fau_reg_64_t reg,
349 int64_t value)
350{
351 cvmx_send_single(__cvmx_fau_iobdma_data
352 (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
353}
354
355/**
356 * Perform an async atomic 32 bit add. The old value is
357 * placed in the scratch memory at byte address scraddr.
358 *
359 * @scraddr: Scratch memory byte address to put response in.
360 * Must be 8 byte aligned.
361 * @reg: FAU atomic register to access. 0 <= reg < 2048.
362 * - Step by 4 for 32 bit access.
363 * @value: Signed value to add.
364 * Note: Only the low 22 bits are available.
365 * Returns Placed in the scratch pad register
366 */
367static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
368 cvmx_fau_reg_32_t reg,
369 int32_t value)
370{
371 cvmx_send_single(__cvmx_fau_iobdma_data
372 (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
373}
374
375/**
376 * Perform an async atomic 16 bit add. The old value is
377 * placed in the scratch memory at byte address scraddr.
378 *
379 * @scraddr: Scratch memory byte address to put response in.
380 * Must be 8 byte aligned.
381 * @reg: FAU atomic register to access. 0 <= reg < 2048.
382 * - Step by 2 for 16 bit access.
383 * @value: Signed value to add.
384 * Returns Placed in the scratch pad register
385 */
386static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr,
387 cvmx_fau_reg_16_t reg,
388 int16_t value)
389{
390 cvmx_send_single(__cvmx_fau_iobdma_data
391 (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
392}
393
394/**
395 * Perform an async atomic 8 bit add. The old value is
396 * placed in the scratch memory at byte address scraddr.
397 *
398 * @scraddr: Scratch memory byte address to put response in.
399 * Must be 8 byte aligned.
400 * @reg: FAU atomic register to access. 0 <= reg < 2048.
401 * @value: Signed value to add.
402 * Returns Placed in the scratch pad register
403 */
404static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr,
405 cvmx_fau_reg_8_t reg,
406 int8_t value)
407{
408 cvmx_send_single(__cvmx_fau_iobdma_data
409 (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
410}
411
412/**
413 * Perform an async atomic 64 bit add after the current tag
414 * switch completes.
415 *
416 * @scraddr: Scratch memory byte address to put response in. Must be
417 * 8 byte aligned. If a timeout occurs, the error bit (63)
418 * will be set. Otherwise the value of the register before
419 * the update will be returned
420 *
421 * @reg: FAU atomic register to access. 0 <= reg < 2048.
422 * - Step by 8 for 64 bit access.
423 * @value: Signed value to add.
424 * Note: Only the low 22 bits are available.
425 * Returns Placed in the scratch pad register
426 */
427static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr,
428 cvmx_fau_reg_64_t reg,
429 int64_t value)
430{
431 cvmx_send_single(__cvmx_fau_iobdma_data
432 (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
433}
434
435/**
436 * Perform an async atomic 32 bit add after the current tag
437 * switch completes.
438 *
439 * @scraddr: Scratch memory byte address to put response in. Must be
440 * 8 byte aligned. If a timeout occurs, the error bit (63)
441 * will be set. Otherwise the value of the register before
442 * the update will be returned
443 *
444 * @reg: FAU atomic register to access. 0 <= reg < 2048.
445 * - Step by 4 for 32 bit access.
446 * @value: Signed value to add.
447 * Note: Only the low 22 bits are available.
448 * Returns Placed in the scratch pad register
449 */
450static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr,
451 cvmx_fau_reg_32_t reg,
452 int32_t value)
453{
454 cvmx_send_single(__cvmx_fau_iobdma_data
455 (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
456}
457
458/**
459 * Perform an async atomic 16 bit add after the current tag
460 * switch completes.
461 *
462 * @scraddr: Scratch memory byte address to put response in. Must be
463 * 8 byte aligned. If a timeout occurs, the error bit (63)
464 * will be set. Otherwise the value of the register before
465 * the update will be returned
466 *
467 * @reg: FAU atomic register to access. 0 <= reg < 2048.
468 * - Step by 2 for 16 bit access.
469 * @value: Signed value to add.
470 *
471 * Returns Placed in the scratch pad register
472 */
473static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr,
474 cvmx_fau_reg_16_t reg,
475 int16_t value)
476{
477 cvmx_send_single(__cvmx_fau_iobdma_data
478 (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
479}
480
481/**
482 * Perform an async atomic 8 bit add after the current tag
483 * switch completes.
484 *
485 * @scraddr: Scratch memory byte address to put response in. Must be
486 * 8 byte aligned. If a timeout occurs, the error bit (63)
487 * will be set. Otherwise the value of the register before
488 * the update will be returned
489 *
490 * @reg: FAU atomic register to access. 0 <= reg < 2048.
491 * @value: Signed value to add.
492 *
493 * Returns Placed in the scratch pad register
494 */
495static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr,
496 cvmx_fau_reg_8_t reg,
497 int8_t value)
498{
499 cvmx_send_single(__cvmx_fau_iobdma_data
500 (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
501}
502
503/**
504 * Perform an atomic 64 bit add
505 *
506 * @reg: FAU atomic register to access. 0 <= reg < 2048.
507 * - Step by 8 for 64 bit access.
508 * @value: Signed value to add.
509 */
510static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
511{
512 cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value);
513}
514
515/**
516 * Perform an atomic 32 bit add
517 *
518 * @reg: FAU atomic register to access. 0 <= reg < 2048.
519 * - Step by 4 for 32 bit access.
520 * @value: Signed value to add.
521 */
522static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
523{
524 cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
525}
526
527/**
528 * Perform an atomic 16 bit add
529 *
530 * @reg: FAU atomic register to access. 0 <= reg < 2048.
531 * - Step by 2 for 16 bit access.
532 * @value: Signed value to add.
533 */
534static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
535{
536 cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
537}
538
539/**
540 * Perform an atomic 8 bit add
541 *
542 * @reg: FAU atomic register to access. 0 <= reg < 2048.
543 * @value: Signed value to add.
544 */
545static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
546{
547 cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
548}
549
550/**
551 * Perform an atomic 64 bit write
552 *
553 * @reg: FAU atomic register to access. 0 <= reg < 2048.
554 * - Step by 8 for 64 bit access.
555 * @value: Signed value to write.
556 */
557static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
558{
559 cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value);
560}
561
562/**
563 * Perform an atomic 32 bit write
564 *
565 * @reg: FAU atomic register to access. 0 <= reg < 2048.
566 * - Step by 4 for 32 bit access.
567 * @value: Signed value to write.
568 */
569static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
570{
571 cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
572}
573
574/**
575 * Perform an atomic 16 bit write
576 *
577 * @reg: FAU atomic register to access. 0 <= reg < 2048.
578 * - Step by 2 for 16 bit access.
579 * @value: Signed value to write.
580 */
581static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
582{
583 cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
584}
585
586/**
587 * Perform an atomic 8 bit write
588 *
589 * @reg: FAU atomic register to access. 0 <= reg < 2048.
590 * @value: Signed value to write.
591 */
592static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
593{
594 cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);
595}
596
597#endif /* __CVMX_FAU_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa-defs.h b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
new file mode 100644
index 000000000000..bf5546b90110
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-fpa-defs.h
@@ -0,0 +1,403 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_FPA_DEFS_H__
29#define __CVMX_FPA_DEFS_H__
30
31#define CVMX_FPA_BIST_STATUS \
32 CVMX_ADD_IO_SEG(0x00011800280000E8ull)
33#define CVMX_FPA_CTL_STATUS \
34 CVMX_ADD_IO_SEG(0x0001180028000050ull)
35#define CVMX_FPA_FPF0_MARKS \
36 CVMX_ADD_IO_SEG(0x0001180028000000ull)
37#define CVMX_FPA_FPF0_SIZE \
38 CVMX_ADD_IO_SEG(0x0001180028000058ull)
39#define CVMX_FPA_FPF1_MARKS \
40 CVMX_ADD_IO_SEG(0x0001180028000008ull)
41#define CVMX_FPA_FPF2_MARKS \
42 CVMX_ADD_IO_SEG(0x0001180028000010ull)
43#define CVMX_FPA_FPF3_MARKS \
44 CVMX_ADD_IO_SEG(0x0001180028000018ull)
45#define CVMX_FPA_FPF4_MARKS \
46 CVMX_ADD_IO_SEG(0x0001180028000020ull)
47#define CVMX_FPA_FPF5_MARKS \
48 CVMX_ADD_IO_SEG(0x0001180028000028ull)
49#define CVMX_FPA_FPF6_MARKS \
50 CVMX_ADD_IO_SEG(0x0001180028000030ull)
51#define CVMX_FPA_FPF7_MARKS \
52 CVMX_ADD_IO_SEG(0x0001180028000038ull)
53#define CVMX_FPA_FPFX_MARKS(offset) \
54 CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1)
55#define CVMX_FPA_FPFX_SIZE(offset) \
56 CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1)
57#define CVMX_FPA_INT_ENB \
58 CVMX_ADD_IO_SEG(0x0001180028000048ull)
59#define CVMX_FPA_INT_SUM \
60 CVMX_ADD_IO_SEG(0x0001180028000040ull)
61#define CVMX_FPA_QUE0_PAGE_INDEX \
62 CVMX_ADD_IO_SEG(0x00011800280000F0ull)
63#define CVMX_FPA_QUE1_PAGE_INDEX \
64 CVMX_ADD_IO_SEG(0x00011800280000F8ull)
65#define CVMX_FPA_QUE2_PAGE_INDEX \
66 CVMX_ADD_IO_SEG(0x0001180028000100ull)
67#define CVMX_FPA_QUE3_PAGE_INDEX \
68 CVMX_ADD_IO_SEG(0x0001180028000108ull)
69#define CVMX_FPA_QUE4_PAGE_INDEX \
70 CVMX_ADD_IO_SEG(0x0001180028000110ull)
71#define CVMX_FPA_QUE5_PAGE_INDEX \
72 CVMX_ADD_IO_SEG(0x0001180028000118ull)
73#define CVMX_FPA_QUE6_PAGE_INDEX \
74 CVMX_ADD_IO_SEG(0x0001180028000120ull)
75#define CVMX_FPA_QUE7_PAGE_INDEX \
76 CVMX_ADD_IO_SEG(0x0001180028000128ull)
77#define CVMX_FPA_QUEX_AVAILABLE(offset) \
78 CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8))
79#define CVMX_FPA_QUEX_PAGE_INDEX(offset) \
80 CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8))
81#define CVMX_FPA_QUE_ACT \
82 CVMX_ADD_IO_SEG(0x0001180028000138ull)
83#define CVMX_FPA_QUE_EXP \
84 CVMX_ADD_IO_SEG(0x0001180028000130ull)
85#define CVMX_FPA_WART_CTL \
86 CVMX_ADD_IO_SEG(0x00011800280000D8ull)
87#define CVMX_FPA_WART_STATUS \
88 CVMX_ADD_IO_SEG(0x00011800280000E0ull)
89
90union cvmx_fpa_bist_status {
91 uint64_t u64;
92 struct cvmx_fpa_bist_status_s {
93 uint64_t reserved_5_63:59;
94 uint64_t frd:1;
95 uint64_t fpf0:1;
96 uint64_t fpf1:1;
97 uint64_t ffr:1;
98 uint64_t fdr:1;
99 } s;
100 struct cvmx_fpa_bist_status_s cn30xx;
101 struct cvmx_fpa_bist_status_s cn31xx;
102 struct cvmx_fpa_bist_status_s cn38xx;
103 struct cvmx_fpa_bist_status_s cn38xxp2;
104 struct cvmx_fpa_bist_status_s cn50xx;
105 struct cvmx_fpa_bist_status_s cn52xx;
106 struct cvmx_fpa_bist_status_s cn52xxp1;
107 struct cvmx_fpa_bist_status_s cn56xx;
108 struct cvmx_fpa_bist_status_s cn56xxp1;
109 struct cvmx_fpa_bist_status_s cn58xx;
110 struct cvmx_fpa_bist_status_s cn58xxp1;
111};
112
113union cvmx_fpa_ctl_status {
114 uint64_t u64;
115 struct cvmx_fpa_ctl_status_s {
116 uint64_t reserved_18_63:46;
117 uint64_t reset:1;
118 uint64_t use_ldt:1;
119 uint64_t use_stt:1;
120 uint64_t enb:1;
121 uint64_t mem1_err:7;
122 uint64_t mem0_err:7;
123 } s;
124 struct cvmx_fpa_ctl_status_s cn30xx;
125 struct cvmx_fpa_ctl_status_s cn31xx;
126 struct cvmx_fpa_ctl_status_s cn38xx;
127 struct cvmx_fpa_ctl_status_s cn38xxp2;
128 struct cvmx_fpa_ctl_status_s cn50xx;
129 struct cvmx_fpa_ctl_status_s cn52xx;
130 struct cvmx_fpa_ctl_status_s cn52xxp1;
131 struct cvmx_fpa_ctl_status_s cn56xx;
132 struct cvmx_fpa_ctl_status_s cn56xxp1;
133 struct cvmx_fpa_ctl_status_s cn58xx;
134 struct cvmx_fpa_ctl_status_s cn58xxp1;
135};
136
137union cvmx_fpa_fpfx_marks {
138 uint64_t u64;
139 struct cvmx_fpa_fpfx_marks_s {
140 uint64_t reserved_22_63:42;
141 uint64_t fpf_wr:11;
142 uint64_t fpf_rd:11;
143 } s;
144 struct cvmx_fpa_fpfx_marks_s cn38xx;
145 struct cvmx_fpa_fpfx_marks_s cn38xxp2;
146 struct cvmx_fpa_fpfx_marks_s cn56xx;
147 struct cvmx_fpa_fpfx_marks_s cn56xxp1;
148 struct cvmx_fpa_fpfx_marks_s cn58xx;
149 struct cvmx_fpa_fpfx_marks_s cn58xxp1;
150};
151
152union cvmx_fpa_fpfx_size {
153 uint64_t u64;
154 struct cvmx_fpa_fpfx_size_s {
155 uint64_t reserved_11_63:53;
156 uint64_t fpf_siz:11;
157 } s;
158 struct cvmx_fpa_fpfx_size_s cn38xx;
159 struct cvmx_fpa_fpfx_size_s cn38xxp2;
160 struct cvmx_fpa_fpfx_size_s cn56xx;
161 struct cvmx_fpa_fpfx_size_s cn56xxp1;
162 struct cvmx_fpa_fpfx_size_s cn58xx;
163 struct cvmx_fpa_fpfx_size_s cn58xxp1;
164};
165
166union cvmx_fpa_fpf0_marks {
167 uint64_t u64;
168 struct cvmx_fpa_fpf0_marks_s {
169 uint64_t reserved_24_63:40;
170 uint64_t fpf_wr:12;
171 uint64_t fpf_rd:12;
172 } s;
173 struct cvmx_fpa_fpf0_marks_s cn38xx;
174 struct cvmx_fpa_fpf0_marks_s cn38xxp2;
175 struct cvmx_fpa_fpf0_marks_s cn56xx;
176 struct cvmx_fpa_fpf0_marks_s cn56xxp1;
177 struct cvmx_fpa_fpf0_marks_s cn58xx;
178 struct cvmx_fpa_fpf0_marks_s cn58xxp1;
179};
180
181union cvmx_fpa_fpf0_size {
182 uint64_t u64;
183 struct cvmx_fpa_fpf0_size_s {
184 uint64_t reserved_12_63:52;
185 uint64_t fpf_siz:12;
186 } s;
187 struct cvmx_fpa_fpf0_size_s cn38xx;
188 struct cvmx_fpa_fpf0_size_s cn38xxp2;
189 struct cvmx_fpa_fpf0_size_s cn56xx;
190 struct cvmx_fpa_fpf0_size_s cn56xxp1;
191 struct cvmx_fpa_fpf0_size_s cn58xx;
192 struct cvmx_fpa_fpf0_size_s cn58xxp1;
193};
194
195union cvmx_fpa_int_enb {
196 uint64_t u64;
197 struct cvmx_fpa_int_enb_s {
198 uint64_t reserved_28_63:36;
199 uint64_t q7_perr:1;
200 uint64_t q7_coff:1;
201 uint64_t q7_und:1;
202 uint64_t q6_perr:1;
203 uint64_t q6_coff:1;
204 uint64_t q6_und:1;
205 uint64_t q5_perr:1;
206 uint64_t q5_coff:1;
207 uint64_t q5_und:1;
208 uint64_t q4_perr:1;
209 uint64_t q4_coff:1;
210 uint64_t q4_und:1;
211 uint64_t q3_perr:1;
212 uint64_t q3_coff:1;
213 uint64_t q3_und:1;
214 uint64_t q2_perr:1;
215 uint64_t q2_coff:1;
216 uint64_t q2_und:1;
217 uint64_t q1_perr:1;
218 uint64_t q1_coff:1;
219 uint64_t q1_und:1;
220 uint64_t q0_perr:1;
221 uint64_t q0_coff:1;
222 uint64_t q0_und:1;
223 uint64_t fed1_dbe:1;
224 uint64_t fed1_sbe:1;
225 uint64_t fed0_dbe:1;
226 uint64_t fed0_sbe:1;
227 } s;
228 struct cvmx_fpa_int_enb_s cn30xx;
229 struct cvmx_fpa_int_enb_s cn31xx;
230 struct cvmx_fpa_int_enb_s cn38xx;
231 struct cvmx_fpa_int_enb_s cn38xxp2;
232 struct cvmx_fpa_int_enb_s cn50xx;
233 struct cvmx_fpa_int_enb_s cn52xx;
234 struct cvmx_fpa_int_enb_s cn52xxp1;
235 struct cvmx_fpa_int_enb_s cn56xx;
236 struct cvmx_fpa_int_enb_s cn56xxp1;
237 struct cvmx_fpa_int_enb_s cn58xx;
238 struct cvmx_fpa_int_enb_s cn58xxp1;
239};
240
241union cvmx_fpa_int_sum {
242 uint64_t u64;
243 struct cvmx_fpa_int_sum_s {
244 uint64_t reserved_28_63:36;
245 uint64_t q7_perr:1;
246 uint64_t q7_coff:1;
247 uint64_t q7_und:1;
248 uint64_t q6_perr:1;
249 uint64_t q6_coff:1;
250 uint64_t q6_und:1;
251 uint64_t q5_perr:1;
252 uint64_t q5_coff:1;
253 uint64_t q5_und:1;
254 uint64_t q4_perr:1;
255 uint64_t q4_coff:1;
256 uint64_t q4_und:1;
257 uint64_t q3_perr:1;
258 uint64_t q3_coff:1;
259 uint64_t q3_und:1;
260 uint64_t q2_perr:1;
261 uint64_t q2_coff:1;
262 uint64_t q2_und:1;
263 uint64_t q1_perr:1;
264 uint64_t q1_coff:1;
265 uint64_t q1_und:1;
266 uint64_t q0_perr:1;
267 uint64_t q0_coff:1;
268 uint64_t q0_und:1;
269 uint64_t fed1_dbe:1;
270 uint64_t fed1_sbe:1;
271 uint64_t fed0_dbe:1;
272 uint64_t fed0_sbe:1;
273 } s;
274 struct cvmx_fpa_int_sum_s cn30xx;
275 struct cvmx_fpa_int_sum_s cn31xx;
276 struct cvmx_fpa_int_sum_s cn38xx;
277 struct cvmx_fpa_int_sum_s cn38xxp2;
278 struct cvmx_fpa_int_sum_s cn50xx;
279 struct cvmx_fpa_int_sum_s cn52xx;
280 struct cvmx_fpa_int_sum_s cn52xxp1;
281 struct cvmx_fpa_int_sum_s cn56xx;
282 struct cvmx_fpa_int_sum_s cn56xxp1;
283 struct cvmx_fpa_int_sum_s cn58xx;
284 struct cvmx_fpa_int_sum_s cn58xxp1;
285};
286
287union cvmx_fpa_quex_available {
288 uint64_t u64;
289 struct cvmx_fpa_quex_available_s {
290 uint64_t reserved_29_63:35;
291 uint64_t que_siz:29;
292 } s;
293 struct cvmx_fpa_quex_available_s cn30xx;
294 struct cvmx_fpa_quex_available_s cn31xx;
295 struct cvmx_fpa_quex_available_s cn38xx;
296 struct cvmx_fpa_quex_available_s cn38xxp2;
297 struct cvmx_fpa_quex_available_s cn50xx;
298 struct cvmx_fpa_quex_available_s cn52xx;
299 struct cvmx_fpa_quex_available_s cn52xxp1;
300 struct cvmx_fpa_quex_available_s cn56xx;
301 struct cvmx_fpa_quex_available_s cn56xxp1;
302 struct cvmx_fpa_quex_available_s cn58xx;
303 struct cvmx_fpa_quex_available_s cn58xxp1;
304};
305
306union cvmx_fpa_quex_page_index {
307 uint64_t u64;
308 struct cvmx_fpa_quex_page_index_s {
309 uint64_t reserved_25_63:39;
310 uint64_t pg_num:25;
311 } s;
312 struct cvmx_fpa_quex_page_index_s cn30xx;
313 struct cvmx_fpa_quex_page_index_s cn31xx;
314 struct cvmx_fpa_quex_page_index_s cn38xx;
315 struct cvmx_fpa_quex_page_index_s cn38xxp2;
316 struct cvmx_fpa_quex_page_index_s cn50xx;
317 struct cvmx_fpa_quex_page_index_s cn52xx;
318 struct cvmx_fpa_quex_page_index_s cn52xxp1;
319 struct cvmx_fpa_quex_page_index_s cn56xx;
320 struct cvmx_fpa_quex_page_index_s cn56xxp1;
321 struct cvmx_fpa_quex_page_index_s cn58xx;
322 struct cvmx_fpa_quex_page_index_s cn58xxp1;
323};
324
325union cvmx_fpa_que_act {
326 uint64_t u64;
327 struct cvmx_fpa_que_act_s {
328 uint64_t reserved_29_63:35;
329 uint64_t act_que:3;
330 uint64_t act_indx:26;
331 } s;
332 struct cvmx_fpa_que_act_s cn30xx;
333 struct cvmx_fpa_que_act_s cn31xx;
334 struct cvmx_fpa_que_act_s cn38xx;
335 struct cvmx_fpa_que_act_s cn38xxp2;
336 struct cvmx_fpa_que_act_s cn50xx;
337 struct cvmx_fpa_que_act_s cn52xx;
338 struct cvmx_fpa_que_act_s cn52xxp1;
339 struct cvmx_fpa_que_act_s cn56xx;
340 struct cvmx_fpa_que_act_s cn56xxp1;
341 struct cvmx_fpa_que_act_s cn58xx;
342 struct cvmx_fpa_que_act_s cn58xxp1;
343};
344
345union cvmx_fpa_que_exp {
346 uint64_t u64;
347 struct cvmx_fpa_que_exp_s {
348 uint64_t reserved_29_63:35;
349 uint64_t exp_que:3;
350 uint64_t exp_indx:26;
351 } s;
352 struct cvmx_fpa_que_exp_s cn30xx;
353 struct cvmx_fpa_que_exp_s cn31xx;
354 struct cvmx_fpa_que_exp_s cn38xx;
355 struct cvmx_fpa_que_exp_s cn38xxp2;
356 struct cvmx_fpa_que_exp_s cn50xx;
357 struct cvmx_fpa_que_exp_s cn52xx;
358 struct cvmx_fpa_que_exp_s cn52xxp1;
359 struct cvmx_fpa_que_exp_s cn56xx;
360 struct cvmx_fpa_que_exp_s cn56xxp1;
361 struct cvmx_fpa_que_exp_s cn58xx;
362 struct cvmx_fpa_que_exp_s cn58xxp1;
363};
364
365union cvmx_fpa_wart_ctl {
366 uint64_t u64;
367 struct cvmx_fpa_wart_ctl_s {
368 uint64_t reserved_16_63:48;
369 uint64_t ctl:16;
370 } s;
371 struct cvmx_fpa_wart_ctl_s cn30xx;
372 struct cvmx_fpa_wart_ctl_s cn31xx;
373 struct cvmx_fpa_wart_ctl_s cn38xx;
374 struct cvmx_fpa_wart_ctl_s cn38xxp2;
375 struct cvmx_fpa_wart_ctl_s cn50xx;
376 struct cvmx_fpa_wart_ctl_s cn52xx;
377 struct cvmx_fpa_wart_ctl_s cn52xxp1;
378 struct cvmx_fpa_wart_ctl_s cn56xx;
379 struct cvmx_fpa_wart_ctl_s cn56xxp1;
380 struct cvmx_fpa_wart_ctl_s cn58xx;
381 struct cvmx_fpa_wart_ctl_s cn58xxp1;
382};
383
384union cvmx_fpa_wart_status {
385 uint64_t u64;
386 struct cvmx_fpa_wart_status_s {
387 uint64_t reserved_32_63:32;
388 uint64_t status:32;
389 } s;
390 struct cvmx_fpa_wart_status_s cn30xx;
391 struct cvmx_fpa_wart_status_s cn31xx;
392 struct cvmx_fpa_wart_status_s cn38xx;
393 struct cvmx_fpa_wart_status_s cn38xxp2;
394 struct cvmx_fpa_wart_status_s cn50xx;
395 struct cvmx_fpa_wart_status_s cn52xx;
396 struct cvmx_fpa_wart_status_s cn52xxp1;
397 struct cvmx_fpa_wart_status_s cn56xx;
398 struct cvmx_fpa_wart_status_s cn56xxp1;
399 struct cvmx_fpa_wart_status_s cn58xx;
400 struct cvmx_fpa_wart_status_s cn58xxp1;
401};
402
403#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h
new file mode 100644
index 000000000000..1f04f9658736
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-fpa.h
@@ -0,0 +1,299 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Interface to the hardware Free Pool Allocator.
32 *
33 *
34 */
35
36#ifndef __CVMX_FPA_H__
37#define __CVMX_FPA_H__
38
39#include "cvmx-address.h"
40#include "cvmx-fpa-defs.h"
41
42#define CVMX_FPA_NUM_POOLS 8
43#define CVMX_FPA_MIN_BLOCK_SIZE 128
44#define CVMX_FPA_ALIGNMENT 128
45
46/**
47 * Structure describing the data format used for stores to the FPA.
48 */
49typedef union {
50 uint64_t u64;
51 struct {
52 /*
53 * the (64-bit word) location in scratchpad to write
54 * to (if len != 0)
55 */
56 uint64_t scraddr:8;
57 /* the number of words in the response (0 => no response) */
58 uint64_t len:8;
59 /* the ID of the device on the non-coherent bus */
60 uint64_t did:8;
61 /*
62 * the address that will appear in the first tick on
63 * the NCB bus.
64 */
65 uint64_t addr:40;
66 } s;
67} cvmx_fpa_iobdma_data_t;
68
69/**
70 * Structure describing the current state of a FPA pool.
71 */
72typedef struct {
73 /* Name it was created under */
74 const char *name;
75 /* Size of each block */
76 uint64_t size;
77 /* The base memory address of whole block */
78 void *base;
79 /* The number of elements in the pool at creation */
80 uint64_t starting_element_count;
81} cvmx_fpa_pool_info_t;
82
83/**
84 * Current state of all the pools. Use access functions
85 * instead of using it directly.
86 */
87extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
88
89/* CSR typedefs have been moved to cvmx-csr-*.h */
90
91/**
92 * Return the name of the pool
93 *
94 * @pool: Pool to get the name of
95 * Returns The name
96 */
97static inline const char *cvmx_fpa_get_name(uint64_t pool)
98{
99 return cvmx_fpa_pool_info[pool].name;
100}
101
102/**
103 * Return the base of the pool
104 *
105 * @pool: Pool to get the base of
106 * Returns The base
107 */
108static inline void *cvmx_fpa_get_base(uint64_t pool)
109{
110 return cvmx_fpa_pool_info[pool].base;
111}
112
113/**
114 * Check if a pointer belongs to an FPA pool. Return non-zero
115 * if the supplied pointer is inside the memory controlled by
116 * an FPA pool.
117 *
118 * @pool: Pool to check
119 * @ptr: Pointer to check
120 * Returns Non-zero if pointer is in the pool. Zero if not
121 */
122static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr)
123{
124 return ((ptr >= cvmx_fpa_pool_info[pool].base) &&
125 ((char *)ptr <
126 ((char *)(cvmx_fpa_pool_info[pool].base)) +
127 cvmx_fpa_pool_info[pool].size *
128 cvmx_fpa_pool_info[pool].starting_element_count));
129}
130
131/**
132 * Enable the FPA for use. Must be performed after any CSR
133 * configuration but before any other FPA functions.
134 */
135static inline void cvmx_fpa_enable(void)
136{
137 union cvmx_fpa_ctl_status status;
138
139 status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
140 if (status.s.enb) {
141 cvmx_dprintf
142 ("Warning: Enabling FPA when FPA already enabled.\n");
143 }
144
145 /*
146 * Do runtime check as we allow pass1 compiled code to run on
147 * pass2 chips.
148 */
149 if (cvmx_octeon_is_pass1()) {
150 union cvmx_fpa_fpfx_marks marks;
151 int i;
152 for (i = 1; i < 8; i++) {
153 marks.u64 =
154 cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull);
155 marks.s.fpf_wr = 0xe0;
156 cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull,
157 marks.u64);
158 }
159
160 /* Enforce a 10 cycle delay between config and enable */
161 cvmx_wait(10);
162 }
163
164 /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
165 status.u64 = 0;
166 status.s.enb = 1;
167 cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
168}
169
170/**
171 * Get a new block from the FPA
172 *
173 * @pool: Pool to get the block from
174 * Returns Pointer to the block or NULL on failure
175 */
176static inline void *cvmx_fpa_alloc(uint64_t pool)
177{
178 uint64_t address =
179 cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)));
180 if (address)
181 return cvmx_phys_to_ptr(address);
182 else
183 return NULL;
184}
185
186/**
187 * Asynchronously get a new block from the FPA
188 *
189 * @scr_addr: Local scratch address to put response in. This is a byte address,
190 * but must be 8 byte aligned.
191 * @pool: Pool to get the block from
192 */
193static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
194{
195 cvmx_fpa_iobdma_data_t data;
196
197 /*
198 * Hardware only uses 64 bit aligned locations, so convert
199 * from byte address to 64-bit index
200 */
201 data.s.scraddr = scr_addr >> 3;
202 data.s.len = 1;
203 data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool);
204 data.s.addr = 0;
205 cvmx_send_single(data.u64);
206}
207
208/**
209 * Free a block allocated with a FPA pool. Does NOT provide memory
210 * ordering in cases where the memory block was modified by the core.
211 *
212 * @ptr: Block to free
213 * @pool: Pool to put it in
214 * @num_cache_lines:
215 * Cache lines to invalidate
216 */
217static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool,
218 uint64_t num_cache_lines)
219{
220 cvmx_addr_t newptr;
221 newptr.u64 = cvmx_ptr_to_phys(ptr);
222 newptr.sfilldidspace.didspace =
223 CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
224 /* Prevent GCC from reordering around free */
225 barrier();
226 /* value written is number of cache lines not written back */
227 cvmx_write_io(newptr.u64, num_cache_lines);
228}
229
230/**
231 * Free a block allocated with a FPA pool. Provides required memory
232 * ordering in cases where memory block was modified by core.
233 *
234 * @ptr: Block to free
235 * @pool: Pool to put it in
236 * @num_cache_lines:
237 * Cache lines to invalidate
238 */
239static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
240 uint64_t num_cache_lines)
241{
242 cvmx_addr_t newptr;
243 newptr.u64 = cvmx_ptr_to_phys(ptr);
244 newptr.sfilldidspace.didspace =
245 CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
246 /*
247 * Make sure that any previous writes to memory go out before
248 * we free this buffer. This also serves as a barrier to
249 * prevent GCC from reordering operations to after the
250 * free.
251 */
252 CVMX_SYNCWS;
253 /* value written is number of cache lines not written back */
254 cvmx_write_io(newptr.u64, num_cache_lines);
255}
256
257/**
258 * Setup a FPA pool to control a new block of memory.
259 * This can only be called once per pool. Make sure proper
260 * locking enforces this.
261 *
262 * @pool: Pool to initialize
263 * 0 <= pool < 8
264 * @name: Constant character string to name this pool.
265 * String is not copied.
266 * @buffer: Pointer to the block of memory to use. This must be
267 * accessible by all processors and external hardware.
268 * @block_size: Size for each block controlled by the FPA
269 * @num_blocks: Number of blocks
270 *
271 * Returns 0 on Success,
272 * -1 on failure
273 */
274extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
275 uint64_t block_size, uint64_t num_blocks);
276
277/**
278 * Shutdown a Memory pool and validate that it had all of
279 * the buffers originally placed in it. This should only be
280 * called by one processor after all hardware has finished
281 * using the pool.
282 *
283 * @pool: Pool to shutdown
284 * Returns Zero on success
285 * - Positive is count of missing buffers
286 * - Negative is too many buffers or corrupted pointers
287 */
288extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
289
290/**
291 * Get the size of blocks controlled by the pool
292 * This is resolved to a constant at compile time.
293 *
294 * @pool: Pool to access
295 * Returns Size of the block in bytes
296 */
297uint64_t cvmx_fpa_get_block_size(uint64_t pool);
298
299#endif /* __CVM_FPA_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
new file mode 100644
index 000000000000..946a43a73fd7
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-gmxx-defs.h
@@ -0,0 +1,2529 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_GMXX_DEFS_H__
29#define __CVMX_GMXX_DEFS_H__
30
31#define CVMX_GMXX_BAD_REG(block_id) \
32 CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_GMXX_BIST(block_id) \
34 CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_GMXX_CLK_EN(block_id) \
36 CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_GMXX_HG2_CONTROL(block_id) \
38 CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_GMXX_INF_MODE(block_id) \
40 CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_GMXX_NXA_ADR(block_id) \
42 CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \
44 CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_GMXX_PRTX_CFG(offset, block_id) \
46 CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \
48 CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \
50 CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \
52 CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \
54 CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \
56 CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \
58 CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \
60 CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \
62 CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
63#define CVMX_GMXX_RXX_DECISION(offset, block_id) \
64 CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
65#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \
66 CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
67#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \
68 CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
69#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \
70 CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
71#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \
72 CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
73#define CVMX_GMXX_RXX_IFG(offset, block_id) \
74 CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
75#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \
76 CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
77#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \
78 CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
79#define CVMX_GMXX_RXX_JABBER(offset, block_id) \
80 CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
81#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \
82 CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
83#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \
84 CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
85#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \
86 CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
87#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \
88 CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
89#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \
90 CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
91#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \
92 CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
93#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \
94 CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
95#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \
96 CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
97#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \
98 CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
99#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \
100 CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
101#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \
102 CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
103#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \
104 CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
105#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \
106 CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
107#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \
108 CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
109#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \
110 CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
111#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \
112 CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
113#define CVMX_GMXX_RX_HG2_STATUS(block_id) \
114 CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull))
115#define CVMX_GMXX_RX_PASS_EN(block_id) \
116 CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull))
117#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \
118 CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull))
119#define CVMX_GMXX_RX_PRTS(block_id) \
120 CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull))
121#define CVMX_GMXX_RX_PRT_INFO(block_id) \
122 CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull))
123#define CVMX_GMXX_RX_TX_STATUS(block_id) \
124 CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull))
125#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \
126 CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull))
127#define CVMX_GMXX_RX_XAUI_CTL(block_id) \
128 CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull))
129#define CVMX_GMXX_SMACX(offset, block_id) \
130 CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
131#define CVMX_GMXX_STAT_BP(block_id) \
132 CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull))
133#define CVMX_GMXX_TXX_APPEND(offset, block_id) \
134 CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
135#define CVMX_GMXX_TXX_BURST(offset, block_id) \
136 CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
137#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \
138 CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
139#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \
140 CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
141#define CVMX_GMXX_TXX_CLK(offset, block_id) \
142 CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
143#define CVMX_GMXX_TXX_CTL(offset, block_id) \
144 CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
145#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \
146 CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
147#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \
148 CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
149#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \
150 CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
151#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \
152 CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
153#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \
154 CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
155#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \
156 CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
157#define CVMX_GMXX_TXX_SLOT(offset, block_id) \
158 CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
159#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \
160 CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
161#define CVMX_GMXX_TXX_STAT0(offset, block_id) \
162 CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
163#define CVMX_GMXX_TXX_STAT1(offset, block_id) \
164 CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
165#define CVMX_GMXX_TXX_STAT2(offset, block_id) \
166 CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
167#define CVMX_GMXX_TXX_STAT3(offset, block_id) \
168 CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
169#define CVMX_GMXX_TXX_STAT4(offset, block_id) \
170 CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
171#define CVMX_GMXX_TXX_STAT5(offset, block_id) \
172 CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
173#define CVMX_GMXX_TXX_STAT6(offset, block_id) \
174 CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
175#define CVMX_GMXX_TXX_STAT7(offset, block_id) \
176 CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
177#define CVMX_GMXX_TXX_STAT8(offset, block_id) \
178 CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
179#define CVMX_GMXX_TXX_STAT9(offset, block_id) \
180 CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
181#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \
182 CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
183#define CVMX_GMXX_TXX_THRESH(offset, block_id) \
184 CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
185#define CVMX_GMXX_TX_BP(block_id) \
186 CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull))
187#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \
188 CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull))
189#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \
190 CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull))
191#define CVMX_GMXX_TX_CORRUPT(block_id) \
192 CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull))
193#define CVMX_GMXX_TX_HG2_REG1(block_id) \
194 CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull))
195#define CVMX_GMXX_TX_HG2_REG2(block_id) \
196 CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull))
197#define CVMX_GMXX_TX_IFG(block_id) \
198 CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull))
199#define CVMX_GMXX_TX_INT_EN(block_id) \
200 CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull))
201#define CVMX_GMXX_TX_INT_REG(block_id) \
202 CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull))
203#define CVMX_GMXX_TX_JAM(block_id) \
204 CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull))
205#define CVMX_GMXX_TX_LFSR(block_id) \
206 CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull))
207#define CVMX_GMXX_TX_OVR_BP(block_id) \
208 CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull))
209#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \
210 CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull))
211#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \
212 CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull))
213#define CVMX_GMXX_TX_PRTS(block_id) \
214 CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull))
215#define CVMX_GMXX_TX_SPI_CTL(block_id) \
216 CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull))
217#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \
218 CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull))
219#define CVMX_GMXX_TX_SPI_MAX(block_id) \
220 CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull))
221#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \
222 CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
223#define CVMX_GMXX_TX_SPI_THRESH(block_id) \
224 CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull))
225#define CVMX_GMXX_TX_XAUI_CTL(block_id) \
226 CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull))
227#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \
228 CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull))
229
230union cvmx_gmxx_bad_reg {
231 uint64_t u64;
232 struct cvmx_gmxx_bad_reg_s {
233 uint64_t reserved_31_63:33;
234 uint64_t inb_nxa:4;
235 uint64_t statovr:1;
236 uint64_t loststat:4;
237 uint64_t reserved_18_21:4;
238 uint64_t out_ovr:16;
239 uint64_t ncb_ovr:1;
240 uint64_t out_col:1;
241 } s;
242 struct cvmx_gmxx_bad_reg_cn30xx {
243 uint64_t reserved_31_63:33;
244 uint64_t inb_nxa:4;
245 uint64_t statovr:1;
246 uint64_t reserved_25_25:1;
247 uint64_t loststat:3;
248 uint64_t reserved_5_21:17;
249 uint64_t out_ovr:3;
250 uint64_t reserved_0_1:2;
251 } cn30xx;
252 struct cvmx_gmxx_bad_reg_cn30xx cn31xx;
253 struct cvmx_gmxx_bad_reg_s cn38xx;
254 struct cvmx_gmxx_bad_reg_s cn38xxp2;
255 struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
256 struct cvmx_gmxx_bad_reg_cn52xx {
257 uint64_t reserved_31_63:33;
258 uint64_t inb_nxa:4;
259 uint64_t statovr:1;
260 uint64_t loststat:4;
261 uint64_t reserved_6_21:16;
262 uint64_t out_ovr:4;
263 uint64_t reserved_0_1:2;
264 } cn52xx;
265 struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;
266 struct cvmx_gmxx_bad_reg_cn52xx cn56xx;
267 struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
268 struct cvmx_gmxx_bad_reg_s cn58xx;
269 struct cvmx_gmxx_bad_reg_s cn58xxp1;
270};
271
272union cvmx_gmxx_bist {
273 uint64_t u64;
274 struct cvmx_gmxx_bist_s {
275 uint64_t reserved_17_63:47;
276 uint64_t status:17;
277 } s;
278 struct cvmx_gmxx_bist_cn30xx {
279 uint64_t reserved_10_63:54;
280 uint64_t status:10;
281 } cn30xx;
282 struct cvmx_gmxx_bist_cn30xx cn31xx;
283 struct cvmx_gmxx_bist_cn30xx cn38xx;
284 struct cvmx_gmxx_bist_cn30xx cn38xxp2;
285 struct cvmx_gmxx_bist_cn50xx {
286 uint64_t reserved_12_63:52;
287 uint64_t status:12;
288 } cn50xx;
289 struct cvmx_gmxx_bist_cn52xx {
290 uint64_t reserved_16_63:48;
291 uint64_t status:16;
292 } cn52xx;
293 struct cvmx_gmxx_bist_cn52xx cn52xxp1;
294 struct cvmx_gmxx_bist_cn52xx cn56xx;
295 struct cvmx_gmxx_bist_cn52xx cn56xxp1;
296 struct cvmx_gmxx_bist_s cn58xx;
297 struct cvmx_gmxx_bist_s cn58xxp1;
298};
299
300union cvmx_gmxx_clk_en {
301 uint64_t u64;
302 struct cvmx_gmxx_clk_en_s {
303 uint64_t reserved_1_63:63;
304 uint64_t clk_en:1;
305 } s;
306 struct cvmx_gmxx_clk_en_s cn52xx;
307 struct cvmx_gmxx_clk_en_s cn52xxp1;
308 struct cvmx_gmxx_clk_en_s cn56xx;
309 struct cvmx_gmxx_clk_en_s cn56xxp1;
310};
311
312union cvmx_gmxx_hg2_control {
313 uint64_t u64;
314 struct cvmx_gmxx_hg2_control_s {
315 uint64_t reserved_19_63:45;
316 uint64_t hg2tx_en:1;
317 uint64_t hg2rx_en:1;
318 uint64_t phys_en:1;
319 uint64_t logl_en:16;
320 } s;
321 struct cvmx_gmxx_hg2_control_s cn52xx;
322 struct cvmx_gmxx_hg2_control_s cn52xxp1;
323 struct cvmx_gmxx_hg2_control_s cn56xx;
324};
325
326union cvmx_gmxx_inf_mode {
327 uint64_t u64;
328 struct cvmx_gmxx_inf_mode_s {
329 uint64_t reserved_10_63:54;
330 uint64_t speed:2;
331 uint64_t reserved_6_7:2;
332 uint64_t mode:2;
333 uint64_t reserved_3_3:1;
334 uint64_t p0mii:1;
335 uint64_t en:1;
336 uint64_t type:1;
337 } s;
338 struct cvmx_gmxx_inf_mode_cn30xx {
339 uint64_t reserved_3_63:61;
340 uint64_t p0mii:1;
341 uint64_t en:1;
342 uint64_t type:1;
343 } cn30xx;
344 struct cvmx_gmxx_inf_mode_cn31xx {
345 uint64_t reserved_2_63:62;
346 uint64_t en:1;
347 uint64_t type:1;
348 } cn31xx;
349 struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
350 struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
351 struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
352 struct cvmx_gmxx_inf_mode_cn52xx {
353 uint64_t reserved_10_63:54;
354 uint64_t speed:2;
355 uint64_t reserved_6_7:2;
356 uint64_t mode:2;
357 uint64_t reserved_2_3:2;
358 uint64_t en:1;
359 uint64_t type:1;
360 } cn52xx;
361 struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;
362 struct cvmx_gmxx_inf_mode_cn52xx cn56xx;
363 struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
364 struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
365 struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
366};
367
368union cvmx_gmxx_nxa_adr {
369 uint64_t u64;
370 struct cvmx_gmxx_nxa_adr_s {
371 uint64_t reserved_6_63:58;
372 uint64_t prt:6;
373 } s;
374 struct cvmx_gmxx_nxa_adr_s cn30xx;
375 struct cvmx_gmxx_nxa_adr_s cn31xx;
376 struct cvmx_gmxx_nxa_adr_s cn38xx;
377 struct cvmx_gmxx_nxa_adr_s cn38xxp2;
378 struct cvmx_gmxx_nxa_adr_s cn50xx;
379 struct cvmx_gmxx_nxa_adr_s cn52xx;
380 struct cvmx_gmxx_nxa_adr_s cn52xxp1;
381 struct cvmx_gmxx_nxa_adr_s cn56xx;
382 struct cvmx_gmxx_nxa_adr_s cn56xxp1;
383 struct cvmx_gmxx_nxa_adr_s cn58xx;
384 struct cvmx_gmxx_nxa_adr_s cn58xxp1;
385};
386
387union cvmx_gmxx_prtx_cbfc_ctl {
388 uint64_t u64;
389 struct cvmx_gmxx_prtx_cbfc_ctl_s {
390 uint64_t phys_en:16;
391 uint64_t logl_en:16;
392 uint64_t phys_bp:16;
393 uint64_t reserved_4_15:12;
394 uint64_t bck_en:1;
395 uint64_t drp_en:1;
396 uint64_t tx_en:1;
397 uint64_t rx_en:1;
398 } s;
399 struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
400 struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
401};
402
403union cvmx_gmxx_prtx_cfg {
404 uint64_t u64;
405 struct cvmx_gmxx_prtx_cfg_s {
406 uint64_t reserved_14_63:50;
407 uint64_t tx_idle:1;
408 uint64_t rx_idle:1;
409 uint64_t reserved_9_11:3;
410 uint64_t speed_msb:1;
411 uint64_t reserved_4_7:4;
412 uint64_t slottime:1;
413 uint64_t duplex:1;
414 uint64_t speed:1;
415 uint64_t en:1;
416 } s;
417 struct cvmx_gmxx_prtx_cfg_cn30xx {
418 uint64_t reserved_4_63:60;
419 uint64_t slottime:1;
420 uint64_t duplex:1;
421 uint64_t speed:1;
422 uint64_t en:1;
423 } cn30xx;
424 struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;
425 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
426 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
427 struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
428 struct cvmx_gmxx_prtx_cfg_s cn52xx;
429 struct cvmx_gmxx_prtx_cfg_s cn52xxp1;
430 struct cvmx_gmxx_prtx_cfg_s cn56xx;
431 struct cvmx_gmxx_prtx_cfg_s cn56xxp1;
432 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
433 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
434};
435
436union cvmx_gmxx_rxx_adr_cam0 {
437 uint64_t u64;
438 struct cvmx_gmxx_rxx_adr_cam0_s {
439 uint64_t adr:64;
440 } s;
441 struct cvmx_gmxx_rxx_adr_cam0_s cn30xx;
442 struct cvmx_gmxx_rxx_adr_cam0_s cn31xx;
443 struct cvmx_gmxx_rxx_adr_cam0_s cn38xx;
444 struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2;
445 struct cvmx_gmxx_rxx_adr_cam0_s cn50xx;
446 struct cvmx_gmxx_rxx_adr_cam0_s cn52xx;
447 struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1;
448 struct cvmx_gmxx_rxx_adr_cam0_s cn56xx;
449 struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
450 struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
451 struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
452};
453
454union cvmx_gmxx_rxx_adr_cam1 {
455 uint64_t u64;
456 struct cvmx_gmxx_rxx_adr_cam1_s {
457 uint64_t adr:64;
458 } s;
459 struct cvmx_gmxx_rxx_adr_cam1_s cn30xx;
460 struct cvmx_gmxx_rxx_adr_cam1_s cn31xx;
461 struct cvmx_gmxx_rxx_adr_cam1_s cn38xx;
462 struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2;
463 struct cvmx_gmxx_rxx_adr_cam1_s cn50xx;
464 struct cvmx_gmxx_rxx_adr_cam1_s cn52xx;
465 struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1;
466 struct cvmx_gmxx_rxx_adr_cam1_s cn56xx;
467 struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
468 struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
469 struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
470};
471
472union cvmx_gmxx_rxx_adr_cam2 {
473 uint64_t u64;
474 struct cvmx_gmxx_rxx_adr_cam2_s {
475 uint64_t adr:64;
476 } s;
477 struct cvmx_gmxx_rxx_adr_cam2_s cn30xx;
478 struct cvmx_gmxx_rxx_adr_cam2_s cn31xx;
479 struct cvmx_gmxx_rxx_adr_cam2_s cn38xx;
480 struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2;
481 struct cvmx_gmxx_rxx_adr_cam2_s cn50xx;
482 struct cvmx_gmxx_rxx_adr_cam2_s cn52xx;
483 struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1;
484 struct cvmx_gmxx_rxx_adr_cam2_s cn56xx;
485 struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
486 struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
487 struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
488};
489
490union cvmx_gmxx_rxx_adr_cam3 {
491 uint64_t u64;
492 struct cvmx_gmxx_rxx_adr_cam3_s {
493 uint64_t adr:64;
494 } s;
495 struct cvmx_gmxx_rxx_adr_cam3_s cn30xx;
496 struct cvmx_gmxx_rxx_adr_cam3_s cn31xx;
497 struct cvmx_gmxx_rxx_adr_cam3_s cn38xx;
498 struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2;
499 struct cvmx_gmxx_rxx_adr_cam3_s cn50xx;
500 struct cvmx_gmxx_rxx_adr_cam3_s cn52xx;
501 struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1;
502 struct cvmx_gmxx_rxx_adr_cam3_s cn56xx;
503 struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
504 struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
505 struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
506};
507
508union cvmx_gmxx_rxx_adr_cam4 {
509 uint64_t u64;
510 struct cvmx_gmxx_rxx_adr_cam4_s {
511 uint64_t adr:64;
512 } s;
513 struct cvmx_gmxx_rxx_adr_cam4_s cn30xx;
514 struct cvmx_gmxx_rxx_adr_cam4_s cn31xx;
515 struct cvmx_gmxx_rxx_adr_cam4_s cn38xx;
516 struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2;
517 struct cvmx_gmxx_rxx_adr_cam4_s cn50xx;
518 struct cvmx_gmxx_rxx_adr_cam4_s cn52xx;
519 struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1;
520 struct cvmx_gmxx_rxx_adr_cam4_s cn56xx;
521 struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
522 struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
523 struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
524};
525
526union cvmx_gmxx_rxx_adr_cam5 {
527 uint64_t u64;
528 struct cvmx_gmxx_rxx_adr_cam5_s {
529 uint64_t adr:64;
530 } s;
531 struct cvmx_gmxx_rxx_adr_cam5_s cn30xx;
532 struct cvmx_gmxx_rxx_adr_cam5_s cn31xx;
533 struct cvmx_gmxx_rxx_adr_cam5_s cn38xx;
534 struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2;
535 struct cvmx_gmxx_rxx_adr_cam5_s cn50xx;
536 struct cvmx_gmxx_rxx_adr_cam5_s cn52xx;
537 struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1;
538 struct cvmx_gmxx_rxx_adr_cam5_s cn56xx;
539 struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
540 struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
541 struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
542};
543
544union cvmx_gmxx_rxx_adr_cam_en {
545 uint64_t u64;
546 struct cvmx_gmxx_rxx_adr_cam_en_s {
547 uint64_t reserved_8_63:56;
548 uint64_t en:8;
549 } s;
550 struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;
551 struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;
552 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx;
553 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2;
554 struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx;
555 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx;
556 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1;
557 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx;
558 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
559 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
560 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
561};
562
563union cvmx_gmxx_rxx_adr_ctl {
564 uint64_t u64;
565 struct cvmx_gmxx_rxx_adr_ctl_s {
566 uint64_t reserved_4_63:60;
567 uint64_t cam_mode:1;
568 uint64_t mcst:2;
569 uint64_t bcst:1;
570 } s;
571 struct cvmx_gmxx_rxx_adr_ctl_s cn30xx;
572 struct cvmx_gmxx_rxx_adr_ctl_s cn31xx;
573 struct cvmx_gmxx_rxx_adr_ctl_s cn38xx;
574 struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2;
575 struct cvmx_gmxx_rxx_adr_ctl_s cn50xx;
576 struct cvmx_gmxx_rxx_adr_ctl_s cn52xx;
577 struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1;
578 struct cvmx_gmxx_rxx_adr_ctl_s cn56xx;
579 struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
580 struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
581 struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
582};
583
584union cvmx_gmxx_rxx_decision {
585 uint64_t u64;
586 struct cvmx_gmxx_rxx_decision_s {
587 uint64_t reserved_5_63:59;
588 uint64_t cnt:5;
589 } s;
590 struct cvmx_gmxx_rxx_decision_s cn30xx;
591 struct cvmx_gmxx_rxx_decision_s cn31xx;
592 struct cvmx_gmxx_rxx_decision_s cn38xx;
593 struct cvmx_gmxx_rxx_decision_s cn38xxp2;
594 struct cvmx_gmxx_rxx_decision_s cn50xx;
595 struct cvmx_gmxx_rxx_decision_s cn52xx;
596 struct cvmx_gmxx_rxx_decision_s cn52xxp1;
597 struct cvmx_gmxx_rxx_decision_s cn56xx;
598 struct cvmx_gmxx_rxx_decision_s cn56xxp1;
599 struct cvmx_gmxx_rxx_decision_s cn58xx;
600 struct cvmx_gmxx_rxx_decision_s cn58xxp1;
601};
602
603union cvmx_gmxx_rxx_frm_chk {
604 uint64_t u64;
605 struct cvmx_gmxx_rxx_frm_chk_s {
606 uint64_t reserved_10_63:54;
607 uint64_t niberr:1;
608 uint64_t skperr:1;
609 uint64_t rcverr:1;
610 uint64_t lenerr:1;
611 uint64_t alnerr:1;
612 uint64_t fcserr:1;
613 uint64_t jabber:1;
614 uint64_t maxerr:1;
615 uint64_t carext:1;
616 uint64_t minerr:1;
617 } s;
618 struct cvmx_gmxx_rxx_frm_chk_s cn30xx;
619 struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
620 struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
621 struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
622 struct cvmx_gmxx_rxx_frm_chk_cn50xx {
623 uint64_t reserved_10_63:54;
624 uint64_t niberr:1;
625 uint64_t skperr:1;
626 uint64_t rcverr:1;
627 uint64_t reserved_6_6:1;
628 uint64_t alnerr:1;
629 uint64_t fcserr:1;
630 uint64_t jabber:1;
631 uint64_t reserved_2_2:1;
632 uint64_t carext:1;
633 uint64_t reserved_0_0:1;
634 } cn50xx;
635 struct cvmx_gmxx_rxx_frm_chk_cn52xx {
636 uint64_t reserved_9_63:55;
637 uint64_t skperr:1;
638 uint64_t rcverr:1;
639 uint64_t reserved_5_6:2;
640 uint64_t fcserr:1;
641 uint64_t jabber:1;
642 uint64_t reserved_2_2:1;
643 uint64_t carext:1;
644 uint64_t reserved_0_0:1;
645 } cn52xx;
646 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;
647 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;
648 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
649 struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
650 struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
651};
652
653union cvmx_gmxx_rxx_frm_ctl {
654 uint64_t u64;
655 struct cvmx_gmxx_rxx_frm_ctl_s {
656 uint64_t reserved_11_63:53;
657 uint64_t null_dis:1;
658 uint64_t pre_align:1;
659 uint64_t pad_len:1;
660 uint64_t vlan_len:1;
661 uint64_t pre_free:1;
662 uint64_t ctl_smac:1;
663 uint64_t ctl_mcst:1;
664 uint64_t ctl_bck:1;
665 uint64_t ctl_drp:1;
666 uint64_t pre_strp:1;
667 uint64_t pre_chk:1;
668 } s;
669 struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
670 uint64_t reserved_9_63:55;
671 uint64_t pad_len:1;
672 uint64_t vlan_len:1;
673 uint64_t pre_free:1;
674 uint64_t ctl_smac:1;
675 uint64_t ctl_mcst:1;
676 uint64_t ctl_bck:1;
677 uint64_t ctl_drp:1;
678 uint64_t pre_strp:1;
679 uint64_t pre_chk:1;
680 } cn30xx;
681 struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
682 uint64_t reserved_8_63:56;
683 uint64_t vlan_len:1;
684 uint64_t pre_free:1;
685 uint64_t ctl_smac:1;
686 uint64_t ctl_mcst:1;
687 uint64_t ctl_bck:1;
688 uint64_t ctl_drp:1;
689 uint64_t pre_strp:1;
690 uint64_t pre_chk:1;
691 } cn31xx;
692 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
693 struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
694 struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
695 uint64_t reserved_11_63:53;
696 uint64_t null_dis:1;
697 uint64_t pre_align:1;
698 uint64_t reserved_7_8:2;
699 uint64_t pre_free:1;
700 uint64_t ctl_smac:1;
701 uint64_t ctl_mcst:1;
702 uint64_t ctl_bck:1;
703 uint64_t ctl_drp:1;
704 uint64_t pre_strp:1;
705 uint64_t pre_chk:1;
706 } cn50xx;
707 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
708 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
709 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
710 struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
711 uint64_t reserved_10_63:54;
712 uint64_t pre_align:1;
713 uint64_t reserved_7_8:2;
714 uint64_t pre_free:1;
715 uint64_t ctl_smac:1;
716 uint64_t ctl_mcst:1;
717 uint64_t ctl_bck:1;
718 uint64_t ctl_drp:1;
719 uint64_t pre_strp:1;
720 uint64_t pre_chk:1;
721 } cn56xxp1;
722 struct cvmx_gmxx_rxx_frm_ctl_s cn58xx;
723 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
724};
725
726union cvmx_gmxx_rxx_frm_max {
727 uint64_t u64;
728 struct cvmx_gmxx_rxx_frm_max_s {
729 uint64_t reserved_16_63:48;
730 uint64_t len:16;
731 } s;
732 struct cvmx_gmxx_rxx_frm_max_s cn30xx;
733 struct cvmx_gmxx_rxx_frm_max_s cn31xx;
734 struct cvmx_gmxx_rxx_frm_max_s cn38xx;
735 struct cvmx_gmxx_rxx_frm_max_s cn38xxp2;
736 struct cvmx_gmxx_rxx_frm_max_s cn58xx;
737 struct cvmx_gmxx_rxx_frm_max_s cn58xxp1;
738};
739
740union cvmx_gmxx_rxx_frm_min {
741 uint64_t u64;
742 struct cvmx_gmxx_rxx_frm_min_s {
743 uint64_t reserved_16_63:48;
744 uint64_t len:16;
745 } s;
746 struct cvmx_gmxx_rxx_frm_min_s cn30xx;
747 struct cvmx_gmxx_rxx_frm_min_s cn31xx;
748 struct cvmx_gmxx_rxx_frm_min_s cn38xx;
749 struct cvmx_gmxx_rxx_frm_min_s cn38xxp2;
750 struct cvmx_gmxx_rxx_frm_min_s cn58xx;
751 struct cvmx_gmxx_rxx_frm_min_s cn58xxp1;
752};
753
754union cvmx_gmxx_rxx_ifg {
755 uint64_t u64;
756 struct cvmx_gmxx_rxx_ifg_s {
757 uint64_t reserved_4_63:60;
758 uint64_t ifg:4;
759 } s;
760 struct cvmx_gmxx_rxx_ifg_s cn30xx;
761 struct cvmx_gmxx_rxx_ifg_s cn31xx;
762 struct cvmx_gmxx_rxx_ifg_s cn38xx;
763 struct cvmx_gmxx_rxx_ifg_s cn38xxp2;
764 struct cvmx_gmxx_rxx_ifg_s cn50xx;
765 struct cvmx_gmxx_rxx_ifg_s cn52xx;
766 struct cvmx_gmxx_rxx_ifg_s cn52xxp1;
767 struct cvmx_gmxx_rxx_ifg_s cn56xx;
768 struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
769 struct cvmx_gmxx_rxx_ifg_s cn58xx;
770 struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
771};
772
773union cvmx_gmxx_rxx_int_en {
774 uint64_t u64;
775 struct cvmx_gmxx_rxx_int_en_s {
776 uint64_t reserved_29_63:35;
777 uint64_t hg2cc:1;
778 uint64_t hg2fld:1;
779 uint64_t undat:1;
780 uint64_t uneop:1;
781 uint64_t unsop:1;
782 uint64_t bad_term:1;
783 uint64_t bad_seq:1;
784 uint64_t rem_fault:1;
785 uint64_t loc_fault:1;
786 uint64_t pause_drp:1;
787 uint64_t phy_dupx:1;
788 uint64_t phy_spd:1;
789 uint64_t phy_link:1;
790 uint64_t ifgerr:1;
791 uint64_t coldet:1;
792 uint64_t falerr:1;
793 uint64_t rsverr:1;
794 uint64_t pcterr:1;
795 uint64_t ovrerr:1;
796 uint64_t niberr:1;
797 uint64_t skperr:1;
798 uint64_t rcverr:1;
799 uint64_t lenerr:1;
800 uint64_t alnerr:1;
801 uint64_t fcserr:1;
802 uint64_t jabber:1;
803 uint64_t maxerr:1;
804 uint64_t carext:1;
805 uint64_t minerr:1;
806 } s;
807 struct cvmx_gmxx_rxx_int_en_cn30xx {
808 uint64_t reserved_19_63:45;
809 uint64_t phy_dupx:1;
810 uint64_t phy_spd:1;
811 uint64_t phy_link:1;
812 uint64_t ifgerr:1;
813 uint64_t coldet:1;
814 uint64_t falerr:1;
815 uint64_t rsverr:1;
816 uint64_t pcterr:1;
817 uint64_t ovrerr:1;
818 uint64_t niberr:1;
819 uint64_t skperr:1;
820 uint64_t rcverr:1;
821 uint64_t lenerr:1;
822 uint64_t alnerr:1;
823 uint64_t fcserr:1;
824 uint64_t jabber:1;
825 uint64_t maxerr:1;
826 uint64_t carext:1;
827 uint64_t minerr:1;
828 } cn30xx;
829 struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
830 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
831 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
832 struct cvmx_gmxx_rxx_int_en_cn50xx {
833 uint64_t reserved_20_63:44;
834 uint64_t pause_drp:1;
835 uint64_t phy_dupx:1;
836 uint64_t phy_spd:1;
837 uint64_t phy_link:1;
838 uint64_t ifgerr:1;
839 uint64_t coldet:1;
840 uint64_t falerr:1;
841 uint64_t rsverr:1;
842 uint64_t pcterr:1;
843 uint64_t ovrerr:1;
844 uint64_t niberr:1;
845 uint64_t skperr:1;
846 uint64_t rcverr:1;
847 uint64_t reserved_6_6:1;
848 uint64_t alnerr:1;
849 uint64_t fcserr:1;
850 uint64_t jabber:1;
851 uint64_t reserved_2_2:1;
852 uint64_t carext:1;
853 uint64_t reserved_0_0:1;
854 } cn50xx;
855 struct cvmx_gmxx_rxx_int_en_cn52xx {
856 uint64_t reserved_29_63:35;
857 uint64_t hg2cc:1;
858 uint64_t hg2fld:1;
859 uint64_t undat:1;
860 uint64_t uneop:1;
861 uint64_t unsop:1;
862 uint64_t bad_term:1;
863 uint64_t bad_seq:1;
864 uint64_t rem_fault:1;
865 uint64_t loc_fault:1;
866 uint64_t pause_drp:1;
867 uint64_t reserved_16_18:3;
868 uint64_t ifgerr:1;
869 uint64_t coldet:1;
870 uint64_t falerr:1;
871 uint64_t rsverr:1;
872 uint64_t pcterr:1;
873 uint64_t ovrerr:1;
874 uint64_t reserved_9_9:1;
875 uint64_t skperr:1;
876 uint64_t rcverr:1;
877 uint64_t reserved_5_6:2;
878 uint64_t fcserr:1;
879 uint64_t jabber:1;
880 uint64_t reserved_2_2:1;
881 uint64_t carext:1;
882 uint64_t reserved_0_0:1;
883 } cn52xx;
884 struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
885 struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
886 struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
887 uint64_t reserved_27_63:37;
888 uint64_t undat:1;
889 uint64_t uneop:1;
890 uint64_t unsop:1;
891 uint64_t bad_term:1;
892 uint64_t bad_seq:1;
893 uint64_t rem_fault:1;
894 uint64_t loc_fault:1;
895 uint64_t pause_drp:1;
896 uint64_t reserved_16_18:3;
897 uint64_t ifgerr:1;
898 uint64_t coldet:1;
899 uint64_t falerr:1;
900 uint64_t rsverr:1;
901 uint64_t pcterr:1;
902 uint64_t ovrerr:1;
903 uint64_t reserved_9_9:1;
904 uint64_t skperr:1;
905 uint64_t rcverr:1;
906 uint64_t reserved_5_6:2;
907 uint64_t fcserr:1;
908 uint64_t jabber:1;
909 uint64_t reserved_2_2:1;
910 uint64_t carext:1;
911 uint64_t reserved_0_0:1;
912 } cn56xxp1;
913 struct cvmx_gmxx_rxx_int_en_cn58xx {
914 uint64_t reserved_20_63:44;
915 uint64_t pause_drp:1;
916 uint64_t phy_dupx:1;
917 uint64_t phy_spd:1;
918 uint64_t phy_link:1;
919 uint64_t ifgerr:1;
920 uint64_t coldet:1;
921 uint64_t falerr:1;
922 uint64_t rsverr:1;
923 uint64_t pcterr:1;
924 uint64_t ovrerr:1;
925 uint64_t niberr:1;
926 uint64_t skperr:1;
927 uint64_t rcverr:1;
928 uint64_t lenerr:1;
929 uint64_t alnerr:1;
930 uint64_t fcserr:1;
931 uint64_t jabber:1;
932 uint64_t maxerr:1;
933 uint64_t carext:1;
934 uint64_t minerr:1;
935 } cn58xx;
936 struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
937};
938
939union cvmx_gmxx_rxx_int_reg {
940 uint64_t u64;
941 struct cvmx_gmxx_rxx_int_reg_s {
942 uint64_t reserved_29_63:35;
943 uint64_t hg2cc:1;
944 uint64_t hg2fld:1;
945 uint64_t undat:1;
946 uint64_t uneop:1;
947 uint64_t unsop:1;
948 uint64_t bad_term:1;
949 uint64_t bad_seq:1;
950 uint64_t rem_fault:1;
951 uint64_t loc_fault:1;
952 uint64_t pause_drp:1;
953 uint64_t phy_dupx:1;
954 uint64_t phy_spd:1;
955 uint64_t phy_link:1;
956 uint64_t ifgerr:1;
957 uint64_t coldet:1;
958 uint64_t falerr:1;
959 uint64_t rsverr:1;
960 uint64_t pcterr:1;
961 uint64_t ovrerr:1;
962 uint64_t niberr:1;
963 uint64_t skperr:1;
964 uint64_t rcverr:1;
965 uint64_t lenerr:1;
966 uint64_t alnerr:1;
967 uint64_t fcserr:1;
968 uint64_t jabber:1;
969 uint64_t maxerr:1;
970 uint64_t carext:1;
971 uint64_t minerr:1;
972 } s;
973 struct cvmx_gmxx_rxx_int_reg_cn30xx {
974 uint64_t reserved_19_63:45;
975 uint64_t phy_dupx:1;
976 uint64_t phy_spd:1;
977 uint64_t phy_link:1;
978 uint64_t ifgerr:1;
979 uint64_t coldet:1;
980 uint64_t falerr:1;
981 uint64_t rsverr:1;
982 uint64_t pcterr:1;
983 uint64_t ovrerr:1;
984 uint64_t niberr:1;
985 uint64_t skperr:1;
986 uint64_t rcverr:1;
987 uint64_t lenerr:1;
988 uint64_t alnerr:1;
989 uint64_t fcserr:1;
990 uint64_t jabber:1;
991 uint64_t maxerr:1;
992 uint64_t carext:1;
993 uint64_t minerr:1;
994 } cn30xx;
995 struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
996 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
997 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
998 struct cvmx_gmxx_rxx_int_reg_cn50xx {
999 uint64_t reserved_20_63:44;
1000 uint64_t pause_drp:1;
1001 uint64_t phy_dupx:1;
1002 uint64_t phy_spd:1;
1003 uint64_t phy_link:1;
1004 uint64_t ifgerr:1;
1005 uint64_t coldet:1;
1006 uint64_t falerr:1;
1007 uint64_t rsverr:1;
1008 uint64_t pcterr:1;
1009 uint64_t ovrerr:1;
1010 uint64_t niberr:1;
1011 uint64_t skperr:1;
1012 uint64_t rcverr:1;
1013 uint64_t reserved_6_6:1;
1014 uint64_t alnerr:1;
1015 uint64_t fcserr:1;
1016 uint64_t jabber:1;
1017 uint64_t reserved_2_2:1;
1018 uint64_t carext:1;
1019 uint64_t reserved_0_0:1;
1020 } cn50xx;
1021 struct cvmx_gmxx_rxx_int_reg_cn52xx {
1022 uint64_t reserved_29_63:35;
1023 uint64_t hg2cc:1;
1024 uint64_t hg2fld:1;
1025 uint64_t undat:1;
1026 uint64_t uneop:1;
1027 uint64_t unsop:1;
1028 uint64_t bad_term:1;
1029 uint64_t bad_seq:1;
1030 uint64_t rem_fault:1;
1031 uint64_t loc_fault:1;
1032 uint64_t pause_drp:1;
1033 uint64_t reserved_16_18:3;
1034 uint64_t ifgerr:1;
1035 uint64_t coldet:1;
1036 uint64_t falerr:1;
1037 uint64_t rsverr:1;
1038 uint64_t pcterr:1;
1039 uint64_t ovrerr:1;
1040 uint64_t reserved_9_9:1;
1041 uint64_t skperr:1;
1042 uint64_t rcverr:1;
1043 uint64_t reserved_5_6:2;
1044 uint64_t fcserr:1;
1045 uint64_t jabber:1;
1046 uint64_t reserved_2_2:1;
1047 uint64_t carext:1;
1048 uint64_t reserved_0_0:1;
1049 } cn52xx;
1050 struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1;
1051 struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx;
1052 struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
1053 uint64_t reserved_27_63:37;
1054 uint64_t undat:1;
1055 uint64_t uneop:1;
1056 uint64_t unsop:1;
1057 uint64_t bad_term:1;
1058 uint64_t bad_seq:1;
1059 uint64_t rem_fault:1;
1060 uint64_t loc_fault:1;
1061 uint64_t pause_drp:1;
1062 uint64_t reserved_16_18:3;
1063 uint64_t ifgerr:1;
1064 uint64_t coldet:1;
1065 uint64_t falerr:1;
1066 uint64_t rsverr:1;
1067 uint64_t pcterr:1;
1068 uint64_t ovrerr:1;
1069 uint64_t reserved_9_9:1;
1070 uint64_t skperr:1;
1071 uint64_t rcverr:1;
1072 uint64_t reserved_5_6:2;
1073 uint64_t fcserr:1;
1074 uint64_t jabber:1;
1075 uint64_t reserved_2_2:1;
1076 uint64_t carext:1;
1077 uint64_t reserved_0_0:1;
1078 } cn56xxp1;
1079 struct cvmx_gmxx_rxx_int_reg_cn58xx {
1080 uint64_t reserved_20_63:44;
1081 uint64_t pause_drp:1;
1082 uint64_t phy_dupx:1;
1083 uint64_t phy_spd:1;
1084 uint64_t phy_link:1;
1085 uint64_t ifgerr:1;
1086 uint64_t coldet:1;
1087 uint64_t falerr:1;
1088 uint64_t rsverr:1;
1089 uint64_t pcterr:1;
1090 uint64_t ovrerr:1;
1091 uint64_t niberr:1;
1092 uint64_t skperr:1;
1093 uint64_t rcverr:1;
1094 uint64_t lenerr:1;
1095 uint64_t alnerr:1;
1096 uint64_t fcserr:1;
1097 uint64_t jabber:1;
1098 uint64_t maxerr:1;
1099 uint64_t carext:1;
1100 uint64_t minerr:1;
1101 } cn58xx;
1102 struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1;
1103};
1104
1105union cvmx_gmxx_rxx_jabber {
1106 uint64_t u64;
1107 struct cvmx_gmxx_rxx_jabber_s {
1108 uint64_t reserved_16_63:48;
1109 uint64_t cnt:16;
1110 } s;
1111 struct cvmx_gmxx_rxx_jabber_s cn30xx;
1112 struct cvmx_gmxx_rxx_jabber_s cn31xx;
1113 struct cvmx_gmxx_rxx_jabber_s cn38xx;
1114 struct cvmx_gmxx_rxx_jabber_s cn38xxp2;
1115 struct cvmx_gmxx_rxx_jabber_s cn50xx;
1116 struct cvmx_gmxx_rxx_jabber_s cn52xx;
1117 struct cvmx_gmxx_rxx_jabber_s cn52xxp1;
1118 struct cvmx_gmxx_rxx_jabber_s cn56xx;
1119 struct cvmx_gmxx_rxx_jabber_s cn56xxp1;
1120 struct cvmx_gmxx_rxx_jabber_s cn58xx;
1121 struct cvmx_gmxx_rxx_jabber_s cn58xxp1;
1122};
1123
1124union cvmx_gmxx_rxx_pause_drop_time {
1125 uint64_t u64;
1126 struct cvmx_gmxx_rxx_pause_drop_time_s {
1127 uint64_t reserved_16_63:48;
1128 uint64_t status:16;
1129 } s;
1130 struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
1131 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
1132 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
1133 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
1134 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
1135 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
1136 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
1137};
1138
1139union cvmx_gmxx_rxx_rx_inbnd {
1140 uint64_t u64;
1141 struct cvmx_gmxx_rxx_rx_inbnd_s {
1142 uint64_t reserved_4_63:60;
1143 uint64_t duplex:1;
1144 uint64_t speed:2;
1145 uint64_t status:1;
1146 } s;
1147 struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx;
1148 struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx;
1149 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx;
1150 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2;
1151 struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx;
1152 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx;
1153 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1;
1154};
1155
1156union cvmx_gmxx_rxx_stats_ctl {
1157 uint64_t u64;
1158 struct cvmx_gmxx_rxx_stats_ctl_s {
1159 uint64_t reserved_1_63:63;
1160 uint64_t rd_clr:1;
1161 } s;
1162 struct cvmx_gmxx_rxx_stats_ctl_s cn30xx;
1163 struct cvmx_gmxx_rxx_stats_ctl_s cn31xx;
1164 struct cvmx_gmxx_rxx_stats_ctl_s cn38xx;
1165 struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2;
1166 struct cvmx_gmxx_rxx_stats_ctl_s cn50xx;
1167 struct cvmx_gmxx_rxx_stats_ctl_s cn52xx;
1168 struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1;
1169 struct cvmx_gmxx_rxx_stats_ctl_s cn56xx;
1170 struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1;
1171 struct cvmx_gmxx_rxx_stats_ctl_s cn58xx;
1172 struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1;
1173};
1174
1175union cvmx_gmxx_rxx_stats_octs {
1176 uint64_t u64;
1177 struct cvmx_gmxx_rxx_stats_octs_s {
1178 uint64_t reserved_48_63:16;
1179 uint64_t cnt:48;
1180 } s;
1181 struct cvmx_gmxx_rxx_stats_octs_s cn30xx;
1182 struct cvmx_gmxx_rxx_stats_octs_s cn31xx;
1183 struct cvmx_gmxx_rxx_stats_octs_s cn38xx;
1184 struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2;
1185 struct cvmx_gmxx_rxx_stats_octs_s cn50xx;
1186 struct cvmx_gmxx_rxx_stats_octs_s cn52xx;
1187 struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1;
1188 struct cvmx_gmxx_rxx_stats_octs_s cn56xx;
1189 struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1;
1190 struct cvmx_gmxx_rxx_stats_octs_s cn58xx;
1191 struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1;
1192};
1193
1194union cvmx_gmxx_rxx_stats_octs_ctl {
1195 uint64_t u64;
1196 struct cvmx_gmxx_rxx_stats_octs_ctl_s {
1197 uint64_t reserved_48_63:16;
1198 uint64_t cnt:48;
1199 } s;
1200 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
1201 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
1202 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
1203 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
1204 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
1205 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
1206 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
1207 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
1208 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
1209 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
1210 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
1211};
1212
1213union cvmx_gmxx_rxx_stats_octs_dmac {
1214 uint64_t u64;
1215 struct cvmx_gmxx_rxx_stats_octs_dmac_s {
1216 uint64_t reserved_48_63:16;
1217 uint64_t cnt:48;
1218 } s;
1219 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
1220 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
1221 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
1222 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
1223 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
1224 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
1225 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
1226 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
1227 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
1228 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
1229 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
1230};
1231
1232union cvmx_gmxx_rxx_stats_octs_drp {
1233 uint64_t u64;
1234 struct cvmx_gmxx_rxx_stats_octs_drp_s {
1235 uint64_t reserved_48_63:16;
1236 uint64_t cnt:48;
1237 } s;
1238 struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
1239 struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
1240 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
1241 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
1242 struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
1243 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
1244 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
1245 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
1246 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
1247 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
1248 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
1249};
1250
1251union cvmx_gmxx_rxx_stats_pkts {
1252 uint64_t u64;
1253 struct cvmx_gmxx_rxx_stats_pkts_s {
1254 uint64_t reserved_32_63:32;
1255 uint64_t cnt:32;
1256 } s;
1257 struct cvmx_gmxx_rxx_stats_pkts_s cn30xx;
1258 struct cvmx_gmxx_rxx_stats_pkts_s cn31xx;
1259 struct cvmx_gmxx_rxx_stats_pkts_s cn38xx;
1260 struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2;
1261 struct cvmx_gmxx_rxx_stats_pkts_s cn50xx;
1262 struct cvmx_gmxx_rxx_stats_pkts_s cn52xx;
1263 struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1;
1264 struct cvmx_gmxx_rxx_stats_pkts_s cn56xx;
1265 struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1;
1266 struct cvmx_gmxx_rxx_stats_pkts_s cn58xx;
1267 struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1;
1268};
1269
1270union cvmx_gmxx_rxx_stats_pkts_bad {
1271 uint64_t u64;
1272 struct cvmx_gmxx_rxx_stats_pkts_bad_s {
1273 uint64_t reserved_32_63:32;
1274 uint64_t cnt:32;
1275 } s;
1276 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
1277 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
1278 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
1279 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
1280 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
1281 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
1282 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
1283 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
1284 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
1285 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
1286 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
1287};
1288
1289union cvmx_gmxx_rxx_stats_pkts_ctl {
1290 uint64_t u64;
1291 struct cvmx_gmxx_rxx_stats_pkts_ctl_s {
1292 uint64_t reserved_32_63:32;
1293 uint64_t cnt:32;
1294 } s;
1295 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
1296 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
1297 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
1298 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
1299 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
1300 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
1301 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
1302 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
1303 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
1304 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
1305 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
1306};
1307
1308union cvmx_gmxx_rxx_stats_pkts_dmac {
1309 uint64_t u64;
1310 struct cvmx_gmxx_rxx_stats_pkts_dmac_s {
1311 uint64_t reserved_32_63:32;
1312 uint64_t cnt:32;
1313 } s;
1314 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
1315 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
1316 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
1317 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
1318 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
1319 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
1320 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
1321 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
1322 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
1323 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
1324 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
1325};
1326
1327union cvmx_gmxx_rxx_stats_pkts_drp {
1328 uint64_t u64;
1329 struct cvmx_gmxx_rxx_stats_pkts_drp_s {
1330 uint64_t reserved_32_63:32;
1331 uint64_t cnt:32;
1332 } s;
1333 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
1334 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
1335 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
1336 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
1337 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
1338 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
1339 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
1340 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
1341 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
1342 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
1343 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
1344};
1345
1346union cvmx_gmxx_rxx_udd_skp {
1347 uint64_t u64;
1348 struct cvmx_gmxx_rxx_udd_skp_s {
1349 uint64_t reserved_9_63:55;
1350 uint64_t fcssel:1;
1351 uint64_t reserved_7_7:1;
1352 uint64_t len:7;
1353 } s;
1354 struct cvmx_gmxx_rxx_udd_skp_s cn30xx;
1355 struct cvmx_gmxx_rxx_udd_skp_s cn31xx;
1356 struct cvmx_gmxx_rxx_udd_skp_s cn38xx;
1357 struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2;
1358 struct cvmx_gmxx_rxx_udd_skp_s cn50xx;
1359 struct cvmx_gmxx_rxx_udd_skp_s cn52xx;
1360 struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1;
1361 struct cvmx_gmxx_rxx_udd_skp_s cn56xx;
1362 struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1;
1363 struct cvmx_gmxx_rxx_udd_skp_s cn58xx;
1364 struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1;
1365};
1366
1367union cvmx_gmxx_rx_bp_dropx {
1368 uint64_t u64;
1369 struct cvmx_gmxx_rx_bp_dropx_s {
1370 uint64_t reserved_6_63:58;
1371 uint64_t mark:6;
1372 } s;
1373 struct cvmx_gmxx_rx_bp_dropx_s cn30xx;
1374 struct cvmx_gmxx_rx_bp_dropx_s cn31xx;
1375 struct cvmx_gmxx_rx_bp_dropx_s cn38xx;
1376 struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2;
1377 struct cvmx_gmxx_rx_bp_dropx_s cn50xx;
1378 struct cvmx_gmxx_rx_bp_dropx_s cn52xx;
1379 struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1;
1380 struct cvmx_gmxx_rx_bp_dropx_s cn56xx;
1381 struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1;
1382 struct cvmx_gmxx_rx_bp_dropx_s cn58xx;
1383 struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1;
1384};
1385
1386union cvmx_gmxx_rx_bp_offx {
1387 uint64_t u64;
1388 struct cvmx_gmxx_rx_bp_offx_s {
1389 uint64_t reserved_6_63:58;
1390 uint64_t mark:6;
1391 } s;
1392 struct cvmx_gmxx_rx_bp_offx_s cn30xx;
1393 struct cvmx_gmxx_rx_bp_offx_s cn31xx;
1394 struct cvmx_gmxx_rx_bp_offx_s cn38xx;
1395 struct cvmx_gmxx_rx_bp_offx_s cn38xxp2;
1396 struct cvmx_gmxx_rx_bp_offx_s cn50xx;
1397 struct cvmx_gmxx_rx_bp_offx_s cn52xx;
1398 struct cvmx_gmxx_rx_bp_offx_s cn52xxp1;
1399 struct cvmx_gmxx_rx_bp_offx_s cn56xx;
1400 struct cvmx_gmxx_rx_bp_offx_s cn56xxp1;
1401 struct cvmx_gmxx_rx_bp_offx_s cn58xx;
1402 struct cvmx_gmxx_rx_bp_offx_s cn58xxp1;
1403};
1404
1405union cvmx_gmxx_rx_bp_onx {
1406 uint64_t u64;
1407 struct cvmx_gmxx_rx_bp_onx_s {
1408 uint64_t reserved_9_63:55;
1409 uint64_t mark:9;
1410 } s;
1411 struct cvmx_gmxx_rx_bp_onx_s cn30xx;
1412 struct cvmx_gmxx_rx_bp_onx_s cn31xx;
1413 struct cvmx_gmxx_rx_bp_onx_s cn38xx;
1414 struct cvmx_gmxx_rx_bp_onx_s cn38xxp2;
1415 struct cvmx_gmxx_rx_bp_onx_s cn50xx;
1416 struct cvmx_gmxx_rx_bp_onx_s cn52xx;
1417 struct cvmx_gmxx_rx_bp_onx_s cn52xxp1;
1418 struct cvmx_gmxx_rx_bp_onx_s cn56xx;
1419 struct cvmx_gmxx_rx_bp_onx_s cn56xxp1;
1420 struct cvmx_gmxx_rx_bp_onx_s cn58xx;
1421 struct cvmx_gmxx_rx_bp_onx_s cn58xxp1;
1422};
1423
1424union cvmx_gmxx_rx_hg2_status {
1425 uint64_t u64;
1426 struct cvmx_gmxx_rx_hg2_status_s {
1427 uint64_t reserved_48_63:16;
1428 uint64_t phtim2go:16;
1429 uint64_t xof:16;
1430 uint64_t lgtim2go:16;
1431 } s;
1432 struct cvmx_gmxx_rx_hg2_status_s cn52xx;
1433 struct cvmx_gmxx_rx_hg2_status_s cn52xxp1;
1434 struct cvmx_gmxx_rx_hg2_status_s cn56xx;
1435};
1436
1437union cvmx_gmxx_rx_pass_en {
1438 uint64_t u64;
1439 struct cvmx_gmxx_rx_pass_en_s {
1440 uint64_t reserved_16_63:48;
1441 uint64_t en:16;
1442 } s;
1443 struct cvmx_gmxx_rx_pass_en_s cn38xx;
1444 struct cvmx_gmxx_rx_pass_en_s cn38xxp2;
1445 struct cvmx_gmxx_rx_pass_en_s cn58xx;
1446 struct cvmx_gmxx_rx_pass_en_s cn58xxp1;
1447};
1448
1449union cvmx_gmxx_rx_pass_mapx {
1450 uint64_t u64;
1451 struct cvmx_gmxx_rx_pass_mapx_s {
1452 uint64_t reserved_4_63:60;
1453 uint64_t dprt:4;
1454 } s;
1455 struct cvmx_gmxx_rx_pass_mapx_s cn38xx;
1456 struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2;
1457 struct cvmx_gmxx_rx_pass_mapx_s cn58xx;
1458 struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1;
1459};
1460
1461union cvmx_gmxx_rx_prt_info {
1462 uint64_t u64;
1463 struct cvmx_gmxx_rx_prt_info_s {
1464 uint64_t reserved_32_63:32;
1465 uint64_t drop:16;
1466 uint64_t commit:16;
1467 } s;
1468 struct cvmx_gmxx_rx_prt_info_cn30xx {
1469 uint64_t reserved_19_63:45;
1470 uint64_t drop:3;
1471 uint64_t reserved_3_15:13;
1472 uint64_t commit:3;
1473 } cn30xx;
1474 struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx;
1475 struct cvmx_gmxx_rx_prt_info_s cn38xx;
1476 struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx;
1477 struct cvmx_gmxx_rx_prt_info_cn52xx {
1478 uint64_t reserved_20_63:44;
1479 uint64_t drop:4;
1480 uint64_t reserved_4_15:12;
1481 uint64_t commit:4;
1482 } cn52xx;
1483 struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1;
1484 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx;
1485 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1;
1486 struct cvmx_gmxx_rx_prt_info_s cn58xx;
1487 struct cvmx_gmxx_rx_prt_info_s cn58xxp1;
1488};
1489
1490union cvmx_gmxx_rx_prts {
1491 uint64_t u64;
1492 struct cvmx_gmxx_rx_prts_s {
1493 uint64_t reserved_3_63:61;
1494 uint64_t prts:3;
1495 } s;
1496 struct cvmx_gmxx_rx_prts_s cn30xx;
1497 struct cvmx_gmxx_rx_prts_s cn31xx;
1498 struct cvmx_gmxx_rx_prts_s cn38xx;
1499 struct cvmx_gmxx_rx_prts_s cn38xxp2;
1500 struct cvmx_gmxx_rx_prts_s cn50xx;
1501 struct cvmx_gmxx_rx_prts_s cn52xx;
1502 struct cvmx_gmxx_rx_prts_s cn52xxp1;
1503 struct cvmx_gmxx_rx_prts_s cn56xx;
1504 struct cvmx_gmxx_rx_prts_s cn56xxp1;
1505 struct cvmx_gmxx_rx_prts_s cn58xx;
1506 struct cvmx_gmxx_rx_prts_s cn58xxp1;
1507};
1508
1509union cvmx_gmxx_rx_tx_status {
1510 uint64_t u64;
1511 struct cvmx_gmxx_rx_tx_status_s {
1512 uint64_t reserved_7_63:57;
1513 uint64_t tx:3;
1514 uint64_t reserved_3_3:1;
1515 uint64_t rx:3;
1516 } s;
1517 struct cvmx_gmxx_rx_tx_status_s cn30xx;
1518 struct cvmx_gmxx_rx_tx_status_s cn31xx;
1519 struct cvmx_gmxx_rx_tx_status_s cn50xx;
1520};
1521
1522union cvmx_gmxx_rx_xaui_bad_col {
1523 uint64_t u64;
1524 struct cvmx_gmxx_rx_xaui_bad_col_s {
1525 uint64_t reserved_40_63:24;
1526 uint64_t val:1;
1527 uint64_t state:3;
1528 uint64_t lane_rxc:4;
1529 uint64_t lane_rxd:32;
1530 } s;
1531 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx;
1532 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1;
1533 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx;
1534 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1;
1535};
1536
1537union cvmx_gmxx_rx_xaui_ctl {
1538 uint64_t u64;
1539 struct cvmx_gmxx_rx_xaui_ctl_s {
1540 uint64_t reserved_2_63:62;
1541 uint64_t status:2;
1542 } s;
1543 struct cvmx_gmxx_rx_xaui_ctl_s cn52xx;
1544 struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1;
1545 struct cvmx_gmxx_rx_xaui_ctl_s cn56xx;
1546 struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1;
1547};
1548
1549union cvmx_gmxx_smacx {
1550 uint64_t u64;
1551 struct cvmx_gmxx_smacx_s {
1552 uint64_t reserved_48_63:16;
1553 uint64_t smac:48;
1554 } s;
1555 struct cvmx_gmxx_smacx_s cn30xx;
1556 struct cvmx_gmxx_smacx_s cn31xx;
1557 struct cvmx_gmxx_smacx_s cn38xx;
1558 struct cvmx_gmxx_smacx_s cn38xxp2;
1559 struct cvmx_gmxx_smacx_s cn50xx;
1560 struct cvmx_gmxx_smacx_s cn52xx;
1561 struct cvmx_gmxx_smacx_s cn52xxp1;
1562 struct cvmx_gmxx_smacx_s cn56xx;
1563 struct cvmx_gmxx_smacx_s cn56xxp1;
1564 struct cvmx_gmxx_smacx_s cn58xx;
1565 struct cvmx_gmxx_smacx_s cn58xxp1;
1566};
1567
1568union cvmx_gmxx_stat_bp {
1569 uint64_t u64;
1570 struct cvmx_gmxx_stat_bp_s {
1571 uint64_t reserved_17_63:47;
1572 uint64_t bp:1;
1573 uint64_t cnt:16;
1574 } s;
1575 struct cvmx_gmxx_stat_bp_s cn30xx;
1576 struct cvmx_gmxx_stat_bp_s cn31xx;
1577 struct cvmx_gmxx_stat_bp_s cn38xx;
1578 struct cvmx_gmxx_stat_bp_s cn38xxp2;
1579 struct cvmx_gmxx_stat_bp_s cn50xx;
1580 struct cvmx_gmxx_stat_bp_s cn52xx;
1581 struct cvmx_gmxx_stat_bp_s cn52xxp1;
1582 struct cvmx_gmxx_stat_bp_s cn56xx;
1583 struct cvmx_gmxx_stat_bp_s cn56xxp1;
1584 struct cvmx_gmxx_stat_bp_s cn58xx;
1585 struct cvmx_gmxx_stat_bp_s cn58xxp1;
1586};
1587
1588union cvmx_gmxx_txx_append {
1589 uint64_t u64;
1590 struct cvmx_gmxx_txx_append_s {
1591 uint64_t reserved_4_63:60;
1592 uint64_t force_fcs:1;
1593 uint64_t fcs:1;
1594 uint64_t pad:1;
1595 uint64_t preamble:1;
1596 } s;
1597 struct cvmx_gmxx_txx_append_s cn30xx;
1598 struct cvmx_gmxx_txx_append_s cn31xx;
1599 struct cvmx_gmxx_txx_append_s cn38xx;
1600 struct cvmx_gmxx_txx_append_s cn38xxp2;
1601 struct cvmx_gmxx_txx_append_s cn50xx;
1602 struct cvmx_gmxx_txx_append_s cn52xx;
1603 struct cvmx_gmxx_txx_append_s cn52xxp1;
1604 struct cvmx_gmxx_txx_append_s cn56xx;
1605 struct cvmx_gmxx_txx_append_s cn56xxp1;
1606 struct cvmx_gmxx_txx_append_s cn58xx;
1607 struct cvmx_gmxx_txx_append_s cn58xxp1;
1608};
1609
1610union cvmx_gmxx_txx_burst {
1611 uint64_t u64;
1612 struct cvmx_gmxx_txx_burst_s {
1613 uint64_t reserved_16_63:48;
1614 uint64_t burst:16;
1615 } s;
1616 struct cvmx_gmxx_txx_burst_s cn30xx;
1617 struct cvmx_gmxx_txx_burst_s cn31xx;
1618 struct cvmx_gmxx_txx_burst_s cn38xx;
1619 struct cvmx_gmxx_txx_burst_s cn38xxp2;
1620 struct cvmx_gmxx_txx_burst_s cn50xx;
1621 struct cvmx_gmxx_txx_burst_s cn52xx;
1622 struct cvmx_gmxx_txx_burst_s cn52xxp1;
1623 struct cvmx_gmxx_txx_burst_s cn56xx;
1624 struct cvmx_gmxx_txx_burst_s cn56xxp1;
1625 struct cvmx_gmxx_txx_burst_s cn58xx;
1626 struct cvmx_gmxx_txx_burst_s cn58xxp1;
1627};
1628
1629union cvmx_gmxx_txx_cbfc_xoff {
1630 uint64_t u64;
1631 struct cvmx_gmxx_txx_cbfc_xoff_s {
1632 uint64_t reserved_16_63:48;
1633 uint64_t xoff:16;
1634 } s;
1635 struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx;
1636 struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx;
1637};
1638
1639union cvmx_gmxx_txx_cbfc_xon {
1640 uint64_t u64;
1641 struct cvmx_gmxx_txx_cbfc_xon_s {
1642 uint64_t reserved_16_63:48;
1643 uint64_t xon:16;
1644 } s;
1645 struct cvmx_gmxx_txx_cbfc_xon_s cn52xx;
1646 struct cvmx_gmxx_txx_cbfc_xon_s cn56xx;
1647};
1648
1649union cvmx_gmxx_txx_clk {
1650 uint64_t u64;
1651 struct cvmx_gmxx_txx_clk_s {
1652 uint64_t reserved_6_63:58;
1653 uint64_t clk_cnt:6;
1654 } s;
1655 struct cvmx_gmxx_txx_clk_s cn30xx;
1656 struct cvmx_gmxx_txx_clk_s cn31xx;
1657 struct cvmx_gmxx_txx_clk_s cn38xx;
1658 struct cvmx_gmxx_txx_clk_s cn38xxp2;
1659 struct cvmx_gmxx_txx_clk_s cn50xx;
1660 struct cvmx_gmxx_txx_clk_s cn58xx;
1661 struct cvmx_gmxx_txx_clk_s cn58xxp1;
1662};
1663
1664union cvmx_gmxx_txx_ctl {
1665 uint64_t u64;
1666 struct cvmx_gmxx_txx_ctl_s {
1667 uint64_t reserved_2_63:62;
1668 uint64_t xsdef_en:1;
1669 uint64_t xscol_en:1;
1670 } s;
1671 struct cvmx_gmxx_txx_ctl_s cn30xx;
1672 struct cvmx_gmxx_txx_ctl_s cn31xx;
1673 struct cvmx_gmxx_txx_ctl_s cn38xx;
1674 struct cvmx_gmxx_txx_ctl_s cn38xxp2;
1675 struct cvmx_gmxx_txx_ctl_s cn50xx;
1676 struct cvmx_gmxx_txx_ctl_s cn52xx;
1677 struct cvmx_gmxx_txx_ctl_s cn52xxp1;
1678 struct cvmx_gmxx_txx_ctl_s cn56xx;
1679 struct cvmx_gmxx_txx_ctl_s cn56xxp1;
1680 struct cvmx_gmxx_txx_ctl_s cn58xx;
1681 struct cvmx_gmxx_txx_ctl_s cn58xxp1;
1682};
1683
1684union cvmx_gmxx_txx_min_pkt {
1685 uint64_t u64;
1686 struct cvmx_gmxx_txx_min_pkt_s {
1687 uint64_t reserved_8_63:56;
1688 uint64_t min_size:8;
1689 } s;
1690 struct cvmx_gmxx_txx_min_pkt_s cn30xx;
1691 struct cvmx_gmxx_txx_min_pkt_s cn31xx;
1692 struct cvmx_gmxx_txx_min_pkt_s cn38xx;
1693 struct cvmx_gmxx_txx_min_pkt_s cn38xxp2;
1694 struct cvmx_gmxx_txx_min_pkt_s cn50xx;
1695 struct cvmx_gmxx_txx_min_pkt_s cn52xx;
1696 struct cvmx_gmxx_txx_min_pkt_s cn52xxp1;
1697 struct cvmx_gmxx_txx_min_pkt_s cn56xx;
1698 struct cvmx_gmxx_txx_min_pkt_s cn56xxp1;
1699 struct cvmx_gmxx_txx_min_pkt_s cn58xx;
1700 struct cvmx_gmxx_txx_min_pkt_s cn58xxp1;
1701};
1702
1703union cvmx_gmxx_txx_pause_pkt_interval {
1704 uint64_t u64;
1705 struct cvmx_gmxx_txx_pause_pkt_interval_s {
1706 uint64_t reserved_16_63:48;
1707 uint64_t interval:16;
1708 } s;
1709 struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
1710 struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
1711 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
1712 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
1713 struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
1714 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
1715 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
1716 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
1717 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
1718 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
1719 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
1720};
1721
1722union cvmx_gmxx_txx_pause_pkt_time {
1723 uint64_t u64;
1724 struct cvmx_gmxx_txx_pause_pkt_time_s {
1725 uint64_t reserved_16_63:48;
1726 uint64_t time:16;
1727 } s;
1728 struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
1729 struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
1730 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
1731 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
1732 struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
1733 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
1734 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
1735 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
1736 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
1737 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
1738 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
1739};
1740
1741union cvmx_gmxx_txx_pause_togo {
1742 uint64_t u64;
1743 struct cvmx_gmxx_txx_pause_togo_s {
1744 uint64_t reserved_32_63:32;
1745 uint64_t msg_time:16;
1746 uint64_t time:16;
1747 } s;
1748 struct cvmx_gmxx_txx_pause_togo_cn30xx {
1749 uint64_t reserved_16_63:48;
1750 uint64_t time:16;
1751 } cn30xx;
1752 struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
1753 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
1754 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
1755 struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
1756 struct cvmx_gmxx_txx_pause_togo_s cn52xx;
1757 struct cvmx_gmxx_txx_pause_togo_s cn52xxp1;
1758 struct cvmx_gmxx_txx_pause_togo_s cn56xx;
1759 struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
1760 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
1761 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
1762};
1763
1764union cvmx_gmxx_txx_pause_zero {
1765 uint64_t u64;
1766 struct cvmx_gmxx_txx_pause_zero_s {
1767 uint64_t reserved_1_63:63;
1768 uint64_t send:1;
1769 } s;
1770 struct cvmx_gmxx_txx_pause_zero_s cn30xx;
1771 struct cvmx_gmxx_txx_pause_zero_s cn31xx;
1772 struct cvmx_gmxx_txx_pause_zero_s cn38xx;
1773 struct cvmx_gmxx_txx_pause_zero_s cn38xxp2;
1774 struct cvmx_gmxx_txx_pause_zero_s cn50xx;
1775 struct cvmx_gmxx_txx_pause_zero_s cn52xx;
1776 struct cvmx_gmxx_txx_pause_zero_s cn52xxp1;
1777 struct cvmx_gmxx_txx_pause_zero_s cn56xx;
1778 struct cvmx_gmxx_txx_pause_zero_s cn56xxp1;
1779 struct cvmx_gmxx_txx_pause_zero_s cn58xx;
1780 struct cvmx_gmxx_txx_pause_zero_s cn58xxp1;
1781};
1782
1783union cvmx_gmxx_txx_sgmii_ctl {
1784 uint64_t u64;
1785 struct cvmx_gmxx_txx_sgmii_ctl_s {
1786 uint64_t reserved_1_63:63;
1787 uint64_t align:1;
1788 } s;
1789 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx;
1790 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1;
1791 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx;
1792 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1;
1793};
1794
1795union cvmx_gmxx_txx_slot {
1796 uint64_t u64;
1797 struct cvmx_gmxx_txx_slot_s {
1798 uint64_t reserved_10_63:54;
1799 uint64_t slot:10;
1800 } s;
1801 struct cvmx_gmxx_txx_slot_s cn30xx;
1802 struct cvmx_gmxx_txx_slot_s cn31xx;
1803 struct cvmx_gmxx_txx_slot_s cn38xx;
1804 struct cvmx_gmxx_txx_slot_s cn38xxp2;
1805 struct cvmx_gmxx_txx_slot_s cn50xx;
1806 struct cvmx_gmxx_txx_slot_s cn52xx;
1807 struct cvmx_gmxx_txx_slot_s cn52xxp1;
1808 struct cvmx_gmxx_txx_slot_s cn56xx;
1809 struct cvmx_gmxx_txx_slot_s cn56xxp1;
1810 struct cvmx_gmxx_txx_slot_s cn58xx;
1811 struct cvmx_gmxx_txx_slot_s cn58xxp1;
1812};
1813
1814union cvmx_gmxx_txx_soft_pause {
1815 uint64_t u64;
1816 struct cvmx_gmxx_txx_soft_pause_s {
1817 uint64_t reserved_16_63:48;
1818 uint64_t time:16;
1819 } s;
1820 struct cvmx_gmxx_txx_soft_pause_s cn30xx;
1821 struct cvmx_gmxx_txx_soft_pause_s cn31xx;
1822 struct cvmx_gmxx_txx_soft_pause_s cn38xx;
1823 struct cvmx_gmxx_txx_soft_pause_s cn38xxp2;
1824 struct cvmx_gmxx_txx_soft_pause_s cn50xx;
1825 struct cvmx_gmxx_txx_soft_pause_s cn52xx;
1826 struct cvmx_gmxx_txx_soft_pause_s cn52xxp1;
1827 struct cvmx_gmxx_txx_soft_pause_s cn56xx;
1828 struct cvmx_gmxx_txx_soft_pause_s cn56xxp1;
1829 struct cvmx_gmxx_txx_soft_pause_s cn58xx;
1830 struct cvmx_gmxx_txx_soft_pause_s cn58xxp1;
1831};
1832
1833union cvmx_gmxx_txx_stat0 {
1834 uint64_t u64;
1835 struct cvmx_gmxx_txx_stat0_s {
1836 uint64_t xsdef:32;
1837 uint64_t xscol:32;
1838 } s;
1839 struct cvmx_gmxx_txx_stat0_s cn30xx;
1840 struct cvmx_gmxx_txx_stat0_s cn31xx;
1841 struct cvmx_gmxx_txx_stat0_s cn38xx;
1842 struct cvmx_gmxx_txx_stat0_s cn38xxp2;
1843 struct cvmx_gmxx_txx_stat0_s cn50xx;
1844 struct cvmx_gmxx_txx_stat0_s cn52xx;
1845 struct cvmx_gmxx_txx_stat0_s cn52xxp1;
1846 struct cvmx_gmxx_txx_stat0_s cn56xx;
1847 struct cvmx_gmxx_txx_stat0_s cn56xxp1;
1848 struct cvmx_gmxx_txx_stat0_s cn58xx;
1849 struct cvmx_gmxx_txx_stat0_s cn58xxp1;
1850};
1851
1852union cvmx_gmxx_txx_stat1 {
1853 uint64_t u64;
1854 struct cvmx_gmxx_txx_stat1_s {
1855 uint64_t scol:32;
1856 uint64_t mcol:32;
1857 } s;
1858 struct cvmx_gmxx_txx_stat1_s cn30xx;
1859 struct cvmx_gmxx_txx_stat1_s cn31xx;
1860 struct cvmx_gmxx_txx_stat1_s cn38xx;
1861 struct cvmx_gmxx_txx_stat1_s cn38xxp2;
1862 struct cvmx_gmxx_txx_stat1_s cn50xx;
1863 struct cvmx_gmxx_txx_stat1_s cn52xx;
1864 struct cvmx_gmxx_txx_stat1_s cn52xxp1;
1865 struct cvmx_gmxx_txx_stat1_s cn56xx;
1866 struct cvmx_gmxx_txx_stat1_s cn56xxp1;
1867 struct cvmx_gmxx_txx_stat1_s cn58xx;
1868 struct cvmx_gmxx_txx_stat1_s cn58xxp1;
1869};
1870
1871union cvmx_gmxx_txx_stat2 {
1872 uint64_t u64;
1873 struct cvmx_gmxx_txx_stat2_s {
1874 uint64_t reserved_48_63:16;
1875 uint64_t octs:48;
1876 } s;
1877 struct cvmx_gmxx_txx_stat2_s cn30xx;
1878 struct cvmx_gmxx_txx_stat2_s cn31xx;
1879 struct cvmx_gmxx_txx_stat2_s cn38xx;
1880 struct cvmx_gmxx_txx_stat2_s cn38xxp2;
1881 struct cvmx_gmxx_txx_stat2_s cn50xx;
1882 struct cvmx_gmxx_txx_stat2_s cn52xx;
1883 struct cvmx_gmxx_txx_stat2_s cn52xxp1;
1884 struct cvmx_gmxx_txx_stat2_s cn56xx;
1885 struct cvmx_gmxx_txx_stat2_s cn56xxp1;
1886 struct cvmx_gmxx_txx_stat2_s cn58xx;
1887 struct cvmx_gmxx_txx_stat2_s cn58xxp1;
1888};
1889
1890union cvmx_gmxx_txx_stat3 {
1891 uint64_t u64;
1892 struct cvmx_gmxx_txx_stat3_s {
1893 uint64_t reserved_32_63:32;
1894 uint64_t pkts:32;
1895 } s;
1896 struct cvmx_gmxx_txx_stat3_s cn30xx;
1897 struct cvmx_gmxx_txx_stat3_s cn31xx;
1898 struct cvmx_gmxx_txx_stat3_s cn38xx;
1899 struct cvmx_gmxx_txx_stat3_s cn38xxp2;
1900 struct cvmx_gmxx_txx_stat3_s cn50xx;
1901 struct cvmx_gmxx_txx_stat3_s cn52xx;
1902 struct cvmx_gmxx_txx_stat3_s cn52xxp1;
1903 struct cvmx_gmxx_txx_stat3_s cn56xx;
1904 struct cvmx_gmxx_txx_stat3_s cn56xxp1;
1905 struct cvmx_gmxx_txx_stat3_s cn58xx;
1906 struct cvmx_gmxx_txx_stat3_s cn58xxp1;
1907};
1908
1909union cvmx_gmxx_txx_stat4 {
1910 uint64_t u64;
1911 struct cvmx_gmxx_txx_stat4_s {
1912 uint64_t hist1:32;
1913 uint64_t hist0:32;
1914 } s;
1915 struct cvmx_gmxx_txx_stat4_s cn30xx;
1916 struct cvmx_gmxx_txx_stat4_s cn31xx;
1917 struct cvmx_gmxx_txx_stat4_s cn38xx;
1918 struct cvmx_gmxx_txx_stat4_s cn38xxp2;
1919 struct cvmx_gmxx_txx_stat4_s cn50xx;
1920 struct cvmx_gmxx_txx_stat4_s cn52xx;
1921 struct cvmx_gmxx_txx_stat4_s cn52xxp1;
1922 struct cvmx_gmxx_txx_stat4_s cn56xx;
1923 struct cvmx_gmxx_txx_stat4_s cn56xxp1;
1924 struct cvmx_gmxx_txx_stat4_s cn58xx;
1925 struct cvmx_gmxx_txx_stat4_s cn58xxp1;
1926};
1927
1928union cvmx_gmxx_txx_stat5 {
1929 uint64_t u64;
1930 struct cvmx_gmxx_txx_stat5_s {
1931 uint64_t hist3:32;
1932 uint64_t hist2:32;
1933 } s;
1934 struct cvmx_gmxx_txx_stat5_s cn30xx;
1935 struct cvmx_gmxx_txx_stat5_s cn31xx;
1936 struct cvmx_gmxx_txx_stat5_s cn38xx;
1937 struct cvmx_gmxx_txx_stat5_s cn38xxp2;
1938 struct cvmx_gmxx_txx_stat5_s cn50xx;
1939 struct cvmx_gmxx_txx_stat5_s cn52xx;
1940 struct cvmx_gmxx_txx_stat5_s cn52xxp1;
1941 struct cvmx_gmxx_txx_stat5_s cn56xx;
1942 struct cvmx_gmxx_txx_stat5_s cn56xxp1;
1943 struct cvmx_gmxx_txx_stat5_s cn58xx;
1944 struct cvmx_gmxx_txx_stat5_s cn58xxp1;
1945};
1946
1947union cvmx_gmxx_txx_stat6 {
1948 uint64_t u64;
1949 struct cvmx_gmxx_txx_stat6_s {
1950 uint64_t hist5:32;
1951 uint64_t hist4:32;
1952 } s;
1953 struct cvmx_gmxx_txx_stat6_s cn30xx;
1954 struct cvmx_gmxx_txx_stat6_s cn31xx;
1955 struct cvmx_gmxx_txx_stat6_s cn38xx;
1956 struct cvmx_gmxx_txx_stat6_s cn38xxp2;
1957 struct cvmx_gmxx_txx_stat6_s cn50xx;
1958 struct cvmx_gmxx_txx_stat6_s cn52xx;
1959 struct cvmx_gmxx_txx_stat6_s cn52xxp1;
1960 struct cvmx_gmxx_txx_stat6_s cn56xx;
1961 struct cvmx_gmxx_txx_stat6_s cn56xxp1;
1962 struct cvmx_gmxx_txx_stat6_s cn58xx;
1963 struct cvmx_gmxx_txx_stat6_s cn58xxp1;
1964};
1965
1966union cvmx_gmxx_txx_stat7 {
1967 uint64_t u64;
1968 struct cvmx_gmxx_txx_stat7_s {
1969 uint64_t hist7:32;
1970 uint64_t hist6:32;
1971 } s;
1972 struct cvmx_gmxx_txx_stat7_s cn30xx;
1973 struct cvmx_gmxx_txx_stat7_s cn31xx;
1974 struct cvmx_gmxx_txx_stat7_s cn38xx;
1975 struct cvmx_gmxx_txx_stat7_s cn38xxp2;
1976 struct cvmx_gmxx_txx_stat7_s cn50xx;
1977 struct cvmx_gmxx_txx_stat7_s cn52xx;
1978 struct cvmx_gmxx_txx_stat7_s cn52xxp1;
1979 struct cvmx_gmxx_txx_stat7_s cn56xx;
1980 struct cvmx_gmxx_txx_stat7_s cn56xxp1;
1981 struct cvmx_gmxx_txx_stat7_s cn58xx;
1982 struct cvmx_gmxx_txx_stat7_s cn58xxp1;
1983};
1984
1985union cvmx_gmxx_txx_stat8 {
1986 uint64_t u64;
1987 struct cvmx_gmxx_txx_stat8_s {
1988 uint64_t mcst:32;
1989 uint64_t bcst:32;
1990 } s;
1991 struct cvmx_gmxx_txx_stat8_s cn30xx;
1992 struct cvmx_gmxx_txx_stat8_s cn31xx;
1993 struct cvmx_gmxx_txx_stat8_s cn38xx;
1994 struct cvmx_gmxx_txx_stat8_s cn38xxp2;
1995 struct cvmx_gmxx_txx_stat8_s cn50xx;
1996 struct cvmx_gmxx_txx_stat8_s cn52xx;
1997 struct cvmx_gmxx_txx_stat8_s cn52xxp1;
1998 struct cvmx_gmxx_txx_stat8_s cn56xx;
1999 struct cvmx_gmxx_txx_stat8_s cn56xxp1;
2000 struct cvmx_gmxx_txx_stat8_s cn58xx;
2001 struct cvmx_gmxx_txx_stat8_s cn58xxp1;
2002};
2003
2004union cvmx_gmxx_txx_stat9 {
2005 uint64_t u64;
2006 struct cvmx_gmxx_txx_stat9_s {
2007 uint64_t undflw:32;
2008 uint64_t ctl:32;
2009 } s;
2010 struct cvmx_gmxx_txx_stat9_s cn30xx;
2011 struct cvmx_gmxx_txx_stat9_s cn31xx;
2012 struct cvmx_gmxx_txx_stat9_s cn38xx;
2013 struct cvmx_gmxx_txx_stat9_s cn38xxp2;
2014 struct cvmx_gmxx_txx_stat9_s cn50xx;
2015 struct cvmx_gmxx_txx_stat9_s cn52xx;
2016 struct cvmx_gmxx_txx_stat9_s cn52xxp1;
2017 struct cvmx_gmxx_txx_stat9_s cn56xx;
2018 struct cvmx_gmxx_txx_stat9_s cn56xxp1;
2019 struct cvmx_gmxx_txx_stat9_s cn58xx;
2020 struct cvmx_gmxx_txx_stat9_s cn58xxp1;
2021};
2022
2023union cvmx_gmxx_txx_stats_ctl {
2024 uint64_t u64;
2025 struct cvmx_gmxx_txx_stats_ctl_s {
2026 uint64_t reserved_1_63:63;
2027 uint64_t rd_clr:1;
2028 } s;
2029 struct cvmx_gmxx_txx_stats_ctl_s cn30xx;
2030 struct cvmx_gmxx_txx_stats_ctl_s cn31xx;
2031 struct cvmx_gmxx_txx_stats_ctl_s cn38xx;
2032 struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2;
2033 struct cvmx_gmxx_txx_stats_ctl_s cn50xx;
2034 struct cvmx_gmxx_txx_stats_ctl_s cn52xx;
2035 struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1;
2036 struct cvmx_gmxx_txx_stats_ctl_s cn56xx;
2037 struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1;
2038 struct cvmx_gmxx_txx_stats_ctl_s cn58xx;
2039 struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1;
2040};
2041
2042union cvmx_gmxx_txx_thresh {
2043 uint64_t u64;
2044 struct cvmx_gmxx_txx_thresh_s {
2045 uint64_t reserved_9_63:55;
2046 uint64_t cnt:9;
2047 } s;
2048 struct cvmx_gmxx_txx_thresh_cn30xx {
2049 uint64_t reserved_7_63:57;
2050 uint64_t cnt:7;
2051 } cn30xx;
2052 struct cvmx_gmxx_txx_thresh_cn30xx cn31xx;
2053 struct cvmx_gmxx_txx_thresh_s cn38xx;
2054 struct cvmx_gmxx_txx_thresh_s cn38xxp2;
2055 struct cvmx_gmxx_txx_thresh_cn30xx cn50xx;
2056 struct cvmx_gmxx_txx_thresh_s cn52xx;
2057 struct cvmx_gmxx_txx_thresh_s cn52xxp1;
2058 struct cvmx_gmxx_txx_thresh_s cn56xx;
2059 struct cvmx_gmxx_txx_thresh_s cn56xxp1;
2060 struct cvmx_gmxx_txx_thresh_s cn58xx;
2061 struct cvmx_gmxx_txx_thresh_s cn58xxp1;
2062};
2063
2064union cvmx_gmxx_tx_bp {
2065 uint64_t u64;
2066 struct cvmx_gmxx_tx_bp_s {
2067 uint64_t reserved_4_63:60;
2068 uint64_t bp:4;
2069 } s;
2070 struct cvmx_gmxx_tx_bp_cn30xx {
2071 uint64_t reserved_3_63:61;
2072 uint64_t bp:3;
2073 } cn30xx;
2074 struct cvmx_gmxx_tx_bp_cn30xx cn31xx;
2075 struct cvmx_gmxx_tx_bp_s cn38xx;
2076 struct cvmx_gmxx_tx_bp_s cn38xxp2;
2077 struct cvmx_gmxx_tx_bp_cn30xx cn50xx;
2078 struct cvmx_gmxx_tx_bp_s cn52xx;
2079 struct cvmx_gmxx_tx_bp_s cn52xxp1;
2080 struct cvmx_gmxx_tx_bp_s cn56xx;
2081 struct cvmx_gmxx_tx_bp_s cn56xxp1;
2082 struct cvmx_gmxx_tx_bp_s cn58xx;
2083 struct cvmx_gmxx_tx_bp_s cn58xxp1;
2084};
2085
2086union cvmx_gmxx_tx_clk_mskx {
2087 uint64_t u64;
2088 struct cvmx_gmxx_tx_clk_mskx_s {
2089 uint64_t reserved_1_63:63;
2090 uint64_t msk:1;
2091 } s;
2092 struct cvmx_gmxx_tx_clk_mskx_s cn30xx;
2093 struct cvmx_gmxx_tx_clk_mskx_s cn50xx;
2094};
2095
2096union cvmx_gmxx_tx_col_attempt {
2097 uint64_t u64;
2098 struct cvmx_gmxx_tx_col_attempt_s {
2099 uint64_t reserved_5_63:59;
2100 uint64_t limit:5;
2101 } s;
2102 struct cvmx_gmxx_tx_col_attempt_s cn30xx;
2103 struct cvmx_gmxx_tx_col_attempt_s cn31xx;
2104 struct cvmx_gmxx_tx_col_attempt_s cn38xx;
2105 struct cvmx_gmxx_tx_col_attempt_s cn38xxp2;
2106 struct cvmx_gmxx_tx_col_attempt_s cn50xx;
2107 struct cvmx_gmxx_tx_col_attempt_s cn52xx;
2108 struct cvmx_gmxx_tx_col_attempt_s cn52xxp1;
2109 struct cvmx_gmxx_tx_col_attempt_s cn56xx;
2110 struct cvmx_gmxx_tx_col_attempt_s cn56xxp1;
2111 struct cvmx_gmxx_tx_col_attempt_s cn58xx;
2112 struct cvmx_gmxx_tx_col_attempt_s cn58xxp1;
2113};
2114
2115union cvmx_gmxx_tx_corrupt {
2116 uint64_t u64;
2117 struct cvmx_gmxx_tx_corrupt_s {
2118 uint64_t reserved_4_63:60;
2119 uint64_t corrupt:4;
2120 } s;
2121 struct cvmx_gmxx_tx_corrupt_cn30xx {
2122 uint64_t reserved_3_63:61;
2123 uint64_t corrupt:3;
2124 } cn30xx;
2125 struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx;
2126 struct cvmx_gmxx_tx_corrupt_s cn38xx;
2127 struct cvmx_gmxx_tx_corrupt_s cn38xxp2;
2128 struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx;
2129 struct cvmx_gmxx_tx_corrupt_s cn52xx;
2130 struct cvmx_gmxx_tx_corrupt_s cn52xxp1;
2131 struct cvmx_gmxx_tx_corrupt_s cn56xx;
2132 struct cvmx_gmxx_tx_corrupt_s cn56xxp1;
2133 struct cvmx_gmxx_tx_corrupt_s cn58xx;
2134 struct cvmx_gmxx_tx_corrupt_s cn58xxp1;
2135};
2136
2137union cvmx_gmxx_tx_hg2_reg1 {
2138 uint64_t u64;
2139 struct cvmx_gmxx_tx_hg2_reg1_s {
2140 uint64_t reserved_16_63:48;
2141 uint64_t tx_xof:16;
2142 } s;
2143 struct cvmx_gmxx_tx_hg2_reg1_s cn52xx;
2144 struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1;
2145 struct cvmx_gmxx_tx_hg2_reg1_s cn56xx;
2146};
2147
2148union cvmx_gmxx_tx_hg2_reg2 {
2149 uint64_t u64;
2150 struct cvmx_gmxx_tx_hg2_reg2_s {
2151 uint64_t reserved_16_63:48;
2152 uint64_t tx_xon:16;
2153 } s;
2154 struct cvmx_gmxx_tx_hg2_reg2_s cn52xx;
2155 struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1;
2156 struct cvmx_gmxx_tx_hg2_reg2_s cn56xx;
2157};
2158
2159union cvmx_gmxx_tx_ifg {
2160 uint64_t u64;
2161 struct cvmx_gmxx_tx_ifg_s {
2162 uint64_t reserved_8_63:56;
2163 uint64_t ifg2:4;
2164 uint64_t ifg1:4;
2165 } s;
2166 struct cvmx_gmxx_tx_ifg_s cn30xx;
2167 struct cvmx_gmxx_tx_ifg_s cn31xx;
2168 struct cvmx_gmxx_tx_ifg_s cn38xx;
2169 struct cvmx_gmxx_tx_ifg_s cn38xxp2;
2170 struct cvmx_gmxx_tx_ifg_s cn50xx;
2171 struct cvmx_gmxx_tx_ifg_s cn52xx;
2172 struct cvmx_gmxx_tx_ifg_s cn52xxp1;
2173 struct cvmx_gmxx_tx_ifg_s cn56xx;
2174 struct cvmx_gmxx_tx_ifg_s cn56xxp1;
2175 struct cvmx_gmxx_tx_ifg_s cn58xx;
2176 struct cvmx_gmxx_tx_ifg_s cn58xxp1;
2177};
2178
2179union cvmx_gmxx_tx_int_en {
2180 uint64_t u64;
2181 struct cvmx_gmxx_tx_int_en_s {
2182 uint64_t reserved_20_63:44;
2183 uint64_t late_col:4;
2184 uint64_t xsdef:4;
2185 uint64_t xscol:4;
2186 uint64_t reserved_6_7:2;
2187 uint64_t undflw:4;
2188 uint64_t ncb_nxa:1;
2189 uint64_t pko_nxa:1;
2190 } s;
2191 struct cvmx_gmxx_tx_int_en_cn30xx {
2192 uint64_t reserved_19_63:45;
2193 uint64_t late_col:3;
2194 uint64_t reserved_15_15:1;
2195 uint64_t xsdef:3;
2196 uint64_t reserved_11_11:1;
2197 uint64_t xscol:3;
2198 uint64_t reserved_5_7:3;
2199 uint64_t undflw:3;
2200 uint64_t reserved_1_1:1;
2201 uint64_t pko_nxa:1;
2202 } cn30xx;
2203 struct cvmx_gmxx_tx_int_en_cn31xx {
2204 uint64_t reserved_15_63:49;
2205 uint64_t xsdef:3;
2206 uint64_t reserved_11_11:1;
2207 uint64_t xscol:3;
2208 uint64_t reserved_5_7:3;
2209 uint64_t undflw:3;
2210 uint64_t reserved_1_1:1;
2211 uint64_t pko_nxa:1;
2212 } cn31xx;
2213 struct cvmx_gmxx_tx_int_en_s cn38xx;
2214 struct cvmx_gmxx_tx_int_en_cn38xxp2 {
2215 uint64_t reserved_16_63:48;
2216 uint64_t xsdef:4;
2217 uint64_t xscol:4;
2218 uint64_t reserved_6_7:2;
2219 uint64_t undflw:4;
2220 uint64_t ncb_nxa:1;
2221 uint64_t pko_nxa:1;
2222 } cn38xxp2;
2223 struct cvmx_gmxx_tx_int_en_cn30xx cn50xx;
2224 struct cvmx_gmxx_tx_int_en_cn52xx {
2225 uint64_t reserved_20_63:44;
2226 uint64_t late_col:4;
2227 uint64_t xsdef:4;
2228 uint64_t xscol:4;
2229 uint64_t reserved_6_7:2;
2230 uint64_t undflw:4;
2231 uint64_t reserved_1_1:1;
2232 uint64_t pko_nxa:1;
2233 } cn52xx;
2234 struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1;
2235 struct cvmx_gmxx_tx_int_en_cn52xx cn56xx;
2236 struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1;
2237 struct cvmx_gmxx_tx_int_en_s cn58xx;
2238 struct cvmx_gmxx_tx_int_en_s cn58xxp1;
2239};
2240
2241union cvmx_gmxx_tx_int_reg {
2242 uint64_t u64;
2243 struct cvmx_gmxx_tx_int_reg_s {
2244 uint64_t reserved_20_63:44;
2245 uint64_t late_col:4;
2246 uint64_t xsdef:4;
2247 uint64_t xscol:4;
2248 uint64_t reserved_6_7:2;
2249 uint64_t undflw:4;
2250 uint64_t ncb_nxa:1;
2251 uint64_t pko_nxa:1;
2252 } s;
2253 struct cvmx_gmxx_tx_int_reg_cn30xx {
2254 uint64_t reserved_19_63:45;
2255 uint64_t late_col:3;
2256 uint64_t reserved_15_15:1;
2257 uint64_t xsdef:3;
2258 uint64_t reserved_11_11:1;
2259 uint64_t xscol:3;
2260 uint64_t reserved_5_7:3;
2261 uint64_t undflw:3;
2262 uint64_t reserved_1_1:1;
2263 uint64_t pko_nxa:1;
2264 } cn30xx;
2265 struct cvmx_gmxx_tx_int_reg_cn31xx {
2266 uint64_t reserved_15_63:49;
2267 uint64_t xsdef:3;
2268 uint64_t reserved_11_11:1;
2269 uint64_t xscol:3;
2270 uint64_t reserved_5_7:3;
2271 uint64_t undflw:3;
2272 uint64_t reserved_1_1:1;
2273 uint64_t pko_nxa:1;
2274 } cn31xx;
2275 struct cvmx_gmxx_tx_int_reg_s cn38xx;
2276 struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
2277 uint64_t reserved_16_63:48;
2278 uint64_t xsdef:4;
2279 uint64_t xscol:4;
2280 uint64_t reserved_6_7:2;
2281 uint64_t undflw:4;
2282 uint64_t ncb_nxa:1;
2283 uint64_t pko_nxa:1;
2284 } cn38xxp2;
2285 struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx;
2286 struct cvmx_gmxx_tx_int_reg_cn52xx {
2287 uint64_t reserved_20_63:44;
2288 uint64_t late_col:4;
2289 uint64_t xsdef:4;
2290 uint64_t xscol:4;
2291 uint64_t reserved_6_7:2;
2292 uint64_t undflw:4;
2293 uint64_t reserved_1_1:1;
2294 uint64_t pko_nxa:1;
2295 } cn52xx;
2296 struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1;
2297 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx;
2298 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1;
2299 struct cvmx_gmxx_tx_int_reg_s cn58xx;
2300 struct cvmx_gmxx_tx_int_reg_s cn58xxp1;
2301};
2302
2303union cvmx_gmxx_tx_jam {
2304 uint64_t u64;
2305 struct cvmx_gmxx_tx_jam_s {
2306 uint64_t reserved_8_63:56;
2307 uint64_t jam:8;
2308 } s;
2309 struct cvmx_gmxx_tx_jam_s cn30xx;
2310 struct cvmx_gmxx_tx_jam_s cn31xx;
2311 struct cvmx_gmxx_tx_jam_s cn38xx;
2312 struct cvmx_gmxx_tx_jam_s cn38xxp2;
2313 struct cvmx_gmxx_tx_jam_s cn50xx;
2314 struct cvmx_gmxx_tx_jam_s cn52xx;
2315 struct cvmx_gmxx_tx_jam_s cn52xxp1;
2316 struct cvmx_gmxx_tx_jam_s cn56xx;
2317 struct cvmx_gmxx_tx_jam_s cn56xxp1;
2318 struct cvmx_gmxx_tx_jam_s cn58xx;
2319 struct cvmx_gmxx_tx_jam_s cn58xxp1;
2320};
2321
2322union cvmx_gmxx_tx_lfsr {
2323 uint64_t u64;
2324 struct cvmx_gmxx_tx_lfsr_s {
2325 uint64_t reserved_16_63:48;
2326 uint64_t lfsr:16;
2327 } s;
2328 struct cvmx_gmxx_tx_lfsr_s cn30xx;
2329 struct cvmx_gmxx_tx_lfsr_s cn31xx;
2330 struct cvmx_gmxx_tx_lfsr_s cn38xx;
2331 struct cvmx_gmxx_tx_lfsr_s cn38xxp2;
2332 struct cvmx_gmxx_tx_lfsr_s cn50xx;
2333 struct cvmx_gmxx_tx_lfsr_s cn52xx;
2334 struct cvmx_gmxx_tx_lfsr_s cn52xxp1;
2335 struct cvmx_gmxx_tx_lfsr_s cn56xx;
2336 struct cvmx_gmxx_tx_lfsr_s cn56xxp1;
2337 struct cvmx_gmxx_tx_lfsr_s cn58xx;
2338 struct cvmx_gmxx_tx_lfsr_s cn58xxp1;
2339};
2340
2341union cvmx_gmxx_tx_ovr_bp {
2342 uint64_t u64;
2343 struct cvmx_gmxx_tx_ovr_bp_s {
2344 uint64_t reserved_48_63:16;
2345 uint64_t tx_prt_bp:16;
2346 uint64_t reserved_12_31:20;
2347 uint64_t en:4;
2348 uint64_t bp:4;
2349 uint64_t ign_full:4;
2350 } s;
2351 struct cvmx_gmxx_tx_ovr_bp_cn30xx {
2352 uint64_t reserved_11_63:53;
2353 uint64_t en:3;
2354 uint64_t reserved_7_7:1;
2355 uint64_t bp:3;
2356 uint64_t reserved_3_3:1;
2357 uint64_t ign_full:3;
2358 } cn30xx;
2359 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx;
2360 struct cvmx_gmxx_tx_ovr_bp_cn38xx {
2361 uint64_t reserved_12_63:52;
2362 uint64_t en:4;
2363 uint64_t bp:4;
2364 uint64_t ign_full:4;
2365 } cn38xx;
2366 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2;
2367 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx;
2368 struct cvmx_gmxx_tx_ovr_bp_s cn52xx;
2369 struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1;
2370 struct cvmx_gmxx_tx_ovr_bp_s cn56xx;
2371 struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1;
2372 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx;
2373 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1;
2374};
2375
2376union cvmx_gmxx_tx_pause_pkt_dmac {
2377 uint64_t u64;
2378 struct cvmx_gmxx_tx_pause_pkt_dmac_s {
2379 uint64_t reserved_48_63:16;
2380 uint64_t dmac:48;
2381 } s;
2382 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;
2383 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;
2384 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;
2385 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;
2386 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;
2387 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;
2388 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;
2389 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;
2390 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
2391 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
2392 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
2393};
2394
2395union cvmx_gmxx_tx_pause_pkt_type {
2396 uint64_t u64;
2397 struct cvmx_gmxx_tx_pause_pkt_type_s {
2398 uint64_t reserved_16_63:48;
2399 uint64_t type:16;
2400 } s;
2401 struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;
2402 struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;
2403 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;
2404 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;
2405 struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;
2406 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;
2407 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;
2408 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;
2409 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
2410 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
2411 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
2412};
2413
2414union cvmx_gmxx_tx_prts {
2415 uint64_t u64;
2416 struct cvmx_gmxx_tx_prts_s {
2417 uint64_t reserved_5_63:59;
2418 uint64_t prts:5;
2419 } s;
2420 struct cvmx_gmxx_tx_prts_s cn30xx;
2421 struct cvmx_gmxx_tx_prts_s cn31xx;
2422 struct cvmx_gmxx_tx_prts_s cn38xx;
2423 struct cvmx_gmxx_tx_prts_s cn38xxp2;
2424 struct cvmx_gmxx_tx_prts_s cn50xx;
2425 struct cvmx_gmxx_tx_prts_s cn52xx;
2426 struct cvmx_gmxx_tx_prts_s cn52xxp1;
2427 struct cvmx_gmxx_tx_prts_s cn56xx;
2428 struct cvmx_gmxx_tx_prts_s cn56xxp1;
2429 struct cvmx_gmxx_tx_prts_s cn58xx;
2430 struct cvmx_gmxx_tx_prts_s cn58xxp1;
2431};
2432
2433union cvmx_gmxx_tx_spi_ctl {
2434 uint64_t u64;
2435 struct cvmx_gmxx_tx_spi_ctl_s {
2436 uint64_t reserved_2_63:62;
2437 uint64_t tpa_clr:1;
2438 uint64_t cont_pkt:1;
2439 } s;
2440 struct cvmx_gmxx_tx_spi_ctl_s cn38xx;
2441 struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2;
2442 struct cvmx_gmxx_tx_spi_ctl_s cn58xx;
2443 struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1;
2444};
2445
2446union cvmx_gmxx_tx_spi_drain {
2447 uint64_t u64;
2448 struct cvmx_gmxx_tx_spi_drain_s {
2449 uint64_t reserved_16_63:48;
2450 uint64_t drain:16;
2451 } s;
2452 struct cvmx_gmxx_tx_spi_drain_s cn38xx;
2453 struct cvmx_gmxx_tx_spi_drain_s cn58xx;
2454 struct cvmx_gmxx_tx_spi_drain_s cn58xxp1;
2455};
2456
2457union cvmx_gmxx_tx_spi_max {
2458 uint64_t u64;
2459 struct cvmx_gmxx_tx_spi_max_s {
2460 uint64_t reserved_23_63:41;
2461 uint64_t slice:7;
2462 uint64_t max2:8;
2463 uint64_t max1:8;
2464 } s;
2465 struct cvmx_gmxx_tx_spi_max_cn38xx {
2466 uint64_t reserved_16_63:48;
2467 uint64_t max2:8;
2468 uint64_t max1:8;
2469 } cn38xx;
2470 struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2;
2471 struct cvmx_gmxx_tx_spi_max_s cn58xx;
2472 struct cvmx_gmxx_tx_spi_max_s cn58xxp1;
2473};
2474
2475union cvmx_gmxx_tx_spi_roundx {
2476 uint64_t u64;
2477 struct cvmx_gmxx_tx_spi_roundx_s {
2478 uint64_t reserved_16_63:48;
2479 uint64_t round:16;
2480 } s;
2481 struct cvmx_gmxx_tx_spi_roundx_s cn58xx;
2482 struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1;
2483};
2484
2485union cvmx_gmxx_tx_spi_thresh {
2486 uint64_t u64;
2487 struct cvmx_gmxx_tx_spi_thresh_s {
2488 uint64_t reserved_6_63:58;
2489 uint64_t thresh:6;
2490 } s;
2491 struct cvmx_gmxx_tx_spi_thresh_s cn38xx;
2492 struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2;
2493 struct cvmx_gmxx_tx_spi_thresh_s cn58xx;
2494 struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1;
2495};
2496
2497union cvmx_gmxx_tx_xaui_ctl {
2498 uint64_t u64;
2499 struct cvmx_gmxx_tx_xaui_ctl_s {
2500 uint64_t reserved_11_63:53;
2501 uint64_t hg_pause_hgi:2;
2502 uint64_t hg_en:1;
2503 uint64_t reserved_7_7:1;
2504 uint64_t ls_byp:1;
2505 uint64_t ls:2;
2506 uint64_t reserved_2_3:2;
2507 uint64_t uni_en:1;
2508 uint64_t dic_en:1;
2509 } s;
2510 struct cvmx_gmxx_tx_xaui_ctl_s cn52xx;
2511 struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1;
2512 struct cvmx_gmxx_tx_xaui_ctl_s cn56xx;
2513 struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1;
2514};
2515
2516union cvmx_gmxx_xaui_ext_loopback {
2517 uint64_t u64;
2518 struct cvmx_gmxx_xaui_ext_loopback_s {
2519 uint64_t reserved_5_63:59;
2520 uint64_t en:1;
2521 uint64_t thresh:4;
2522 } s;
2523 struct cvmx_gmxx_xaui_ext_loopback_s cn52xx;
2524 struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
2525 struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
2526 struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
2527};
2528
2529#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
new file mode 100644
index 000000000000..88527fa835c9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -0,0 +1,157 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * Helper functions to abstract board specific data about
31 * network ports from the rest of the cvmx-helper files.
32 *
33 */
34#ifndef __CVMX_HELPER_BOARD_H__
35#define __CVMX_HELPER_BOARD_H__
36
37#include "cvmx-helper.h"
38
39typedef enum {
40 set_phy_link_flags_autoneg = 0x1,
41 set_phy_link_flags_flow_control_dont_touch = 0x0 << 1,
42 set_phy_link_flags_flow_control_enable = 0x1 << 1,
43 set_phy_link_flags_flow_control_disable = 0x2 << 1,
44 set_phy_link_flags_flow_control_mask = 0x3 << 1, /* Mask for 2 bit wide flow control field */
45} cvmx_helper_board_set_phy_link_flags_types_t;
46
47/*
48 * Fake IPD port, the RGMII/MII interface may use different PHY, use
49 * this macro to return appropriate MIX address to read the PHY.
50 */
51#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10
52
53/**
54 * cvmx_override_board_link_get(int ipd_port) is a function
55 * pointer. It is meant to allow customization of the process of
56 * talking to a PHY to determine link speed. It is called every
57 * time a PHY must be polled for link status. Users should set
58 * this pointer to a function before calling any cvmx-helper
59 * operations.
60 */
61extern cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port);
62
63/**
64 * Return the MII PHY address associated with the given IPD
65 * port. A result of -1 means there isn't a MII capable PHY
66 * connected to this port. On chips supporting multiple MII
67 * busses the bus number is encoded in bits <15:8>.
68 *
69 * This function must be modifed for every new Octeon board.
70 * Internally it uses switch statements based on the cvmx_sysinfo
71 * data to determine board types and revisions. It relys on the
72 * fact that every Octeon board receives a unique board type
73 * enumeration from the bootloader.
74 *
75 * @ipd_port: Octeon IPD port to get the MII address for.
76 *
77 * Returns MII PHY address and bus number or -1.
78 */
79extern int cvmx_helper_board_get_mii_address(int ipd_port);
80
81/**
82 * This function as a board specific method of changing the PHY
83 * speed, duplex, and autonegotiation. This programs the PHY and
84 * not Octeon. This can be used to force Octeon's links to
85 * specific settings.
86 *
87 * @phy_addr: The address of the PHY to program
88 * @link_flags:
89 * Flags to control autonegotiation. Bit 0 is autonegotiation
90 * enable/disable to maintain backware compatibility.
91 * @link_info: Link speed to program. If the speed is zero and autonegotiation
92 * is enabled, all possible negotiation speeds are advertised.
93 *
94 * Returns Zero on success, negative on failure
95 */
96int cvmx_helper_board_link_set_phy(int phy_addr,
97 cvmx_helper_board_set_phy_link_flags_types_t
98 link_flags,
99 cvmx_helper_link_info_t link_info);
100
101/**
102 * This function is the board specific method of determining an
103 * ethernet ports link speed. Most Octeon boards have Marvell PHYs
104 * and are handled by the fall through case. This function must be
105 * updated for boards that don't have the normal Marvell PHYs.
106 *
107 * This function must be modifed for every new Octeon board.
108 * Internally it uses switch statements based on the cvmx_sysinfo
109 * data to determine board types and revisions. It relys on the
110 * fact that every Octeon board receives a unique board type
111 * enumeration from the bootloader.
112 *
113 * @ipd_port: IPD input port associated with the port we want to get link
114 * status for.
115 *
116 * Returns The ports link status. If the link isn't fully resolved, this must
117 * return zero.
118 */
119extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port);
120
121/**
122 * This function is called by cvmx_helper_interface_probe() after it
123 * determines the number of ports Octeon can support on a specific
124 * interface. This function is the per board location to override
125 * this value. It is called with the number of ports Octeon might
126 * support and should return the number of actual ports on the
127 * board.
128 *
129 * This function must be modifed for every new Octeon board.
130 * Internally it uses switch statements based on the cvmx_sysinfo
131 * data to determine board types and revisions. It relys on the
132 * fact that every Octeon board receives a unique board type
133 * enumeration from the bootloader.
134 *
135 * @interface: Interface to probe
136 * @supported_ports:
137 * Number of ports Octeon supports.
138 *
139 * Returns Number of ports the actual board supports. Many times this will
140 * simple be "support_ports".
141 */
142extern int __cvmx_helper_board_interface_probe(int interface,
143 int supported_ports);
144
145/**
146 * Enable packet input/output from the hardware. This function is
147 * called after by cvmx_helper_packet_hardware_enable() to
148 * perform board specific initialization. For most boards
149 * nothing is needed.
150 *
151 * @interface: Interface to enable
152 *
153 * Returns Zero on success, negative on failure
154 */
155extern int __cvmx_helper_board_hardware_enable(int interface);
156
157#endif /* __CVMX_HELPER_BOARD_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
new file mode 100644
index 000000000000..5ff8c93198de
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
@@ -0,0 +1,64 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Helper functions for FPA setup.
32 *
33 */
34#ifndef __CVMX_HELPER_H_FPA__
35#define __CVMX_HELPER_H_FPA__
36
37/**
38 * Allocate memory and initialize the FPA pools using memory
39 * from cvmx-bootmem. Sizes of each element in the pools is
40 * controlled by the cvmx-config.h header file. Specifying
41 * zero for any parameter will cause that FPA pool to not be
42 * setup. This is useful if you aren't using some of the
43 * hardware and want to save memory.
44 *
45 * @packet_buffers:
46 * Number of packet buffers to allocate
47 * @work_queue_entries:
48 * Number of work queue entries
49 * @pko_buffers:
50 * PKO Command buffers. You should at minimum have two per
51 * each PKO queue.
52 * @tim_buffers:
53 * TIM ring buffer command queues. At least two per timer bucket
54 * is recommened.
55 * @dfa_buffers:
56 * DFA command buffer. A relatively small (32 for example)
57 * number should work.
58 * Returns Zero on success, non-zero if out of memory
59 */
60extern int cvmx_helper_initialize_fpa(int packet_buffers,
61 int work_queue_entries, int pko_buffers,
62 int tim_buffers, int dfa_buffers);
63
64#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-loop.h b/arch/mips/include/asm/octeon/cvmx-helper-loop.h
new file mode 100644
index 000000000000..077f0e9d3b2d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-loop.h
@@ -0,0 +1,60 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as published by
11 * the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful,
14 * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
16 * See the GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this file; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 * or visit http://www.gnu.org/licenses/.
22 *
23 * This file may also be available under a different license from Cavium.
24 * Contact Cavium Networks for more information
25 ***********************license end**************************************/
26
27/**
28 * @file
29 *
30 * Functions for LOOP initialization, configuration,
31 * and monitoring.
32 *
33 */
34#ifndef __CVMX_HELPER_LOOP_H__
35#define __CVMX_HELPER_LOOP_H__
36
37/**
38 * Probe a LOOP interface and determine the number of ports
39 * connected to it. The LOOP interface should still be down after
40 * this call.
41 *
42 * @interface: Interface to probe
43 *
44 * Returns Number of ports on the interface. Zero to disable.
45 */
46extern int __cvmx_helper_loop_probe(int interface);
47static inline int __cvmx_helper_loop_enumerate(int interface) {return 4; }
48
49/**
50 * Bringup and enable a LOOP interface. After this call packet
51 * I/O should be fully functional. This is called with IPD
52 * enabled but PKO disabled.
53 *
54 * @interface: Interface to bring up
55 *
56 * Returns Zero on success, negative on failure
57 */
58extern int __cvmx_helper_loop_enable(int interface);
59
60#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-npi.h b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
new file mode 100644
index 000000000000..8df4c7fafdba
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-npi.h
@@ -0,0 +1,61 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Functions for NPI initialization, configuration,
32 * and monitoring.
33 *
34 */
35#ifndef __CVMX_HELPER_NPI_H__
36#define __CVMX_HELPER_NPI_H__
37
38/**
39 * Probe a NPI interface and determine the number of ports
40 * connected to it. The NPI interface should still be down after
41 * this call.
42 *
43 * @interface: Interface to probe
44 *
45 * Returns Number of ports on the interface. Zero to disable.
46 */
47extern int __cvmx_helper_npi_probe(int interface);
48#define __cvmx_helper_npi_enumerate __cvmx_helper_npi_probe
49
50/**
51 * Bringup and enable a NPI interface. After this call packet
52 * I/O should be fully functional. This is called with IPD
53 * enabled but PKO disabled.
54 *
55 * @interface: Interface to bring up
56 *
57 * Returns Zero on success, negative on failure
58 */
59extern int __cvmx_helper_npi_enable(int interface);
60
61#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
new file mode 100644
index 000000000000..78295ba0050f
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
@@ -0,0 +1,111 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Functions for RGMII/GMII/MII initialization, configuration,
32 * and monitoring.
33 *
34 */
35#ifndef __CVMX_HELPER_RGMII_H__
36#define __CVMX_HELPER_RGMII_H__
37
38/**
39 * Probe RGMII ports and determine the number present
40 *
41 * @interface: Interface to probe
42 *
43 * Returns Number of RGMII/GMII/MII ports (0-4).
44 */
45extern int __cvmx_helper_rgmii_probe(int interface);
46#define __cvmx_helper_rgmii_enumerate __cvmx_helper_rgmii_probe
47
48/**
49 * Put an RGMII interface in loopback mode. Internal packets sent
50 * out will be received back again on the same port. Externally
51 * received packets will echo back out.
52 *
53 * @port: IPD port number to loop.
54 */
55extern void cvmx_helper_rgmii_internal_loopback(int port);
56
57/**
58 * Configure all of the ASX, GMX, and PKO regsiters required
59 * to get RGMII to function on the supplied interface.
60 *
61 * @interface: PKO Interface to configure (0 or 1)
62 *
63 * Returns Zero on success
64 */
65extern int __cvmx_helper_rgmii_enable(int interface);
66
67/**
68 * Return the link state of an IPD/PKO port as returned by
69 * auto negotiation. The result of this function may not match
70 * Octeon's link config if auto negotiation has changed since
71 * the last call to cvmx_helper_link_set().
72 *
73 * @ipd_port: IPD/PKO port to query
74 *
75 * Returns Link state
76 */
77extern cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port);
78
79/**
80 * Configure an IPD/PKO port for the specified link state. This
81 * function does not influence auto negotiation at the PHY level.
82 * The passed link state must always match the link state returned
83 * by cvmx_helper_link_get(). It is normally best to use
84 * cvmx_helper_link_autoconf() instead.
85 *
86 * @ipd_port: IPD/PKO port to configure
87 * @link_info: The new link state
88 *
89 * Returns Zero on success, negative on failure
90 */
91extern int __cvmx_helper_rgmii_link_set(int ipd_port,
92 cvmx_helper_link_info_t link_info);
93
94/**
95 * Configure a port for internal and/or external loopback. Internal loopback
96 * causes packets sent by the port to be received by Octeon. External loopback
97 * causes packets received from the wire to sent out again.
98 *
99 * @ipd_port: IPD/PKO port to loopback.
100 * @enable_internal:
101 * Non zero if you want internal loopback
102 * @enable_external:
103 * Non zero if you want external loopback
104 *
105 * Returns Zero on success, negative on failure.
106 */
107extern int __cvmx_helper_rgmii_configure_loopback(int ipd_port,
108 int enable_internal,
109 int enable_external);
110
111#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
new file mode 100644
index 000000000000..9a9b6c103ede
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
@@ -0,0 +1,105 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Functions for SGMII initialization, configuration,
32 * and monitoring.
33 *
34 */
35#ifndef __CVMX_HELPER_SGMII_H__
36#define __CVMX_HELPER_SGMII_H__
37
38/**
39 * Probe a SGMII interface and determine the number of ports
40 * connected to it. The SGMII interface should still be down after
41 * this call.
42 *
43 * @interface: Interface to probe
44 *
45 * Returns Number of ports on the interface. Zero to disable.
46 */
47extern int __cvmx_helper_sgmii_probe(int interface);
48extern int __cvmx_helper_sgmii_enumerate(int interface);
49
50/**
51 * Bringup and enable a SGMII interface. After this call packet
52 * I/O should be fully functional. This is called with IPD
53 * enabled but PKO disabled.
54 *
55 * @interface: Interface to bring up
56 *
57 * Returns Zero on success, negative on failure
58 */
59extern int __cvmx_helper_sgmii_enable(int interface);
60
61/**
62 * Return the link state of an IPD/PKO port as returned by
63 * auto negotiation. The result of this function may not match
64 * Octeon's link config if auto negotiation has changed since
65 * the last call to cvmx_helper_link_set().
66 *
67 * @ipd_port: IPD/PKO port to query
68 *
69 * Returns Link state
70 */
71extern cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port);
72
73/**
74 * Configure an IPD/PKO port for the specified link state. This
75 * function does not influence auto negotiation at the PHY level.
76 * The passed link state must always match the link state returned
77 * by cvmx_helper_link_get(). It is normally best to use
78 * cvmx_helper_link_autoconf() instead.
79 *
80 * @ipd_port: IPD/PKO port to configure
81 * @link_info: The new link state
82 *
83 * Returns Zero on success, negative on failure
84 */
85extern int __cvmx_helper_sgmii_link_set(int ipd_port,
86 cvmx_helper_link_info_t link_info);
87
88/**
89 * Configure a port for internal and/or external loopback. Internal loopback
90 * causes packets sent by the port to be received by Octeon. External loopback
91 * causes packets received from the wire to sent out again.
92 *
93 * @ipd_port: IPD/PKO port to loopback.
94 * @enable_internal:
95 * Non zero if you want internal loopback
96 * @enable_external:
97 * Non zero if you want external loopback
98 *
99 * Returns Zero on success, negative on failure.
100 */
101extern int __cvmx_helper_sgmii_configure_loopback(int ipd_port,
102 int enable_internal,
103 int enable_external);
104
105#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-spi.h b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
new file mode 100644
index 000000000000..9f1c6b968f91
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-spi.h
@@ -0,0 +1,85 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Functions for SPI initialization, configuration,
30 * and monitoring.
31 */
32#ifndef __CVMX_HELPER_SPI_H__
33#define __CVMX_HELPER_SPI_H__
34
35/**
36 * Probe a SPI interface and determine the number of ports
37 * connected to it. The SPI interface should still be down after
38 * this call.
39 *
40 * @interface: Interface to probe
41 *
42 * Returns Number of ports on the interface. Zero to disable.
43 */
44extern int __cvmx_helper_spi_probe(int interface);
45extern int __cvmx_helper_spi_enumerate(int interface);
46
47/**
48 * Bringup and enable a SPI interface. After this call packet I/O
49 * should be fully functional. This is called with IPD enabled but
50 * PKO disabled.
51 *
52 * @interface: Interface to bring up
53 *
54 * Returns Zero on success, negative on failure
55 */
56extern int __cvmx_helper_spi_enable(int interface);
57
58/**
59 * Return the link state of an IPD/PKO port as returned by
60 * auto negotiation. The result of this function may not match
61 * Octeon's link config if auto negotiation has changed since
62 * the last call to cvmx_helper_link_set().
63 *
64 * @ipd_port: IPD/PKO port to query
65 *
66 * Returns Link state
67 */
68extern cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port);
69
70/**
71 * Configure an IPD/PKO port for the specified link state. This
72 * function does not influence auto negotiation at the PHY level.
73 * The passed link state must always match the link state returned
74 * by cvmx_helper_link_get(). It is normally best to use
75 * cvmx_helper_link_autoconf() instead.
76 *
77 * @ipd_port: IPD/PKO port to configure
78 * @link_info: The new link state
79 *
80 * Returns Zero on success, negative on failure
81 */
82extern int __cvmx_helper_spi_link_set(int ipd_port,
83 cvmx_helper_link_info_t link_info);
84
85#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h
new file mode 100644
index 000000000000..6a6e52fc22c1
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h
@@ -0,0 +1,215 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Small helper utilities.
31 *
32 */
33
34#ifndef __CVMX_HELPER_UTIL_H__
35#define __CVMX_HELPER_UTIL_H__
36
37/**
38 * Convert a interface mode into a human readable string
39 *
40 * @mode: Mode to convert
41 *
42 * Returns String
43 */
44extern const char
45 *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode);
46
47/**
48 * Debug routine to dump the packet structure to the console
49 *
50 * @work: Work queue entry containing the packet to dump
51 * Returns
52 */
53extern int cvmx_helper_dump_packet(cvmx_wqe_t *work);
54
55/**
56 * Setup Random Early Drop on a specific input queue
57 *
58 * @queue: Input queue to setup RED on (0-7)
59 * @pass_thresh:
60 * Packets will begin slowly dropping when there are less than
61 * this many packet buffers free in FPA 0.
62 * @drop_thresh:
63 * All incomming packets will be dropped when there are less
64 * than this many free packet buffers in FPA 0.
65 * Returns Zero on success. Negative on failure
66 */
67extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh,
68 int drop_thresh);
69
70/**
71 * Setup Random Early Drop to automatically begin dropping packets.
72 *
73 * @pass_thresh:
74 * Packets will begin slowly dropping when there are less than
75 * this many packet buffers free in FPA 0.
76 * @drop_thresh:
77 * All incomming packets will be dropped when there are less
78 * than this many free packet buffers in FPA 0.
79 * Returns Zero on success. Negative on failure
80 */
81extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);
82
83/**
84 * Get the version of the CVMX libraries.
85 *
86 * Returns Version string. Note this buffer is allocated statically
87 * and will be shared by all callers.
88 */
89extern const char *cvmx_helper_get_version(void);
90
91/**
92 * Setup the common GMX settings that determine the number of
93 * ports. These setting apply to almost all configurations of all
94 * chips.
95 *
96 * @interface: Interface to configure
97 * @num_ports: Number of ports on the interface
98 *
99 * Returns Zero on success, negative on failure
100 */
101extern int __cvmx_helper_setup_gmx(int interface, int num_ports);
102
103/**
104 * Returns the IPD/PKO port number for a port on the given
105 * interface.
106 *
107 * @interface: Interface to use
108 * @port: Port on the interface
109 *
110 * Returns IPD/PKO port number
111 */
112extern int cvmx_helper_get_ipd_port(int interface, int port);
113
114/**
115 * Returns the IPD/PKO port number for the first port on the given
116 * interface.
117 *
118 * @interface: Interface to use
119 *
120 * Returns IPD/PKO port number
121 */
122static inline int cvmx_helper_get_first_ipd_port(int interface)
123{
124 return cvmx_helper_get_ipd_port(interface, 0);
125}
126
127/**
128 * Returns the IPD/PKO port number for the last port on the given
129 * interface.
130 *
131 * @interface: Interface to use
132 *
133 * Returns IPD/PKO port number
134 */
135static inline int cvmx_helper_get_last_ipd_port(int interface)
136{
137 extern int cvmx_helper_ports_on_interface(int interface);
138
139 return cvmx_helper_get_first_ipd_port(interface) +
140 cvmx_helper_ports_on_interface(interface) - 1;
141}
142
143/**
144 * Free the packet buffers contained in a work queue entry.
145 * The work queue entry is not freed.
146 *
147 * @work: Work queue entry with packet to free
148 */
149static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work)
150{
151 uint64_t number_buffers;
152 union cvmx_buf_ptr buffer_ptr;
153 union cvmx_buf_ptr next_buffer_ptr;
154 uint64_t start_of_buffer;
155
156 number_buffers = work->word2.s.bufs;
157 if (number_buffers == 0)
158 return;
159 buffer_ptr = work->packet_ptr;
160
161 /*
162 * Since the number of buffers is not zero, we know this is
163 * not a dynamic short packet. We need to check if it is a
164 * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is
165 * true, we need to free all buffers except for the first
166 * one. The caller doesn't expect their WQE pointer to be
167 * freed
168 */
169 start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
170 if (cvmx_ptr_to_phys(work) == start_of_buffer) {
171 next_buffer_ptr =
172 *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
173 buffer_ptr = next_buffer_ptr;
174 number_buffers--;
175 }
176
177 while (number_buffers--) {
178 /*
179 * Remember the back pointer is in cache lines, not
180 * 64bit words
181 */
182 start_of_buffer =
183 ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
184 /*
185 * Read pointer to next buffer before we free the
186 * current buffer.
187 */
188 next_buffer_ptr =
189 *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
190 cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer),
191 buffer_ptr.s.pool, 0);
192 buffer_ptr = next_buffer_ptr;
193 }
194}
195
196/**
197 * Returns the interface number for an IPD/PKO port number.
198 *
199 * @ipd_port: IPD/PKO port number
200 *
201 * Returns Interface number
202 */
203extern int cvmx_helper_get_interface_num(int ipd_port);
204
205/**
206 * Returns the interface index number for an IPD/PKO port
207 * number.
208 *
209 * @ipd_port: IPD/PKO port number
210 *
211 * Returns Interface index number
212 */
213extern int cvmx_helper_get_interface_index_num(int ipd_port);
214
215#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
new file mode 100644
index 000000000000..f6fbc4f45b56
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
@@ -0,0 +1,104 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Functions for XAUI initialization, configuration,
32 * and monitoring.
33 *
34 */
35#ifndef __CVMX_HELPER_XAUI_H__
36#define __CVMX_HELPER_XAUI_H__
37
38/**
39 * Probe a XAUI interface and determine the number of ports
40 * connected to it. The XAUI interface should still be down
41 * after this call.
42 *
43 * @interface: Interface to probe
44 *
45 * Returns Number of ports on the interface. Zero to disable.
46 */
47extern int __cvmx_helper_xaui_probe(int interface);
48extern int __cvmx_helper_xaui_enumerate(int interface);
49
50/**
51 * Bringup and enable a XAUI interface. After this call packet
52 * I/O should be fully functional. This is called with IPD
53 * enabled but PKO disabled.
54 *
55 * @interface: Interface to bring up
56 *
57 * Returns Zero on success, negative on failure
58 */
59extern int __cvmx_helper_xaui_enable(int interface);
60
61/**
62 * Return the link state of an IPD/PKO port as returned by
63 * auto negotiation. The result of this function may not match
64 * Octeon's link config if auto negotiation has changed since
65 * the last call to cvmx_helper_link_set().
66 *
67 * @ipd_port: IPD/PKO port to query
68 *
69 * Returns Link state
70 */
71extern cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port);
72
73/**
74 * Configure an IPD/PKO port for the specified link state. This
75 * function does not influence auto negotiation at the PHY level.
76 * The passed link state must always match the link state returned
77 * by cvmx_helper_link_get(). It is normally best to use
78 * cvmx_helper_link_autoconf() instead.
79 *
80 * @ipd_port: IPD/PKO port to configure
81 * @link_info: The new link state
82 *
83 * Returns Zero on success, negative on failure
84 */
85extern int __cvmx_helper_xaui_link_set(int ipd_port,
86 cvmx_helper_link_info_t link_info);
87
88/**
89 * Configure a port for internal and/or external loopback. Internal loopback
90 * causes packets sent by the port to be received by Octeon. External loopback
91 * causes packets received from the wire to sent out again.
92 *
93 * @ipd_port: IPD/PKO port to loopback.
94 * @enable_internal:
95 * Non zero if you want internal loopback
96 * @enable_external:
97 * Non zero if you want external loopback
98 *
99 * Returns Zero on success, negative on failure.
100 */
101extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
102 int enable_internal,
103 int enable_external);
104#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h
new file mode 100644
index 000000000000..3169cd79f2ac
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper.h
@@ -0,0 +1,228 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Helper functions for common, but complicated tasks.
31 *
32 */
33
34#ifndef __CVMX_HELPER_H__
35#define __CVMX_HELPER_H__
36
37#include "cvmx-config.h"
38#include "cvmx-fpa.h"
39#include "cvmx-wqe.h"
40
41typedef enum {
42 CVMX_HELPER_INTERFACE_MODE_DISABLED,
43 CVMX_HELPER_INTERFACE_MODE_RGMII,
44 CVMX_HELPER_INTERFACE_MODE_GMII,
45 CVMX_HELPER_INTERFACE_MODE_SPI,
46 CVMX_HELPER_INTERFACE_MODE_PCIE,
47 CVMX_HELPER_INTERFACE_MODE_XAUI,
48 CVMX_HELPER_INTERFACE_MODE_SGMII,
49 CVMX_HELPER_INTERFACE_MODE_PICMG,
50 CVMX_HELPER_INTERFACE_MODE_NPI,
51 CVMX_HELPER_INTERFACE_MODE_LOOP,
52} cvmx_helper_interface_mode_t;
53
54typedef union {
55 uint64_t u64;
56 struct {
57 uint64_t reserved_20_63:44;
58 uint64_t link_up:1; /**< Is the physical link up? */
59 uint64_t full_duplex:1; /**< 1 if the link is full duplex */
60 uint64_t speed:18; /**< Speed of the link in Mbps */
61 } s;
62} cvmx_helper_link_info_t;
63
64#include "cvmx-helper-fpa.h"
65
66#include <asm/octeon/cvmx-helper-errata.h>
67#include "cvmx-helper-loop.h"
68#include "cvmx-helper-npi.h"
69#include "cvmx-helper-rgmii.h"
70#include "cvmx-helper-sgmii.h"
71#include "cvmx-helper-spi.h"
72#include "cvmx-helper-util.h"
73#include "cvmx-helper-xaui.h"
74
75/**
76 * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
77 * priorities[16]) is a function pointer. It is meant to allow
78 * customization of the PKO queue priorities based on the port
79 * number. Users should set this pointer to a function before
80 * calling any cvmx-helper operations.
81 */
82extern void (*cvmx_override_pko_queue_priority) (int pko_port,
83 uint64_t priorities[16]);
84
85/**
86 * cvmx_override_ipd_port_setup(int ipd_port) is a function
87 * pointer. It is meant to allow customization of the IPD port
88 * setup before packet input/output comes online. It is called
89 * after cvmx-helper does the default IPD configuration, but
90 * before IPD is enabled. Users should set this pointer to a
91 * function before calling any cvmx-helper operations.
92 */
93extern void (*cvmx_override_ipd_port_setup) (int ipd_port);
94
95/**
96 * This function enables the IPD and also enables the packet interfaces.
97 * The packet interfaces (RGMII and SPI) must be enabled after the
98 * IPD. This should be called by the user program after any additional
99 * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD
100 * is not set in the executive-config.h file.
101 *
102 * Returns 0 on success
103 * -1 on failure
104 */
105extern int cvmx_helper_ipd_and_packet_input_enable(void);
106
107/**
108 * Initialize the PIP, IPD, and PKO hardware to support
109 * simple priority based queues for the ethernet ports. Each
110 * port is configured with a number of priority queues based
111 * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower
112 * priority than the previous.
113 *
114 * Returns Zero on success, non-zero on failure
115 */
116extern int cvmx_helper_initialize_packet_io_global(void);
117
118/**
119 * Does core local initialization for packet io
120 *
121 * Returns Zero on success, non-zero on failure
122 */
123extern int cvmx_helper_initialize_packet_io_local(void);
124
125/**
126 * Returns the number of ports on the given interface.
127 * The interface must be initialized before the port count
128 * can be returned.
129 *
130 * @interface: Which interface to return port count for.
131 *
132 * Returns Port count for interface
133 * -1 for uninitialized interface
134 */
135extern int cvmx_helper_ports_on_interface(int interface);
136
137/**
138 * Return the number of interfaces the chip has. Each interface
139 * may have multiple ports. Most chips support two interfaces,
140 * but the CNX0XX and CNX1XX are exceptions. These only support
141 * one interface.
142 *
143 * Returns Number of interfaces on chip
144 */
145extern int cvmx_helper_get_number_of_interfaces(void);
146
147/**
148 * Get the operating mode of an interface. Depending on the Octeon
149 * chip and configuration, this function returns an enumeration
150 * of the type of packet I/O supported by an interface.
151 *
152 * @interface: Interface to probe
153 *
154 * Returns Mode of the interface. Unknown or unsupported interfaces return
155 * DISABLED.
156 */
157extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
158 interface);
159
160/**
161 * Auto configure an IPD/PKO port link state and speed. This
162 * function basically does the equivalent of:
163 * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
164 *
165 * @ipd_port: IPD/PKO port to auto configure
166 *
167 * Returns Link state after configure
168 */
169extern cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port);
170
171/**
172 * Return the link state of an IPD/PKO port as returned by
173 * auto negotiation. The result of this function may not match
174 * Octeon's link config if auto negotiation has changed since
175 * the last call to cvmx_helper_link_set().
176 *
177 * @ipd_port: IPD/PKO port to query
178 *
179 * Returns Link state
180 */
181extern cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port);
182
183/**
184 * Configure an IPD/PKO port for the specified link state. This
185 * function does not influence auto negotiation at the PHY level.
186 * The passed link state must always match the link state returned
187 * by cvmx_helper_link_get(). It is normally best to use
188 * cvmx_helper_link_autoconf() instead.
189 *
190 * @ipd_port: IPD/PKO port to configure
191 * @link_info: The new link state
192 *
193 * Returns Zero on success, negative on failure
194 */
195extern int cvmx_helper_link_set(int ipd_port,
196 cvmx_helper_link_info_t link_info);
197
198/**
199 * This function probes an interface to determine the actual
200 * number of hardware ports connected to it. It doesn't setup the
201 * ports or enable them. The main goal here is to set the global
202 * interface_port_count[interface] correctly. Hardware setup of the
203 * ports will be performed later.
204 *
205 * @interface: Interface to probe
206 *
207 * Returns Zero on success, negative on failure
208 */
209extern int cvmx_helper_interface_probe(int interface);
210extern int cvmx_helper_interface_enumerate(int interface);
211
212/**
213 * Configure a port for internal and/or external loopback. Internal loopback
214 * causes packets sent by the port to be received by Octeon. External loopback
215 * causes packets received from the wire to sent out again.
216 *
217 * @ipd_port: IPD/PKO port to loopback.
218 * @enable_internal:
219 * Non zero if you want internal loopback
220 * @enable_external:
221 * Non zero if you want external loopback
222 *
223 * Returns Zero on success, negative on failure.
224 */
225extern int cvmx_helper_configure_loopback(int ipd_port, int enable_internal,
226 int enable_external);
227
228#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h
new file mode 100644
index 000000000000..115a552c5c7f
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ipd.h
@@ -0,0 +1,338 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * Interface to the hardware Input Packet Data unit.
31 */
32
33#ifndef __CVMX_IPD_H__
34#define __CVMX_IPD_H__
35
36#include <asm/octeon/octeon-feature.h>
37
38#include <asm/octeon/cvmx-ipd-defs.h>
39
40enum cvmx_ipd_mode {
41 CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */
42 CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */
43 CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */
44 CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */
45};
46
47#ifndef CVMX_ENABLE_LEN_M8_FIX
48#define CVMX_ENABLE_LEN_M8_FIX 0
49#endif
50
51/* CSR typedefs have been moved to cvmx-csr-*.h */
52typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_mbuff_first_skip_t;
53typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_first_next_ptr_back_t;
54
55typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t;
56typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
57
58/**
59 * Configure IPD
60 *
61 * @mbuff_size: Packets buffer size in 8 byte words
62 * @first_mbuff_skip:
63 * Number of 8 byte words to skip in the first buffer
64 * @not_first_mbuff_skip:
65 * Number of 8 byte words to skip in each following buffer
66 * @first_back: Must be same as first_mbuff_skip / 128
67 * @second_back:
68 * Must be same as not_first_mbuff_skip / 128
69 * @wqe_fpa_pool:
70 * FPA pool to get work entries from
71 * @cache_mode:
72 * @back_pres_enable_flag:
73 * Enable or disable port back pressure
74 */
75static inline void cvmx_ipd_config(uint64_t mbuff_size,
76 uint64_t first_mbuff_skip,
77 uint64_t not_first_mbuff_skip,
78 uint64_t first_back,
79 uint64_t second_back,
80 uint64_t wqe_fpa_pool,
81 enum cvmx_ipd_mode cache_mode,
82 uint64_t back_pres_enable_flag)
83{
84 cvmx_ipd_mbuff_first_skip_t first_skip;
85 cvmx_ipd_mbuff_not_first_skip_t not_first_skip;
86 union cvmx_ipd_packet_mbuff_size size;
87 cvmx_ipd_first_next_ptr_back_t first_back_struct;
88 cvmx_ipd_second_next_ptr_back_t second_back_struct;
89 union cvmx_ipd_wqe_fpa_queue wqe_pool;
90 union cvmx_ipd_ctl_status ipd_ctl_reg;
91
92 first_skip.u64 = 0;
93 first_skip.s.skip_sz = first_mbuff_skip;
94 cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);
95
96 not_first_skip.u64 = 0;
97 not_first_skip.s.skip_sz = not_first_mbuff_skip;
98 cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);
99
100 size.u64 = 0;
101 size.s.mb_size = mbuff_size;
102 cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);
103
104 first_back_struct.u64 = 0;
105 first_back_struct.s.back = first_back;
106 cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);
107
108 second_back_struct.u64 = 0;
109 second_back_struct.s.back = second_back;
110 cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64);
111
112 wqe_pool.u64 = 0;
113 wqe_pool.s.wqe_pool = wqe_fpa_pool;
114 cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64);
115
116 ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
117 ipd_ctl_reg.s.opc_mode = cache_mode;
118 ipd_ctl_reg.s.pbp_en = back_pres_enable_flag;
119 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64);
120
121 /* Note: the example RED code that used to be here has been moved to
122 cvmx_helper_setup_red */
123}
124
125/**
126 * Enable IPD
127 */
128static inline void cvmx_ipd_enable(void)
129{
130 union cvmx_ipd_ctl_status ipd_reg;
131 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
132 if (ipd_reg.s.ipd_en) {
133 cvmx_dprintf
134 ("Warning: Enabling IPD when IPD already enabled.\n");
135 }
136 ipd_reg.s.ipd_en = 1;
137#if CVMX_ENABLE_LEN_M8_FIX
138 if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
139 ipd_reg.s.len_m8 = TRUE;
140#endif
141 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
142}
143
144/**
145 * Disable IPD
146 */
147static inline void cvmx_ipd_disable(void)
148{
149 union cvmx_ipd_ctl_status ipd_reg;
150 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
151 ipd_reg.s.ipd_en = 0;
152 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
153}
154
155/**
156 * Supportive function for cvmx_fpa_shutdown_pool.
157 */
158static inline void cvmx_ipd_free_ptr(void)
159{
160 /* Only CN38XXp{1,2} cannot read pointer out of the IPD */
161 if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)
162 && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
163 int no_wptr = 0;
164 union cvmx_ipd_ptr_count ipd_ptr_count;
165 ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
166
167 /* Handle Work Queue Entry in cn56xx and cn52xx */
168 if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
169 union cvmx_ipd_ctl_status ipd_ctl_status;
170 ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
171 if (ipd_ctl_status.s.no_wptr)
172 no_wptr = 1;
173 }
174
175 /* Free the prefetched WQE */
176 if (ipd_ptr_count.s.wqev_cnt) {
177 union cvmx_ipd_wqe_ptr_valid ipd_wqe_ptr_valid;
178 ipd_wqe_ptr_valid.u64 =
179 cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
180 if (no_wptr)
181 cvmx_fpa_free(cvmx_phys_to_ptr
182 ((uint64_t) ipd_wqe_ptr_valid.s.
183 ptr << 7), CVMX_FPA_PACKET_POOL,
184 0);
185 else
186 cvmx_fpa_free(cvmx_phys_to_ptr
187 ((uint64_t) ipd_wqe_ptr_valid.s.
188 ptr << 7), CVMX_FPA_WQE_POOL, 0);
189 }
190
191 /* Free all WQE in the fifo */
192 if (ipd_ptr_count.s.wqe_pcnt) {
193 int i;
194 union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
195 ipd_pwp_ptr_fifo_ctl.u64 =
196 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
197 for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
198 ipd_pwp_ptr_fifo_ctl.s.cena = 0;
199 ipd_pwp_ptr_fifo_ctl.s.raddr =
200 ipd_pwp_ptr_fifo_ctl.s.max_cnts +
201 (ipd_pwp_ptr_fifo_ctl.s.wraddr +
202 i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
203 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
204 ipd_pwp_ptr_fifo_ctl.u64);
205 ipd_pwp_ptr_fifo_ctl.u64 =
206 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
207 if (no_wptr)
208 cvmx_fpa_free(cvmx_phys_to_ptr
209 ((uint64_t)
210 ipd_pwp_ptr_fifo_ctl.s.
211 ptr << 7),
212 CVMX_FPA_PACKET_POOL, 0);
213 else
214 cvmx_fpa_free(cvmx_phys_to_ptr
215 ((uint64_t)
216 ipd_pwp_ptr_fifo_ctl.s.
217 ptr << 7),
218 CVMX_FPA_WQE_POOL, 0);
219 }
220 ipd_pwp_ptr_fifo_ctl.s.cena = 1;
221 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
222 ipd_pwp_ptr_fifo_ctl.u64);
223 }
224
225 /* Free the prefetched packet */
226 if (ipd_ptr_count.s.pktv_cnt) {
227 union cvmx_ipd_pkt_ptr_valid ipd_pkt_ptr_valid;
228 ipd_pkt_ptr_valid.u64 =
229 cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
230 cvmx_fpa_free(cvmx_phys_to_ptr
231 (ipd_pkt_ptr_valid.s.ptr << 7),
232 CVMX_FPA_PACKET_POOL, 0);
233 }
234
235 /* Free the per port prefetched packets */
236 if (1) {
237 int i;
238 union cvmx_ipd_prc_port_ptr_fifo_ctl
239 ipd_prc_port_ptr_fifo_ctl;
240 ipd_prc_port_ptr_fifo_ctl.u64 =
241 cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
242
243 for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
244 i++) {
245 ipd_prc_port_ptr_fifo_ctl.s.cena = 0;
246 ipd_prc_port_ptr_fifo_ctl.s.raddr =
247 i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
248 cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
249 ipd_prc_port_ptr_fifo_ctl.u64);
250 ipd_prc_port_ptr_fifo_ctl.u64 =
251 cvmx_read_csr
252 (CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
253 cvmx_fpa_free(cvmx_phys_to_ptr
254 ((uint64_t)
255 ipd_prc_port_ptr_fifo_ctl.s.
256 ptr << 7), CVMX_FPA_PACKET_POOL,
257 0);
258 }
259 ipd_prc_port_ptr_fifo_ctl.s.cena = 1;
260 cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
261 ipd_prc_port_ptr_fifo_ctl.u64);
262 }
263
264 /* Free all packets in the holding fifo */
265 if (ipd_ptr_count.s.pfif_cnt) {
266 int i;
267 union cvmx_ipd_prc_hold_ptr_fifo_ctl
268 ipd_prc_hold_ptr_fifo_ctl;
269
270 ipd_prc_hold_ptr_fifo_ctl.u64 =
271 cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
272
273 for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
274 ipd_prc_hold_ptr_fifo_ctl.s.cena = 0;
275 ipd_prc_hold_ptr_fifo_ctl.s.raddr =
276 (ipd_prc_hold_ptr_fifo_ctl.s.praddr +
277 i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt;
278 cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
279 ipd_prc_hold_ptr_fifo_ctl.u64);
280 ipd_prc_hold_ptr_fifo_ctl.u64 =
281 cvmx_read_csr
282 (CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
283 cvmx_fpa_free(cvmx_phys_to_ptr
284 ((uint64_t)
285 ipd_prc_hold_ptr_fifo_ctl.s.
286 ptr << 7), CVMX_FPA_PACKET_POOL,
287 0);
288 }
289 ipd_prc_hold_ptr_fifo_ctl.s.cena = 1;
290 cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
291 ipd_prc_hold_ptr_fifo_ctl.u64);
292 }
293
294 /* Free all packets in the fifo */
295 if (ipd_ptr_count.s.pkt_pcnt) {
296 int i;
297 union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
298 ipd_pwp_ptr_fifo_ctl.u64 =
299 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
300
301 for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
302 ipd_pwp_ptr_fifo_ctl.s.cena = 0;
303 ipd_pwp_ptr_fifo_ctl.s.raddr =
304 (ipd_pwp_ptr_fifo_ctl.s.praddr +
305 i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
306 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
307 ipd_pwp_ptr_fifo_ctl.u64);
308 ipd_pwp_ptr_fifo_ctl.u64 =
309 cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
310 cvmx_fpa_free(cvmx_phys_to_ptr
311 ((uint64_t) ipd_pwp_ptr_fifo_ctl.
312 s.ptr << 7),
313 CVMX_FPA_PACKET_POOL, 0);
314 }
315 ipd_pwp_ptr_fifo_ctl.s.cena = 1;
316 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
317 ipd_pwp_ptr_fifo_ctl.u64);
318 }
319
320 /* Reset the IPD to get all buffers out of it */
321 {
322 union cvmx_ipd_ctl_status ipd_ctl_status;
323 ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
324 ipd_ctl_status.s.reset = 1;
325 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
326 }
327
328 /* Reset the PIP */
329 {
330 union cvmx_pip_sft_rst pip_sft_rst;
331 pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);
332 pip_sft_rst.s.rst = 1;
333 cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
334 }
335 }
336}
337
338#endif /* __CVMX_IPD_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h
new file mode 100644
index 000000000000..d88ab8d8e37d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mdio.h
@@ -0,0 +1,506 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
31 * clause 22 and clause 45 operations.
32 *
33 */
34
35#ifndef __CVMX_MIO_H__
36#define __CVMX_MIO_H__
37
38#include "cvmx-smix-defs.h"
39
40/**
41 * PHY register 0 from the 802.3 spec
42 */
43#define CVMX_MDIO_PHY_REG_CONTROL 0
44typedef union {
45 uint16_t u16;
46 struct {
47 uint16_t reset:1;
48 uint16_t loopback:1;
49 uint16_t speed_lsb:1;
50 uint16_t autoneg_enable:1;
51 uint16_t power_down:1;
52 uint16_t isolate:1;
53 uint16_t restart_autoneg:1;
54 uint16_t duplex:1;
55 uint16_t collision_test:1;
56 uint16_t speed_msb:1;
57 uint16_t unidirectional_enable:1;
58 uint16_t reserved_0_4:5;
59 } s;
60} cvmx_mdio_phy_reg_control_t;
61
62/**
63 * PHY register 1 from the 802.3 spec
64 */
65#define CVMX_MDIO_PHY_REG_STATUS 1
66typedef union {
67 uint16_t u16;
68 struct {
69 uint16_t capable_100base_t4:1;
70 uint16_t capable_100base_x_full:1;
71 uint16_t capable_100base_x_half:1;
72 uint16_t capable_10_full:1;
73 uint16_t capable_10_half:1;
74 uint16_t capable_100base_t2_full:1;
75 uint16_t capable_100base_t2_half:1;
76 uint16_t capable_extended_status:1;
77 uint16_t capable_unidirectional:1;
78 uint16_t capable_mf_preamble_suppression:1;
79 uint16_t autoneg_complete:1;
80 uint16_t remote_fault:1;
81 uint16_t capable_autoneg:1;
82 uint16_t link_status:1;
83 uint16_t jabber_detect:1;
84 uint16_t capable_extended_registers:1;
85
86 } s;
87} cvmx_mdio_phy_reg_status_t;
88
89/**
90 * PHY register 2 from the 802.3 spec
91 */
92#define CVMX_MDIO_PHY_REG_ID1 2
93typedef union {
94 uint16_t u16;
95 struct {
96 uint16_t oui_bits_3_18;
97 } s;
98} cvmx_mdio_phy_reg_id1_t;
99
100/**
101 * PHY register 3 from the 802.3 spec
102 */
103#define CVMX_MDIO_PHY_REG_ID2 3
104typedef union {
105 uint16_t u16;
106 struct {
107 uint16_t oui_bits_19_24:6;
108 uint16_t model:6;
109 uint16_t revision:4;
110 } s;
111} cvmx_mdio_phy_reg_id2_t;
112
113/**
114 * PHY register 4 from the 802.3 spec
115 */
116#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4
117typedef union {
118 uint16_t u16;
119 struct {
120 uint16_t next_page:1;
121 uint16_t reserved_14:1;
122 uint16_t remote_fault:1;
123 uint16_t reserved_12:1;
124 uint16_t asymmetric_pause:1;
125 uint16_t pause:1;
126 uint16_t advert_100base_t4:1;
127 uint16_t advert_100base_tx_full:1;
128 uint16_t advert_100base_tx_half:1;
129 uint16_t advert_10base_tx_full:1;
130 uint16_t advert_10base_tx_half:1;
131 uint16_t selector:5;
132 } s;
133} cvmx_mdio_phy_reg_autoneg_adver_t;
134
135/**
136 * PHY register 5 from the 802.3 spec
137 */
138#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5
139typedef union {
140 uint16_t u16;
141 struct {
142 uint16_t next_page:1;
143 uint16_t ack:1;
144 uint16_t remote_fault:1;
145 uint16_t reserved_12:1;
146 uint16_t asymmetric_pause:1;
147 uint16_t pause:1;
148 uint16_t advert_100base_t4:1;
149 uint16_t advert_100base_tx_full:1;
150 uint16_t advert_100base_tx_half:1;
151 uint16_t advert_10base_tx_full:1;
152 uint16_t advert_10base_tx_half:1;
153 uint16_t selector:5;
154 } s;
155} cvmx_mdio_phy_reg_link_partner_ability_t;
156
157/**
158 * PHY register 6 from the 802.3 spec
159 */
160#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6
161typedef union {
162 uint16_t u16;
163 struct {
164 uint16_t reserved_5_15:11;
165 uint16_t parallel_detection_fault:1;
166 uint16_t link_partner_next_page_capable:1;
167 uint16_t local_next_page_capable:1;
168 uint16_t page_received:1;
169 uint16_t link_partner_autoneg_capable:1;
170
171 } s;
172} cvmx_mdio_phy_reg_autoneg_expansion_t;
173
174/**
175 * PHY register 9 from the 802.3 spec
176 */
177#define CVMX_MDIO_PHY_REG_CONTROL_1000 9
178typedef union {
179 uint16_t u16;
180 struct {
181 uint16_t test_mode:3;
182 uint16_t manual_master_slave:1;
183 uint16_t master:1;
184 uint16_t port_type:1;
185 uint16_t advert_1000base_t_full:1;
186 uint16_t advert_1000base_t_half:1;
187 uint16_t reserved_0_7:8;
188 } s;
189} cvmx_mdio_phy_reg_control_1000_t;
190
191/**
192 * PHY register 10 from the 802.3 spec
193 */
194#define CVMX_MDIO_PHY_REG_STATUS_1000 10
195typedef union {
196 uint16_t u16;
197 struct {
198 uint16_t master_slave_fault:1;
199 uint16_t is_master:1;
200 uint16_t local_receiver_ok:1;
201 uint16_t remote_receiver_ok:1;
202 uint16_t remote_capable_1000base_t_full:1;
203 uint16_t remote_capable_1000base_t_half:1;
204 uint16_t reserved_8_9:2;
205 uint16_t idle_error_count:8;
206 } s;
207} cvmx_mdio_phy_reg_status_1000_t;
208
209/**
210 * PHY register 15 from the 802.3 spec
211 */
212#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15
213typedef union {
214 uint16_t u16;
215 struct {
216 uint16_t capable_1000base_x_full:1;
217 uint16_t capable_1000base_x_half:1;
218 uint16_t capable_1000base_t_full:1;
219 uint16_t capable_1000base_t_half:1;
220 uint16_t reserved_0_11:12;
221 } s;
222} cvmx_mdio_phy_reg_extended_status_t;
223
224/**
225 * PHY register 13 from the 802.3 spec
226 */
227#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13
228typedef union {
229 uint16_t u16;
230 struct {
231 uint16_t function:2;
232 uint16_t reserved_5_13:9;
233 uint16_t devad:5;
234 } s;
235} cvmx_mdio_phy_reg_mmd_control_t;
236
237/**
238 * PHY register 14 from the 802.3 spec
239 */
240#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14
241typedef union {
242 uint16_t u16;
243 struct {
244 uint16_t address_data:16;
245 } s;
246} cvmx_mdio_phy_reg_mmd_address_data_t;
247
248/* Operating request encodings. */
249#define MDIO_CLAUSE_22_WRITE 0
250#define MDIO_CLAUSE_22_READ 1
251
252#define MDIO_CLAUSE_45_ADDRESS 0
253#define MDIO_CLAUSE_45_WRITE 1
254#define MDIO_CLAUSE_45_READ_INC 2
255#define MDIO_CLAUSE_45_READ 3
256
257/* MMD identifiers, mostly for accessing devices within XENPAK modules. */
258#define CVMX_MMD_DEVICE_PMA_PMD 1
259#define CVMX_MMD_DEVICE_WIS 2
260#define CVMX_MMD_DEVICE_PCS 3
261#define CVMX_MMD_DEVICE_PHY_XS 4
262#define CVMX_MMD_DEVICE_DTS_XS 5
263#define CVMX_MMD_DEVICE_TC 6
264#define CVMX_MMD_DEVICE_CL22_EXT 29
265#define CVMX_MMD_DEVICE_VENDOR_1 30
266#define CVMX_MMD_DEVICE_VENDOR_2 31
267
268/* Helper function to put MDIO interface into clause 45 mode */
269static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
270{
271 union cvmx_smix_clk smi_clk;
272 /* Put bus into clause 45 mode */
273 smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
274 smi_clk.s.mode = 1;
275 smi_clk.s.preamble = 1;
276 cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
277}
278
279/* Helper function to put MDIO interface into clause 22 mode */
280static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
281{
282 union cvmx_smix_clk smi_clk;
283 /* Put bus into clause 22 mode */
284 smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
285 smi_clk.s.mode = 0;
286 cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
287}
288
289/**
290 * Perform an MII read. This function is used to read PHY
291 * registers controlling auto negotiation.
292 *
293 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
294 * support multiple busses.
295 * @phy_id: The MII phy id
296 * @location: Register location to read
297 *
298 * Returns Result from the read or -1 on failure
299 */
300static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
301{
302 union cvmx_smix_cmd smi_cmd;
303 union cvmx_smix_rd_dat smi_rd;
304 int timeout = 1000;
305
306 if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
307 __cvmx_mdio_set_clause22_mode(bus_id);
308
309 smi_cmd.u64 = 0;
310 smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ;
311 smi_cmd.s.phy_adr = phy_id;
312 smi_cmd.s.reg_adr = location;
313 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
314
315 do {
316 cvmx_wait(1000);
317 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
318 } while (smi_rd.s.pending && timeout--);
319
320 if (smi_rd.s.val)
321 return smi_rd.s.dat;
322 else
323 return -1;
324}
325
326/**
327 * Perform an MII write. This function is used to write PHY
328 * registers controlling auto negotiation.
329 *
330 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
331 * support multiple busses.
332 * @phy_id: The MII phy id
333 * @location: Register location to write
334 * @val: Value to write
335 *
336 * Returns -1 on error
337 * 0 on success
338 */
339static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
340{
341 union cvmx_smix_cmd smi_cmd;
342 union cvmx_smix_wr_dat smi_wr;
343 int timeout = 1000;
344
345 if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
346 __cvmx_mdio_set_clause22_mode(bus_id);
347
348 smi_wr.u64 = 0;
349 smi_wr.s.dat = val;
350 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
351
352 smi_cmd.u64 = 0;
353 smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE;
354 smi_cmd.s.phy_adr = phy_id;
355 smi_cmd.s.reg_adr = location;
356 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
357
358 do {
359 cvmx_wait(1000);
360 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
361 } while (smi_wr.s.pending && --timeout);
362 if (timeout <= 0)
363 return -1;
364
365 return 0;
366}
367
368/**
369 * Perform an IEEE 802.3 clause 45 MII read. This function is used to
370 * read PHY registers controlling auto negotiation.
371 *
372 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
373 * support multiple busses.
374 * @phy_id: The MII phy id
375 * @device: MDIO Managable Device (MMD) id
376 * @location: Register location to read
377 *
378 * Returns Result from the read or -1 on failure
379 */
380
381static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
382 int location)
383{
384 union cvmx_smix_cmd smi_cmd;
385 union cvmx_smix_rd_dat smi_rd;
386 union cvmx_smix_wr_dat smi_wr;
387 int timeout = 1000;
388
389 if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
390 return -1;
391
392 __cvmx_mdio_set_clause45_mode(bus_id);
393
394 smi_wr.u64 = 0;
395 smi_wr.s.dat = location;
396 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
397
398 smi_cmd.u64 = 0;
399 smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
400 smi_cmd.s.phy_adr = phy_id;
401 smi_cmd.s.reg_adr = device;
402 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
403
404 do {
405 cvmx_wait(1000);
406 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
407 } while (smi_wr.s.pending && --timeout);
408 if (timeout <= 0) {
409 cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
410 "device %2d register %2d TIME OUT(address)\n",
411 bus_id, phy_id, device, location);
412 return -1;
413 }
414
415 smi_cmd.u64 = 0;
416 smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ;
417 smi_cmd.s.phy_adr = phy_id;
418 smi_cmd.s.reg_adr = device;
419 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
420
421 do {
422 cvmx_wait(1000);
423 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
424 } while (smi_rd.s.pending && --timeout);
425
426 if (timeout <= 0) {
427 cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
428 "device %2d register %2d TIME OUT(data)\n",
429 bus_id, phy_id, device, location);
430 return -1;
431 }
432
433 if (smi_rd.s.val)
434 return smi_rd.s.dat;
435 else {
436 cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
437 "device %2d register %2d INVALID READ\n",
438 bus_id, phy_id, device, location);
439 return -1;
440 }
441}
442
443/**
444 * Perform an IEEE 802.3 clause 45 MII write. This function is used to
445 * write PHY registers controlling auto negotiation.
446 *
447 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
448 * support multiple busses.
449 * @phy_id: The MII phy id
450 * @device: MDIO Managable Device (MMD) id
451 * @location: Register location to write
452 * @val: Value to write
453 *
454 * Returns -1 on error
455 * 0 on success
456 */
457static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device,
458 int location, int val)
459{
460 union cvmx_smix_cmd smi_cmd;
461 union cvmx_smix_wr_dat smi_wr;
462 int timeout = 1000;
463
464 if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
465 return -1;
466
467 __cvmx_mdio_set_clause45_mode(bus_id);
468
469 smi_wr.u64 = 0;
470 smi_wr.s.dat = location;
471 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
472
473 smi_cmd.u64 = 0;
474 smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
475 smi_cmd.s.phy_adr = phy_id;
476 smi_cmd.s.reg_adr = device;
477 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
478
479 do {
480 cvmx_wait(1000);
481 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
482 } while (smi_wr.s.pending && --timeout);
483 if (timeout <= 0)
484 return -1;
485
486 smi_wr.u64 = 0;
487 smi_wr.s.dat = val;
488 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
489
490 smi_cmd.u64 = 0;
491 smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE;
492 smi_cmd.s.phy_adr = phy_id;
493 smi_cmd.s.reg_adr = device;
494 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
495
496 do {
497 cvmx_wait(1000);
498 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
499 } while (smi_wr.s.pending && --timeout);
500 if (timeout <= 0)
501 return -1;
502
503 return 0;
504}
505
506#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
index 52b14a333ad4..b1774126736d 100644
--- a/arch/mips/include/asm/octeon/cvmx-mio-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -43,6 +43,22 @@
43#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8) 43#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
44#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8) 44#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
45#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull)) 45#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull))
46#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull))
47#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull))
48#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull))
49#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull))
50#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull))
51#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull))
52#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull))
53#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
54#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull))
55#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull))
56#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull))
57#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull))
58#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull))
59#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull))
60#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull))
61#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull))
46#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8) 62#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
47#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull)) 63#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull))
48#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull)) 64#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull))
@@ -60,6 +76,7 @@
60#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull)) 76#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull))
61#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull)) 77#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull))
62#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull)) 78#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull))
79#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull))
63#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull)) 80#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull))
64#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull)) 81#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull))
65#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull)) 82#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull))
@@ -68,14 +85,25 @@
68#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull)) 85#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull))
69#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull)) 86#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull))
70#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull)) 87#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull))
88#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull))
89#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull))
90#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull))
91#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull))
71#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull)) 92#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull))
72#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull)) 93#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull))
73#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull)) 94#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull))
74#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull)) 95#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull))
75#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull)) 96#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull))
97#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull))
98#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull))
99#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull))
100#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull))
76#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull)) 101#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull))
102#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
77#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull)) 103#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull))
78#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull)) 104#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull))
105#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull))
106#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
79#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8) 107#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
80#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull)) 108#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull))
81#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull)) 109#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull))
@@ -183,11 +211,21 @@ union cvmx_mio_boot_bist_stat {
183 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; 211 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
184 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; 212 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
185 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; 213 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
214 struct cvmx_mio_boot_bist_stat_cn61xx {
215 uint64_t reserved_12_63:52;
216 uint64_t stat:12;
217 } cn61xx;
186 struct cvmx_mio_boot_bist_stat_cn63xx { 218 struct cvmx_mio_boot_bist_stat_cn63xx {
187 uint64_t reserved_9_63:55; 219 uint64_t reserved_9_63:55;
188 uint64_t stat:9; 220 uint64_t stat:9;
189 } cn63xx; 221 } cn63xx;
190 struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1; 222 struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1;
223 struct cvmx_mio_boot_bist_stat_cn66xx {
224 uint64_t reserved_10_63:54;
225 uint64_t stat:10;
226 } cn66xx;
227 struct cvmx_mio_boot_bist_stat_cn66xx cn68xx;
228 struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1;
191}; 229};
192 230
193union cvmx_mio_boot_comp { 231union cvmx_mio_boot_comp {
@@ -204,12 +242,16 @@ union cvmx_mio_boot_comp {
204 struct cvmx_mio_boot_comp_cn50xx cn52xxp1; 242 struct cvmx_mio_boot_comp_cn50xx cn52xxp1;
205 struct cvmx_mio_boot_comp_cn50xx cn56xx; 243 struct cvmx_mio_boot_comp_cn50xx cn56xx;
206 struct cvmx_mio_boot_comp_cn50xx cn56xxp1; 244 struct cvmx_mio_boot_comp_cn50xx cn56xxp1;
207 struct cvmx_mio_boot_comp_cn63xx { 245 struct cvmx_mio_boot_comp_cn61xx {
208 uint64_t reserved_12_63:52; 246 uint64_t reserved_12_63:52;
209 uint64_t pctl:6; 247 uint64_t pctl:6;
210 uint64_t nctl:6; 248 uint64_t nctl:6;
211 } cn63xx; 249 } cn61xx;
212 struct cvmx_mio_boot_comp_cn63xx cn63xxp1; 250 struct cvmx_mio_boot_comp_cn61xx cn63xx;
251 struct cvmx_mio_boot_comp_cn61xx cn63xxp1;
252 struct cvmx_mio_boot_comp_cn61xx cn66xx;
253 struct cvmx_mio_boot_comp_cn61xx cn68xx;
254 struct cvmx_mio_boot_comp_cn61xx cn68xxp1;
213}; 255};
214 256
215union cvmx_mio_boot_dma_cfgx { 257union cvmx_mio_boot_dma_cfgx {
@@ -230,8 +272,12 @@ union cvmx_mio_boot_dma_cfgx {
230 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; 272 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
231 struct cvmx_mio_boot_dma_cfgx_s cn56xx; 273 struct cvmx_mio_boot_dma_cfgx_s cn56xx;
232 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1; 274 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
275 struct cvmx_mio_boot_dma_cfgx_s cn61xx;
233 struct cvmx_mio_boot_dma_cfgx_s cn63xx; 276 struct cvmx_mio_boot_dma_cfgx_s cn63xx;
234 struct cvmx_mio_boot_dma_cfgx_s cn63xxp1; 277 struct cvmx_mio_boot_dma_cfgx_s cn63xxp1;
278 struct cvmx_mio_boot_dma_cfgx_s cn66xx;
279 struct cvmx_mio_boot_dma_cfgx_s cn68xx;
280 struct cvmx_mio_boot_dma_cfgx_s cn68xxp1;
235}; 281};
236 282
237union cvmx_mio_boot_dma_intx { 283union cvmx_mio_boot_dma_intx {
@@ -245,8 +291,12 @@ union cvmx_mio_boot_dma_intx {
245 struct cvmx_mio_boot_dma_intx_s cn52xxp1; 291 struct cvmx_mio_boot_dma_intx_s cn52xxp1;
246 struct cvmx_mio_boot_dma_intx_s cn56xx; 292 struct cvmx_mio_boot_dma_intx_s cn56xx;
247 struct cvmx_mio_boot_dma_intx_s cn56xxp1; 293 struct cvmx_mio_boot_dma_intx_s cn56xxp1;
294 struct cvmx_mio_boot_dma_intx_s cn61xx;
248 struct cvmx_mio_boot_dma_intx_s cn63xx; 295 struct cvmx_mio_boot_dma_intx_s cn63xx;
249 struct cvmx_mio_boot_dma_intx_s cn63xxp1; 296 struct cvmx_mio_boot_dma_intx_s cn63xxp1;
297 struct cvmx_mio_boot_dma_intx_s cn66xx;
298 struct cvmx_mio_boot_dma_intx_s cn68xx;
299 struct cvmx_mio_boot_dma_intx_s cn68xxp1;
250}; 300};
251 301
252union cvmx_mio_boot_dma_int_enx { 302union cvmx_mio_boot_dma_int_enx {
@@ -260,8 +310,12 @@ union cvmx_mio_boot_dma_int_enx {
260 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; 310 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
261 struct cvmx_mio_boot_dma_int_enx_s cn56xx; 311 struct cvmx_mio_boot_dma_int_enx_s cn56xx;
262 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1; 312 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
313 struct cvmx_mio_boot_dma_int_enx_s cn61xx;
263 struct cvmx_mio_boot_dma_int_enx_s cn63xx; 314 struct cvmx_mio_boot_dma_int_enx_s cn63xx;
264 struct cvmx_mio_boot_dma_int_enx_s cn63xxp1; 315 struct cvmx_mio_boot_dma_int_enx_s cn63xxp1;
316 struct cvmx_mio_boot_dma_int_enx_s cn66xx;
317 struct cvmx_mio_boot_dma_int_enx_s cn68xx;
318 struct cvmx_mio_boot_dma_int_enx_s cn68xxp1;
265}; 319};
266 320
267union cvmx_mio_boot_dma_timx { 321union cvmx_mio_boot_dma_timx {
@@ -287,8 +341,12 @@ union cvmx_mio_boot_dma_timx {
287 struct cvmx_mio_boot_dma_timx_s cn52xxp1; 341 struct cvmx_mio_boot_dma_timx_s cn52xxp1;
288 struct cvmx_mio_boot_dma_timx_s cn56xx; 342 struct cvmx_mio_boot_dma_timx_s cn56xx;
289 struct cvmx_mio_boot_dma_timx_s cn56xxp1; 343 struct cvmx_mio_boot_dma_timx_s cn56xxp1;
344 struct cvmx_mio_boot_dma_timx_s cn61xx;
290 struct cvmx_mio_boot_dma_timx_s cn63xx; 345 struct cvmx_mio_boot_dma_timx_s cn63xx;
291 struct cvmx_mio_boot_dma_timx_s cn63xxp1; 346 struct cvmx_mio_boot_dma_timx_s cn63xxp1;
347 struct cvmx_mio_boot_dma_timx_s cn66xx;
348 struct cvmx_mio_boot_dma_timx_s cn68xx;
349 struct cvmx_mio_boot_dma_timx_s cn68xxp1;
292}; 350};
293 351
294union cvmx_mio_boot_err { 352union cvmx_mio_boot_err {
@@ -309,8 +367,12 @@ union cvmx_mio_boot_err {
309 struct cvmx_mio_boot_err_s cn56xxp1; 367 struct cvmx_mio_boot_err_s cn56xxp1;
310 struct cvmx_mio_boot_err_s cn58xx; 368 struct cvmx_mio_boot_err_s cn58xx;
311 struct cvmx_mio_boot_err_s cn58xxp1; 369 struct cvmx_mio_boot_err_s cn58xxp1;
370 struct cvmx_mio_boot_err_s cn61xx;
312 struct cvmx_mio_boot_err_s cn63xx; 371 struct cvmx_mio_boot_err_s cn63xx;
313 struct cvmx_mio_boot_err_s cn63xxp1; 372 struct cvmx_mio_boot_err_s cn63xxp1;
373 struct cvmx_mio_boot_err_s cn66xx;
374 struct cvmx_mio_boot_err_s cn68xx;
375 struct cvmx_mio_boot_err_s cn68xxp1;
314}; 376};
315 377
316union cvmx_mio_boot_int { 378union cvmx_mio_boot_int {
@@ -331,8 +393,12 @@ union cvmx_mio_boot_int {
331 struct cvmx_mio_boot_int_s cn56xxp1; 393 struct cvmx_mio_boot_int_s cn56xxp1;
332 struct cvmx_mio_boot_int_s cn58xx; 394 struct cvmx_mio_boot_int_s cn58xx;
333 struct cvmx_mio_boot_int_s cn58xxp1; 395 struct cvmx_mio_boot_int_s cn58xxp1;
396 struct cvmx_mio_boot_int_s cn61xx;
334 struct cvmx_mio_boot_int_s cn63xx; 397 struct cvmx_mio_boot_int_s cn63xx;
335 struct cvmx_mio_boot_int_s cn63xxp1; 398 struct cvmx_mio_boot_int_s cn63xxp1;
399 struct cvmx_mio_boot_int_s cn66xx;
400 struct cvmx_mio_boot_int_s cn68xx;
401 struct cvmx_mio_boot_int_s cn68xxp1;
336}; 402};
337 403
338union cvmx_mio_boot_loc_adr { 404union cvmx_mio_boot_loc_adr {
@@ -353,8 +419,12 @@ union cvmx_mio_boot_loc_adr {
353 struct cvmx_mio_boot_loc_adr_s cn56xxp1; 419 struct cvmx_mio_boot_loc_adr_s cn56xxp1;
354 struct cvmx_mio_boot_loc_adr_s cn58xx; 420 struct cvmx_mio_boot_loc_adr_s cn58xx;
355 struct cvmx_mio_boot_loc_adr_s cn58xxp1; 421 struct cvmx_mio_boot_loc_adr_s cn58xxp1;
422 struct cvmx_mio_boot_loc_adr_s cn61xx;
356 struct cvmx_mio_boot_loc_adr_s cn63xx; 423 struct cvmx_mio_boot_loc_adr_s cn63xx;
357 struct cvmx_mio_boot_loc_adr_s cn63xxp1; 424 struct cvmx_mio_boot_loc_adr_s cn63xxp1;
425 struct cvmx_mio_boot_loc_adr_s cn66xx;
426 struct cvmx_mio_boot_loc_adr_s cn68xx;
427 struct cvmx_mio_boot_loc_adr_s cn68xxp1;
358}; 428};
359 429
360union cvmx_mio_boot_loc_cfgx { 430union cvmx_mio_boot_loc_cfgx {
@@ -377,8 +447,12 @@ union cvmx_mio_boot_loc_cfgx {
377 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1; 447 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
378 struct cvmx_mio_boot_loc_cfgx_s cn58xx; 448 struct cvmx_mio_boot_loc_cfgx_s cn58xx;
379 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1; 449 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
450 struct cvmx_mio_boot_loc_cfgx_s cn61xx;
380 struct cvmx_mio_boot_loc_cfgx_s cn63xx; 451 struct cvmx_mio_boot_loc_cfgx_s cn63xx;
381 struct cvmx_mio_boot_loc_cfgx_s cn63xxp1; 452 struct cvmx_mio_boot_loc_cfgx_s cn63xxp1;
453 struct cvmx_mio_boot_loc_cfgx_s cn66xx;
454 struct cvmx_mio_boot_loc_cfgx_s cn68xx;
455 struct cvmx_mio_boot_loc_cfgx_s cn68xxp1;
382}; 456};
383 457
384union cvmx_mio_boot_loc_dat { 458union cvmx_mio_boot_loc_dat {
@@ -397,14 +471,19 @@ union cvmx_mio_boot_loc_dat {
397 struct cvmx_mio_boot_loc_dat_s cn56xxp1; 471 struct cvmx_mio_boot_loc_dat_s cn56xxp1;
398 struct cvmx_mio_boot_loc_dat_s cn58xx; 472 struct cvmx_mio_boot_loc_dat_s cn58xx;
399 struct cvmx_mio_boot_loc_dat_s cn58xxp1; 473 struct cvmx_mio_boot_loc_dat_s cn58xxp1;
474 struct cvmx_mio_boot_loc_dat_s cn61xx;
400 struct cvmx_mio_boot_loc_dat_s cn63xx; 475 struct cvmx_mio_boot_loc_dat_s cn63xx;
401 struct cvmx_mio_boot_loc_dat_s cn63xxp1; 476 struct cvmx_mio_boot_loc_dat_s cn63xxp1;
477 struct cvmx_mio_boot_loc_dat_s cn66xx;
478 struct cvmx_mio_boot_loc_dat_s cn68xx;
479 struct cvmx_mio_boot_loc_dat_s cn68xxp1;
402}; 480};
403 481
404union cvmx_mio_boot_pin_defs { 482union cvmx_mio_boot_pin_defs {
405 uint64_t u64; 483 uint64_t u64;
406 struct cvmx_mio_boot_pin_defs_s { 484 struct cvmx_mio_boot_pin_defs_s {
407 uint64_t reserved_16_63:48; 485 uint64_t reserved_32_63:32;
486 uint64_t user1:16;
408 uint64_t ale:1; 487 uint64_t ale:1;
409 uint64_t width:1; 488 uint64_t width:1;
410 uint64_t dmack_p2:1; 489 uint64_t dmack_p2:1;
@@ -412,7 +491,7 @@ union cvmx_mio_boot_pin_defs {
412 uint64_t dmack_p0:1; 491 uint64_t dmack_p0:1;
413 uint64_t term:2; 492 uint64_t term:2;
414 uint64_t nand:1; 493 uint64_t nand:1;
415 uint64_t reserved_0_7:8; 494 uint64_t user0:8;
416 } s; 495 } s;
417 struct cvmx_mio_boot_pin_defs_cn52xx { 496 struct cvmx_mio_boot_pin_defs_cn52xx {
418 uint64_t reserved_16_63:48; 497 uint64_t reserved_16_63:48;
@@ -435,8 +514,23 @@ union cvmx_mio_boot_pin_defs {
435 uint64_t term:2; 514 uint64_t term:2;
436 uint64_t reserved_0_8:9; 515 uint64_t reserved_0_8:9;
437 } cn56xx; 516 } cn56xx;
517 struct cvmx_mio_boot_pin_defs_cn61xx {
518 uint64_t reserved_32_63:32;
519 uint64_t user1:16;
520 uint64_t ale:1;
521 uint64_t width:1;
522 uint64_t reserved_13_13:1;
523 uint64_t dmack_p1:1;
524 uint64_t dmack_p0:1;
525 uint64_t term:2;
526 uint64_t nand:1;
527 uint64_t user0:8;
528 } cn61xx;
438 struct cvmx_mio_boot_pin_defs_cn52xx cn63xx; 529 struct cvmx_mio_boot_pin_defs_cn52xx cn63xx;
439 struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1; 530 struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1;
531 struct cvmx_mio_boot_pin_defs_cn52xx cn66xx;
532 struct cvmx_mio_boot_pin_defs_cn52xx cn68xx;
533 struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1;
440}; 534};
441 535
442union cvmx_mio_boot_reg_cfgx { 536union cvmx_mio_boot_reg_cfgx {
@@ -498,8 +592,12 @@ union cvmx_mio_boot_reg_cfgx {
498 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1; 592 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
499 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx; 593 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
500 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1; 594 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
595 struct cvmx_mio_boot_reg_cfgx_s cn61xx;
501 struct cvmx_mio_boot_reg_cfgx_s cn63xx; 596 struct cvmx_mio_boot_reg_cfgx_s cn63xx;
502 struct cvmx_mio_boot_reg_cfgx_s cn63xxp1; 597 struct cvmx_mio_boot_reg_cfgx_s cn63xxp1;
598 struct cvmx_mio_boot_reg_cfgx_s cn66xx;
599 struct cvmx_mio_boot_reg_cfgx_s cn68xx;
600 struct cvmx_mio_boot_reg_cfgx_s cn68xxp1;
503}; 601};
504 602
505union cvmx_mio_boot_reg_timx { 603union cvmx_mio_boot_reg_timx {
@@ -544,8 +642,12 @@ union cvmx_mio_boot_reg_timx {
544 struct cvmx_mio_boot_reg_timx_s cn56xxp1; 642 struct cvmx_mio_boot_reg_timx_s cn56xxp1;
545 struct cvmx_mio_boot_reg_timx_s cn58xx; 643 struct cvmx_mio_boot_reg_timx_s cn58xx;
546 struct cvmx_mio_boot_reg_timx_s cn58xxp1; 644 struct cvmx_mio_boot_reg_timx_s cn58xxp1;
645 struct cvmx_mio_boot_reg_timx_s cn61xx;
547 struct cvmx_mio_boot_reg_timx_s cn63xx; 646 struct cvmx_mio_boot_reg_timx_s cn63xx;
548 struct cvmx_mio_boot_reg_timx_s cn63xxp1; 647 struct cvmx_mio_boot_reg_timx_s cn63xxp1;
648 struct cvmx_mio_boot_reg_timx_s cn66xx;
649 struct cvmx_mio_boot_reg_timx_s cn68xx;
650 struct cvmx_mio_boot_reg_timx_s cn68xxp1;
549}; 651};
550 652
551union cvmx_mio_boot_thr { 653union cvmx_mio_boot_thr {
@@ -574,8 +676,231 @@ union cvmx_mio_boot_thr {
574 struct cvmx_mio_boot_thr_s cn56xxp1; 676 struct cvmx_mio_boot_thr_s cn56xxp1;
575 struct cvmx_mio_boot_thr_cn30xx cn58xx; 677 struct cvmx_mio_boot_thr_cn30xx cn58xx;
576 struct cvmx_mio_boot_thr_cn30xx cn58xxp1; 678 struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
679 struct cvmx_mio_boot_thr_s cn61xx;
577 struct cvmx_mio_boot_thr_s cn63xx; 680 struct cvmx_mio_boot_thr_s cn63xx;
578 struct cvmx_mio_boot_thr_s cn63xxp1; 681 struct cvmx_mio_boot_thr_s cn63xxp1;
682 struct cvmx_mio_boot_thr_s cn66xx;
683 struct cvmx_mio_boot_thr_s cn68xx;
684 struct cvmx_mio_boot_thr_s cn68xxp1;
685};
686
687union cvmx_mio_emm_buf_dat {
688 uint64_t u64;
689 struct cvmx_mio_emm_buf_dat_s {
690 uint64_t dat:64;
691 } s;
692 struct cvmx_mio_emm_buf_dat_s cn61xx;
693};
694
695union cvmx_mio_emm_buf_idx {
696 uint64_t u64;
697 struct cvmx_mio_emm_buf_idx_s {
698 uint64_t reserved_17_63:47;
699 uint64_t inc:1;
700 uint64_t reserved_7_15:9;
701 uint64_t buf_num:1;
702 uint64_t offset:6;
703 } s;
704 struct cvmx_mio_emm_buf_idx_s cn61xx;
705};
706
707union cvmx_mio_emm_cfg {
708 uint64_t u64;
709 struct cvmx_mio_emm_cfg_s {
710 uint64_t reserved_17_63:47;
711 uint64_t boot_fail:1;
712 uint64_t reserved_4_15:12;
713 uint64_t bus_ena:4;
714 } s;
715 struct cvmx_mio_emm_cfg_s cn61xx;
716};
717
718union cvmx_mio_emm_cmd {
719 uint64_t u64;
720 struct cvmx_mio_emm_cmd_s {
721 uint64_t reserved_62_63:2;
722 uint64_t bus_id:2;
723 uint64_t cmd_val:1;
724 uint64_t reserved_56_58:3;
725 uint64_t dbuf:1;
726 uint64_t offset:6;
727 uint64_t reserved_43_48:6;
728 uint64_t ctype_xor:2;
729 uint64_t rtype_xor:3;
730 uint64_t cmd_idx:6;
731 uint64_t arg:32;
732 } s;
733 struct cvmx_mio_emm_cmd_s cn61xx;
734};
735
736union cvmx_mio_emm_dma {
737 uint64_t u64;
738 struct cvmx_mio_emm_dma_s {
739 uint64_t reserved_62_63:2;
740 uint64_t bus_id:2;
741 uint64_t dma_val:1;
742 uint64_t sector:1;
743 uint64_t dat_null:1;
744 uint64_t thres:6;
745 uint64_t rel_wr:1;
746 uint64_t rw:1;
747 uint64_t multi:1;
748 uint64_t block_cnt:16;
749 uint64_t card_addr:32;
750 } s;
751 struct cvmx_mio_emm_dma_s cn61xx;
752};
753
754union cvmx_mio_emm_int {
755 uint64_t u64;
756 struct cvmx_mio_emm_int_s {
757 uint64_t reserved_7_63:57;
758 uint64_t switch_err:1;
759 uint64_t switch_done:1;
760 uint64_t dma_err:1;
761 uint64_t cmd_err:1;
762 uint64_t dma_done:1;
763 uint64_t cmd_done:1;
764 uint64_t buf_done:1;
765 } s;
766 struct cvmx_mio_emm_int_s cn61xx;
767};
768
769union cvmx_mio_emm_int_en {
770 uint64_t u64;
771 struct cvmx_mio_emm_int_en_s {
772 uint64_t reserved_7_63:57;
773 uint64_t switch_err:1;
774 uint64_t switch_done:1;
775 uint64_t dma_err:1;
776 uint64_t cmd_err:1;
777 uint64_t dma_done:1;
778 uint64_t cmd_done:1;
779 uint64_t buf_done:1;
780 } s;
781 struct cvmx_mio_emm_int_en_s cn61xx;
782};
783
784union cvmx_mio_emm_modex {
785 uint64_t u64;
786 struct cvmx_mio_emm_modex_s {
787 uint64_t reserved_49_63:15;
788 uint64_t hs_timing:1;
789 uint64_t reserved_43_47:5;
790 uint64_t bus_width:3;
791 uint64_t reserved_36_39:4;
792 uint64_t power_class:4;
793 uint64_t clk_hi:16;
794 uint64_t clk_lo:16;
795 } s;
796 struct cvmx_mio_emm_modex_s cn61xx;
797};
798
799union cvmx_mio_emm_rca {
800 uint64_t u64;
801 struct cvmx_mio_emm_rca_s {
802 uint64_t reserved_16_63:48;
803 uint64_t card_rca:16;
804 } s;
805 struct cvmx_mio_emm_rca_s cn61xx;
806};
807
808union cvmx_mio_emm_rsp_hi {
809 uint64_t u64;
810 struct cvmx_mio_emm_rsp_hi_s {
811 uint64_t dat:64;
812 } s;
813 struct cvmx_mio_emm_rsp_hi_s cn61xx;
814};
815
816union cvmx_mio_emm_rsp_lo {
817 uint64_t u64;
818 struct cvmx_mio_emm_rsp_lo_s {
819 uint64_t dat:64;
820 } s;
821 struct cvmx_mio_emm_rsp_lo_s cn61xx;
822};
823
824union cvmx_mio_emm_rsp_sts {
825 uint64_t u64;
826 struct cvmx_mio_emm_rsp_sts_s {
827 uint64_t reserved_62_63:2;
828 uint64_t bus_id:2;
829 uint64_t cmd_val:1;
830 uint64_t switch_val:1;
831 uint64_t dma_val:1;
832 uint64_t dma_pend:1;
833 uint64_t reserved_29_55:27;
834 uint64_t dbuf_err:1;
835 uint64_t reserved_24_27:4;
836 uint64_t dbuf:1;
837 uint64_t blk_timeout:1;
838 uint64_t blk_crc_err:1;
839 uint64_t rsp_busybit:1;
840 uint64_t stp_timeout:1;
841 uint64_t stp_crc_err:1;
842 uint64_t stp_bad_sts:1;
843 uint64_t stp_val:1;
844 uint64_t rsp_timeout:1;
845 uint64_t rsp_crc_err:1;
846 uint64_t rsp_bad_sts:1;
847 uint64_t rsp_val:1;
848 uint64_t rsp_type:3;
849 uint64_t cmd_type:2;
850 uint64_t cmd_idx:6;
851 uint64_t cmd_done:1;
852 } s;
853 struct cvmx_mio_emm_rsp_sts_s cn61xx;
854};
855
856union cvmx_mio_emm_sample {
857 uint64_t u64;
858 struct cvmx_mio_emm_sample_s {
859 uint64_t reserved_26_63:38;
860 uint64_t cmd_cnt:10;
861 uint64_t reserved_10_15:6;
862 uint64_t dat_cnt:10;
863 } s;
864 struct cvmx_mio_emm_sample_s cn61xx;
865};
866
867union cvmx_mio_emm_sts_mask {
868 uint64_t u64;
869 struct cvmx_mio_emm_sts_mask_s {
870 uint64_t reserved_32_63:32;
871 uint64_t sts_msk:32;
872 } s;
873 struct cvmx_mio_emm_sts_mask_s cn61xx;
874};
875
876union cvmx_mio_emm_switch {
877 uint64_t u64;
878 struct cvmx_mio_emm_switch_s {
879 uint64_t reserved_62_63:2;
880 uint64_t bus_id:2;
881 uint64_t switch_exe:1;
882 uint64_t switch_err0:1;
883 uint64_t switch_err1:1;
884 uint64_t switch_err2:1;
885 uint64_t reserved_49_55:7;
886 uint64_t hs_timing:1;
887 uint64_t reserved_43_47:5;
888 uint64_t bus_width:3;
889 uint64_t reserved_36_39:4;
890 uint64_t power_class:4;
891 uint64_t clk_hi:16;
892 uint64_t clk_lo:16;
893 } s;
894 struct cvmx_mio_emm_switch_s cn61xx;
895};
896
897union cvmx_mio_emm_wdog {
898 uint64_t u64;
899 struct cvmx_mio_emm_wdog_s {
900 uint64_t reserved_26_63:38;
901 uint64_t clk_cnt:26;
902 } s;
903 struct cvmx_mio_emm_wdog_s cn61xx;
579}; 904};
580 905
581union cvmx_mio_fus_bnk_datx { 906union cvmx_mio_fus_bnk_datx {
@@ -590,8 +915,12 @@ union cvmx_mio_fus_bnk_datx {
590 struct cvmx_mio_fus_bnk_datx_s cn56xxp1; 915 struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
591 struct cvmx_mio_fus_bnk_datx_s cn58xx; 916 struct cvmx_mio_fus_bnk_datx_s cn58xx;
592 struct cvmx_mio_fus_bnk_datx_s cn58xxp1; 917 struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
918 struct cvmx_mio_fus_bnk_datx_s cn61xx;
593 struct cvmx_mio_fus_bnk_datx_s cn63xx; 919 struct cvmx_mio_fus_bnk_datx_s cn63xx;
594 struct cvmx_mio_fus_bnk_datx_s cn63xxp1; 920 struct cvmx_mio_fus_bnk_datx_s cn63xxp1;
921 struct cvmx_mio_fus_bnk_datx_s cn66xx;
922 struct cvmx_mio_fus_bnk_datx_s cn68xx;
923 struct cvmx_mio_fus_bnk_datx_s cn68xxp1;
595}; 924};
596 925
597union cvmx_mio_fus_dat0 { 926union cvmx_mio_fus_dat0 {
@@ -611,8 +940,12 @@ union cvmx_mio_fus_dat0 {
611 struct cvmx_mio_fus_dat0_s cn56xxp1; 940 struct cvmx_mio_fus_dat0_s cn56xxp1;
612 struct cvmx_mio_fus_dat0_s cn58xx; 941 struct cvmx_mio_fus_dat0_s cn58xx;
613 struct cvmx_mio_fus_dat0_s cn58xxp1; 942 struct cvmx_mio_fus_dat0_s cn58xxp1;
943 struct cvmx_mio_fus_dat0_s cn61xx;
614 struct cvmx_mio_fus_dat0_s cn63xx; 944 struct cvmx_mio_fus_dat0_s cn63xx;
615 struct cvmx_mio_fus_dat0_s cn63xxp1; 945 struct cvmx_mio_fus_dat0_s cn63xxp1;
946 struct cvmx_mio_fus_dat0_s cn66xx;
947 struct cvmx_mio_fus_dat0_s cn68xx;
948 struct cvmx_mio_fus_dat0_s cn68xxp1;
616}; 949};
617 950
618union cvmx_mio_fus_dat1 { 951union cvmx_mio_fus_dat1 {
@@ -632,14 +965,21 @@ union cvmx_mio_fus_dat1 {
632 struct cvmx_mio_fus_dat1_s cn56xxp1; 965 struct cvmx_mio_fus_dat1_s cn56xxp1;
633 struct cvmx_mio_fus_dat1_s cn58xx; 966 struct cvmx_mio_fus_dat1_s cn58xx;
634 struct cvmx_mio_fus_dat1_s cn58xxp1; 967 struct cvmx_mio_fus_dat1_s cn58xxp1;
968 struct cvmx_mio_fus_dat1_s cn61xx;
635 struct cvmx_mio_fus_dat1_s cn63xx; 969 struct cvmx_mio_fus_dat1_s cn63xx;
636 struct cvmx_mio_fus_dat1_s cn63xxp1; 970 struct cvmx_mio_fus_dat1_s cn63xxp1;
971 struct cvmx_mio_fus_dat1_s cn66xx;
972 struct cvmx_mio_fus_dat1_s cn68xx;
973 struct cvmx_mio_fus_dat1_s cn68xxp1;
637}; 974};
638 975
639union cvmx_mio_fus_dat2 { 976union cvmx_mio_fus_dat2 {
640 uint64_t u64; 977 uint64_t u64;
641 struct cvmx_mio_fus_dat2_s { 978 struct cvmx_mio_fus_dat2_s {
642 uint64_t reserved_35_63:29; 979 uint64_t reserved_48_63:16;
980 uint64_t fus118:1;
981 uint64_t rom_info:10;
982 uint64_t power_limit:2;
643 uint64_t dorm_crypto:1; 983 uint64_t dorm_crypto:1;
644 uint64_t fus318:1; 984 uint64_t fus318:1;
645 uint64_t raid_en:1; 985 uint64_t raid_en:1;
@@ -747,6 +1087,23 @@ union cvmx_mio_fus_dat2 {
747 uint64_t pp_dis:16; 1087 uint64_t pp_dis:16;
748 } cn58xx; 1088 } cn58xx;
749 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; 1089 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
1090 struct cvmx_mio_fus_dat2_cn61xx {
1091 uint64_t reserved_48_63:16;
1092 uint64_t fus118:1;
1093 uint64_t rom_info:10;
1094 uint64_t power_limit:2;
1095 uint64_t dorm_crypto:1;
1096 uint64_t fus318:1;
1097 uint64_t raid_en:1;
1098 uint64_t reserved_29_31:3;
1099 uint64_t nodfa_cp2:1;
1100 uint64_t nomul:1;
1101 uint64_t nocrypto:1;
1102 uint64_t reserved_24_25:2;
1103 uint64_t chip_id:8;
1104 uint64_t reserved_4_15:12;
1105 uint64_t pp_dis:4;
1106 } cn61xx;
750 struct cvmx_mio_fus_dat2_cn63xx { 1107 struct cvmx_mio_fus_dat2_cn63xx {
751 uint64_t reserved_35_63:29; 1108 uint64_t reserved_35_63:29;
752 uint64_t dorm_crypto:1; 1109 uint64_t dorm_crypto:1;
@@ -762,6 +1119,38 @@ union cvmx_mio_fus_dat2 {
762 uint64_t pp_dis:6; 1119 uint64_t pp_dis:6;
763 } cn63xx; 1120 } cn63xx;
764 struct cvmx_mio_fus_dat2_cn63xx cn63xxp1; 1121 struct cvmx_mio_fus_dat2_cn63xx cn63xxp1;
1122 struct cvmx_mio_fus_dat2_cn66xx {
1123 uint64_t reserved_48_63:16;
1124 uint64_t fus118:1;
1125 uint64_t rom_info:10;
1126 uint64_t power_limit:2;
1127 uint64_t dorm_crypto:1;
1128 uint64_t fus318:1;
1129 uint64_t raid_en:1;
1130 uint64_t reserved_29_31:3;
1131 uint64_t nodfa_cp2:1;
1132 uint64_t nomul:1;
1133 uint64_t nocrypto:1;
1134 uint64_t reserved_24_25:2;
1135 uint64_t chip_id:8;
1136 uint64_t reserved_10_15:6;
1137 uint64_t pp_dis:10;
1138 } cn66xx;
1139 struct cvmx_mio_fus_dat2_cn68xx {
1140 uint64_t reserved_37_63:27;
1141 uint64_t power_limit:2;
1142 uint64_t dorm_crypto:1;
1143 uint64_t fus318:1;
1144 uint64_t raid_en:1;
1145 uint64_t reserved_29_31:3;
1146 uint64_t nodfa_cp2:1;
1147 uint64_t nomul:1;
1148 uint64_t nocrypto:1;
1149 uint64_t reserved_24_25:2;
1150 uint64_t chip_id:8;
1151 uint64_t reserved_0_15:16;
1152 } cn68xx;
1153 struct cvmx_mio_fus_dat2_cn68xx cn68xxp1;
765}; 1154};
766 1155
767union cvmx_mio_fus_dat3 { 1156union cvmx_mio_fus_dat3 {
@@ -834,7 +1223,7 @@ union cvmx_mio_fus_dat3 {
834 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1; 1223 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
835 struct cvmx_mio_fus_dat3_cn38xx cn58xx; 1224 struct cvmx_mio_fus_dat3_cn38xx cn58xx;
836 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; 1225 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
837 struct cvmx_mio_fus_dat3_cn63xx { 1226 struct cvmx_mio_fus_dat3_cn61xx {
838 uint64_t reserved_58_63:6; 1227 uint64_t reserved_58_63:6;
839 uint64_t pll_ctl:10; 1228 uint64_t pll_ctl:10;
840 uint64_t dfa_info_dte:3; 1229 uint64_t dfa_info_dte:3;
@@ -853,8 +1242,12 @@ union cvmx_mio_fus_dat3 {
853 uint64_t nozip:1; 1242 uint64_t nozip:1;
854 uint64_t nodfa_dte:1; 1243 uint64_t nodfa_dte:1;
855 uint64_t reserved_0_23:24; 1244 uint64_t reserved_0_23:24;
856 } cn63xx; 1245 } cn61xx;
857 struct cvmx_mio_fus_dat3_cn63xx cn63xxp1; 1246 struct cvmx_mio_fus_dat3_cn61xx cn63xx;
1247 struct cvmx_mio_fus_dat3_cn61xx cn63xxp1;
1248 struct cvmx_mio_fus_dat3_cn61xx cn66xx;
1249 struct cvmx_mio_fus_dat3_cn61xx cn68xx;
1250 struct cvmx_mio_fus_dat3_cn61xx cn68xxp1;
858}; 1251};
859 1252
860union cvmx_mio_fus_ema { 1253union cvmx_mio_fus_ema {
@@ -875,8 +1268,12 @@ union cvmx_mio_fus_ema {
875 uint64_t ema:2; 1268 uint64_t ema:2;
876 } cn58xx; 1269 } cn58xx;
877 struct cvmx_mio_fus_ema_cn58xx cn58xxp1; 1270 struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
1271 struct cvmx_mio_fus_ema_s cn61xx;
878 struct cvmx_mio_fus_ema_s cn63xx; 1272 struct cvmx_mio_fus_ema_s cn63xx;
879 struct cvmx_mio_fus_ema_s cn63xxp1; 1273 struct cvmx_mio_fus_ema_s cn63xxp1;
1274 struct cvmx_mio_fus_ema_s cn66xx;
1275 struct cvmx_mio_fus_ema_s cn68xx;
1276 struct cvmx_mio_fus_ema_s cn68xxp1;
880}; 1277};
881 1278
882union cvmx_mio_fus_pdf { 1279union cvmx_mio_fus_pdf {
@@ -890,14 +1287,21 @@ union cvmx_mio_fus_pdf {
890 struct cvmx_mio_fus_pdf_s cn56xx; 1287 struct cvmx_mio_fus_pdf_s cn56xx;
891 struct cvmx_mio_fus_pdf_s cn56xxp1; 1288 struct cvmx_mio_fus_pdf_s cn56xxp1;
892 struct cvmx_mio_fus_pdf_s cn58xx; 1289 struct cvmx_mio_fus_pdf_s cn58xx;
1290 struct cvmx_mio_fus_pdf_s cn61xx;
893 struct cvmx_mio_fus_pdf_s cn63xx; 1291 struct cvmx_mio_fus_pdf_s cn63xx;
894 struct cvmx_mio_fus_pdf_s cn63xxp1; 1292 struct cvmx_mio_fus_pdf_s cn63xxp1;
1293 struct cvmx_mio_fus_pdf_s cn66xx;
1294 struct cvmx_mio_fus_pdf_s cn68xx;
1295 struct cvmx_mio_fus_pdf_s cn68xxp1;
895}; 1296};
896 1297
897union cvmx_mio_fus_pll { 1298union cvmx_mio_fus_pll {
898 uint64_t u64; 1299 uint64_t u64;
899 struct cvmx_mio_fus_pll_s { 1300 struct cvmx_mio_fus_pll_s {
900 uint64_t reserved_8_63:56; 1301 uint64_t reserved_48_63:16;
1302 uint64_t rclk_align_r:8;
1303 uint64_t rclk_align_l:8;
1304 uint64_t reserved_8_31:24;
901 uint64_t c_cout_rst:1; 1305 uint64_t c_cout_rst:1;
902 uint64_t c_cout_sel:2; 1306 uint64_t c_cout_sel:2;
903 uint64_t pnr_cout_rst:1; 1307 uint64_t pnr_cout_rst:1;
@@ -916,8 +1320,20 @@ union cvmx_mio_fus_pll {
916 struct cvmx_mio_fus_pll_cn50xx cn56xxp1; 1320 struct cvmx_mio_fus_pll_cn50xx cn56xxp1;
917 struct cvmx_mio_fus_pll_cn50xx cn58xx; 1321 struct cvmx_mio_fus_pll_cn50xx cn58xx;
918 struct cvmx_mio_fus_pll_cn50xx cn58xxp1; 1322 struct cvmx_mio_fus_pll_cn50xx cn58xxp1;
919 struct cvmx_mio_fus_pll_s cn63xx; 1323 struct cvmx_mio_fus_pll_cn61xx {
920 struct cvmx_mio_fus_pll_s cn63xxp1; 1324 uint64_t reserved_8_63:56;
1325 uint64_t c_cout_rst:1;
1326 uint64_t c_cout_sel:2;
1327 uint64_t pnr_cout_rst:1;
1328 uint64_t pnr_cout_sel:2;
1329 uint64_t rfslip:1;
1330 uint64_t fbslip:1;
1331 } cn61xx;
1332 struct cvmx_mio_fus_pll_cn61xx cn63xx;
1333 struct cvmx_mio_fus_pll_cn61xx cn63xxp1;
1334 struct cvmx_mio_fus_pll_cn61xx cn66xx;
1335 struct cvmx_mio_fus_pll_s cn68xx;
1336 struct cvmx_mio_fus_pll_s cn68xxp1;
921}; 1337};
922 1338
923union cvmx_mio_fus_prog { 1339union cvmx_mio_fus_prog {
@@ -941,8 +1357,12 @@ union cvmx_mio_fus_prog {
941 struct cvmx_mio_fus_prog_cn30xx cn56xxp1; 1357 struct cvmx_mio_fus_prog_cn30xx cn56xxp1;
942 struct cvmx_mio_fus_prog_cn30xx cn58xx; 1358 struct cvmx_mio_fus_prog_cn30xx cn58xx;
943 struct cvmx_mio_fus_prog_cn30xx cn58xxp1; 1359 struct cvmx_mio_fus_prog_cn30xx cn58xxp1;
1360 struct cvmx_mio_fus_prog_s cn61xx;
944 struct cvmx_mio_fus_prog_s cn63xx; 1361 struct cvmx_mio_fus_prog_s cn63xx;
945 struct cvmx_mio_fus_prog_s cn63xxp1; 1362 struct cvmx_mio_fus_prog_s cn63xxp1;
1363 struct cvmx_mio_fus_prog_s cn66xx;
1364 struct cvmx_mio_fus_prog_s cn68xx;
1365 struct cvmx_mio_fus_prog_s cn68xxp1;
946}; 1366};
947 1367
948union cvmx_mio_fus_prog_times { 1368union cvmx_mio_fus_prog_times {
@@ -969,7 +1389,7 @@ union cvmx_mio_fus_prog_times {
969 struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1; 1389 struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1;
970 struct cvmx_mio_fus_prog_times_cn50xx cn58xx; 1390 struct cvmx_mio_fus_prog_times_cn50xx cn58xx;
971 struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1; 1391 struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1;
972 struct cvmx_mio_fus_prog_times_cn63xx { 1392 struct cvmx_mio_fus_prog_times_cn61xx {
973 uint64_t reserved_35_63:29; 1393 uint64_t reserved_35_63:29;
974 uint64_t vgate_pin:1; 1394 uint64_t vgate_pin:1;
975 uint64_t fsrc_pin:1; 1395 uint64_t fsrc_pin:1;
@@ -978,8 +1398,12 @@ union cvmx_mio_fus_prog_times {
978 uint64_t sclk_lo:4; 1398 uint64_t sclk_lo:4;
979 uint64_t sclk_hi:15; 1399 uint64_t sclk_hi:15;
980 uint64_t setup:6; 1400 uint64_t setup:6;
981 } cn63xx; 1401 } cn61xx;
982 struct cvmx_mio_fus_prog_times_cn63xx cn63xxp1; 1402 struct cvmx_mio_fus_prog_times_cn61xx cn63xx;
1403 struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1;
1404 struct cvmx_mio_fus_prog_times_cn61xx cn66xx;
1405 struct cvmx_mio_fus_prog_times_cn61xx cn68xx;
1406 struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1;
983}; 1407};
984 1408
985union cvmx_mio_fus_rcmd { 1409union cvmx_mio_fus_rcmd {
@@ -1013,8 +1437,12 @@ union cvmx_mio_fus_rcmd {
1013 struct cvmx_mio_fus_rcmd_s cn56xxp1; 1437 struct cvmx_mio_fus_rcmd_s cn56xxp1;
1014 struct cvmx_mio_fus_rcmd_cn30xx cn58xx; 1438 struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
1015 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1; 1439 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
1440 struct cvmx_mio_fus_rcmd_s cn61xx;
1016 struct cvmx_mio_fus_rcmd_s cn63xx; 1441 struct cvmx_mio_fus_rcmd_s cn63xx;
1017 struct cvmx_mio_fus_rcmd_s cn63xxp1; 1442 struct cvmx_mio_fus_rcmd_s cn63xxp1;
1443 struct cvmx_mio_fus_rcmd_s cn66xx;
1444 struct cvmx_mio_fus_rcmd_s cn68xx;
1445 struct cvmx_mio_fus_rcmd_s cn68xxp1;
1018}; 1446};
1019 1447
1020union cvmx_mio_fus_read_times { 1448union cvmx_mio_fus_read_times {
@@ -1027,8 +1455,12 @@ union cvmx_mio_fus_read_times {
1027 uint64_t sdh:4; 1455 uint64_t sdh:4;
1028 uint64_t setup:10; 1456 uint64_t setup:10;
1029 } s; 1457 } s;
1458 struct cvmx_mio_fus_read_times_s cn61xx;
1030 struct cvmx_mio_fus_read_times_s cn63xx; 1459 struct cvmx_mio_fus_read_times_s cn63xx;
1031 struct cvmx_mio_fus_read_times_s cn63xxp1; 1460 struct cvmx_mio_fus_read_times_s cn63xxp1;
1461 struct cvmx_mio_fus_read_times_s cn66xx;
1462 struct cvmx_mio_fus_read_times_s cn68xx;
1463 struct cvmx_mio_fus_read_times_s cn68xxp1;
1032}; 1464};
1033 1465
1034union cvmx_mio_fus_repair_res0 { 1466union cvmx_mio_fus_repair_res0 {
@@ -1040,8 +1472,12 @@ union cvmx_mio_fus_repair_res0 {
1040 uint64_t repair1:18; 1472 uint64_t repair1:18;
1041 uint64_t repair0:18; 1473 uint64_t repair0:18;
1042 } s; 1474 } s;
1475 struct cvmx_mio_fus_repair_res0_s cn61xx;
1043 struct cvmx_mio_fus_repair_res0_s cn63xx; 1476 struct cvmx_mio_fus_repair_res0_s cn63xx;
1044 struct cvmx_mio_fus_repair_res0_s cn63xxp1; 1477 struct cvmx_mio_fus_repair_res0_s cn63xxp1;
1478 struct cvmx_mio_fus_repair_res0_s cn66xx;
1479 struct cvmx_mio_fus_repair_res0_s cn68xx;
1480 struct cvmx_mio_fus_repair_res0_s cn68xxp1;
1045}; 1481};
1046 1482
1047union cvmx_mio_fus_repair_res1 { 1483union cvmx_mio_fus_repair_res1 {
@@ -1052,8 +1488,12 @@ union cvmx_mio_fus_repair_res1 {
1052 uint64_t repair4:18; 1488 uint64_t repair4:18;
1053 uint64_t repair3:18; 1489 uint64_t repair3:18;
1054 } s; 1490 } s;
1491 struct cvmx_mio_fus_repair_res1_s cn61xx;
1055 struct cvmx_mio_fus_repair_res1_s cn63xx; 1492 struct cvmx_mio_fus_repair_res1_s cn63xx;
1056 struct cvmx_mio_fus_repair_res1_s cn63xxp1; 1493 struct cvmx_mio_fus_repair_res1_s cn63xxp1;
1494 struct cvmx_mio_fus_repair_res1_s cn66xx;
1495 struct cvmx_mio_fus_repair_res1_s cn68xx;
1496 struct cvmx_mio_fus_repair_res1_s cn68xxp1;
1057}; 1497};
1058 1498
1059union cvmx_mio_fus_repair_res2 { 1499union cvmx_mio_fus_repair_res2 {
@@ -1062,8 +1502,12 @@ union cvmx_mio_fus_repair_res2 {
1062 uint64_t reserved_18_63:46; 1502 uint64_t reserved_18_63:46;
1063 uint64_t repair6:18; 1503 uint64_t repair6:18;
1064 } s; 1504 } s;
1505 struct cvmx_mio_fus_repair_res2_s cn61xx;
1065 struct cvmx_mio_fus_repair_res2_s cn63xx; 1506 struct cvmx_mio_fus_repair_res2_s cn63xx;
1066 struct cvmx_mio_fus_repair_res2_s cn63xxp1; 1507 struct cvmx_mio_fus_repair_res2_s cn63xxp1;
1508 struct cvmx_mio_fus_repair_res2_s cn66xx;
1509 struct cvmx_mio_fus_repair_res2_s cn68xx;
1510 struct cvmx_mio_fus_repair_res2_s cn68xxp1;
1067}; 1511};
1068 1512
1069union cvmx_mio_fus_spr_repair_res { 1513union cvmx_mio_fus_spr_repair_res {
@@ -1084,8 +1528,12 @@ union cvmx_mio_fus_spr_repair_res {
1084 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1; 1528 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
1085 struct cvmx_mio_fus_spr_repair_res_s cn58xx; 1529 struct cvmx_mio_fus_spr_repair_res_s cn58xx;
1086 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1; 1530 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
1531 struct cvmx_mio_fus_spr_repair_res_s cn61xx;
1087 struct cvmx_mio_fus_spr_repair_res_s cn63xx; 1532 struct cvmx_mio_fus_spr_repair_res_s cn63xx;
1088 struct cvmx_mio_fus_spr_repair_res_s cn63xxp1; 1533 struct cvmx_mio_fus_spr_repair_res_s cn63xxp1;
1534 struct cvmx_mio_fus_spr_repair_res_s cn66xx;
1535 struct cvmx_mio_fus_spr_repair_res_s cn68xx;
1536 struct cvmx_mio_fus_spr_repair_res_s cn68xxp1;
1089}; 1537};
1090 1538
1091union cvmx_mio_fus_spr_repair_sum { 1539union cvmx_mio_fus_spr_repair_sum {
@@ -1104,8 +1552,22 @@ union cvmx_mio_fus_spr_repair_sum {
1104 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1; 1552 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
1105 struct cvmx_mio_fus_spr_repair_sum_s cn58xx; 1553 struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
1106 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1; 1554 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
1555 struct cvmx_mio_fus_spr_repair_sum_s cn61xx;
1107 struct cvmx_mio_fus_spr_repair_sum_s cn63xx; 1556 struct cvmx_mio_fus_spr_repair_sum_s cn63xx;
1108 struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1; 1557 struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1;
1558 struct cvmx_mio_fus_spr_repair_sum_s cn66xx;
1559 struct cvmx_mio_fus_spr_repair_sum_s cn68xx;
1560 struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1;
1561};
1562
1563union cvmx_mio_fus_tgg {
1564 uint64_t u64;
1565 struct cvmx_mio_fus_tgg_s {
1566 uint64_t val:1;
1567 uint64_t dat:63;
1568 } s;
1569 struct cvmx_mio_fus_tgg_s cn61xx;
1570 struct cvmx_mio_fus_tgg_s cn66xx;
1109}; 1571};
1110 1572
1111union cvmx_mio_fus_unlock { 1573union cvmx_mio_fus_unlock {
@@ -1141,11 +1603,15 @@ union cvmx_mio_fus_wadr {
1141 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1; 1603 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
1142 struct cvmx_mio_fus_wadr_cn50xx cn58xx; 1604 struct cvmx_mio_fus_wadr_cn50xx cn58xx;
1143 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; 1605 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
1144 struct cvmx_mio_fus_wadr_cn63xx { 1606 struct cvmx_mio_fus_wadr_cn61xx {
1145 uint64_t reserved_4_63:60; 1607 uint64_t reserved_4_63:60;
1146 uint64_t addr:4; 1608 uint64_t addr:4;
1147 } cn63xx; 1609 } cn61xx;
1148 struct cvmx_mio_fus_wadr_cn63xx cn63xxp1; 1610 struct cvmx_mio_fus_wadr_cn61xx cn63xx;
1611 struct cvmx_mio_fus_wadr_cn61xx cn63xxp1;
1612 struct cvmx_mio_fus_wadr_cn61xx cn66xx;
1613 struct cvmx_mio_fus_wadr_cn61xx cn68xx;
1614 struct cvmx_mio_fus_wadr_cn61xx cn68xxp1;
1149}; 1615};
1150 1616
1151union cvmx_mio_gpio_comp { 1617union cvmx_mio_gpio_comp {
@@ -1155,8 +1621,12 @@ union cvmx_mio_gpio_comp {
1155 uint64_t pctl:6; 1621 uint64_t pctl:6;
1156 uint64_t nctl:6; 1622 uint64_t nctl:6;
1157 } s; 1623 } s;
1624 struct cvmx_mio_gpio_comp_s cn61xx;
1158 struct cvmx_mio_gpio_comp_s cn63xx; 1625 struct cvmx_mio_gpio_comp_s cn63xx;
1159 struct cvmx_mio_gpio_comp_s cn63xxp1; 1626 struct cvmx_mio_gpio_comp_s cn63xxp1;
1627 struct cvmx_mio_gpio_comp_s cn66xx;
1628 struct cvmx_mio_gpio_comp_s cn68xx;
1629 struct cvmx_mio_gpio_comp_s cn68xxp1;
1160}; 1630};
1161 1631
1162union cvmx_mio_ndf_dma_cfg { 1632union cvmx_mio_ndf_dma_cfg {
@@ -1174,8 +1644,12 @@ union cvmx_mio_ndf_dma_cfg {
1174 uint64_t adr:36; 1644 uint64_t adr:36;
1175 } s; 1645 } s;
1176 struct cvmx_mio_ndf_dma_cfg_s cn52xx; 1646 struct cvmx_mio_ndf_dma_cfg_s cn52xx;
1647 struct cvmx_mio_ndf_dma_cfg_s cn61xx;
1177 struct cvmx_mio_ndf_dma_cfg_s cn63xx; 1648 struct cvmx_mio_ndf_dma_cfg_s cn63xx;
1178 struct cvmx_mio_ndf_dma_cfg_s cn63xxp1; 1649 struct cvmx_mio_ndf_dma_cfg_s cn63xxp1;
1650 struct cvmx_mio_ndf_dma_cfg_s cn66xx;
1651 struct cvmx_mio_ndf_dma_cfg_s cn68xx;
1652 struct cvmx_mio_ndf_dma_cfg_s cn68xxp1;
1179}; 1653};
1180 1654
1181union cvmx_mio_ndf_dma_int { 1655union cvmx_mio_ndf_dma_int {
@@ -1185,8 +1659,12 @@ union cvmx_mio_ndf_dma_int {
1185 uint64_t done:1; 1659 uint64_t done:1;
1186 } s; 1660 } s;
1187 struct cvmx_mio_ndf_dma_int_s cn52xx; 1661 struct cvmx_mio_ndf_dma_int_s cn52xx;
1662 struct cvmx_mio_ndf_dma_int_s cn61xx;
1188 struct cvmx_mio_ndf_dma_int_s cn63xx; 1663 struct cvmx_mio_ndf_dma_int_s cn63xx;
1189 struct cvmx_mio_ndf_dma_int_s cn63xxp1; 1664 struct cvmx_mio_ndf_dma_int_s cn63xxp1;
1665 struct cvmx_mio_ndf_dma_int_s cn66xx;
1666 struct cvmx_mio_ndf_dma_int_s cn68xx;
1667 struct cvmx_mio_ndf_dma_int_s cn68xxp1;
1190}; 1668};
1191 1669
1192union cvmx_mio_ndf_dma_int_en { 1670union cvmx_mio_ndf_dma_int_en {
@@ -1196,8 +1674,12 @@ union cvmx_mio_ndf_dma_int_en {
1196 uint64_t done:1; 1674 uint64_t done:1;
1197 } s; 1675 } s;
1198 struct cvmx_mio_ndf_dma_int_en_s cn52xx; 1676 struct cvmx_mio_ndf_dma_int_en_s cn52xx;
1677 struct cvmx_mio_ndf_dma_int_en_s cn61xx;
1199 struct cvmx_mio_ndf_dma_int_en_s cn63xx; 1678 struct cvmx_mio_ndf_dma_int_en_s cn63xx;
1200 struct cvmx_mio_ndf_dma_int_en_s cn63xxp1; 1679 struct cvmx_mio_ndf_dma_int_en_s cn63xxp1;
1680 struct cvmx_mio_ndf_dma_int_en_s cn66xx;
1681 struct cvmx_mio_ndf_dma_int_en_s cn68xx;
1682 struct cvmx_mio_ndf_dma_int_en_s cn68xxp1;
1201}; 1683};
1202 1684
1203union cvmx_mio_pll_ctl { 1685union cvmx_mio_pll_ctl {
@@ -1220,10 +1702,63 @@ union cvmx_mio_pll_setting {
1220 struct cvmx_mio_pll_setting_s cn31xx; 1702 struct cvmx_mio_pll_setting_s cn31xx;
1221}; 1703};
1222 1704
1705union cvmx_mio_ptp_ckout_hi_incr {
1706 uint64_t u64;
1707 struct cvmx_mio_ptp_ckout_hi_incr_s {
1708 uint64_t nanosec:32;
1709 uint64_t frnanosec:32;
1710 } s;
1711 struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx;
1712 struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx;
1713 struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx;
1714};
1715
1716union cvmx_mio_ptp_ckout_lo_incr {
1717 uint64_t u64;
1718 struct cvmx_mio_ptp_ckout_lo_incr_s {
1719 uint64_t nanosec:32;
1720 uint64_t frnanosec:32;
1721 } s;
1722 struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx;
1723 struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx;
1724 struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx;
1725};
1726
1727union cvmx_mio_ptp_ckout_thresh_hi {
1728 uint64_t u64;
1729 struct cvmx_mio_ptp_ckout_thresh_hi_s {
1730 uint64_t nanosec:64;
1731 } s;
1732 struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx;
1733 struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx;
1734 struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx;
1735};
1736
1737union cvmx_mio_ptp_ckout_thresh_lo {
1738 uint64_t u64;
1739 struct cvmx_mio_ptp_ckout_thresh_lo_s {
1740 uint64_t reserved_32_63:32;
1741 uint64_t frnanosec:32;
1742 } s;
1743 struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx;
1744 struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx;
1745 struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx;
1746};
1747
1223union cvmx_mio_ptp_clock_cfg { 1748union cvmx_mio_ptp_clock_cfg {
1224 uint64_t u64; 1749 uint64_t u64;
1225 struct cvmx_mio_ptp_clock_cfg_s { 1750 struct cvmx_mio_ptp_clock_cfg_s {
1226 uint64_t reserved_24_63:40; 1751 uint64_t reserved_42_63:22;
1752 uint64_t pps:1;
1753 uint64_t ckout:1;
1754 uint64_t ext_clk_edge:2;
1755 uint64_t ckout_out4:1;
1756 uint64_t pps_out:5;
1757 uint64_t pps_inv:1;
1758 uint64_t pps_en:1;
1759 uint64_t ckout_out:4;
1760 uint64_t ckout_inv:1;
1761 uint64_t ckout_en:1;
1227 uint64_t evcnt_in:6; 1762 uint64_t evcnt_in:6;
1228 uint64_t evcnt_edge:1; 1763 uint64_t evcnt_edge:1;
1229 uint64_t evcnt_en:1; 1764 uint64_t evcnt_en:1;
@@ -1234,8 +1769,42 @@ union cvmx_mio_ptp_clock_cfg {
1234 uint64_t ext_clk_en:1; 1769 uint64_t ext_clk_en:1;
1235 uint64_t ptp_en:1; 1770 uint64_t ptp_en:1;
1236 } s; 1771 } s;
1237 struct cvmx_mio_ptp_clock_cfg_s cn63xx; 1772 struct cvmx_mio_ptp_clock_cfg_s cn61xx;
1238 struct cvmx_mio_ptp_clock_cfg_s cn63xxp1; 1773 struct cvmx_mio_ptp_clock_cfg_cn63xx {
1774 uint64_t reserved_24_63:40;
1775 uint64_t evcnt_in:6;
1776 uint64_t evcnt_edge:1;
1777 uint64_t evcnt_en:1;
1778 uint64_t tstmp_in:6;
1779 uint64_t tstmp_edge:1;
1780 uint64_t tstmp_en:1;
1781 uint64_t ext_clk_in:6;
1782 uint64_t ext_clk_en:1;
1783 uint64_t ptp_en:1;
1784 } cn63xx;
1785 struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1;
1786 struct cvmx_mio_ptp_clock_cfg_cn66xx {
1787 uint64_t reserved_40_63:24;
1788 uint64_t ext_clk_edge:2;
1789 uint64_t ckout_out4:1;
1790 uint64_t pps_out:5;
1791 uint64_t pps_inv:1;
1792 uint64_t pps_en:1;
1793 uint64_t ckout_out:4;
1794 uint64_t ckout_inv:1;
1795 uint64_t ckout_en:1;
1796 uint64_t evcnt_in:6;
1797 uint64_t evcnt_edge:1;
1798 uint64_t evcnt_en:1;
1799 uint64_t tstmp_in:6;
1800 uint64_t tstmp_edge:1;
1801 uint64_t tstmp_en:1;
1802 uint64_t ext_clk_in:6;
1803 uint64_t ext_clk_en:1;
1804 uint64_t ptp_en:1;
1805 } cn66xx;
1806 struct cvmx_mio_ptp_clock_cfg_s cn68xx;
1807 struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1;
1239}; 1808};
1240 1809
1241union cvmx_mio_ptp_clock_comp { 1810union cvmx_mio_ptp_clock_comp {
@@ -1244,8 +1813,12 @@ union cvmx_mio_ptp_clock_comp {
1244 uint64_t nanosec:32; 1813 uint64_t nanosec:32;
1245 uint64_t frnanosec:32; 1814 uint64_t frnanosec:32;
1246 } s; 1815 } s;
1816 struct cvmx_mio_ptp_clock_comp_s cn61xx;
1247 struct cvmx_mio_ptp_clock_comp_s cn63xx; 1817 struct cvmx_mio_ptp_clock_comp_s cn63xx;
1248 struct cvmx_mio_ptp_clock_comp_s cn63xxp1; 1818 struct cvmx_mio_ptp_clock_comp_s cn63xxp1;
1819 struct cvmx_mio_ptp_clock_comp_s cn66xx;
1820 struct cvmx_mio_ptp_clock_comp_s cn68xx;
1821 struct cvmx_mio_ptp_clock_comp_s cn68xxp1;
1249}; 1822};
1250 1823
1251union cvmx_mio_ptp_clock_hi { 1824union cvmx_mio_ptp_clock_hi {
@@ -1253,8 +1826,12 @@ union cvmx_mio_ptp_clock_hi {
1253 struct cvmx_mio_ptp_clock_hi_s { 1826 struct cvmx_mio_ptp_clock_hi_s {
1254 uint64_t nanosec:64; 1827 uint64_t nanosec:64;
1255 } s; 1828 } s;
1829 struct cvmx_mio_ptp_clock_hi_s cn61xx;
1256 struct cvmx_mio_ptp_clock_hi_s cn63xx; 1830 struct cvmx_mio_ptp_clock_hi_s cn63xx;
1257 struct cvmx_mio_ptp_clock_hi_s cn63xxp1; 1831 struct cvmx_mio_ptp_clock_hi_s cn63xxp1;
1832 struct cvmx_mio_ptp_clock_hi_s cn66xx;
1833 struct cvmx_mio_ptp_clock_hi_s cn68xx;
1834 struct cvmx_mio_ptp_clock_hi_s cn68xxp1;
1258}; 1835};
1259 1836
1260union cvmx_mio_ptp_clock_lo { 1837union cvmx_mio_ptp_clock_lo {
@@ -1263,8 +1840,12 @@ union cvmx_mio_ptp_clock_lo {
1263 uint64_t reserved_32_63:32; 1840 uint64_t reserved_32_63:32;
1264 uint64_t frnanosec:32; 1841 uint64_t frnanosec:32;
1265 } s; 1842 } s;
1843 struct cvmx_mio_ptp_clock_lo_s cn61xx;
1266 struct cvmx_mio_ptp_clock_lo_s cn63xx; 1844 struct cvmx_mio_ptp_clock_lo_s cn63xx;
1267 struct cvmx_mio_ptp_clock_lo_s cn63xxp1; 1845 struct cvmx_mio_ptp_clock_lo_s cn63xxp1;
1846 struct cvmx_mio_ptp_clock_lo_s cn66xx;
1847 struct cvmx_mio_ptp_clock_lo_s cn68xx;
1848 struct cvmx_mio_ptp_clock_lo_s cn68xxp1;
1268}; 1849};
1269 1850
1270union cvmx_mio_ptp_evt_cnt { 1851union cvmx_mio_ptp_evt_cnt {
@@ -1272,8 +1853,55 @@ union cvmx_mio_ptp_evt_cnt {
1272 struct cvmx_mio_ptp_evt_cnt_s { 1853 struct cvmx_mio_ptp_evt_cnt_s {
1273 uint64_t cntr:64; 1854 uint64_t cntr:64;
1274 } s; 1855 } s;
1856 struct cvmx_mio_ptp_evt_cnt_s cn61xx;
1275 struct cvmx_mio_ptp_evt_cnt_s cn63xx; 1857 struct cvmx_mio_ptp_evt_cnt_s cn63xx;
1276 struct cvmx_mio_ptp_evt_cnt_s cn63xxp1; 1858 struct cvmx_mio_ptp_evt_cnt_s cn63xxp1;
1859 struct cvmx_mio_ptp_evt_cnt_s cn66xx;
1860 struct cvmx_mio_ptp_evt_cnt_s cn68xx;
1861 struct cvmx_mio_ptp_evt_cnt_s cn68xxp1;
1862};
1863
1864union cvmx_mio_ptp_pps_hi_incr {
1865 uint64_t u64;
1866 struct cvmx_mio_ptp_pps_hi_incr_s {
1867 uint64_t nanosec:32;
1868 uint64_t frnanosec:32;
1869 } s;
1870 struct cvmx_mio_ptp_pps_hi_incr_s cn61xx;
1871 struct cvmx_mio_ptp_pps_hi_incr_s cn66xx;
1872 struct cvmx_mio_ptp_pps_hi_incr_s cn68xx;
1873};
1874
1875union cvmx_mio_ptp_pps_lo_incr {
1876 uint64_t u64;
1877 struct cvmx_mio_ptp_pps_lo_incr_s {
1878 uint64_t nanosec:32;
1879 uint64_t frnanosec:32;
1880 } s;
1881 struct cvmx_mio_ptp_pps_lo_incr_s cn61xx;
1882 struct cvmx_mio_ptp_pps_lo_incr_s cn66xx;
1883 struct cvmx_mio_ptp_pps_lo_incr_s cn68xx;
1884};
1885
1886union cvmx_mio_ptp_pps_thresh_hi {
1887 uint64_t u64;
1888 struct cvmx_mio_ptp_pps_thresh_hi_s {
1889 uint64_t nanosec:64;
1890 } s;
1891 struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx;
1892 struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx;
1893 struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx;
1894};
1895
1896union cvmx_mio_ptp_pps_thresh_lo {
1897 uint64_t u64;
1898 struct cvmx_mio_ptp_pps_thresh_lo_s {
1899 uint64_t reserved_32_63:32;
1900 uint64_t frnanosec:32;
1901 } s;
1902 struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx;
1903 struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx;
1904 struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx;
1277}; 1905};
1278 1906
1279union cvmx_mio_ptp_timestamp { 1907union cvmx_mio_ptp_timestamp {
@@ -1281,14 +1909,52 @@ union cvmx_mio_ptp_timestamp {
1281 struct cvmx_mio_ptp_timestamp_s { 1909 struct cvmx_mio_ptp_timestamp_s {
1282 uint64_t nanosec:64; 1910 uint64_t nanosec:64;
1283 } s; 1911 } s;
1912 struct cvmx_mio_ptp_timestamp_s cn61xx;
1284 struct cvmx_mio_ptp_timestamp_s cn63xx; 1913 struct cvmx_mio_ptp_timestamp_s cn63xx;
1285 struct cvmx_mio_ptp_timestamp_s cn63xxp1; 1914 struct cvmx_mio_ptp_timestamp_s cn63xxp1;
1915 struct cvmx_mio_ptp_timestamp_s cn66xx;
1916 struct cvmx_mio_ptp_timestamp_s cn68xx;
1917 struct cvmx_mio_ptp_timestamp_s cn68xxp1;
1918};
1919
1920union cvmx_mio_qlmx_cfg {
1921 uint64_t u64;
1922 struct cvmx_mio_qlmx_cfg_s {
1923 uint64_t reserved_12_63:52;
1924 uint64_t qlm_spd:4;
1925 uint64_t reserved_4_7:4;
1926 uint64_t qlm_cfg:4;
1927 } s;
1928 struct cvmx_mio_qlmx_cfg_cn61xx {
1929 uint64_t reserved_12_63:52;
1930 uint64_t qlm_spd:4;
1931 uint64_t reserved_2_7:6;
1932 uint64_t qlm_cfg:2;
1933 } cn61xx;
1934 struct cvmx_mio_qlmx_cfg_s cn66xx;
1935 struct cvmx_mio_qlmx_cfg_cn68xx {
1936 uint64_t reserved_12_63:52;
1937 uint64_t qlm_spd:4;
1938 uint64_t reserved_3_7:5;
1939 uint64_t qlm_cfg:3;
1940 } cn68xx;
1941 struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1;
1286}; 1942};
1287 1943
1288union cvmx_mio_rst_boot { 1944union cvmx_mio_rst_boot {
1289 uint64_t u64; 1945 uint64_t u64;
1290 struct cvmx_mio_rst_boot_s { 1946 struct cvmx_mio_rst_boot_s {
1291 uint64_t reserved_36_63:28; 1947 uint64_t chipkill:1;
1948 uint64_t jtcsrdis:1;
1949 uint64_t ejtagdis:1;
1950 uint64_t romen:1;
1951 uint64_t ckill_ppdis:1;
1952 uint64_t jt_tstmode:1;
1953 uint64_t reserved_50_57:8;
1954 uint64_t lboot_ext:2;
1955 uint64_t reserved_44_47:4;
1956 uint64_t qlm4_spd:4;
1957 uint64_t qlm3_spd:4;
1292 uint64_t c_mul:6; 1958 uint64_t c_mul:6;
1293 uint64_t pnr_mul:6; 1959 uint64_t pnr_mul:6;
1294 uint64_t qlm2_spd:4; 1960 uint64_t qlm2_spd:4;
@@ -1298,32 +1964,168 @@ union cvmx_mio_rst_boot {
1298 uint64_t rboot:1; 1964 uint64_t rboot:1;
1299 uint64_t rboot_pin:1; 1965 uint64_t rboot_pin:1;
1300 } s; 1966 } s;
1301 struct cvmx_mio_rst_boot_s cn63xx; 1967 struct cvmx_mio_rst_boot_cn61xx {
1302 struct cvmx_mio_rst_boot_s cn63xxp1; 1968 uint64_t chipkill:1;
1969 uint64_t jtcsrdis:1;
1970 uint64_t ejtagdis:1;
1971 uint64_t romen:1;
1972 uint64_t ckill_ppdis:1;
1973 uint64_t jt_tstmode:1;
1974 uint64_t reserved_50_57:8;
1975 uint64_t lboot_ext:2;
1976 uint64_t reserved_36_47:12;
1977 uint64_t c_mul:6;
1978 uint64_t pnr_mul:6;
1979 uint64_t qlm2_spd:4;
1980 uint64_t qlm1_spd:4;
1981 uint64_t qlm0_spd:4;
1982 uint64_t lboot:10;
1983 uint64_t rboot:1;
1984 uint64_t rboot_pin:1;
1985 } cn61xx;
1986 struct cvmx_mio_rst_boot_cn63xx {
1987 uint64_t reserved_36_63:28;
1988 uint64_t c_mul:6;
1989 uint64_t pnr_mul:6;
1990 uint64_t qlm2_spd:4;
1991 uint64_t qlm1_spd:4;
1992 uint64_t qlm0_spd:4;
1993 uint64_t lboot:10;
1994 uint64_t rboot:1;
1995 uint64_t rboot_pin:1;
1996 } cn63xx;
1997 struct cvmx_mio_rst_boot_cn63xx cn63xxp1;
1998 struct cvmx_mio_rst_boot_cn66xx {
1999 uint64_t chipkill:1;
2000 uint64_t jtcsrdis:1;
2001 uint64_t ejtagdis:1;
2002 uint64_t romen:1;
2003 uint64_t ckill_ppdis:1;
2004 uint64_t reserved_50_58:9;
2005 uint64_t lboot_ext:2;
2006 uint64_t reserved_36_47:12;
2007 uint64_t c_mul:6;
2008 uint64_t pnr_mul:6;
2009 uint64_t qlm2_spd:4;
2010 uint64_t qlm1_spd:4;
2011 uint64_t qlm0_spd:4;
2012 uint64_t lboot:10;
2013 uint64_t rboot:1;
2014 uint64_t rboot_pin:1;
2015 } cn66xx;
2016 struct cvmx_mio_rst_boot_cn68xx {
2017 uint64_t reserved_59_63:5;
2018 uint64_t jt_tstmode:1;
2019 uint64_t reserved_44_57:14;
2020 uint64_t qlm4_spd:4;
2021 uint64_t qlm3_spd:4;
2022 uint64_t c_mul:6;
2023 uint64_t pnr_mul:6;
2024 uint64_t qlm2_spd:4;
2025 uint64_t qlm1_spd:4;
2026 uint64_t qlm0_spd:4;
2027 uint64_t lboot:10;
2028 uint64_t rboot:1;
2029 uint64_t rboot_pin:1;
2030 } cn68xx;
2031 struct cvmx_mio_rst_boot_cn68xxp1 {
2032 uint64_t reserved_44_63:20;
2033 uint64_t qlm4_spd:4;
2034 uint64_t qlm3_spd:4;
2035 uint64_t c_mul:6;
2036 uint64_t pnr_mul:6;
2037 uint64_t qlm2_spd:4;
2038 uint64_t qlm1_spd:4;
2039 uint64_t qlm0_spd:4;
2040 uint64_t lboot:10;
2041 uint64_t rboot:1;
2042 uint64_t rboot_pin:1;
2043 } cn68xxp1;
1303}; 2044};
1304 2045
1305union cvmx_mio_rst_cfg { 2046union cvmx_mio_rst_cfg {
1306 uint64_t u64; 2047 uint64_t u64;
1307 struct cvmx_mio_rst_cfg_s { 2048 struct cvmx_mio_rst_cfg_s {
2049 uint64_t reserved_3_63:61;
2050 uint64_t cntl_clr_bist:1;
2051 uint64_t warm_clr_bist:1;
2052 uint64_t soft_clr_bist:1;
2053 } s;
2054 struct cvmx_mio_rst_cfg_cn61xx {
1308 uint64_t bist_delay:58; 2055 uint64_t bist_delay:58;
1309 uint64_t reserved_3_5:3; 2056 uint64_t reserved_3_5:3;
1310 uint64_t cntl_clr_bist:1; 2057 uint64_t cntl_clr_bist:1;
1311 uint64_t warm_clr_bist:1; 2058 uint64_t warm_clr_bist:1;
1312 uint64_t soft_clr_bist:1; 2059 uint64_t soft_clr_bist:1;
1313 } s; 2060 } cn61xx;
1314 struct cvmx_mio_rst_cfg_s cn63xx; 2061 struct cvmx_mio_rst_cfg_cn61xx cn63xx;
1315 struct cvmx_mio_rst_cfg_cn63xxp1 { 2062 struct cvmx_mio_rst_cfg_cn63xxp1 {
1316 uint64_t bist_delay:58; 2063 uint64_t bist_delay:58;
1317 uint64_t reserved_2_5:4; 2064 uint64_t reserved_2_5:4;
1318 uint64_t warm_clr_bist:1; 2065 uint64_t warm_clr_bist:1;
1319 uint64_t soft_clr_bist:1; 2066 uint64_t soft_clr_bist:1;
1320 } cn63xxp1; 2067 } cn63xxp1;
2068 struct cvmx_mio_rst_cfg_cn61xx cn66xx;
2069 struct cvmx_mio_rst_cfg_cn68xx {
2070 uint64_t bist_delay:56;
2071 uint64_t reserved_3_7:5;
2072 uint64_t cntl_clr_bist:1;
2073 uint64_t warm_clr_bist:1;
2074 uint64_t soft_clr_bist:1;
2075 } cn68xx;
2076 struct cvmx_mio_rst_cfg_cn68xx cn68xxp1;
2077};
2078
2079union cvmx_mio_rst_ckill {
2080 uint64_t u64;
2081 struct cvmx_mio_rst_ckill_s {
2082 uint64_t reserved_47_63:17;
2083 uint64_t timer:47;
2084 } s;
2085 struct cvmx_mio_rst_ckill_s cn61xx;
2086 struct cvmx_mio_rst_ckill_s cn66xx;
2087};
2088
2089union cvmx_mio_rst_cntlx {
2090 uint64_t u64;
2091 struct cvmx_mio_rst_cntlx_s {
2092 uint64_t reserved_13_63:51;
2093 uint64_t in_rev_ln:1;
2094 uint64_t rev_lanes:1;
2095 uint64_t gen1_only:1;
2096 uint64_t prst_link:1;
2097 uint64_t rst_done:1;
2098 uint64_t rst_link:1;
2099 uint64_t host_mode:1;
2100 uint64_t prtmode:2;
2101 uint64_t rst_drv:1;
2102 uint64_t rst_rcv:1;
2103 uint64_t rst_chip:1;
2104 uint64_t rst_val:1;
2105 } s;
2106 struct cvmx_mio_rst_cntlx_s cn61xx;
2107 struct cvmx_mio_rst_cntlx_cn66xx {
2108 uint64_t reserved_10_63:54;
2109 uint64_t prst_link:1;
2110 uint64_t rst_done:1;
2111 uint64_t rst_link:1;
2112 uint64_t host_mode:1;
2113 uint64_t prtmode:2;
2114 uint64_t rst_drv:1;
2115 uint64_t rst_rcv:1;
2116 uint64_t rst_chip:1;
2117 uint64_t rst_val:1;
2118 } cn66xx;
2119 struct cvmx_mio_rst_cntlx_cn66xx cn68xx;
1321}; 2120};
1322 2121
1323union cvmx_mio_rst_ctlx { 2122union cvmx_mio_rst_ctlx {
1324 uint64_t u64; 2123 uint64_t u64;
1325 struct cvmx_mio_rst_ctlx_s { 2124 struct cvmx_mio_rst_ctlx_s {
1326 uint64_t reserved_10_63:54; 2125 uint64_t reserved_13_63:51;
2126 uint64_t in_rev_ln:1;
2127 uint64_t rev_lanes:1;
2128 uint64_t gen1_only:1;
1327 uint64_t prst_link:1; 2129 uint64_t prst_link:1;
1328 uint64_t rst_done:1; 2130 uint64_t rst_done:1;
1329 uint64_t rst_link:1; 2131 uint64_t rst_link:1;
@@ -1334,7 +2136,19 @@ union cvmx_mio_rst_ctlx {
1334 uint64_t rst_chip:1; 2136 uint64_t rst_chip:1;
1335 uint64_t rst_val:1; 2137 uint64_t rst_val:1;
1336 } s; 2138 } s;
1337 struct cvmx_mio_rst_ctlx_s cn63xx; 2139 struct cvmx_mio_rst_ctlx_s cn61xx;
2140 struct cvmx_mio_rst_ctlx_cn63xx {
2141 uint64_t reserved_10_63:54;
2142 uint64_t prst_link:1;
2143 uint64_t rst_done:1;
2144 uint64_t rst_link:1;
2145 uint64_t host_mode:1;
2146 uint64_t prtmode:2;
2147 uint64_t rst_drv:1;
2148 uint64_t rst_rcv:1;
2149 uint64_t rst_chip:1;
2150 uint64_t rst_val:1;
2151 } cn63xx;
1338 struct cvmx_mio_rst_ctlx_cn63xxp1 { 2152 struct cvmx_mio_rst_ctlx_cn63xxp1 {
1339 uint64_t reserved_9_63:55; 2153 uint64_t reserved_9_63:55;
1340 uint64_t rst_done:1; 2154 uint64_t rst_done:1;
@@ -1346,17 +2160,24 @@ union cvmx_mio_rst_ctlx {
1346 uint64_t rst_chip:1; 2160 uint64_t rst_chip:1;
1347 uint64_t rst_val:1; 2161 uint64_t rst_val:1;
1348 } cn63xxp1; 2162 } cn63xxp1;
2163 struct cvmx_mio_rst_ctlx_cn63xx cn66xx;
2164 struct cvmx_mio_rst_ctlx_cn63xx cn68xx;
2165 struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1;
1349}; 2166};
1350 2167
1351union cvmx_mio_rst_delay { 2168union cvmx_mio_rst_delay {
1352 uint64_t u64; 2169 uint64_t u64;
1353 struct cvmx_mio_rst_delay_s { 2170 struct cvmx_mio_rst_delay_s {
1354 uint64_t reserved_32_63:32; 2171 uint64_t reserved_32_63:32;
1355 uint64_t soft_rst_dly:16;
1356 uint64_t warm_rst_dly:16; 2172 uint64_t warm_rst_dly:16;
2173 uint64_t soft_rst_dly:16;
1357 } s; 2174 } s;
2175 struct cvmx_mio_rst_delay_s cn61xx;
1358 struct cvmx_mio_rst_delay_s cn63xx; 2176 struct cvmx_mio_rst_delay_s cn63xx;
1359 struct cvmx_mio_rst_delay_s cn63xxp1; 2177 struct cvmx_mio_rst_delay_s cn63xxp1;
2178 struct cvmx_mio_rst_delay_s cn66xx;
2179 struct cvmx_mio_rst_delay_s cn68xx;
2180 struct cvmx_mio_rst_delay_s cn68xxp1;
1360}; 2181};
1361 2182
1362union cvmx_mio_rst_int { 2183union cvmx_mio_rst_int {
@@ -1365,12 +2186,25 @@ union cvmx_mio_rst_int {
1365 uint64_t reserved_10_63:54; 2186 uint64_t reserved_10_63:54;
1366 uint64_t perst1:1; 2187 uint64_t perst1:1;
1367 uint64_t perst0:1; 2188 uint64_t perst0:1;
1368 uint64_t reserved_2_7:6; 2189 uint64_t reserved_4_7:4;
2190 uint64_t rst_link3:1;
2191 uint64_t rst_link2:1;
1369 uint64_t rst_link1:1; 2192 uint64_t rst_link1:1;
1370 uint64_t rst_link0:1; 2193 uint64_t rst_link0:1;
1371 } s; 2194 } s;
1372 struct cvmx_mio_rst_int_s cn63xx; 2195 struct cvmx_mio_rst_int_cn61xx {
1373 struct cvmx_mio_rst_int_s cn63xxp1; 2196 uint64_t reserved_10_63:54;
2197 uint64_t perst1:1;
2198 uint64_t perst0:1;
2199 uint64_t reserved_2_7:6;
2200 uint64_t rst_link1:1;
2201 uint64_t rst_link0:1;
2202 } cn61xx;
2203 struct cvmx_mio_rst_int_cn61xx cn63xx;
2204 struct cvmx_mio_rst_int_cn61xx cn63xxp1;
2205 struct cvmx_mio_rst_int_s cn66xx;
2206 struct cvmx_mio_rst_int_cn61xx cn68xx;
2207 struct cvmx_mio_rst_int_cn61xx cn68xxp1;
1374}; 2208};
1375 2209
1376union cvmx_mio_rst_int_en { 2210union cvmx_mio_rst_int_en {
@@ -1379,12 +2213,25 @@ union cvmx_mio_rst_int_en {
1379 uint64_t reserved_10_63:54; 2213 uint64_t reserved_10_63:54;
1380 uint64_t perst1:1; 2214 uint64_t perst1:1;
1381 uint64_t perst0:1; 2215 uint64_t perst0:1;
1382 uint64_t reserved_2_7:6; 2216 uint64_t reserved_4_7:4;
2217 uint64_t rst_link3:1;
2218 uint64_t rst_link2:1;
1383 uint64_t rst_link1:1; 2219 uint64_t rst_link1:1;
1384 uint64_t rst_link0:1; 2220 uint64_t rst_link0:1;
1385 } s; 2221 } s;
1386 struct cvmx_mio_rst_int_en_s cn63xx; 2222 struct cvmx_mio_rst_int_en_cn61xx {
1387 struct cvmx_mio_rst_int_en_s cn63xxp1; 2223 uint64_t reserved_10_63:54;
2224 uint64_t perst1:1;
2225 uint64_t perst0:1;
2226 uint64_t reserved_2_7:6;
2227 uint64_t rst_link1:1;
2228 uint64_t rst_link0:1;
2229 } cn61xx;
2230 struct cvmx_mio_rst_int_en_cn61xx cn63xx;
2231 struct cvmx_mio_rst_int_en_cn61xx cn63xxp1;
2232 struct cvmx_mio_rst_int_en_s cn66xx;
2233 struct cvmx_mio_rst_int_en_cn61xx cn68xx;
2234 struct cvmx_mio_rst_int_en_cn61xx cn68xxp1;
1388}; 2235};
1389 2236
1390union cvmx_mio_twsx_int { 2237union cvmx_mio_twsx_int {
@@ -1424,8 +2271,12 @@ union cvmx_mio_twsx_int {
1424 struct cvmx_mio_twsx_int_s cn56xxp1; 2271 struct cvmx_mio_twsx_int_s cn56xxp1;
1425 struct cvmx_mio_twsx_int_s cn58xx; 2272 struct cvmx_mio_twsx_int_s cn58xx;
1426 struct cvmx_mio_twsx_int_s cn58xxp1; 2273 struct cvmx_mio_twsx_int_s cn58xxp1;
2274 struct cvmx_mio_twsx_int_s cn61xx;
1427 struct cvmx_mio_twsx_int_s cn63xx; 2275 struct cvmx_mio_twsx_int_s cn63xx;
1428 struct cvmx_mio_twsx_int_s cn63xxp1; 2276 struct cvmx_mio_twsx_int_s cn63xxp1;
2277 struct cvmx_mio_twsx_int_s cn66xx;
2278 struct cvmx_mio_twsx_int_s cn68xx;
2279 struct cvmx_mio_twsx_int_s cn68xxp1;
1429}; 2280};
1430 2281
1431union cvmx_mio_twsx_sw_twsi { 2282union cvmx_mio_twsx_sw_twsi {
@@ -1455,8 +2306,12 @@ union cvmx_mio_twsx_sw_twsi {
1455 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1; 2306 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
1456 struct cvmx_mio_twsx_sw_twsi_s cn58xx; 2307 struct cvmx_mio_twsx_sw_twsi_s cn58xx;
1457 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1; 2308 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
2309 struct cvmx_mio_twsx_sw_twsi_s cn61xx;
1458 struct cvmx_mio_twsx_sw_twsi_s cn63xx; 2310 struct cvmx_mio_twsx_sw_twsi_s cn63xx;
1459 struct cvmx_mio_twsx_sw_twsi_s cn63xxp1; 2311 struct cvmx_mio_twsx_sw_twsi_s cn63xxp1;
2312 struct cvmx_mio_twsx_sw_twsi_s cn66xx;
2313 struct cvmx_mio_twsx_sw_twsi_s cn68xx;
2314 struct cvmx_mio_twsx_sw_twsi_s cn68xxp1;
1460}; 2315};
1461 2316
1462union cvmx_mio_twsx_sw_twsi_ext { 2317union cvmx_mio_twsx_sw_twsi_ext {
@@ -1477,8 +2332,12 @@ union cvmx_mio_twsx_sw_twsi_ext {
1477 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1; 2332 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
1478 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx; 2333 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
1479 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1; 2334 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
2335 struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx;
1480 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx; 2336 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx;
1481 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1; 2337 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1;
2338 struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx;
2339 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx;
2340 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1;
1482}; 2341};
1483 2342
1484union cvmx_mio_twsx_twsi_sw { 2343union cvmx_mio_twsx_twsi_sw {
@@ -1499,8 +2358,12 @@ union cvmx_mio_twsx_twsi_sw {
1499 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1; 2358 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
1500 struct cvmx_mio_twsx_twsi_sw_s cn58xx; 2359 struct cvmx_mio_twsx_twsi_sw_s cn58xx;
1501 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1; 2360 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
2361 struct cvmx_mio_twsx_twsi_sw_s cn61xx;
1502 struct cvmx_mio_twsx_twsi_sw_s cn63xx; 2362 struct cvmx_mio_twsx_twsi_sw_s cn63xx;
1503 struct cvmx_mio_twsx_twsi_sw_s cn63xxp1; 2363 struct cvmx_mio_twsx_twsi_sw_s cn63xxp1;
2364 struct cvmx_mio_twsx_twsi_sw_s cn66xx;
2365 struct cvmx_mio_twsx_twsi_sw_s cn68xx;
2366 struct cvmx_mio_twsx_twsi_sw_s cn68xxp1;
1504}; 2367};
1505 2368
1506union cvmx_mio_uartx_dlh { 2369union cvmx_mio_uartx_dlh {
@@ -1520,8 +2383,12 @@ union cvmx_mio_uartx_dlh {
1520 struct cvmx_mio_uartx_dlh_s cn56xxp1; 2383 struct cvmx_mio_uartx_dlh_s cn56xxp1;
1521 struct cvmx_mio_uartx_dlh_s cn58xx; 2384 struct cvmx_mio_uartx_dlh_s cn58xx;
1522 struct cvmx_mio_uartx_dlh_s cn58xxp1; 2385 struct cvmx_mio_uartx_dlh_s cn58xxp1;
2386 struct cvmx_mio_uartx_dlh_s cn61xx;
1523 struct cvmx_mio_uartx_dlh_s cn63xx; 2387 struct cvmx_mio_uartx_dlh_s cn63xx;
1524 struct cvmx_mio_uartx_dlh_s cn63xxp1; 2388 struct cvmx_mio_uartx_dlh_s cn63xxp1;
2389 struct cvmx_mio_uartx_dlh_s cn66xx;
2390 struct cvmx_mio_uartx_dlh_s cn68xx;
2391 struct cvmx_mio_uartx_dlh_s cn68xxp1;
1525}; 2392};
1526 2393
1527union cvmx_mio_uartx_dll { 2394union cvmx_mio_uartx_dll {
@@ -1541,8 +2408,12 @@ union cvmx_mio_uartx_dll {
1541 struct cvmx_mio_uartx_dll_s cn56xxp1; 2408 struct cvmx_mio_uartx_dll_s cn56xxp1;
1542 struct cvmx_mio_uartx_dll_s cn58xx; 2409 struct cvmx_mio_uartx_dll_s cn58xx;
1543 struct cvmx_mio_uartx_dll_s cn58xxp1; 2410 struct cvmx_mio_uartx_dll_s cn58xxp1;
2411 struct cvmx_mio_uartx_dll_s cn61xx;
1544 struct cvmx_mio_uartx_dll_s cn63xx; 2412 struct cvmx_mio_uartx_dll_s cn63xx;
1545 struct cvmx_mio_uartx_dll_s cn63xxp1; 2413 struct cvmx_mio_uartx_dll_s cn63xxp1;
2414 struct cvmx_mio_uartx_dll_s cn66xx;
2415 struct cvmx_mio_uartx_dll_s cn68xx;
2416 struct cvmx_mio_uartx_dll_s cn68xxp1;
1546}; 2417};
1547 2418
1548union cvmx_mio_uartx_far { 2419union cvmx_mio_uartx_far {
@@ -1562,8 +2433,12 @@ union cvmx_mio_uartx_far {
1562 struct cvmx_mio_uartx_far_s cn56xxp1; 2433 struct cvmx_mio_uartx_far_s cn56xxp1;
1563 struct cvmx_mio_uartx_far_s cn58xx; 2434 struct cvmx_mio_uartx_far_s cn58xx;
1564 struct cvmx_mio_uartx_far_s cn58xxp1; 2435 struct cvmx_mio_uartx_far_s cn58xxp1;
2436 struct cvmx_mio_uartx_far_s cn61xx;
1565 struct cvmx_mio_uartx_far_s cn63xx; 2437 struct cvmx_mio_uartx_far_s cn63xx;
1566 struct cvmx_mio_uartx_far_s cn63xxp1; 2438 struct cvmx_mio_uartx_far_s cn63xxp1;
2439 struct cvmx_mio_uartx_far_s cn66xx;
2440 struct cvmx_mio_uartx_far_s cn68xx;
2441 struct cvmx_mio_uartx_far_s cn68xxp1;
1567}; 2442};
1568 2443
1569union cvmx_mio_uartx_fcr { 2444union cvmx_mio_uartx_fcr {
@@ -1588,8 +2463,12 @@ union cvmx_mio_uartx_fcr {
1588 struct cvmx_mio_uartx_fcr_s cn56xxp1; 2463 struct cvmx_mio_uartx_fcr_s cn56xxp1;
1589 struct cvmx_mio_uartx_fcr_s cn58xx; 2464 struct cvmx_mio_uartx_fcr_s cn58xx;
1590 struct cvmx_mio_uartx_fcr_s cn58xxp1; 2465 struct cvmx_mio_uartx_fcr_s cn58xxp1;
2466 struct cvmx_mio_uartx_fcr_s cn61xx;
1591 struct cvmx_mio_uartx_fcr_s cn63xx; 2467 struct cvmx_mio_uartx_fcr_s cn63xx;
1592 struct cvmx_mio_uartx_fcr_s cn63xxp1; 2468 struct cvmx_mio_uartx_fcr_s cn63xxp1;
2469 struct cvmx_mio_uartx_fcr_s cn66xx;
2470 struct cvmx_mio_uartx_fcr_s cn68xx;
2471 struct cvmx_mio_uartx_fcr_s cn68xxp1;
1593}; 2472};
1594 2473
1595union cvmx_mio_uartx_htx { 2474union cvmx_mio_uartx_htx {
@@ -1609,8 +2488,12 @@ union cvmx_mio_uartx_htx {
1609 struct cvmx_mio_uartx_htx_s cn56xxp1; 2488 struct cvmx_mio_uartx_htx_s cn56xxp1;
1610 struct cvmx_mio_uartx_htx_s cn58xx; 2489 struct cvmx_mio_uartx_htx_s cn58xx;
1611 struct cvmx_mio_uartx_htx_s cn58xxp1; 2490 struct cvmx_mio_uartx_htx_s cn58xxp1;
2491 struct cvmx_mio_uartx_htx_s cn61xx;
1612 struct cvmx_mio_uartx_htx_s cn63xx; 2492 struct cvmx_mio_uartx_htx_s cn63xx;
1613 struct cvmx_mio_uartx_htx_s cn63xxp1; 2493 struct cvmx_mio_uartx_htx_s cn63xxp1;
2494 struct cvmx_mio_uartx_htx_s cn66xx;
2495 struct cvmx_mio_uartx_htx_s cn68xx;
2496 struct cvmx_mio_uartx_htx_s cn68xxp1;
1614}; 2497};
1615 2498
1616union cvmx_mio_uartx_ier { 2499union cvmx_mio_uartx_ier {
@@ -1635,8 +2518,12 @@ union cvmx_mio_uartx_ier {
1635 struct cvmx_mio_uartx_ier_s cn56xxp1; 2518 struct cvmx_mio_uartx_ier_s cn56xxp1;
1636 struct cvmx_mio_uartx_ier_s cn58xx; 2519 struct cvmx_mio_uartx_ier_s cn58xx;
1637 struct cvmx_mio_uartx_ier_s cn58xxp1; 2520 struct cvmx_mio_uartx_ier_s cn58xxp1;
2521 struct cvmx_mio_uartx_ier_s cn61xx;
1638 struct cvmx_mio_uartx_ier_s cn63xx; 2522 struct cvmx_mio_uartx_ier_s cn63xx;
1639 struct cvmx_mio_uartx_ier_s cn63xxp1; 2523 struct cvmx_mio_uartx_ier_s cn63xxp1;
2524 struct cvmx_mio_uartx_ier_s cn66xx;
2525 struct cvmx_mio_uartx_ier_s cn68xx;
2526 struct cvmx_mio_uartx_ier_s cn68xxp1;
1640}; 2527};
1641 2528
1642union cvmx_mio_uartx_iir { 2529union cvmx_mio_uartx_iir {
@@ -1658,8 +2545,12 @@ union cvmx_mio_uartx_iir {
1658 struct cvmx_mio_uartx_iir_s cn56xxp1; 2545 struct cvmx_mio_uartx_iir_s cn56xxp1;
1659 struct cvmx_mio_uartx_iir_s cn58xx; 2546 struct cvmx_mio_uartx_iir_s cn58xx;
1660 struct cvmx_mio_uartx_iir_s cn58xxp1; 2547 struct cvmx_mio_uartx_iir_s cn58xxp1;
2548 struct cvmx_mio_uartx_iir_s cn61xx;
1661 struct cvmx_mio_uartx_iir_s cn63xx; 2549 struct cvmx_mio_uartx_iir_s cn63xx;
1662 struct cvmx_mio_uartx_iir_s cn63xxp1; 2550 struct cvmx_mio_uartx_iir_s cn63xxp1;
2551 struct cvmx_mio_uartx_iir_s cn66xx;
2552 struct cvmx_mio_uartx_iir_s cn68xx;
2553 struct cvmx_mio_uartx_iir_s cn68xxp1;
1663}; 2554};
1664 2555
1665union cvmx_mio_uartx_lcr { 2556union cvmx_mio_uartx_lcr {
@@ -1685,8 +2576,12 @@ union cvmx_mio_uartx_lcr {
1685 struct cvmx_mio_uartx_lcr_s cn56xxp1; 2576 struct cvmx_mio_uartx_lcr_s cn56xxp1;
1686 struct cvmx_mio_uartx_lcr_s cn58xx; 2577 struct cvmx_mio_uartx_lcr_s cn58xx;
1687 struct cvmx_mio_uartx_lcr_s cn58xxp1; 2578 struct cvmx_mio_uartx_lcr_s cn58xxp1;
2579 struct cvmx_mio_uartx_lcr_s cn61xx;
1688 struct cvmx_mio_uartx_lcr_s cn63xx; 2580 struct cvmx_mio_uartx_lcr_s cn63xx;
1689 struct cvmx_mio_uartx_lcr_s cn63xxp1; 2581 struct cvmx_mio_uartx_lcr_s cn63xxp1;
2582 struct cvmx_mio_uartx_lcr_s cn66xx;
2583 struct cvmx_mio_uartx_lcr_s cn68xx;
2584 struct cvmx_mio_uartx_lcr_s cn68xxp1;
1690}; 2585};
1691 2586
1692union cvmx_mio_uartx_lsr { 2587union cvmx_mio_uartx_lsr {
@@ -1713,8 +2608,12 @@ union cvmx_mio_uartx_lsr {
1713 struct cvmx_mio_uartx_lsr_s cn56xxp1; 2608 struct cvmx_mio_uartx_lsr_s cn56xxp1;
1714 struct cvmx_mio_uartx_lsr_s cn58xx; 2609 struct cvmx_mio_uartx_lsr_s cn58xx;
1715 struct cvmx_mio_uartx_lsr_s cn58xxp1; 2610 struct cvmx_mio_uartx_lsr_s cn58xxp1;
2611 struct cvmx_mio_uartx_lsr_s cn61xx;
1716 struct cvmx_mio_uartx_lsr_s cn63xx; 2612 struct cvmx_mio_uartx_lsr_s cn63xx;
1717 struct cvmx_mio_uartx_lsr_s cn63xxp1; 2613 struct cvmx_mio_uartx_lsr_s cn63xxp1;
2614 struct cvmx_mio_uartx_lsr_s cn66xx;
2615 struct cvmx_mio_uartx_lsr_s cn68xx;
2616 struct cvmx_mio_uartx_lsr_s cn68xxp1;
1718}; 2617};
1719 2618
1720union cvmx_mio_uartx_mcr { 2619union cvmx_mio_uartx_mcr {
@@ -1739,8 +2638,12 @@ union cvmx_mio_uartx_mcr {
1739 struct cvmx_mio_uartx_mcr_s cn56xxp1; 2638 struct cvmx_mio_uartx_mcr_s cn56xxp1;
1740 struct cvmx_mio_uartx_mcr_s cn58xx; 2639 struct cvmx_mio_uartx_mcr_s cn58xx;
1741 struct cvmx_mio_uartx_mcr_s cn58xxp1; 2640 struct cvmx_mio_uartx_mcr_s cn58xxp1;
2641 struct cvmx_mio_uartx_mcr_s cn61xx;
1742 struct cvmx_mio_uartx_mcr_s cn63xx; 2642 struct cvmx_mio_uartx_mcr_s cn63xx;
1743 struct cvmx_mio_uartx_mcr_s cn63xxp1; 2643 struct cvmx_mio_uartx_mcr_s cn63xxp1;
2644 struct cvmx_mio_uartx_mcr_s cn66xx;
2645 struct cvmx_mio_uartx_mcr_s cn68xx;
2646 struct cvmx_mio_uartx_mcr_s cn68xxp1;
1744}; 2647};
1745 2648
1746union cvmx_mio_uartx_msr { 2649union cvmx_mio_uartx_msr {
@@ -1767,8 +2670,12 @@ union cvmx_mio_uartx_msr {
1767 struct cvmx_mio_uartx_msr_s cn56xxp1; 2670 struct cvmx_mio_uartx_msr_s cn56xxp1;
1768 struct cvmx_mio_uartx_msr_s cn58xx; 2671 struct cvmx_mio_uartx_msr_s cn58xx;
1769 struct cvmx_mio_uartx_msr_s cn58xxp1; 2672 struct cvmx_mio_uartx_msr_s cn58xxp1;
2673 struct cvmx_mio_uartx_msr_s cn61xx;
1770 struct cvmx_mio_uartx_msr_s cn63xx; 2674 struct cvmx_mio_uartx_msr_s cn63xx;
1771 struct cvmx_mio_uartx_msr_s cn63xxp1; 2675 struct cvmx_mio_uartx_msr_s cn63xxp1;
2676 struct cvmx_mio_uartx_msr_s cn66xx;
2677 struct cvmx_mio_uartx_msr_s cn68xx;
2678 struct cvmx_mio_uartx_msr_s cn68xxp1;
1772}; 2679};
1773 2680
1774union cvmx_mio_uartx_rbr { 2681union cvmx_mio_uartx_rbr {
@@ -1788,8 +2695,12 @@ union cvmx_mio_uartx_rbr {
1788 struct cvmx_mio_uartx_rbr_s cn56xxp1; 2695 struct cvmx_mio_uartx_rbr_s cn56xxp1;
1789 struct cvmx_mio_uartx_rbr_s cn58xx; 2696 struct cvmx_mio_uartx_rbr_s cn58xx;
1790 struct cvmx_mio_uartx_rbr_s cn58xxp1; 2697 struct cvmx_mio_uartx_rbr_s cn58xxp1;
2698 struct cvmx_mio_uartx_rbr_s cn61xx;
1791 struct cvmx_mio_uartx_rbr_s cn63xx; 2699 struct cvmx_mio_uartx_rbr_s cn63xx;
1792 struct cvmx_mio_uartx_rbr_s cn63xxp1; 2700 struct cvmx_mio_uartx_rbr_s cn63xxp1;
2701 struct cvmx_mio_uartx_rbr_s cn66xx;
2702 struct cvmx_mio_uartx_rbr_s cn68xx;
2703 struct cvmx_mio_uartx_rbr_s cn68xxp1;
1793}; 2704};
1794 2705
1795union cvmx_mio_uartx_rfl { 2706union cvmx_mio_uartx_rfl {
@@ -1809,8 +2720,12 @@ union cvmx_mio_uartx_rfl {
1809 struct cvmx_mio_uartx_rfl_s cn56xxp1; 2720 struct cvmx_mio_uartx_rfl_s cn56xxp1;
1810 struct cvmx_mio_uartx_rfl_s cn58xx; 2721 struct cvmx_mio_uartx_rfl_s cn58xx;
1811 struct cvmx_mio_uartx_rfl_s cn58xxp1; 2722 struct cvmx_mio_uartx_rfl_s cn58xxp1;
2723 struct cvmx_mio_uartx_rfl_s cn61xx;
1812 struct cvmx_mio_uartx_rfl_s cn63xx; 2724 struct cvmx_mio_uartx_rfl_s cn63xx;
1813 struct cvmx_mio_uartx_rfl_s cn63xxp1; 2725 struct cvmx_mio_uartx_rfl_s cn63xxp1;
2726 struct cvmx_mio_uartx_rfl_s cn66xx;
2727 struct cvmx_mio_uartx_rfl_s cn68xx;
2728 struct cvmx_mio_uartx_rfl_s cn68xxp1;
1814}; 2729};
1815 2730
1816union cvmx_mio_uartx_rfw { 2731union cvmx_mio_uartx_rfw {
@@ -1832,8 +2747,12 @@ union cvmx_mio_uartx_rfw {
1832 struct cvmx_mio_uartx_rfw_s cn56xxp1; 2747 struct cvmx_mio_uartx_rfw_s cn56xxp1;
1833 struct cvmx_mio_uartx_rfw_s cn58xx; 2748 struct cvmx_mio_uartx_rfw_s cn58xx;
1834 struct cvmx_mio_uartx_rfw_s cn58xxp1; 2749 struct cvmx_mio_uartx_rfw_s cn58xxp1;
2750 struct cvmx_mio_uartx_rfw_s cn61xx;
1835 struct cvmx_mio_uartx_rfw_s cn63xx; 2751 struct cvmx_mio_uartx_rfw_s cn63xx;
1836 struct cvmx_mio_uartx_rfw_s cn63xxp1; 2752 struct cvmx_mio_uartx_rfw_s cn63xxp1;
2753 struct cvmx_mio_uartx_rfw_s cn66xx;
2754 struct cvmx_mio_uartx_rfw_s cn68xx;
2755 struct cvmx_mio_uartx_rfw_s cn68xxp1;
1837}; 2756};
1838 2757
1839union cvmx_mio_uartx_sbcr { 2758union cvmx_mio_uartx_sbcr {
@@ -1853,8 +2772,12 @@ union cvmx_mio_uartx_sbcr {
1853 struct cvmx_mio_uartx_sbcr_s cn56xxp1; 2772 struct cvmx_mio_uartx_sbcr_s cn56xxp1;
1854 struct cvmx_mio_uartx_sbcr_s cn58xx; 2773 struct cvmx_mio_uartx_sbcr_s cn58xx;
1855 struct cvmx_mio_uartx_sbcr_s cn58xxp1; 2774 struct cvmx_mio_uartx_sbcr_s cn58xxp1;
2775 struct cvmx_mio_uartx_sbcr_s cn61xx;
1856 struct cvmx_mio_uartx_sbcr_s cn63xx; 2776 struct cvmx_mio_uartx_sbcr_s cn63xx;
1857 struct cvmx_mio_uartx_sbcr_s cn63xxp1; 2777 struct cvmx_mio_uartx_sbcr_s cn63xxp1;
2778 struct cvmx_mio_uartx_sbcr_s cn66xx;
2779 struct cvmx_mio_uartx_sbcr_s cn68xx;
2780 struct cvmx_mio_uartx_sbcr_s cn68xxp1;
1858}; 2781};
1859 2782
1860union cvmx_mio_uartx_scr { 2783union cvmx_mio_uartx_scr {
@@ -1874,8 +2797,12 @@ union cvmx_mio_uartx_scr {
1874 struct cvmx_mio_uartx_scr_s cn56xxp1; 2797 struct cvmx_mio_uartx_scr_s cn56xxp1;
1875 struct cvmx_mio_uartx_scr_s cn58xx; 2798 struct cvmx_mio_uartx_scr_s cn58xx;
1876 struct cvmx_mio_uartx_scr_s cn58xxp1; 2799 struct cvmx_mio_uartx_scr_s cn58xxp1;
2800 struct cvmx_mio_uartx_scr_s cn61xx;
1877 struct cvmx_mio_uartx_scr_s cn63xx; 2801 struct cvmx_mio_uartx_scr_s cn63xx;
1878 struct cvmx_mio_uartx_scr_s cn63xxp1; 2802 struct cvmx_mio_uartx_scr_s cn63xxp1;
2803 struct cvmx_mio_uartx_scr_s cn66xx;
2804 struct cvmx_mio_uartx_scr_s cn68xx;
2805 struct cvmx_mio_uartx_scr_s cn68xxp1;
1879}; 2806};
1880 2807
1881union cvmx_mio_uartx_sfe { 2808union cvmx_mio_uartx_sfe {
@@ -1895,8 +2822,12 @@ union cvmx_mio_uartx_sfe {
1895 struct cvmx_mio_uartx_sfe_s cn56xxp1; 2822 struct cvmx_mio_uartx_sfe_s cn56xxp1;
1896 struct cvmx_mio_uartx_sfe_s cn58xx; 2823 struct cvmx_mio_uartx_sfe_s cn58xx;
1897 struct cvmx_mio_uartx_sfe_s cn58xxp1; 2824 struct cvmx_mio_uartx_sfe_s cn58xxp1;
2825 struct cvmx_mio_uartx_sfe_s cn61xx;
1898 struct cvmx_mio_uartx_sfe_s cn63xx; 2826 struct cvmx_mio_uartx_sfe_s cn63xx;
1899 struct cvmx_mio_uartx_sfe_s cn63xxp1; 2827 struct cvmx_mio_uartx_sfe_s cn63xxp1;
2828 struct cvmx_mio_uartx_sfe_s cn66xx;
2829 struct cvmx_mio_uartx_sfe_s cn68xx;
2830 struct cvmx_mio_uartx_sfe_s cn68xxp1;
1900}; 2831};
1901 2832
1902union cvmx_mio_uartx_srr { 2833union cvmx_mio_uartx_srr {
@@ -1918,8 +2849,12 @@ union cvmx_mio_uartx_srr {
1918 struct cvmx_mio_uartx_srr_s cn56xxp1; 2849 struct cvmx_mio_uartx_srr_s cn56xxp1;
1919 struct cvmx_mio_uartx_srr_s cn58xx; 2850 struct cvmx_mio_uartx_srr_s cn58xx;
1920 struct cvmx_mio_uartx_srr_s cn58xxp1; 2851 struct cvmx_mio_uartx_srr_s cn58xxp1;
2852 struct cvmx_mio_uartx_srr_s cn61xx;
1921 struct cvmx_mio_uartx_srr_s cn63xx; 2853 struct cvmx_mio_uartx_srr_s cn63xx;
1922 struct cvmx_mio_uartx_srr_s cn63xxp1; 2854 struct cvmx_mio_uartx_srr_s cn63xxp1;
2855 struct cvmx_mio_uartx_srr_s cn66xx;
2856 struct cvmx_mio_uartx_srr_s cn68xx;
2857 struct cvmx_mio_uartx_srr_s cn68xxp1;
1923}; 2858};
1924 2859
1925union cvmx_mio_uartx_srt { 2860union cvmx_mio_uartx_srt {
@@ -1939,8 +2874,12 @@ union cvmx_mio_uartx_srt {
1939 struct cvmx_mio_uartx_srt_s cn56xxp1; 2874 struct cvmx_mio_uartx_srt_s cn56xxp1;
1940 struct cvmx_mio_uartx_srt_s cn58xx; 2875 struct cvmx_mio_uartx_srt_s cn58xx;
1941 struct cvmx_mio_uartx_srt_s cn58xxp1; 2876 struct cvmx_mio_uartx_srt_s cn58xxp1;
2877 struct cvmx_mio_uartx_srt_s cn61xx;
1942 struct cvmx_mio_uartx_srt_s cn63xx; 2878 struct cvmx_mio_uartx_srt_s cn63xx;
1943 struct cvmx_mio_uartx_srt_s cn63xxp1; 2879 struct cvmx_mio_uartx_srt_s cn63xxp1;
2880 struct cvmx_mio_uartx_srt_s cn66xx;
2881 struct cvmx_mio_uartx_srt_s cn68xx;
2882 struct cvmx_mio_uartx_srt_s cn68xxp1;
1944}; 2883};
1945 2884
1946union cvmx_mio_uartx_srts { 2885union cvmx_mio_uartx_srts {
@@ -1960,8 +2899,12 @@ union cvmx_mio_uartx_srts {
1960 struct cvmx_mio_uartx_srts_s cn56xxp1; 2899 struct cvmx_mio_uartx_srts_s cn56xxp1;
1961 struct cvmx_mio_uartx_srts_s cn58xx; 2900 struct cvmx_mio_uartx_srts_s cn58xx;
1962 struct cvmx_mio_uartx_srts_s cn58xxp1; 2901 struct cvmx_mio_uartx_srts_s cn58xxp1;
2902 struct cvmx_mio_uartx_srts_s cn61xx;
1963 struct cvmx_mio_uartx_srts_s cn63xx; 2903 struct cvmx_mio_uartx_srts_s cn63xx;
1964 struct cvmx_mio_uartx_srts_s cn63xxp1; 2904 struct cvmx_mio_uartx_srts_s cn63xxp1;
2905 struct cvmx_mio_uartx_srts_s cn66xx;
2906 struct cvmx_mio_uartx_srts_s cn68xx;
2907 struct cvmx_mio_uartx_srts_s cn68xxp1;
1965}; 2908};
1966 2909
1967union cvmx_mio_uartx_stt { 2910union cvmx_mio_uartx_stt {
@@ -1981,8 +2924,12 @@ union cvmx_mio_uartx_stt {
1981 struct cvmx_mio_uartx_stt_s cn56xxp1; 2924 struct cvmx_mio_uartx_stt_s cn56xxp1;
1982 struct cvmx_mio_uartx_stt_s cn58xx; 2925 struct cvmx_mio_uartx_stt_s cn58xx;
1983 struct cvmx_mio_uartx_stt_s cn58xxp1; 2926 struct cvmx_mio_uartx_stt_s cn58xxp1;
2927 struct cvmx_mio_uartx_stt_s cn61xx;
1984 struct cvmx_mio_uartx_stt_s cn63xx; 2928 struct cvmx_mio_uartx_stt_s cn63xx;
1985 struct cvmx_mio_uartx_stt_s cn63xxp1; 2929 struct cvmx_mio_uartx_stt_s cn63xxp1;
2930 struct cvmx_mio_uartx_stt_s cn66xx;
2931 struct cvmx_mio_uartx_stt_s cn68xx;
2932 struct cvmx_mio_uartx_stt_s cn68xxp1;
1986}; 2933};
1987 2934
1988union cvmx_mio_uartx_tfl { 2935union cvmx_mio_uartx_tfl {
@@ -2002,8 +2949,12 @@ union cvmx_mio_uartx_tfl {
2002 struct cvmx_mio_uartx_tfl_s cn56xxp1; 2949 struct cvmx_mio_uartx_tfl_s cn56xxp1;
2003 struct cvmx_mio_uartx_tfl_s cn58xx; 2950 struct cvmx_mio_uartx_tfl_s cn58xx;
2004 struct cvmx_mio_uartx_tfl_s cn58xxp1; 2951 struct cvmx_mio_uartx_tfl_s cn58xxp1;
2952 struct cvmx_mio_uartx_tfl_s cn61xx;
2005 struct cvmx_mio_uartx_tfl_s cn63xx; 2953 struct cvmx_mio_uartx_tfl_s cn63xx;
2006 struct cvmx_mio_uartx_tfl_s cn63xxp1; 2954 struct cvmx_mio_uartx_tfl_s cn63xxp1;
2955 struct cvmx_mio_uartx_tfl_s cn66xx;
2956 struct cvmx_mio_uartx_tfl_s cn68xx;
2957 struct cvmx_mio_uartx_tfl_s cn68xxp1;
2007}; 2958};
2008 2959
2009union cvmx_mio_uartx_tfr { 2960union cvmx_mio_uartx_tfr {
@@ -2023,8 +2974,12 @@ union cvmx_mio_uartx_tfr {
2023 struct cvmx_mio_uartx_tfr_s cn56xxp1; 2974 struct cvmx_mio_uartx_tfr_s cn56xxp1;
2024 struct cvmx_mio_uartx_tfr_s cn58xx; 2975 struct cvmx_mio_uartx_tfr_s cn58xx;
2025 struct cvmx_mio_uartx_tfr_s cn58xxp1; 2976 struct cvmx_mio_uartx_tfr_s cn58xxp1;
2977 struct cvmx_mio_uartx_tfr_s cn61xx;
2026 struct cvmx_mio_uartx_tfr_s cn63xx; 2978 struct cvmx_mio_uartx_tfr_s cn63xx;
2027 struct cvmx_mio_uartx_tfr_s cn63xxp1; 2979 struct cvmx_mio_uartx_tfr_s cn63xxp1;
2980 struct cvmx_mio_uartx_tfr_s cn66xx;
2981 struct cvmx_mio_uartx_tfr_s cn68xx;
2982 struct cvmx_mio_uartx_tfr_s cn68xxp1;
2028}; 2983};
2029 2984
2030union cvmx_mio_uartx_thr { 2985union cvmx_mio_uartx_thr {
@@ -2044,8 +2999,12 @@ union cvmx_mio_uartx_thr {
2044 struct cvmx_mio_uartx_thr_s cn56xxp1; 2999 struct cvmx_mio_uartx_thr_s cn56xxp1;
2045 struct cvmx_mio_uartx_thr_s cn58xx; 3000 struct cvmx_mio_uartx_thr_s cn58xx;
2046 struct cvmx_mio_uartx_thr_s cn58xxp1; 3001 struct cvmx_mio_uartx_thr_s cn58xxp1;
3002 struct cvmx_mio_uartx_thr_s cn61xx;
2047 struct cvmx_mio_uartx_thr_s cn63xx; 3003 struct cvmx_mio_uartx_thr_s cn63xx;
2048 struct cvmx_mio_uartx_thr_s cn63xxp1; 3004 struct cvmx_mio_uartx_thr_s cn63xxp1;
3005 struct cvmx_mio_uartx_thr_s cn66xx;
3006 struct cvmx_mio_uartx_thr_s cn68xx;
3007 struct cvmx_mio_uartx_thr_s cn68xxp1;
2049}; 3008};
2050 3009
2051union cvmx_mio_uartx_usr { 3010union cvmx_mio_uartx_usr {
@@ -2069,8 +3028,12 @@ union cvmx_mio_uartx_usr {
2069 struct cvmx_mio_uartx_usr_s cn56xxp1; 3028 struct cvmx_mio_uartx_usr_s cn56xxp1;
2070 struct cvmx_mio_uartx_usr_s cn58xx; 3029 struct cvmx_mio_uartx_usr_s cn58xx;
2071 struct cvmx_mio_uartx_usr_s cn58xxp1; 3030 struct cvmx_mio_uartx_usr_s cn58xxp1;
3031 struct cvmx_mio_uartx_usr_s cn61xx;
2072 struct cvmx_mio_uartx_usr_s cn63xx; 3032 struct cvmx_mio_uartx_usr_s cn63xx;
2073 struct cvmx_mio_uartx_usr_s cn63xxp1; 3033 struct cvmx_mio_uartx_usr_s cn63xxp1;
3034 struct cvmx_mio_uartx_usr_s cn66xx;
3035 struct cvmx_mio_uartx_usr_s cn68xx;
3036 struct cvmx_mio_uartx_usr_s cn68xxp1;
2074}; 3037};
2075 3038
2076union cvmx_mio_uart2_dlh { 3039union cvmx_mio_uart2_dlh {
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 9899a9d2ba72..a3075f733ca5 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2011 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -65,7 +65,7 @@
65#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull) 65#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
66#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull) 66#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
67#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull) 67#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
68#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12) 68#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
69#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull) 69#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
70#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull) 70#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
71#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull) 71#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index f8cb88902efb..7b1dc8b74e5b 100644
--- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2011 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -116,8 +116,12 @@ union cvmx_pciercx_cfg000 {
116 struct cvmx_pciercx_cfg000_s cn52xxp1; 116 struct cvmx_pciercx_cfg000_s cn52xxp1;
117 struct cvmx_pciercx_cfg000_s cn56xx; 117 struct cvmx_pciercx_cfg000_s cn56xx;
118 struct cvmx_pciercx_cfg000_s cn56xxp1; 118 struct cvmx_pciercx_cfg000_s cn56xxp1;
119 struct cvmx_pciercx_cfg000_s cn61xx;
119 struct cvmx_pciercx_cfg000_s cn63xx; 120 struct cvmx_pciercx_cfg000_s cn63xx;
120 struct cvmx_pciercx_cfg000_s cn63xxp1; 121 struct cvmx_pciercx_cfg000_s cn63xxp1;
122 struct cvmx_pciercx_cfg000_s cn66xx;
123 struct cvmx_pciercx_cfg000_s cn68xx;
124 struct cvmx_pciercx_cfg000_s cn68xxp1;
121}; 125};
122 126
123union cvmx_pciercx_cfg001 { 127union cvmx_pciercx_cfg001 {
@@ -152,8 +156,12 @@ union cvmx_pciercx_cfg001 {
152 struct cvmx_pciercx_cfg001_s cn52xxp1; 156 struct cvmx_pciercx_cfg001_s cn52xxp1;
153 struct cvmx_pciercx_cfg001_s cn56xx; 157 struct cvmx_pciercx_cfg001_s cn56xx;
154 struct cvmx_pciercx_cfg001_s cn56xxp1; 158 struct cvmx_pciercx_cfg001_s cn56xxp1;
159 struct cvmx_pciercx_cfg001_s cn61xx;
155 struct cvmx_pciercx_cfg001_s cn63xx; 160 struct cvmx_pciercx_cfg001_s cn63xx;
156 struct cvmx_pciercx_cfg001_s cn63xxp1; 161 struct cvmx_pciercx_cfg001_s cn63xxp1;
162 struct cvmx_pciercx_cfg001_s cn66xx;
163 struct cvmx_pciercx_cfg001_s cn68xx;
164 struct cvmx_pciercx_cfg001_s cn68xxp1;
157}; 165};
158 166
159union cvmx_pciercx_cfg002 { 167union cvmx_pciercx_cfg002 {
@@ -168,8 +176,12 @@ union cvmx_pciercx_cfg002 {
168 struct cvmx_pciercx_cfg002_s cn52xxp1; 176 struct cvmx_pciercx_cfg002_s cn52xxp1;
169 struct cvmx_pciercx_cfg002_s cn56xx; 177 struct cvmx_pciercx_cfg002_s cn56xx;
170 struct cvmx_pciercx_cfg002_s cn56xxp1; 178 struct cvmx_pciercx_cfg002_s cn56xxp1;
179 struct cvmx_pciercx_cfg002_s cn61xx;
171 struct cvmx_pciercx_cfg002_s cn63xx; 180 struct cvmx_pciercx_cfg002_s cn63xx;
172 struct cvmx_pciercx_cfg002_s cn63xxp1; 181 struct cvmx_pciercx_cfg002_s cn63xxp1;
182 struct cvmx_pciercx_cfg002_s cn66xx;
183 struct cvmx_pciercx_cfg002_s cn68xx;
184 struct cvmx_pciercx_cfg002_s cn68xxp1;
173}; 185};
174 186
175union cvmx_pciercx_cfg003 { 187union cvmx_pciercx_cfg003 {
@@ -185,8 +197,12 @@ union cvmx_pciercx_cfg003 {
185 struct cvmx_pciercx_cfg003_s cn52xxp1; 197 struct cvmx_pciercx_cfg003_s cn52xxp1;
186 struct cvmx_pciercx_cfg003_s cn56xx; 198 struct cvmx_pciercx_cfg003_s cn56xx;
187 struct cvmx_pciercx_cfg003_s cn56xxp1; 199 struct cvmx_pciercx_cfg003_s cn56xxp1;
200 struct cvmx_pciercx_cfg003_s cn61xx;
188 struct cvmx_pciercx_cfg003_s cn63xx; 201 struct cvmx_pciercx_cfg003_s cn63xx;
189 struct cvmx_pciercx_cfg003_s cn63xxp1; 202 struct cvmx_pciercx_cfg003_s cn63xxp1;
203 struct cvmx_pciercx_cfg003_s cn66xx;
204 struct cvmx_pciercx_cfg003_s cn68xx;
205 struct cvmx_pciercx_cfg003_s cn68xxp1;
190}; 206};
191 207
192union cvmx_pciercx_cfg004 { 208union cvmx_pciercx_cfg004 {
@@ -198,8 +214,12 @@ union cvmx_pciercx_cfg004 {
198 struct cvmx_pciercx_cfg004_s cn52xxp1; 214 struct cvmx_pciercx_cfg004_s cn52xxp1;
199 struct cvmx_pciercx_cfg004_s cn56xx; 215 struct cvmx_pciercx_cfg004_s cn56xx;
200 struct cvmx_pciercx_cfg004_s cn56xxp1; 216 struct cvmx_pciercx_cfg004_s cn56xxp1;
217 struct cvmx_pciercx_cfg004_s cn61xx;
201 struct cvmx_pciercx_cfg004_s cn63xx; 218 struct cvmx_pciercx_cfg004_s cn63xx;
202 struct cvmx_pciercx_cfg004_s cn63xxp1; 219 struct cvmx_pciercx_cfg004_s cn63xxp1;
220 struct cvmx_pciercx_cfg004_s cn66xx;
221 struct cvmx_pciercx_cfg004_s cn68xx;
222 struct cvmx_pciercx_cfg004_s cn68xxp1;
203}; 223};
204 224
205union cvmx_pciercx_cfg005 { 225union cvmx_pciercx_cfg005 {
@@ -211,8 +231,12 @@ union cvmx_pciercx_cfg005 {
211 struct cvmx_pciercx_cfg005_s cn52xxp1; 231 struct cvmx_pciercx_cfg005_s cn52xxp1;
212 struct cvmx_pciercx_cfg005_s cn56xx; 232 struct cvmx_pciercx_cfg005_s cn56xx;
213 struct cvmx_pciercx_cfg005_s cn56xxp1; 233 struct cvmx_pciercx_cfg005_s cn56xxp1;
234 struct cvmx_pciercx_cfg005_s cn61xx;
214 struct cvmx_pciercx_cfg005_s cn63xx; 235 struct cvmx_pciercx_cfg005_s cn63xx;
215 struct cvmx_pciercx_cfg005_s cn63xxp1; 236 struct cvmx_pciercx_cfg005_s cn63xxp1;
237 struct cvmx_pciercx_cfg005_s cn66xx;
238 struct cvmx_pciercx_cfg005_s cn68xx;
239 struct cvmx_pciercx_cfg005_s cn68xxp1;
216}; 240};
217 241
218union cvmx_pciercx_cfg006 { 242union cvmx_pciercx_cfg006 {
@@ -227,8 +251,12 @@ union cvmx_pciercx_cfg006 {
227 struct cvmx_pciercx_cfg006_s cn52xxp1; 251 struct cvmx_pciercx_cfg006_s cn52xxp1;
228 struct cvmx_pciercx_cfg006_s cn56xx; 252 struct cvmx_pciercx_cfg006_s cn56xx;
229 struct cvmx_pciercx_cfg006_s cn56xxp1; 253 struct cvmx_pciercx_cfg006_s cn56xxp1;
254 struct cvmx_pciercx_cfg006_s cn61xx;
230 struct cvmx_pciercx_cfg006_s cn63xx; 255 struct cvmx_pciercx_cfg006_s cn63xx;
231 struct cvmx_pciercx_cfg006_s cn63xxp1; 256 struct cvmx_pciercx_cfg006_s cn63xxp1;
257 struct cvmx_pciercx_cfg006_s cn66xx;
258 struct cvmx_pciercx_cfg006_s cn68xx;
259 struct cvmx_pciercx_cfg006_s cn68xxp1;
232}; 260};
233 261
234union cvmx_pciercx_cfg007 { 262union cvmx_pciercx_cfg007 {
@@ -256,8 +284,12 @@ union cvmx_pciercx_cfg007 {
256 struct cvmx_pciercx_cfg007_s cn52xxp1; 284 struct cvmx_pciercx_cfg007_s cn52xxp1;
257 struct cvmx_pciercx_cfg007_s cn56xx; 285 struct cvmx_pciercx_cfg007_s cn56xx;
258 struct cvmx_pciercx_cfg007_s cn56xxp1; 286 struct cvmx_pciercx_cfg007_s cn56xxp1;
287 struct cvmx_pciercx_cfg007_s cn61xx;
259 struct cvmx_pciercx_cfg007_s cn63xx; 288 struct cvmx_pciercx_cfg007_s cn63xx;
260 struct cvmx_pciercx_cfg007_s cn63xxp1; 289 struct cvmx_pciercx_cfg007_s cn63xxp1;
290 struct cvmx_pciercx_cfg007_s cn66xx;
291 struct cvmx_pciercx_cfg007_s cn68xx;
292 struct cvmx_pciercx_cfg007_s cn68xxp1;
261}; 293};
262 294
263union cvmx_pciercx_cfg008 { 295union cvmx_pciercx_cfg008 {
@@ -272,8 +304,12 @@ union cvmx_pciercx_cfg008 {
272 struct cvmx_pciercx_cfg008_s cn52xxp1; 304 struct cvmx_pciercx_cfg008_s cn52xxp1;
273 struct cvmx_pciercx_cfg008_s cn56xx; 305 struct cvmx_pciercx_cfg008_s cn56xx;
274 struct cvmx_pciercx_cfg008_s cn56xxp1; 306 struct cvmx_pciercx_cfg008_s cn56xxp1;
307 struct cvmx_pciercx_cfg008_s cn61xx;
275 struct cvmx_pciercx_cfg008_s cn63xx; 308 struct cvmx_pciercx_cfg008_s cn63xx;
276 struct cvmx_pciercx_cfg008_s cn63xxp1; 309 struct cvmx_pciercx_cfg008_s cn63xxp1;
310 struct cvmx_pciercx_cfg008_s cn66xx;
311 struct cvmx_pciercx_cfg008_s cn68xx;
312 struct cvmx_pciercx_cfg008_s cn68xxp1;
277}; 313};
278 314
279union cvmx_pciercx_cfg009 { 315union cvmx_pciercx_cfg009 {
@@ -290,8 +326,12 @@ union cvmx_pciercx_cfg009 {
290 struct cvmx_pciercx_cfg009_s cn52xxp1; 326 struct cvmx_pciercx_cfg009_s cn52xxp1;
291 struct cvmx_pciercx_cfg009_s cn56xx; 327 struct cvmx_pciercx_cfg009_s cn56xx;
292 struct cvmx_pciercx_cfg009_s cn56xxp1; 328 struct cvmx_pciercx_cfg009_s cn56xxp1;
329 struct cvmx_pciercx_cfg009_s cn61xx;
293 struct cvmx_pciercx_cfg009_s cn63xx; 330 struct cvmx_pciercx_cfg009_s cn63xx;
294 struct cvmx_pciercx_cfg009_s cn63xxp1; 331 struct cvmx_pciercx_cfg009_s cn63xxp1;
332 struct cvmx_pciercx_cfg009_s cn66xx;
333 struct cvmx_pciercx_cfg009_s cn68xx;
334 struct cvmx_pciercx_cfg009_s cn68xxp1;
295}; 335};
296 336
297union cvmx_pciercx_cfg010 { 337union cvmx_pciercx_cfg010 {
@@ -303,8 +343,12 @@ union cvmx_pciercx_cfg010 {
303 struct cvmx_pciercx_cfg010_s cn52xxp1; 343 struct cvmx_pciercx_cfg010_s cn52xxp1;
304 struct cvmx_pciercx_cfg010_s cn56xx; 344 struct cvmx_pciercx_cfg010_s cn56xx;
305 struct cvmx_pciercx_cfg010_s cn56xxp1; 345 struct cvmx_pciercx_cfg010_s cn56xxp1;
346 struct cvmx_pciercx_cfg010_s cn61xx;
306 struct cvmx_pciercx_cfg010_s cn63xx; 347 struct cvmx_pciercx_cfg010_s cn63xx;
307 struct cvmx_pciercx_cfg010_s cn63xxp1; 348 struct cvmx_pciercx_cfg010_s cn63xxp1;
349 struct cvmx_pciercx_cfg010_s cn66xx;
350 struct cvmx_pciercx_cfg010_s cn68xx;
351 struct cvmx_pciercx_cfg010_s cn68xxp1;
308}; 352};
309 353
310union cvmx_pciercx_cfg011 { 354union cvmx_pciercx_cfg011 {
@@ -316,8 +360,12 @@ union cvmx_pciercx_cfg011 {
316 struct cvmx_pciercx_cfg011_s cn52xxp1; 360 struct cvmx_pciercx_cfg011_s cn52xxp1;
317 struct cvmx_pciercx_cfg011_s cn56xx; 361 struct cvmx_pciercx_cfg011_s cn56xx;
318 struct cvmx_pciercx_cfg011_s cn56xxp1; 362 struct cvmx_pciercx_cfg011_s cn56xxp1;
363 struct cvmx_pciercx_cfg011_s cn61xx;
319 struct cvmx_pciercx_cfg011_s cn63xx; 364 struct cvmx_pciercx_cfg011_s cn63xx;
320 struct cvmx_pciercx_cfg011_s cn63xxp1; 365 struct cvmx_pciercx_cfg011_s cn63xxp1;
366 struct cvmx_pciercx_cfg011_s cn66xx;
367 struct cvmx_pciercx_cfg011_s cn68xx;
368 struct cvmx_pciercx_cfg011_s cn68xxp1;
321}; 369};
322 370
323union cvmx_pciercx_cfg012 { 371union cvmx_pciercx_cfg012 {
@@ -330,8 +378,12 @@ union cvmx_pciercx_cfg012 {
330 struct cvmx_pciercx_cfg012_s cn52xxp1; 378 struct cvmx_pciercx_cfg012_s cn52xxp1;
331 struct cvmx_pciercx_cfg012_s cn56xx; 379 struct cvmx_pciercx_cfg012_s cn56xx;
332 struct cvmx_pciercx_cfg012_s cn56xxp1; 380 struct cvmx_pciercx_cfg012_s cn56xxp1;
381 struct cvmx_pciercx_cfg012_s cn61xx;
333 struct cvmx_pciercx_cfg012_s cn63xx; 382 struct cvmx_pciercx_cfg012_s cn63xx;
334 struct cvmx_pciercx_cfg012_s cn63xxp1; 383 struct cvmx_pciercx_cfg012_s cn63xxp1;
384 struct cvmx_pciercx_cfg012_s cn66xx;
385 struct cvmx_pciercx_cfg012_s cn68xx;
386 struct cvmx_pciercx_cfg012_s cn68xxp1;
335}; 387};
336 388
337union cvmx_pciercx_cfg013 { 389union cvmx_pciercx_cfg013 {
@@ -344,8 +396,12 @@ union cvmx_pciercx_cfg013 {
344 struct cvmx_pciercx_cfg013_s cn52xxp1; 396 struct cvmx_pciercx_cfg013_s cn52xxp1;
345 struct cvmx_pciercx_cfg013_s cn56xx; 397 struct cvmx_pciercx_cfg013_s cn56xx;
346 struct cvmx_pciercx_cfg013_s cn56xxp1; 398 struct cvmx_pciercx_cfg013_s cn56xxp1;
399 struct cvmx_pciercx_cfg013_s cn61xx;
347 struct cvmx_pciercx_cfg013_s cn63xx; 400 struct cvmx_pciercx_cfg013_s cn63xx;
348 struct cvmx_pciercx_cfg013_s cn63xxp1; 401 struct cvmx_pciercx_cfg013_s cn63xxp1;
402 struct cvmx_pciercx_cfg013_s cn66xx;
403 struct cvmx_pciercx_cfg013_s cn68xx;
404 struct cvmx_pciercx_cfg013_s cn68xxp1;
349}; 405};
350 406
351union cvmx_pciercx_cfg014 { 407union cvmx_pciercx_cfg014 {
@@ -357,8 +413,12 @@ union cvmx_pciercx_cfg014 {
357 struct cvmx_pciercx_cfg014_s cn52xxp1; 413 struct cvmx_pciercx_cfg014_s cn52xxp1;
358 struct cvmx_pciercx_cfg014_s cn56xx; 414 struct cvmx_pciercx_cfg014_s cn56xx;
359 struct cvmx_pciercx_cfg014_s cn56xxp1; 415 struct cvmx_pciercx_cfg014_s cn56xxp1;
416 struct cvmx_pciercx_cfg014_s cn61xx;
360 struct cvmx_pciercx_cfg014_s cn63xx; 417 struct cvmx_pciercx_cfg014_s cn63xx;
361 struct cvmx_pciercx_cfg014_s cn63xxp1; 418 struct cvmx_pciercx_cfg014_s cn63xxp1;
419 struct cvmx_pciercx_cfg014_s cn66xx;
420 struct cvmx_pciercx_cfg014_s cn68xx;
421 struct cvmx_pciercx_cfg014_s cn68xxp1;
362}; 422};
363 423
364union cvmx_pciercx_cfg015 { 424union cvmx_pciercx_cfg015 {
@@ -384,8 +444,12 @@ union cvmx_pciercx_cfg015 {
384 struct cvmx_pciercx_cfg015_s cn52xxp1; 444 struct cvmx_pciercx_cfg015_s cn52xxp1;
385 struct cvmx_pciercx_cfg015_s cn56xx; 445 struct cvmx_pciercx_cfg015_s cn56xx;
386 struct cvmx_pciercx_cfg015_s cn56xxp1; 446 struct cvmx_pciercx_cfg015_s cn56xxp1;
447 struct cvmx_pciercx_cfg015_s cn61xx;
387 struct cvmx_pciercx_cfg015_s cn63xx; 448 struct cvmx_pciercx_cfg015_s cn63xx;
388 struct cvmx_pciercx_cfg015_s cn63xxp1; 449 struct cvmx_pciercx_cfg015_s cn63xxp1;
450 struct cvmx_pciercx_cfg015_s cn66xx;
451 struct cvmx_pciercx_cfg015_s cn68xx;
452 struct cvmx_pciercx_cfg015_s cn68xxp1;
389}; 453};
390 454
391union cvmx_pciercx_cfg016 { 455union cvmx_pciercx_cfg016 {
@@ -406,8 +470,12 @@ union cvmx_pciercx_cfg016 {
406 struct cvmx_pciercx_cfg016_s cn52xxp1; 470 struct cvmx_pciercx_cfg016_s cn52xxp1;
407 struct cvmx_pciercx_cfg016_s cn56xx; 471 struct cvmx_pciercx_cfg016_s cn56xx;
408 struct cvmx_pciercx_cfg016_s cn56xxp1; 472 struct cvmx_pciercx_cfg016_s cn56xxp1;
473 struct cvmx_pciercx_cfg016_s cn61xx;
409 struct cvmx_pciercx_cfg016_s cn63xx; 474 struct cvmx_pciercx_cfg016_s cn63xx;
410 struct cvmx_pciercx_cfg016_s cn63xxp1; 475 struct cvmx_pciercx_cfg016_s cn63xxp1;
476 struct cvmx_pciercx_cfg016_s cn66xx;
477 struct cvmx_pciercx_cfg016_s cn68xx;
478 struct cvmx_pciercx_cfg016_s cn68xxp1;
411}; 479};
412 480
413union cvmx_pciercx_cfg017 { 481union cvmx_pciercx_cfg017 {
@@ -430,14 +498,19 @@ union cvmx_pciercx_cfg017 {
430 struct cvmx_pciercx_cfg017_s cn52xxp1; 498 struct cvmx_pciercx_cfg017_s cn52xxp1;
431 struct cvmx_pciercx_cfg017_s cn56xx; 499 struct cvmx_pciercx_cfg017_s cn56xx;
432 struct cvmx_pciercx_cfg017_s cn56xxp1; 500 struct cvmx_pciercx_cfg017_s cn56xxp1;
501 struct cvmx_pciercx_cfg017_s cn61xx;
433 struct cvmx_pciercx_cfg017_s cn63xx; 502 struct cvmx_pciercx_cfg017_s cn63xx;
434 struct cvmx_pciercx_cfg017_s cn63xxp1; 503 struct cvmx_pciercx_cfg017_s cn63xxp1;
504 struct cvmx_pciercx_cfg017_s cn66xx;
505 struct cvmx_pciercx_cfg017_s cn68xx;
506 struct cvmx_pciercx_cfg017_s cn68xxp1;
435}; 507};
436 508
437union cvmx_pciercx_cfg020 { 509union cvmx_pciercx_cfg020 {
438 uint32_t u32; 510 uint32_t u32;
439 struct cvmx_pciercx_cfg020_s { 511 struct cvmx_pciercx_cfg020_s {
440 uint32_t reserved_24_31:8; 512 uint32_t reserved_25_31:7;
513 uint32_t pvm:1;
441 uint32_t m64:1; 514 uint32_t m64:1;
442 uint32_t mme:3; 515 uint32_t mme:3;
443 uint32_t mmc:3; 516 uint32_t mmc:3;
@@ -445,12 +518,24 @@ union cvmx_pciercx_cfg020 {
445 uint32_t ncp:8; 518 uint32_t ncp:8;
446 uint32_t msicid:8; 519 uint32_t msicid:8;
447 } s; 520 } s;
448 struct cvmx_pciercx_cfg020_s cn52xx; 521 struct cvmx_pciercx_cfg020_cn52xx {
449 struct cvmx_pciercx_cfg020_s cn52xxp1; 522 uint32_t reserved_24_31:8;
450 struct cvmx_pciercx_cfg020_s cn56xx; 523 uint32_t m64:1;
451 struct cvmx_pciercx_cfg020_s cn56xxp1; 524 uint32_t mme:3;
452 struct cvmx_pciercx_cfg020_s cn63xx; 525 uint32_t mmc:3;
453 struct cvmx_pciercx_cfg020_s cn63xxp1; 526 uint32_t msien:1;
527 uint32_t ncp:8;
528 uint32_t msicid:8;
529 } cn52xx;
530 struct cvmx_pciercx_cfg020_cn52xx cn52xxp1;
531 struct cvmx_pciercx_cfg020_cn52xx cn56xx;
532 struct cvmx_pciercx_cfg020_cn52xx cn56xxp1;
533 struct cvmx_pciercx_cfg020_s cn61xx;
534 struct cvmx_pciercx_cfg020_cn52xx cn63xx;
535 struct cvmx_pciercx_cfg020_cn52xx cn63xxp1;
536 struct cvmx_pciercx_cfg020_cn52xx cn66xx;
537 struct cvmx_pciercx_cfg020_cn52xx cn68xx;
538 struct cvmx_pciercx_cfg020_cn52xx cn68xxp1;
454}; 539};
455 540
456union cvmx_pciercx_cfg021 { 541union cvmx_pciercx_cfg021 {
@@ -463,8 +548,12 @@ union cvmx_pciercx_cfg021 {
463 struct cvmx_pciercx_cfg021_s cn52xxp1; 548 struct cvmx_pciercx_cfg021_s cn52xxp1;
464 struct cvmx_pciercx_cfg021_s cn56xx; 549 struct cvmx_pciercx_cfg021_s cn56xx;
465 struct cvmx_pciercx_cfg021_s cn56xxp1; 550 struct cvmx_pciercx_cfg021_s cn56xxp1;
551 struct cvmx_pciercx_cfg021_s cn61xx;
466 struct cvmx_pciercx_cfg021_s cn63xx; 552 struct cvmx_pciercx_cfg021_s cn63xx;
467 struct cvmx_pciercx_cfg021_s cn63xxp1; 553 struct cvmx_pciercx_cfg021_s cn63xxp1;
554 struct cvmx_pciercx_cfg021_s cn66xx;
555 struct cvmx_pciercx_cfg021_s cn68xx;
556 struct cvmx_pciercx_cfg021_s cn68xxp1;
468}; 557};
469 558
470union cvmx_pciercx_cfg022 { 559union cvmx_pciercx_cfg022 {
@@ -476,8 +565,12 @@ union cvmx_pciercx_cfg022 {
476 struct cvmx_pciercx_cfg022_s cn52xxp1; 565 struct cvmx_pciercx_cfg022_s cn52xxp1;
477 struct cvmx_pciercx_cfg022_s cn56xx; 566 struct cvmx_pciercx_cfg022_s cn56xx;
478 struct cvmx_pciercx_cfg022_s cn56xxp1; 567 struct cvmx_pciercx_cfg022_s cn56xxp1;
568 struct cvmx_pciercx_cfg022_s cn61xx;
479 struct cvmx_pciercx_cfg022_s cn63xx; 569 struct cvmx_pciercx_cfg022_s cn63xx;
480 struct cvmx_pciercx_cfg022_s cn63xxp1; 570 struct cvmx_pciercx_cfg022_s cn63xxp1;
571 struct cvmx_pciercx_cfg022_s cn66xx;
572 struct cvmx_pciercx_cfg022_s cn68xx;
573 struct cvmx_pciercx_cfg022_s cn68xxp1;
481}; 574};
482 575
483union cvmx_pciercx_cfg023 { 576union cvmx_pciercx_cfg023 {
@@ -490,8 +583,12 @@ union cvmx_pciercx_cfg023 {
490 struct cvmx_pciercx_cfg023_s cn52xxp1; 583 struct cvmx_pciercx_cfg023_s cn52xxp1;
491 struct cvmx_pciercx_cfg023_s cn56xx; 584 struct cvmx_pciercx_cfg023_s cn56xx;
492 struct cvmx_pciercx_cfg023_s cn56xxp1; 585 struct cvmx_pciercx_cfg023_s cn56xxp1;
586 struct cvmx_pciercx_cfg023_s cn61xx;
493 struct cvmx_pciercx_cfg023_s cn63xx; 587 struct cvmx_pciercx_cfg023_s cn63xx;
494 struct cvmx_pciercx_cfg023_s cn63xxp1; 588 struct cvmx_pciercx_cfg023_s cn63xxp1;
589 struct cvmx_pciercx_cfg023_s cn66xx;
590 struct cvmx_pciercx_cfg023_s cn68xx;
591 struct cvmx_pciercx_cfg023_s cn68xxp1;
495}; 592};
496 593
497union cvmx_pciercx_cfg028 { 594union cvmx_pciercx_cfg028 {
@@ -509,8 +606,12 @@ union cvmx_pciercx_cfg028 {
509 struct cvmx_pciercx_cfg028_s cn52xxp1; 606 struct cvmx_pciercx_cfg028_s cn52xxp1;
510 struct cvmx_pciercx_cfg028_s cn56xx; 607 struct cvmx_pciercx_cfg028_s cn56xx;
511 struct cvmx_pciercx_cfg028_s cn56xxp1; 608 struct cvmx_pciercx_cfg028_s cn56xxp1;
609 struct cvmx_pciercx_cfg028_s cn61xx;
512 struct cvmx_pciercx_cfg028_s cn63xx; 610 struct cvmx_pciercx_cfg028_s cn63xx;
513 struct cvmx_pciercx_cfg028_s cn63xxp1; 611 struct cvmx_pciercx_cfg028_s cn63xxp1;
612 struct cvmx_pciercx_cfg028_s cn66xx;
613 struct cvmx_pciercx_cfg028_s cn68xx;
614 struct cvmx_pciercx_cfg028_s cn68xxp1;
514}; 615};
515 616
516union cvmx_pciercx_cfg029 { 617union cvmx_pciercx_cfg029 {
@@ -532,8 +633,12 @@ union cvmx_pciercx_cfg029 {
532 struct cvmx_pciercx_cfg029_s cn52xxp1; 633 struct cvmx_pciercx_cfg029_s cn52xxp1;
533 struct cvmx_pciercx_cfg029_s cn56xx; 634 struct cvmx_pciercx_cfg029_s cn56xx;
534 struct cvmx_pciercx_cfg029_s cn56xxp1; 635 struct cvmx_pciercx_cfg029_s cn56xxp1;
636 struct cvmx_pciercx_cfg029_s cn61xx;
535 struct cvmx_pciercx_cfg029_s cn63xx; 637 struct cvmx_pciercx_cfg029_s cn63xx;
536 struct cvmx_pciercx_cfg029_s cn63xxp1; 638 struct cvmx_pciercx_cfg029_s cn63xxp1;
639 struct cvmx_pciercx_cfg029_s cn66xx;
640 struct cvmx_pciercx_cfg029_s cn68xx;
641 struct cvmx_pciercx_cfg029_s cn68xxp1;
537}; 642};
538 643
539union cvmx_pciercx_cfg030 { 644union cvmx_pciercx_cfg030 {
@@ -563,15 +668,20 @@ union cvmx_pciercx_cfg030 {
563 struct cvmx_pciercx_cfg030_s cn52xxp1; 668 struct cvmx_pciercx_cfg030_s cn52xxp1;
564 struct cvmx_pciercx_cfg030_s cn56xx; 669 struct cvmx_pciercx_cfg030_s cn56xx;
565 struct cvmx_pciercx_cfg030_s cn56xxp1; 670 struct cvmx_pciercx_cfg030_s cn56xxp1;
671 struct cvmx_pciercx_cfg030_s cn61xx;
566 struct cvmx_pciercx_cfg030_s cn63xx; 672 struct cvmx_pciercx_cfg030_s cn63xx;
567 struct cvmx_pciercx_cfg030_s cn63xxp1; 673 struct cvmx_pciercx_cfg030_s cn63xxp1;
674 struct cvmx_pciercx_cfg030_s cn66xx;
675 struct cvmx_pciercx_cfg030_s cn68xx;
676 struct cvmx_pciercx_cfg030_s cn68xxp1;
568}; 677};
569 678
570union cvmx_pciercx_cfg031 { 679union cvmx_pciercx_cfg031 {
571 uint32_t u32; 680 uint32_t u32;
572 struct cvmx_pciercx_cfg031_s { 681 struct cvmx_pciercx_cfg031_s {
573 uint32_t pnum:8; 682 uint32_t pnum:8;
574 uint32_t reserved_22_23:2; 683 uint32_t reserved_23_23:1;
684 uint32_t aspm:1;
575 uint32_t lbnc:1; 685 uint32_t lbnc:1;
576 uint32_t dllarc:1; 686 uint32_t dllarc:1;
577 uint32_t sderc:1; 687 uint32_t sderc:1;
@@ -582,12 +692,28 @@ union cvmx_pciercx_cfg031 {
582 uint32_t mlw:6; 692 uint32_t mlw:6;
583 uint32_t mls:4; 693 uint32_t mls:4;
584 } s; 694 } s;
585 struct cvmx_pciercx_cfg031_s cn52xx; 695 struct cvmx_pciercx_cfg031_cn52xx {
586 struct cvmx_pciercx_cfg031_s cn52xxp1; 696 uint32_t pnum:8;
587 struct cvmx_pciercx_cfg031_s cn56xx; 697 uint32_t reserved_22_23:2;
588 struct cvmx_pciercx_cfg031_s cn56xxp1; 698 uint32_t lbnc:1;
589 struct cvmx_pciercx_cfg031_s cn63xx; 699 uint32_t dllarc:1;
590 struct cvmx_pciercx_cfg031_s cn63xxp1; 700 uint32_t sderc:1;
701 uint32_t cpm:1;
702 uint32_t l1el:3;
703 uint32_t l0el:3;
704 uint32_t aslpms:2;
705 uint32_t mlw:6;
706 uint32_t mls:4;
707 } cn52xx;
708 struct cvmx_pciercx_cfg031_cn52xx cn52xxp1;
709 struct cvmx_pciercx_cfg031_cn52xx cn56xx;
710 struct cvmx_pciercx_cfg031_cn52xx cn56xxp1;
711 struct cvmx_pciercx_cfg031_s cn61xx;
712 struct cvmx_pciercx_cfg031_cn52xx cn63xx;
713 struct cvmx_pciercx_cfg031_cn52xx cn63xxp1;
714 struct cvmx_pciercx_cfg031_s cn66xx;
715 struct cvmx_pciercx_cfg031_s cn68xx;
716 struct cvmx_pciercx_cfg031_cn52xx cn68xxp1;
591}; 717};
592 718
593union cvmx_pciercx_cfg032 { 719union cvmx_pciercx_cfg032 {
@@ -618,8 +744,12 @@ union cvmx_pciercx_cfg032 {
618 struct cvmx_pciercx_cfg032_s cn52xxp1; 744 struct cvmx_pciercx_cfg032_s cn52xxp1;
619 struct cvmx_pciercx_cfg032_s cn56xx; 745 struct cvmx_pciercx_cfg032_s cn56xx;
620 struct cvmx_pciercx_cfg032_s cn56xxp1; 746 struct cvmx_pciercx_cfg032_s cn56xxp1;
747 struct cvmx_pciercx_cfg032_s cn61xx;
621 struct cvmx_pciercx_cfg032_s cn63xx; 748 struct cvmx_pciercx_cfg032_s cn63xx;
622 struct cvmx_pciercx_cfg032_s cn63xxp1; 749 struct cvmx_pciercx_cfg032_s cn63xxp1;
750 struct cvmx_pciercx_cfg032_s cn66xx;
751 struct cvmx_pciercx_cfg032_s cn68xx;
752 struct cvmx_pciercx_cfg032_s cn68xxp1;
623}; 753};
624 754
625union cvmx_pciercx_cfg033 { 755union cvmx_pciercx_cfg033 {
@@ -642,8 +772,12 @@ union cvmx_pciercx_cfg033 {
642 struct cvmx_pciercx_cfg033_s cn52xxp1; 772 struct cvmx_pciercx_cfg033_s cn52xxp1;
643 struct cvmx_pciercx_cfg033_s cn56xx; 773 struct cvmx_pciercx_cfg033_s cn56xx;
644 struct cvmx_pciercx_cfg033_s cn56xxp1; 774 struct cvmx_pciercx_cfg033_s cn56xxp1;
775 struct cvmx_pciercx_cfg033_s cn61xx;
645 struct cvmx_pciercx_cfg033_s cn63xx; 776 struct cvmx_pciercx_cfg033_s cn63xx;
646 struct cvmx_pciercx_cfg033_s cn63xxp1; 777 struct cvmx_pciercx_cfg033_s cn63xxp1;
778 struct cvmx_pciercx_cfg033_s cn66xx;
779 struct cvmx_pciercx_cfg033_s cn68xx;
780 struct cvmx_pciercx_cfg033_s cn68xxp1;
647}; 781};
648 782
649union cvmx_pciercx_cfg034 { 783union cvmx_pciercx_cfg034 {
@@ -676,8 +810,12 @@ union cvmx_pciercx_cfg034 {
676 struct cvmx_pciercx_cfg034_s cn52xxp1; 810 struct cvmx_pciercx_cfg034_s cn52xxp1;
677 struct cvmx_pciercx_cfg034_s cn56xx; 811 struct cvmx_pciercx_cfg034_s cn56xx;
678 struct cvmx_pciercx_cfg034_s cn56xxp1; 812 struct cvmx_pciercx_cfg034_s cn56xxp1;
813 struct cvmx_pciercx_cfg034_s cn61xx;
679 struct cvmx_pciercx_cfg034_s cn63xx; 814 struct cvmx_pciercx_cfg034_s cn63xx;
680 struct cvmx_pciercx_cfg034_s cn63xxp1; 815 struct cvmx_pciercx_cfg034_s cn63xxp1;
816 struct cvmx_pciercx_cfg034_s cn66xx;
817 struct cvmx_pciercx_cfg034_s cn68xx;
818 struct cvmx_pciercx_cfg034_s cn68xxp1;
681}; 819};
682 820
683union cvmx_pciercx_cfg035 { 821union cvmx_pciercx_cfg035 {
@@ -696,8 +834,12 @@ union cvmx_pciercx_cfg035 {
696 struct cvmx_pciercx_cfg035_s cn52xxp1; 834 struct cvmx_pciercx_cfg035_s cn52xxp1;
697 struct cvmx_pciercx_cfg035_s cn56xx; 835 struct cvmx_pciercx_cfg035_s cn56xx;
698 struct cvmx_pciercx_cfg035_s cn56xxp1; 836 struct cvmx_pciercx_cfg035_s cn56xxp1;
837 struct cvmx_pciercx_cfg035_s cn61xx;
699 struct cvmx_pciercx_cfg035_s cn63xx; 838 struct cvmx_pciercx_cfg035_s cn63xx;
700 struct cvmx_pciercx_cfg035_s cn63xxp1; 839 struct cvmx_pciercx_cfg035_s cn63xxp1;
840 struct cvmx_pciercx_cfg035_s cn66xx;
841 struct cvmx_pciercx_cfg035_s cn68xx;
842 struct cvmx_pciercx_cfg035_s cn68xxp1;
701}; 843};
702 844
703union cvmx_pciercx_cfg036 { 845union cvmx_pciercx_cfg036 {
@@ -712,38 +854,95 @@ union cvmx_pciercx_cfg036 {
712 struct cvmx_pciercx_cfg036_s cn52xxp1; 854 struct cvmx_pciercx_cfg036_s cn52xxp1;
713 struct cvmx_pciercx_cfg036_s cn56xx; 855 struct cvmx_pciercx_cfg036_s cn56xx;
714 struct cvmx_pciercx_cfg036_s cn56xxp1; 856 struct cvmx_pciercx_cfg036_s cn56xxp1;
857 struct cvmx_pciercx_cfg036_s cn61xx;
715 struct cvmx_pciercx_cfg036_s cn63xx; 858 struct cvmx_pciercx_cfg036_s cn63xx;
716 struct cvmx_pciercx_cfg036_s cn63xxp1; 859 struct cvmx_pciercx_cfg036_s cn63xxp1;
860 struct cvmx_pciercx_cfg036_s cn66xx;
861 struct cvmx_pciercx_cfg036_s cn68xx;
862 struct cvmx_pciercx_cfg036_s cn68xxp1;
717}; 863};
718 864
719union cvmx_pciercx_cfg037 { 865union cvmx_pciercx_cfg037 {
720 uint32_t u32; 866 uint32_t u32;
721 struct cvmx_pciercx_cfg037_s { 867 struct cvmx_pciercx_cfg037_s {
722 uint32_t reserved_5_31:27; 868 uint32_t reserved_14_31:18;
869 uint32_t tph:2;
870 uint32_t reserved_11_11:1;
871 uint32_t noroprpr:1;
872 uint32_t atom128s:1;
873 uint32_t atom64s:1;
874 uint32_t atom32s:1;
875 uint32_t atom_ops:1;
876 uint32_t reserved_5_5:1;
723 uint32_t ctds:1; 877 uint32_t ctds:1;
724 uint32_t ctrs:4; 878 uint32_t ctrs:4;
725 } s; 879 } s;
726 struct cvmx_pciercx_cfg037_s cn52xx; 880 struct cvmx_pciercx_cfg037_cn52xx {
727 struct cvmx_pciercx_cfg037_s cn52xxp1; 881 uint32_t reserved_5_31:27;
728 struct cvmx_pciercx_cfg037_s cn56xx; 882 uint32_t ctds:1;
729 struct cvmx_pciercx_cfg037_s cn56xxp1; 883 uint32_t ctrs:4;
730 struct cvmx_pciercx_cfg037_s cn63xx; 884 } cn52xx;
731 struct cvmx_pciercx_cfg037_s cn63xxp1; 885 struct cvmx_pciercx_cfg037_cn52xx cn52xxp1;
886 struct cvmx_pciercx_cfg037_cn52xx cn56xx;
887 struct cvmx_pciercx_cfg037_cn52xx cn56xxp1;
888 struct cvmx_pciercx_cfg037_cn61xx {
889 uint32_t reserved_14_31:18;
890 uint32_t tph:2;
891 uint32_t reserved_11_11:1;
892 uint32_t noroprpr:1;
893 uint32_t atom128s:1;
894 uint32_t atom64s:1;
895 uint32_t atom32s:1;
896 uint32_t atom_ops:1;
897 uint32_t ari_fw:1;
898 uint32_t ctds:1;
899 uint32_t ctrs:4;
900 } cn61xx;
901 struct cvmx_pciercx_cfg037_cn52xx cn63xx;
902 struct cvmx_pciercx_cfg037_cn52xx cn63xxp1;
903 struct cvmx_pciercx_cfg037_cn66xx {
904 uint32_t reserved_14_31:18;
905 uint32_t tph:2;
906 uint32_t reserved_11_11:1;
907 uint32_t noroprpr:1;
908 uint32_t atom128s:1;
909 uint32_t atom64s:1;
910 uint32_t atom32s:1;
911 uint32_t atom_ops:1;
912 uint32_t ari:1;
913 uint32_t ctds:1;
914 uint32_t ctrs:4;
915 } cn66xx;
916 struct cvmx_pciercx_cfg037_cn66xx cn68xx;
917 struct cvmx_pciercx_cfg037_cn66xx cn68xxp1;
732}; 918};
733 919
734union cvmx_pciercx_cfg038 { 920union cvmx_pciercx_cfg038 {
735 uint32_t u32; 921 uint32_t u32;
736 struct cvmx_pciercx_cfg038_s { 922 struct cvmx_pciercx_cfg038_s {
737 uint32_t reserved_5_31:27; 923 uint32_t reserved_10_31:22;
924 uint32_t id0_cp:1;
925 uint32_t id0_rq:1;
926 uint32_t atom_op_eb:1;
927 uint32_t atom_op:1;
928 uint32_t ari:1;
738 uint32_t ctd:1; 929 uint32_t ctd:1;
739 uint32_t ctv:4; 930 uint32_t ctv:4;
740 } s; 931 } s;
741 struct cvmx_pciercx_cfg038_s cn52xx; 932 struct cvmx_pciercx_cfg038_cn52xx {
742 struct cvmx_pciercx_cfg038_s cn52xxp1; 933 uint32_t reserved_5_31:27;
743 struct cvmx_pciercx_cfg038_s cn56xx; 934 uint32_t ctd:1;
744 struct cvmx_pciercx_cfg038_s cn56xxp1; 935 uint32_t ctv:4;
745 struct cvmx_pciercx_cfg038_s cn63xx; 936 } cn52xx;
746 struct cvmx_pciercx_cfg038_s cn63xxp1; 937 struct cvmx_pciercx_cfg038_cn52xx cn52xxp1;
938 struct cvmx_pciercx_cfg038_cn52xx cn56xx;
939 struct cvmx_pciercx_cfg038_cn52xx cn56xxp1;
940 struct cvmx_pciercx_cfg038_s cn61xx;
941 struct cvmx_pciercx_cfg038_cn52xx cn63xx;
942 struct cvmx_pciercx_cfg038_cn52xx cn63xxp1;
943 struct cvmx_pciercx_cfg038_s cn66xx;
944 struct cvmx_pciercx_cfg038_s cn68xx;
945 struct cvmx_pciercx_cfg038_s cn68xxp1;
747}; 946};
748 947
749union cvmx_pciercx_cfg039 { 948union cvmx_pciercx_cfg039 {
@@ -760,8 +959,12 @@ union cvmx_pciercx_cfg039 {
760 struct cvmx_pciercx_cfg039_cn52xx cn52xxp1; 959 struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
761 struct cvmx_pciercx_cfg039_cn52xx cn56xx; 960 struct cvmx_pciercx_cfg039_cn52xx cn56xx;
762 struct cvmx_pciercx_cfg039_cn52xx cn56xxp1; 961 struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
962 struct cvmx_pciercx_cfg039_s cn61xx;
763 struct cvmx_pciercx_cfg039_s cn63xx; 963 struct cvmx_pciercx_cfg039_s cn63xx;
764 struct cvmx_pciercx_cfg039_cn52xx cn63xxp1; 964 struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
965 struct cvmx_pciercx_cfg039_s cn66xx;
966 struct cvmx_pciercx_cfg039_s cn68xx;
967 struct cvmx_pciercx_cfg039_s cn68xxp1;
765}; 968};
766 969
767union cvmx_pciercx_cfg040 { 970union cvmx_pciercx_cfg040 {
@@ -785,8 +988,12 @@ union cvmx_pciercx_cfg040 {
785 struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; 988 struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
786 struct cvmx_pciercx_cfg040_cn52xx cn56xx; 989 struct cvmx_pciercx_cfg040_cn52xx cn56xx;
787 struct cvmx_pciercx_cfg040_cn52xx cn56xxp1; 990 struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
991 struct cvmx_pciercx_cfg040_s cn61xx;
788 struct cvmx_pciercx_cfg040_s cn63xx; 992 struct cvmx_pciercx_cfg040_s cn63xx;
789 struct cvmx_pciercx_cfg040_s cn63xxp1; 993 struct cvmx_pciercx_cfg040_s cn63xxp1;
994 struct cvmx_pciercx_cfg040_s cn66xx;
995 struct cvmx_pciercx_cfg040_s cn68xx;
996 struct cvmx_pciercx_cfg040_s cn68xxp1;
790}; 997};
791 998
792union cvmx_pciercx_cfg041 { 999union cvmx_pciercx_cfg041 {
@@ -798,8 +1005,12 @@ union cvmx_pciercx_cfg041 {
798 struct cvmx_pciercx_cfg041_s cn52xxp1; 1005 struct cvmx_pciercx_cfg041_s cn52xxp1;
799 struct cvmx_pciercx_cfg041_s cn56xx; 1006 struct cvmx_pciercx_cfg041_s cn56xx;
800 struct cvmx_pciercx_cfg041_s cn56xxp1; 1007 struct cvmx_pciercx_cfg041_s cn56xxp1;
1008 struct cvmx_pciercx_cfg041_s cn61xx;
801 struct cvmx_pciercx_cfg041_s cn63xx; 1009 struct cvmx_pciercx_cfg041_s cn63xx;
802 struct cvmx_pciercx_cfg041_s cn63xxp1; 1010 struct cvmx_pciercx_cfg041_s cn63xxp1;
1011 struct cvmx_pciercx_cfg041_s cn66xx;
1012 struct cvmx_pciercx_cfg041_s cn68xx;
1013 struct cvmx_pciercx_cfg041_s cn68xxp1;
803}; 1014};
804 1015
805union cvmx_pciercx_cfg042 { 1016union cvmx_pciercx_cfg042 {
@@ -811,8 +1022,12 @@ union cvmx_pciercx_cfg042 {
811 struct cvmx_pciercx_cfg042_s cn52xxp1; 1022 struct cvmx_pciercx_cfg042_s cn52xxp1;
812 struct cvmx_pciercx_cfg042_s cn56xx; 1023 struct cvmx_pciercx_cfg042_s cn56xx;
813 struct cvmx_pciercx_cfg042_s cn56xxp1; 1024 struct cvmx_pciercx_cfg042_s cn56xxp1;
1025 struct cvmx_pciercx_cfg042_s cn61xx;
814 struct cvmx_pciercx_cfg042_s cn63xx; 1026 struct cvmx_pciercx_cfg042_s cn63xx;
815 struct cvmx_pciercx_cfg042_s cn63xxp1; 1027 struct cvmx_pciercx_cfg042_s cn63xxp1;
1028 struct cvmx_pciercx_cfg042_s cn66xx;
1029 struct cvmx_pciercx_cfg042_s cn68xx;
1030 struct cvmx_pciercx_cfg042_s cn68xxp1;
816}; 1031};
817 1032
818union cvmx_pciercx_cfg064 { 1033union cvmx_pciercx_cfg064 {
@@ -826,14 +1041,20 @@ union cvmx_pciercx_cfg064 {
826 struct cvmx_pciercx_cfg064_s cn52xxp1; 1041 struct cvmx_pciercx_cfg064_s cn52xxp1;
827 struct cvmx_pciercx_cfg064_s cn56xx; 1042 struct cvmx_pciercx_cfg064_s cn56xx;
828 struct cvmx_pciercx_cfg064_s cn56xxp1; 1043 struct cvmx_pciercx_cfg064_s cn56xxp1;
1044 struct cvmx_pciercx_cfg064_s cn61xx;
829 struct cvmx_pciercx_cfg064_s cn63xx; 1045 struct cvmx_pciercx_cfg064_s cn63xx;
830 struct cvmx_pciercx_cfg064_s cn63xxp1; 1046 struct cvmx_pciercx_cfg064_s cn63xxp1;
1047 struct cvmx_pciercx_cfg064_s cn66xx;
1048 struct cvmx_pciercx_cfg064_s cn68xx;
1049 struct cvmx_pciercx_cfg064_s cn68xxp1;
831}; 1050};
832 1051
833union cvmx_pciercx_cfg065 { 1052union cvmx_pciercx_cfg065 {
834 uint32_t u32; 1053 uint32_t u32;
835 struct cvmx_pciercx_cfg065_s { 1054 struct cvmx_pciercx_cfg065_s {
836 uint32_t reserved_21_31:11; 1055 uint32_t reserved_25_31:7;
1056 uint32_t uatombs:1;
1057 uint32_t reserved_21_23:3;
837 uint32_t ures:1; 1058 uint32_t ures:1;
838 uint32_t ecrces:1; 1059 uint32_t ecrces:1;
839 uint32_t mtlps:1; 1060 uint32_t mtlps:1;
@@ -848,18 +1069,39 @@ union cvmx_pciercx_cfg065 {
848 uint32_t dlpes:1; 1069 uint32_t dlpes:1;
849 uint32_t reserved_0_3:4; 1070 uint32_t reserved_0_3:4;
850 } s; 1071 } s;
851 struct cvmx_pciercx_cfg065_s cn52xx; 1072 struct cvmx_pciercx_cfg065_cn52xx {
852 struct cvmx_pciercx_cfg065_s cn52xxp1; 1073 uint32_t reserved_21_31:11;
853 struct cvmx_pciercx_cfg065_s cn56xx; 1074 uint32_t ures:1;
854 struct cvmx_pciercx_cfg065_s cn56xxp1; 1075 uint32_t ecrces:1;
855 struct cvmx_pciercx_cfg065_s cn63xx; 1076 uint32_t mtlps:1;
856 struct cvmx_pciercx_cfg065_s cn63xxp1; 1077 uint32_t ros:1;
1078 uint32_t ucs:1;
1079 uint32_t cas:1;
1080 uint32_t cts:1;
1081 uint32_t fcpes:1;
1082 uint32_t ptlps:1;
1083 uint32_t reserved_6_11:6;
1084 uint32_t sdes:1;
1085 uint32_t dlpes:1;
1086 uint32_t reserved_0_3:4;
1087 } cn52xx;
1088 struct cvmx_pciercx_cfg065_cn52xx cn52xxp1;
1089 struct cvmx_pciercx_cfg065_cn52xx cn56xx;
1090 struct cvmx_pciercx_cfg065_cn52xx cn56xxp1;
1091 struct cvmx_pciercx_cfg065_s cn61xx;
1092 struct cvmx_pciercx_cfg065_cn52xx cn63xx;
1093 struct cvmx_pciercx_cfg065_cn52xx cn63xxp1;
1094 struct cvmx_pciercx_cfg065_s cn66xx;
1095 struct cvmx_pciercx_cfg065_s cn68xx;
1096 struct cvmx_pciercx_cfg065_cn52xx cn68xxp1;
857}; 1097};
858 1098
859union cvmx_pciercx_cfg066 { 1099union cvmx_pciercx_cfg066 {
860 uint32_t u32; 1100 uint32_t u32;
861 struct cvmx_pciercx_cfg066_s { 1101 struct cvmx_pciercx_cfg066_s {
862 uint32_t reserved_21_31:11; 1102 uint32_t reserved_25_31:7;
1103 uint32_t uatombm:1;
1104 uint32_t reserved_21_23:3;
863 uint32_t urem:1; 1105 uint32_t urem:1;
864 uint32_t ecrcem:1; 1106 uint32_t ecrcem:1;
865 uint32_t mtlpm:1; 1107 uint32_t mtlpm:1;
@@ -874,18 +1116,39 @@ union cvmx_pciercx_cfg066 {
874 uint32_t dlpem:1; 1116 uint32_t dlpem:1;
875 uint32_t reserved_0_3:4; 1117 uint32_t reserved_0_3:4;
876 } s; 1118 } s;
877 struct cvmx_pciercx_cfg066_s cn52xx; 1119 struct cvmx_pciercx_cfg066_cn52xx {
878 struct cvmx_pciercx_cfg066_s cn52xxp1; 1120 uint32_t reserved_21_31:11;
879 struct cvmx_pciercx_cfg066_s cn56xx; 1121 uint32_t urem:1;
880 struct cvmx_pciercx_cfg066_s cn56xxp1; 1122 uint32_t ecrcem:1;
881 struct cvmx_pciercx_cfg066_s cn63xx; 1123 uint32_t mtlpm:1;
882 struct cvmx_pciercx_cfg066_s cn63xxp1; 1124 uint32_t rom:1;
1125 uint32_t ucm:1;
1126 uint32_t cam:1;
1127 uint32_t ctm:1;
1128 uint32_t fcpem:1;
1129 uint32_t ptlpm:1;
1130 uint32_t reserved_6_11:6;
1131 uint32_t sdem:1;
1132 uint32_t dlpem:1;
1133 uint32_t reserved_0_3:4;
1134 } cn52xx;
1135 struct cvmx_pciercx_cfg066_cn52xx cn52xxp1;
1136 struct cvmx_pciercx_cfg066_cn52xx cn56xx;
1137 struct cvmx_pciercx_cfg066_cn52xx cn56xxp1;
1138 struct cvmx_pciercx_cfg066_s cn61xx;
1139 struct cvmx_pciercx_cfg066_cn52xx cn63xx;
1140 struct cvmx_pciercx_cfg066_cn52xx cn63xxp1;
1141 struct cvmx_pciercx_cfg066_s cn66xx;
1142 struct cvmx_pciercx_cfg066_s cn68xx;
1143 struct cvmx_pciercx_cfg066_cn52xx cn68xxp1;
883}; 1144};
884 1145
885union cvmx_pciercx_cfg067 { 1146union cvmx_pciercx_cfg067 {
886 uint32_t u32; 1147 uint32_t u32;
887 struct cvmx_pciercx_cfg067_s { 1148 struct cvmx_pciercx_cfg067_s {
888 uint32_t reserved_21_31:11; 1149 uint32_t reserved_25_31:7;
1150 uint32_t uatombs:1;
1151 uint32_t reserved_21_23:3;
889 uint32_t ures:1; 1152 uint32_t ures:1;
890 uint32_t ecrces:1; 1153 uint32_t ecrces:1;
891 uint32_t mtlps:1; 1154 uint32_t mtlps:1;
@@ -900,12 +1163,31 @@ union cvmx_pciercx_cfg067 {
900 uint32_t dlpes:1; 1163 uint32_t dlpes:1;
901 uint32_t reserved_0_3:4; 1164 uint32_t reserved_0_3:4;
902 } s; 1165 } s;
903 struct cvmx_pciercx_cfg067_s cn52xx; 1166 struct cvmx_pciercx_cfg067_cn52xx {
904 struct cvmx_pciercx_cfg067_s cn52xxp1; 1167 uint32_t reserved_21_31:11;
905 struct cvmx_pciercx_cfg067_s cn56xx; 1168 uint32_t ures:1;
906 struct cvmx_pciercx_cfg067_s cn56xxp1; 1169 uint32_t ecrces:1;
907 struct cvmx_pciercx_cfg067_s cn63xx; 1170 uint32_t mtlps:1;
908 struct cvmx_pciercx_cfg067_s cn63xxp1; 1171 uint32_t ros:1;
1172 uint32_t ucs:1;
1173 uint32_t cas:1;
1174 uint32_t cts:1;
1175 uint32_t fcpes:1;
1176 uint32_t ptlps:1;
1177 uint32_t reserved_6_11:6;
1178 uint32_t sdes:1;
1179 uint32_t dlpes:1;
1180 uint32_t reserved_0_3:4;
1181 } cn52xx;
1182 struct cvmx_pciercx_cfg067_cn52xx cn52xxp1;
1183 struct cvmx_pciercx_cfg067_cn52xx cn56xx;
1184 struct cvmx_pciercx_cfg067_cn52xx cn56xxp1;
1185 struct cvmx_pciercx_cfg067_s cn61xx;
1186 struct cvmx_pciercx_cfg067_cn52xx cn63xx;
1187 struct cvmx_pciercx_cfg067_cn52xx cn63xxp1;
1188 struct cvmx_pciercx_cfg067_s cn66xx;
1189 struct cvmx_pciercx_cfg067_s cn68xx;
1190 struct cvmx_pciercx_cfg067_cn52xx cn68xxp1;
909}; 1191};
910 1192
911union cvmx_pciercx_cfg068 { 1193union cvmx_pciercx_cfg068 {
@@ -925,8 +1207,12 @@ union cvmx_pciercx_cfg068 {
925 struct cvmx_pciercx_cfg068_s cn52xxp1; 1207 struct cvmx_pciercx_cfg068_s cn52xxp1;
926 struct cvmx_pciercx_cfg068_s cn56xx; 1208 struct cvmx_pciercx_cfg068_s cn56xx;
927 struct cvmx_pciercx_cfg068_s cn56xxp1; 1209 struct cvmx_pciercx_cfg068_s cn56xxp1;
1210 struct cvmx_pciercx_cfg068_s cn61xx;
928 struct cvmx_pciercx_cfg068_s cn63xx; 1211 struct cvmx_pciercx_cfg068_s cn63xx;
929 struct cvmx_pciercx_cfg068_s cn63xxp1; 1212 struct cvmx_pciercx_cfg068_s cn63xxp1;
1213 struct cvmx_pciercx_cfg068_s cn66xx;
1214 struct cvmx_pciercx_cfg068_s cn68xx;
1215 struct cvmx_pciercx_cfg068_s cn68xxp1;
930}; 1216};
931 1217
932union cvmx_pciercx_cfg069 { 1218union cvmx_pciercx_cfg069 {
@@ -946,8 +1232,12 @@ union cvmx_pciercx_cfg069 {
946 struct cvmx_pciercx_cfg069_s cn52xxp1; 1232 struct cvmx_pciercx_cfg069_s cn52xxp1;
947 struct cvmx_pciercx_cfg069_s cn56xx; 1233 struct cvmx_pciercx_cfg069_s cn56xx;
948 struct cvmx_pciercx_cfg069_s cn56xxp1; 1234 struct cvmx_pciercx_cfg069_s cn56xxp1;
1235 struct cvmx_pciercx_cfg069_s cn61xx;
949 struct cvmx_pciercx_cfg069_s cn63xx; 1236 struct cvmx_pciercx_cfg069_s cn63xx;
950 struct cvmx_pciercx_cfg069_s cn63xxp1; 1237 struct cvmx_pciercx_cfg069_s cn63xxp1;
1238 struct cvmx_pciercx_cfg069_s cn66xx;
1239 struct cvmx_pciercx_cfg069_s cn68xx;
1240 struct cvmx_pciercx_cfg069_s cn68xxp1;
951}; 1241};
952 1242
953union cvmx_pciercx_cfg070 { 1243union cvmx_pciercx_cfg070 {
@@ -964,8 +1254,12 @@ union cvmx_pciercx_cfg070 {
964 struct cvmx_pciercx_cfg070_s cn52xxp1; 1254 struct cvmx_pciercx_cfg070_s cn52xxp1;
965 struct cvmx_pciercx_cfg070_s cn56xx; 1255 struct cvmx_pciercx_cfg070_s cn56xx;
966 struct cvmx_pciercx_cfg070_s cn56xxp1; 1256 struct cvmx_pciercx_cfg070_s cn56xxp1;
1257 struct cvmx_pciercx_cfg070_s cn61xx;
967 struct cvmx_pciercx_cfg070_s cn63xx; 1258 struct cvmx_pciercx_cfg070_s cn63xx;
968 struct cvmx_pciercx_cfg070_s cn63xxp1; 1259 struct cvmx_pciercx_cfg070_s cn63xxp1;
1260 struct cvmx_pciercx_cfg070_s cn66xx;
1261 struct cvmx_pciercx_cfg070_s cn68xx;
1262 struct cvmx_pciercx_cfg070_s cn68xxp1;
969}; 1263};
970 1264
971union cvmx_pciercx_cfg071 { 1265union cvmx_pciercx_cfg071 {
@@ -977,8 +1271,12 @@ union cvmx_pciercx_cfg071 {
977 struct cvmx_pciercx_cfg071_s cn52xxp1; 1271 struct cvmx_pciercx_cfg071_s cn52xxp1;
978 struct cvmx_pciercx_cfg071_s cn56xx; 1272 struct cvmx_pciercx_cfg071_s cn56xx;
979 struct cvmx_pciercx_cfg071_s cn56xxp1; 1273 struct cvmx_pciercx_cfg071_s cn56xxp1;
1274 struct cvmx_pciercx_cfg071_s cn61xx;
980 struct cvmx_pciercx_cfg071_s cn63xx; 1275 struct cvmx_pciercx_cfg071_s cn63xx;
981 struct cvmx_pciercx_cfg071_s cn63xxp1; 1276 struct cvmx_pciercx_cfg071_s cn63xxp1;
1277 struct cvmx_pciercx_cfg071_s cn66xx;
1278 struct cvmx_pciercx_cfg071_s cn68xx;
1279 struct cvmx_pciercx_cfg071_s cn68xxp1;
982}; 1280};
983 1281
984union cvmx_pciercx_cfg072 { 1282union cvmx_pciercx_cfg072 {
@@ -990,8 +1288,12 @@ union cvmx_pciercx_cfg072 {
990 struct cvmx_pciercx_cfg072_s cn52xxp1; 1288 struct cvmx_pciercx_cfg072_s cn52xxp1;
991 struct cvmx_pciercx_cfg072_s cn56xx; 1289 struct cvmx_pciercx_cfg072_s cn56xx;
992 struct cvmx_pciercx_cfg072_s cn56xxp1; 1290 struct cvmx_pciercx_cfg072_s cn56xxp1;
1291 struct cvmx_pciercx_cfg072_s cn61xx;
993 struct cvmx_pciercx_cfg072_s cn63xx; 1292 struct cvmx_pciercx_cfg072_s cn63xx;
994 struct cvmx_pciercx_cfg072_s cn63xxp1; 1293 struct cvmx_pciercx_cfg072_s cn63xxp1;
1294 struct cvmx_pciercx_cfg072_s cn66xx;
1295 struct cvmx_pciercx_cfg072_s cn68xx;
1296 struct cvmx_pciercx_cfg072_s cn68xxp1;
995}; 1297};
996 1298
997union cvmx_pciercx_cfg073 { 1299union cvmx_pciercx_cfg073 {
@@ -1003,8 +1305,12 @@ union cvmx_pciercx_cfg073 {
1003 struct cvmx_pciercx_cfg073_s cn52xxp1; 1305 struct cvmx_pciercx_cfg073_s cn52xxp1;
1004 struct cvmx_pciercx_cfg073_s cn56xx; 1306 struct cvmx_pciercx_cfg073_s cn56xx;
1005 struct cvmx_pciercx_cfg073_s cn56xxp1; 1307 struct cvmx_pciercx_cfg073_s cn56xxp1;
1308 struct cvmx_pciercx_cfg073_s cn61xx;
1006 struct cvmx_pciercx_cfg073_s cn63xx; 1309 struct cvmx_pciercx_cfg073_s cn63xx;
1007 struct cvmx_pciercx_cfg073_s cn63xxp1; 1310 struct cvmx_pciercx_cfg073_s cn63xxp1;
1311 struct cvmx_pciercx_cfg073_s cn66xx;
1312 struct cvmx_pciercx_cfg073_s cn68xx;
1313 struct cvmx_pciercx_cfg073_s cn68xxp1;
1008}; 1314};
1009 1315
1010union cvmx_pciercx_cfg074 { 1316union cvmx_pciercx_cfg074 {
@@ -1016,8 +1322,12 @@ union cvmx_pciercx_cfg074 {
1016 struct cvmx_pciercx_cfg074_s cn52xxp1; 1322 struct cvmx_pciercx_cfg074_s cn52xxp1;
1017 struct cvmx_pciercx_cfg074_s cn56xx; 1323 struct cvmx_pciercx_cfg074_s cn56xx;
1018 struct cvmx_pciercx_cfg074_s cn56xxp1; 1324 struct cvmx_pciercx_cfg074_s cn56xxp1;
1325 struct cvmx_pciercx_cfg074_s cn61xx;
1019 struct cvmx_pciercx_cfg074_s cn63xx; 1326 struct cvmx_pciercx_cfg074_s cn63xx;
1020 struct cvmx_pciercx_cfg074_s cn63xxp1; 1327 struct cvmx_pciercx_cfg074_s cn63xxp1;
1328 struct cvmx_pciercx_cfg074_s cn66xx;
1329 struct cvmx_pciercx_cfg074_s cn68xx;
1330 struct cvmx_pciercx_cfg074_s cn68xxp1;
1021}; 1331};
1022 1332
1023union cvmx_pciercx_cfg075 { 1333union cvmx_pciercx_cfg075 {
@@ -1032,8 +1342,12 @@ union cvmx_pciercx_cfg075 {
1032 struct cvmx_pciercx_cfg075_s cn52xxp1; 1342 struct cvmx_pciercx_cfg075_s cn52xxp1;
1033 struct cvmx_pciercx_cfg075_s cn56xx; 1343 struct cvmx_pciercx_cfg075_s cn56xx;
1034 struct cvmx_pciercx_cfg075_s cn56xxp1; 1344 struct cvmx_pciercx_cfg075_s cn56xxp1;
1345 struct cvmx_pciercx_cfg075_s cn61xx;
1035 struct cvmx_pciercx_cfg075_s cn63xx; 1346 struct cvmx_pciercx_cfg075_s cn63xx;
1036 struct cvmx_pciercx_cfg075_s cn63xxp1; 1347 struct cvmx_pciercx_cfg075_s cn63xxp1;
1348 struct cvmx_pciercx_cfg075_s cn66xx;
1349 struct cvmx_pciercx_cfg075_s cn68xx;
1350 struct cvmx_pciercx_cfg075_s cn68xxp1;
1037}; 1351};
1038 1352
1039union cvmx_pciercx_cfg076 { 1353union cvmx_pciercx_cfg076 {
@@ -1053,8 +1367,12 @@ union cvmx_pciercx_cfg076 {
1053 struct cvmx_pciercx_cfg076_s cn52xxp1; 1367 struct cvmx_pciercx_cfg076_s cn52xxp1;
1054 struct cvmx_pciercx_cfg076_s cn56xx; 1368 struct cvmx_pciercx_cfg076_s cn56xx;
1055 struct cvmx_pciercx_cfg076_s cn56xxp1; 1369 struct cvmx_pciercx_cfg076_s cn56xxp1;
1370 struct cvmx_pciercx_cfg076_s cn61xx;
1056 struct cvmx_pciercx_cfg076_s cn63xx; 1371 struct cvmx_pciercx_cfg076_s cn63xx;
1057 struct cvmx_pciercx_cfg076_s cn63xxp1; 1372 struct cvmx_pciercx_cfg076_s cn63xxp1;
1373 struct cvmx_pciercx_cfg076_s cn66xx;
1374 struct cvmx_pciercx_cfg076_s cn68xx;
1375 struct cvmx_pciercx_cfg076_s cn68xxp1;
1058}; 1376};
1059 1377
1060union cvmx_pciercx_cfg077 { 1378union cvmx_pciercx_cfg077 {
@@ -1067,8 +1385,12 @@ union cvmx_pciercx_cfg077 {
1067 struct cvmx_pciercx_cfg077_s cn52xxp1; 1385 struct cvmx_pciercx_cfg077_s cn52xxp1;
1068 struct cvmx_pciercx_cfg077_s cn56xx; 1386 struct cvmx_pciercx_cfg077_s cn56xx;
1069 struct cvmx_pciercx_cfg077_s cn56xxp1; 1387 struct cvmx_pciercx_cfg077_s cn56xxp1;
1388 struct cvmx_pciercx_cfg077_s cn61xx;
1070 struct cvmx_pciercx_cfg077_s cn63xx; 1389 struct cvmx_pciercx_cfg077_s cn63xx;
1071 struct cvmx_pciercx_cfg077_s cn63xxp1; 1390 struct cvmx_pciercx_cfg077_s cn63xxp1;
1391 struct cvmx_pciercx_cfg077_s cn66xx;
1392 struct cvmx_pciercx_cfg077_s cn68xx;
1393 struct cvmx_pciercx_cfg077_s cn68xxp1;
1072}; 1394};
1073 1395
1074union cvmx_pciercx_cfg448 { 1396union cvmx_pciercx_cfg448 {
@@ -1081,8 +1403,12 @@ union cvmx_pciercx_cfg448 {
1081 struct cvmx_pciercx_cfg448_s cn52xxp1; 1403 struct cvmx_pciercx_cfg448_s cn52xxp1;
1082 struct cvmx_pciercx_cfg448_s cn56xx; 1404 struct cvmx_pciercx_cfg448_s cn56xx;
1083 struct cvmx_pciercx_cfg448_s cn56xxp1; 1405 struct cvmx_pciercx_cfg448_s cn56xxp1;
1406 struct cvmx_pciercx_cfg448_s cn61xx;
1084 struct cvmx_pciercx_cfg448_s cn63xx; 1407 struct cvmx_pciercx_cfg448_s cn63xx;
1085 struct cvmx_pciercx_cfg448_s cn63xxp1; 1408 struct cvmx_pciercx_cfg448_s cn63xxp1;
1409 struct cvmx_pciercx_cfg448_s cn66xx;
1410 struct cvmx_pciercx_cfg448_s cn68xx;
1411 struct cvmx_pciercx_cfg448_s cn68xxp1;
1086}; 1412};
1087 1413
1088union cvmx_pciercx_cfg449 { 1414union cvmx_pciercx_cfg449 {
@@ -1094,8 +1420,12 @@ union cvmx_pciercx_cfg449 {
1094 struct cvmx_pciercx_cfg449_s cn52xxp1; 1420 struct cvmx_pciercx_cfg449_s cn52xxp1;
1095 struct cvmx_pciercx_cfg449_s cn56xx; 1421 struct cvmx_pciercx_cfg449_s cn56xx;
1096 struct cvmx_pciercx_cfg449_s cn56xxp1; 1422 struct cvmx_pciercx_cfg449_s cn56xxp1;
1423 struct cvmx_pciercx_cfg449_s cn61xx;
1097 struct cvmx_pciercx_cfg449_s cn63xx; 1424 struct cvmx_pciercx_cfg449_s cn63xx;
1098 struct cvmx_pciercx_cfg449_s cn63xxp1; 1425 struct cvmx_pciercx_cfg449_s cn63xxp1;
1426 struct cvmx_pciercx_cfg449_s cn66xx;
1427 struct cvmx_pciercx_cfg449_s cn68xx;
1428 struct cvmx_pciercx_cfg449_s cn68xxp1;
1099}; 1429};
1100 1430
1101union cvmx_pciercx_cfg450 { 1431union cvmx_pciercx_cfg450 {
@@ -1112,26 +1442,42 @@ union cvmx_pciercx_cfg450 {
1112 struct cvmx_pciercx_cfg450_s cn52xxp1; 1442 struct cvmx_pciercx_cfg450_s cn52xxp1;
1113 struct cvmx_pciercx_cfg450_s cn56xx; 1443 struct cvmx_pciercx_cfg450_s cn56xx;
1114 struct cvmx_pciercx_cfg450_s cn56xxp1; 1444 struct cvmx_pciercx_cfg450_s cn56xxp1;
1445 struct cvmx_pciercx_cfg450_s cn61xx;
1115 struct cvmx_pciercx_cfg450_s cn63xx; 1446 struct cvmx_pciercx_cfg450_s cn63xx;
1116 struct cvmx_pciercx_cfg450_s cn63xxp1; 1447 struct cvmx_pciercx_cfg450_s cn63xxp1;
1448 struct cvmx_pciercx_cfg450_s cn66xx;
1449 struct cvmx_pciercx_cfg450_s cn68xx;
1450 struct cvmx_pciercx_cfg450_s cn68xxp1;
1117}; 1451};
1118 1452
1119union cvmx_pciercx_cfg451 { 1453union cvmx_pciercx_cfg451 {
1120 uint32_t u32; 1454 uint32_t u32;
1121 struct cvmx_pciercx_cfg451_s { 1455 struct cvmx_pciercx_cfg451_s {
1122 uint32_t reserved_30_31:2; 1456 uint32_t reserved_31_31:1;
1457 uint32_t easpml1:1;
1123 uint32_t l1el:3; 1458 uint32_t l1el:3;
1124 uint32_t l0el:3; 1459 uint32_t l0el:3;
1125 uint32_t n_fts_cc:8; 1460 uint32_t n_fts_cc:8;
1126 uint32_t n_fts:8; 1461 uint32_t n_fts:8;
1127 uint32_t ack_freq:8; 1462 uint32_t ack_freq:8;
1128 } s; 1463 } s;
1129 struct cvmx_pciercx_cfg451_s cn52xx; 1464 struct cvmx_pciercx_cfg451_cn52xx {
1130 struct cvmx_pciercx_cfg451_s cn52xxp1; 1465 uint32_t reserved_30_31:2;
1131 struct cvmx_pciercx_cfg451_s cn56xx; 1466 uint32_t l1el:3;
1132 struct cvmx_pciercx_cfg451_s cn56xxp1; 1467 uint32_t l0el:3;
1133 struct cvmx_pciercx_cfg451_s cn63xx; 1468 uint32_t n_fts_cc:8;
1134 struct cvmx_pciercx_cfg451_s cn63xxp1; 1469 uint32_t n_fts:8;
1470 uint32_t ack_freq:8;
1471 } cn52xx;
1472 struct cvmx_pciercx_cfg451_cn52xx cn52xxp1;
1473 struct cvmx_pciercx_cfg451_cn52xx cn56xx;
1474 struct cvmx_pciercx_cfg451_cn52xx cn56xxp1;
1475 struct cvmx_pciercx_cfg451_s cn61xx;
1476 struct cvmx_pciercx_cfg451_cn52xx cn63xx;
1477 struct cvmx_pciercx_cfg451_cn52xx cn63xxp1;
1478 struct cvmx_pciercx_cfg451_s cn66xx;
1479 struct cvmx_pciercx_cfg451_s cn68xx;
1480 struct cvmx_pciercx_cfg451_s cn68xxp1;
1135}; 1481};
1136 1482
1137union cvmx_pciercx_cfg452 { 1483union cvmx_pciercx_cfg452 {
@@ -1155,8 +1501,24 @@ union cvmx_pciercx_cfg452 {
1155 struct cvmx_pciercx_cfg452_s cn52xxp1; 1501 struct cvmx_pciercx_cfg452_s cn52xxp1;
1156 struct cvmx_pciercx_cfg452_s cn56xx; 1502 struct cvmx_pciercx_cfg452_s cn56xx;
1157 struct cvmx_pciercx_cfg452_s cn56xxp1; 1503 struct cvmx_pciercx_cfg452_s cn56xxp1;
1504 struct cvmx_pciercx_cfg452_cn61xx {
1505 uint32_t reserved_22_31:10;
1506 uint32_t lme:6;
1507 uint32_t reserved_8_15:8;
1508 uint32_t flm:1;
1509 uint32_t reserved_6_6:1;
1510 uint32_t dllle:1;
1511 uint32_t reserved_4_4:1;
1512 uint32_t ra:1;
1513 uint32_t le:1;
1514 uint32_t sd:1;
1515 uint32_t omr:1;
1516 } cn61xx;
1158 struct cvmx_pciercx_cfg452_s cn63xx; 1517 struct cvmx_pciercx_cfg452_s cn63xx;
1159 struct cvmx_pciercx_cfg452_s cn63xxp1; 1518 struct cvmx_pciercx_cfg452_s cn63xxp1;
1519 struct cvmx_pciercx_cfg452_cn61xx cn66xx;
1520 struct cvmx_pciercx_cfg452_cn61xx cn68xx;
1521 struct cvmx_pciercx_cfg452_cn61xx cn68xxp1;
1160}; 1522};
1161 1523
1162union cvmx_pciercx_cfg453 { 1524union cvmx_pciercx_cfg453 {
@@ -1172,13 +1534,26 @@ union cvmx_pciercx_cfg453 {
1172 struct cvmx_pciercx_cfg453_s cn52xxp1; 1534 struct cvmx_pciercx_cfg453_s cn52xxp1;
1173 struct cvmx_pciercx_cfg453_s cn56xx; 1535 struct cvmx_pciercx_cfg453_s cn56xx;
1174 struct cvmx_pciercx_cfg453_s cn56xxp1; 1536 struct cvmx_pciercx_cfg453_s cn56xxp1;
1537 struct cvmx_pciercx_cfg453_s cn61xx;
1175 struct cvmx_pciercx_cfg453_s cn63xx; 1538 struct cvmx_pciercx_cfg453_s cn63xx;
1176 struct cvmx_pciercx_cfg453_s cn63xxp1; 1539 struct cvmx_pciercx_cfg453_s cn63xxp1;
1540 struct cvmx_pciercx_cfg453_s cn66xx;
1541 struct cvmx_pciercx_cfg453_s cn68xx;
1542 struct cvmx_pciercx_cfg453_s cn68xxp1;
1177}; 1543};
1178 1544
1179union cvmx_pciercx_cfg454 { 1545union cvmx_pciercx_cfg454 {
1180 uint32_t u32; 1546 uint32_t u32;
1181 struct cvmx_pciercx_cfg454_s { 1547 struct cvmx_pciercx_cfg454_s {
1548 uint32_t cx_nfunc:3;
1549 uint32_t tmfcwt:5;
1550 uint32_t tmanlt:5;
1551 uint32_t tmrt:5;
1552 uint32_t reserved_11_13:3;
1553 uint32_t nskps:3;
1554 uint32_t reserved_0_7:8;
1555 } s;
1556 struct cvmx_pciercx_cfg454_cn52xx {
1182 uint32_t reserved_29_31:3; 1557 uint32_t reserved_29_31:3;
1183 uint32_t tmfcwt:5; 1558 uint32_t tmfcwt:5;
1184 uint32_t tmanlt:5; 1559 uint32_t tmanlt:5;
@@ -1187,13 +1562,23 @@ union cvmx_pciercx_cfg454 {
1187 uint32_t nskps:3; 1562 uint32_t nskps:3;
1188 uint32_t reserved_4_7:4; 1563 uint32_t reserved_4_7:4;
1189 uint32_t ntss:4; 1564 uint32_t ntss:4;
1190 } s; 1565 } cn52xx;
1191 struct cvmx_pciercx_cfg454_s cn52xx; 1566 struct cvmx_pciercx_cfg454_cn52xx cn52xxp1;
1192 struct cvmx_pciercx_cfg454_s cn52xxp1; 1567 struct cvmx_pciercx_cfg454_cn52xx cn56xx;
1193 struct cvmx_pciercx_cfg454_s cn56xx; 1568 struct cvmx_pciercx_cfg454_cn52xx cn56xxp1;
1194 struct cvmx_pciercx_cfg454_s cn56xxp1; 1569 struct cvmx_pciercx_cfg454_cn61xx {
1195 struct cvmx_pciercx_cfg454_s cn63xx; 1570 uint32_t cx_nfunc:3;
1196 struct cvmx_pciercx_cfg454_s cn63xxp1; 1571 uint32_t tmfcwt:5;
1572 uint32_t tmanlt:5;
1573 uint32_t tmrt:5;
1574 uint32_t reserved_8_13:6;
1575 uint32_t mfuncn:8;
1576 } cn61xx;
1577 struct cvmx_pciercx_cfg454_cn52xx cn63xx;
1578 struct cvmx_pciercx_cfg454_cn52xx cn63xxp1;
1579 struct cvmx_pciercx_cfg454_cn61xx cn66xx;
1580 struct cvmx_pciercx_cfg454_cn61xx cn68xx;
1581 struct cvmx_pciercx_cfg454_cn52xx cn68xxp1;
1197}; 1582};
1198 1583
1199union cvmx_pciercx_cfg455 { 1584union cvmx_pciercx_cfg455 {
@@ -1223,23 +1608,37 @@ union cvmx_pciercx_cfg455 {
1223 struct cvmx_pciercx_cfg455_s cn52xxp1; 1608 struct cvmx_pciercx_cfg455_s cn52xxp1;
1224 struct cvmx_pciercx_cfg455_s cn56xx; 1609 struct cvmx_pciercx_cfg455_s cn56xx;
1225 struct cvmx_pciercx_cfg455_s cn56xxp1; 1610 struct cvmx_pciercx_cfg455_s cn56xxp1;
1611 struct cvmx_pciercx_cfg455_s cn61xx;
1226 struct cvmx_pciercx_cfg455_s cn63xx; 1612 struct cvmx_pciercx_cfg455_s cn63xx;
1227 struct cvmx_pciercx_cfg455_s cn63xxp1; 1613 struct cvmx_pciercx_cfg455_s cn63xxp1;
1614 struct cvmx_pciercx_cfg455_s cn66xx;
1615 struct cvmx_pciercx_cfg455_s cn68xx;
1616 struct cvmx_pciercx_cfg455_s cn68xxp1;
1228}; 1617};
1229 1618
1230union cvmx_pciercx_cfg456 { 1619union cvmx_pciercx_cfg456 {
1231 uint32_t u32; 1620 uint32_t u32;
1232 struct cvmx_pciercx_cfg456_s { 1621 struct cvmx_pciercx_cfg456_s {
1233 uint32_t reserved_2_31:30; 1622 uint32_t reserved_4_31:28;
1623 uint32_t m_handle_flush:1;
1624 uint32_t m_dabort_4ucpl:1;
1234 uint32_t m_vend1_drp:1; 1625 uint32_t m_vend1_drp:1;
1235 uint32_t m_vend0_drp:1; 1626 uint32_t m_vend0_drp:1;
1236 } s; 1627 } s;
1237 struct cvmx_pciercx_cfg456_s cn52xx; 1628 struct cvmx_pciercx_cfg456_cn52xx {
1238 struct cvmx_pciercx_cfg456_s cn52xxp1; 1629 uint32_t reserved_2_31:30;
1239 struct cvmx_pciercx_cfg456_s cn56xx; 1630 uint32_t m_vend1_drp:1;
1240 struct cvmx_pciercx_cfg456_s cn56xxp1; 1631 uint32_t m_vend0_drp:1;
1241 struct cvmx_pciercx_cfg456_s cn63xx; 1632 } cn52xx;
1242 struct cvmx_pciercx_cfg456_s cn63xxp1; 1633 struct cvmx_pciercx_cfg456_cn52xx cn52xxp1;
1634 struct cvmx_pciercx_cfg456_cn52xx cn56xx;
1635 struct cvmx_pciercx_cfg456_cn52xx cn56xxp1;
1636 struct cvmx_pciercx_cfg456_s cn61xx;
1637 struct cvmx_pciercx_cfg456_cn52xx cn63xx;
1638 struct cvmx_pciercx_cfg456_cn52xx cn63xxp1;
1639 struct cvmx_pciercx_cfg456_s cn66xx;
1640 struct cvmx_pciercx_cfg456_s cn68xx;
1641 struct cvmx_pciercx_cfg456_cn52xx cn68xxp1;
1243}; 1642};
1244 1643
1245union cvmx_pciercx_cfg458 { 1644union cvmx_pciercx_cfg458 {
@@ -1251,8 +1650,12 @@ union cvmx_pciercx_cfg458 {
1251 struct cvmx_pciercx_cfg458_s cn52xxp1; 1650 struct cvmx_pciercx_cfg458_s cn52xxp1;
1252 struct cvmx_pciercx_cfg458_s cn56xx; 1651 struct cvmx_pciercx_cfg458_s cn56xx;
1253 struct cvmx_pciercx_cfg458_s cn56xxp1; 1652 struct cvmx_pciercx_cfg458_s cn56xxp1;
1653 struct cvmx_pciercx_cfg458_s cn61xx;
1254 struct cvmx_pciercx_cfg458_s cn63xx; 1654 struct cvmx_pciercx_cfg458_s cn63xx;
1255 struct cvmx_pciercx_cfg458_s cn63xxp1; 1655 struct cvmx_pciercx_cfg458_s cn63xxp1;
1656 struct cvmx_pciercx_cfg458_s cn66xx;
1657 struct cvmx_pciercx_cfg458_s cn68xx;
1658 struct cvmx_pciercx_cfg458_s cn68xxp1;
1256}; 1659};
1257 1660
1258union cvmx_pciercx_cfg459 { 1661union cvmx_pciercx_cfg459 {
@@ -1264,8 +1667,12 @@ union cvmx_pciercx_cfg459 {
1264 struct cvmx_pciercx_cfg459_s cn52xxp1; 1667 struct cvmx_pciercx_cfg459_s cn52xxp1;
1265 struct cvmx_pciercx_cfg459_s cn56xx; 1668 struct cvmx_pciercx_cfg459_s cn56xx;
1266 struct cvmx_pciercx_cfg459_s cn56xxp1; 1669 struct cvmx_pciercx_cfg459_s cn56xxp1;
1670 struct cvmx_pciercx_cfg459_s cn61xx;
1267 struct cvmx_pciercx_cfg459_s cn63xx; 1671 struct cvmx_pciercx_cfg459_s cn63xx;
1268 struct cvmx_pciercx_cfg459_s cn63xxp1; 1672 struct cvmx_pciercx_cfg459_s cn63xxp1;
1673 struct cvmx_pciercx_cfg459_s cn66xx;
1674 struct cvmx_pciercx_cfg459_s cn68xx;
1675 struct cvmx_pciercx_cfg459_s cn68xxp1;
1269}; 1676};
1270 1677
1271union cvmx_pciercx_cfg460 { 1678union cvmx_pciercx_cfg460 {
@@ -1279,8 +1686,12 @@ union cvmx_pciercx_cfg460 {
1279 struct cvmx_pciercx_cfg460_s cn52xxp1; 1686 struct cvmx_pciercx_cfg460_s cn52xxp1;
1280 struct cvmx_pciercx_cfg460_s cn56xx; 1687 struct cvmx_pciercx_cfg460_s cn56xx;
1281 struct cvmx_pciercx_cfg460_s cn56xxp1; 1688 struct cvmx_pciercx_cfg460_s cn56xxp1;
1689 struct cvmx_pciercx_cfg460_s cn61xx;
1282 struct cvmx_pciercx_cfg460_s cn63xx; 1690 struct cvmx_pciercx_cfg460_s cn63xx;
1283 struct cvmx_pciercx_cfg460_s cn63xxp1; 1691 struct cvmx_pciercx_cfg460_s cn63xxp1;
1692 struct cvmx_pciercx_cfg460_s cn66xx;
1693 struct cvmx_pciercx_cfg460_s cn68xx;
1694 struct cvmx_pciercx_cfg460_s cn68xxp1;
1284}; 1695};
1285 1696
1286union cvmx_pciercx_cfg461 { 1697union cvmx_pciercx_cfg461 {
@@ -1294,8 +1705,12 @@ union cvmx_pciercx_cfg461 {
1294 struct cvmx_pciercx_cfg461_s cn52xxp1; 1705 struct cvmx_pciercx_cfg461_s cn52xxp1;
1295 struct cvmx_pciercx_cfg461_s cn56xx; 1706 struct cvmx_pciercx_cfg461_s cn56xx;
1296 struct cvmx_pciercx_cfg461_s cn56xxp1; 1707 struct cvmx_pciercx_cfg461_s cn56xxp1;
1708 struct cvmx_pciercx_cfg461_s cn61xx;
1297 struct cvmx_pciercx_cfg461_s cn63xx; 1709 struct cvmx_pciercx_cfg461_s cn63xx;
1298 struct cvmx_pciercx_cfg461_s cn63xxp1; 1710 struct cvmx_pciercx_cfg461_s cn63xxp1;
1711 struct cvmx_pciercx_cfg461_s cn66xx;
1712 struct cvmx_pciercx_cfg461_s cn68xx;
1713 struct cvmx_pciercx_cfg461_s cn68xxp1;
1299}; 1714};
1300 1715
1301union cvmx_pciercx_cfg462 { 1716union cvmx_pciercx_cfg462 {
@@ -1309,8 +1724,12 @@ union cvmx_pciercx_cfg462 {
1309 struct cvmx_pciercx_cfg462_s cn52xxp1; 1724 struct cvmx_pciercx_cfg462_s cn52xxp1;
1310 struct cvmx_pciercx_cfg462_s cn56xx; 1725 struct cvmx_pciercx_cfg462_s cn56xx;
1311 struct cvmx_pciercx_cfg462_s cn56xxp1; 1726 struct cvmx_pciercx_cfg462_s cn56xxp1;
1727 struct cvmx_pciercx_cfg462_s cn61xx;
1312 struct cvmx_pciercx_cfg462_s cn63xx; 1728 struct cvmx_pciercx_cfg462_s cn63xx;
1313 struct cvmx_pciercx_cfg462_s cn63xxp1; 1729 struct cvmx_pciercx_cfg462_s cn63xxp1;
1730 struct cvmx_pciercx_cfg462_s cn66xx;
1731 struct cvmx_pciercx_cfg462_s cn68xx;
1732 struct cvmx_pciercx_cfg462_s cn68xxp1;
1314}; 1733};
1315 1734
1316union cvmx_pciercx_cfg463 { 1735union cvmx_pciercx_cfg463 {
@@ -1325,8 +1744,12 @@ union cvmx_pciercx_cfg463 {
1325 struct cvmx_pciercx_cfg463_s cn52xxp1; 1744 struct cvmx_pciercx_cfg463_s cn52xxp1;
1326 struct cvmx_pciercx_cfg463_s cn56xx; 1745 struct cvmx_pciercx_cfg463_s cn56xx;
1327 struct cvmx_pciercx_cfg463_s cn56xxp1; 1746 struct cvmx_pciercx_cfg463_s cn56xxp1;
1747 struct cvmx_pciercx_cfg463_s cn61xx;
1328 struct cvmx_pciercx_cfg463_s cn63xx; 1748 struct cvmx_pciercx_cfg463_s cn63xx;
1329 struct cvmx_pciercx_cfg463_s cn63xxp1; 1749 struct cvmx_pciercx_cfg463_s cn63xxp1;
1750 struct cvmx_pciercx_cfg463_s cn66xx;
1751 struct cvmx_pciercx_cfg463_s cn68xx;
1752 struct cvmx_pciercx_cfg463_s cn68xxp1;
1330}; 1753};
1331 1754
1332union cvmx_pciercx_cfg464 { 1755union cvmx_pciercx_cfg464 {
@@ -1341,8 +1764,12 @@ union cvmx_pciercx_cfg464 {
1341 struct cvmx_pciercx_cfg464_s cn52xxp1; 1764 struct cvmx_pciercx_cfg464_s cn52xxp1;
1342 struct cvmx_pciercx_cfg464_s cn56xx; 1765 struct cvmx_pciercx_cfg464_s cn56xx;
1343 struct cvmx_pciercx_cfg464_s cn56xxp1; 1766 struct cvmx_pciercx_cfg464_s cn56xxp1;
1767 struct cvmx_pciercx_cfg464_s cn61xx;
1344 struct cvmx_pciercx_cfg464_s cn63xx; 1768 struct cvmx_pciercx_cfg464_s cn63xx;
1345 struct cvmx_pciercx_cfg464_s cn63xxp1; 1769 struct cvmx_pciercx_cfg464_s cn63xxp1;
1770 struct cvmx_pciercx_cfg464_s cn66xx;
1771 struct cvmx_pciercx_cfg464_s cn68xx;
1772 struct cvmx_pciercx_cfg464_s cn68xxp1;
1346}; 1773};
1347 1774
1348union cvmx_pciercx_cfg465 { 1775union cvmx_pciercx_cfg465 {
@@ -1357,8 +1784,12 @@ union cvmx_pciercx_cfg465 {
1357 struct cvmx_pciercx_cfg465_s cn52xxp1; 1784 struct cvmx_pciercx_cfg465_s cn52xxp1;
1358 struct cvmx_pciercx_cfg465_s cn56xx; 1785 struct cvmx_pciercx_cfg465_s cn56xx;
1359 struct cvmx_pciercx_cfg465_s cn56xxp1; 1786 struct cvmx_pciercx_cfg465_s cn56xxp1;
1787 struct cvmx_pciercx_cfg465_s cn61xx;
1360 struct cvmx_pciercx_cfg465_s cn63xx; 1788 struct cvmx_pciercx_cfg465_s cn63xx;
1361 struct cvmx_pciercx_cfg465_s cn63xxp1; 1789 struct cvmx_pciercx_cfg465_s cn63xxp1;
1790 struct cvmx_pciercx_cfg465_s cn66xx;
1791 struct cvmx_pciercx_cfg465_s cn68xx;
1792 struct cvmx_pciercx_cfg465_s cn68xxp1;
1362}; 1793};
1363 1794
1364union cvmx_pciercx_cfg466 { 1795union cvmx_pciercx_cfg466 {
@@ -1376,8 +1807,12 @@ union cvmx_pciercx_cfg466 {
1376 struct cvmx_pciercx_cfg466_s cn52xxp1; 1807 struct cvmx_pciercx_cfg466_s cn52xxp1;
1377 struct cvmx_pciercx_cfg466_s cn56xx; 1808 struct cvmx_pciercx_cfg466_s cn56xx;
1378 struct cvmx_pciercx_cfg466_s cn56xxp1; 1809 struct cvmx_pciercx_cfg466_s cn56xxp1;
1810 struct cvmx_pciercx_cfg466_s cn61xx;
1379 struct cvmx_pciercx_cfg466_s cn63xx; 1811 struct cvmx_pciercx_cfg466_s cn63xx;
1380 struct cvmx_pciercx_cfg466_s cn63xxp1; 1812 struct cvmx_pciercx_cfg466_s cn63xxp1;
1813 struct cvmx_pciercx_cfg466_s cn66xx;
1814 struct cvmx_pciercx_cfg466_s cn68xx;
1815 struct cvmx_pciercx_cfg466_s cn68xxp1;
1381}; 1816};
1382 1817
1383union cvmx_pciercx_cfg467 { 1818union cvmx_pciercx_cfg467 {
@@ -1393,8 +1828,12 @@ union cvmx_pciercx_cfg467 {
1393 struct cvmx_pciercx_cfg467_s cn52xxp1; 1828 struct cvmx_pciercx_cfg467_s cn52xxp1;
1394 struct cvmx_pciercx_cfg467_s cn56xx; 1829 struct cvmx_pciercx_cfg467_s cn56xx;
1395 struct cvmx_pciercx_cfg467_s cn56xxp1; 1830 struct cvmx_pciercx_cfg467_s cn56xxp1;
1831 struct cvmx_pciercx_cfg467_s cn61xx;
1396 struct cvmx_pciercx_cfg467_s cn63xx; 1832 struct cvmx_pciercx_cfg467_s cn63xx;
1397 struct cvmx_pciercx_cfg467_s cn63xxp1; 1833 struct cvmx_pciercx_cfg467_s cn63xxp1;
1834 struct cvmx_pciercx_cfg467_s cn66xx;
1835 struct cvmx_pciercx_cfg467_s cn68xx;
1836 struct cvmx_pciercx_cfg467_s cn68xxp1;
1398}; 1837};
1399 1838
1400union cvmx_pciercx_cfg468 { 1839union cvmx_pciercx_cfg468 {
@@ -1410,8 +1849,12 @@ union cvmx_pciercx_cfg468 {
1410 struct cvmx_pciercx_cfg468_s cn52xxp1; 1849 struct cvmx_pciercx_cfg468_s cn52xxp1;
1411 struct cvmx_pciercx_cfg468_s cn56xx; 1850 struct cvmx_pciercx_cfg468_s cn56xx;
1412 struct cvmx_pciercx_cfg468_s cn56xxp1; 1851 struct cvmx_pciercx_cfg468_s cn56xxp1;
1852 struct cvmx_pciercx_cfg468_s cn61xx;
1413 struct cvmx_pciercx_cfg468_s cn63xx; 1853 struct cvmx_pciercx_cfg468_s cn63xx;
1414 struct cvmx_pciercx_cfg468_s cn63xxp1; 1854 struct cvmx_pciercx_cfg468_s cn63xxp1;
1855 struct cvmx_pciercx_cfg468_s cn66xx;
1856 struct cvmx_pciercx_cfg468_s cn68xx;
1857 struct cvmx_pciercx_cfg468_s cn68xxp1;
1415}; 1858};
1416 1859
1417union cvmx_pciercx_cfg490 { 1860union cvmx_pciercx_cfg490 {
@@ -1426,8 +1869,12 @@ union cvmx_pciercx_cfg490 {
1426 struct cvmx_pciercx_cfg490_s cn52xxp1; 1869 struct cvmx_pciercx_cfg490_s cn52xxp1;
1427 struct cvmx_pciercx_cfg490_s cn56xx; 1870 struct cvmx_pciercx_cfg490_s cn56xx;
1428 struct cvmx_pciercx_cfg490_s cn56xxp1; 1871 struct cvmx_pciercx_cfg490_s cn56xxp1;
1872 struct cvmx_pciercx_cfg490_s cn61xx;
1429 struct cvmx_pciercx_cfg490_s cn63xx; 1873 struct cvmx_pciercx_cfg490_s cn63xx;
1430 struct cvmx_pciercx_cfg490_s cn63xxp1; 1874 struct cvmx_pciercx_cfg490_s cn63xxp1;
1875 struct cvmx_pciercx_cfg490_s cn66xx;
1876 struct cvmx_pciercx_cfg490_s cn68xx;
1877 struct cvmx_pciercx_cfg490_s cn68xxp1;
1431}; 1878};
1432 1879
1433union cvmx_pciercx_cfg491 { 1880union cvmx_pciercx_cfg491 {
@@ -1442,8 +1889,12 @@ union cvmx_pciercx_cfg491 {
1442 struct cvmx_pciercx_cfg491_s cn52xxp1; 1889 struct cvmx_pciercx_cfg491_s cn52xxp1;
1443 struct cvmx_pciercx_cfg491_s cn56xx; 1890 struct cvmx_pciercx_cfg491_s cn56xx;
1444 struct cvmx_pciercx_cfg491_s cn56xxp1; 1891 struct cvmx_pciercx_cfg491_s cn56xxp1;
1892 struct cvmx_pciercx_cfg491_s cn61xx;
1445 struct cvmx_pciercx_cfg491_s cn63xx; 1893 struct cvmx_pciercx_cfg491_s cn63xx;
1446 struct cvmx_pciercx_cfg491_s cn63xxp1; 1894 struct cvmx_pciercx_cfg491_s cn63xxp1;
1895 struct cvmx_pciercx_cfg491_s cn66xx;
1896 struct cvmx_pciercx_cfg491_s cn68xx;
1897 struct cvmx_pciercx_cfg491_s cn68xxp1;
1447}; 1898};
1448 1899
1449union cvmx_pciercx_cfg492 { 1900union cvmx_pciercx_cfg492 {
@@ -1458,8 +1909,12 @@ union cvmx_pciercx_cfg492 {
1458 struct cvmx_pciercx_cfg492_s cn52xxp1; 1909 struct cvmx_pciercx_cfg492_s cn52xxp1;
1459 struct cvmx_pciercx_cfg492_s cn56xx; 1910 struct cvmx_pciercx_cfg492_s cn56xx;
1460 struct cvmx_pciercx_cfg492_s cn56xxp1; 1911 struct cvmx_pciercx_cfg492_s cn56xxp1;
1912 struct cvmx_pciercx_cfg492_s cn61xx;
1461 struct cvmx_pciercx_cfg492_s cn63xx; 1913 struct cvmx_pciercx_cfg492_s cn63xx;
1462 struct cvmx_pciercx_cfg492_s cn63xxp1; 1914 struct cvmx_pciercx_cfg492_s cn63xxp1;
1915 struct cvmx_pciercx_cfg492_s cn66xx;
1916 struct cvmx_pciercx_cfg492_s cn68xx;
1917 struct cvmx_pciercx_cfg492_s cn68xxp1;
1463}; 1918};
1464 1919
1465union cvmx_pciercx_cfg515 { 1920union cvmx_pciercx_cfg515 {
@@ -1473,8 +1928,12 @@ union cvmx_pciercx_cfg515 {
1473 uint32_t le:9; 1928 uint32_t le:9;
1474 uint32_t n_fts:8; 1929 uint32_t n_fts:8;
1475 } s; 1930 } s;
1931 struct cvmx_pciercx_cfg515_s cn61xx;
1476 struct cvmx_pciercx_cfg515_s cn63xx; 1932 struct cvmx_pciercx_cfg515_s cn63xx;
1477 struct cvmx_pciercx_cfg515_s cn63xxp1; 1933 struct cvmx_pciercx_cfg515_s cn63xxp1;
1934 struct cvmx_pciercx_cfg515_s cn66xx;
1935 struct cvmx_pciercx_cfg515_s cn68xx;
1936 struct cvmx_pciercx_cfg515_s cn68xxp1;
1478}; 1937};
1479 1938
1480union cvmx_pciercx_cfg516 { 1939union cvmx_pciercx_cfg516 {
@@ -1486,8 +1945,12 @@ union cvmx_pciercx_cfg516 {
1486 struct cvmx_pciercx_cfg516_s cn52xxp1; 1945 struct cvmx_pciercx_cfg516_s cn52xxp1;
1487 struct cvmx_pciercx_cfg516_s cn56xx; 1946 struct cvmx_pciercx_cfg516_s cn56xx;
1488 struct cvmx_pciercx_cfg516_s cn56xxp1; 1947 struct cvmx_pciercx_cfg516_s cn56xxp1;
1948 struct cvmx_pciercx_cfg516_s cn61xx;
1489 struct cvmx_pciercx_cfg516_s cn63xx; 1949 struct cvmx_pciercx_cfg516_s cn63xx;
1490 struct cvmx_pciercx_cfg516_s cn63xxp1; 1950 struct cvmx_pciercx_cfg516_s cn63xxp1;
1951 struct cvmx_pciercx_cfg516_s cn66xx;
1952 struct cvmx_pciercx_cfg516_s cn68xx;
1953 struct cvmx_pciercx_cfg516_s cn68xxp1;
1491}; 1954};
1492 1955
1493union cvmx_pciercx_cfg517 { 1956union cvmx_pciercx_cfg517 {
@@ -1499,8 +1962,12 @@ union cvmx_pciercx_cfg517 {
1499 struct cvmx_pciercx_cfg517_s cn52xxp1; 1962 struct cvmx_pciercx_cfg517_s cn52xxp1;
1500 struct cvmx_pciercx_cfg517_s cn56xx; 1963 struct cvmx_pciercx_cfg517_s cn56xx;
1501 struct cvmx_pciercx_cfg517_s cn56xxp1; 1964 struct cvmx_pciercx_cfg517_s cn56xxp1;
1965 struct cvmx_pciercx_cfg517_s cn61xx;
1502 struct cvmx_pciercx_cfg517_s cn63xx; 1966 struct cvmx_pciercx_cfg517_s cn63xx;
1503 struct cvmx_pciercx_cfg517_s cn63xxp1; 1967 struct cvmx_pciercx_cfg517_s cn63xxp1;
1968 struct cvmx_pciercx_cfg517_s cn66xx;
1969 struct cvmx_pciercx_cfg517_s cn68xx;
1970 struct cvmx_pciercx_cfg517_s cn68xxp1;
1504}; 1971};
1505 1972
1506#endif 1973#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
new file mode 100644
index 000000000000..d45952df5f5b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h
@@ -0,0 +1,370 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCSX_DEFS_H__
29#define __CVMX_PCSX_DEFS_H__
30
31#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \
32 CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \
34 CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \
36 CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \
38 CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_PCSX_INTX_EN_REG(offset, block_id) \
40 CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_PCSX_INTX_REG(offset, block_id) \
42 CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \
44 CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \
46 CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \
48 CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \
50 CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \
52 CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \
54 CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \
56 CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \
58 CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \
60 CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \
62 CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
63#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \
64 CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
65
66union cvmx_pcsx_anx_adv_reg {
67 uint64_t u64;
68 struct cvmx_pcsx_anx_adv_reg_s {
69 uint64_t reserved_16_63:48;
70 uint64_t np:1;
71 uint64_t reserved_14_14:1;
72 uint64_t rem_flt:2;
73 uint64_t reserved_9_11:3;
74 uint64_t pause:2;
75 uint64_t hfd:1;
76 uint64_t fd:1;
77 uint64_t reserved_0_4:5;
78 } s;
79 struct cvmx_pcsx_anx_adv_reg_s cn52xx;
80 struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
81 struct cvmx_pcsx_anx_adv_reg_s cn56xx;
82 struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
83};
84
85union cvmx_pcsx_anx_ext_st_reg {
86 uint64_t u64;
87 struct cvmx_pcsx_anx_ext_st_reg_s {
88 uint64_t reserved_16_63:48;
89 uint64_t thou_xfd:1;
90 uint64_t thou_xhd:1;
91 uint64_t thou_tfd:1;
92 uint64_t thou_thd:1;
93 uint64_t reserved_0_11:12;
94 } s;
95 struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
96 struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
97 struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
98 struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
99};
100
101union cvmx_pcsx_anx_lp_abil_reg {
102 uint64_t u64;
103 struct cvmx_pcsx_anx_lp_abil_reg_s {
104 uint64_t reserved_16_63:48;
105 uint64_t np:1;
106 uint64_t ack:1;
107 uint64_t rem_flt:2;
108 uint64_t reserved_9_11:3;
109 uint64_t pause:2;
110 uint64_t hfd:1;
111 uint64_t fd:1;
112 uint64_t reserved_0_4:5;
113 } s;
114 struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
115 struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
116 struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
117 struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
118};
119
120union cvmx_pcsx_anx_results_reg {
121 uint64_t u64;
122 struct cvmx_pcsx_anx_results_reg_s {
123 uint64_t reserved_7_63:57;
124 uint64_t pause:2;
125 uint64_t spd:2;
126 uint64_t an_cpt:1;
127 uint64_t dup:1;
128 uint64_t link_ok:1;
129 } s;
130 struct cvmx_pcsx_anx_results_reg_s cn52xx;
131 struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
132 struct cvmx_pcsx_anx_results_reg_s cn56xx;
133 struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
134};
135
136union cvmx_pcsx_intx_en_reg {
137 uint64_t u64;
138 struct cvmx_pcsx_intx_en_reg_s {
139 uint64_t reserved_12_63:52;
140 uint64_t dup:1;
141 uint64_t sync_bad_en:1;
142 uint64_t an_bad_en:1;
143 uint64_t rxlock_en:1;
144 uint64_t rxbad_en:1;
145 uint64_t rxerr_en:1;
146 uint64_t txbad_en:1;
147 uint64_t txfifo_en:1;
148 uint64_t txfifu_en:1;
149 uint64_t an_err_en:1;
150 uint64_t xmit_en:1;
151 uint64_t lnkspd_en:1;
152 } s;
153 struct cvmx_pcsx_intx_en_reg_s cn52xx;
154 struct cvmx_pcsx_intx_en_reg_s cn52xxp1;
155 struct cvmx_pcsx_intx_en_reg_s cn56xx;
156 struct cvmx_pcsx_intx_en_reg_s cn56xxp1;
157};
158
159union cvmx_pcsx_intx_reg {
160 uint64_t u64;
161 struct cvmx_pcsx_intx_reg_s {
162 uint64_t reserved_12_63:52;
163 uint64_t dup:1;
164 uint64_t sync_bad:1;
165 uint64_t an_bad:1;
166 uint64_t rxlock:1;
167 uint64_t rxbad:1;
168 uint64_t rxerr:1;
169 uint64_t txbad:1;
170 uint64_t txfifo:1;
171 uint64_t txfifu:1;
172 uint64_t an_err:1;
173 uint64_t xmit:1;
174 uint64_t lnkspd:1;
175 } s;
176 struct cvmx_pcsx_intx_reg_s cn52xx;
177 struct cvmx_pcsx_intx_reg_s cn52xxp1;
178 struct cvmx_pcsx_intx_reg_s cn56xx;
179 struct cvmx_pcsx_intx_reg_s cn56xxp1;
180};
181
182union cvmx_pcsx_linkx_timer_count_reg {
183 uint64_t u64;
184 struct cvmx_pcsx_linkx_timer_count_reg_s {
185 uint64_t reserved_16_63:48;
186 uint64_t count:16;
187 } s;
188 struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
189 struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
190 struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
191 struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
192};
193
194union cvmx_pcsx_log_anlx_reg {
195 uint64_t u64;
196 struct cvmx_pcsx_log_anlx_reg_s {
197 uint64_t reserved_4_63:60;
198 uint64_t lafifovfl:1;
199 uint64_t la_en:1;
200 uint64_t pkt_sz:2;
201 } s;
202 struct cvmx_pcsx_log_anlx_reg_s cn52xx;
203 struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
204 struct cvmx_pcsx_log_anlx_reg_s cn56xx;
205 struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
206};
207
208union cvmx_pcsx_miscx_ctl_reg {
209 uint64_t u64;
210 struct cvmx_pcsx_miscx_ctl_reg_s {
211 uint64_t reserved_13_63:51;
212 uint64_t sgmii:1;
213 uint64_t gmxeno:1;
214 uint64_t loopbck2:1;
215 uint64_t mac_phy:1;
216 uint64_t mode:1;
217 uint64_t an_ovrd:1;
218 uint64_t samp_pt:7;
219 } s;
220 struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
221 struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
222 struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
223 struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
224};
225
226union cvmx_pcsx_mrx_control_reg {
227 uint64_t u64;
228 struct cvmx_pcsx_mrx_control_reg_s {
229 uint64_t reserved_16_63:48;
230 uint64_t reset:1;
231 uint64_t loopbck1:1;
232 uint64_t spdlsb:1;
233 uint64_t an_en:1;
234 uint64_t pwr_dn:1;
235 uint64_t reserved_10_10:1;
236 uint64_t rst_an:1;
237 uint64_t dup:1;
238 uint64_t coltst:1;
239 uint64_t spdmsb:1;
240 uint64_t uni:1;
241 uint64_t reserved_0_4:5;
242 } s;
243 struct cvmx_pcsx_mrx_control_reg_s cn52xx;
244 struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
245 struct cvmx_pcsx_mrx_control_reg_s cn56xx;
246 struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
247};
248
249union cvmx_pcsx_mrx_status_reg {
250 uint64_t u64;
251 struct cvmx_pcsx_mrx_status_reg_s {
252 uint64_t reserved_16_63:48;
253 uint64_t hun_t4:1;
254 uint64_t hun_xfd:1;
255 uint64_t hun_xhd:1;
256 uint64_t ten_fd:1;
257 uint64_t ten_hd:1;
258 uint64_t hun_t2fd:1;
259 uint64_t hun_t2hd:1;
260 uint64_t ext_st:1;
261 uint64_t reserved_7_7:1;
262 uint64_t prb_sup:1;
263 uint64_t an_cpt:1;
264 uint64_t rm_flt:1;
265 uint64_t an_abil:1;
266 uint64_t lnk_st:1;
267 uint64_t reserved_1_1:1;
268 uint64_t extnd:1;
269 } s;
270 struct cvmx_pcsx_mrx_status_reg_s cn52xx;
271 struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
272 struct cvmx_pcsx_mrx_status_reg_s cn56xx;
273 struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
274};
275
276union cvmx_pcsx_rxx_states_reg {
277 uint64_t u64;
278 struct cvmx_pcsx_rxx_states_reg_s {
279 uint64_t reserved_16_63:48;
280 uint64_t rx_bad:1;
281 uint64_t rx_st:5;
282 uint64_t sync_bad:1;
283 uint64_t sync:4;
284 uint64_t an_bad:1;
285 uint64_t an_st:4;
286 } s;
287 struct cvmx_pcsx_rxx_states_reg_s cn52xx;
288 struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
289 struct cvmx_pcsx_rxx_states_reg_s cn56xx;
290 struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
291};
292
293union cvmx_pcsx_rxx_sync_reg {
294 uint64_t u64;
295 struct cvmx_pcsx_rxx_sync_reg_s {
296 uint64_t reserved_2_63:62;
297 uint64_t sync:1;
298 uint64_t bit_lock:1;
299 } s;
300 struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
301 struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
302 struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
303 struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
304};
305
306union cvmx_pcsx_sgmx_an_adv_reg {
307 uint64_t u64;
308 struct cvmx_pcsx_sgmx_an_adv_reg_s {
309 uint64_t reserved_16_63:48;
310 uint64_t link:1;
311 uint64_t ack:1;
312 uint64_t reserved_13_13:1;
313 uint64_t dup:1;
314 uint64_t speed:2;
315 uint64_t reserved_1_9:9;
316 uint64_t one:1;
317 } s;
318 struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
319 struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
320 struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
321 struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
322};
323
324union cvmx_pcsx_sgmx_lp_adv_reg {
325 uint64_t u64;
326 struct cvmx_pcsx_sgmx_lp_adv_reg_s {
327 uint64_t reserved_16_63:48;
328 uint64_t link:1;
329 uint64_t reserved_13_14:2;
330 uint64_t dup:1;
331 uint64_t speed:2;
332 uint64_t reserved_1_9:9;
333 uint64_t one:1;
334 } s;
335 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
336 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
337 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
338 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
339};
340
341union cvmx_pcsx_txx_states_reg {
342 uint64_t u64;
343 struct cvmx_pcsx_txx_states_reg_s {
344 uint64_t reserved_7_63:57;
345 uint64_t xmit:2;
346 uint64_t tx_bad:1;
347 uint64_t ord_st:4;
348 } s;
349 struct cvmx_pcsx_txx_states_reg_s cn52xx;
350 struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
351 struct cvmx_pcsx_txx_states_reg_s cn56xx;
352 struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
353};
354
355union cvmx_pcsx_tx_rxx_polarity_reg {
356 uint64_t u64;
357 struct cvmx_pcsx_tx_rxx_polarity_reg_s {
358 uint64_t reserved_4_63:60;
359 uint64_t rxovrd:1;
360 uint64_t autorxpl:1;
361 uint64_t rxplrt:1;
362 uint64_t txplrt:1;
363 } s;
364 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
365 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
366 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
367 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
368};
369
370#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
new file mode 100644
index 000000000000..55d120fe8aed
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pcsxx-defs.h
@@ -0,0 +1,316 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCSXX_DEFS_H__
29#define __CVMX_PCSXX_DEFS_H__
30
31#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \
32 CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_PCSXX_BIST_STATUS_REG(block_id) \
34 CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \
36 CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_PCSXX_CONTROL1_REG(block_id) \
38 CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_PCSXX_CONTROL2_REG(block_id) \
40 CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_PCSXX_INT_EN_REG(block_id) \
42 CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_PCSXX_INT_REG(block_id) \
44 CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_PCSXX_LOG_ANL_REG(block_id) \
46 CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_PCSXX_MISC_CTL_REG(block_id) \
48 CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \
50 CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_PCSXX_SPD_ABIL_REG(block_id) \
52 CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_PCSXX_STATUS1_REG(block_id) \
54 CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_PCSXX_STATUS2_REG(block_id) \
56 CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \
58 CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \
60 CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull))
61
62union cvmx_pcsxx_10gbx_status_reg {
63 uint64_t u64;
64 struct cvmx_pcsxx_10gbx_status_reg_s {
65 uint64_t reserved_13_63:51;
66 uint64_t alignd:1;
67 uint64_t pattst:1;
68 uint64_t reserved_4_10:7;
69 uint64_t l3sync:1;
70 uint64_t l2sync:1;
71 uint64_t l1sync:1;
72 uint64_t l0sync:1;
73 } s;
74 struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
75 struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
76 struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
77 struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
78};
79
80union cvmx_pcsxx_bist_status_reg {
81 uint64_t u64;
82 struct cvmx_pcsxx_bist_status_reg_s {
83 uint64_t reserved_1_63:63;
84 uint64_t bist_status:1;
85 } s;
86 struct cvmx_pcsxx_bist_status_reg_s cn52xx;
87 struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
88 struct cvmx_pcsxx_bist_status_reg_s cn56xx;
89 struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
90};
91
92union cvmx_pcsxx_bit_lock_status_reg {
93 uint64_t u64;
94 struct cvmx_pcsxx_bit_lock_status_reg_s {
95 uint64_t reserved_4_63:60;
96 uint64_t bitlck3:1;
97 uint64_t bitlck2:1;
98 uint64_t bitlck1:1;
99 uint64_t bitlck0:1;
100 } s;
101 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
102 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
103 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
104 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
105};
106
107union cvmx_pcsxx_control1_reg {
108 uint64_t u64;
109 struct cvmx_pcsxx_control1_reg_s {
110 uint64_t reserved_16_63:48;
111 uint64_t reset:1;
112 uint64_t loopbck1:1;
113 uint64_t spdsel1:1;
114 uint64_t reserved_12_12:1;
115 uint64_t lo_pwr:1;
116 uint64_t reserved_7_10:4;
117 uint64_t spdsel0:1;
118 uint64_t spd:4;
119 uint64_t reserved_0_1:2;
120 } s;
121 struct cvmx_pcsxx_control1_reg_s cn52xx;
122 struct cvmx_pcsxx_control1_reg_s cn52xxp1;
123 struct cvmx_pcsxx_control1_reg_s cn56xx;
124 struct cvmx_pcsxx_control1_reg_s cn56xxp1;
125};
126
127union cvmx_pcsxx_control2_reg {
128 uint64_t u64;
129 struct cvmx_pcsxx_control2_reg_s {
130 uint64_t reserved_2_63:62;
131 uint64_t type:2;
132 } s;
133 struct cvmx_pcsxx_control2_reg_s cn52xx;
134 struct cvmx_pcsxx_control2_reg_s cn52xxp1;
135 struct cvmx_pcsxx_control2_reg_s cn56xx;
136 struct cvmx_pcsxx_control2_reg_s cn56xxp1;
137};
138
139union cvmx_pcsxx_int_en_reg {
140 uint64_t u64;
141 struct cvmx_pcsxx_int_en_reg_s {
142 uint64_t reserved_6_63:58;
143 uint64_t algnlos_en:1;
144 uint64_t synlos_en:1;
145 uint64_t bitlckls_en:1;
146 uint64_t rxsynbad_en:1;
147 uint64_t rxbad_en:1;
148 uint64_t txflt_en:1;
149 } s;
150 struct cvmx_pcsxx_int_en_reg_s cn52xx;
151 struct cvmx_pcsxx_int_en_reg_s cn52xxp1;
152 struct cvmx_pcsxx_int_en_reg_s cn56xx;
153 struct cvmx_pcsxx_int_en_reg_s cn56xxp1;
154};
155
156union cvmx_pcsxx_int_reg {
157 uint64_t u64;
158 struct cvmx_pcsxx_int_reg_s {
159 uint64_t reserved_6_63:58;
160 uint64_t algnlos:1;
161 uint64_t synlos:1;
162 uint64_t bitlckls:1;
163 uint64_t rxsynbad:1;
164 uint64_t rxbad:1;
165 uint64_t txflt:1;
166 } s;
167 struct cvmx_pcsxx_int_reg_s cn52xx;
168 struct cvmx_pcsxx_int_reg_s cn52xxp1;
169 struct cvmx_pcsxx_int_reg_s cn56xx;
170 struct cvmx_pcsxx_int_reg_s cn56xxp1;
171};
172
173union cvmx_pcsxx_log_anl_reg {
174 uint64_t u64;
175 struct cvmx_pcsxx_log_anl_reg_s {
176 uint64_t reserved_7_63:57;
177 uint64_t enc_mode:1;
178 uint64_t drop_ln:2;
179 uint64_t lafifovfl:1;
180 uint64_t la_en:1;
181 uint64_t pkt_sz:2;
182 } s;
183 struct cvmx_pcsxx_log_anl_reg_s cn52xx;
184 struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
185 struct cvmx_pcsxx_log_anl_reg_s cn56xx;
186 struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
187};
188
189union cvmx_pcsxx_misc_ctl_reg {
190 uint64_t u64;
191 struct cvmx_pcsxx_misc_ctl_reg_s {
192 uint64_t reserved_4_63:60;
193 uint64_t tx_swap:1;
194 uint64_t rx_swap:1;
195 uint64_t xaui:1;
196 uint64_t gmxeno:1;
197 } s;
198 struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
199 struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
200 struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
201 struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
202};
203
204union cvmx_pcsxx_rx_sync_states_reg {
205 uint64_t u64;
206 struct cvmx_pcsxx_rx_sync_states_reg_s {
207 uint64_t reserved_16_63:48;
208 uint64_t sync3st:4;
209 uint64_t sync2st:4;
210 uint64_t sync1st:4;
211 uint64_t sync0st:4;
212 } s;
213 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
214 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
215 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
216 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
217};
218
219union cvmx_pcsxx_spd_abil_reg {
220 uint64_t u64;
221 struct cvmx_pcsxx_spd_abil_reg_s {
222 uint64_t reserved_2_63:62;
223 uint64_t tenpasst:1;
224 uint64_t tengb:1;
225 } s;
226 struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
227 struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
228 struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
229 struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
230};
231
232union cvmx_pcsxx_status1_reg {
233 uint64_t u64;
234 struct cvmx_pcsxx_status1_reg_s {
235 uint64_t reserved_8_63:56;
236 uint64_t flt:1;
237 uint64_t reserved_3_6:4;
238 uint64_t rcv_lnk:1;
239 uint64_t lpable:1;
240 uint64_t reserved_0_0:1;
241 } s;
242 struct cvmx_pcsxx_status1_reg_s cn52xx;
243 struct cvmx_pcsxx_status1_reg_s cn52xxp1;
244 struct cvmx_pcsxx_status1_reg_s cn56xx;
245 struct cvmx_pcsxx_status1_reg_s cn56xxp1;
246};
247
248union cvmx_pcsxx_status2_reg {
249 uint64_t u64;
250 struct cvmx_pcsxx_status2_reg_s {
251 uint64_t reserved_16_63:48;
252 uint64_t dev:2;
253 uint64_t reserved_12_13:2;
254 uint64_t xmtflt:1;
255 uint64_t rcvflt:1;
256 uint64_t reserved_3_9:7;
257 uint64_t tengb_w:1;
258 uint64_t tengb_x:1;
259 uint64_t tengb_r:1;
260 } s;
261 struct cvmx_pcsxx_status2_reg_s cn52xx;
262 struct cvmx_pcsxx_status2_reg_s cn52xxp1;
263 struct cvmx_pcsxx_status2_reg_s cn56xx;
264 struct cvmx_pcsxx_status2_reg_s cn56xxp1;
265};
266
267union cvmx_pcsxx_tx_rx_polarity_reg {
268 uint64_t u64;
269 struct cvmx_pcsxx_tx_rx_polarity_reg_s {
270 uint64_t reserved_10_63:54;
271 uint64_t xor_rxplrt:4;
272 uint64_t xor_txplrt:4;
273 uint64_t rxplrt:1;
274 uint64_t txplrt:1;
275 } s;
276 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
277 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
278 uint64_t reserved_2_63:62;
279 uint64_t rxplrt:1;
280 uint64_t txplrt:1;
281 } cn52xxp1;
282 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
283 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
284};
285
286union cvmx_pcsxx_tx_rx_states_reg {
287 uint64_t u64;
288 struct cvmx_pcsxx_tx_rx_states_reg_s {
289 uint64_t reserved_14_63:50;
290 uint64_t term_err:1;
291 uint64_t syn3bad:1;
292 uint64_t syn2bad:1;
293 uint64_t syn1bad:1;
294 uint64_t syn0bad:1;
295 uint64_t rxbad:1;
296 uint64_t algn_st:3;
297 uint64_t rx_st:2;
298 uint64_t tx_st:3;
299 } s;
300 struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
301 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
302 uint64_t reserved_13_63:51;
303 uint64_t syn3bad:1;
304 uint64_t syn2bad:1;
305 uint64_t syn1bad:1;
306 uint64_t syn0bad:1;
307 uint64_t rxbad:1;
308 uint64_t algn_st:3;
309 uint64_t rx_st:2;
310 uint64_t tx_st:3;
311 } cn52xxp1;
312 struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
313 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
314};
315
316#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
new file mode 100644
index 000000000000..be189a2585e0
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
@@ -0,0 +1,509 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PEMX_DEFS_H__
29#define __CVMX_PEMX_DEFS_H__
30
31#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
32#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
33#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
34#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
35#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
36#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
37#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
38#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
39#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
40#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
41#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
42#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
43#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
44#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
45#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
46#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
47#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
48#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
49#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
50#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
51#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
52#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
53
54union cvmx_pemx_bar1_indexx {
55 uint64_t u64;
56 struct cvmx_pemx_bar1_indexx_s {
57 uint64_t reserved_20_63:44;
58 uint64_t addr_idx:16;
59 uint64_t ca:1;
60 uint64_t end_swp:2;
61 uint64_t addr_v:1;
62 } s;
63 struct cvmx_pemx_bar1_indexx_s cn61xx;
64 struct cvmx_pemx_bar1_indexx_s cn63xx;
65 struct cvmx_pemx_bar1_indexx_s cn63xxp1;
66 struct cvmx_pemx_bar1_indexx_s cn66xx;
67 struct cvmx_pemx_bar1_indexx_s cn68xx;
68 struct cvmx_pemx_bar1_indexx_s cn68xxp1;
69};
70
71union cvmx_pemx_bar2_mask {
72 uint64_t u64;
73 struct cvmx_pemx_bar2_mask_s {
74 uint64_t reserved_38_63:26;
75 uint64_t mask:35;
76 uint64_t reserved_0_2:3;
77 } s;
78 struct cvmx_pemx_bar2_mask_s cn61xx;
79 struct cvmx_pemx_bar2_mask_s cn66xx;
80 struct cvmx_pemx_bar2_mask_s cn68xx;
81 struct cvmx_pemx_bar2_mask_s cn68xxp1;
82};
83
84union cvmx_pemx_bar_ctl {
85 uint64_t u64;
86 struct cvmx_pemx_bar_ctl_s {
87 uint64_t reserved_7_63:57;
88 uint64_t bar1_siz:3;
89 uint64_t bar2_enb:1;
90 uint64_t bar2_esx:2;
91 uint64_t bar2_cax:1;
92 } s;
93 struct cvmx_pemx_bar_ctl_s cn61xx;
94 struct cvmx_pemx_bar_ctl_s cn63xx;
95 struct cvmx_pemx_bar_ctl_s cn63xxp1;
96 struct cvmx_pemx_bar_ctl_s cn66xx;
97 struct cvmx_pemx_bar_ctl_s cn68xx;
98 struct cvmx_pemx_bar_ctl_s cn68xxp1;
99};
100
101union cvmx_pemx_bist_status {
102 uint64_t u64;
103 struct cvmx_pemx_bist_status_s {
104 uint64_t reserved_8_63:56;
105 uint64_t retry:1;
106 uint64_t rqdata0:1;
107 uint64_t rqdata1:1;
108 uint64_t rqdata2:1;
109 uint64_t rqdata3:1;
110 uint64_t rqhdr1:1;
111 uint64_t rqhdr0:1;
112 uint64_t sot:1;
113 } s;
114 struct cvmx_pemx_bist_status_s cn61xx;
115 struct cvmx_pemx_bist_status_s cn63xx;
116 struct cvmx_pemx_bist_status_s cn63xxp1;
117 struct cvmx_pemx_bist_status_s cn66xx;
118 struct cvmx_pemx_bist_status_s cn68xx;
119 struct cvmx_pemx_bist_status_s cn68xxp1;
120};
121
122union cvmx_pemx_bist_status2 {
123 uint64_t u64;
124 struct cvmx_pemx_bist_status2_s {
125 uint64_t reserved_10_63:54;
126 uint64_t e2p_cpl:1;
127 uint64_t e2p_n:1;
128 uint64_t e2p_p:1;
129 uint64_t peai_p2e:1;
130 uint64_t pef_tpf1:1;
131 uint64_t pef_tpf0:1;
132 uint64_t pef_tnf:1;
133 uint64_t pef_tcf1:1;
134 uint64_t pef_tc0:1;
135 uint64_t ppf:1;
136 } s;
137 struct cvmx_pemx_bist_status2_s cn61xx;
138 struct cvmx_pemx_bist_status2_s cn63xx;
139 struct cvmx_pemx_bist_status2_s cn63xxp1;
140 struct cvmx_pemx_bist_status2_s cn66xx;
141 struct cvmx_pemx_bist_status2_s cn68xx;
142 struct cvmx_pemx_bist_status2_s cn68xxp1;
143};
144
145union cvmx_pemx_cfg_rd {
146 uint64_t u64;
147 struct cvmx_pemx_cfg_rd_s {
148 uint64_t data:32;
149 uint64_t addr:32;
150 } s;
151 struct cvmx_pemx_cfg_rd_s cn61xx;
152 struct cvmx_pemx_cfg_rd_s cn63xx;
153 struct cvmx_pemx_cfg_rd_s cn63xxp1;
154 struct cvmx_pemx_cfg_rd_s cn66xx;
155 struct cvmx_pemx_cfg_rd_s cn68xx;
156 struct cvmx_pemx_cfg_rd_s cn68xxp1;
157};
158
159union cvmx_pemx_cfg_wr {
160 uint64_t u64;
161 struct cvmx_pemx_cfg_wr_s {
162 uint64_t data:32;
163 uint64_t addr:32;
164 } s;
165 struct cvmx_pemx_cfg_wr_s cn61xx;
166 struct cvmx_pemx_cfg_wr_s cn63xx;
167 struct cvmx_pemx_cfg_wr_s cn63xxp1;
168 struct cvmx_pemx_cfg_wr_s cn66xx;
169 struct cvmx_pemx_cfg_wr_s cn68xx;
170 struct cvmx_pemx_cfg_wr_s cn68xxp1;
171};
172
173union cvmx_pemx_cpl_lut_valid {
174 uint64_t u64;
175 struct cvmx_pemx_cpl_lut_valid_s {
176 uint64_t reserved_32_63:32;
177 uint64_t tag:32;
178 } s;
179 struct cvmx_pemx_cpl_lut_valid_s cn61xx;
180 struct cvmx_pemx_cpl_lut_valid_s cn63xx;
181 struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
182 struct cvmx_pemx_cpl_lut_valid_s cn66xx;
183 struct cvmx_pemx_cpl_lut_valid_s cn68xx;
184 struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
185};
186
187union cvmx_pemx_ctl_status {
188 uint64_t u64;
189 struct cvmx_pemx_ctl_status_s {
190 uint64_t reserved_48_63:16;
191 uint64_t auto_sd:1;
192 uint64_t dnum:5;
193 uint64_t pbus:8;
194 uint64_t reserved_32_33:2;
195 uint64_t cfg_rtry:16;
196 uint64_t reserved_12_15:4;
197 uint64_t pm_xtoff:1;
198 uint64_t pm_xpme:1;
199 uint64_t ob_p_cmd:1;
200 uint64_t reserved_7_8:2;
201 uint64_t nf_ecrc:1;
202 uint64_t dly_one:1;
203 uint64_t lnk_enb:1;
204 uint64_t ro_ctlp:1;
205 uint64_t fast_lm:1;
206 uint64_t inv_ecrc:1;
207 uint64_t inv_lcrc:1;
208 } s;
209 struct cvmx_pemx_ctl_status_s cn61xx;
210 struct cvmx_pemx_ctl_status_s cn63xx;
211 struct cvmx_pemx_ctl_status_s cn63xxp1;
212 struct cvmx_pemx_ctl_status_s cn66xx;
213 struct cvmx_pemx_ctl_status_s cn68xx;
214 struct cvmx_pemx_ctl_status_s cn68xxp1;
215};
216
217union cvmx_pemx_dbg_info {
218 uint64_t u64;
219 struct cvmx_pemx_dbg_info_s {
220 uint64_t reserved_31_63:33;
221 uint64_t ecrc_e:1;
222 uint64_t rawwpp:1;
223 uint64_t racpp:1;
224 uint64_t ramtlp:1;
225 uint64_t rarwdns:1;
226 uint64_t caar:1;
227 uint64_t racca:1;
228 uint64_t racur:1;
229 uint64_t rauc:1;
230 uint64_t rqo:1;
231 uint64_t fcuv:1;
232 uint64_t rpe:1;
233 uint64_t fcpvwt:1;
234 uint64_t dpeoosd:1;
235 uint64_t rtwdle:1;
236 uint64_t rdwdle:1;
237 uint64_t mre:1;
238 uint64_t rte:1;
239 uint64_t acto:1;
240 uint64_t rvdm:1;
241 uint64_t rumep:1;
242 uint64_t rptamrc:1;
243 uint64_t rpmerc:1;
244 uint64_t rfemrc:1;
245 uint64_t rnfemrc:1;
246 uint64_t rcemrc:1;
247 uint64_t rpoison:1;
248 uint64_t recrce:1;
249 uint64_t rtlplle:1;
250 uint64_t rtlpmal:1;
251 uint64_t spoison:1;
252 } s;
253 struct cvmx_pemx_dbg_info_s cn61xx;
254 struct cvmx_pemx_dbg_info_s cn63xx;
255 struct cvmx_pemx_dbg_info_s cn63xxp1;
256 struct cvmx_pemx_dbg_info_s cn66xx;
257 struct cvmx_pemx_dbg_info_s cn68xx;
258 struct cvmx_pemx_dbg_info_s cn68xxp1;
259};
260
261union cvmx_pemx_dbg_info_en {
262 uint64_t u64;
263 struct cvmx_pemx_dbg_info_en_s {
264 uint64_t reserved_31_63:33;
265 uint64_t ecrc_e:1;
266 uint64_t rawwpp:1;
267 uint64_t racpp:1;
268 uint64_t ramtlp:1;
269 uint64_t rarwdns:1;
270 uint64_t caar:1;
271 uint64_t racca:1;
272 uint64_t racur:1;
273 uint64_t rauc:1;
274 uint64_t rqo:1;
275 uint64_t fcuv:1;
276 uint64_t rpe:1;
277 uint64_t fcpvwt:1;
278 uint64_t dpeoosd:1;
279 uint64_t rtwdle:1;
280 uint64_t rdwdle:1;
281 uint64_t mre:1;
282 uint64_t rte:1;
283 uint64_t acto:1;
284 uint64_t rvdm:1;
285 uint64_t rumep:1;
286 uint64_t rptamrc:1;
287 uint64_t rpmerc:1;
288 uint64_t rfemrc:1;
289 uint64_t rnfemrc:1;
290 uint64_t rcemrc:1;
291 uint64_t rpoison:1;
292 uint64_t recrce:1;
293 uint64_t rtlplle:1;
294 uint64_t rtlpmal:1;
295 uint64_t spoison:1;
296 } s;
297 struct cvmx_pemx_dbg_info_en_s cn61xx;
298 struct cvmx_pemx_dbg_info_en_s cn63xx;
299 struct cvmx_pemx_dbg_info_en_s cn63xxp1;
300 struct cvmx_pemx_dbg_info_en_s cn66xx;
301 struct cvmx_pemx_dbg_info_en_s cn68xx;
302 struct cvmx_pemx_dbg_info_en_s cn68xxp1;
303};
304
305union cvmx_pemx_diag_status {
306 uint64_t u64;
307 struct cvmx_pemx_diag_status_s {
308 uint64_t reserved_4_63:60;
309 uint64_t pm_dst:1;
310 uint64_t pm_stat:1;
311 uint64_t pm_en:1;
312 uint64_t aux_en:1;
313 } s;
314 struct cvmx_pemx_diag_status_s cn61xx;
315 struct cvmx_pemx_diag_status_s cn63xx;
316 struct cvmx_pemx_diag_status_s cn63xxp1;
317 struct cvmx_pemx_diag_status_s cn66xx;
318 struct cvmx_pemx_diag_status_s cn68xx;
319 struct cvmx_pemx_diag_status_s cn68xxp1;
320};
321
322union cvmx_pemx_inb_read_credits {
323 uint64_t u64;
324 struct cvmx_pemx_inb_read_credits_s {
325 uint64_t reserved_6_63:58;
326 uint64_t num:6;
327 } s;
328 struct cvmx_pemx_inb_read_credits_s cn61xx;
329 struct cvmx_pemx_inb_read_credits_s cn66xx;
330 struct cvmx_pemx_inb_read_credits_s cn68xx;
331};
332
333union cvmx_pemx_int_enb {
334 uint64_t u64;
335 struct cvmx_pemx_int_enb_s {
336 uint64_t reserved_14_63:50;
337 uint64_t crs_dr:1;
338 uint64_t crs_er:1;
339 uint64_t rdlk:1;
340 uint64_t exc:1;
341 uint64_t un_bx:1;
342 uint64_t un_b2:1;
343 uint64_t un_b1:1;
344 uint64_t up_bx:1;
345 uint64_t up_b2:1;
346 uint64_t up_b1:1;
347 uint64_t pmem:1;
348 uint64_t pmei:1;
349 uint64_t se:1;
350 uint64_t aeri:1;
351 } s;
352 struct cvmx_pemx_int_enb_s cn61xx;
353 struct cvmx_pemx_int_enb_s cn63xx;
354 struct cvmx_pemx_int_enb_s cn63xxp1;
355 struct cvmx_pemx_int_enb_s cn66xx;
356 struct cvmx_pemx_int_enb_s cn68xx;
357 struct cvmx_pemx_int_enb_s cn68xxp1;
358};
359
360union cvmx_pemx_int_enb_int {
361 uint64_t u64;
362 struct cvmx_pemx_int_enb_int_s {
363 uint64_t reserved_14_63:50;
364 uint64_t crs_dr:1;
365 uint64_t crs_er:1;
366 uint64_t rdlk:1;
367 uint64_t exc:1;
368 uint64_t un_bx:1;
369 uint64_t un_b2:1;
370 uint64_t un_b1:1;
371 uint64_t up_bx:1;
372 uint64_t up_b2:1;
373 uint64_t up_b1:1;
374 uint64_t pmem:1;
375 uint64_t pmei:1;
376 uint64_t se:1;
377 uint64_t aeri:1;
378 } s;
379 struct cvmx_pemx_int_enb_int_s cn61xx;
380 struct cvmx_pemx_int_enb_int_s cn63xx;
381 struct cvmx_pemx_int_enb_int_s cn63xxp1;
382 struct cvmx_pemx_int_enb_int_s cn66xx;
383 struct cvmx_pemx_int_enb_int_s cn68xx;
384 struct cvmx_pemx_int_enb_int_s cn68xxp1;
385};
386
387union cvmx_pemx_int_sum {
388 uint64_t u64;
389 struct cvmx_pemx_int_sum_s {
390 uint64_t reserved_14_63:50;
391 uint64_t crs_dr:1;
392 uint64_t crs_er:1;
393 uint64_t rdlk:1;
394 uint64_t exc:1;
395 uint64_t un_bx:1;
396 uint64_t un_b2:1;
397 uint64_t un_b1:1;
398 uint64_t up_bx:1;
399 uint64_t up_b2:1;
400 uint64_t up_b1:1;
401 uint64_t pmem:1;
402 uint64_t pmei:1;
403 uint64_t se:1;
404 uint64_t aeri:1;
405 } s;
406 struct cvmx_pemx_int_sum_s cn61xx;
407 struct cvmx_pemx_int_sum_s cn63xx;
408 struct cvmx_pemx_int_sum_s cn63xxp1;
409 struct cvmx_pemx_int_sum_s cn66xx;
410 struct cvmx_pemx_int_sum_s cn68xx;
411 struct cvmx_pemx_int_sum_s cn68xxp1;
412};
413
414union cvmx_pemx_p2n_bar0_start {
415 uint64_t u64;
416 struct cvmx_pemx_p2n_bar0_start_s {
417 uint64_t addr:50;
418 uint64_t reserved_0_13:14;
419 } s;
420 struct cvmx_pemx_p2n_bar0_start_s cn61xx;
421 struct cvmx_pemx_p2n_bar0_start_s cn63xx;
422 struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
423 struct cvmx_pemx_p2n_bar0_start_s cn66xx;
424 struct cvmx_pemx_p2n_bar0_start_s cn68xx;
425 struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
426};
427
428union cvmx_pemx_p2n_bar1_start {
429 uint64_t u64;
430 struct cvmx_pemx_p2n_bar1_start_s {
431 uint64_t addr:38;
432 uint64_t reserved_0_25:26;
433 } s;
434 struct cvmx_pemx_p2n_bar1_start_s cn61xx;
435 struct cvmx_pemx_p2n_bar1_start_s cn63xx;
436 struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
437 struct cvmx_pemx_p2n_bar1_start_s cn66xx;
438 struct cvmx_pemx_p2n_bar1_start_s cn68xx;
439 struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
440};
441
442union cvmx_pemx_p2n_bar2_start {
443 uint64_t u64;
444 struct cvmx_pemx_p2n_bar2_start_s {
445 uint64_t addr:23;
446 uint64_t reserved_0_40:41;
447 } s;
448 struct cvmx_pemx_p2n_bar2_start_s cn61xx;
449 struct cvmx_pemx_p2n_bar2_start_s cn63xx;
450 struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
451 struct cvmx_pemx_p2n_bar2_start_s cn66xx;
452 struct cvmx_pemx_p2n_bar2_start_s cn68xx;
453 struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
454};
455
456union cvmx_pemx_p2p_barx_end {
457 uint64_t u64;
458 struct cvmx_pemx_p2p_barx_end_s {
459 uint64_t addr:52;
460 uint64_t reserved_0_11:12;
461 } s;
462 struct cvmx_pemx_p2p_barx_end_s cn63xx;
463 struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
464 struct cvmx_pemx_p2p_barx_end_s cn66xx;
465 struct cvmx_pemx_p2p_barx_end_s cn68xx;
466 struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
467};
468
469union cvmx_pemx_p2p_barx_start {
470 uint64_t u64;
471 struct cvmx_pemx_p2p_barx_start_s {
472 uint64_t addr:52;
473 uint64_t reserved_0_11:12;
474 } s;
475 struct cvmx_pemx_p2p_barx_start_s cn63xx;
476 struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
477 struct cvmx_pemx_p2p_barx_start_s cn66xx;
478 struct cvmx_pemx_p2p_barx_start_s cn68xx;
479 struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
480};
481
482union cvmx_pemx_tlp_credits {
483 uint64_t u64;
484 struct cvmx_pemx_tlp_credits_s {
485 uint64_t reserved_56_63:8;
486 uint64_t peai_ppf:8;
487 uint64_t pem_cpl:8;
488 uint64_t pem_np:8;
489 uint64_t pem_p:8;
490 uint64_t sli_cpl:8;
491 uint64_t sli_np:8;
492 uint64_t sli_p:8;
493 } s;
494 struct cvmx_pemx_tlp_credits_cn61xx {
495 uint64_t reserved_56_63:8;
496 uint64_t peai_ppf:8;
497 uint64_t reserved_24_47:24;
498 uint64_t sli_cpl:8;
499 uint64_t sli_np:8;
500 uint64_t sli_p:8;
501 } cn61xx;
502 struct cvmx_pemx_tlp_credits_s cn63xx;
503 struct cvmx_pemx_tlp_credits_s cn63xxp1;
504 struct cvmx_pemx_tlp_credits_s cn66xx;
505 struct cvmx_pemx_tlp_credits_s cn68xx;
506 struct cvmx_pemx_tlp_credits_s cn68xxp1;
507};
508
509#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index 5ab8679d89af..4438d211988b 100644
--- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2010 Cavium Networks 7 * Copyright (c) 2003-2011 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -25,13 +25,6 @@
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/ 26 ***********************license end**************************************/
27 27
28/**
29 * cvmx-pexp-defs.h
30 *
31 * Configuration and status register (CSR) definitions for
32 * OCTEON PEXP.
33 *
34 */
35#ifndef __CVMX_PEXP_DEFS_H__ 28#ifndef __CVMX_PEXP_DEFS_H__
36#define __CVMX_PEXP_DEFS_H__ 29#define __CVMX_PEXP_DEFS_H__
37 30
@@ -139,7 +132,7 @@
139#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull)) 132#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
140#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull)) 133#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
141#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull)) 134#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
142#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16) 135#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
143#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull)) 136#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
144#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull)) 137#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
145#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull)) 138#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
@@ -152,7 +145,10 @@
152#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull)) 145#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
153#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull)) 146#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
154#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull)) 147#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
148#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
149#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
155#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull)) 150#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
151#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
156#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull)) 152#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
157#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12) 153#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
158#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull)) 154#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
@@ -206,6 +202,7 @@
206#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull)) 202#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
207#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull)) 203#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
208#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull)) 204#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
205#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
209#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull)) 206#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
210#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull)) 207#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
211#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull)) 208#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
@@ -214,12 +211,14 @@
214#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull)) 211#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
215#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull)) 212#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
216#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull)) 213#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
217#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16) 214#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
215#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
218#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull)) 216#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
219#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull)) 217#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
220#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull)) 218#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
221#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull)) 219#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
222#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull)) 220#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
221#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
223#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull)) 222#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
224 223
225#endif 224#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
new file mode 100644
index 000000000000..5a369100ca68
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
@@ -0,0 +1,1267 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PIP_DEFS_H__
29#define __CVMX_PIP_DEFS_H__
30
31/*
32 * Enumeration representing the amount of packet processing
33 * and validation performed by the input hardware.
34 */
35enum cvmx_pip_port_parse_mode {
36 /*
37 * Packet input doesn't perform any processing of the input
38 * packet.
39 */
40 CVMX_PIP_PORT_CFG_MODE_NONE = 0ull,
41 /*
42 * Full packet processing is performed with pointer starting
43 * at the L2 (ethernet MAC) header.
44 */
45 CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,
46 /*
47 * Input packets are assumed to be IP. Results from non IP
48 * packets is undefined. Pointers reference the beginning of
49 * the IP header.
50 */
51 CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull
52};
53
54#define CVMX_PIP_BCK_PRS \
55 CVMX_ADD_IO_SEG(0x00011800A0000038ull)
56#define CVMX_PIP_BIST_STATUS \
57 CVMX_ADD_IO_SEG(0x00011800A0000000ull)
58#define CVMX_PIP_CRC_CTLX(offset) \
59 CVMX_ADD_IO_SEG(0x00011800A0000040ull + (((offset) & 1) * 8))
60#define CVMX_PIP_CRC_IVX(offset) \
61 CVMX_ADD_IO_SEG(0x00011800A0000050ull + (((offset) & 1) * 8))
62#define CVMX_PIP_DEC_IPSECX(offset) \
63 CVMX_ADD_IO_SEG(0x00011800A0000080ull + (((offset) & 3) * 8))
64#define CVMX_PIP_DSA_SRC_GRP \
65 CVMX_ADD_IO_SEG(0x00011800A0000190ull)
66#define CVMX_PIP_DSA_VID_GRP \
67 CVMX_ADD_IO_SEG(0x00011800A0000198ull)
68#define CVMX_PIP_FRM_LEN_CHKX(offset) \
69 CVMX_ADD_IO_SEG(0x00011800A0000180ull + (((offset) & 1) * 8))
70#define CVMX_PIP_GBL_CFG \
71 CVMX_ADD_IO_SEG(0x00011800A0000028ull)
72#define CVMX_PIP_GBL_CTL \
73 CVMX_ADD_IO_SEG(0x00011800A0000020ull)
74#define CVMX_PIP_HG_PRI_QOS \
75 CVMX_ADD_IO_SEG(0x00011800A00001A0ull)
76#define CVMX_PIP_INT_EN \
77 CVMX_ADD_IO_SEG(0x00011800A0000010ull)
78#define CVMX_PIP_INT_REG \
79 CVMX_ADD_IO_SEG(0x00011800A0000008ull)
80#define CVMX_PIP_IP_OFFSET \
81 CVMX_ADD_IO_SEG(0x00011800A0000060ull)
82#define CVMX_PIP_PRT_CFGX(offset) \
83 CVMX_ADD_IO_SEG(0x00011800A0000200ull + (((offset) & 63) * 8))
84#define CVMX_PIP_PRT_TAGX(offset) \
85 CVMX_ADD_IO_SEG(0x00011800A0000400ull + (((offset) & 63) * 8))
86#define CVMX_PIP_QOS_DIFFX(offset) \
87 CVMX_ADD_IO_SEG(0x00011800A0000600ull + (((offset) & 63) * 8))
88#define CVMX_PIP_QOS_VLANX(offset) \
89 CVMX_ADD_IO_SEG(0x00011800A00000C0ull + (((offset) & 7) * 8))
90#define CVMX_PIP_QOS_WATCHX(offset) \
91 CVMX_ADD_IO_SEG(0x00011800A0000100ull + (((offset) & 7) * 8))
92#define CVMX_PIP_RAW_WORD \
93 CVMX_ADD_IO_SEG(0x00011800A00000B0ull)
94#define CVMX_PIP_SFT_RST \
95 CVMX_ADD_IO_SEG(0x00011800A0000030ull)
96#define CVMX_PIP_STAT0_PRTX(offset) \
97 CVMX_ADD_IO_SEG(0x00011800A0000800ull + (((offset) & 63) * 80))
98#define CVMX_PIP_STAT1_PRTX(offset) \
99 CVMX_ADD_IO_SEG(0x00011800A0000808ull + (((offset) & 63) * 80))
100#define CVMX_PIP_STAT2_PRTX(offset) \
101 CVMX_ADD_IO_SEG(0x00011800A0000810ull + (((offset) & 63) * 80))
102#define CVMX_PIP_STAT3_PRTX(offset) \
103 CVMX_ADD_IO_SEG(0x00011800A0000818ull + (((offset) & 63) * 80))
104#define CVMX_PIP_STAT4_PRTX(offset) \
105 CVMX_ADD_IO_SEG(0x00011800A0000820ull + (((offset) & 63) * 80))
106#define CVMX_PIP_STAT5_PRTX(offset) \
107 CVMX_ADD_IO_SEG(0x00011800A0000828ull + (((offset) & 63) * 80))
108#define CVMX_PIP_STAT6_PRTX(offset) \
109 CVMX_ADD_IO_SEG(0x00011800A0000830ull + (((offset) & 63) * 80))
110#define CVMX_PIP_STAT7_PRTX(offset) \
111 CVMX_ADD_IO_SEG(0x00011800A0000838ull + (((offset) & 63) * 80))
112#define CVMX_PIP_STAT8_PRTX(offset) \
113 CVMX_ADD_IO_SEG(0x00011800A0000840ull + (((offset) & 63) * 80))
114#define CVMX_PIP_STAT9_PRTX(offset) \
115 CVMX_ADD_IO_SEG(0x00011800A0000848ull + (((offset) & 63) * 80))
116#define CVMX_PIP_STAT_CTL \
117 CVMX_ADD_IO_SEG(0x00011800A0000018ull)
118#define CVMX_PIP_STAT_INB_ERRSX(offset) \
119 CVMX_ADD_IO_SEG(0x00011800A0001A10ull + (((offset) & 63) * 32))
120#define CVMX_PIP_STAT_INB_OCTSX(offset) \
121 CVMX_ADD_IO_SEG(0x00011800A0001A08ull + (((offset) & 63) * 32))
122#define CVMX_PIP_STAT_INB_PKTSX(offset) \
123 CVMX_ADD_IO_SEG(0x00011800A0001A00ull + (((offset) & 63) * 32))
124#define CVMX_PIP_TAG_INCX(offset) \
125 CVMX_ADD_IO_SEG(0x00011800A0001800ull + (((offset) & 63) * 8))
126#define CVMX_PIP_TAG_MASK \
127 CVMX_ADD_IO_SEG(0x00011800A0000070ull)
128#define CVMX_PIP_TAG_SECRET \
129 CVMX_ADD_IO_SEG(0x00011800A0000068ull)
130#define CVMX_PIP_TODO_ENTRY \
131 CVMX_ADD_IO_SEG(0x00011800A0000078ull)
132
133union cvmx_pip_bck_prs {
134 uint64_t u64;
135 struct cvmx_pip_bck_prs_s {
136 uint64_t bckprs:1;
137 uint64_t reserved_13_62:50;
138 uint64_t hiwater:5;
139 uint64_t reserved_5_7:3;
140 uint64_t lowater:5;
141 } s;
142 struct cvmx_pip_bck_prs_s cn38xx;
143 struct cvmx_pip_bck_prs_s cn38xxp2;
144 struct cvmx_pip_bck_prs_s cn56xx;
145 struct cvmx_pip_bck_prs_s cn56xxp1;
146 struct cvmx_pip_bck_prs_s cn58xx;
147 struct cvmx_pip_bck_prs_s cn58xxp1;
148};
149
150union cvmx_pip_bist_status {
151 uint64_t u64;
152 struct cvmx_pip_bist_status_s {
153 uint64_t reserved_18_63:46;
154 uint64_t bist:18;
155 } s;
156 struct cvmx_pip_bist_status_s cn30xx;
157 struct cvmx_pip_bist_status_s cn31xx;
158 struct cvmx_pip_bist_status_s cn38xx;
159 struct cvmx_pip_bist_status_s cn38xxp2;
160 struct cvmx_pip_bist_status_cn50xx {
161 uint64_t reserved_17_63:47;
162 uint64_t bist:17;
163 } cn50xx;
164 struct cvmx_pip_bist_status_s cn52xx;
165 struct cvmx_pip_bist_status_s cn52xxp1;
166 struct cvmx_pip_bist_status_s cn56xx;
167 struct cvmx_pip_bist_status_s cn56xxp1;
168 struct cvmx_pip_bist_status_s cn58xx;
169 struct cvmx_pip_bist_status_s cn58xxp1;
170};
171
172union cvmx_pip_crc_ctlx {
173 uint64_t u64;
174 struct cvmx_pip_crc_ctlx_s {
175 uint64_t reserved_2_63:62;
176 uint64_t invres:1;
177 uint64_t reflect:1;
178 } s;
179 struct cvmx_pip_crc_ctlx_s cn38xx;
180 struct cvmx_pip_crc_ctlx_s cn38xxp2;
181 struct cvmx_pip_crc_ctlx_s cn58xx;
182 struct cvmx_pip_crc_ctlx_s cn58xxp1;
183};
184
185union cvmx_pip_crc_ivx {
186 uint64_t u64;
187 struct cvmx_pip_crc_ivx_s {
188 uint64_t reserved_32_63:32;
189 uint64_t iv:32;
190 } s;
191 struct cvmx_pip_crc_ivx_s cn38xx;
192 struct cvmx_pip_crc_ivx_s cn38xxp2;
193 struct cvmx_pip_crc_ivx_s cn58xx;
194 struct cvmx_pip_crc_ivx_s cn58xxp1;
195};
196
197union cvmx_pip_dec_ipsecx {
198 uint64_t u64;
199 struct cvmx_pip_dec_ipsecx_s {
200 uint64_t reserved_18_63:46;
201 uint64_t tcp:1;
202 uint64_t udp:1;
203 uint64_t dprt:16;
204 } s;
205 struct cvmx_pip_dec_ipsecx_s cn30xx;
206 struct cvmx_pip_dec_ipsecx_s cn31xx;
207 struct cvmx_pip_dec_ipsecx_s cn38xx;
208 struct cvmx_pip_dec_ipsecx_s cn38xxp2;
209 struct cvmx_pip_dec_ipsecx_s cn50xx;
210 struct cvmx_pip_dec_ipsecx_s cn52xx;
211 struct cvmx_pip_dec_ipsecx_s cn52xxp1;
212 struct cvmx_pip_dec_ipsecx_s cn56xx;
213 struct cvmx_pip_dec_ipsecx_s cn56xxp1;
214 struct cvmx_pip_dec_ipsecx_s cn58xx;
215 struct cvmx_pip_dec_ipsecx_s cn58xxp1;
216};
217
218union cvmx_pip_dsa_src_grp {
219 uint64_t u64;
220 struct cvmx_pip_dsa_src_grp_s {
221 uint64_t map15:4;
222 uint64_t map14:4;
223 uint64_t map13:4;
224 uint64_t map12:4;
225 uint64_t map11:4;
226 uint64_t map10:4;
227 uint64_t map9:4;
228 uint64_t map8:4;
229 uint64_t map7:4;
230 uint64_t map6:4;
231 uint64_t map5:4;
232 uint64_t map4:4;
233 uint64_t map3:4;
234 uint64_t map2:4;
235 uint64_t map1:4;
236 uint64_t map0:4;
237 } s;
238 struct cvmx_pip_dsa_src_grp_s cn52xx;
239 struct cvmx_pip_dsa_src_grp_s cn52xxp1;
240 struct cvmx_pip_dsa_src_grp_s cn56xx;
241};
242
243union cvmx_pip_dsa_vid_grp {
244 uint64_t u64;
245 struct cvmx_pip_dsa_vid_grp_s {
246 uint64_t map15:4;
247 uint64_t map14:4;
248 uint64_t map13:4;
249 uint64_t map12:4;
250 uint64_t map11:4;
251 uint64_t map10:4;
252 uint64_t map9:4;
253 uint64_t map8:4;
254 uint64_t map7:4;
255 uint64_t map6:4;
256 uint64_t map5:4;
257 uint64_t map4:4;
258 uint64_t map3:4;
259 uint64_t map2:4;
260 uint64_t map1:4;
261 uint64_t map0:4;
262 } s;
263 struct cvmx_pip_dsa_vid_grp_s cn52xx;
264 struct cvmx_pip_dsa_vid_grp_s cn52xxp1;
265 struct cvmx_pip_dsa_vid_grp_s cn56xx;
266};
267
268union cvmx_pip_frm_len_chkx {
269 uint64_t u64;
270 struct cvmx_pip_frm_len_chkx_s {
271 uint64_t reserved_32_63:32;
272 uint64_t maxlen:16;
273 uint64_t minlen:16;
274 } s;
275 struct cvmx_pip_frm_len_chkx_s cn50xx;
276 struct cvmx_pip_frm_len_chkx_s cn52xx;
277 struct cvmx_pip_frm_len_chkx_s cn52xxp1;
278 struct cvmx_pip_frm_len_chkx_s cn56xx;
279 struct cvmx_pip_frm_len_chkx_s cn56xxp1;
280};
281
282union cvmx_pip_gbl_cfg {
283 uint64_t u64;
284 struct cvmx_pip_gbl_cfg_s {
285 uint64_t reserved_19_63:45;
286 uint64_t tag_syn:1;
287 uint64_t ip6_udp:1;
288 uint64_t max_l2:1;
289 uint64_t reserved_11_15:5;
290 uint64_t raw_shf:3;
291 uint64_t reserved_3_7:5;
292 uint64_t nip_shf:3;
293 } s;
294 struct cvmx_pip_gbl_cfg_s cn30xx;
295 struct cvmx_pip_gbl_cfg_s cn31xx;
296 struct cvmx_pip_gbl_cfg_s cn38xx;
297 struct cvmx_pip_gbl_cfg_s cn38xxp2;
298 struct cvmx_pip_gbl_cfg_s cn50xx;
299 struct cvmx_pip_gbl_cfg_s cn52xx;
300 struct cvmx_pip_gbl_cfg_s cn52xxp1;
301 struct cvmx_pip_gbl_cfg_s cn56xx;
302 struct cvmx_pip_gbl_cfg_s cn56xxp1;
303 struct cvmx_pip_gbl_cfg_s cn58xx;
304 struct cvmx_pip_gbl_cfg_s cn58xxp1;
305};
306
307union cvmx_pip_gbl_ctl {
308 uint64_t u64;
309 struct cvmx_pip_gbl_ctl_s {
310 uint64_t reserved_27_63:37;
311 uint64_t dsa_grp_tvid:1;
312 uint64_t dsa_grp_scmd:1;
313 uint64_t dsa_grp_sid:1;
314 uint64_t reserved_21_23:3;
315 uint64_t ring_en:1;
316 uint64_t reserved_17_19:3;
317 uint64_t ignrs:1;
318 uint64_t vs_wqe:1;
319 uint64_t vs_qos:1;
320 uint64_t l2_mal:1;
321 uint64_t tcp_flag:1;
322 uint64_t l4_len:1;
323 uint64_t l4_chk:1;
324 uint64_t l4_prt:1;
325 uint64_t l4_mal:1;
326 uint64_t reserved_6_7:2;
327 uint64_t ip6_eext:2;
328 uint64_t ip4_opts:1;
329 uint64_t ip_hop:1;
330 uint64_t ip_mal:1;
331 uint64_t ip_chk:1;
332 } s;
333 struct cvmx_pip_gbl_ctl_cn30xx {
334 uint64_t reserved_17_63:47;
335 uint64_t ignrs:1;
336 uint64_t vs_wqe:1;
337 uint64_t vs_qos:1;
338 uint64_t l2_mal:1;
339 uint64_t tcp_flag:1;
340 uint64_t l4_len:1;
341 uint64_t l4_chk:1;
342 uint64_t l4_prt:1;
343 uint64_t l4_mal:1;
344 uint64_t reserved_6_7:2;
345 uint64_t ip6_eext:2;
346 uint64_t ip4_opts:1;
347 uint64_t ip_hop:1;
348 uint64_t ip_mal:1;
349 uint64_t ip_chk:1;
350 } cn30xx;
351 struct cvmx_pip_gbl_ctl_cn30xx cn31xx;
352 struct cvmx_pip_gbl_ctl_cn30xx cn38xx;
353 struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2;
354 struct cvmx_pip_gbl_ctl_cn30xx cn50xx;
355 struct cvmx_pip_gbl_ctl_s cn52xx;
356 struct cvmx_pip_gbl_ctl_s cn52xxp1;
357 struct cvmx_pip_gbl_ctl_s cn56xx;
358 struct cvmx_pip_gbl_ctl_cn56xxp1 {
359 uint64_t reserved_21_63:43;
360 uint64_t ring_en:1;
361 uint64_t reserved_17_19:3;
362 uint64_t ignrs:1;
363 uint64_t vs_wqe:1;
364 uint64_t vs_qos:1;
365 uint64_t l2_mal:1;
366 uint64_t tcp_flag:1;
367 uint64_t l4_len:1;
368 uint64_t l4_chk:1;
369 uint64_t l4_prt:1;
370 uint64_t l4_mal:1;
371 uint64_t reserved_6_7:2;
372 uint64_t ip6_eext:2;
373 uint64_t ip4_opts:1;
374 uint64_t ip_hop:1;
375 uint64_t ip_mal:1;
376 uint64_t ip_chk:1;
377 } cn56xxp1;
378 struct cvmx_pip_gbl_ctl_cn30xx cn58xx;
379 struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1;
380};
381
382union cvmx_pip_hg_pri_qos {
383 uint64_t u64;
384 struct cvmx_pip_hg_pri_qos_s {
385 uint64_t reserved_11_63:53;
386 uint64_t qos:3;
387 uint64_t reserved_6_7:2;
388 uint64_t pri:6;
389 } s;
390 struct cvmx_pip_hg_pri_qos_s cn52xx;
391 struct cvmx_pip_hg_pri_qos_s cn52xxp1;
392 struct cvmx_pip_hg_pri_qos_s cn56xx;
393};
394
395union cvmx_pip_int_en {
396 uint64_t u64;
397 struct cvmx_pip_int_en_s {
398 uint64_t reserved_13_63:51;
399 uint64_t punyerr:1;
400 uint64_t lenerr:1;
401 uint64_t maxerr:1;
402 uint64_t minerr:1;
403 uint64_t beperr:1;
404 uint64_t feperr:1;
405 uint64_t todoovr:1;
406 uint64_t skprunt:1;
407 uint64_t badtag:1;
408 uint64_t prtnxa:1;
409 uint64_t bckprs:1;
410 uint64_t crcerr:1;
411 uint64_t pktdrp:1;
412 } s;
413 struct cvmx_pip_int_en_cn30xx {
414 uint64_t reserved_9_63:55;
415 uint64_t beperr:1;
416 uint64_t feperr:1;
417 uint64_t todoovr:1;
418 uint64_t skprunt:1;
419 uint64_t badtag:1;
420 uint64_t prtnxa:1;
421 uint64_t bckprs:1;
422 uint64_t crcerr:1;
423 uint64_t pktdrp:1;
424 } cn30xx;
425 struct cvmx_pip_int_en_cn30xx cn31xx;
426 struct cvmx_pip_int_en_cn30xx cn38xx;
427 struct cvmx_pip_int_en_cn30xx cn38xxp2;
428 struct cvmx_pip_int_en_cn50xx {
429 uint64_t reserved_12_63:52;
430 uint64_t lenerr:1;
431 uint64_t maxerr:1;
432 uint64_t minerr:1;
433 uint64_t beperr:1;
434 uint64_t feperr:1;
435 uint64_t todoovr:1;
436 uint64_t skprunt:1;
437 uint64_t badtag:1;
438 uint64_t prtnxa:1;
439 uint64_t bckprs:1;
440 uint64_t reserved_1_1:1;
441 uint64_t pktdrp:1;
442 } cn50xx;
443 struct cvmx_pip_int_en_cn52xx {
444 uint64_t reserved_13_63:51;
445 uint64_t punyerr:1;
446 uint64_t lenerr:1;
447 uint64_t maxerr:1;
448 uint64_t minerr:1;
449 uint64_t beperr:1;
450 uint64_t feperr:1;
451 uint64_t todoovr:1;
452 uint64_t skprunt:1;
453 uint64_t badtag:1;
454 uint64_t prtnxa:1;
455 uint64_t bckprs:1;
456 uint64_t reserved_1_1:1;
457 uint64_t pktdrp:1;
458 } cn52xx;
459 struct cvmx_pip_int_en_cn52xx cn52xxp1;
460 struct cvmx_pip_int_en_s cn56xx;
461 struct cvmx_pip_int_en_cn56xxp1 {
462 uint64_t reserved_12_63:52;
463 uint64_t lenerr:1;
464 uint64_t maxerr:1;
465 uint64_t minerr:1;
466 uint64_t beperr:1;
467 uint64_t feperr:1;
468 uint64_t todoovr:1;
469 uint64_t skprunt:1;
470 uint64_t badtag:1;
471 uint64_t prtnxa:1;
472 uint64_t bckprs:1;
473 uint64_t crcerr:1;
474 uint64_t pktdrp:1;
475 } cn56xxp1;
476 struct cvmx_pip_int_en_cn58xx {
477 uint64_t reserved_13_63:51;
478 uint64_t punyerr:1;
479 uint64_t reserved_9_11:3;
480 uint64_t beperr:1;
481 uint64_t feperr:1;
482 uint64_t todoovr:1;
483 uint64_t skprunt:1;
484 uint64_t badtag:1;
485 uint64_t prtnxa:1;
486 uint64_t bckprs:1;
487 uint64_t crcerr:1;
488 uint64_t pktdrp:1;
489 } cn58xx;
490 struct cvmx_pip_int_en_cn30xx cn58xxp1;
491};
492
493union cvmx_pip_int_reg {
494 uint64_t u64;
495 struct cvmx_pip_int_reg_s {
496 uint64_t reserved_13_63:51;
497 uint64_t punyerr:1;
498 uint64_t lenerr:1;
499 uint64_t maxerr:1;
500 uint64_t minerr:1;
501 uint64_t beperr:1;
502 uint64_t feperr:1;
503 uint64_t todoovr:1;
504 uint64_t skprunt:1;
505 uint64_t badtag:1;
506 uint64_t prtnxa:1;
507 uint64_t bckprs:1;
508 uint64_t crcerr:1;
509 uint64_t pktdrp:1;
510 } s;
511 struct cvmx_pip_int_reg_cn30xx {
512 uint64_t reserved_9_63:55;
513 uint64_t beperr:1;
514 uint64_t feperr:1;
515 uint64_t todoovr:1;
516 uint64_t skprunt:1;
517 uint64_t badtag:1;
518 uint64_t prtnxa:1;
519 uint64_t bckprs:1;
520 uint64_t crcerr:1;
521 uint64_t pktdrp:1;
522 } cn30xx;
523 struct cvmx_pip_int_reg_cn30xx cn31xx;
524 struct cvmx_pip_int_reg_cn30xx cn38xx;
525 struct cvmx_pip_int_reg_cn30xx cn38xxp2;
526 struct cvmx_pip_int_reg_cn50xx {
527 uint64_t reserved_12_63:52;
528 uint64_t lenerr:1;
529 uint64_t maxerr:1;
530 uint64_t minerr:1;
531 uint64_t beperr:1;
532 uint64_t feperr:1;
533 uint64_t todoovr:1;
534 uint64_t skprunt:1;
535 uint64_t badtag:1;
536 uint64_t prtnxa:1;
537 uint64_t bckprs:1;
538 uint64_t reserved_1_1:1;
539 uint64_t pktdrp:1;
540 } cn50xx;
541 struct cvmx_pip_int_reg_cn52xx {
542 uint64_t reserved_13_63:51;
543 uint64_t punyerr:1;
544 uint64_t lenerr:1;
545 uint64_t maxerr:1;
546 uint64_t minerr:1;
547 uint64_t beperr:1;
548 uint64_t feperr:1;
549 uint64_t todoovr:1;
550 uint64_t skprunt:1;
551 uint64_t badtag:1;
552 uint64_t prtnxa:1;
553 uint64_t bckprs:1;
554 uint64_t reserved_1_1:1;
555 uint64_t pktdrp:1;
556 } cn52xx;
557 struct cvmx_pip_int_reg_cn52xx cn52xxp1;
558 struct cvmx_pip_int_reg_s cn56xx;
559 struct cvmx_pip_int_reg_cn56xxp1 {
560 uint64_t reserved_12_63:52;
561 uint64_t lenerr:1;
562 uint64_t maxerr:1;
563 uint64_t minerr:1;
564 uint64_t beperr:1;
565 uint64_t feperr:1;
566 uint64_t todoovr:1;
567 uint64_t skprunt:1;
568 uint64_t badtag:1;
569 uint64_t prtnxa:1;
570 uint64_t bckprs:1;
571 uint64_t crcerr:1;
572 uint64_t pktdrp:1;
573 } cn56xxp1;
574 struct cvmx_pip_int_reg_cn58xx {
575 uint64_t reserved_13_63:51;
576 uint64_t punyerr:1;
577 uint64_t reserved_9_11:3;
578 uint64_t beperr:1;
579 uint64_t feperr:1;
580 uint64_t todoovr:1;
581 uint64_t skprunt:1;
582 uint64_t badtag:1;
583 uint64_t prtnxa:1;
584 uint64_t bckprs:1;
585 uint64_t crcerr:1;
586 uint64_t pktdrp:1;
587 } cn58xx;
588 struct cvmx_pip_int_reg_cn30xx cn58xxp1;
589};
590
591union cvmx_pip_ip_offset {
592 uint64_t u64;
593 struct cvmx_pip_ip_offset_s {
594 uint64_t reserved_3_63:61;
595 uint64_t offset:3;
596 } s;
597 struct cvmx_pip_ip_offset_s cn30xx;
598 struct cvmx_pip_ip_offset_s cn31xx;
599 struct cvmx_pip_ip_offset_s cn38xx;
600 struct cvmx_pip_ip_offset_s cn38xxp2;
601 struct cvmx_pip_ip_offset_s cn50xx;
602 struct cvmx_pip_ip_offset_s cn52xx;
603 struct cvmx_pip_ip_offset_s cn52xxp1;
604 struct cvmx_pip_ip_offset_s cn56xx;
605 struct cvmx_pip_ip_offset_s cn56xxp1;
606 struct cvmx_pip_ip_offset_s cn58xx;
607 struct cvmx_pip_ip_offset_s cn58xxp1;
608};
609
610union cvmx_pip_prt_cfgx {
611 uint64_t u64;
612 struct cvmx_pip_prt_cfgx_s {
613 uint64_t reserved_53_63:11;
614 uint64_t pad_len:1;
615 uint64_t vlan_len:1;
616 uint64_t lenerr_en:1;
617 uint64_t maxerr_en:1;
618 uint64_t minerr_en:1;
619 uint64_t grp_wat_47:4;
620 uint64_t qos_wat_47:4;
621 uint64_t reserved_37_39:3;
622 uint64_t rawdrp:1;
623 uint64_t tag_inc:2;
624 uint64_t dyn_rs:1;
625 uint64_t inst_hdr:1;
626 uint64_t grp_wat:4;
627 uint64_t hg_qos:1;
628 uint64_t qos:3;
629 uint64_t qos_wat:4;
630 uint64_t qos_vsel:1;
631 uint64_t qos_vod:1;
632 uint64_t qos_diff:1;
633 uint64_t qos_vlan:1;
634 uint64_t reserved_13_15:3;
635 uint64_t crc_en:1;
636 uint64_t higig_en:1;
637 uint64_t dsa_en:1;
638 uint64_t mode:2;
639 uint64_t reserved_7_7:1;
640 uint64_t skip:7;
641 } s;
642 struct cvmx_pip_prt_cfgx_cn30xx {
643 uint64_t reserved_37_63:27;
644 uint64_t rawdrp:1;
645 uint64_t tag_inc:2;
646 uint64_t dyn_rs:1;
647 uint64_t inst_hdr:1;
648 uint64_t grp_wat:4;
649 uint64_t reserved_27_27:1;
650 uint64_t qos:3;
651 uint64_t qos_wat:4;
652 uint64_t reserved_18_19:2;
653 uint64_t qos_diff:1;
654 uint64_t qos_vlan:1;
655 uint64_t reserved_10_15:6;
656 uint64_t mode:2;
657 uint64_t reserved_7_7:1;
658 uint64_t skip:7;
659 } cn30xx;
660 struct cvmx_pip_prt_cfgx_cn30xx cn31xx;
661 struct cvmx_pip_prt_cfgx_cn38xx {
662 uint64_t reserved_37_63:27;
663 uint64_t rawdrp:1;
664 uint64_t tag_inc:2;
665 uint64_t dyn_rs:1;
666 uint64_t inst_hdr:1;
667 uint64_t grp_wat:4;
668 uint64_t reserved_27_27:1;
669 uint64_t qos:3;
670 uint64_t qos_wat:4;
671 uint64_t reserved_18_19:2;
672 uint64_t qos_diff:1;
673 uint64_t qos_vlan:1;
674 uint64_t reserved_13_15:3;
675 uint64_t crc_en:1;
676 uint64_t reserved_10_11:2;
677 uint64_t mode:2;
678 uint64_t reserved_7_7:1;
679 uint64_t skip:7;
680 } cn38xx;
681 struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2;
682 struct cvmx_pip_prt_cfgx_cn50xx {
683 uint64_t reserved_53_63:11;
684 uint64_t pad_len:1;
685 uint64_t vlan_len:1;
686 uint64_t lenerr_en:1;
687 uint64_t maxerr_en:1;
688 uint64_t minerr_en:1;
689 uint64_t grp_wat_47:4;
690 uint64_t qos_wat_47:4;
691 uint64_t reserved_37_39:3;
692 uint64_t rawdrp:1;
693 uint64_t tag_inc:2;
694 uint64_t dyn_rs:1;
695 uint64_t inst_hdr:1;
696 uint64_t grp_wat:4;
697 uint64_t reserved_27_27:1;
698 uint64_t qos:3;
699 uint64_t qos_wat:4;
700 uint64_t reserved_19_19:1;
701 uint64_t qos_vod:1;
702 uint64_t qos_diff:1;
703 uint64_t qos_vlan:1;
704 uint64_t reserved_13_15:3;
705 uint64_t crc_en:1;
706 uint64_t reserved_10_11:2;
707 uint64_t mode:2;
708 uint64_t reserved_7_7:1;
709 uint64_t skip:7;
710 } cn50xx;
711 struct cvmx_pip_prt_cfgx_s cn52xx;
712 struct cvmx_pip_prt_cfgx_s cn52xxp1;
713 struct cvmx_pip_prt_cfgx_s cn56xx;
714 struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1;
715 struct cvmx_pip_prt_cfgx_cn58xx {
716 uint64_t reserved_37_63:27;
717 uint64_t rawdrp:1;
718 uint64_t tag_inc:2;
719 uint64_t dyn_rs:1;
720 uint64_t inst_hdr:1;
721 uint64_t grp_wat:4;
722 uint64_t reserved_27_27:1;
723 uint64_t qos:3;
724 uint64_t qos_wat:4;
725 uint64_t reserved_19_19:1;
726 uint64_t qos_vod:1;
727 uint64_t qos_diff:1;
728 uint64_t qos_vlan:1;
729 uint64_t reserved_13_15:3;
730 uint64_t crc_en:1;
731 uint64_t reserved_10_11:2;
732 uint64_t mode:2;
733 uint64_t reserved_7_7:1;
734 uint64_t skip:7;
735 } cn58xx;
736 struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1;
737};
738
739union cvmx_pip_prt_tagx {
740 uint64_t u64;
741 struct cvmx_pip_prt_tagx_s {
742 uint64_t reserved_40_63:24;
743 uint64_t grptagbase:4;
744 uint64_t grptagmask:4;
745 uint64_t grptag:1;
746 uint64_t grptag_mskip:1;
747 uint64_t tag_mode:2;
748 uint64_t inc_vs:2;
749 uint64_t inc_vlan:1;
750 uint64_t inc_prt_flag:1;
751 uint64_t ip6_dprt_flag:1;
752 uint64_t ip4_dprt_flag:1;
753 uint64_t ip6_sprt_flag:1;
754 uint64_t ip4_sprt_flag:1;
755 uint64_t ip6_nxth_flag:1;
756 uint64_t ip4_pctl_flag:1;
757 uint64_t ip6_dst_flag:1;
758 uint64_t ip4_dst_flag:1;
759 uint64_t ip6_src_flag:1;
760 uint64_t ip4_src_flag:1;
761 uint64_t tcp6_tag_type:2;
762 uint64_t tcp4_tag_type:2;
763 uint64_t ip6_tag_type:2;
764 uint64_t ip4_tag_type:2;
765 uint64_t non_tag_type:2;
766 uint64_t grp:4;
767 } s;
768 struct cvmx_pip_prt_tagx_cn30xx {
769 uint64_t reserved_40_63:24;
770 uint64_t grptagbase:4;
771 uint64_t grptagmask:4;
772 uint64_t grptag:1;
773 uint64_t reserved_30_30:1;
774 uint64_t tag_mode:2;
775 uint64_t inc_vs:2;
776 uint64_t inc_vlan:1;
777 uint64_t inc_prt_flag:1;
778 uint64_t ip6_dprt_flag:1;
779 uint64_t ip4_dprt_flag:1;
780 uint64_t ip6_sprt_flag:1;
781 uint64_t ip4_sprt_flag:1;
782 uint64_t ip6_nxth_flag:1;
783 uint64_t ip4_pctl_flag:1;
784 uint64_t ip6_dst_flag:1;
785 uint64_t ip4_dst_flag:1;
786 uint64_t ip6_src_flag:1;
787 uint64_t ip4_src_flag:1;
788 uint64_t tcp6_tag_type:2;
789 uint64_t tcp4_tag_type:2;
790 uint64_t ip6_tag_type:2;
791 uint64_t ip4_tag_type:2;
792 uint64_t non_tag_type:2;
793 uint64_t grp:4;
794 } cn30xx;
795 struct cvmx_pip_prt_tagx_cn30xx cn31xx;
796 struct cvmx_pip_prt_tagx_cn30xx cn38xx;
797 struct cvmx_pip_prt_tagx_cn30xx cn38xxp2;
798 struct cvmx_pip_prt_tagx_s cn50xx;
799 struct cvmx_pip_prt_tagx_s cn52xx;
800 struct cvmx_pip_prt_tagx_s cn52xxp1;
801 struct cvmx_pip_prt_tagx_s cn56xx;
802 struct cvmx_pip_prt_tagx_s cn56xxp1;
803 struct cvmx_pip_prt_tagx_cn30xx cn58xx;
804 struct cvmx_pip_prt_tagx_cn30xx cn58xxp1;
805};
806
807union cvmx_pip_qos_diffx {
808 uint64_t u64;
809 struct cvmx_pip_qos_diffx_s {
810 uint64_t reserved_3_63:61;
811 uint64_t qos:3;
812 } s;
813 struct cvmx_pip_qos_diffx_s cn30xx;
814 struct cvmx_pip_qos_diffx_s cn31xx;
815 struct cvmx_pip_qos_diffx_s cn38xx;
816 struct cvmx_pip_qos_diffx_s cn38xxp2;
817 struct cvmx_pip_qos_diffx_s cn50xx;
818 struct cvmx_pip_qos_diffx_s cn52xx;
819 struct cvmx_pip_qos_diffx_s cn52xxp1;
820 struct cvmx_pip_qos_diffx_s cn56xx;
821 struct cvmx_pip_qos_diffx_s cn56xxp1;
822 struct cvmx_pip_qos_diffx_s cn58xx;
823 struct cvmx_pip_qos_diffx_s cn58xxp1;
824};
825
826union cvmx_pip_qos_vlanx {
827 uint64_t u64;
828 struct cvmx_pip_qos_vlanx_s {
829 uint64_t reserved_7_63:57;
830 uint64_t qos1:3;
831 uint64_t reserved_3_3:1;
832 uint64_t qos:3;
833 } s;
834 struct cvmx_pip_qos_vlanx_cn30xx {
835 uint64_t reserved_3_63:61;
836 uint64_t qos:3;
837 } cn30xx;
838 struct cvmx_pip_qos_vlanx_cn30xx cn31xx;
839 struct cvmx_pip_qos_vlanx_cn30xx cn38xx;
840 struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2;
841 struct cvmx_pip_qos_vlanx_cn30xx cn50xx;
842 struct cvmx_pip_qos_vlanx_s cn52xx;
843 struct cvmx_pip_qos_vlanx_s cn52xxp1;
844 struct cvmx_pip_qos_vlanx_s cn56xx;
845 struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1;
846 struct cvmx_pip_qos_vlanx_cn30xx cn58xx;
847 struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1;
848};
849
850union cvmx_pip_qos_watchx {
851 uint64_t u64;
852 struct cvmx_pip_qos_watchx_s {
853 uint64_t reserved_48_63:16;
854 uint64_t mask:16;
855 uint64_t reserved_28_31:4;
856 uint64_t grp:4;
857 uint64_t reserved_23_23:1;
858 uint64_t qos:3;
859 uint64_t reserved_19_19:1;
860 uint64_t match_type:3;
861 uint64_t match_value:16;
862 } s;
863 struct cvmx_pip_qos_watchx_cn30xx {
864 uint64_t reserved_48_63:16;
865 uint64_t mask:16;
866 uint64_t reserved_28_31:4;
867 uint64_t grp:4;
868 uint64_t reserved_23_23:1;
869 uint64_t qos:3;
870 uint64_t reserved_18_19:2;
871 uint64_t match_type:2;
872 uint64_t match_value:16;
873 } cn30xx;
874 struct cvmx_pip_qos_watchx_cn30xx cn31xx;
875 struct cvmx_pip_qos_watchx_cn30xx cn38xx;
876 struct cvmx_pip_qos_watchx_cn30xx cn38xxp2;
877 struct cvmx_pip_qos_watchx_s cn50xx;
878 struct cvmx_pip_qos_watchx_s cn52xx;
879 struct cvmx_pip_qos_watchx_s cn52xxp1;
880 struct cvmx_pip_qos_watchx_s cn56xx;
881 struct cvmx_pip_qos_watchx_s cn56xxp1;
882 struct cvmx_pip_qos_watchx_cn30xx cn58xx;
883 struct cvmx_pip_qos_watchx_cn30xx cn58xxp1;
884};
885
886union cvmx_pip_raw_word {
887 uint64_t u64;
888 struct cvmx_pip_raw_word_s {
889 uint64_t reserved_56_63:8;
890 uint64_t word:56;
891 } s;
892 struct cvmx_pip_raw_word_s cn30xx;
893 struct cvmx_pip_raw_word_s cn31xx;
894 struct cvmx_pip_raw_word_s cn38xx;
895 struct cvmx_pip_raw_word_s cn38xxp2;
896 struct cvmx_pip_raw_word_s cn50xx;
897 struct cvmx_pip_raw_word_s cn52xx;
898 struct cvmx_pip_raw_word_s cn52xxp1;
899 struct cvmx_pip_raw_word_s cn56xx;
900 struct cvmx_pip_raw_word_s cn56xxp1;
901 struct cvmx_pip_raw_word_s cn58xx;
902 struct cvmx_pip_raw_word_s cn58xxp1;
903};
904
905union cvmx_pip_sft_rst {
906 uint64_t u64;
907 struct cvmx_pip_sft_rst_s {
908 uint64_t reserved_1_63:63;
909 uint64_t rst:1;
910 } s;
911 struct cvmx_pip_sft_rst_s cn30xx;
912 struct cvmx_pip_sft_rst_s cn31xx;
913 struct cvmx_pip_sft_rst_s cn38xx;
914 struct cvmx_pip_sft_rst_s cn50xx;
915 struct cvmx_pip_sft_rst_s cn52xx;
916 struct cvmx_pip_sft_rst_s cn52xxp1;
917 struct cvmx_pip_sft_rst_s cn56xx;
918 struct cvmx_pip_sft_rst_s cn56xxp1;
919 struct cvmx_pip_sft_rst_s cn58xx;
920 struct cvmx_pip_sft_rst_s cn58xxp1;
921};
922
923union cvmx_pip_stat0_prtx {
924 uint64_t u64;
925 struct cvmx_pip_stat0_prtx_s {
926 uint64_t drp_pkts:32;
927 uint64_t drp_octs:32;
928 } s;
929 struct cvmx_pip_stat0_prtx_s cn30xx;
930 struct cvmx_pip_stat0_prtx_s cn31xx;
931 struct cvmx_pip_stat0_prtx_s cn38xx;
932 struct cvmx_pip_stat0_prtx_s cn38xxp2;
933 struct cvmx_pip_stat0_prtx_s cn50xx;
934 struct cvmx_pip_stat0_prtx_s cn52xx;
935 struct cvmx_pip_stat0_prtx_s cn52xxp1;
936 struct cvmx_pip_stat0_prtx_s cn56xx;
937 struct cvmx_pip_stat0_prtx_s cn56xxp1;
938 struct cvmx_pip_stat0_prtx_s cn58xx;
939 struct cvmx_pip_stat0_prtx_s cn58xxp1;
940};
941
942union cvmx_pip_stat1_prtx {
943 uint64_t u64;
944 struct cvmx_pip_stat1_prtx_s {
945 uint64_t reserved_48_63:16;
946 uint64_t octs:48;
947 } s;
948 struct cvmx_pip_stat1_prtx_s cn30xx;
949 struct cvmx_pip_stat1_prtx_s cn31xx;
950 struct cvmx_pip_stat1_prtx_s cn38xx;
951 struct cvmx_pip_stat1_prtx_s cn38xxp2;
952 struct cvmx_pip_stat1_prtx_s cn50xx;
953 struct cvmx_pip_stat1_prtx_s cn52xx;
954 struct cvmx_pip_stat1_prtx_s cn52xxp1;
955 struct cvmx_pip_stat1_prtx_s cn56xx;
956 struct cvmx_pip_stat1_prtx_s cn56xxp1;
957 struct cvmx_pip_stat1_prtx_s cn58xx;
958 struct cvmx_pip_stat1_prtx_s cn58xxp1;
959};
960
961union cvmx_pip_stat2_prtx {
962 uint64_t u64;
963 struct cvmx_pip_stat2_prtx_s {
964 uint64_t pkts:32;
965 uint64_t raw:32;
966 } s;
967 struct cvmx_pip_stat2_prtx_s cn30xx;
968 struct cvmx_pip_stat2_prtx_s cn31xx;
969 struct cvmx_pip_stat2_prtx_s cn38xx;
970 struct cvmx_pip_stat2_prtx_s cn38xxp2;
971 struct cvmx_pip_stat2_prtx_s cn50xx;
972 struct cvmx_pip_stat2_prtx_s cn52xx;
973 struct cvmx_pip_stat2_prtx_s cn52xxp1;
974 struct cvmx_pip_stat2_prtx_s cn56xx;
975 struct cvmx_pip_stat2_prtx_s cn56xxp1;
976 struct cvmx_pip_stat2_prtx_s cn58xx;
977 struct cvmx_pip_stat2_prtx_s cn58xxp1;
978};
979
980union cvmx_pip_stat3_prtx {
981 uint64_t u64;
982 struct cvmx_pip_stat3_prtx_s {
983 uint64_t bcst:32;
984 uint64_t mcst:32;
985 } s;
986 struct cvmx_pip_stat3_prtx_s cn30xx;
987 struct cvmx_pip_stat3_prtx_s cn31xx;
988 struct cvmx_pip_stat3_prtx_s cn38xx;
989 struct cvmx_pip_stat3_prtx_s cn38xxp2;
990 struct cvmx_pip_stat3_prtx_s cn50xx;
991 struct cvmx_pip_stat3_prtx_s cn52xx;
992 struct cvmx_pip_stat3_prtx_s cn52xxp1;
993 struct cvmx_pip_stat3_prtx_s cn56xx;
994 struct cvmx_pip_stat3_prtx_s cn56xxp1;
995 struct cvmx_pip_stat3_prtx_s cn58xx;
996 struct cvmx_pip_stat3_prtx_s cn58xxp1;
997};
998
999union cvmx_pip_stat4_prtx {
1000 uint64_t u64;
1001 struct cvmx_pip_stat4_prtx_s {
1002 uint64_t h65to127:32;
1003 uint64_t h64:32;
1004 } s;
1005 struct cvmx_pip_stat4_prtx_s cn30xx;
1006 struct cvmx_pip_stat4_prtx_s cn31xx;
1007 struct cvmx_pip_stat4_prtx_s cn38xx;
1008 struct cvmx_pip_stat4_prtx_s cn38xxp2;
1009 struct cvmx_pip_stat4_prtx_s cn50xx;
1010 struct cvmx_pip_stat4_prtx_s cn52xx;
1011 struct cvmx_pip_stat4_prtx_s cn52xxp1;
1012 struct cvmx_pip_stat4_prtx_s cn56xx;
1013 struct cvmx_pip_stat4_prtx_s cn56xxp1;
1014 struct cvmx_pip_stat4_prtx_s cn58xx;
1015 struct cvmx_pip_stat4_prtx_s cn58xxp1;
1016};
1017
1018union cvmx_pip_stat5_prtx {
1019 uint64_t u64;
1020 struct cvmx_pip_stat5_prtx_s {
1021 uint64_t h256to511:32;
1022 uint64_t h128to255:32;
1023 } s;
1024 struct cvmx_pip_stat5_prtx_s cn30xx;
1025 struct cvmx_pip_stat5_prtx_s cn31xx;
1026 struct cvmx_pip_stat5_prtx_s cn38xx;
1027 struct cvmx_pip_stat5_prtx_s cn38xxp2;
1028 struct cvmx_pip_stat5_prtx_s cn50xx;
1029 struct cvmx_pip_stat5_prtx_s cn52xx;
1030 struct cvmx_pip_stat5_prtx_s cn52xxp1;
1031 struct cvmx_pip_stat5_prtx_s cn56xx;
1032 struct cvmx_pip_stat5_prtx_s cn56xxp1;
1033 struct cvmx_pip_stat5_prtx_s cn58xx;
1034 struct cvmx_pip_stat5_prtx_s cn58xxp1;
1035};
1036
1037union cvmx_pip_stat6_prtx {
1038 uint64_t u64;
1039 struct cvmx_pip_stat6_prtx_s {
1040 uint64_t h1024to1518:32;
1041 uint64_t h512to1023:32;
1042 } s;
1043 struct cvmx_pip_stat6_prtx_s cn30xx;
1044 struct cvmx_pip_stat6_prtx_s cn31xx;
1045 struct cvmx_pip_stat6_prtx_s cn38xx;
1046 struct cvmx_pip_stat6_prtx_s cn38xxp2;
1047 struct cvmx_pip_stat6_prtx_s cn50xx;
1048 struct cvmx_pip_stat6_prtx_s cn52xx;
1049 struct cvmx_pip_stat6_prtx_s cn52xxp1;
1050 struct cvmx_pip_stat6_prtx_s cn56xx;
1051 struct cvmx_pip_stat6_prtx_s cn56xxp1;
1052 struct cvmx_pip_stat6_prtx_s cn58xx;
1053 struct cvmx_pip_stat6_prtx_s cn58xxp1;
1054};
1055
1056union cvmx_pip_stat7_prtx {
1057 uint64_t u64;
1058 struct cvmx_pip_stat7_prtx_s {
1059 uint64_t fcs:32;
1060 uint64_t h1519:32;
1061 } s;
1062 struct cvmx_pip_stat7_prtx_s cn30xx;
1063 struct cvmx_pip_stat7_prtx_s cn31xx;
1064 struct cvmx_pip_stat7_prtx_s cn38xx;
1065 struct cvmx_pip_stat7_prtx_s cn38xxp2;
1066 struct cvmx_pip_stat7_prtx_s cn50xx;
1067 struct cvmx_pip_stat7_prtx_s cn52xx;
1068 struct cvmx_pip_stat7_prtx_s cn52xxp1;
1069 struct cvmx_pip_stat7_prtx_s cn56xx;
1070 struct cvmx_pip_stat7_prtx_s cn56xxp1;
1071 struct cvmx_pip_stat7_prtx_s cn58xx;
1072 struct cvmx_pip_stat7_prtx_s cn58xxp1;
1073};
1074
1075union cvmx_pip_stat8_prtx {
1076 uint64_t u64;
1077 struct cvmx_pip_stat8_prtx_s {
1078 uint64_t frag:32;
1079 uint64_t undersz:32;
1080 } s;
1081 struct cvmx_pip_stat8_prtx_s cn30xx;
1082 struct cvmx_pip_stat8_prtx_s cn31xx;
1083 struct cvmx_pip_stat8_prtx_s cn38xx;
1084 struct cvmx_pip_stat8_prtx_s cn38xxp2;
1085 struct cvmx_pip_stat8_prtx_s cn50xx;
1086 struct cvmx_pip_stat8_prtx_s cn52xx;
1087 struct cvmx_pip_stat8_prtx_s cn52xxp1;
1088 struct cvmx_pip_stat8_prtx_s cn56xx;
1089 struct cvmx_pip_stat8_prtx_s cn56xxp1;
1090 struct cvmx_pip_stat8_prtx_s cn58xx;
1091 struct cvmx_pip_stat8_prtx_s cn58xxp1;
1092};
1093
1094union cvmx_pip_stat9_prtx {
1095 uint64_t u64;
1096 struct cvmx_pip_stat9_prtx_s {
1097 uint64_t jabber:32;
1098 uint64_t oversz:32;
1099 } s;
1100 struct cvmx_pip_stat9_prtx_s cn30xx;
1101 struct cvmx_pip_stat9_prtx_s cn31xx;
1102 struct cvmx_pip_stat9_prtx_s cn38xx;
1103 struct cvmx_pip_stat9_prtx_s cn38xxp2;
1104 struct cvmx_pip_stat9_prtx_s cn50xx;
1105 struct cvmx_pip_stat9_prtx_s cn52xx;
1106 struct cvmx_pip_stat9_prtx_s cn52xxp1;
1107 struct cvmx_pip_stat9_prtx_s cn56xx;
1108 struct cvmx_pip_stat9_prtx_s cn56xxp1;
1109 struct cvmx_pip_stat9_prtx_s cn58xx;
1110 struct cvmx_pip_stat9_prtx_s cn58xxp1;
1111};
1112
1113union cvmx_pip_stat_ctl {
1114 uint64_t u64;
1115 struct cvmx_pip_stat_ctl_s {
1116 uint64_t reserved_1_63:63;
1117 uint64_t rdclr:1;
1118 } s;
1119 struct cvmx_pip_stat_ctl_s cn30xx;
1120 struct cvmx_pip_stat_ctl_s cn31xx;
1121 struct cvmx_pip_stat_ctl_s cn38xx;
1122 struct cvmx_pip_stat_ctl_s cn38xxp2;
1123 struct cvmx_pip_stat_ctl_s cn50xx;
1124 struct cvmx_pip_stat_ctl_s cn52xx;
1125 struct cvmx_pip_stat_ctl_s cn52xxp1;
1126 struct cvmx_pip_stat_ctl_s cn56xx;
1127 struct cvmx_pip_stat_ctl_s cn56xxp1;
1128 struct cvmx_pip_stat_ctl_s cn58xx;
1129 struct cvmx_pip_stat_ctl_s cn58xxp1;
1130};
1131
1132union cvmx_pip_stat_inb_errsx {
1133 uint64_t u64;
1134 struct cvmx_pip_stat_inb_errsx_s {
1135 uint64_t reserved_16_63:48;
1136 uint64_t errs:16;
1137 } s;
1138 struct cvmx_pip_stat_inb_errsx_s cn30xx;
1139 struct cvmx_pip_stat_inb_errsx_s cn31xx;
1140 struct cvmx_pip_stat_inb_errsx_s cn38xx;
1141 struct cvmx_pip_stat_inb_errsx_s cn38xxp2;
1142 struct cvmx_pip_stat_inb_errsx_s cn50xx;
1143 struct cvmx_pip_stat_inb_errsx_s cn52xx;
1144 struct cvmx_pip_stat_inb_errsx_s cn52xxp1;
1145 struct cvmx_pip_stat_inb_errsx_s cn56xx;
1146 struct cvmx_pip_stat_inb_errsx_s cn56xxp1;
1147 struct cvmx_pip_stat_inb_errsx_s cn58xx;
1148 struct cvmx_pip_stat_inb_errsx_s cn58xxp1;
1149};
1150
1151union cvmx_pip_stat_inb_octsx {
1152 uint64_t u64;
1153 struct cvmx_pip_stat_inb_octsx_s {
1154 uint64_t reserved_48_63:16;
1155 uint64_t octs:48;
1156 } s;
1157 struct cvmx_pip_stat_inb_octsx_s cn30xx;
1158 struct cvmx_pip_stat_inb_octsx_s cn31xx;
1159 struct cvmx_pip_stat_inb_octsx_s cn38xx;
1160 struct cvmx_pip_stat_inb_octsx_s cn38xxp2;
1161 struct cvmx_pip_stat_inb_octsx_s cn50xx;
1162 struct cvmx_pip_stat_inb_octsx_s cn52xx;
1163 struct cvmx_pip_stat_inb_octsx_s cn52xxp1;
1164 struct cvmx_pip_stat_inb_octsx_s cn56xx;
1165 struct cvmx_pip_stat_inb_octsx_s cn56xxp1;
1166 struct cvmx_pip_stat_inb_octsx_s cn58xx;
1167 struct cvmx_pip_stat_inb_octsx_s cn58xxp1;
1168};
1169
1170union cvmx_pip_stat_inb_pktsx {
1171 uint64_t u64;
1172 struct cvmx_pip_stat_inb_pktsx_s {
1173 uint64_t reserved_32_63:32;
1174 uint64_t pkts:32;
1175 } s;
1176 struct cvmx_pip_stat_inb_pktsx_s cn30xx;
1177 struct cvmx_pip_stat_inb_pktsx_s cn31xx;
1178 struct cvmx_pip_stat_inb_pktsx_s cn38xx;
1179 struct cvmx_pip_stat_inb_pktsx_s cn38xxp2;
1180 struct cvmx_pip_stat_inb_pktsx_s cn50xx;
1181 struct cvmx_pip_stat_inb_pktsx_s cn52xx;
1182 struct cvmx_pip_stat_inb_pktsx_s cn52xxp1;
1183 struct cvmx_pip_stat_inb_pktsx_s cn56xx;
1184 struct cvmx_pip_stat_inb_pktsx_s cn56xxp1;
1185 struct cvmx_pip_stat_inb_pktsx_s cn58xx;
1186 struct cvmx_pip_stat_inb_pktsx_s cn58xxp1;
1187};
1188
1189union cvmx_pip_tag_incx {
1190 uint64_t u64;
1191 struct cvmx_pip_tag_incx_s {
1192 uint64_t reserved_8_63:56;
1193 uint64_t en:8;
1194 } s;
1195 struct cvmx_pip_tag_incx_s cn30xx;
1196 struct cvmx_pip_tag_incx_s cn31xx;
1197 struct cvmx_pip_tag_incx_s cn38xx;
1198 struct cvmx_pip_tag_incx_s cn38xxp2;
1199 struct cvmx_pip_tag_incx_s cn50xx;
1200 struct cvmx_pip_tag_incx_s cn52xx;
1201 struct cvmx_pip_tag_incx_s cn52xxp1;
1202 struct cvmx_pip_tag_incx_s cn56xx;
1203 struct cvmx_pip_tag_incx_s cn56xxp1;
1204 struct cvmx_pip_tag_incx_s cn58xx;
1205 struct cvmx_pip_tag_incx_s cn58xxp1;
1206};
1207
1208union cvmx_pip_tag_mask {
1209 uint64_t u64;
1210 struct cvmx_pip_tag_mask_s {
1211 uint64_t reserved_16_63:48;
1212 uint64_t mask:16;
1213 } s;
1214 struct cvmx_pip_tag_mask_s cn30xx;
1215 struct cvmx_pip_tag_mask_s cn31xx;
1216 struct cvmx_pip_tag_mask_s cn38xx;
1217 struct cvmx_pip_tag_mask_s cn38xxp2;
1218 struct cvmx_pip_tag_mask_s cn50xx;
1219 struct cvmx_pip_tag_mask_s cn52xx;
1220 struct cvmx_pip_tag_mask_s cn52xxp1;
1221 struct cvmx_pip_tag_mask_s cn56xx;
1222 struct cvmx_pip_tag_mask_s cn56xxp1;
1223 struct cvmx_pip_tag_mask_s cn58xx;
1224 struct cvmx_pip_tag_mask_s cn58xxp1;
1225};
1226
1227union cvmx_pip_tag_secret {
1228 uint64_t u64;
1229 struct cvmx_pip_tag_secret_s {
1230 uint64_t reserved_32_63:32;
1231 uint64_t dst:16;
1232 uint64_t src:16;
1233 } s;
1234 struct cvmx_pip_tag_secret_s cn30xx;
1235 struct cvmx_pip_tag_secret_s cn31xx;
1236 struct cvmx_pip_tag_secret_s cn38xx;
1237 struct cvmx_pip_tag_secret_s cn38xxp2;
1238 struct cvmx_pip_tag_secret_s cn50xx;
1239 struct cvmx_pip_tag_secret_s cn52xx;
1240 struct cvmx_pip_tag_secret_s cn52xxp1;
1241 struct cvmx_pip_tag_secret_s cn56xx;
1242 struct cvmx_pip_tag_secret_s cn56xxp1;
1243 struct cvmx_pip_tag_secret_s cn58xx;
1244 struct cvmx_pip_tag_secret_s cn58xxp1;
1245};
1246
1247union cvmx_pip_todo_entry {
1248 uint64_t u64;
1249 struct cvmx_pip_todo_entry_s {
1250 uint64_t val:1;
1251 uint64_t reserved_62_62:1;
1252 uint64_t entry:62;
1253 } s;
1254 struct cvmx_pip_todo_entry_s cn30xx;
1255 struct cvmx_pip_todo_entry_s cn31xx;
1256 struct cvmx_pip_todo_entry_s cn38xx;
1257 struct cvmx_pip_todo_entry_s cn38xxp2;
1258 struct cvmx_pip_todo_entry_s cn50xx;
1259 struct cvmx_pip_todo_entry_s cn52xx;
1260 struct cvmx_pip_todo_entry_s cn52xxp1;
1261 struct cvmx_pip_todo_entry_s cn56xx;
1262 struct cvmx_pip_todo_entry_s cn56xxp1;
1263 struct cvmx_pip_todo_entry_s cn58xx;
1264 struct cvmx_pip_todo_entry_s cn58xxp1;
1265};
1266
1267#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h
new file mode 100644
index 000000000000..78dbce8f2c5e
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pip.h
@@ -0,0 +1,524 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Interface to the hardware Packet Input Processing unit.
30 *
31 */
32
33#ifndef __CVMX_PIP_H__
34#define __CVMX_PIP_H__
35
36#include "cvmx-wqe.h"
37#include "cvmx-fpa.h"
38#include "cvmx-pip-defs.h"
39
40#define CVMX_PIP_NUM_INPUT_PORTS 40
41#define CVMX_PIP_NUM_WATCHERS 4
42
43/*
44 * Encodes the different error and exception codes
45 */
46typedef enum {
47 CVMX_PIP_L4_NO_ERR = 0ull,
48 /*
49 * 1 = TCP (UDP) packet not long enough to cover TCP (UDP)
50 * header
51 */
52 CVMX_PIP_L4_MAL_ERR = 1ull,
53 /* 2 = TCP/UDP checksum failure */
54 CVMX_PIP_CHK_ERR = 2ull,
55 /*
56 * 3 = TCP/UDP length check (TCP/UDP length does not match IP
57 * length).
58 */
59 CVMX_PIP_L4_LENGTH_ERR = 3ull,
60 /* 4 = illegal TCP/UDP port (either source or dest port is zero) */
61 CVMX_PIP_BAD_PRT_ERR = 4ull,
62 /* 8 = TCP flags = FIN only */
63 CVMX_PIP_TCP_FLG8_ERR = 8ull,
64 /* 9 = TCP flags = 0 */
65 CVMX_PIP_TCP_FLG9_ERR = 9ull,
66 /* 10 = TCP flags = FIN+RST+* */
67 CVMX_PIP_TCP_FLG10_ERR = 10ull,
68 /* 11 = TCP flags = SYN+URG+* */
69 CVMX_PIP_TCP_FLG11_ERR = 11ull,
70 /* 12 = TCP flags = SYN+RST+* */
71 CVMX_PIP_TCP_FLG12_ERR = 12ull,
72 /* 13 = TCP flags = SYN+FIN+* */
73 CVMX_PIP_TCP_FLG13_ERR = 13ull
74} cvmx_pip_l4_err_t;
75
76typedef enum {
77
78 CVMX_PIP_IP_NO_ERR = 0ull,
79 /* 1 = not IPv4 or IPv6 */
80 CVMX_PIP_NOT_IP = 1ull,
81 /* 2 = IPv4 header checksum violation */
82 CVMX_PIP_IPV4_HDR_CHK = 2ull,
83 /* 3 = malformed (packet not long enough to cover IP hdr) */
84 CVMX_PIP_IP_MAL_HDR = 3ull,
85 /* 4 = malformed (packet not long enough to cover len in IP hdr) */
86 CVMX_PIP_IP_MAL_PKT = 4ull,
87 /* 5 = TTL / hop count equal zero */
88 CVMX_PIP_TTL_HOP = 5ull,
89 /* 6 = IPv4 options / IPv6 early extension headers */
90 CVMX_PIP_OPTS = 6ull
91} cvmx_pip_ip_exc_t;
92
93/**
94 * NOTES
95 * late collision (data received before collision)
96 * late collisions cannot be detected by the receiver
97 * they would appear as JAM bits which would appear as bad FCS
98 * or carrier extend error which is CVMX_PIP_EXTEND_ERR
99 */
100typedef enum {
101 /* No error */
102 CVMX_PIP_RX_NO_ERR = 0ull,
103 /* RGM+SPI 1 = partially received packet (buffering/bandwidth
104 * not adequate) */
105 CVMX_PIP_PARTIAL_ERR = 1ull,
106 /* RGM+SPI 2 = receive packet too large and truncated */
107 CVMX_PIP_JABBER_ERR = 2ull,
108 /*
109 * RGM 3 = max frame error (pkt len > max frame len) (with FCS
110 * error)
111 */
112 CVMX_PIP_OVER_FCS_ERR = 3ull,
113 /* RGM+SPI 4 = max frame error (pkt len > max frame len) */
114 CVMX_PIP_OVER_ERR = 4ull,
115 /*
116 * RGM 5 = nibble error (data not byte multiple - 100M and 10M
117 * only)
118 */
119 CVMX_PIP_ALIGN_ERR = 5ull,
120 /*
121 * RGM 6 = min frame error (pkt len < min frame len) (with FCS
122 * error)
123 */
124 CVMX_PIP_UNDER_FCS_ERR = 6ull,
125 /* RGM 7 = FCS error */
126 CVMX_PIP_GMX_FCS_ERR = 7ull,
127 /* RGM+SPI 8 = min frame error (pkt len < min frame len) */
128 CVMX_PIP_UNDER_ERR = 8ull,
129 /* RGM 9 = Frame carrier extend error */
130 CVMX_PIP_EXTEND_ERR = 9ull,
131 /*
132 * RGM 10 = length mismatch (len did not match len in L2
133 * length/type)
134 */
135 CVMX_PIP_LENGTH_ERR = 10ull,
136 /* RGM 11 = Frame error (some or all data bits marked err) */
137 CVMX_PIP_DAT_ERR = 11ull,
138 /* SPI 11 = DIP4 error */
139 CVMX_PIP_DIP_ERR = 11ull,
140 /*
141 * RGM 12 = packet was not large enough to pass the skipper -
142 * no inspection could occur.
143 */
144 CVMX_PIP_SKIP_ERR = 12ull,
145 /*
146 * RGM 13 = studder error (data not repeated - 100M and 10M
147 * only)
148 */
149 CVMX_PIP_NIBBLE_ERR = 13ull,
150 /* RGM+SPI 16 = FCS error */
151 CVMX_PIP_PIP_FCS = 16L,
152 /*
153 * RGM+SPI+PCI 17 = packet was not large enough to pass the
154 * skipper - no inspection could occur.
155 */
156 CVMX_PIP_PIP_SKIP_ERR = 17L,
157 /*
158 * RGM+SPI+PCI 18 = malformed l2 (packet not long enough to
159 * cover L2 hdr).
160 */
161 CVMX_PIP_PIP_L2_MAL_HDR = 18L
162 /*
163 * NOTES: xx = late collision (data received before collision)
164 * late collisions cannot be detected by the receiver
165 * they would appear as JAM bits which would appear as
166 * bad FCS or carrier extend error which is
167 * CVMX_PIP_EXTEND_ERR
168 */
169} cvmx_pip_rcv_err_t;
170
171/**
172 * This defines the err_code field errors in the work Q entry
173 */
174typedef union {
175 cvmx_pip_l4_err_t l4_err;
176 cvmx_pip_ip_exc_t ip_exc;
177 cvmx_pip_rcv_err_t rcv_err;
178} cvmx_pip_err_t;
179
180/**
181 * Status statistics for a port
182 */
183typedef struct {
184 /* Inbound octets marked to be dropped by the IPD */
185 uint32_t dropped_octets;
186 /* Inbound packets marked to be dropped by the IPD */
187 uint32_t dropped_packets;
188 /* RAW PCI Packets received by PIP per port */
189 uint32_t pci_raw_packets;
190 /* Number of octets processed by PIP */
191 uint32_t octets;
192 /* Number of packets processed by PIP */
193 uint32_t packets;
194 /*
195 * Number of indentified L2 multicast packets. Does not
196 * include broadcast packets. Only includes packets whose
197 * parse mode is SKIP_TO_L2
198 */
199 uint32_t multicast_packets;
200 /*
201 * Number of indentified L2 broadcast packets. Does not
202 * include multicast packets. Only includes packets whose
203 * parse mode is SKIP_TO_L2
204 */
205 uint32_t broadcast_packets;
206 /* Number of 64B packets */
207 uint32_t len_64_packets;
208 /* Number of 65-127B packets */
209 uint32_t len_65_127_packets;
210 /* Number of 128-255B packets */
211 uint32_t len_128_255_packets;
212 /* Number of 256-511B packets */
213 uint32_t len_256_511_packets;
214 /* Number of 512-1023B packets */
215 uint32_t len_512_1023_packets;
216 /* Number of 1024-1518B packets */
217 uint32_t len_1024_1518_packets;
218 /* Number of 1519-max packets */
219 uint32_t len_1519_max_packets;
220 /* Number of packets with FCS or Align opcode errors */
221 uint32_t fcs_align_err_packets;
222 /* Number of packets with length < min */
223 uint32_t runt_packets;
224 /* Number of packets with length < min and FCS error */
225 uint32_t runt_crc_packets;
226 /* Number of packets with length > max */
227 uint32_t oversize_packets;
228 /* Number of packets with length > max and FCS error */
229 uint32_t oversize_crc_packets;
230 /* Number of packets without GMX/SPX/PCI errors received by PIP */
231 uint32_t inb_packets;
232 /*
233 * Total number of octets from all packets received by PIP,
234 * including CRC
235 */
236 uint64_t inb_octets;
237 /* Number of packets with GMX/SPX/PCI errors received by PIP */
238 uint16_t inb_errors;
239} cvmx_pip_port_status_t;
240
241/**
242 * Definition of the PIP custom header that can be prepended
243 * to a packet by external hardware.
244 */
245typedef union {
246 uint64_t u64;
247 struct {
248 /*
249 * Documented as R - Set if the Packet is RAWFULL. If
250 * set, this header must be the full 8 bytes.
251 */
252 uint64_t rawfull:1;
253 /* Must be zero */
254 uint64_t reserved0:5;
255 /* PIP parse mode for this packet */
256 uint64_t parse_mode:2;
257 /* Must be zero */
258 uint64_t reserved1:1;
259 /*
260 * Skip amount, including this header, to the
261 * beginning of the packet
262 */
263 uint64_t skip_len:7;
264 /* Must be zero */
265 uint64_t reserved2:6;
266 /* POW input queue for this packet */
267 uint64_t qos:3;
268 /* POW input group for this packet */
269 uint64_t grp:4;
270 /*
271 * Flag to store this packet in the work queue entry,
272 * if possible
273 */
274 uint64_t rs:1;
275 /* POW input tag type */
276 uint64_t tag_type:2;
277 /* POW input tag */
278 uint64_t tag:32;
279 } s;
280} cvmx_pip_pkt_inst_hdr_t;
281
282/* CSR typedefs have been moved to cvmx-csr-*.h */
283
284/**
285 * Configure an ethernet input port
286 *
287 * @port_num: Port number to configure
288 * @port_cfg: Port hardware configuration
289 * @port_tag_cfg:
290 * Port POW tagging configuration
291 */
292static inline void cvmx_pip_config_port(uint64_t port_num,
293 union cvmx_pip_prt_cfgx port_cfg,
294 union cvmx_pip_prt_tagx port_tag_cfg)
295{
296 cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
297 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
298}
299#if 0
300/**
301 * @deprecated This function is a thin wrapper around the Pass1 version
302 * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
303 * setting the group that is incompatible with this function,
304 * the preferred upgrade path is to use the CSR directly.
305 *
306 * Configure the global QoS packet watchers. Each watcher is
307 * capable of matching a field in a packet to determine the
308 * QoS queue for scheduling.
309 *
310 * @watcher: Watcher number to configure (0 - 3).
311 * @match_type: Watcher match type
312 * @match_value:
313 * Value the watcher will match against
314 * @qos: QoS queue for packets matching this watcher
315 */
316static inline void cvmx_pip_config_watcher(uint64_t watcher,
317 cvmx_pip_qos_watch_types match_type,
318 uint64_t match_value, uint64_t qos)
319{
320 cvmx_pip_port_watcher_cfg_t watcher_config;
321
322 watcher_config.u64 = 0;
323 watcher_config.s.match_type = match_type;
324 watcher_config.s.match_value = match_value;
325 watcher_config.s.qos = qos;
326
327 cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
328}
329#endif
330/**
331 * Configure the VLAN priority to QoS queue mapping.
332 *
333 * @vlan_priority:
334 * VLAN priority (0-7)
335 * @qos: QoS queue for packets matching this watcher
336 */
337static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority,
338 uint64_t qos)
339{
340 union cvmx_pip_qos_vlanx pip_qos_vlanx;
341 pip_qos_vlanx.u64 = 0;
342 pip_qos_vlanx.s.qos = qos;
343 cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
344}
345
346/**
347 * Configure the Diffserv to QoS queue mapping.
348 *
349 * @diffserv: Diffserv field value (0-63)
350 * @qos: QoS queue for packets matching this watcher
351 */
352static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
353{
354 union cvmx_pip_qos_diffx pip_qos_diffx;
355 pip_qos_diffx.u64 = 0;
356 pip_qos_diffx.s.qos = qos;
357 cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
358}
359
360/**
361 * Get the status counters for a port.
362 *
363 * @port_num: Port number to get statistics for.
364 * @clear: Set to 1 to clear the counters after they are read
365 * @status: Where to put the results.
366 */
367static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
368 cvmx_pip_port_status_t *status)
369{
370 union cvmx_pip_stat_ctl pip_stat_ctl;
371 union cvmx_pip_stat0_prtx stat0;
372 union cvmx_pip_stat1_prtx stat1;
373 union cvmx_pip_stat2_prtx stat2;
374 union cvmx_pip_stat3_prtx stat3;
375 union cvmx_pip_stat4_prtx stat4;
376 union cvmx_pip_stat5_prtx stat5;
377 union cvmx_pip_stat6_prtx stat6;
378 union cvmx_pip_stat7_prtx stat7;
379 union cvmx_pip_stat8_prtx stat8;
380 union cvmx_pip_stat9_prtx stat9;
381 union cvmx_pip_stat_inb_pktsx pip_stat_inb_pktsx;
382 union cvmx_pip_stat_inb_octsx pip_stat_inb_octsx;
383 union cvmx_pip_stat_inb_errsx pip_stat_inb_errsx;
384
385 pip_stat_ctl.u64 = 0;
386 pip_stat_ctl.s.rdclr = clear;
387 cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
388
389 stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
390 stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
391 stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
392 stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
393 stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
394 stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
395 stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
396 stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
397 stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
398 stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
399 pip_stat_inb_pktsx.u64 =
400 cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
401 pip_stat_inb_octsx.u64 =
402 cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
403 pip_stat_inb_errsx.u64 =
404 cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
405
406 status->dropped_octets = stat0.s.drp_octs;
407 status->dropped_packets = stat0.s.drp_pkts;
408 status->octets = stat1.s.octs;
409 status->pci_raw_packets = stat2.s.raw;
410 status->packets = stat2.s.pkts;
411 status->multicast_packets = stat3.s.mcst;
412 status->broadcast_packets = stat3.s.bcst;
413 status->len_64_packets = stat4.s.h64;
414 status->len_65_127_packets = stat4.s.h65to127;
415 status->len_128_255_packets = stat5.s.h128to255;
416 status->len_256_511_packets = stat5.s.h256to511;
417 status->len_512_1023_packets = stat6.s.h512to1023;
418 status->len_1024_1518_packets = stat6.s.h1024to1518;
419 status->len_1519_max_packets = stat7.s.h1519;
420 status->fcs_align_err_packets = stat7.s.fcs;
421 status->runt_packets = stat8.s.undersz;
422 status->runt_crc_packets = stat8.s.frag;
423 status->oversize_packets = stat9.s.oversz;
424 status->oversize_crc_packets = stat9.s.jabber;
425 status->inb_packets = pip_stat_inb_pktsx.s.pkts;
426 status->inb_octets = pip_stat_inb_octsx.s.octs;
427 status->inb_errors = pip_stat_inb_errsx.s.errs;
428
429 if (cvmx_octeon_is_pass1()) {
430 /*
431 * Kludge to fix Octeon Pass 1 errata - Drop counts
432 * don't work.
433 */
434 if (status->inb_packets > status->packets)
435 status->dropped_packets =
436 status->inb_packets - status->packets;
437 else
438 status->dropped_packets = 0;
439 if (status->inb_octets - status->inb_packets * 4 >
440 status->octets)
441 status->dropped_octets =
442 status->inb_octets - status->inb_packets * 4 -
443 status->octets;
444 else
445 status->dropped_octets = 0;
446 }
447}
448
449/**
450 * Configure the hardware CRC engine
451 *
452 * @interface: Interface to configure (0 or 1)
453 * @invert_result:
454 * Invert the result of the CRC
455 * @reflect: Reflect
456 * @initialization_vector:
457 * CRC initialization vector
458 */
459static inline void cvmx_pip_config_crc(uint64_t interface,
460 uint64_t invert_result, uint64_t reflect,
461 uint32_t initialization_vector)
462{
463 if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
464 union cvmx_pip_crc_ctlx config;
465 union cvmx_pip_crc_ivx pip_crc_ivx;
466
467 config.u64 = 0;
468 config.s.invres = invert_result;
469 config.s.reflect = reflect;
470 cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);
471
472 pip_crc_ivx.u64 = 0;
473 pip_crc_ivx.s.iv = initialization_vector;
474 cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);
475 }
476}
477
478/**
479 * Clear all bits in a tag mask. This should be called on
480 * startup before any calls to cvmx_pip_tag_mask_set. Each bit
481 * set in the final mask represent a byte used in the packet for
482 * tag generation.
483 *
484 * @mask_index: Which tag mask to clear (0..3)
485 */
486static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
487{
488 uint64_t index;
489 union cvmx_pip_tag_incx pip_tag_incx;
490 pip_tag_incx.u64 = 0;
491 pip_tag_incx.s.en = 0;
492 for (index = mask_index * 16; index < (mask_index + 1) * 16; index++)
493 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
494}
495
496/**
497 * Sets a range of bits in the tag mask. The tag mask is used
498 * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
499 * There are four separate masks that can be configured.
500 *
501 * @mask_index: Which tag mask to modify (0..3)
502 * @offset: Offset into the bitmask to set bits at. Use the GCC macro
503 * offsetof() to determine the offsets into packet headers.
504 * For example, offsetof(ethhdr, protocol) returns the offset
505 * of the ethernet protocol field. The bitmask selects which
506 * bytes to include the the tag, with bit offset X selecting
507 * byte at offset X from the beginning of the packet data.
508 * @len: Number of bytes to include. Usually this is the sizeof()
509 * the field.
510 */
511static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset,
512 uint64_t len)
513{
514 while (len--) {
515 union cvmx_pip_tag_incx pip_tag_incx;
516 uint64_t index = mask_index * 16 + offset / 8;
517 pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));
518 pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
519 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
520 offset++;
521 }
522}
523
524#endif /* __CVMX_PIP_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pko-defs.h b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
new file mode 100644
index 000000000000..50e779cf1ad8
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pko-defs.h
@@ -0,0 +1,1133 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PKO_DEFS_H__
29#define __CVMX_PKO_DEFS_H__
30
31#define CVMX_PKO_MEM_COUNT0 \
32 CVMX_ADD_IO_SEG(0x0001180050001080ull)
33#define CVMX_PKO_MEM_COUNT1 \
34 CVMX_ADD_IO_SEG(0x0001180050001088ull)
35#define CVMX_PKO_MEM_DEBUG0 \
36 CVMX_ADD_IO_SEG(0x0001180050001100ull)
37#define CVMX_PKO_MEM_DEBUG1 \
38 CVMX_ADD_IO_SEG(0x0001180050001108ull)
39#define CVMX_PKO_MEM_DEBUG10 \
40 CVMX_ADD_IO_SEG(0x0001180050001150ull)
41#define CVMX_PKO_MEM_DEBUG11 \
42 CVMX_ADD_IO_SEG(0x0001180050001158ull)
43#define CVMX_PKO_MEM_DEBUG12 \
44 CVMX_ADD_IO_SEG(0x0001180050001160ull)
45#define CVMX_PKO_MEM_DEBUG13 \
46 CVMX_ADD_IO_SEG(0x0001180050001168ull)
47#define CVMX_PKO_MEM_DEBUG14 \
48 CVMX_ADD_IO_SEG(0x0001180050001170ull)
49#define CVMX_PKO_MEM_DEBUG2 \
50 CVMX_ADD_IO_SEG(0x0001180050001110ull)
51#define CVMX_PKO_MEM_DEBUG3 \
52 CVMX_ADD_IO_SEG(0x0001180050001118ull)
53#define CVMX_PKO_MEM_DEBUG4 \
54 CVMX_ADD_IO_SEG(0x0001180050001120ull)
55#define CVMX_PKO_MEM_DEBUG5 \
56 CVMX_ADD_IO_SEG(0x0001180050001128ull)
57#define CVMX_PKO_MEM_DEBUG6 \
58 CVMX_ADD_IO_SEG(0x0001180050001130ull)
59#define CVMX_PKO_MEM_DEBUG7 \
60 CVMX_ADD_IO_SEG(0x0001180050001138ull)
61#define CVMX_PKO_MEM_DEBUG8 \
62 CVMX_ADD_IO_SEG(0x0001180050001140ull)
63#define CVMX_PKO_MEM_DEBUG9 \
64 CVMX_ADD_IO_SEG(0x0001180050001148ull)
65#define CVMX_PKO_MEM_PORT_PTRS \
66 CVMX_ADD_IO_SEG(0x0001180050001010ull)
67#define CVMX_PKO_MEM_PORT_QOS \
68 CVMX_ADD_IO_SEG(0x0001180050001018ull)
69#define CVMX_PKO_MEM_PORT_RATE0 \
70 CVMX_ADD_IO_SEG(0x0001180050001020ull)
71#define CVMX_PKO_MEM_PORT_RATE1 \
72 CVMX_ADD_IO_SEG(0x0001180050001028ull)
73#define CVMX_PKO_MEM_QUEUE_PTRS \
74 CVMX_ADD_IO_SEG(0x0001180050001000ull)
75#define CVMX_PKO_MEM_QUEUE_QOS \
76 CVMX_ADD_IO_SEG(0x0001180050001008ull)
77#define CVMX_PKO_REG_BIST_RESULT \
78 CVMX_ADD_IO_SEG(0x0001180050000080ull)
79#define CVMX_PKO_REG_CMD_BUF \
80 CVMX_ADD_IO_SEG(0x0001180050000010ull)
81#define CVMX_PKO_REG_CRC_CTLX(offset) \
82 CVMX_ADD_IO_SEG(0x0001180050000028ull + (((offset) & 1) * 8))
83#define CVMX_PKO_REG_CRC_ENABLE \
84 CVMX_ADD_IO_SEG(0x0001180050000020ull)
85#define CVMX_PKO_REG_CRC_IVX(offset) \
86 CVMX_ADD_IO_SEG(0x0001180050000038ull + (((offset) & 1) * 8))
87#define CVMX_PKO_REG_DEBUG0 \
88 CVMX_ADD_IO_SEG(0x0001180050000098ull)
89#define CVMX_PKO_REG_DEBUG1 \
90 CVMX_ADD_IO_SEG(0x00011800500000A0ull)
91#define CVMX_PKO_REG_DEBUG2 \
92 CVMX_ADD_IO_SEG(0x00011800500000A8ull)
93#define CVMX_PKO_REG_DEBUG3 \
94 CVMX_ADD_IO_SEG(0x00011800500000B0ull)
95#define CVMX_PKO_REG_ENGINE_INFLIGHT \
96 CVMX_ADD_IO_SEG(0x0001180050000050ull)
97#define CVMX_PKO_REG_ENGINE_THRESH \
98 CVMX_ADD_IO_SEG(0x0001180050000058ull)
99#define CVMX_PKO_REG_ERROR \
100 CVMX_ADD_IO_SEG(0x0001180050000088ull)
101#define CVMX_PKO_REG_FLAGS \
102 CVMX_ADD_IO_SEG(0x0001180050000000ull)
103#define CVMX_PKO_REG_GMX_PORT_MODE \
104 CVMX_ADD_IO_SEG(0x0001180050000018ull)
105#define CVMX_PKO_REG_INT_MASK \
106 CVMX_ADD_IO_SEG(0x0001180050000090ull)
107#define CVMX_PKO_REG_QUEUE_MODE \
108 CVMX_ADD_IO_SEG(0x0001180050000048ull)
109#define CVMX_PKO_REG_QUEUE_PTRS1 \
110 CVMX_ADD_IO_SEG(0x0001180050000100ull)
111#define CVMX_PKO_REG_READ_IDX \
112 CVMX_ADD_IO_SEG(0x0001180050000008ull)
113
114union cvmx_pko_mem_count0 {
115 uint64_t u64;
116 struct cvmx_pko_mem_count0_s {
117 uint64_t reserved_32_63:32;
118 uint64_t count:32;
119 } s;
120 struct cvmx_pko_mem_count0_s cn30xx;
121 struct cvmx_pko_mem_count0_s cn31xx;
122 struct cvmx_pko_mem_count0_s cn38xx;
123 struct cvmx_pko_mem_count0_s cn38xxp2;
124 struct cvmx_pko_mem_count0_s cn50xx;
125 struct cvmx_pko_mem_count0_s cn52xx;
126 struct cvmx_pko_mem_count0_s cn52xxp1;
127 struct cvmx_pko_mem_count0_s cn56xx;
128 struct cvmx_pko_mem_count0_s cn56xxp1;
129 struct cvmx_pko_mem_count0_s cn58xx;
130 struct cvmx_pko_mem_count0_s cn58xxp1;
131};
132
133union cvmx_pko_mem_count1 {
134 uint64_t u64;
135 struct cvmx_pko_mem_count1_s {
136 uint64_t reserved_48_63:16;
137 uint64_t count:48;
138 } s;
139 struct cvmx_pko_mem_count1_s cn30xx;
140 struct cvmx_pko_mem_count1_s cn31xx;
141 struct cvmx_pko_mem_count1_s cn38xx;
142 struct cvmx_pko_mem_count1_s cn38xxp2;
143 struct cvmx_pko_mem_count1_s cn50xx;
144 struct cvmx_pko_mem_count1_s cn52xx;
145 struct cvmx_pko_mem_count1_s cn52xxp1;
146 struct cvmx_pko_mem_count1_s cn56xx;
147 struct cvmx_pko_mem_count1_s cn56xxp1;
148 struct cvmx_pko_mem_count1_s cn58xx;
149 struct cvmx_pko_mem_count1_s cn58xxp1;
150};
151
152union cvmx_pko_mem_debug0 {
153 uint64_t u64;
154 struct cvmx_pko_mem_debug0_s {
155 uint64_t fau:28;
156 uint64_t cmd:14;
157 uint64_t segs:6;
158 uint64_t size:16;
159 } s;
160 struct cvmx_pko_mem_debug0_s cn30xx;
161 struct cvmx_pko_mem_debug0_s cn31xx;
162 struct cvmx_pko_mem_debug0_s cn38xx;
163 struct cvmx_pko_mem_debug0_s cn38xxp2;
164 struct cvmx_pko_mem_debug0_s cn50xx;
165 struct cvmx_pko_mem_debug0_s cn52xx;
166 struct cvmx_pko_mem_debug0_s cn52xxp1;
167 struct cvmx_pko_mem_debug0_s cn56xx;
168 struct cvmx_pko_mem_debug0_s cn56xxp1;
169 struct cvmx_pko_mem_debug0_s cn58xx;
170 struct cvmx_pko_mem_debug0_s cn58xxp1;
171};
172
173union cvmx_pko_mem_debug1 {
174 uint64_t u64;
175 struct cvmx_pko_mem_debug1_s {
176 uint64_t i:1;
177 uint64_t back:4;
178 uint64_t pool:3;
179 uint64_t size:16;
180 uint64_t ptr:40;
181 } s;
182 struct cvmx_pko_mem_debug1_s cn30xx;
183 struct cvmx_pko_mem_debug1_s cn31xx;
184 struct cvmx_pko_mem_debug1_s cn38xx;
185 struct cvmx_pko_mem_debug1_s cn38xxp2;
186 struct cvmx_pko_mem_debug1_s cn50xx;
187 struct cvmx_pko_mem_debug1_s cn52xx;
188 struct cvmx_pko_mem_debug1_s cn52xxp1;
189 struct cvmx_pko_mem_debug1_s cn56xx;
190 struct cvmx_pko_mem_debug1_s cn56xxp1;
191 struct cvmx_pko_mem_debug1_s cn58xx;
192 struct cvmx_pko_mem_debug1_s cn58xxp1;
193};
194
195union cvmx_pko_mem_debug10 {
196 uint64_t u64;
197 struct cvmx_pko_mem_debug10_s {
198 uint64_t reserved_0_63:64;
199 } s;
200 struct cvmx_pko_mem_debug10_cn30xx {
201 uint64_t fau:28;
202 uint64_t cmd:14;
203 uint64_t segs:6;
204 uint64_t size:16;
205 } cn30xx;
206 struct cvmx_pko_mem_debug10_cn30xx cn31xx;
207 struct cvmx_pko_mem_debug10_cn30xx cn38xx;
208 struct cvmx_pko_mem_debug10_cn30xx cn38xxp2;
209 struct cvmx_pko_mem_debug10_cn50xx {
210 uint64_t reserved_49_63:15;
211 uint64_t ptrs1:17;
212 uint64_t reserved_17_31:15;
213 uint64_t ptrs2:17;
214 } cn50xx;
215 struct cvmx_pko_mem_debug10_cn50xx cn52xx;
216 struct cvmx_pko_mem_debug10_cn50xx cn52xxp1;
217 struct cvmx_pko_mem_debug10_cn50xx cn56xx;
218 struct cvmx_pko_mem_debug10_cn50xx cn56xxp1;
219 struct cvmx_pko_mem_debug10_cn50xx cn58xx;
220 struct cvmx_pko_mem_debug10_cn50xx cn58xxp1;
221};
222
223union cvmx_pko_mem_debug11 {
224 uint64_t u64;
225 struct cvmx_pko_mem_debug11_s {
226 uint64_t i:1;
227 uint64_t back:4;
228 uint64_t pool:3;
229 uint64_t size:16;
230 uint64_t reserved_0_39:40;
231 } s;
232 struct cvmx_pko_mem_debug11_cn30xx {
233 uint64_t i:1;
234 uint64_t back:4;
235 uint64_t pool:3;
236 uint64_t size:16;
237 uint64_t ptr:40;
238 } cn30xx;
239 struct cvmx_pko_mem_debug11_cn30xx cn31xx;
240 struct cvmx_pko_mem_debug11_cn30xx cn38xx;
241 struct cvmx_pko_mem_debug11_cn30xx cn38xxp2;
242 struct cvmx_pko_mem_debug11_cn50xx {
243 uint64_t reserved_23_63:41;
244 uint64_t maj:1;
245 uint64_t uid:3;
246 uint64_t sop:1;
247 uint64_t len:1;
248 uint64_t chk:1;
249 uint64_t cnt:13;
250 uint64_t mod:3;
251 } cn50xx;
252 struct cvmx_pko_mem_debug11_cn50xx cn52xx;
253 struct cvmx_pko_mem_debug11_cn50xx cn52xxp1;
254 struct cvmx_pko_mem_debug11_cn50xx cn56xx;
255 struct cvmx_pko_mem_debug11_cn50xx cn56xxp1;
256 struct cvmx_pko_mem_debug11_cn50xx cn58xx;
257 struct cvmx_pko_mem_debug11_cn50xx cn58xxp1;
258};
259
260union cvmx_pko_mem_debug12 {
261 uint64_t u64;
262 struct cvmx_pko_mem_debug12_s {
263 uint64_t reserved_0_63:64;
264 } s;
265 struct cvmx_pko_mem_debug12_cn30xx {
266 uint64_t data:64;
267 } cn30xx;
268 struct cvmx_pko_mem_debug12_cn30xx cn31xx;
269 struct cvmx_pko_mem_debug12_cn30xx cn38xx;
270 struct cvmx_pko_mem_debug12_cn30xx cn38xxp2;
271 struct cvmx_pko_mem_debug12_cn50xx {
272 uint64_t fau:28;
273 uint64_t cmd:14;
274 uint64_t segs:6;
275 uint64_t size:16;
276 } cn50xx;
277 struct cvmx_pko_mem_debug12_cn50xx cn52xx;
278 struct cvmx_pko_mem_debug12_cn50xx cn52xxp1;
279 struct cvmx_pko_mem_debug12_cn50xx cn56xx;
280 struct cvmx_pko_mem_debug12_cn50xx cn56xxp1;
281 struct cvmx_pko_mem_debug12_cn50xx cn58xx;
282 struct cvmx_pko_mem_debug12_cn50xx cn58xxp1;
283};
284
285union cvmx_pko_mem_debug13 {
286 uint64_t u64;
287 struct cvmx_pko_mem_debug13_s {
288 uint64_t i:1;
289 uint64_t back:4;
290 uint64_t pool:3;
291 uint64_t reserved_0_55:56;
292 } s;
293 struct cvmx_pko_mem_debug13_cn30xx {
294 uint64_t reserved_51_63:13;
295 uint64_t widx:17;
296 uint64_t ridx2:17;
297 uint64_t widx2:17;
298 } cn30xx;
299 struct cvmx_pko_mem_debug13_cn30xx cn31xx;
300 struct cvmx_pko_mem_debug13_cn30xx cn38xx;
301 struct cvmx_pko_mem_debug13_cn30xx cn38xxp2;
302 struct cvmx_pko_mem_debug13_cn50xx {
303 uint64_t i:1;
304 uint64_t back:4;
305 uint64_t pool:3;
306 uint64_t size:16;
307 uint64_t ptr:40;
308 } cn50xx;
309 struct cvmx_pko_mem_debug13_cn50xx cn52xx;
310 struct cvmx_pko_mem_debug13_cn50xx cn52xxp1;
311 struct cvmx_pko_mem_debug13_cn50xx cn56xx;
312 struct cvmx_pko_mem_debug13_cn50xx cn56xxp1;
313 struct cvmx_pko_mem_debug13_cn50xx cn58xx;
314 struct cvmx_pko_mem_debug13_cn50xx cn58xxp1;
315};
316
317union cvmx_pko_mem_debug14 {
318 uint64_t u64;
319 struct cvmx_pko_mem_debug14_s {
320 uint64_t reserved_0_63:64;
321 } s;
322 struct cvmx_pko_mem_debug14_cn30xx {
323 uint64_t reserved_17_63:47;
324 uint64_t ridx:17;
325 } cn30xx;
326 struct cvmx_pko_mem_debug14_cn30xx cn31xx;
327 struct cvmx_pko_mem_debug14_cn30xx cn38xx;
328 struct cvmx_pko_mem_debug14_cn30xx cn38xxp2;
329 struct cvmx_pko_mem_debug14_cn52xx {
330 uint64_t data:64;
331 } cn52xx;
332 struct cvmx_pko_mem_debug14_cn52xx cn52xxp1;
333 struct cvmx_pko_mem_debug14_cn52xx cn56xx;
334 struct cvmx_pko_mem_debug14_cn52xx cn56xxp1;
335};
336
337union cvmx_pko_mem_debug2 {
338 uint64_t u64;
339 struct cvmx_pko_mem_debug2_s {
340 uint64_t i:1;
341 uint64_t back:4;
342 uint64_t pool:3;
343 uint64_t size:16;
344 uint64_t ptr:40;
345 } s;
346 struct cvmx_pko_mem_debug2_s cn30xx;
347 struct cvmx_pko_mem_debug2_s cn31xx;
348 struct cvmx_pko_mem_debug2_s cn38xx;
349 struct cvmx_pko_mem_debug2_s cn38xxp2;
350 struct cvmx_pko_mem_debug2_s cn50xx;
351 struct cvmx_pko_mem_debug2_s cn52xx;
352 struct cvmx_pko_mem_debug2_s cn52xxp1;
353 struct cvmx_pko_mem_debug2_s cn56xx;
354 struct cvmx_pko_mem_debug2_s cn56xxp1;
355 struct cvmx_pko_mem_debug2_s cn58xx;
356 struct cvmx_pko_mem_debug2_s cn58xxp1;
357};
358
359union cvmx_pko_mem_debug3 {
360 uint64_t u64;
361 struct cvmx_pko_mem_debug3_s {
362 uint64_t reserved_0_63:64;
363 } s;
364 struct cvmx_pko_mem_debug3_cn30xx {
365 uint64_t i:1;
366 uint64_t back:4;
367 uint64_t pool:3;
368 uint64_t size:16;
369 uint64_t ptr:40;
370 } cn30xx;
371 struct cvmx_pko_mem_debug3_cn30xx cn31xx;
372 struct cvmx_pko_mem_debug3_cn30xx cn38xx;
373 struct cvmx_pko_mem_debug3_cn30xx cn38xxp2;
374 struct cvmx_pko_mem_debug3_cn50xx {
375 uint64_t data:64;
376 } cn50xx;
377 struct cvmx_pko_mem_debug3_cn50xx cn52xx;
378 struct cvmx_pko_mem_debug3_cn50xx cn52xxp1;
379 struct cvmx_pko_mem_debug3_cn50xx cn56xx;
380 struct cvmx_pko_mem_debug3_cn50xx cn56xxp1;
381 struct cvmx_pko_mem_debug3_cn50xx cn58xx;
382 struct cvmx_pko_mem_debug3_cn50xx cn58xxp1;
383};
384
385union cvmx_pko_mem_debug4 {
386 uint64_t u64;
387 struct cvmx_pko_mem_debug4_s {
388 uint64_t reserved_0_63:64;
389 } s;
390 struct cvmx_pko_mem_debug4_cn30xx {
391 uint64_t data:64;
392 } cn30xx;
393 struct cvmx_pko_mem_debug4_cn30xx cn31xx;
394 struct cvmx_pko_mem_debug4_cn30xx cn38xx;
395 struct cvmx_pko_mem_debug4_cn30xx cn38xxp2;
396 struct cvmx_pko_mem_debug4_cn50xx {
397 uint64_t cmnd_segs:3;
398 uint64_t cmnd_siz:16;
399 uint64_t cmnd_off:6;
400 uint64_t uid:3;
401 uint64_t dread_sop:1;
402 uint64_t init_dwrite:1;
403 uint64_t chk_once:1;
404 uint64_t chk_mode:1;
405 uint64_t active:1;
406 uint64_t static_p:1;
407 uint64_t qos:3;
408 uint64_t qcb_ridx:5;
409 uint64_t qid_off_max:4;
410 uint64_t qid_off:4;
411 uint64_t qid_base:8;
412 uint64_t wait:1;
413 uint64_t minor:2;
414 uint64_t major:3;
415 } cn50xx;
416 struct cvmx_pko_mem_debug4_cn52xx {
417 uint64_t curr_siz:8;
418 uint64_t curr_off:16;
419 uint64_t cmnd_segs:6;
420 uint64_t cmnd_siz:16;
421 uint64_t cmnd_off:6;
422 uint64_t uid:2;
423 uint64_t dread_sop:1;
424 uint64_t init_dwrite:1;
425 uint64_t chk_once:1;
426 uint64_t chk_mode:1;
427 uint64_t wait:1;
428 uint64_t minor:2;
429 uint64_t major:3;
430 } cn52xx;
431 struct cvmx_pko_mem_debug4_cn52xx cn52xxp1;
432 struct cvmx_pko_mem_debug4_cn52xx cn56xx;
433 struct cvmx_pko_mem_debug4_cn52xx cn56xxp1;
434 struct cvmx_pko_mem_debug4_cn50xx cn58xx;
435 struct cvmx_pko_mem_debug4_cn50xx cn58xxp1;
436};
437
438union cvmx_pko_mem_debug5 {
439 uint64_t u64;
440 struct cvmx_pko_mem_debug5_s {
441 uint64_t reserved_0_63:64;
442 } s;
443 struct cvmx_pko_mem_debug5_cn30xx {
444 uint64_t dwri_mod:1;
445 uint64_t dwri_sop:1;
446 uint64_t dwri_len:1;
447 uint64_t dwri_cnt:13;
448 uint64_t cmnd_siz:16;
449 uint64_t uid:1;
450 uint64_t xfer_wor:1;
451 uint64_t xfer_dwr:1;
452 uint64_t cbuf_fre:1;
453 uint64_t reserved_27_27:1;
454 uint64_t chk_mode:1;
455 uint64_t active:1;
456 uint64_t qos:3;
457 uint64_t qcb_ridx:5;
458 uint64_t qid_off:3;
459 uint64_t qid_base:7;
460 uint64_t wait:1;
461 uint64_t minor:2;
462 uint64_t major:4;
463 } cn30xx;
464 struct cvmx_pko_mem_debug5_cn30xx cn31xx;
465 struct cvmx_pko_mem_debug5_cn30xx cn38xx;
466 struct cvmx_pko_mem_debug5_cn30xx cn38xxp2;
467 struct cvmx_pko_mem_debug5_cn50xx {
468 uint64_t curr_ptr:29;
469 uint64_t curr_siz:16;
470 uint64_t curr_off:16;
471 uint64_t cmnd_segs:3;
472 } cn50xx;
473 struct cvmx_pko_mem_debug5_cn52xx {
474 uint64_t reserved_54_63:10;
475 uint64_t nxt_inflt:6;
476 uint64_t curr_ptr:40;
477 uint64_t curr_siz:8;
478 } cn52xx;
479 struct cvmx_pko_mem_debug5_cn52xx cn52xxp1;
480 struct cvmx_pko_mem_debug5_cn52xx cn56xx;
481 struct cvmx_pko_mem_debug5_cn52xx cn56xxp1;
482 struct cvmx_pko_mem_debug5_cn50xx cn58xx;
483 struct cvmx_pko_mem_debug5_cn50xx cn58xxp1;
484};
485
486union cvmx_pko_mem_debug6 {
487 uint64_t u64;
488 struct cvmx_pko_mem_debug6_s {
489 uint64_t reserved_37_63:27;
490 uint64_t qid_offres:4;
491 uint64_t qid_offths:4;
492 uint64_t preempter:1;
493 uint64_t preemptee:1;
494 uint64_t preempted:1;
495 uint64_t active:1;
496 uint64_t statc:1;
497 uint64_t qos:3;
498 uint64_t qcb_ridx:5;
499 uint64_t qid_offmax:4;
500 uint64_t reserved_0_11:12;
501 } s;
502 struct cvmx_pko_mem_debug6_cn30xx {
503 uint64_t reserved_11_63:53;
504 uint64_t qid_offm:3;
505 uint64_t static_p:1;
506 uint64_t work_min:3;
507 uint64_t dwri_chk:1;
508 uint64_t dwri_uid:1;
509 uint64_t dwri_mod:2;
510 } cn30xx;
511 struct cvmx_pko_mem_debug6_cn30xx cn31xx;
512 struct cvmx_pko_mem_debug6_cn30xx cn38xx;
513 struct cvmx_pko_mem_debug6_cn30xx cn38xxp2;
514 struct cvmx_pko_mem_debug6_cn50xx {
515 uint64_t reserved_11_63:53;
516 uint64_t curr_ptr:11;
517 } cn50xx;
518 struct cvmx_pko_mem_debug6_cn52xx {
519 uint64_t reserved_37_63:27;
520 uint64_t qid_offres:4;
521 uint64_t qid_offths:4;
522 uint64_t preempter:1;
523 uint64_t preemptee:1;
524 uint64_t preempted:1;
525 uint64_t active:1;
526 uint64_t statc:1;
527 uint64_t qos:3;
528 uint64_t qcb_ridx:5;
529 uint64_t qid_offmax:4;
530 uint64_t qid_off:4;
531 uint64_t qid_base:8;
532 } cn52xx;
533 struct cvmx_pko_mem_debug6_cn52xx cn52xxp1;
534 struct cvmx_pko_mem_debug6_cn52xx cn56xx;
535 struct cvmx_pko_mem_debug6_cn52xx cn56xxp1;
536 struct cvmx_pko_mem_debug6_cn50xx cn58xx;
537 struct cvmx_pko_mem_debug6_cn50xx cn58xxp1;
538};
539
540union cvmx_pko_mem_debug7 {
541 uint64_t u64;
542 struct cvmx_pko_mem_debug7_s {
543 uint64_t qos:5;
544 uint64_t tail:1;
545 uint64_t reserved_0_57:58;
546 } s;
547 struct cvmx_pko_mem_debug7_cn30xx {
548 uint64_t reserved_58_63:6;
549 uint64_t dwb:9;
550 uint64_t start:33;
551 uint64_t size:16;
552 } cn30xx;
553 struct cvmx_pko_mem_debug7_cn30xx cn31xx;
554 struct cvmx_pko_mem_debug7_cn30xx cn38xx;
555 struct cvmx_pko_mem_debug7_cn30xx cn38xxp2;
556 struct cvmx_pko_mem_debug7_cn50xx {
557 uint64_t qos:5;
558 uint64_t tail:1;
559 uint64_t buf_siz:13;
560 uint64_t buf_ptr:33;
561 uint64_t qcb_widx:6;
562 uint64_t qcb_ridx:6;
563 } cn50xx;
564 struct cvmx_pko_mem_debug7_cn50xx cn52xx;
565 struct cvmx_pko_mem_debug7_cn50xx cn52xxp1;
566 struct cvmx_pko_mem_debug7_cn50xx cn56xx;
567 struct cvmx_pko_mem_debug7_cn50xx cn56xxp1;
568 struct cvmx_pko_mem_debug7_cn50xx cn58xx;
569 struct cvmx_pko_mem_debug7_cn50xx cn58xxp1;
570};
571
572union cvmx_pko_mem_debug8 {
573 uint64_t u64;
574 struct cvmx_pko_mem_debug8_s {
575 uint64_t reserved_59_63:5;
576 uint64_t tail:1;
577 uint64_t buf_siz:13;
578 uint64_t reserved_0_44:45;
579 } s;
580 struct cvmx_pko_mem_debug8_cn30xx {
581 uint64_t qos:5;
582 uint64_t tail:1;
583 uint64_t buf_siz:13;
584 uint64_t buf_ptr:33;
585 uint64_t qcb_widx:6;
586 uint64_t qcb_ridx:6;
587 } cn30xx;
588 struct cvmx_pko_mem_debug8_cn30xx cn31xx;
589 struct cvmx_pko_mem_debug8_cn30xx cn38xx;
590 struct cvmx_pko_mem_debug8_cn30xx cn38xxp2;
591 struct cvmx_pko_mem_debug8_cn50xx {
592 uint64_t reserved_28_63:36;
593 uint64_t doorbell:20;
594 uint64_t reserved_6_7:2;
595 uint64_t static_p:1;
596 uint64_t s_tail:1;
597 uint64_t static_q:1;
598 uint64_t qos:3;
599 } cn50xx;
600 struct cvmx_pko_mem_debug8_cn52xx {
601 uint64_t reserved_29_63:35;
602 uint64_t preempter:1;
603 uint64_t doorbell:20;
604 uint64_t reserved_7_7:1;
605 uint64_t preemptee:1;
606 uint64_t static_p:1;
607 uint64_t s_tail:1;
608 uint64_t static_q:1;
609 uint64_t qos:3;
610 } cn52xx;
611 struct cvmx_pko_mem_debug8_cn52xx cn52xxp1;
612 struct cvmx_pko_mem_debug8_cn52xx cn56xx;
613 struct cvmx_pko_mem_debug8_cn52xx cn56xxp1;
614 struct cvmx_pko_mem_debug8_cn50xx cn58xx;
615 struct cvmx_pko_mem_debug8_cn50xx cn58xxp1;
616};
617
618union cvmx_pko_mem_debug9 {
619 uint64_t u64;
620 struct cvmx_pko_mem_debug9_s {
621 uint64_t reserved_49_63:15;
622 uint64_t ptrs0:17;
623 uint64_t reserved_0_31:32;
624 } s;
625 struct cvmx_pko_mem_debug9_cn30xx {
626 uint64_t reserved_28_63:36;
627 uint64_t doorbell:20;
628 uint64_t reserved_5_7:3;
629 uint64_t s_tail:1;
630 uint64_t static_q:1;
631 uint64_t qos:3;
632 } cn30xx;
633 struct cvmx_pko_mem_debug9_cn30xx cn31xx;
634 struct cvmx_pko_mem_debug9_cn38xx {
635 uint64_t reserved_28_63:36;
636 uint64_t doorbell:20;
637 uint64_t reserved_6_7:2;
638 uint64_t static_p:1;
639 uint64_t s_tail:1;
640 uint64_t static_q:1;
641 uint64_t qos:3;
642 } cn38xx;
643 struct cvmx_pko_mem_debug9_cn38xx cn38xxp2;
644 struct cvmx_pko_mem_debug9_cn50xx {
645 uint64_t reserved_49_63:15;
646 uint64_t ptrs0:17;
647 uint64_t reserved_17_31:15;
648 uint64_t ptrs3:17;
649 } cn50xx;
650 struct cvmx_pko_mem_debug9_cn50xx cn52xx;
651 struct cvmx_pko_mem_debug9_cn50xx cn52xxp1;
652 struct cvmx_pko_mem_debug9_cn50xx cn56xx;
653 struct cvmx_pko_mem_debug9_cn50xx cn56xxp1;
654 struct cvmx_pko_mem_debug9_cn50xx cn58xx;
655 struct cvmx_pko_mem_debug9_cn50xx cn58xxp1;
656};
657
658union cvmx_pko_mem_port_ptrs {
659 uint64_t u64;
660 struct cvmx_pko_mem_port_ptrs_s {
661 uint64_t reserved_62_63:2;
662 uint64_t static_p:1;
663 uint64_t qos_mask:8;
664 uint64_t reserved_16_52:37;
665 uint64_t bp_port:6;
666 uint64_t eid:4;
667 uint64_t pid:6;
668 } s;
669 struct cvmx_pko_mem_port_ptrs_s cn52xx;
670 struct cvmx_pko_mem_port_ptrs_s cn52xxp1;
671 struct cvmx_pko_mem_port_ptrs_s cn56xx;
672 struct cvmx_pko_mem_port_ptrs_s cn56xxp1;
673};
674
675union cvmx_pko_mem_port_qos {
676 uint64_t u64;
677 struct cvmx_pko_mem_port_qos_s {
678 uint64_t reserved_61_63:3;
679 uint64_t qos_mask:8;
680 uint64_t reserved_10_52:43;
681 uint64_t eid:4;
682 uint64_t pid:6;
683 } s;
684 struct cvmx_pko_mem_port_qos_s cn52xx;
685 struct cvmx_pko_mem_port_qos_s cn52xxp1;
686 struct cvmx_pko_mem_port_qos_s cn56xx;
687 struct cvmx_pko_mem_port_qos_s cn56xxp1;
688};
689
690union cvmx_pko_mem_port_rate0 {
691 uint64_t u64;
692 struct cvmx_pko_mem_port_rate0_s {
693 uint64_t reserved_51_63:13;
694 uint64_t rate_word:19;
695 uint64_t rate_pkt:24;
696 uint64_t reserved_6_7:2;
697 uint64_t pid:6;
698 } s;
699 struct cvmx_pko_mem_port_rate0_s cn52xx;
700 struct cvmx_pko_mem_port_rate0_s cn52xxp1;
701 struct cvmx_pko_mem_port_rate0_s cn56xx;
702 struct cvmx_pko_mem_port_rate0_s cn56xxp1;
703};
704
705union cvmx_pko_mem_port_rate1 {
706 uint64_t u64;
707 struct cvmx_pko_mem_port_rate1_s {
708 uint64_t reserved_32_63:32;
709 uint64_t rate_lim:24;
710 uint64_t reserved_6_7:2;
711 uint64_t pid:6;
712 } s;
713 struct cvmx_pko_mem_port_rate1_s cn52xx;
714 struct cvmx_pko_mem_port_rate1_s cn52xxp1;
715 struct cvmx_pko_mem_port_rate1_s cn56xx;
716 struct cvmx_pko_mem_port_rate1_s cn56xxp1;
717};
718
719union cvmx_pko_mem_queue_ptrs {
720 uint64_t u64;
721 struct cvmx_pko_mem_queue_ptrs_s {
722 uint64_t s_tail:1;
723 uint64_t static_p:1;
724 uint64_t static_q:1;
725 uint64_t qos_mask:8;
726 uint64_t buf_ptr:36;
727 uint64_t tail:1;
728 uint64_t index:3;
729 uint64_t port:6;
730 uint64_t queue:7;
731 } s;
732 struct cvmx_pko_mem_queue_ptrs_s cn30xx;
733 struct cvmx_pko_mem_queue_ptrs_s cn31xx;
734 struct cvmx_pko_mem_queue_ptrs_s cn38xx;
735 struct cvmx_pko_mem_queue_ptrs_s cn38xxp2;
736 struct cvmx_pko_mem_queue_ptrs_s cn50xx;
737 struct cvmx_pko_mem_queue_ptrs_s cn52xx;
738 struct cvmx_pko_mem_queue_ptrs_s cn52xxp1;
739 struct cvmx_pko_mem_queue_ptrs_s cn56xx;
740 struct cvmx_pko_mem_queue_ptrs_s cn56xxp1;
741 struct cvmx_pko_mem_queue_ptrs_s cn58xx;
742 struct cvmx_pko_mem_queue_ptrs_s cn58xxp1;
743};
744
745union cvmx_pko_mem_queue_qos {
746 uint64_t u64;
747 struct cvmx_pko_mem_queue_qos_s {
748 uint64_t reserved_61_63:3;
749 uint64_t qos_mask:8;
750 uint64_t reserved_13_52:40;
751 uint64_t pid:6;
752 uint64_t qid:7;
753 } s;
754 struct cvmx_pko_mem_queue_qos_s cn30xx;
755 struct cvmx_pko_mem_queue_qos_s cn31xx;
756 struct cvmx_pko_mem_queue_qos_s cn38xx;
757 struct cvmx_pko_mem_queue_qos_s cn38xxp2;
758 struct cvmx_pko_mem_queue_qos_s cn50xx;
759 struct cvmx_pko_mem_queue_qos_s cn52xx;
760 struct cvmx_pko_mem_queue_qos_s cn52xxp1;
761 struct cvmx_pko_mem_queue_qos_s cn56xx;
762 struct cvmx_pko_mem_queue_qos_s cn56xxp1;
763 struct cvmx_pko_mem_queue_qos_s cn58xx;
764 struct cvmx_pko_mem_queue_qos_s cn58xxp1;
765};
766
767union cvmx_pko_reg_bist_result {
768 uint64_t u64;
769 struct cvmx_pko_reg_bist_result_s {
770 uint64_t reserved_0_63:64;
771 } s;
772 struct cvmx_pko_reg_bist_result_cn30xx {
773 uint64_t reserved_27_63:37;
774 uint64_t psb2:5;
775 uint64_t count:1;
776 uint64_t rif:1;
777 uint64_t wif:1;
778 uint64_t ncb:1;
779 uint64_t out:1;
780 uint64_t crc:1;
781 uint64_t chk:1;
782 uint64_t qsb:2;
783 uint64_t qcb:2;
784 uint64_t pdb:4;
785 uint64_t psb:7;
786 } cn30xx;
787 struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
788 struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
789 struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
790 struct cvmx_pko_reg_bist_result_cn50xx {
791 uint64_t reserved_33_63:31;
792 uint64_t csr:1;
793 uint64_t iob:1;
794 uint64_t out_crc:1;
795 uint64_t out_ctl:3;
796 uint64_t out_sta:1;
797 uint64_t out_wif:1;
798 uint64_t prt_chk:3;
799 uint64_t prt_nxt:1;
800 uint64_t prt_psb:6;
801 uint64_t ncb_inb:2;
802 uint64_t prt_qcb:2;
803 uint64_t prt_qsb:3;
804 uint64_t dat_dat:4;
805 uint64_t dat_ptr:4;
806 } cn50xx;
807 struct cvmx_pko_reg_bist_result_cn52xx {
808 uint64_t reserved_35_63:29;
809 uint64_t csr:1;
810 uint64_t iob:1;
811 uint64_t out_dat:1;
812 uint64_t out_ctl:3;
813 uint64_t out_sta:1;
814 uint64_t out_wif:1;
815 uint64_t prt_chk:3;
816 uint64_t prt_nxt:1;
817 uint64_t prt_psb:8;
818 uint64_t ncb_inb:2;
819 uint64_t prt_qcb:2;
820 uint64_t prt_qsb:3;
821 uint64_t prt_ctl:2;
822 uint64_t dat_dat:2;
823 uint64_t dat_ptr:4;
824 } cn52xx;
825 struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
826 struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
827 struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
828 struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
829 struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
830};
831
832union cvmx_pko_reg_cmd_buf {
833 uint64_t u64;
834 struct cvmx_pko_reg_cmd_buf_s {
835 uint64_t reserved_23_63:41;
836 uint64_t pool:3;
837 uint64_t reserved_13_19:7;
838 uint64_t size:13;
839 } s;
840 struct cvmx_pko_reg_cmd_buf_s cn30xx;
841 struct cvmx_pko_reg_cmd_buf_s cn31xx;
842 struct cvmx_pko_reg_cmd_buf_s cn38xx;
843 struct cvmx_pko_reg_cmd_buf_s cn38xxp2;
844 struct cvmx_pko_reg_cmd_buf_s cn50xx;
845 struct cvmx_pko_reg_cmd_buf_s cn52xx;
846 struct cvmx_pko_reg_cmd_buf_s cn52xxp1;
847 struct cvmx_pko_reg_cmd_buf_s cn56xx;
848 struct cvmx_pko_reg_cmd_buf_s cn56xxp1;
849 struct cvmx_pko_reg_cmd_buf_s cn58xx;
850 struct cvmx_pko_reg_cmd_buf_s cn58xxp1;
851};
852
853union cvmx_pko_reg_crc_ctlx {
854 uint64_t u64;
855 struct cvmx_pko_reg_crc_ctlx_s {
856 uint64_t reserved_2_63:62;
857 uint64_t invres:1;
858 uint64_t refin:1;
859 } s;
860 struct cvmx_pko_reg_crc_ctlx_s cn38xx;
861 struct cvmx_pko_reg_crc_ctlx_s cn38xxp2;
862 struct cvmx_pko_reg_crc_ctlx_s cn58xx;
863 struct cvmx_pko_reg_crc_ctlx_s cn58xxp1;
864};
865
866union cvmx_pko_reg_crc_enable {
867 uint64_t u64;
868 struct cvmx_pko_reg_crc_enable_s {
869 uint64_t reserved_32_63:32;
870 uint64_t enable:32;
871 } s;
872 struct cvmx_pko_reg_crc_enable_s cn38xx;
873 struct cvmx_pko_reg_crc_enable_s cn38xxp2;
874 struct cvmx_pko_reg_crc_enable_s cn58xx;
875 struct cvmx_pko_reg_crc_enable_s cn58xxp1;
876};
877
878union cvmx_pko_reg_crc_ivx {
879 uint64_t u64;
880 struct cvmx_pko_reg_crc_ivx_s {
881 uint64_t reserved_32_63:32;
882 uint64_t iv:32;
883 } s;
884 struct cvmx_pko_reg_crc_ivx_s cn38xx;
885 struct cvmx_pko_reg_crc_ivx_s cn38xxp2;
886 struct cvmx_pko_reg_crc_ivx_s cn58xx;
887 struct cvmx_pko_reg_crc_ivx_s cn58xxp1;
888};
889
890union cvmx_pko_reg_debug0 {
891 uint64_t u64;
892 struct cvmx_pko_reg_debug0_s {
893 uint64_t asserts:64;
894 } s;
895 struct cvmx_pko_reg_debug0_cn30xx {
896 uint64_t reserved_17_63:47;
897 uint64_t asserts:17;
898 } cn30xx;
899 struct cvmx_pko_reg_debug0_cn30xx cn31xx;
900 struct cvmx_pko_reg_debug0_cn30xx cn38xx;
901 struct cvmx_pko_reg_debug0_cn30xx cn38xxp2;
902 struct cvmx_pko_reg_debug0_s cn50xx;
903 struct cvmx_pko_reg_debug0_s cn52xx;
904 struct cvmx_pko_reg_debug0_s cn52xxp1;
905 struct cvmx_pko_reg_debug0_s cn56xx;
906 struct cvmx_pko_reg_debug0_s cn56xxp1;
907 struct cvmx_pko_reg_debug0_s cn58xx;
908 struct cvmx_pko_reg_debug0_s cn58xxp1;
909};
910
911union cvmx_pko_reg_debug1 {
912 uint64_t u64;
913 struct cvmx_pko_reg_debug1_s {
914 uint64_t asserts:64;
915 } s;
916 struct cvmx_pko_reg_debug1_s cn50xx;
917 struct cvmx_pko_reg_debug1_s cn52xx;
918 struct cvmx_pko_reg_debug1_s cn52xxp1;
919 struct cvmx_pko_reg_debug1_s cn56xx;
920 struct cvmx_pko_reg_debug1_s cn56xxp1;
921 struct cvmx_pko_reg_debug1_s cn58xx;
922 struct cvmx_pko_reg_debug1_s cn58xxp1;
923};
924
925union cvmx_pko_reg_debug2 {
926 uint64_t u64;
927 struct cvmx_pko_reg_debug2_s {
928 uint64_t asserts:64;
929 } s;
930 struct cvmx_pko_reg_debug2_s cn50xx;
931 struct cvmx_pko_reg_debug2_s cn52xx;
932 struct cvmx_pko_reg_debug2_s cn52xxp1;
933 struct cvmx_pko_reg_debug2_s cn56xx;
934 struct cvmx_pko_reg_debug2_s cn56xxp1;
935 struct cvmx_pko_reg_debug2_s cn58xx;
936 struct cvmx_pko_reg_debug2_s cn58xxp1;
937};
938
939union cvmx_pko_reg_debug3 {
940 uint64_t u64;
941 struct cvmx_pko_reg_debug3_s {
942 uint64_t asserts:64;
943 } s;
944 struct cvmx_pko_reg_debug3_s cn50xx;
945 struct cvmx_pko_reg_debug3_s cn52xx;
946 struct cvmx_pko_reg_debug3_s cn52xxp1;
947 struct cvmx_pko_reg_debug3_s cn56xx;
948 struct cvmx_pko_reg_debug3_s cn56xxp1;
949 struct cvmx_pko_reg_debug3_s cn58xx;
950 struct cvmx_pko_reg_debug3_s cn58xxp1;
951};
952
953union cvmx_pko_reg_engine_inflight {
954 uint64_t u64;
955 struct cvmx_pko_reg_engine_inflight_s {
956 uint64_t reserved_40_63:24;
957 uint64_t engine9:4;
958 uint64_t engine8:4;
959 uint64_t engine7:4;
960 uint64_t engine6:4;
961 uint64_t engine5:4;
962 uint64_t engine4:4;
963 uint64_t engine3:4;
964 uint64_t engine2:4;
965 uint64_t engine1:4;
966 uint64_t engine0:4;
967 } s;
968 struct cvmx_pko_reg_engine_inflight_s cn52xx;
969 struct cvmx_pko_reg_engine_inflight_s cn52xxp1;
970 struct cvmx_pko_reg_engine_inflight_s cn56xx;
971 struct cvmx_pko_reg_engine_inflight_s cn56xxp1;
972};
973
974union cvmx_pko_reg_engine_thresh {
975 uint64_t u64;
976 struct cvmx_pko_reg_engine_thresh_s {
977 uint64_t reserved_10_63:54;
978 uint64_t mask:10;
979 } s;
980 struct cvmx_pko_reg_engine_thresh_s cn52xx;
981 struct cvmx_pko_reg_engine_thresh_s cn52xxp1;
982 struct cvmx_pko_reg_engine_thresh_s cn56xx;
983 struct cvmx_pko_reg_engine_thresh_s cn56xxp1;
984};
985
986union cvmx_pko_reg_error {
987 uint64_t u64;
988 struct cvmx_pko_reg_error_s {
989 uint64_t reserved_3_63:61;
990 uint64_t currzero:1;
991 uint64_t doorbell:1;
992 uint64_t parity:1;
993 } s;
994 struct cvmx_pko_reg_error_cn30xx {
995 uint64_t reserved_2_63:62;
996 uint64_t doorbell:1;
997 uint64_t parity:1;
998 } cn30xx;
999 struct cvmx_pko_reg_error_cn30xx cn31xx;
1000 struct cvmx_pko_reg_error_cn30xx cn38xx;
1001 struct cvmx_pko_reg_error_cn30xx cn38xxp2;
1002 struct cvmx_pko_reg_error_s cn50xx;
1003 struct cvmx_pko_reg_error_s cn52xx;
1004 struct cvmx_pko_reg_error_s cn52xxp1;
1005 struct cvmx_pko_reg_error_s cn56xx;
1006 struct cvmx_pko_reg_error_s cn56xxp1;
1007 struct cvmx_pko_reg_error_s cn58xx;
1008 struct cvmx_pko_reg_error_s cn58xxp1;
1009};
1010
1011union cvmx_pko_reg_flags {
1012 uint64_t u64;
1013 struct cvmx_pko_reg_flags_s {
1014 uint64_t reserved_4_63:60;
1015 uint64_t reset:1;
1016 uint64_t store_be:1;
1017 uint64_t ena_dwb:1;
1018 uint64_t ena_pko:1;
1019 } s;
1020 struct cvmx_pko_reg_flags_s cn30xx;
1021 struct cvmx_pko_reg_flags_s cn31xx;
1022 struct cvmx_pko_reg_flags_s cn38xx;
1023 struct cvmx_pko_reg_flags_s cn38xxp2;
1024 struct cvmx_pko_reg_flags_s cn50xx;
1025 struct cvmx_pko_reg_flags_s cn52xx;
1026 struct cvmx_pko_reg_flags_s cn52xxp1;
1027 struct cvmx_pko_reg_flags_s cn56xx;
1028 struct cvmx_pko_reg_flags_s cn56xxp1;
1029 struct cvmx_pko_reg_flags_s cn58xx;
1030 struct cvmx_pko_reg_flags_s cn58xxp1;
1031};
1032
1033union cvmx_pko_reg_gmx_port_mode {
1034 uint64_t u64;
1035 struct cvmx_pko_reg_gmx_port_mode_s {
1036 uint64_t reserved_6_63:58;
1037 uint64_t mode1:3;
1038 uint64_t mode0:3;
1039 } s;
1040 struct cvmx_pko_reg_gmx_port_mode_s cn30xx;
1041 struct cvmx_pko_reg_gmx_port_mode_s cn31xx;
1042 struct cvmx_pko_reg_gmx_port_mode_s cn38xx;
1043 struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2;
1044 struct cvmx_pko_reg_gmx_port_mode_s cn50xx;
1045 struct cvmx_pko_reg_gmx_port_mode_s cn52xx;
1046 struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1;
1047 struct cvmx_pko_reg_gmx_port_mode_s cn56xx;
1048 struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1;
1049 struct cvmx_pko_reg_gmx_port_mode_s cn58xx;
1050 struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1;
1051};
1052
1053union cvmx_pko_reg_int_mask {
1054 uint64_t u64;
1055 struct cvmx_pko_reg_int_mask_s {
1056 uint64_t reserved_3_63:61;
1057 uint64_t currzero:1;
1058 uint64_t doorbell:1;
1059 uint64_t parity:1;
1060 } s;
1061 struct cvmx_pko_reg_int_mask_cn30xx {
1062 uint64_t reserved_2_63:62;
1063 uint64_t doorbell:1;
1064 uint64_t parity:1;
1065 } cn30xx;
1066 struct cvmx_pko_reg_int_mask_cn30xx cn31xx;
1067 struct cvmx_pko_reg_int_mask_cn30xx cn38xx;
1068 struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2;
1069 struct cvmx_pko_reg_int_mask_s cn50xx;
1070 struct cvmx_pko_reg_int_mask_s cn52xx;
1071 struct cvmx_pko_reg_int_mask_s cn52xxp1;
1072 struct cvmx_pko_reg_int_mask_s cn56xx;
1073 struct cvmx_pko_reg_int_mask_s cn56xxp1;
1074 struct cvmx_pko_reg_int_mask_s cn58xx;
1075 struct cvmx_pko_reg_int_mask_s cn58xxp1;
1076};
1077
1078union cvmx_pko_reg_queue_mode {
1079 uint64_t u64;
1080 struct cvmx_pko_reg_queue_mode_s {
1081 uint64_t reserved_2_63:62;
1082 uint64_t mode:2;
1083 } s;
1084 struct cvmx_pko_reg_queue_mode_s cn30xx;
1085 struct cvmx_pko_reg_queue_mode_s cn31xx;
1086 struct cvmx_pko_reg_queue_mode_s cn38xx;
1087 struct cvmx_pko_reg_queue_mode_s cn38xxp2;
1088 struct cvmx_pko_reg_queue_mode_s cn50xx;
1089 struct cvmx_pko_reg_queue_mode_s cn52xx;
1090 struct cvmx_pko_reg_queue_mode_s cn52xxp1;
1091 struct cvmx_pko_reg_queue_mode_s cn56xx;
1092 struct cvmx_pko_reg_queue_mode_s cn56xxp1;
1093 struct cvmx_pko_reg_queue_mode_s cn58xx;
1094 struct cvmx_pko_reg_queue_mode_s cn58xxp1;
1095};
1096
1097union cvmx_pko_reg_queue_ptrs1 {
1098 uint64_t u64;
1099 struct cvmx_pko_reg_queue_ptrs1_s {
1100 uint64_t reserved_2_63:62;
1101 uint64_t idx3:1;
1102 uint64_t qid7:1;
1103 } s;
1104 struct cvmx_pko_reg_queue_ptrs1_s cn50xx;
1105 struct cvmx_pko_reg_queue_ptrs1_s cn52xx;
1106 struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1;
1107 struct cvmx_pko_reg_queue_ptrs1_s cn56xx;
1108 struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1;
1109 struct cvmx_pko_reg_queue_ptrs1_s cn58xx;
1110 struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1;
1111};
1112
1113union cvmx_pko_reg_read_idx {
1114 uint64_t u64;
1115 struct cvmx_pko_reg_read_idx_s {
1116 uint64_t reserved_16_63:48;
1117 uint64_t inc:8;
1118 uint64_t index:8;
1119 } s;
1120 struct cvmx_pko_reg_read_idx_s cn30xx;
1121 struct cvmx_pko_reg_read_idx_s cn31xx;
1122 struct cvmx_pko_reg_read_idx_s cn38xx;
1123 struct cvmx_pko_reg_read_idx_s cn38xxp2;
1124 struct cvmx_pko_reg_read_idx_s cn50xx;
1125 struct cvmx_pko_reg_read_idx_s cn52xx;
1126 struct cvmx_pko_reg_read_idx_s cn52xxp1;
1127 struct cvmx_pko_reg_read_idx_s cn56xx;
1128 struct cvmx_pko_reg_read_idx_s cn56xxp1;
1129 struct cvmx_pko_reg_read_idx_s cn58xx;
1130 struct cvmx_pko_reg_read_idx_s cn58xxp1;
1131};
1132
1133#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
new file mode 100644
index 000000000000..de3412aada5d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
@@ -0,0 +1,610 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * Interface to the hardware Packet Output unit.
31 *
32 * Starting with SDK 1.7.0, the PKO output functions now support
33 * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to
34 * function similarly to previous SDKs by using POW atomic tags
35 * to preserve ordering and exclusivity. As a new option, you
36 * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc
37 * memory based locking instead. This locking has the advantage
38 * of not affecting the tag state but doesn't preserve packet
39 * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most
40 * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
41 * with hand tuned fast path code.
42 *
43 * Some of other SDK differences visible to the command command
44 * queuing:
45 * - PKO indexes are no longer stored in the FAU. A large
46 * percentage of the FAU register block used to be tied up
47 * maintaining PKO queue pointers. These are now stored in a
48 * global named block.
49 * - The PKO <b>use_locking</b> parameter can now have a global
50 * effect. Since all application use the same named block,
51 * queue locking correctly applies across all operating
52 * systems when using CVMX_PKO_LOCK_CMD_QUEUE.
53 * - PKO 3 word commands are now supported. Use
54 * cvmx_pko_send_packet_finish3().
55 *
56 */
57
58#ifndef __CVMX_PKO_H__
59#define __CVMX_PKO_H__
60
61#include "cvmx-fpa.h"
62#include "cvmx-pow.h"
63#include "cvmx-cmd-queue.h"
64#include "cvmx-pko-defs.h"
65
66/* Adjust the command buffer size by 1 word so that in the case of using only
67 * two word PKO commands no command words stradle buffers. The useful values
68 * for this are 0 and 1. */
69#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
70
71#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
72#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \
73 OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \
74 OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \
75 (OCTEON_IS_MODEL(OCTEON_CN58XX) || \
76 OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
77#define CVMX_PKO_NUM_OUTPUT_PORTS 40
78/* use this for queues that are not used */
79#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63
80#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9
81#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF
82#define CVMX_PKO_MAX_QUEUE_DEPTH 0
83
84typedef enum {
85 CVMX_PKO_SUCCESS,
86 CVMX_PKO_INVALID_PORT,
87 CVMX_PKO_INVALID_QUEUE,
88 CVMX_PKO_INVALID_PRIORITY,
89 CVMX_PKO_NO_MEMORY,
90 CVMX_PKO_PORT_ALREADY_SETUP,
91 CVMX_PKO_CMD_QUEUE_INIT_ERROR
92} cvmx_pko_status_t;
93
94/**
95 * This enumeration represents the differnet locking modes supported by PKO.
96 */
97typedef enum {
98 /*
99 * PKO doesn't do any locking. It is the responsibility of the
100 * application to make sure that no other core is accessing
101 * the same queue at the same time
102 */
103 CVMX_PKO_LOCK_NONE = 0,
104 /*
105 * PKO performs an atomic tagswitch to insure exclusive access
106 * to the output queue. This will maintain packet ordering on
107 * output.
108 */
109 CVMX_PKO_LOCK_ATOMIC_TAG = 1,
110 /*
111 * PKO uses the common command queue locks to insure exclusive
112 * access to the output queue. This is a memory based
113 * ll/sc. This is the most portable locking mechanism.
114 */
115 CVMX_PKO_LOCK_CMD_QUEUE = 2,
116} cvmx_pko_lock_t;
117
118typedef struct {
119 uint32_t packets;
120 uint64_t octets;
121 uint64_t doorbell;
122} cvmx_pko_port_status_t;
123
124/**
125 * This structure defines the address to use on a packet enqueue
126 */
127typedef union {
128 uint64_t u64;
129 struct {
130 /* Must CVMX_IO_SEG */
131 uint64_t mem_space:2;
132 /* Must be zero */
133 uint64_t reserved:13;
134 /* Must be one */
135 uint64_t is_io:1;
136 /* The ID of the device on the non-coherent bus */
137 uint64_t did:8;
138 /* Must be zero */
139 uint64_t reserved2:4;
140 /* Must be zero */
141 uint64_t reserved3:18;
142 /*
143 * The hardware likes to have the output port in
144 * addition to the output queue,
145 */
146 uint64_t port:6;
147 /*
148 * The output queue to send the packet to (0-127 are
149 * legal)
150 */
151 uint64_t queue:9;
152 /* Must be zero */
153 uint64_t reserved4:3;
154 } s;
155} cvmx_pko_doorbell_address_t;
156
157/**
158 * Structure of the first packet output command word.
159 */
160typedef union {
161 uint64_t u64;
162 struct {
163 /*
164 * The size of the reg1 operation - could be 8, 16,
165 * 32, or 64 bits.
166 */
167 uint64_t size1:2;
168 /*
169 * The size of the reg0 operation - could be 8, 16,
170 * 32, or 64 bits.
171 */
172 uint64_t size0:2;
173 /*
174 * If set, subtract 1, if clear, subtract packet
175 * size.
176 */
177 uint64_t subone1:1;
178 /*
179 * The register, subtract will be done if reg1 is
180 * non-zero.
181 */
182 uint64_t reg1:11;
183 /* If set, subtract 1, if clear, subtract packet size */
184 uint64_t subone0:1;
185 /* The register, subtract will be done if reg0 is non-zero */
186 uint64_t reg0:11;
187 /*
188 * When set, interpret segment pointer and segment
189 * bytes in little endian order.
190 */
191 uint64_t le:1;
192 /*
193 * When set, packet data not allocated in L2 cache by
194 * PKO.
195 */
196 uint64_t n2:1;
197 /*
198 * If set and rsp is set, word3 contains a pointer to
199 * a work queue entry.
200 */
201 uint64_t wqp:1;
202 /* If set, the hardware will send a response when done */
203 uint64_t rsp:1;
204 /*
205 * If set, the supplied pkt_ptr is really a pointer to
206 * a list of pkt_ptr's.
207 */
208 uint64_t gather:1;
209 /*
210 * If ipoffp1 is non zero, (ipoffp1-1) is the number
211 * of bytes to IP header, and the hardware will
212 * calculate and insert the UDP/TCP checksum.
213 */
214 uint64_t ipoffp1:7;
215 /*
216 * If set, ignore the I bit (force to zero) from all
217 * pointer structures.
218 */
219 uint64_t ignore_i:1;
220 /*
221 * If clear, the hardware will attempt to free the
222 * buffers containing the packet.
223 */
224 uint64_t dontfree:1;
225 /*
226 * The total number of segs in the packet, if gather
227 * set, also gather list length.
228 */
229 uint64_t segs:6;
230 /* Including L2, but no trailing CRC */
231 uint64_t total_bytes:16;
232 } s;
233} cvmx_pko_command_word0_t;
234
235/* CSR typedefs have been moved to cvmx-csr-*.h */
236
237/**
238 * Definition of internal state for Packet output processing
239 */
240typedef struct {
241 /* ptr to start of buffer, offset kept in FAU reg */
242 uint64_t *start_ptr;
243} cvmx_pko_state_elem_t;
244
245/**
246 * Call before any other calls to initialize the packet
247 * output system.
248 */
249extern void cvmx_pko_initialize_global(void);
250extern int cvmx_pko_initialize_local(void);
251
252/**
253 * Enables the packet output hardware. It must already be
254 * configured.
255 */
256extern void cvmx_pko_enable(void);
257
258/**
259 * Disables the packet output. Does not affect any configuration.
260 */
261extern void cvmx_pko_disable(void);
262
263/**
264 * Shutdown and free resources required by packet output.
265 */
266
267extern void cvmx_pko_shutdown(void);
268
269/**
270 * Configure a output port and the associated queues for use.
271 *
272 * @port: Port to configure.
273 * @base_queue: First queue number to associate with this port.
274 * @num_queues: Number of queues t oassociate with this port
275 * @priority: Array of priority levels for each queue. Values are
276 * allowed to be 1-8. A value of 8 get 8 times the traffic
277 * of a value of 1. There must be num_queues elements in the
278 * array.
279 */
280extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
281 uint64_t base_queue,
282 uint64_t num_queues,
283 const uint64_t priority[]);
284
285/**
286 * Ring the packet output doorbell. This tells the packet
287 * output hardware that "len" command words have been added
288 * to its pending list. This command includes the required
289 * CVMX_SYNCWS before the doorbell ring.
290 *
291 * @port: Port the packet is for
292 * @queue: Queue the packet is for
293 * @len: Length of the command in 64 bit words
294 */
295static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue,
296 uint64_t len)
297{
298 cvmx_pko_doorbell_address_t ptr;
299
300 ptr.u64 = 0;
301 ptr.s.mem_space = CVMX_IO_SEG;
302 ptr.s.did = CVMX_OCT_DID_PKT_SEND;
303 ptr.s.is_io = 1;
304 ptr.s.port = port;
305 ptr.s.queue = queue;
306 /*
307 * Need to make sure output queue data is in DRAM before
308 * doorbell write.
309 */
310 CVMX_SYNCWS;
311 cvmx_write_io(ptr.u64, len);
312}
313
314/**
315 * Prepare to send a packet. This may initiate a tag switch to
316 * get exclusive access to the output queue structure, and
317 * performs other prep work for the packet send operation.
318 *
319 * cvmx_pko_send_packet_finish() MUST be called after this function is called,
320 * and must be called with the same port/queue/use_locking arguments.
321 *
322 * The use_locking parameter allows the caller to use three
323 * possible locking modes.
324 * - CVMX_PKO_LOCK_NONE
325 * - PKO doesn't do any locking. It is the responsibility
326 * of the application to make sure that no other core
327 * is accessing the same queue at the same time.
328 * - CVMX_PKO_LOCK_ATOMIC_TAG
329 * - PKO performs an atomic tagswitch to insure exclusive
330 * access to the output queue. This will maintain
331 * packet ordering on output.
332 * - CVMX_PKO_LOCK_CMD_QUEUE
333 * - PKO uses the common command queue locks to insure
334 * exclusive access to the output queue. This is a
335 * memory based ll/sc. This is the most portable
336 * locking mechanism.
337 *
338 * NOTE: If atomic locking is used, the POW entry CANNOT be
339 * descheduled, as it does not contain a valid WQE pointer.
340 *
341 * @port: Port to send it on
342 * @queue: Queue to use
343 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
344 * CVMX_PKO_LOCK_CMD_QUEUE
345 */
346
347static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
348 cvmx_pko_lock_t use_locking)
349{
350 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) {
351 /*
352 * Must do a full switch here to handle all cases. We
353 * use a fake WQE pointer, as the POW does not access
354 * this memory. The WQE pointer and group are only
355 * used if this work is descheduled, which is not
356 * supported by the
357 * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish
358 * combination. Note that this is a special case in
359 * which these fake values can be used - this is not a
360 * general technique.
361 */
362 uint32_t tag =
363 CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT |
364 CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT |
365 (CVMX_TAG_SUBGROUP_MASK & queue);
366 cvmx_pow_tag_sw_full((cvmx_wqe_t *) cvmx_phys_to_ptr(0x80), tag,
367 CVMX_POW_TAG_TYPE_ATOMIC, 0);
368 }
369}
370
371/**
372 * Complete packet output. cvmx_pko_send_packet_prepare() must be
373 * called exactly once before this, and the same parameters must be
374 * passed to both cvmx_pko_send_packet_prepare() and
375 * cvmx_pko_send_packet_finish().
376 *
377 * @port: Port to send it on
378 * @queue: Queue to use
379 * @pko_command:
380 * PKO HW command word
381 * @packet: Packet to send
382 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
383 * CVMX_PKO_LOCK_CMD_QUEUE
384 *
385 * Returns returns CVMX_PKO_SUCCESS on success, or error code on
386 * failure of output
387 */
388static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
389 uint64_t port,
390 uint64_t queue,
391 cvmx_pko_command_word0_t pko_command,
392 union cvmx_buf_ptr packet,
393 cvmx_pko_lock_t use_locking)
394{
395 cvmx_cmd_queue_result_t result;
396 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
397 cvmx_pow_tag_sw_wait();
398 result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
399 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
400 pko_command.u64, packet.u64);
401 if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
402 cvmx_pko_doorbell(port, queue, 2);
403 return CVMX_PKO_SUCCESS;
404 } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
405 || (result == CVMX_CMD_QUEUE_FULL)) {
406 return CVMX_PKO_NO_MEMORY;
407 } else {
408 return CVMX_PKO_INVALID_QUEUE;
409 }
410}
411
412/**
413 * Complete packet output. cvmx_pko_send_packet_prepare() must be
414 * called exactly once before this, and the same parameters must be
415 * passed to both cvmx_pko_send_packet_prepare() and
416 * cvmx_pko_send_packet_finish().
417 *
418 * @port: Port to send it on
419 * @queue: Queue to use
420 * @pko_command:
421 * PKO HW command word
422 * @packet: Packet to send
423 * @addr: Plysical address of a work queue entry or physical address
424 * to zero on complete.
425 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
426 * CVMX_PKO_LOCK_CMD_QUEUE
427 *
428 * Returns returns CVMX_PKO_SUCCESS on success, or error code on
429 * failure of output
430 */
431static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(
432 uint64_t port,
433 uint64_t queue,
434 cvmx_pko_command_word0_t pko_command,
435 union cvmx_buf_ptr packet,
436 uint64_t addr,
437 cvmx_pko_lock_t use_locking)
438{
439 cvmx_cmd_queue_result_t result;
440 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
441 cvmx_pow_tag_sw_wait();
442 result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
443 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
444 pko_command.u64, packet.u64, addr);
445 if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
446 cvmx_pko_doorbell(port, queue, 3);
447 return CVMX_PKO_SUCCESS;
448 } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
449 || (result == CVMX_CMD_QUEUE_FULL)) {
450 return CVMX_PKO_NO_MEMORY;
451 } else {
452 return CVMX_PKO_INVALID_QUEUE;
453 }
454}
455
456/**
457 * Return the pko output queue associated with a port and a specific core.
458 * In normal mode (PKO lockless operation is disabled), the value returned
459 * is the base queue.
460 *
461 * @port: Port number
462 * @core: Core to get queue for
463 *
464 * Returns Core-specific output queue
465 */
466static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
467{
468#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
469#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
470#endif
471#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
472#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
473#endif
474
475 if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
476 return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
477 else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
478 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
479 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port -
480 16) *
481 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core;
482 else if ((port >= 32) && (port < 36))
483 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
484 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
485 CVMX_PKO_MAX_PORTS_INTERFACE1 *
486 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port -
487 32) *
488 CVMX_PKO_QUEUES_PER_PORT_PCI;
489 else if ((port >= 36) && (port < 40))
490 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
491 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
492 CVMX_PKO_MAX_PORTS_INTERFACE1 *
493 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
494 4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port -
495 36) *
496 CVMX_PKO_QUEUES_PER_PORT_LOOP;
497 else
498 /* Given the limit on the number of ports we can map to
499 * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
500 * divided among all cores), the remaining unmapped ports
501 * are assigned an illegal queue number */
502 return CVMX_PKO_ILLEGAL_QUEUE;
503}
504
505/**
506 * For a given port number, return the base pko output queue
507 * for the port.
508 *
509 * @port: Port number
510 * Returns Base output queue
511 */
512static inline int cvmx_pko_get_base_queue(int port)
513{
514 return cvmx_pko_get_base_queue_per_core(port, 0);
515}
516
517/**
518 * For a given port number, return the number of pko output queues.
519 *
520 * @port: Port number
521 * Returns Number of output queues
522 */
523static inline int cvmx_pko_get_num_queues(int port)
524{
525 if (port < 16)
526 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
527 else if (port < 32)
528 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
529 else if (port < 36)
530 return CVMX_PKO_QUEUES_PER_PORT_PCI;
531 else if (port < 40)
532 return CVMX_PKO_QUEUES_PER_PORT_LOOP;
533 else
534 return 0;
535}
536
537/**
538 * Get the status counters for a port.
539 *
540 * @port_num: Port number to get statistics for.
541 * @clear: Set to 1 to clear the counters after they are read
542 * @status: Where to put the results.
543 */
544static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
545 cvmx_pko_port_status_t *status)
546{
547 union cvmx_pko_reg_read_idx pko_reg_read_idx;
548 union cvmx_pko_mem_count0 pko_mem_count0;
549 union cvmx_pko_mem_count1 pko_mem_count1;
550
551 pko_reg_read_idx.u64 = 0;
552 pko_reg_read_idx.s.index = port_num;
553 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
554
555 pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
556 status->packets = pko_mem_count0.s.count;
557 if (clear) {
558 pko_mem_count0.s.count = port_num;
559 cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
560 }
561
562 pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
563 status->octets = pko_mem_count1.s.count;
564 if (clear) {
565 pko_mem_count1.s.count = port_num;
566 cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
567 }
568
569 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
570 union cvmx_pko_mem_debug9 debug9;
571 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
572 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
573 debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
574 status->doorbell = debug9.cn38xx.doorbell;
575 } else {
576 union cvmx_pko_mem_debug8 debug8;
577 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
578 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
579 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
580 status->doorbell = debug8.cn58xx.doorbell;
581 }
582}
583
584/**
585 * Rate limit a PKO port to a max packets/sec. This function is only
586 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
587 *
588 * @port: Port to rate limit
589 * @packets_s: Maximum packet/sec
590 * @burst: Maximum number of packets to burst in a row before rate
591 * limiting cuts in.
592 *
593 * Returns Zero on success, negative on failure
594 */
595extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
596
597/**
598 * Rate limit a PKO port to a max bits/sec. This function is only
599 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
600 *
601 * @port: Port to rate limit
602 * @bits_s: PKO rate limit in bits/sec
603 * @burst: Maximum number of bits to burst before rate
604 * limiting cuts in.
605 *
606 * Returns Zero on success, negative on failure
607 */
608extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
609
610#endif /* __CVMX_PKO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
new file mode 100644
index 000000000000..999aefe3274c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
@@ -0,0 +1,1982 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * Interface to the hardware Packet Order / Work unit.
30 *
31 * New, starting with SDK 1.7.0, cvmx-pow supports a number of
32 * extended consistency checks. The define
33 * CVMX_ENABLE_POW_CHECKS controls the runtime insertion of POW
34 * internal state checks to find common programming errors. If
35 * CVMX_ENABLE_POW_CHECKS is not defined, checks are by default
36 * enabled. For example, cvmx-pow will check for the following
37 * program errors or POW state inconsistency.
38 * - Requesting a POW operation with an active tag switch in
39 * progress.
40 * - Waiting for a tag switch to complete for an excessively
41 * long period. This is normally a sign of an error in locking
42 * causing deadlock.
43 * - Illegal tag switches from NULL_NULL.
44 * - Illegal tag switches from NULL.
45 * - Illegal deschedule request.
46 * - WQE pointer not matching the one attached to the core by
47 * the POW.
48 *
49 */
50
51#ifndef __CVMX_POW_H__
52#define __CVMX_POW_H__
53
54#include <asm/octeon/cvmx-pow-defs.h>
55
56#include "cvmx-scratch.h"
57#include "cvmx-wqe.h"
58
59/* Default to having all POW constancy checks turned on */
60#ifndef CVMX_ENABLE_POW_CHECKS
61#define CVMX_ENABLE_POW_CHECKS 1
62#endif
63
64enum cvmx_pow_tag_type {
65 /* Tag ordering is maintained */
66 CVMX_POW_TAG_TYPE_ORDERED = 0L,
67 /* Tag ordering is maintained, and at most one PP has the tag */
68 CVMX_POW_TAG_TYPE_ATOMIC = 1L,
69 /*
70 * The work queue entry from the order - NEVER tag switch from
71 * NULL to NULL
72 */
73 CVMX_POW_TAG_TYPE_NULL = 2L,
74 /* A tag switch to NULL, and there is no space reserved in POW
75 * - NEVER tag switch to NULL_NULL
76 * - NEVER tag switch from NULL_NULL
77 * - NULL_NULL is entered at the beginning of time and on a deschedule.
78 * - NULL_NULL can be exited by a new work request. A NULL_SWITCH
79 * load can also switch the state to NULL
80 */
81 CVMX_POW_TAG_TYPE_NULL_NULL = 3L
82};
83
84/**
85 * Wait flag values for pow functions.
86 */
87typedef enum {
88 CVMX_POW_WAIT = 1,
89 CVMX_POW_NO_WAIT = 0,
90} cvmx_pow_wait_t;
91
92/**
93 * POW tag operations. These are used in the data stored to the POW.
94 */
95typedef enum {
96 /*
97 * switch the tag (only) for this PP
98 * - the previous tag should be non-NULL in this case
99 * - tag switch response required
100 * - fields used: op, type, tag
101 */
102 CVMX_POW_TAG_OP_SWTAG = 0L,
103 /*
104 * switch the tag for this PP, with full information
105 * - this should be used when the previous tag is NULL
106 * - tag switch response required
107 * - fields used: address, op, grp, type, tag
108 */
109 CVMX_POW_TAG_OP_SWTAG_FULL = 1L,
110 /*
111 * switch the tag (and/or group) for this PP and de-schedule
112 * - OK to keep the tag the same and only change the group
113 * - fields used: op, no_sched, grp, type, tag
114 */
115 CVMX_POW_TAG_OP_SWTAG_DESCH = 2L,
116 /*
117 * just de-schedule
118 * - fields used: op, no_sched
119 */
120 CVMX_POW_TAG_OP_DESCH = 3L,
121 /*
122 * create an entirely new work queue entry
123 * - fields used: address, op, qos, grp, type, tag
124 */
125 CVMX_POW_TAG_OP_ADDWQ = 4L,
126 /*
127 * just update the work queue pointer and grp for this PP
128 * - fields used: address, op, grp
129 */
130 CVMX_POW_TAG_OP_UPDATE_WQP_GRP = 5L,
131 /*
132 * set the no_sched bit on the de-schedule list
133 *
134 * - does nothing if the selected entry is not on the
135 * de-schedule list
136 *
137 * - does nothing if the stored work queue pointer does not
138 * match the address field
139 *
140 * - fields used: address, index, op
141 *
142 * Before issuing a *_NSCHED operation, SW must guarantee
143 * that all prior deschedules and set/clr NSCHED operations
144 * are complete and all prior switches are complete. The
145 * hardware provides the opsdone bit and swdone bit for SW
146 * polling. After issuing a *_NSCHED operation, SW must
147 * guarantee that the set/clr NSCHED is complete before any
148 * subsequent operations.
149 */
150 CVMX_POW_TAG_OP_SET_NSCHED = 6L,
151 /*
152 * clears the no_sched bit on the de-schedule list
153 *
154 * - does nothing if the selected entry is not on the
155 * de-schedule list
156 *
157 * - does nothing if the stored work queue pointer does not
158 * match the address field
159 *
160 * - fields used: address, index, op
161 *
162 * Before issuing a *_NSCHED operation, SW must guarantee that
163 * all prior deschedules and set/clr NSCHED operations are
164 * complete and all prior switches are complete. The hardware
165 * provides the opsdone bit and swdone bit for SW
166 * polling. After issuing a *_NSCHED operation, SW must
167 * guarantee that the set/clr NSCHED is complete before any
168 * subsequent operations.
169 */
170 CVMX_POW_TAG_OP_CLR_NSCHED = 7L,
171 /* do nothing */
172 CVMX_POW_TAG_OP_NOP = 15L
173} cvmx_pow_tag_op_t;
174
175/**
176 * This structure defines the store data on a store to POW
177 */
178typedef union {
179 uint64_t u64;
180 struct {
181 /*
182 * Don't reschedule this entry. no_sched is used for
183 * CVMX_POW_TAG_OP_SWTAG_DESCH and
184 * CVMX_POW_TAG_OP_DESCH
185 */
186 uint64_t no_sched:1;
187 uint64_t unused:2;
188 /* Tontains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */
189 uint64_t index:13;
190 /* The operation to perform */
191 cvmx_pow_tag_op_t op:4;
192 uint64_t unused2:2;
193 /*
194 * The QOS level for the packet. qos is only used for
195 * CVMX_POW_TAG_OP_ADDWQ
196 */
197 uint64_t qos:3;
198 /*
199 * The group that the work queue entry will be
200 * scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ,
201 * CVMX_POW_TAG_OP_SWTAG_FULL,
202 * CVMX_POW_TAG_OP_SWTAG_DESCH, and
203 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP
204 */
205 uint64_t grp:4;
206 /*
207 * The type of the tag. type is used for everything
208 * except CVMX_POW_TAG_OP_DESCH,
209 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
210 * CVMX_POW_TAG_OP_*_NSCHED
211 */
212 uint64_t type:3;
213 /*
214 * The actual tag. tag is used for everything except
215 * CVMX_POW_TAG_OP_DESCH,
216 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
217 * CVMX_POW_TAG_OP_*_NSCHED
218 */
219 uint64_t tag:32;
220 } s;
221} cvmx_pow_tag_req_t;
222
223/**
224 * This structure describes the address to load stuff from POW
225 */
226typedef union {
227 uint64_t u64;
228
229 /**
230 * Address for new work request loads (did<2:0> == 0)
231 */
232 struct {
233 /* Mips64 address region. Should be CVMX_IO_SEG */
234 uint64_t mem_region:2;
235 /* Must be zero */
236 uint64_t reserved_49_61:13;
237 /* Must be one */
238 uint64_t is_io:1;
239 /* the ID of POW -- did<2:0> == 0 in this case */
240 uint64_t did:8;
241 /* Must be zero */
242 uint64_t reserved_4_39:36;
243 /*
244 * If set, don't return load response until work is
245 * available.
246 */
247 uint64_t wait:1;
248 /* Must be zero */
249 uint64_t reserved_0_2:3;
250 } swork;
251
252 /**
253 * Address for loads to get POW internal status
254 */
255 struct {
256 /* Mips64 address region. Should be CVMX_IO_SEG */
257 uint64_t mem_region:2;
258 /* Must be zero */
259 uint64_t reserved_49_61:13;
260 /* Must be one */
261 uint64_t is_io:1;
262 /* the ID of POW -- did<2:0> == 1 in this case */
263 uint64_t did:8;
264 /* Must be zero */
265 uint64_t reserved_10_39:30;
266 /* The core id to get status for */
267 uint64_t coreid:4;
268 /*
269 * If set and get_cur is set, return reverse tag-list
270 * pointer rather than forward tag-list pointer.
271 */
272 uint64_t get_rev:1;
273 /*
274 * If set, return current status rather than pending
275 * status.
276 */
277 uint64_t get_cur:1;
278 /*
279 * If set, get the work-queue pointer rather than
280 * tag/type.
281 */
282 uint64_t get_wqp:1;
283 /* Must be zero */
284 uint64_t reserved_0_2:3;
285 } sstatus;
286
287 /**
288 * Address for memory loads to get POW internal state
289 */
290 struct {
291 /* Mips64 address region. Should be CVMX_IO_SEG */
292 uint64_t mem_region:2;
293 /* Must be zero */
294 uint64_t reserved_49_61:13;
295 /* Must be one */
296 uint64_t is_io:1;
297 /* the ID of POW -- did<2:0> == 2 in this case */
298 uint64_t did:8;
299 /* Must be zero */
300 uint64_t reserved_16_39:24;
301 /* POW memory index */
302 uint64_t index:11;
303 /*
304 * If set, return deschedule information rather than
305 * the standard response for work-queue index (invalid
306 * if the work-queue entry is not on the deschedule
307 * list).
308 */
309 uint64_t get_des:1;
310 /*
311 * If set, get the work-queue pointer rather than
312 * tag/type (no effect when get_des set).
313 */
314 uint64_t get_wqp:1;
315 /* Must be zero */
316 uint64_t reserved_0_2:3;
317 } smemload;
318
319 /**
320 * Address for index/pointer loads
321 */
322 struct {
323 /* Mips64 address region. Should be CVMX_IO_SEG */
324 uint64_t mem_region:2;
325 /* Must be zero */
326 uint64_t reserved_49_61:13;
327 /* Must be one */
328 uint64_t is_io:1;
329 /* the ID of POW -- did<2:0> == 3 in this case */
330 uint64_t did:8;
331 /* Must be zero */
332 uint64_t reserved_9_39:31;
333 /*
334 * when {get_rmt ==0 AND get_des_get_tail == 0}, this
335 * field selects one of eight POW internal-input
336 * queues (0-7), one per QOS level; values 8-15 are
337 * illegal in this case; when {get_rmt ==0 AND
338 * get_des_get_tail == 1}, this field selects one of
339 * 16 deschedule lists (per group); when get_rmt ==1,
340 * this field selects one of 16 memory-input queue
341 * lists. The two memory-input queue lists associated
342 * with each QOS level are:
343 *
344 * - qosgrp = 0, qosgrp = 8: QOS0
345 * - qosgrp = 1, qosgrp = 9: QOS1
346 * - qosgrp = 2, qosgrp = 10: QOS2
347 * - qosgrp = 3, qosgrp = 11: QOS3
348 * - qosgrp = 4, qosgrp = 12: QOS4
349 * - qosgrp = 5, qosgrp = 13: QOS5
350 * - qosgrp = 6, qosgrp = 14: QOS6
351 * - qosgrp = 7, qosgrp = 15: QOS7
352 */
353 uint64_t qosgrp:4;
354 /*
355 * If set and get_rmt is clear, return deschedule list
356 * indexes rather than indexes for the specified qos
357 * level; if set and get_rmt is set, return the tail
358 * pointer rather than the head pointer for the
359 * specified qos level.
360 */
361 uint64_t get_des_get_tail:1;
362 /*
363 * If set, return remote pointers rather than the
364 * local indexes for the specified qos level.
365 */
366 uint64_t get_rmt:1;
367 /* Must be zero */
368 uint64_t reserved_0_2:3;
369 } sindexload;
370
371 /**
372 * address for NULL_RD request (did<2:0> == 4) when this is read,
373 * HW attempts to change the state to NULL if it is NULL_NULL (the
374 * hardware cannot switch from NULL_NULL to NULL if a POW entry is
375 * not available - software may need to recover by finishing
376 * another piece of work before a POW entry can ever become
377 * available.)
378 */
379 struct {
380 /* Mips64 address region. Should be CVMX_IO_SEG */
381 uint64_t mem_region:2;
382 /* Must be zero */
383 uint64_t reserved_49_61:13;
384 /* Must be one */
385 uint64_t is_io:1;
386 /* the ID of POW -- did<2:0> == 4 in this case */
387 uint64_t did:8;
388 /* Must be zero */
389 uint64_t reserved_0_39:40;
390 } snull_rd;
391} cvmx_pow_load_addr_t;
392
393/**
394 * This structure defines the response to a load/SENDSINGLE to POW
395 * (except CSR reads)
396 */
397typedef union {
398 uint64_t u64;
399
400 /**
401 * Response to new work request loads
402 */
403 struct {
404 /*
405 * Set when no new work queue entry was returned. *
406 * If there was de-scheduled work, the HW will
407 * definitely return it. When this bit is set, it
408 * could mean either mean:
409 *
410 * - There was no work, or
411 *
412 * - There was no work that the HW could find. This
413 * case can happen, regardless of the wait bit value
414 * in the original request, when there is work in
415 * the IQ's that is too deep down the list.
416 */
417 uint64_t no_work:1;
418 /* Must be zero */
419 uint64_t reserved_40_62:23;
420 /* 36 in O1 -- the work queue pointer */
421 uint64_t addr:40;
422 } s_work;
423
424 /**
425 * Result for a POW Status Load (when get_cur==0 and get_wqp==0)
426 */
427 struct {
428 uint64_t reserved_62_63:2;
429 /* Set when there is a pending non-NULL SWTAG or
430 * SWTAG_FULL, and the POW entry has not left the list
431 * for the original tag. */
432 uint64_t pend_switch:1;
433 /* Set when SWTAG_FULL and pend_switch is set. */
434 uint64_t pend_switch_full:1;
435 /*
436 * Set when there is a pending NULL SWTAG, or an
437 * implicit switch to NULL.
438 */
439 uint64_t pend_switch_null:1;
440 /* Set when there is a pending DESCHED or SWTAG_DESCHED. */
441 uint64_t pend_desched:1;
442 /*
443 * Set when there is a pending SWTAG_DESCHED and
444 * pend_desched is set.
445 */
446 uint64_t pend_desched_switch:1;
447 /* Set when nosched is desired and pend_desched is set. */
448 uint64_t pend_nosched:1;
449 /* Set when there is a pending GET_WORK. */
450 uint64_t pend_new_work:1;
451 /*
452 * When pend_new_work is set, this bit indicates that
453 * the wait bit was set.
454 */
455 uint64_t pend_new_work_wait:1;
456 /* Set when there is a pending NULL_RD. */
457 uint64_t pend_null_rd:1;
458 /* Set when there is a pending CLR_NSCHED. */
459 uint64_t pend_nosched_clr:1;
460 uint64_t reserved_51:1;
461 /* This is the index when pend_nosched_clr is set. */
462 uint64_t pend_index:11;
463 /*
464 * This is the new_grp when (pend_desched AND
465 * pend_desched_switch) is set.
466 */
467 uint64_t pend_grp:4;
468 uint64_t reserved_34_35:2;
469 /*
470 * This is the tag type when pend_switch or
471 * (pend_desched AND pend_desched_switch) are set.
472 */
473 uint64_t pend_type:2;
474 /*
475 * - this is the tag when pend_switch or (pend_desched
476 * AND pend_desched_switch) are set.
477 */
478 uint64_t pend_tag:32;
479 } s_sstatus0;
480
481 /**
482 * Result for a POW Status Load (when get_cur==0 and get_wqp==1)
483 */
484 struct {
485 uint64_t reserved_62_63:2;
486 /*
487 * Set when there is a pending non-NULL SWTAG or
488 * SWTAG_FULL, and the POW entry has not left the list
489 * for the original tag.
490 */
491 uint64_t pend_switch:1;
492 /* Set when SWTAG_FULL and pend_switch is set. */
493 uint64_t pend_switch_full:1;
494 /*
495 * Set when there is a pending NULL SWTAG, or an
496 * implicit switch to NULL.
497 */
498 uint64_t pend_switch_null:1;
499 /*
500 * Set when there is a pending DESCHED or
501 * SWTAG_DESCHED.
502 */
503 uint64_t pend_desched:1;
504 /*
505 * Set when there is a pending SWTAG_DESCHED and
506 * pend_desched is set.
507 */
508 uint64_t pend_desched_switch:1;
509 /* Set when nosched is desired and pend_desched is set. */
510 uint64_t pend_nosched:1;
511 /* Set when there is a pending GET_WORK. */
512 uint64_t pend_new_work:1;
513 /*
514 * When pend_new_work is set, this bit indicates that
515 * the wait bit was set.
516 */
517 uint64_t pend_new_work_wait:1;
518 /* Set when there is a pending NULL_RD. */
519 uint64_t pend_null_rd:1;
520 /* Set when there is a pending CLR_NSCHED. */
521 uint64_t pend_nosched_clr:1;
522 uint64_t reserved_51:1;
523 /* This is the index when pend_nosched_clr is set. */
524 uint64_t pend_index:11;
525 /*
526 * This is the new_grp when (pend_desched AND
527 * pend_desched_switch) is set.
528 */
529 uint64_t pend_grp:4;
530 /* This is the wqp when pend_nosched_clr is set. */
531 uint64_t pend_wqp:36;
532 } s_sstatus1;
533
534 /**
535 * Result for a POW Status Load (when get_cur==1, get_wqp==0, and
536 * get_rev==0)
537 */
538 struct {
539 uint64_t reserved_62_63:2;
540 /*
541 * Points to the next POW entry in the tag list when
542 * tail == 0 (and tag_type is not NULL or NULL_NULL).
543 */
544 uint64_t link_index:11;
545 /* The POW entry attached to the core. */
546 uint64_t index:11;
547 /*
548 * The group attached to the core (updated when new
549 * tag list entered on SWTAG_FULL).
550 */
551 uint64_t grp:4;
552 /*
553 * Set when this POW entry is at the head of its tag
554 * list (also set when in the NULL or NULL_NULL
555 * state).
556 */
557 uint64_t head:1;
558 /*
559 * Set when this POW entry is at the tail of its tag
560 * list (also set when in the NULL or NULL_NULL
561 * state).
562 */
563 uint64_t tail:1;
564 /*
565 * The tag type attached to the core (updated when new
566 * tag list entered on SWTAG, SWTAG_FULL, or
567 * SWTAG_DESCHED).
568 */
569 uint64_t tag_type:2;
570 /*
571 * The tag attached to the core (updated when new tag
572 * list entered on SWTAG, SWTAG_FULL, or
573 * SWTAG_DESCHED).
574 */
575 uint64_t tag:32;
576 } s_sstatus2;
577
578 /**
579 * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1)
580 */
581 struct {
582 uint64_t reserved_62_63:2;
583 /*
584 * Points to the prior POW entry in the tag list when
585 * head == 0 (and tag_type is not NULL or
586 * NULL_NULL). This field is unpredictable when the
587 * core's state is NULL or NULL_NULL.
588 */
589 uint64_t revlink_index:11;
590 /* The POW entry attached to the core. */
591 uint64_t index:11;
592 /*
593 * The group attached to the core (updated when new
594 * tag list entered on SWTAG_FULL).
595 */
596 uint64_t grp:4;
597 /* Set when this POW entry is at the head of its tag
598 * list (also set when in the NULL or NULL_NULL
599 * state).
600 */
601 uint64_t head:1;
602 /*
603 * Set when this POW entry is at the tail of its tag
604 * list (also set when in the NULL or NULL_NULL
605 * state).
606 */
607 uint64_t tail:1;
608 /*
609 * The tag type attached to the core (updated when new
610 * tag list entered on SWTAG, SWTAG_FULL, or
611 * SWTAG_DESCHED).
612 */
613 uint64_t tag_type:2;
614 /*
615 * The tag attached to the core (updated when new tag
616 * list entered on SWTAG, SWTAG_FULL, or
617 * SWTAG_DESCHED).
618 */
619 uint64_t tag:32;
620 } s_sstatus3;
621
622 /**
623 * Result for a POW Status Load (when get_cur==1, get_wqp==1, and
624 * get_rev==0)
625 */
626 struct {
627 uint64_t reserved_62_63:2;
628 /*
629 * Points to the next POW entry in the tag list when
630 * tail == 0 (and tag_type is not NULL or NULL_NULL).
631 */
632 uint64_t link_index:11;
633 /* The POW entry attached to the core. */
634 uint64_t index:11;
635 /*
636 * The group attached to the core (updated when new
637 * tag list entered on SWTAG_FULL).
638 */
639 uint64_t grp:4;
640 /*
641 * The wqp attached to the core (updated when new tag
642 * list entered on SWTAG_FULL).
643 */
644 uint64_t wqp:36;
645 } s_sstatus4;
646
647 /**
648 * Result for a POW Status Load (when get_cur==1, get_wqp==1, and
649 * get_rev==1)
650 */
651 struct {
652 uint64_t reserved_62_63:2;
653 /*
654 * Points to the prior POW entry in the tag list when
655 * head == 0 (and tag_type is not NULL or
656 * NULL_NULL). This field is unpredictable when the
657 * core's state is NULL or NULL_NULL.
658 */
659 uint64_t revlink_index:11;
660 /* The POW entry attached to the core. */
661 uint64_t index:11;
662 /*
663 * The group attached to the core (updated when new
664 * tag list entered on SWTAG_FULL).
665 */
666 uint64_t grp:4;
667 /*
668 * The wqp attached to the core (updated when new tag
669 * list entered on SWTAG_FULL).
670 */
671 uint64_t wqp:36;
672 } s_sstatus5;
673
674 /**
675 * Result For POW Memory Load (get_des == 0 and get_wqp == 0)
676 */
677 struct {
678 uint64_t reserved_51_63:13;
679 /*
680 * The next entry in the input, free, descheduled_head
681 * list (unpredictable if entry is the tail of the
682 * list).
683 */
684 uint64_t next_index:11;
685 /* The group of the POW entry. */
686 uint64_t grp:4;
687 uint64_t reserved_35:1;
688 /*
689 * Set when this POW entry is at the tail of its tag
690 * list (also set when in the NULL or NULL_NULL
691 * state).
692 */
693 uint64_t tail:1;
694 /* The tag type of the POW entry. */
695 uint64_t tag_type:2;
696 /* The tag of the POW entry. */
697 uint64_t tag:32;
698 } s_smemload0;
699
700 /**
701 * Result For POW Memory Load (get_des == 0 and get_wqp == 1)
702 */
703 struct {
704 uint64_t reserved_51_63:13;
705 /*
706 * The next entry in the input, free, descheduled_head
707 * list (unpredictable if entry is the tail of the
708 * list).
709 */
710 uint64_t next_index:11;
711 /* The group of the POW entry. */
712 uint64_t grp:4;
713 /* The WQP held in the POW entry. */
714 uint64_t wqp:36;
715 } s_smemload1;
716
717 /**
718 * Result For POW Memory Load (get_des == 1)
719 */
720 struct {
721 uint64_t reserved_51_63:13;
722 /*
723 * The next entry in the tag list connected to the
724 * descheduled head.
725 */
726 uint64_t fwd_index:11;
727 /* The group of the POW entry. */
728 uint64_t grp:4;
729 /* The nosched bit for the POW entry. */
730 uint64_t nosched:1;
731 /* There is a pending tag switch */
732 uint64_t pend_switch:1;
733 /*
734 * The next tag type for the new tag list when
735 * pend_switch is set.
736 */
737 uint64_t pend_type:2;
738 /*
739 * The next tag for the new tag list when pend_switch
740 * is set.
741 */
742 uint64_t pend_tag:32;
743 } s_smemload2;
744
745 /**
746 * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0)
747 */
748 struct {
749 uint64_t reserved_52_63:12;
750 /*
751 * set when there is one or more POW entries on the
752 * free list.
753 */
754 uint64_t free_val:1;
755 /*
756 * set when there is exactly one POW entry on the free
757 * list.
758 */
759 uint64_t free_one:1;
760 uint64_t reserved_49:1;
761 /*
762 * when free_val is set, indicates the first entry on
763 * the free list.
764 */
765 uint64_t free_head:11;
766 uint64_t reserved_37:1;
767 /*
768 * when free_val is set, indicates the last entry on
769 * the free list.
770 */
771 uint64_t free_tail:11;
772 /*
773 * set when there is one or more POW entries on the
774 * input Q list selected by qosgrp.
775 */
776 uint64_t loc_val:1;
777 /*
778 * set when there is exactly one POW entry on the
779 * input Q list selected by qosgrp.
780 */
781 uint64_t loc_one:1;
782 uint64_t reserved_23:1;
783 /*
784 * when loc_val is set, indicates the first entry on
785 * the input Q list selected by qosgrp.
786 */
787 uint64_t loc_head:11;
788 uint64_t reserved_11:1;
789 /*
790 * when loc_val is set, indicates the last entry on
791 * the input Q list selected by qosgrp.
792 */
793 uint64_t loc_tail:11;
794 } sindexload0;
795
796 /**
797 * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1)
798 */
799 struct {
800 uint64_t reserved_52_63:12;
801 /*
802 * set when there is one or more POW entries on the
803 * nosched list.
804 */
805 uint64_t nosched_val:1;
806 /*
807 * set when there is exactly one POW entry on the
808 * nosched list.
809 */
810 uint64_t nosched_one:1;
811 uint64_t reserved_49:1;
812 /*
813 * when nosched_val is set, indicates the first entry
814 * on the nosched list.
815 */
816 uint64_t nosched_head:11;
817 uint64_t reserved_37:1;
818 /*
819 * when nosched_val is set, indicates the last entry
820 * on the nosched list.
821 */
822 uint64_t nosched_tail:11;
823 /*
824 * set when there is one or more descheduled heads on
825 * the descheduled list selected by qosgrp.
826 */
827 uint64_t des_val:1;
828 /*
829 * set when there is exactly one descheduled head on
830 * the descheduled list selected by qosgrp.
831 */
832 uint64_t des_one:1;
833 uint64_t reserved_23:1;
834 /*
835 * when des_val is set, indicates the first
836 * descheduled head on the descheduled list selected
837 * by qosgrp.
838 */
839 uint64_t des_head:11;
840 uint64_t reserved_11:1;
841 /*
842 * when des_val is set, indicates the last descheduled
843 * head on the descheduled list selected by qosgrp.
844 */
845 uint64_t des_tail:11;
846 } sindexload1;
847
848 /**
849 * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0)
850 */
851 struct {
852 uint64_t reserved_39_63:25;
853 /*
854 * Set when this DRAM list is the current head
855 * (i.e. is the next to be reloaded when the POW
856 * hardware reloads a POW entry from DRAM). The POW
857 * hardware alternates between the two DRAM lists
858 * associated with a QOS level when it reloads work
859 * from DRAM into the POW unit.
860 */
861 uint64_t rmt_is_head:1;
862 /*
863 * Set when the DRAM portion of the input Q list
864 * selected by qosgrp contains one or more pieces of
865 * work.
866 */
867 uint64_t rmt_val:1;
868 /*
869 * Set when the DRAM portion of the input Q list
870 * selected by qosgrp contains exactly one piece of
871 * work.
872 */
873 uint64_t rmt_one:1;
874 /*
875 * When rmt_val is set, indicates the first piece of
876 * work on the DRAM input Q list selected by
877 * qosgrp.
878 */
879 uint64_t rmt_head:36;
880 } sindexload2;
881
882 /**
883 * Result For POW Index/Pointer Load (get_rmt ==
884 * 1/get_des_get_tail == 1)
885 */
886 struct {
887 uint64_t reserved_39_63:25;
888 /*
889 * set when this DRAM list is the current head
890 * (i.e. is the next to be reloaded when the POW
891 * hardware reloads a POW entry from DRAM). The POW
892 * hardware alternates between the two DRAM lists
893 * associated with a QOS level when it reloads work
894 * from DRAM into the POW unit.
895 */
896 uint64_t rmt_is_head:1;
897 /*
898 * set when the DRAM portion of the input Q list
899 * selected by qosgrp contains one or more pieces of
900 * work.
901 */
902 uint64_t rmt_val:1;
903 /*
904 * set when the DRAM portion of the input Q list
905 * selected by qosgrp contains exactly one piece of
906 * work.
907 */
908 uint64_t rmt_one:1;
909 /*
910 * when rmt_val is set, indicates the last piece of
911 * work on the DRAM input Q list selected by
912 * qosgrp.
913 */
914 uint64_t rmt_tail:36;
915 } sindexload3;
916
917 /**
918 * Response to NULL_RD request loads
919 */
920 struct {
921 uint64_t unused:62;
922 /* of type cvmx_pow_tag_type_t. state is one of the
923 * following:
924 *
925 * - CVMX_POW_TAG_TYPE_ORDERED
926 * - CVMX_POW_TAG_TYPE_ATOMIC
927 * - CVMX_POW_TAG_TYPE_NULL
928 * - CVMX_POW_TAG_TYPE_NULL_NULL
929 */
930 uint64_t state:2;
931 } s_null_rd;
932
933} cvmx_pow_tag_load_resp_t;
934
935/**
936 * This structure describes the address used for stores to the POW.
937 * The store address is meaningful on stores to the POW. The
938 * hardware assumes that an aligned 64-bit store was used for all
939 * these stores. Note the assumption that the work queue entry is
940 * aligned on an 8-byte boundary (since the low-order 3 address bits
941 * must be zero). Note that not all fields are used by all
942 * operations.
943 *
944 * NOTE: The following is the behavior of the pending switch bit at the PP
945 * for POW stores (i.e. when did<7:3> == 0xc)
946 * - did<2:0> == 0 => pending switch bit is set
947 * - did<2:0> == 1 => no affect on the pending switch bit
948 * - did<2:0> == 3 => pending switch bit is cleared
949 * - did<2:0> == 7 => no affect on the pending switch bit
950 * - did<2:0> == others => must not be used
951 * - No other loads/stores have an affect on the pending switch bit
952 * - The switch bus from POW can clear the pending switch bit
953 *
954 * NOTE: did<2:0> == 2 is used by the HW for a special single-cycle
955 * ADDWQ command that only contains the pointer). SW must never use
956 * did<2:0> == 2.
957 */
958typedef union {
959 /**
960 * Unsigned 64 bit integer representation of store address
961 */
962 uint64_t u64;
963
964 struct {
965 /* Memory region. Should be CVMX_IO_SEG in most cases */
966 uint64_t mem_reg:2;
967 uint64_t reserved_49_61:13; /* Must be zero */
968 uint64_t is_io:1; /* Must be one */
969 /* Device ID of POW. Note that different sub-dids are used. */
970 uint64_t did:8;
971 uint64_t reserved_36_39:4; /* Must be zero */
972 /* Address field. addr<2:0> must be zero */
973 uint64_t addr:36;
974 } stag;
975} cvmx_pow_tag_store_addr_t;
976
977/**
978 * decode of the store data when an IOBDMA SENDSINGLE is sent to POW
979 */
980typedef union {
981 uint64_t u64;
982
983 struct {
984 /*
985 * the (64-bit word) location in scratchpad to write
986 * to (if len != 0)
987 */
988 uint64_t scraddr:8;
989 /* the number of words in the response (0 => no response) */
990 uint64_t len:8;
991 /* the ID of the device on the non-coherent bus */
992 uint64_t did:8;
993 uint64_t unused:36;
994 /* if set, don't return load response until work is available */
995 uint64_t wait:1;
996 uint64_t unused2:3;
997 } s;
998
999} cvmx_pow_iobdma_store_t;
1000
1001/* CSR typedefs have been moved to cvmx-csr-*.h */
1002
1003/**
1004 * Get the POW tag for this core. This returns the current
1005 * tag type, tag, group, and POW entry index associated with
1006 * this core. Index is only valid if the tag type isn't NULL_NULL.
1007 * If a tag switch is pending this routine returns the tag before
1008 * the tag switch, not after.
1009 *
1010 * Returns Current tag
1011 */
1012static inline cvmx_pow_tag_req_t cvmx_pow_get_current_tag(void)
1013{
1014 cvmx_pow_load_addr_t load_addr;
1015 cvmx_pow_tag_load_resp_t load_resp;
1016 cvmx_pow_tag_req_t result;
1017
1018 load_addr.u64 = 0;
1019 load_addr.sstatus.mem_region = CVMX_IO_SEG;
1020 load_addr.sstatus.is_io = 1;
1021 load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
1022 load_addr.sstatus.coreid = cvmx_get_core_num();
1023 load_addr.sstatus.get_cur = 1;
1024 load_resp.u64 = cvmx_read_csr(load_addr.u64);
1025 result.u64 = 0;
1026 result.s.grp = load_resp.s_sstatus2.grp;
1027 result.s.index = load_resp.s_sstatus2.index;
1028 result.s.type = load_resp.s_sstatus2.tag_type;
1029 result.s.tag = load_resp.s_sstatus2.tag;
1030 return result;
1031}
1032
1033/**
1034 * Get the POW WQE for this core. This returns the work queue
1035 * entry currently associated with this core.
1036 *
1037 * Returns WQE pointer
1038 */
1039static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void)
1040{
1041 cvmx_pow_load_addr_t load_addr;
1042 cvmx_pow_tag_load_resp_t load_resp;
1043
1044 load_addr.u64 = 0;
1045 load_addr.sstatus.mem_region = CVMX_IO_SEG;
1046 load_addr.sstatus.is_io = 1;
1047 load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
1048 load_addr.sstatus.coreid = cvmx_get_core_num();
1049 load_addr.sstatus.get_cur = 1;
1050 load_addr.sstatus.get_wqp = 1;
1051 load_resp.u64 = cvmx_read_csr(load_addr.u64);
1052 return (cvmx_wqe_t *) cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp);
1053}
1054
1055#ifndef CVMX_MF_CHORD
1056#define CVMX_MF_CHORD(dest) CVMX_RDHWR(dest, 30)
1057#endif
1058
1059/**
1060 * Print a warning if a tag switch is pending for this core
1061 *
1062 * @function: Function name checking for a pending tag switch
1063 */
1064static inline void __cvmx_pow_warn_if_pending_switch(const char *function)
1065{
1066 uint64_t switch_complete;
1067 CVMX_MF_CHORD(switch_complete);
1068 if (!switch_complete)
1069 pr_warning("%s called with tag switch in progress\n", function);
1070}
1071
1072/**
1073 * Waits for a tag switch to complete by polling the completion bit.
1074 * Note that switches to NULL complete immediately and do not need
1075 * to be waited for.
1076 */
1077static inline void cvmx_pow_tag_sw_wait(void)
1078{
1079 const uint64_t MAX_CYCLES = 1ull << 31;
1080 uint64_t switch_complete;
1081 uint64_t start_cycle = cvmx_get_cycle();
1082 while (1) {
1083 CVMX_MF_CHORD(switch_complete);
1084 if (unlikely(switch_complete))
1085 break;
1086 if (unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES)) {
1087 pr_warning("Tag switch is taking a long time, "
1088 "possible deadlock\n");
1089 start_cycle = -MAX_CYCLES - 1;
1090 }
1091 }
1092}
1093
1094/**
1095 * Synchronous work request. Requests work from the POW.
1096 * This function does NOT wait for previous tag switches to complete,
1097 * so the caller must ensure that there is not a pending tag switch.
1098 *
1099 * @wait: When set, call stalls until work becomes avaiable, or times out.
1100 * If not set, returns immediately.
1101 *
1102 * Returns Returns the WQE pointer from POW. Returns NULL if no work
1103 * was available.
1104 */
1105static inline cvmx_wqe_t *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t
1106 wait)
1107{
1108 cvmx_pow_load_addr_t ptr;
1109 cvmx_pow_tag_load_resp_t result;
1110
1111 if (CVMX_ENABLE_POW_CHECKS)
1112 __cvmx_pow_warn_if_pending_switch(__func__);
1113
1114 ptr.u64 = 0;
1115 ptr.swork.mem_region = CVMX_IO_SEG;
1116 ptr.swork.is_io = 1;
1117 ptr.swork.did = CVMX_OCT_DID_TAG_SWTAG;
1118 ptr.swork.wait = wait;
1119
1120 result.u64 = cvmx_read_csr(ptr.u64);
1121
1122 if (result.s_work.no_work)
1123 return NULL;
1124 else
1125 return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr);
1126}
1127
1128/**
1129 * Synchronous work request. Requests work from the POW.
1130 * This function waits for any previous tag switch to complete before
1131 * requesting the new work.
1132 *
1133 * @wait: When set, call stalls until work becomes avaiable, or times out.
1134 * If not set, returns immediately.
1135 *
1136 * Returns Returns the WQE pointer from POW. Returns NULL if no work
1137 * was available.
1138 */
1139static inline cvmx_wqe_t *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
1140{
1141 if (CVMX_ENABLE_POW_CHECKS)
1142 __cvmx_pow_warn_if_pending_switch(__func__);
1143
1144 /* Must not have a switch pending when requesting work */
1145 cvmx_pow_tag_sw_wait();
1146 return cvmx_pow_work_request_sync_nocheck(wait);
1147
1148}
1149
1150/**
1151 * Synchronous null_rd request. Requests a switch out of NULL_NULL POW state.
1152 * This function waits for any previous tag switch to complete before
1153 * requesting the null_rd.
1154 *
1155 * Returns Returns the POW state of type cvmx_pow_tag_type_t.
1156 */
1157static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void)
1158{
1159 cvmx_pow_load_addr_t ptr;
1160 cvmx_pow_tag_load_resp_t result;
1161
1162 if (CVMX_ENABLE_POW_CHECKS)
1163 __cvmx_pow_warn_if_pending_switch(__func__);
1164
1165 /* Must not have a switch pending when requesting work */
1166 cvmx_pow_tag_sw_wait();
1167
1168 ptr.u64 = 0;
1169 ptr.snull_rd.mem_region = CVMX_IO_SEG;
1170 ptr.snull_rd.is_io = 1;
1171 ptr.snull_rd.did = CVMX_OCT_DID_TAG_NULL_RD;
1172
1173 result.u64 = cvmx_read_csr(ptr.u64);
1174
1175 return (enum cvmx_pow_tag_type) result.s_null_rd.state;
1176}
1177
1178/**
1179 * Asynchronous work request. Work is requested from the POW unit,
1180 * and should later be checked with function
1181 * cvmx_pow_work_response_async. This function does NOT wait for
1182 * previous tag switches to complete, so the caller must ensure that
1183 * there is not a pending tag switch.
1184 *
1185 * @scr_addr: Scratch memory address that response will be returned
1186 * to, which is either a valid WQE, or a response with the
1187 * invalid bit set. Byte address, must be 8 byte aligned.
1188 *
1189 * @wait: 1 to cause response to wait for work to become available (or
1190 * timeout), 0 to cause response to return immediately
1191 */
1192static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
1193 cvmx_pow_wait_t wait)
1194{
1195 cvmx_pow_iobdma_store_t data;
1196
1197 if (CVMX_ENABLE_POW_CHECKS)
1198 __cvmx_pow_warn_if_pending_switch(__func__);
1199
1200 /* scr_addr must be 8 byte aligned */
1201 data.s.scraddr = scr_addr >> 3;
1202 data.s.len = 1;
1203 data.s.did = CVMX_OCT_DID_TAG_SWTAG;
1204 data.s.wait = wait;
1205 cvmx_send_single(data.u64);
1206}
1207
1208/**
1209 * Asynchronous work request. Work is requested from the POW unit,
1210 * and should later be checked with function
1211 * cvmx_pow_work_response_async. This function waits for any previous
1212 * tag switch to complete before requesting the new work.
1213 *
1214 * @scr_addr: Scratch memory address that response will be returned
1215 * to, which is either a valid WQE, or a response with the
1216 * invalid bit set. Byte address, must be 8 byte aligned.
1217 *
1218 * @wait: 1 to cause response to wait for work to become available (or
1219 * timeout), 0 to cause response to return immediately
1220 */
1221static inline void cvmx_pow_work_request_async(int scr_addr,
1222 cvmx_pow_wait_t wait)
1223{
1224 if (CVMX_ENABLE_POW_CHECKS)
1225 __cvmx_pow_warn_if_pending_switch(__func__);
1226
1227 /* Must not have a switch pending when requesting work */
1228 cvmx_pow_tag_sw_wait();
1229 cvmx_pow_work_request_async_nocheck(scr_addr, wait);
1230}
1231
1232/**
1233 * Gets result of asynchronous work request. Performs a IOBDMA sync
1234 * to wait for the response.
1235 *
1236 * @scr_addr: Scratch memory address to get result from Byte address,
1237 * must be 8 byte aligned.
1238 *
1239 * Returns Returns the WQE from the scratch register, or NULL if no
1240 * work was available.
1241 */
1242static inline cvmx_wqe_t *cvmx_pow_work_response_async(int scr_addr)
1243{
1244 cvmx_pow_tag_load_resp_t result;
1245
1246 CVMX_SYNCIOBDMA;
1247 result.u64 = cvmx_scratch_read64(scr_addr);
1248
1249 if (result.s_work.no_work)
1250 return NULL;
1251 else
1252 return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr);
1253}
1254
1255/**
1256 * Checks if a work queue entry pointer returned by a work
1257 * request is valid. It may be invalid due to no work
1258 * being available or due to a timeout.
1259 *
1260 * @wqe_ptr: pointer to a work queue entry returned by the POW
1261 *
1262 * Returns 0 if pointer is valid
1263 * 1 if invalid (no work was returned)
1264 */
1265static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr)
1266{
1267 return wqe_ptr == NULL;
1268}
1269
1270/**
1271 * Starts a tag switch to the provided tag value and tag type.
1272 * Completion for the tag switch must be checked for separately. This
1273 * function does NOT update the work queue entry in dram to match tag
1274 * value and type, so the application must keep track of these if they
1275 * are important to the application. This tag switch command must not
1276 * be used for switches to NULL, as the tag switch pending bit will be
1277 * set by the switch request, but never cleared by the hardware.
1278 *
1279 * NOTE: This should not be used when switching from a NULL tag. Use
1280 * cvmx_pow_tag_sw_full() instead.
1281 *
1282 * This function does no checks, so the caller must ensure that any
1283 * previous tag switch has completed.
1284 *
1285 * @tag: new tag value
1286 * @tag_type: new tag type (ordered or atomic)
1287 */
1288static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag,
1289 enum cvmx_pow_tag_type tag_type)
1290{
1291 cvmx_addr_t ptr;
1292 cvmx_pow_tag_req_t tag_req;
1293
1294 if (CVMX_ENABLE_POW_CHECKS) {
1295 cvmx_pow_tag_req_t current_tag;
1296 __cvmx_pow_warn_if_pending_switch(__func__);
1297 current_tag = cvmx_pow_get_current_tag();
1298 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1299 pr_warning("%s called with NULL_NULL tag\n",
1300 __func__);
1301 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1302 pr_warning("%s called with NULL tag\n", __func__);
1303 if ((current_tag.s.type == tag_type)
1304 && (current_tag.s.tag == tag))
1305 pr_warning("%s called to perform a tag switch to the "
1306 "same tag\n",
1307 __func__);
1308 if (tag_type == CVMX_POW_TAG_TYPE_NULL)
1309 pr_warning("%s called to perform a tag switch to "
1310 "NULL. Use cvmx_pow_tag_sw_null() instead\n",
1311 __func__);
1312 }
1313
1314 /*
1315 * Note that WQE in DRAM is not updated here, as the POW does
1316 * not read from DRAM once the WQE is in flight. See hardware
1317 * manual for complete details. It is the application's
1318 * responsibility to keep track of the current tag value if
1319 * that is important.
1320 */
1321
1322 tag_req.u64 = 0;
1323 tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
1324 tag_req.s.tag = tag;
1325 tag_req.s.type = tag_type;
1326
1327 ptr.u64 = 0;
1328 ptr.sio.mem_region = CVMX_IO_SEG;
1329 ptr.sio.is_io = 1;
1330 ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
1331
1332 /* once this store arrives at POW, it will attempt the switch
1333 software must wait for the switch to complete separately */
1334 cvmx_write_io(ptr.u64, tag_req.u64);
1335}
1336
1337/**
1338 * Starts a tag switch to the provided tag value and tag type.
1339 * Completion for the tag switch must be checked for separately. This
1340 * function does NOT update the work queue entry in dram to match tag
1341 * value and type, so the application must keep track of these if they
1342 * are important to the application. This tag switch command must not
1343 * be used for switches to NULL, as the tag switch pending bit will be
1344 * set by the switch request, but never cleared by the hardware.
1345 *
1346 * NOTE: This should not be used when switching from a NULL tag. Use
1347 * cvmx_pow_tag_sw_full() instead.
1348 *
1349 * This function waits for any previous tag switch to complete, and also
1350 * displays an error on tag switches to NULL.
1351 *
1352 * @tag: new tag value
1353 * @tag_type: new tag type (ordered or atomic)
1354 */
1355static inline void cvmx_pow_tag_sw(uint32_t tag,
1356 enum cvmx_pow_tag_type tag_type)
1357{
1358 if (CVMX_ENABLE_POW_CHECKS)
1359 __cvmx_pow_warn_if_pending_switch(__func__);
1360
1361 /*
1362 * Note that WQE in DRAM is not updated here, as the POW does
1363 * not read from DRAM once the WQE is in flight. See hardware
1364 * manual for complete details. It is the application's
1365 * responsibility to keep track of the current tag value if
1366 * that is important.
1367 */
1368
1369 /*
1370 * Ensure that there is not a pending tag switch, as a tag
1371 * switch cannot be started if a previous switch is still
1372 * pending.
1373 */
1374 cvmx_pow_tag_sw_wait();
1375 cvmx_pow_tag_sw_nocheck(tag, tag_type);
1376}
1377
1378/**
1379 * Starts a tag switch to the provided tag value and tag type.
1380 * Completion for the tag switch must be checked for separately. This
1381 * function does NOT update the work queue entry in dram to match tag
1382 * value and type, so the application must keep track of these if they
1383 * are important to the application. This tag switch command must not
1384 * be used for switches to NULL, as the tag switch pending bit will be
1385 * set by the switch request, but never cleared by the hardware.
1386 *
1387 * This function must be used for tag switches from NULL.
1388 *
1389 * This function does no checks, so the caller must ensure that any
1390 * previous tag switch has completed.
1391 *
1392 * @wqp: pointer to work queue entry to submit. This entry is
1393 * updated to match the other parameters
1394 * @tag: tag value to be assigned to work queue entry
1395 * @tag_type: type of tag
1396 * @group: group value for the work queue entry.
1397 */
1398static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag,
1399 enum cvmx_pow_tag_type tag_type,
1400 uint64_t group)
1401{
1402 cvmx_addr_t ptr;
1403 cvmx_pow_tag_req_t tag_req;
1404
1405 if (CVMX_ENABLE_POW_CHECKS) {
1406 cvmx_pow_tag_req_t current_tag;
1407 __cvmx_pow_warn_if_pending_switch(__func__);
1408 current_tag = cvmx_pow_get_current_tag();
1409 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1410 pr_warning("%s called with NULL_NULL tag\n",
1411 __func__);
1412 if ((current_tag.s.type == tag_type)
1413 && (current_tag.s.tag == tag))
1414 pr_warning("%s called to perform a tag switch to "
1415 "the same tag\n",
1416 __func__);
1417 if (tag_type == CVMX_POW_TAG_TYPE_NULL)
1418 pr_warning("%s called to perform a tag switch to "
1419 "NULL. Use cvmx_pow_tag_sw_null() instead\n",
1420 __func__);
1421 if (wqp != cvmx_phys_to_ptr(0x80))
1422 if (wqp != cvmx_pow_get_current_wqp())
1423 pr_warning("%s passed WQE(%p) doesn't match "
1424 "the address in the POW(%p)\n",
1425 __func__, wqp,
1426 cvmx_pow_get_current_wqp());
1427 }
1428
1429 /*
1430 * Note that WQE in DRAM is not updated here, as the POW does
1431 * not read from DRAM once the WQE is in flight. See hardware
1432 * manual for complete details. It is the application's
1433 * responsibility to keep track of the current tag value if
1434 * that is important.
1435 */
1436
1437 tag_req.u64 = 0;
1438 tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_FULL;
1439 tag_req.s.tag = tag;
1440 tag_req.s.type = tag_type;
1441 tag_req.s.grp = group;
1442
1443 ptr.u64 = 0;
1444 ptr.sio.mem_region = CVMX_IO_SEG;
1445 ptr.sio.is_io = 1;
1446 ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
1447 ptr.sio.offset = CAST64(wqp);
1448
1449 /*
1450 * once this store arrives at POW, it will attempt the switch
1451 * software must wait for the switch to complete separately.
1452 */
1453 cvmx_write_io(ptr.u64, tag_req.u64);
1454}
1455
1456/**
1457 * Starts a tag switch to the provided tag value and tag type.
1458 * Completion for the tag switch must be checked for separately. This
1459 * function does NOT update the work queue entry in dram to match tag
1460 * value and type, so the application must keep track of these if they
1461 * are important to the application. This tag switch command must not
1462 * be used for switches to NULL, as the tag switch pending bit will be
1463 * set by the switch request, but never cleared by the hardware.
1464 *
1465 * This function must be used for tag switches from NULL.
1466 *
1467 * This function waits for any pending tag switches to complete
1468 * before requesting the tag switch.
1469 *
1470 * @wqp: pointer to work queue entry to submit. This entry is updated
1471 * to match the other parameters
1472 * @tag: tag value to be assigned to work queue entry
1473 * @tag_type: type of tag
1474 * @group: group value for the work queue entry.
1475 */
1476static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag,
1477 enum cvmx_pow_tag_type tag_type,
1478 uint64_t group)
1479{
1480 if (CVMX_ENABLE_POW_CHECKS)
1481 __cvmx_pow_warn_if_pending_switch(__func__);
1482
1483 /*
1484 * Ensure that there is not a pending tag switch, as a tag
1485 * switch cannot be started if a previous switch is still
1486 * pending.
1487 */
1488 cvmx_pow_tag_sw_wait();
1489 cvmx_pow_tag_sw_full_nocheck(wqp, tag, tag_type, group);
1490}
1491
1492/**
1493 * Switch to a NULL tag, which ends any ordering or
1494 * synchronization provided by the POW for the current
1495 * work queue entry. This operation completes immediately,
1496 * so completion should not be waited for.
1497 * This function does NOT wait for previous tag switches to complete,
1498 * so the caller must ensure that any previous tag switches have completed.
1499 */
1500static inline void cvmx_pow_tag_sw_null_nocheck(void)
1501{
1502 cvmx_addr_t ptr;
1503 cvmx_pow_tag_req_t tag_req;
1504
1505 if (CVMX_ENABLE_POW_CHECKS) {
1506 cvmx_pow_tag_req_t current_tag;
1507 __cvmx_pow_warn_if_pending_switch(__func__);
1508 current_tag = cvmx_pow_get_current_tag();
1509 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1510 pr_warning("%s called with NULL_NULL tag\n",
1511 __func__);
1512 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1513 pr_warning("%s called when we already have a "
1514 "NULL tag\n",
1515 __func__);
1516 }
1517
1518 tag_req.u64 = 0;
1519 tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
1520 tag_req.s.type = CVMX_POW_TAG_TYPE_NULL;
1521
1522 ptr.u64 = 0;
1523 ptr.sio.mem_region = CVMX_IO_SEG;
1524 ptr.sio.is_io = 1;
1525 ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
1526
1527 cvmx_write_io(ptr.u64, tag_req.u64);
1528
1529 /* switch to NULL completes immediately */
1530}
1531
1532/**
1533 * Switch to a NULL tag, which ends any ordering or
1534 * synchronization provided by the POW for the current
1535 * work queue entry. This operation completes immediately,
1536 * so completion should not be waited for.
1537 * This function waits for any pending tag switches to complete
1538 * before requesting the switch to NULL.
1539 */
1540static inline void cvmx_pow_tag_sw_null(void)
1541{
1542 if (CVMX_ENABLE_POW_CHECKS)
1543 __cvmx_pow_warn_if_pending_switch(__func__);
1544
1545 /*
1546 * Ensure that there is not a pending tag switch, as a tag
1547 * switch cannot be started if a previous switch is still
1548 * pending.
1549 */
1550 cvmx_pow_tag_sw_wait();
1551 cvmx_pow_tag_sw_null_nocheck();
1552
1553 /* switch to NULL completes immediately */
1554}
1555
1556/**
1557 * Submits work to an input queue. This function updates the work
1558 * queue entry in DRAM to match the arguments given. Note that the
1559 * tag provided is for the work queue entry submitted, and is
1560 * unrelated to the tag that the core currently holds.
1561 *
1562 * @wqp: pointer to work queue entry to submit. This entry is
1563 * updated to match the other parameters
1564 * @tag: tag value to be assigned to work queue entry
1565 * @tag_type: type of tag
1566 * @qos: Input queue to add to.
1567 * @grp: group value for the work queue entry.
1568 */
1569static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag,
1570 enum cvmx_pow_tag_type tag_type,
1571 uint64_t qos, uint64_t grp)
1572{
1573 cvmx_addr_t ptr;
1574 cvmx_pow_tag_req_t tag_req;
1575
1576 wqp->qos = qos;
1577 wqp->tag = tag;
1578 wqp->tag_type = tag_type;
1579 wqp->grp = grp;
1580
1581 tag_req.u64 = 0;
1582 tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ;
1583 tag_req.s.type = tag_type;
1584 tag_req.s.tag = tag;
1585 tag_req.s.qos = qos;
1586 tag_req.s.grp = grp;
1587
1588 ptr.u64 = 0;
1589 ptr.sio.mem_region = CVMX_IO_SEG;
1590 ptr.sio.is_io = 1;
1591 ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
1592 ptr.sio.offset = cvmx_ptr_to_phys(wqp);
1593
1594 /*
1595 * SYNC write to memory before the work submit. This is
1596 * necessary as POW may read values from DRAM at this time.
1597 */
1598 CVMX_SYNCWS;
1599 cvmx_write_io(ptr.u64, tag_req.u64);
1600}
1601
1602/**
1603 * This function sets the group mask for a core. The group mask
1604 * indicates which groups each core will accept work from. There are
1605 * 16 groups.
1606 *
1607 * @core_num: core to apply mask to
1608 * @mask: Group mask. There are 16 groups, so only bits 0-15 are valid,
1609 * representing groups 0-15.
1610 * Each 1 bit in the mask enables the core to accept work from
1611 * the corresponding group.
1612 */
1613static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask)
1614{
1615 union cvmx_pow_pp_grp_mskx grp_msk;
1616
1617 grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
1618 grp_msk.s.grp_msk = mask;
1619 cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
1620}
1621
1622/**
1623 * This function sets POW static priorities for a core. Each input queue has
1624 * an associated priority value.
1625 *
1626 * @core_num: core to apply priorities to
1627 * @priority: Vector of 8 priorities, one per POW Input Queue (0-7).
1628 * Highest priority is 0 and lowest is 7. A priority value
1629 * of 0xF instructs POW to skip the Input Queue when
1630 * scheduling to this specific core.
1631 * NOTE: priorities should not have gaps in values, meaning
1632 * {0,1,1,1,1,1,1,1} is a valid configuration while
1633 * {0,2,2,2,2,2,2,2} is not.
1634 */
1635static inline void cvmx_pow_set_priority(uint64_t core_num,
1636 const uint8_t priority[])
1637{
1638 /* POW priorities are supported on CN5xxx and later */
1639 if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
1640 union cvmx_pow_pp_grp_mskx grp_msk;
1641
1642 grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
1643 grp_msk.s.qos0_pri = priority[0];
1644 grp_msk.s.qos1_pri = priority[1];
1645 grp_msk.s.qos2_pri = priority[2];
1646 grp_msk.s.qos3_pri = priority[3];
1647 grp_msk.s.qos4_pri = priority[4];
1648 grp_msk.s.qos5_pri = priority[5];
1649 grp_msk.s.qos6_pri = priority[6];
1650 grp_msk.s.qos7_pri = priority[7];
1651
1652 /* Detect gaps between priorities and flag error */
1653 {
1654 int i;
1655 uint32_t prio_mask = 0;
1656
1657 for (i = 0; i < 8; i++)
1658 if (priority[i] != 0xF)
1659 prio_mask |= 1 << priority[i];
1660
1661 if (prio_mask ^ ((1 << cvmx_pop(prio_mask)) - 1)) {
1662 pr_err("POW static priorities should be "
1663 "contiguous (0x%llx)\n",
1664 (unsigned long long)prio_mask);
1665 return;
1666 }
1667 }
1668
1669 cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
1670 }
1671}
1672
1673/**
1674 * Performs a tag switch and then an immediate deschedule. This completes
1675 * immediately, so completion must not be waited for. This function does NOT
1676 * update the wqe in DRAM to match arguments.
1677 *
1678 * This function does NOT wait for any prior tag switches to complete, so the
1679 * calling code must do this.
1680 *
1681 * Note the following CAVEAT of the Octeon HW behavior when
1682 * re-scheduling DE-SCHEDULEd items whose (next) state is
1683 * ORDERED:
1684 * - If there are no switches pending at the time that the
1685 * HW executes the de-schedule, the HW will only re-schedule
1686 * the head of the FIFO associated with the given tag. This
1687 * means that in many respects, the HW treats this ORDERED
1688 * tag as an ATOMIC tag. Note that in the SWTAG_DESCH
1689 * case (to an ORDERED tag), the HW will do the switch
1690 * before the deschedule whenever it is possible to do
1691 * the switch immediately, so it may often look like
1692 * this case.
1693 * - If there is a pending switch to ORDERED at the time
1694 * the HW executes the de-schedule, the HW will perform
1695 * the switch at the time it re-schedules, and will be
1696 * able to reschedule any/all of the entries with the
1697 * same tag.
1698 * Due to this behavior, the RECOMMENDATION to software is
1699 * that they have a (next) state of ATOMIC when they
1700 * DE-SCHEDULE. If an ORDERED tag is what was really desired,
1701 * SW can choose to immediately switch to an ORDERED tag
1702 * after the work (that has an ATOMIC tag) is re-scheduled.
1703 * Note that since there are never any tag switches pending
1704 * when the HW re-schedules, this switch can be IMMEDIATE upon
1705 * the reception of the pointer during the re-schedule.
1706 *
1707 * @tag: New tag value
1708 * @tag_type: New tag type
1709 * @group: New group value
1710 * @no_sched: Control whether this work queue entry will be rescheduled.
1711 * - 1 : don't schedule this work
1712 * - 0 : allow this work to be scheduled.
1713 */
1714static inline void cvmx_pow_tag_sw_desched_nocheck(
1715 uint32_t tag,
1716 enum cvmx_pow_tag_type tag_type,
1717 uint64_t group,
1718 uint64_t no_sched)
1719{
1720 cvmx_addr_t ptr;
1721 cvmx_pow_tag_req_t tag_req;
1722
1723 if (CVMX_ENABLE_POW_CHECKS) {
1724 cvmx_pow_tag_req_t current_tag;
1725 __cvmx_pow_warn_if_pending_switch(__func__);
1726 current_tag = cvmx_pow_get_current_tag();
1727 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1728 pr_warning("%s called with NULL_NULL tag\n",
1729 __func__);
1730 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1731 pr_warning("%s called with NULL tag. Deschedule not "
1732 "allowed from NULL state\n",
1733 __func__);
1734 if ((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC)
1735 && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC))
1736 pr_warning("%s called where neither the before or "
1737 "after tag is ATOMIC\n",
1738 __func__);
1739 }
1740
1741 tag_req.u64 = 0;
1742 tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_DESCH;
1743 tag_req.s.tag = tag;
1744 tag_req.s.type = tag_type;
1745 tag_req.s.grp = group;
1746 tag_req.s.no_sched = no_sched;
1747
1748 ptr.u64 = 0;
1749 ptr.sio.mem_region = CVMX_IO_SEG;
1750 ptr.sio.is_io = 1;
1751 ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
1752 /*
1753 * since TAG3 is used, this store will clear the local pending
1754 * switch bit.
1755 */
1756 cvmx_write_io(ptr.u64, tag_req.u64);
1757}
1758
1759/**
1760 * Performs a tag switch and then an immediate deschedule. This completes
1761 * immediately, so completion must not be waited for. This function does NOT
1762 * update the wqe in DRAM to match arguments.
1763 *
1764 * This function waits for any prior tag switches to complete, so the
1765 * calling code may call this function with a pending tag switch.
1766 *
1767 * Note the following CAVEAT of the Octeon HW behavior when
1768 * re-scheduling DE-SCHEDULEd items whose (next) state is
1769 * ORDERED:
1770 * - If there are no switches pending at the time that the
1771 * HW executes the de-schedule, the HW will only re-schedule
1772 * the head of the FIFO associated with the given tag. This
1773 * means that in many respects, the HW treats this ORDERED
1774 * tag as an ATOMIC tag. Note that in the SWTAG_DESCH
1775 * case (to an ORDERED tag), the HW will do the switch
1776 * before the deschedule whenever it is possible to do
1777 * the switch immediately, so it may often look like
1778 * this case.
1779 * - If there is a pending switch to ORDERED at the time
1780 * the HW executes the de-schedule, the HW will perform
1781 * the switch at the time it re-schedules, and will be
1782 * able to reschedule any/all of the entries with the
1783 * same tag.
1784 * Due to this behavior, the RECOMMENDATION to software is
1785 * that they have a (next) state of ATOMIC when they
1786 * DE-SCHEDULE. If an ORDERED tag is what was really desired,
1787 * SW can choose to immediately switch to an ORDERED tag
1788 * after the work (that has an ATOMIC tag) is re-scheduled.
1789 * Note that since there are never any tag switches pending
1790 * when the HW re-schedules, this switch can be IMMEDIATE upon
1791 * the reception of the pointer during the re-schedule.
1792 *
1793 * @tag: New tag value
1794 * @tag_type: New tag type
1795 * @group: New group value
1796 * @no_sched: Control whether this work queue entry will be rescheduled.
1797 * - 1 : don't schedule this work
1798 * - 0 : allow this work to be scheduled.
1799 */
1800static inline void cvmx_pow_tag_sw_desched(uint32_t tag,
1801 enum cvmx_pow_tag_type tag_type,
1802 uint64_t group, uint64_t no_sched)
1803{
1804 if (CVMX_ENABLE_POW_CHECKS)
1805 __cvmx_pow_warn_if_pending_switch(__func__);
1806
1807 /* Need to make sure any writes to the work queue entry are complete */
1808 CVMX_SYNCWS;
1809 /*
1810 * Ensure that there is not a pending tag switch, as a tag
1811 * switch cannot be started if a previous switch is still
1812 * pending.
1813 */
1814 cvmx_pow_tag_sw_wait();
1815 cvmx_pow_tag_sw_desched_nocheck(tag, tag_type, group, no_sched);
1816}
1817
1818/**
1819 * Descchedules the current work queue entry.
1820 *
1821 * @no_sched: no schedule flag value to be set on the work queue
1822 * entry. If this is set the entry will not be
1823 * rescheduled.
1824 */
1825static inline void cvmx_pow_desched(uint64_t no_sched)
1826{
1827 cvmx_addr_t ptr;
1828 cvmx_pow_tag_req_t tag_req;
1829
1830 if (CVMX_ENABLE_POW_CHECKS) {
1831 cvmx_pow_tag_req_t current_tag;
1832 __cvmx_pow_warn_if_pending_switch(__func__);
1833 current_tag = cvmx_pow_get_current_tag();
1834 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
1835 pr_warning("%s called with NULL_NULL tag\n",
1836 __func__);
1837 if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
1838 pr_warning("%s called with NULL tag. Deschedule not "
1839 "expected from NULL state\n",
1840 __func__);
1841 }
1842
1843 /* Need to make sure any writes to the work queue entry are complete */
1844 CVMX_SYNCWS;
1845
1846 tag_req.u64 = 0;
1847 tag_req.s.op = CVMX_POW_TAG_OP_DESCH;
1848 tag_req.s.no_sched = no_sched;
1849
1850 ptr.u64 = 0;
1851 ptr.sio.mem_region = CVMX_IO_SEG;
1852 ptr.sio.is_io = 1;
1853 ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
1854 /*
1855 * since TAG3 is used, this store will clear the local pending
1856 * switch bit.
1857 */
1858 cvmx_write_io(ptr.u64, tag_req.u64);
1859}
1860
1861/****************************************************
1862* Define usage of bits within the 32 bit tag values.
1863*****************************************************/
1864
1865/*
1866 * Number of bits of the tag used by software. The SW bits are always
1867 * a contiguous block of the high starting at bit 31. The hardware
1868 * bits are always the low bits. By default, the top 8 bits of the
1869 * tag are reserved for software, and the low 24 are set by the IPD
1870 * unit.
1871 */
1872#define CVMX_TAG_SW_BITS (8)
1873#define CVMX_TAG_SW_SHIFT (32 - CVMX_TAG_SW_BITS)
1874
1875/* Below is the list of values for the top 8 bits of the tag. */
1876/*
1877 * Tag values with top byte of this value are reserved for internal
1878 * executive uses.
1879 */
1880#define CVMX_TAG_SW_BITS_INTERNAL 0x1
1881/* The executive divides the remaining 24 bits as follows:
1882 * - the upper 8 bits (bits 23 - 16 of the tag) define a subgroup
1883 *
1884 * - the lower 16 bits (bits 15 - 0 of the tag) define are the value
1885 * with the subgroup
1886 *
1887 * Note that this section describes the format of tags generated by
1888 * software - refer to the hardware documentation for a description of
1889 * the tags values generated by the packet input hardware. Subgroups
1890 * are defined here.
1891 */
1892/* Mask for the value portion of the tag */
1893#define CVMX_TAG_SUBGROUP_MASK 0xFFFF
1894#define CVMX_TAG_SUBGROUP_SHIFT 16
1895#define CVMX_TAG_SUBGROUP_PKO 0x1
1896
1897/* End of executive tag subgroup definitions */
1898
1899/*
1900 * The remaining values software bit values 0x2 - 0xff are available
1901 * for application use.
1902 */
1903
1904/**
1905 * This function creates a 32 bit tag value from the two values provided.
1906 *
1907 * @sw_bits: The upper bits (number depends on configuration) are set
1908 * to this value. The remainder of bits are set by the
1909 * hw_bits parameter.
1910 *
1911 * @hw_bits: The lower bits (number depends on configuration) are set
1912 * to this value. The remainder of bits are set by the
1913 * sw_bits parameter.
1914 *
1915 * Returns 32 bit value of the combined hw and sw bits.
1916 */
1917static inline uint32_t cvmx_pow_tag_compose(uint64_t sw_bits, uint64_t hw_bits)
1918{
1919 return ((sw_bits & cvmx_build_mask(CVMX_TAG_SW_BITS)) <<
1920 CVMX_TAG_SW_SHIFT) |
1921 (hw_bits & cvmx_build_mask(32 - CVMX_TAG_SW_BITS));
1922}
1923
1924/**
1925 * Extracts the bits allocated for software use from the tag
1926 *
1927 * @tag: 32 bit tag value
1928 *
1929 * Returns N bit software tag value, where N is configurable with the
1930 * CVMX_TAG_SW_BITS define
1931 */
1932static inline uint32_t cvmx_pow_tag_get_sw_bits(uint64_t tag)
1933{
1934 return (tag >> (32 - CVMX_TAG_SW_BITS)) &
1935 cvmx_build_mask(CVMX_TAG_SW_BITS);
1936}
1937
1938/**
1939 *
1940 * Extracts the bits allocated for hardware use from the tag
1941 *
1942 * @tag: 32 bit tag value
1943 *
1944 * Returns (32 - N) bit software tag value, where N is configurable
1945 * with the CVMX_TAG_SW_BITS define
1946 */
1947static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag)
1948{
1949 return tag & cvmx_build_mask(32 - CVMX_TAG_SW_BITS);
1950}
1951
1952/**
1953 * Store the current POW internal state into the supplied
1954 * buffer. It is recommended that you pass a buffer of at least
1955 * 128KB. The format of the capture may change based on SDK
1956 * version and Octeon chip.
1957 *
1958 * @buffer: Buffer to store capture into
1959 * @buffer_size:
1960 * The size of the supplied buffer
1961 *
1962 * Returns Zero on success, negative on failure
1963 */
1964extern int cvmx_pow_capture(void *buffer, int buffer_size);
1965
1966/**
1967 * Dump a POW capture to the console in a human readable format.
1968 *
1969 * @buffer: POW capture from cvmx_pow_capture()
1970 * @buffer_size:
1971 * Size of the buffer
1972 */
1973extern void cvmx_pow_display(void *buffer, int buffer_size);
1974
1975/**
1976 * Return the number of POW entries supported by this chip
1977 *
1978 * Returns Number of POW entries
1979 */
1980extern int cvmx_pow_get_num_entries(void);
1981
1982#endif /* __CVMX_POW_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h
new file mode 100644
index 000000000000..96b70cfd6245
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-scratch.h
@@ -0,0 +1,139 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * This file provides support for the processor local scratch memory.
31 * Scratch memory is byte addressable - all addresses are byte addresses.
32 *
33 */
34
35#ifndef __CVMX_SCRATCH_H__
36#define __CVMX_SCRATCH_H__
37
38/*
39 * Note: This define must be a long, not a long long in order to
40 * compile without warnings for both 32bit and 64bit.
41 */
42#define CVMX_SCRATCH_BASE (-32768l) /* 0xffffffffffff8000 */
43
44/**
45 * Reads an 8 bit value from the processor local scratchpad memory.
46 *
47 * @address: byte address to read from
48 *
49 * Returns value read
50 */
51static inline uint8_t cvmx_scratch_read8(uint64_t address)
52{
53 return *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address);
54}
55
56/**
57 * Reads a 16 bit value from the processor local scratchpad memory.
58 *
59 * @address: byte address to read from
60 *
61 * Returns value read
62 */
63static inline uint16_t cvmx_scratch_read16(uint64_t address)
64{
65 return *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address);
66}
67
68/**
69 * Reads a 32 bit value from the processor local scratchpad memory.
70 *
71 * @address: byte address to read from
72 *
73 * Returns value read
74 */
75static inline uint32_t cvmx_scratch_read32(uint64_t address)
76{
77 return *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address);
78}
79
80/**
81 * Reads a 64 bit value from the processor local scratchpad memory.
82 *
83 * @address: byte address to read from
84 *
85 * Returns value read
86 */
87static inline uint64_t cvmx_scratch_read64(uint64_t address)
88{
89 return *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address);
90}
91
92/**
93 * Writes an 8 bit value to the processor local scratchpad memory.
94 *
95 * @address: byte address to write to
96 * @value: value to write
97 */
98static inline void cvmx_scratch_write8(uint64_t address, uint64_t value)
99{
100 *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address) =
101 (uint8_t) value;
102}
103
104/**
105 * Writes a 32 bit value to the processor local scratchpad memory.
106 *
107 * @address: byte address to write to
108 * @value: value to write
109 */
110static inline void cvmx_scratch_write16(uint64_t address, uint64_t value)
111{
112 *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address) =
113 (uint16_t) value;
114}
115
116/**
117 * Writes a 16 bit value to the processor local scratchpad memory.
118 *
119 * @address: byte address to write to
120 * @value: value to write
121 */
122static inline void cvmx_scratch_write32(uint64_t address, uint64_t value)
123{
124 *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address) =
125 (uint32_t) value;
126}
127
128/**
129 * Writes a 64 bit value to the processor local scratchpad memory.
130 *
131 * @address: byte address to write to
132 * @value: value to write
133 */
134static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
135{
136 *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address) = value;
137}
138
139#endif /* __CVMX_SCRATCH_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
new file mode 100644
index 000000000000..7c6c901d3d28
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
@@ -0,0 +1,2172 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SLI_DEFS_H__
29#define __CVMX_SLI_DEFS_H__
30
31#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
32#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
33#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
34#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
35#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
36#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
37#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
38#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
39#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
40#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
41#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
42#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
43#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
44#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
45#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
46#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
47#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
48#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
49#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
50#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
51#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
52#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
53#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
54#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
55#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
56#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
57#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
58#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
59#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
60#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
61#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
62#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
63#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
64#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
65#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
66#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
67#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
68#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
69#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
70#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
71#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
72#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
73#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
74#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
75#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
76#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
77#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
78#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
79#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
80#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
81#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
82#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
83#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
84#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
85#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
86#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
87#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
88#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
89#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
90#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
91#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
92#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
93#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
94#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
95#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
96#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
97#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
98#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
99#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
100#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
101#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
102#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
103#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
104#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
105#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
106#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
107#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
108#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
109#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
110#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
111#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
112#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
113#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
114#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
115#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
116#define CVMX_SLI_STATE1 (0x0000000000000620ull)
117#define CVMX_SLI_STATE2 (0x0000000000000630ull)
118#define CVMX_SLI_STATE3 (0x0000000000000640ull)
119#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
120#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
121#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
122#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
123#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
124#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
125#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
126
127union cvmx_sli_bist_status {
128 uint64_t u64;
129 struct cvmx_sli_bist_status_s {
130 uint64_t reserved_32_63:32;
131 uint64_t ncb_req:1;
132 uint64_t n2p0_c:1;
133 uint64_t n2p0_o:1;
134 uint64_t n2p1_c:1;
135 uint64_t n2p1_o:1;
136 uint64_t cpl_p0:1;
137 uint64_t cpl_p1:1;
138 uint64_t reserved_19_24:6;
139 uint64_t p2n0_c0:1;
140 uint64_t p2n0_c1:1;
141 uint64_t p2n0_n:1;
142 uint64_t p2n0_p0:1;
143 uint64_t p2n0_p1:1;
144 uint64_t p2n1_c0:1;
145 uint64_t p2n1_c1:1;
146 uint64_t p2n1_n:1;
147 uint64_t p2n1_p0:1;
148 uint64_t p2n1_p1:1;
149 uint64_t reserved_6_8:3;
150 uint64_t dsi1_1:1;
151 uint64_t dsi1_0:1;
152 uint64_t dsi0_1:1;
153 uint64_t dsi0_0:1;
154 uint64_t msi:1;
155 uint64_t ncb_cmd:1;
156 } s;
157 struct cvmx_sli_bist_status_cn61xx {
158 uint64_t reserved_31_63:33;
159 uint64_t n2p0_c:1;
160 uint64_t n2p0_o:1;
161 uint64_t reserved_27_28:2;
162 uint64_t cpl_p0:1;
163 uint64_t cpl_p1:1;
164 uint64_t reserved_19_24:6;
165 uint64_t p2n0_c0:1;
166 uint64_t p2n0_c1:1;
167 uint64_t p2n0_n:1;
168 uint64_t p2n0_p0:1;
169 uint64_t p2n0_p1:1;
170 uint64_t p2n1_c0:1;
171 uint64_t p2n1_c1:1;
172 uint64_t p2n1_n:1;
173 uint64_t p2n1_p0:1;
174 uint64_t p2n1_p1:1;
175 uint64_t reserved_6_8:3;
176 uint64_t dsi1_1:1;
177 uint64_t dsi1_0:1;
178 uint64_t dsi0_1:1;
179 uint64_t dsi0_0:1;
180 uint64_t msi:1;
181 uint64_t ncb_cmd:1;
182 } cn61xx;
183 struct cvmx_sli_bist_status_cn63xx {
184 uint64_t reserved_31_63:33;
185 uint64_t n2p0_c:1;
186 uint64_t n2p0_o:1;
187 uint64_t n2p1_c:1;
188 uint64_t n2p1_o:1;
189 uint64_t cpl_p0:1;
190 uint64_t cpl_p1:1;
191 uint64_t reserved_19_24:6;
192 uint64_t p2n0_c0:1;
193 uint64_t p2n0_c1:1;
194 uint64_t p2n0_n:1;
195 uint64_t p2n0_p0:1;
196 uint64_t p2n0_p1:1;
197 uint64_t p2n1_c0:1;
198 uint64_t p2n1_c1:1;
199 uint64_t p2n1_n:1;
200 uint64_t p2n1_p0:1;
201 uint64_t p2n1_p1:1;
202 uint64_t reserved_6_8:3;
203 uint64_t dsi1_1:1;
204 uint64_t dsi1_0:1;
205 uint64_t dsi0_1:1;
206 uint64_t dsi0_0:1;
207 uint64_t msi:1;
208 uint64_t ncb_cmd:1;
209 } cn63xx;
210 struct cvmx_sli_bist_status_cn63xx cn63xxp1;
211 struct cvmx_sli_bist_status_cn61xx cn66xx;
212 struct cvmx_sli_bist_status_s cn68xx;
213 struct cvmx_sli_bist_status_s cn68xxp1;
214};
215
216union cvmx_sli_ctl_portx {
217 uint64_t u64;
218 struct cvmx_sli_ctl_portx_s {
219 uint64_t reserved_22_63:42;
220 uint64_t intd:1;
221 uint64_t intc:1;
222 uint64_t intb:1;
223 uint64_t inta:1;
224 uint64_t dis_port:1;
225 uint64_t waitl_com:1;
226 uint64_t intd_map:2;
227 uint64_t intc_map:2;
228 uint64_t intb_map:2;
229 uint64_t inta_map:2;
230 uint64_t ctlp_ro:1;
231 uint64_t reserved_6_6:1;
232 uint64_t ptlp_ro:1;
233 uint64_t reserved_1_4:4;
234 uint64_t wait_com:1;
235 } s;
236 struct cvmx_sli_ctl_portx_s cn61xx;
237 struct cvmx_sli_ctl_portx_s cn63xx;
238 struct cvmx_sli_ctl_portx_s cn63xxp1;
239 struct cvmx_sli_ctl_portx_s cn66xx;
240 struct cvmx_sli_ctl_portx_s cn68xx;
241 struct cvmx_sli_ctl_portx_s cn68xxp1;
242};
243
244union cvmx_sli_ctl_status {
245 uint64_t u64;
246 struct cvmx_sli_ctl_status_s {
247 uint64_t reserved_20_63:44;
248 uint64_t p1_ntags:6;
249 uint64_t p0_ntags:6;
250 uint64_t chip_rev:8;
251 } s;
252 struct cvmx_sli_ctl_status_cn61xx {
253 uint64_t reserved_14_63:50;
254 uint64_t p0_ntags:6;
255 uint64_t chip_rev:8;
256 } cn61xx;
257 struct cvmx_sli_ctl_status_s cn63xx;
258 struct cvmx_sli_ctl_status_s cn63xxp1;
259 struct cvmx_sli_ctl_status_cn61xx cn66xx;
260 struct cvmx_sli_ctl_status_s cn68xx;
261 struct cvmx_sli_ctl_status_s cn68xxp1;
262};
263
264union cvmx_sli_data_out_cnt {
265 uint64_t u64;
266 struct cvmx_sli_data_out_cnt_s {
267 uint64_t reserved_44_63:20;
268 uint64_t p1_ucnt:16;
269 uint64_t p1_fcnt:6;
270 uint64_t p0_ucnt:16;
271 uint64_t p0_fcnt:6;
272 } s;
273 struct cvmx_sli_data_out_cnt_s cn61xx;
274 struct cvmx_sli_data_out_cnt_s cn63xx;
275 struct cvmx_sli_data_out_cnt_s cn63xxp1;
276 struct cvmx_sli_data_out_cnt_s cn66xx;
277 struct cvmx_sli_data_out_cnt_s cn68xx;
278 struct cvmx_sli_data_out_cnt_s cn68xxp1;
279};
280
281union cvmx_sli_dbg_data {
282 uint64_t u64;
283 struct cvmx_sli_dbg_data_s {
284 uint64_t reserved_18_63:46;
285 uint64_t dsel_ext:1;
286 uint64_t data:17;
287 } s;
288 struct cvmx_sli_dbg_data_s cn61xx;
289 struct cvmx_sli_dbg_data_s cn63xx;
290 struct cvmx_sli_dbg_data_s cn63xxp1;
291 struct cvmx_sli_dbg_data_s cn66xx;
292 struct cvmx_sli_dbg_data_s cn68xx;
293 struct cvmx_sli_dbg_data_s cn68xxp1;
294};
295
296union cvmx_sli_dbg_select {
297 uint64_t u64;
298 struct cvmx_sli_dbg_select_s {
299 uint64_t reserved_33_63:31;
300 uint64_t adbg_sel:1;
301 uint64_t dbg_sel:32;
302 } s;
303 struct cvmx_sli_dbg_select_s cn61xx;
304 struct cvmx_sli_dbg_select_s cn63xx;
305 struct cvmx_sli_dbg_select_s cn63xxp1;
306 struct cvmx_sli_dbg_select_s cn66xx;
307 struct cvmx_sli_dbg_select_s cn68xx;
308 struct cvmx_sli_dbg_select_s cn68xxp1;
309};
310
311union cvmx_sli_dmax_cnt {
312 uint64_t u64;
313 struct cvmx_sli_dmax_cnt_s {
314 uint64_t reserved_32_63:32;
315 uint64_t cnt:32;
316 } s;
317 struct cvmx_sli_dmax_cnt_s cn61xx;
318 struct cvmx_sli_dmax_cnt_s cn63xx;
319 struct cvmx_sli_dmax_cnt_s cn63xxp1;
320 struct cvmx_sli_dmax_cnt_s cn66xx;
321 struct cvmx_sli_dmax_cnt_s cn68xx;
322 struct cvmx_sli_dmax_cnt_s cn68xxp1;
323};
324
325union cvmx_sli_dmax_int_level {
326 uint64_t u64;
327 struct cvmx_sli_dmax_int_level_s {
328 uint64_t time:32;
329 uint64_t cnt:32;
330 } s;
331 struct cvmx_sli_dmax_int_level_s cn61xx;
332 struct cvmx_sli_dmax_int_level_s cn63xx;
333 struct cvmx_sli_dmax_int_level_s cn63xxp1;
334 struct cvmx_sli_dmax_int_level_s cn66xx;
335 struct cvmx_sli_dmax_int_level_s cn68xx;
336 struct cvmx_sli_dmax_int_level_s cn68xxp1;
337};
338
339union cvmx_sli_dmax_tim {
340 uint64_t u64;
341 struct cvmx_sli_dmax_tim_s {
342 uint64_t reserved_32_63:32;
343 uint64_t tim:32;
344 } s;
345 struct cvmx_sli_dmax_tim_s cn61xx;
346 struct cvmx_sli_dmax_tim_s cn63xx;
347 struct cvmx_sli_dmax_tim_s cn63xxp1;
348 struct cvmx_sli_dmax_tim_s cn66xx;
349 struct cvmx_sli_dmax_tim_s cn68xx;
350 struct cvmx_sli_dmax_tim_s cn68xxp1;
351};
352
353union cvmx_sli_int_enb_ciu {
354 uint64_t u64;
355 struct cvmx_sli_int_enb_ciu_s {
356 uint64_t reserved_62_63:2;
357 uint64_t pipe_err:1;
358 uint64_t ill_pad:1;
359 uint64_t sprt3_err:1;
360 uint64_t sprt2_err:1;
361 uint64_t sprt1_err:1;
362 uint64_t sprt0_err:1;
363 uint64_t pins_err:1;
364 uint64_t pop_err:1;
365 uint64_t pdi_err:1;
366 uint64_t pgl_err:1;
367 uint64_t pin_bp:1;
368 uint64_t pout_err:1;
369 uint64_t psldbof:1;
370 uint64_t pidbof:1;
371 uint64_t reserved_38_47:10;
372 uint64_t dtime:2;
373 uint64_t dcnt:2;
374 uint64_t dmafi:2;
375 uint64_t reserved_28_31:4;
376 uint64_t m3_un_wi:1;
377 uint64_t m3_un_b0:1;
378 uint64_t m3_up_wi:1;
379 uint64_t m3_up_b0:1;
380 uint64_t m2_un_wi:1;
381 uint64_t m2_un_b0:1;
382 uint64_t m2_up_wi:1;
383 uint64_t m2_up_b0:1;
384 uint64_t reserved_18_19:2;
385 uint64_t mio_int1:1;
386 uint64_t mio_int0:1;
387 uint64_t m1_un_wi:1;
388 uint64_t m1_un_b0:1;
389 uint64_t m1_up_wi:1;
390 uint64_t m1_up_b0:1;
391 uint64_t m0_un_wi:1;
392 uint64_t m0_un_b0:1;
393 uint64_t m0_up_wi:1;
394 uint64_t m0_up_b0:1;
395 uint64_t reserved_6_7:2;
396 uint64_t ptime:1;
397 uint64_t pcnt:1;
398 uint64_t iob2big:1;
399 uint64_t bar0_to:1;
400 uint64_t reserved_1_1:1;
401 uint64_t rml_to:1;
402 } s;
403 struct cvmx_sli_int_enb_ciu_cn61xx {
404 uint64_t reserved_61_63:3;
405 uint64_t ill_pad:1;
406 uint64_t sprt3_err:1;
407 uint64_t sprt2_err:1;
408 uint64_t sprt1_err:1;
409 uint64_t sprt0_err:1;
410 uint64_t pins_err:1;
411 uint64_t pop_err:1;
412 uint64_t pdi_err:1;
413 uint64_t pgl_err:1;
414 uint64_t pin_bp:1;
415 uint64_t pout_err:1;
416 uint64_t psldbof:1;
417 uint64_t pidbof:1;
418 uint64_t reserved_38_47:10;
419 uint64_t dtime:2;
420 uint64_t dcnt:2;
421 uint64_t dmafi:2;
422 uint64_t reserved_28_31:4;
423 uint64_t m3_un_wi:1;
424 uint64_t m3_un_b0:1;
425 uint64_t m3_up_wi:1;
426 uint64_t m3_up_b0:1;
427 uint64_t m2_un_wi:1;
428 uint64_t m2_un_b0:1;
429 uint64_t m2_up_wi:1;
430 uint64_t m2_up_b0:1;
431 uint64_t reserved_18_19:2;
432 uint64_t mio_int1:1;
433 uint64_t mio_int0:1;
434 uint64_t m1_un_wi:1;
435 uint64_t m1_un_b0:1;
436 uint64_t m1_up_wi:1;
437 uint64_t m1_up_b0:1;
438 uint64_t m0_un_wi:1;
439 uint64_t m0_un_b0:1;
440 uint64_t m0_up_wi:1;
441 uint64_t m0_up_b0:1;
442 uint64_t reserved_6_7:2;
443 uint64_t ptime:1;
444 uint64_t pcnt:1;
445 uint64_t iob2big:1;
446 uint64_t bar0_to:1;
447 uint64_t reserved_1_1:1;
448 uint64_t rml_to:1;
449 } cn61xx;
450 struct cvmx_sli_int_enb_ciu_cn63xx {
451 uint64_t reserved_61_63:3;
452 uint64_t ill_pad:1;
453 uint64_t reserved_58_59:2;
454 uint64_t sprt1_err:1;
455 uint64_t sprt0_err:1;
456 uint64_t pins_err:1;
457 uint64_t pop_err:1;
458 uint64_t pdi_err:1;
459 uint64_t pgl_err:1;
460 uint64_t pin_bp:1;
461 uint64_t pout_err:1;
462 uint64_t psldbof:1;
463 uint64_t pidbof:1;
464 uint64_t reserved_38_47:10;
465 uint64_t dtime:2;
466 uint64_t dcnt:2;
467 uint64_t dmafi:2;
468 uint64_t reserved_18_31:14;
469 uint64_t mio_int1:1;
470 uint64_t mio_int0:1;
471 uint64_t m1_un_wi:1;
472 uint64_t m1_un_b0:1;
473 uint64_t m1_up_wi:1;
474 uint64_t m1_up_b0:1;
475 uint64_t m0_un_wi:1;
476 uint64_t m0_un_b0:1;
477 uint64_t m0_up_wi:1;
478 uint64_t m0_up_b0:1;
479 uint64_t reserved_6_7:2;
480 uint64_t ptime:1;
481 uint64_t pcnt:1;
482 uint64_t iob2big:1;
483 uint64_t bar0_to:1;
484 uint64_t reserved_1_1:1;
485 uint64_t rml_to:1;
486 } cn63xx;
487 struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
488 struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
489 struct cvmx_sli_int_enb_ciu_cn68xx {
490 uint64_t reserved_62_63:2;
491 uint64_t pipe_err:1;
492 uint64_t ill_pad:1;
493 uint64_t reserved_58_59:2;
494 uint64_t sprt1_err:1;
495 uint64_t sprt0_err:1;
496 uint64_t pins_err:1;
497 uint64_t pop_err:1;
498 uint64_t pdi_err:1;
499 uint64_t pgl_err:1;
500 uint64_t reserved_51_51:1;
501 uint64_t pout_err:1;
502 uint64_t psldbof:1;
503 uint64_t pidbof:1;
504 uint64_t reserved_38_47:10;
505 uint64_t dtime:2;
506 uint64_t dcnt:2;
507 uint64_t dmafi:2;
508 uint64_t reserved_18_31:14;
509 uint64_t mio_int1:1;
510 uint64_t mio_int0:1;
511 uint64_t m1_un_wi:1;
512 uint64_t m1_un_b0:1;
513 uint64_t m1_up_wi:1;
514 uint64_t m1_up_b0:1;
515 uint64_t m0_un_wi:1;
516 uint64_t m0_un_b0:1;
517 uint64_t m0_up_wi:1;
518 uint64_t m0_up_b0:1;
519 uint64_t reserved_6_7:2;
520 uint64_t ptime:1;
521 uint64_t pcnt:1;
522 uint64_t iob2big:1;
523 uint64_t bar0_to:1;
524 uint64_t reserved_1_1:1;
525 uint64_t rml_to:1;
526 } cn68xx;
527 struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
528};
529
530union cvmx_sli_int_enb_portx {
531 uint64_t u64;
532 struct cvmx_sli_int_enb_portx_s {
533 uint64_t reserved_62_63:2;
534 uint64_t pipe_err:1;
535 uint64_t ill_pad:1;
536 uint64_t sprt3_err:1;
537 uint64_t sprt2_err:1;
538 uint64_t sprt1_err:1;
539 uint64_t sprt0_err:1;
540 uint64_t pins_err:1;
541 uint64_t pop_err:1;
542 uint64_t pdi_err:1;
543 uint64_t pgl_err:1;
544 uint64_t pin_bp:1;
545 uint64_t pout_err:1;
546 uint64_t psldbof:1;
547 uint64_t pidbof:1;
548 uint64_t reserved_38_47:10;
549 uint64_t dtime:2;
550 uint64_t dcnt:2;
551 uint64_t dmafi:2;
552 uint64_t reserved_28_31:4;
553 uint64_t m3_un_wi:1;
554 uint64_t m3_un_b0:1;
555 uint64_t m3_up_wi:1;
556 uint64_t m3_up_b0:1;
557 uint64_t m2_un_wi:1;
558 uint64_t m2_un_b0:1;
559 uint64_t m2_up_wi:1;
560 uint64_t m2_up_b0:1;
561 uint64_t mac1_int:1;
562 uint64_t mac0_int:1;
563 uint64_t mio_int1:1;
564 uint64_t mio_int0:1;
565 uint64_t m1_un_wi:1;
566 uint64_t m1_un_b0:1;
567 uint64_t m1_up_wi:1;
568 uint64_t m1_up_b0:1;
569 uint64_t m0_un_wi:1;
570 uint64_t m0_un_b0:1;
571 uint64_t m0_up_wi:1;
572 uint64_t m0_up_b0:1;
573 uint64_t reserved_6_7:2;
574 uint64_t ptime:1;
575 uint64_t pcnt:1;
576 uint64_t iob2big:1;
577 uint64_t bar0_to:1;
578 uint64_t reserved_1_1:1;
579 uint64_t rml_to:1;
580 } s;
581 struct cvmx_sli_int_enb_portx_cn61xx {
582 uint64_t reserved_61_63:3;
583 uint64_t ill_pad:1;
584 uint64_t sprt3_err:1;
585 uint64_t sprt2_err:1;
586 uint64_t sprt1_err:1;
587 uint64_t sprt0_err:1;
588 uint64_t pins_err:1;
589 uint64_t pop_err:1;
590 uint64_t pdi_err:1;
591 uint64_t pgl_err:1;
592 uint64_t pin_bp:1;
593 uint64_t pout_err:1;
594 uint64_t psldbof:1;
595 uint64_t pidbof:1;
596 uint64_t reserved_38_47:10;
597 uint64_t dtime:2;
598 uint64_t dcnt:2;
599 uint64_t dmafi:2;
600 uint64_t reserved_28_31:4;
601 uint64_t m3_un_wi:1;
602 uint64_t m3_un_b0:1;
603 uint64_t m3_up_wi:1;
604 uint64_t m3_up_b0:1;
605 uint64_t m2_un_wi:1;
606 uint64_t m2_un_b0:1;
607 uint64_t m2_up_wi:1;
608 uint64_t m2_up_b0:1;
609 uint64_t mac1_int:1;
610 uint64_t mac0_int:1;
611 uint64_t mio_int1:1;
612 uint64_t mio_int0:1;
613 uint64_t m1_un_wi:1;
614 uint64_t m1_un_b0:1;
615 uint64_t m1_up_wi:1;
616 uint64_t m1_up_b0:1;
617 uint64_t m0_un_wi:1;
618 uint64_t m0_un_b0:1;
619 uint64_t m0_up_wi:1;
620 uint64_t m0_up_b0:1;
621 uint64_t reserved_6_7:2;
622 uint64_t ptime:1;
623 uint64_t pcnt:1;
624 uint64_t iob2big:1;
625 uint64_t bar0_to:1;
626 uint64_t reserved_1_1:1;
627 uint64_t rml_to:1;
628 } cn61xx;
629 struct cvmx_sli_int_enb_portx_cn63xx {
630 uint64_t reserved_61_63:3;
631 uint64_t ill_pad:1;
632 uint64_t reserved_58_59:2;
633 uint64_t sprt1_err:1;
634 uint64_t sprt0_err:1;
635 uint64_t pins_err:1;
636 uint64_t pop_err:1;
637 uint64_t pdi_err:1;
638 uint64_t pgl_err:1;
639 uint64_t pin_bp:1;
640 uint64_t pout_err:1;
641 uint64_t psldbof:1;
642 uint64_t pidbof:1;
643 uint64_t reserved_38_47:10;
644 uint64_t dtime:2;
645 uint64_t dcnt:2;
646 uint64_t dmafi:2;
647 uint64_t reserved_20_31:12;
648 uint64_t mac1_int:1;
649 uint64_t mac0_int:1;
650 uint64_t mio_int1:1;
651 uint64_t mio_int0:1;
652 uint64_t m1_un_wi:1;
653 uint64_t m1_un_b0:1;
654 uint64_t m1_up_wi:1;
655 uint64_t m1_up_b0:1;
656 uint64_t m0_un_wi:1;
657 uint64_t m0_un_b0:1;
658 uint64_t m0_up_wi:1;
659 uint64_t m0_up_b0:1;
660 uint64_t reserved_6_7:2;
661 uint64_t ptime:1;
662 uint64_t pcnt:1;
663 uint64_t iob2big:1;
664 uint64_t bar0_to:1;
665 uint64_t reserved_1_1:1;
666 uint64_t rml_to:1;
667 } cn63xx;
668 struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
669 struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
670 struct cvmx_sli_int_enb_portx_cn68xx {
671 uint64_t reserved_62_63:2;
672 uint64_t pipe_err:1;
673 uint64_t ill_pad:1;
674 uint64_t reserved_58_59:2;
675 uint64_t sprt1_err:1;
676 uint64_t sprt0_err:1;
677 uint64_t pins_err:1;
678 uint64_t pop_err:1;
679 uint64_t pdi_err:1;
680 uint64_t pgl_err:1;
681 uint64_t reserved_51_51:1;
682 uint64_t pout_err:1;
683 uint64_t psldbof:1;
684 uint64_t pidbof:1;
685 uint64_t reserved_38_47:10;
686 uint64_t dtime:2;
687 uint64_t dcnt:2;
688 uint64_t dmafi:2;
689 uint64_t reserved_20_31:12;
690 uint64_t mac1_int:1;
691 uint64_t mac0_int:1;
692 uint64_t mio_int1:1;
693 uint64_t mio_int0:1;
694 uint64_t m1_un_wi:1;
695 uint64_t m1_un_b0:1;
696 uint64_t m1_up_wi:1;
697 uint64_t m1_up_b0:1;
698 uint64_t m0_un_wi:1;
699 uint64_t m0_un_b0:1;
700 uint64_t m0_up_wi:1;
701 uint64_t m0_up_b0:1;
702 uint64_t reserved_6_7:2;
703 uint64_t ptime:1;
704 uint64_t pcnt:1;
705 uint64_t iob2big:1;
706 uint64_t bar0_to:1;
707 uint64_t reserved_1_1:1;
708 uint64_t rml_to:1;
709 } cn68xx;
710 struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
711};
712
713union cvmx_sli_int_sum {
714 uint64_t u64;
715 struct cvmx_sli_int_sum_s {
716 uint64_t reserved_62_63:2;
717 uint64_t pipe_err:1;
718 uint64_t ill_pad:1;
719 uint64_t sprt3_err:1;
720 uint64_t sprt2_err:1;
721 uint64_t sprt1_err:1;
722 uint64_t sprt0_err:1;
723 uint64_t pins_err:1;
724 uint64_t pop_err:1;
725 uint64_t pdi_err:1;
726 uint64_t pgl_err:1;
727 uint64_t pin_bp:1;
728 uint64_t pout_err:1;
729 uint64_t psldbof:1;
730 uint64_t pidbof:1;
731 uint64_t reserved_38_47:10;
732 uint64_t dtime:2;
733 uint64_t dcnt:2;
734 uint64_t dmafi:2;
735 uint64_t reserved_28_31:4;
736 uint64_t m3_un_wi:1;
737 uint64_t m3_un_b0:1;
738 uint64_t m3_up_wi:1;
739 uint64_t m3_up_b0:1;
740 uint64_t m2_un_wi:1;
741 uint64_t m2_un_b0:1;
742 uint64_t m2_up_wi:1;
743 uint64_t m2_up_b0:1;
744 uint64_t mac1_int:1;
745 uint64_t mac0_int:1;
746 uint64_t mio_int1:1;
747 uint64_t mio_int0:1;
748 uint64_t m1_un_wi:1;
749 uint64_t m1_un_b0:1;
750 uint64_t m1_up_wi:1;
751 uint64_t m1_up_b0:1;
752 uint64_t m0_un_wi:1;
753 uint64_t m0_un_b0:1;
754 uint64_t m0_up_wi:1;
755 uint64_t m0_up_b0:1;
756 uint64_t reserved_6_7:2;
757 uint64_t ptime:1;
758 uint64_t pcnt:1;
759 uint64_t iob2big:1;
760 uint64_t bar0_to:1;
761 uint64_t reserved_1_1:1;
762 uint64_t rml_to:1;
763 } s;
764 struct cvmx_sli_int_sum_cn61xx {
765 uint64_t reserved_61_63:3;
766 uint64_t ill_pad:1;
767 uint64_t sprt3_err:1;
768 uint64_t sprt2_err:1;
769 uint64_t sprt1_err:1;
770 uint64_t sprt0_err:1;
771 uint64_t pins_err:1;
772 uint64_t pop_err:1;
773 uint64_t pdi_err:1;
774 uint64_t pgl_err:1;
775 uint64_t pin_bp:1;
776 uint64_t pout_err:1;
777 uint64_t psldbof:1;
778 uint64_t pidbof:1;
779 uint64_t reserved_38_47:10;
780 uint64_t dtime:2;
781 uint64_t dcnt:2;
782 uint64_t dmafi:2;
783 uint64_t reserved_28_31:4;
784 uint64_t m3_un_wi:1;
785 uint64_t m3_un_b0:1;
786 uint64_t m3_up_wi:1;
787 uint64_t m3_up_b0:1;
788 uint64_t m2_un_wi:1;
789 uint64_t m2_un_b0:1;
790 uint64_t m2_up_wi:1;
791 uint64_t m2_up_b0:1;
792 uint64_t mac1_int:1;
793 uint64_t mac0_int:1;
794 uint64_t mio_int1:1;
795 uint64_t mio_int0:1;
796 uint64_t m1_un_wi:1;
797 uint64_t m1_un_b0:1;
798 uint64_t m1_up_wi:1;
799 uint64_t m1_up_b0:1;
800 uint64_t m0_un_wi:1;
801 uint64_t m0_un_b0:1;
802 uint64_t m0_up_wi:1;
803 uint64_t m0_up_b0:1;
804 uint64_t reserved_6_7:2;
805 uint64_t ptime:1;
806 uint64_t pcnt:1;
807 uint64_t iob2big:1;
808 uint64_t bar0_to:1;
809 uint64_t reserved_1_1:1;
810 uint64_t rml_to:1;
811 } cn61xx;
812 struct cvmx_sli_int_sum_cn63xx {
813 uint64_t reserved_61_63:3;
814 uint64_t ill_pad:1;
815 uint64_t reserved_58_59:2;
816 uint64_t sprt1_err:1;
817 uint64_t sprt0_err:1;
818 uint64_t pins_err:1;
819 uint64_t pop_err:1;
820 uint64_t pdi_err:1;
821 uint64_t pgl_err:1;
822 uint64_t pin_bp:1;
823 uint64_t pout_err:1;
824 uint64_t psldbof:1;
825 uint64_t pidbof:1;
826 uint64_t reserved_38_47:10;
827 uint64_t dtime:2;
828 uint64_t dcnt:2;
829 uint64_t dmafi:2;
830 uint64_t reserved_20_31:12;
831 uint64_t mac1_int:1;
832 uint64_t mac0_int:1;
833 uint64_t mio_int1:1;
834 uint64_t mio_int0:1;
835 uint64_t m1_un_wi:1;
836 uint64_t m1_un_b0:1;
837 uint64_t m1_up_wi:1;
838 uint64_t m1_up_b0:1;
839 uint64_t m0_un_wi:1;
840 uint64_t m0_un_b0:1;
841 uint64_t m0_up_wi:1;
842 uint64_t m0_up_b0:1;
843 uint64_t reserved_6_7:2;
844 uint64_t ptime:1;
845 uint64_t pcnt:1;
846 uint64_t iob2big:1;
847 uint64_t bar0_to:1;
848 uint64_t reserved_1_1:1;
849 uint64_t rml_to:1;
850 } cn63xx;
851 struct cvmx_sli_int_sum_cn63xx cn63xxp1;
852 struct cvmx_sli_int_sum_cn61xx cn66xx;
853 struct cvmx_sli_int_sum_cn68xx {
854 uint64_t reserved_62_63:2;
855 uint64_t pipe_err:1;
856 uint64_t ill_pad:1;
857 uint64_t reserved_58_59:2;
858 uint64_t sprt1_err:1;
859 uint64_t sprt0_err:1;
860 uint64_t pins_err:1;
861 uint64_t pop_err:1;
862 uint64_t pdi_err:1;
863 uint64_t pgl_err:1;
864 uint64_t reserved_51_51:1;
865 uint64_t pout_err:1;
866 uint64_t psldbof:1;
867 uint64_t pidbof:1;
868 uint64_t reserved_38_47:10;
869 uint64_t dtime:2;
870 uint64_t dcnt:2;
871 uint64_t dmafi:2;
872 uint64_t reserved_20_31:12;
873 uint64_t mac1_int:1;
874 uint64_t mac0_int:1;
875 uint64_t mio_int1:1;
876 uint64_t mio_int0:1;
877 uint64_t m1_un_wi:1;
878 uint64_t m1_un_b0:1;
879 uint64_t m1_up_wi:1;
880 uint64_t m1_up_b0:1;
881 uint64_t m0_un_wi:1;
882 uint64_t m0_un_b0:1;
883 uint64_t m0_up_wi:1;
884 uint64_t m0_up_b0:1;
885 uint64_t reserved_6_7:2;
886 uint64_t ptime:1;
887 uint64_t pcnt:1;
888 uint64_t iob2big:1;
889 uint64_t bar0_to:1;
890 uint64_t reserved_1_1:1;
891 uint64_t rml_to:1;
892 } cn68xx;
893 struct cvmx_sli_int_sum_cn68xx cn68xxp1;
894};
895
896union cvmx_sli_last_win_rdata0 {
897 uint64_t u64;
898 struct cvmx_sli_last_win_rdata0_s {
899 uint64_t data:64;
900 } s;
901 struct cvmx_sli_last_win_rdata0_s cn61xx;
902 struct cvmx_sli_last_win_rdata0_s cn63xx;
903 struct cvmx_sli_last_win_rdata0_s cn63xxp1;
904 struct cvmx_sli_last_win_rdata0_s cn66xx;
905 struct cvmx_sli_last_win_rdata0_s cn68xx;
906 struct cvmx_sli_last_win_rdata0_s cn68xxp1;
907};
908
909union cvmx_sli_last_win_rdata1 {
910 uint64_t u64;
911 struct cvmx_sli_last_win_rdata1_s {
912 uint64_t data:64;
913 } s;
914 struct cvmx_sli_last_win_rdata1_s cn61xx;
915 struct cvmx_sli_last_win_rdata1_s cn63xx;
916 struct cvmx_sli_last_win_rdata1_s cn63xxp1;
917 struct cvmx_sli_last_win_rdata1_s cn66xx;
918 struct cvmx_sli_last_win_rdata1_s cn68xx;
919 struct cvmx_sli_last_win_rdata1_s cn68xxp1;
920};
921
922union cvmx_sli_last_win_rdata2 {
923 uint64_t u64;
924 struct cvmx_sli_last_win_rdata2_s {
925 uint64_t data:64;
926 } s;
927 struct cvmx_sli_last_win_rdata2_s cn61xx;
928 struct cvmx_sli_last_win_rdata2_s cn66xx;
929};
930
931union cvmx_sli_last_win_rdata3 {
932 uint64_t u64;
933 struct cvmx_sli_last_win_rdata3_s {
934 uint64_t data:64;
935 } s;
936 struct cvmx_sli_last_win_rdata3_s cn61xx;
937 struct cvmx_sli_last_win_rdata3_s cn66xx;
938};
939
940union cvmx_sli_mac_credit_cnt {
941 uint64_t u64;
942 struct cvmx_sli_mac_credit_cnt_s {
943 uint64_t reserved_54_63:10;
944 uint64_t p1_c_d:1;
945 uint64_t p1_n_d:1;
946 uint64_t p1_p_d:1;
947 uint64_t p0_c_d:1;
948 uint64_t p0_n_d:1;
949 uint64_t p0_p_d:1;
950 uint64_t p1_ccnt:8;
951 uint64_t p1_ncnt:8;
952 uint64_t p1_pcnt:8;
953 uint64_t p0_ccnt:8;
954 uint64_t p0_ncnt:8;
955 uint64_t p0_pcnt:8;
956 } s;
957 struct cvmx_sli_mac_credit_cnt_s cn61xx;
958 struct cvmx_sli_mac_credit_cnt_s cn63xx;
959 struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
960 uint64_t reserved_48_63:16;
961 uint64_t p1_ccnt:8;
962 uint64_t p1_ncnt:8;
963 uint64_t p1_pcnt:8;
964 uint64_t p0_ccnt:8;
965 uint64_t p0_ncnt:8;
966 uint64_t p0_pcnt:8;
967 } cn63xxp1;
968 struct cvmx_sli_mac_credit_cnt_s cn66xx;
969 struct cvmx_sli_mac_credit_cnt_s cn68xx;
970 struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
971};
972
973union cvmx_sli_mac_credit_cnt2 {
974 uint64_t u64;
975 struct cvmx_sli_mac_credit_cnt2_s {
976 uint64_t reserved_54_63:10;
977 uint64_t p3_c_d:1;
978 uint64_t p3_n_d:1;
979 uint64_t p3_p_d:1;
980 uint64_t p2_c_d:1;
981 uint64_t p2_n_d:1;
982 uint64_t p2_p_d:1;
983 uint64_t p3_ccnt:8;
984 uint64_t p3_ncnt:8;
985 uint64_t p3_pcnt:8;
986 uint64_t p2_ccnt:8;
987 uint64_t p2_ncnt:8;
988 uint64_t p2_pcnt:8;
989 } s;
990 struct cvmx_sli_mac_credit_cnt2_s cn61xx;
991 struct cvmx_sli_mac_credit_cnt2_s cn66xx;
992};
993
994union cvmx_sli_mac_number {
995 uint64_t u64;
996 struct cvmx_sli_mac_number_s {
997 uint64_t reserved_9_63:55;
998 uint64_t a_mode:1;
999 uint64_t num:8;
1000 } s;
1001 struct cvmx_sli_mac_number_s cn61xx;
1002 struct cvmx_sli_mac_number_cn63xx {
1003 uint64_t reserved_8_63:56;
1004 uint64_t num:8;
1005 } cn63xx;
1006 struct cvmx_sli_mac_number_s cn66xx;
1007 struct cvmx_sli_mac_number_cn63xx cn68xx;
1008 struct cvmx_sli_mac_number_cn63xx cn68xxp1;
1009};
1010
1011union cvmx_sli_mem_access_ctl {
1012 uint64_t u64;
1013 struct cvmx_sli_mem_access_ctl_s {
1014 uint64_t reserved_14_63:50;
1015 uint64_t max_word:4;
1016 uint64_t timer:10;
1017 } s;
1018 struct cvmx_sli_mem_access_ctl_s cn61xx;
1019 struct cvmx_sli_mem_access_ctl_s cn63xx;
1020 struct cvmx_sli_mem_access_ctl_s cn63xxp1;
1021 struct cvmx_sli_mem_access_ctl_s cn66xx;
1022 struct cvmx_sli_mem_access_ctl_s cn68xx;
1023 struct cvmx_sli_mem_access_ctl_s cn68xxp1;
1024};
1025
1026union cvmx_sli_mem_access_subidx {
1027 uint64_t u64;
1028 struct cvmx_sli_mem_access_subidx_s {
1029 uint64_t reserved_43_63:21;
1030 uint64_t zero:1;
1031 uint64_t port:3;
1032 uint64_t nmerge:1;
1033 uint64_t esr:2;
1034 uint64_t esw:2;
1035 uint64_t wtype:2;
1036 uint64_t rtype:2;
1037 uint64_t reserved_0_29:30;
1038 } s;
1039 struct cvmx_sli_mem_access_subidx_cn61xx {
1040 uint64_t reserved_43_63:21;
1041 uint64_t zero:1;
1042 uint64_t port:3;
1043 uint64_t nmerge:1;
1044 uint64_t esr:2;
1045 uint64_t esw:2;
1046 uint64_t wtype:2;
1047 uint64_t rtype:2;
1048 uint64_t ba:30;
1049 } cn61xx;
1050 struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
1051 struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
1052 struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
1053 struct cvmx_sli_mem_access_subidx_cn68xx {
1054 uint64_t reserved_43_63:21;
1055 uint64_t zero:1;
1056 uint64_t port:3;
1057 uint64_t nmerge:1;
1058 uint64_t esr:2;
1059 uint64_t esw:2;
1060 uint64_t wtype:2;
1061 uint64_t rtype:2;
1062 uint64_t ba:28;
1063 uint64_t reserved_0_1:2;
1064 } cn68xx;
1065 struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
1066};
1067
1068union cvmx_sli_msi_enb0 {
1069 uint64_t u64;
1070 struct cvmx_sli_msi_enb0_s {
1071 uint64_t enb:64;
1072 } s;
1073 struct cvmx_sli_msi_enb0_s cn61xx;
1074 struct cvmx_sli_msi_enb0_s cn63xx;
1075 struct cvmx_sli_msi_enb0_s cn63xxp1;
1076 struct cvmx_sli_msi_enb0_s cn66xx;
1077 struct cvmx_sli_msi_enb0_s cn68xx;
1078 struct cvmx_sli_msi_enb0_s cn68xxp1;
1079};
1080
1081union cvmx_sli_msi_enb1 {
1082 uint64_t u64;
1083 struct cvmx_sli_msi_enb1_s {
1084 uint64_t enb:64;
1085 } s;
1086 struct cvmx_sli_msi_enb1_s cn61xx;
1087 struct cvmx_sli_msi_enb1_s cn63xx;
1088 struct cvmx_sli_msi_enb1_s cn63xxp1;
1089 struct cvmx_sli_msi_enb1_s cn66xx;
1090 struct cvmx_sli_msi_enb1_s cn68xx;
1091 struct cvmx_sli_msi_enb1_s cn68xxp1;
1092};
1093
1094union cvmx_sli_msi_enb2 {
1095 uint64_t u64;
1096 struct cvmx_sli_msi_enb2_s {
1097 uint64_t enb:64;
1098 } s;
1099 struct cvmx_sli_msi_enb2_s cn61xx;
1100 struct cvmx_sli_msi_enb2_s cn63xx;
1101 struct cvmx_sli_msi_enb2_s cn63xxp1;
1102 struct cvmx_sli_msi_enb2_s cn66xx;
1103 struct cvmx_sli_msi_enb2_s cn68xx;
1104 struct cvmx_sli_msi_enb2_s cn68xxp1;
1105};
1106
1107union cvmx_sli_msi_enb3 {
1108 uint64_t u64;
1109 struct cvmx_sli_msi_enb3_s {
1110 uint64_t enb:64;
1111 } s;
1112 struct cvmx_sli_msi_enb3_s cn61xx;
1113 struct cvmx_sli_msi_enb3_s cn63xx;
1114 struct cvmx_sli_msi_enb3_s cn63xxp1;
1115 struct cvmx_sli_msi_enb3_s cn66xx;
1116 struct cvmx_sli_msi_enb3_s cn68xx;
1117 struct cvmx_sli_msi_enb3_s cn68xxp1;
1118};
1119
1120union cvmx_sli_msi_rcv0 {
1121 uint64_t u64;
1122 struct cvmx_sli_msi_rcv0_s {
1123 uint64_t intr:64;
1124 } s;
1125 struct cvmx_sli_msi_rcv0_s cn61xx;
1126 struct cvmx_sli_msi_rcv0_s cn63xx;
1127 struct cvmx_sli_msi_rcv0_s cn63xxp1;
1128 struct cvmx_sli_msi_rcv0_s cn66xx;
1129 struct cvmx_sli_msi_rcv0_s cn68xx;
1130 struct cvmx_sli_msi_rcv0_s cn68xxp1;
1131};
1132
1133union cvmx_sli_msi_rcv1 {
1134 uint64_t u64;
1135 struct cvmx_sli_msi_rcv1_s {
1136 uint64_t intr:64;
1137 } s;
1138 struct cvmx_sli_msi_rcv1_s cn61xx;
1139 struct cvmx_sli_msi_rcv1_s cn63xx;
1140 struct cvmx_sli_msi_rcv1_s cn63xxp1;
1141 struct cvmx_sli_msi_rcv1_s cn66xx;
1142 struct cvmx_sli_msi_rcv1_s cn68xx;
1143 struct cvmx_sli_msi_rcv1_s cn68xxp1;
1144};
1145
1146union cvmx_sli_msi_rcv2 {
1147 uint64_t u64;
1148 struct cvmx_sli_msi_rcv2_s {
1149 uint64_t intr:64;
1150 } s;
1151 struct cvmx_sli_msi_rcv2_s cn61xx;
1152 struct cvmx_sli_msi_rcv2_s cn63xx;
1153 struct cvmx_sli_msi_rcv2_s cn63xxp1;
1154 struct cvmx_sli_msi_rcv2_s cn66xx;
1155 struct cvmx_sli_msi_rcv2_s cn68xx;
1156 struct cvmx_sli_msi_rcv2_s cn68xxp1;
1157};
1158
1159union cvmx_sli_msi_rcv3 {
1160 uint64_t u64;
1161 struct cvmx_sli_msi_rcv3_s {
1162 uint64_t intr:64;
1163 } s;
1164 struct cvmx_sli_msi_rcv3_s cn61xx;
1165 struct cvmx_sli_msi_rcv3_s cn63xx;
1166 struct cvmx_sli_msi_rcv3_s cn63xxp1;
1167 struct cvmx_sli_msi_rcv3_s cn66xx;
1168 struct cvmx_sli_msi_rcv3_s cn68xx;
1169 struct cvmx_sli_msi_rcv3_s cn68xxp1;
1170};
1171
1172union cvmx_sli_msi_rd_map {
1173 uint64_t u64;
1174 struct cvmx_sli_msi_rd_map_s {
1175 uint64_t reserved_16_63:48;
1176 uint64_t rd_int:8;
1177 uint64_t msi_int:8;
1178 } s;
1179 struct cvmx_sli_msi_rd_map_s cn61xx;
1180 struct cvmx_sli_msi_rd_map_s cn63xx;
1181 struct cvmx_sli_msi_rd_map_s cn63xxp1;
1182 struct cvmx_sli_msi_rd_map_s cn66xx;
1183 struct cvmx_sli_msi_rd_map_s cn68xx;
1184 struct cvmx_sli_msi_rd_map_s cn68xxp1;
1185};
1186
1187union cvmx_sli_msi_w1c_enb0 {
1188 uint64_t u64;
1189 struct cvmx_sli_msi_w1c_enb0_s {
1190 uint64_t clr:64;
1191 } s;
1192 struct cvmx_sli_msi_w1c_enb0_s cn61xx;
1193 struct cvmx_sli_msi_w1c_enb0_s cn63xx;
1194 struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
1195 struct cvmx_sli_msi_w1c_enb0_s cn66xx;
1196 struct cvmx_sli_msi_w1c_enb0_s cn68xx;
1197 struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
1198};
1199
1200union cvmx_sli_msi_w1c_enb1 {
1201 uint64_t u64;
1202 struct cvmx_sli_msi_w1c_enb1_s {
1203 uint64_t clr:64;
1204 } s;
1205 struct cvmx_sli_msi_w1c_enb1_s cn61xx;
1206 struct cvmx_sli_msi_w1c_enb1_s cn63xx;
1207 struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
1208 struct cvmx_sli_msi_w1c_enb1_s cn66xx;
1209 struct cvmx_sli_msi_w1c_enb1_s cn68xx;
1210 struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
1211};
1212
1213union cvmx_sli_msi_w1c_enb2 {
1214 uint64_t u64;
1215 struct cvmx_sli_msi_w1c_enb2_s {
1216 uint64_t clr:64;
1217 } s;
1218 struct cvmx_sli_msi_w1c_enb2_s cn61xx;
1219 struct cvmx_sli_msi_w1c_enb2_s cn63xx;
1220 struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
1221 struct cvmx_sli_msi_w1c_enb2_s cn66xx;
1222 struct cvmx_sli_msi_w1c_enb2_s cn68xx;
1223 struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
1224};
1225
1226union cvmx_sli_msi_w1c_enb3 {
1227 uint64_t u64;
1228 struct cvmx_sli_msi_w1c_enb3_s {
1229 uint64_t clr:64;
1230 } s;
1231 struct cvmx_sli_msi_w1c_enb3_s cn61xx;
1232 struct cvmx_sli_msi_w1c_enb3_s cn63xx;
1233 struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
1234 struct cvmx_sli_msi_w1c_enb3_s cn66xx;
1235 struct cvmx_sli_msi_w1c_enb3_s cn68xx;
1236 struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
1237};
1238
1239union cvmx_sli_msi_w1s_enb0 {
1240 uint64_t u64;
1241 struct cvmx_sli_msi_w1s_enb0_s {
1242 uint64_t set:64;
1243 } s;
1244 struct cvmx_sli_msi_w1s_enb0_s cn61xx;
1245 struct cvmx_sli_msi_w1s_enb0_s cn63xx;
1246 struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
1247 struct cvmx_sli_msi_w1s_enb0_s cn66xx;
1248 struct cvmx_sli_msi_w1s_enb0_s cn68xx;
1249 struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
1250};
1251
1252union cvmx_sli_msi_w1s_enb1 {
1253 uint64_t u64;
1254 struct cvmx_sli_msi_w1s_enb1_s {
1255 uint64_t set:64;
1256 } s;
1257 struct cvmx_sli_msi_w1s_enb1_s cn61xx;
1258 struct cvmx_sli_msi_w1s_enb1_s cn63xx;
1259 struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
1260 struct cvmx_sli_msi_w1s_enb1_s cn66xx;
1261 struct cvmx_sli_msi_w1s_enb1_s cn68xx;
1262 struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
1263};
1264
1265union cvmx_sli_msi_w1s_enb2 {
1266 uint64_t u64;
1267 struct cvmx_sli_msi_w1s_enb2_s {
1268 uint64_t set:64;
1269 } s;
1270 struct cvmx_sli_msi_w1s_enb2_s cn61xx;
1271 struct cvmx_sli_msi_w1s_enb2_s cn63xx;
1272 struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
1273 struct cvmx_sli_msi_w1s_enb2_s cn66xx;
1274 struct cvmx_sli_msi_w1s_enb2_s cn68xx;
1275 struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
1276};
1277
1278union cvmx_sli_msi_w1s_enb3 {
1279 uint64_t u64;
1280 struct cvmx_sli_msi_w1s_enb3_s {
1281 uint64_t set:64;
1282 } s;
1283 struct cvmx_sli_msi_w1s_enb3_s cn61xx;
1284 struct cvmx_sli_msi_w1s_enb3_s cn63xx;
1285 struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
1286 struct cvmx_sli_msi_w1s_enb3_s cn66xx;
1287 struct cvmx_sli_msi_w1s_enb3_s cn68xx;
1288 struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
1289};
1290
1291union cvmx_sli_msi_wr_map {
1292 uint64_t u64;
1293 struct cvmx_sli_msi_wr_map_s {
1294 uint64_t reserved_16_63:48;
1295 uint64_t ciu_int:8;
1296 uint64_t msi_int:8;
1297 } s;
1298 struct cvmx_sli_msi_wr_map_s cn61xx;
1299 struct cvmx_sli_msi_wr_map_s cn63xx;
1300 struct cvmx_sli_msi_wr_map_s cn63xxp1;
1301 struct cvmx_sli_msi_wr_map_s cn66xx;
1302 struct cvmx_sli_msi_wr_map_s cn68xx;
1303 struct cvmx_sli_msi_wr_map_s cn68xxp1;
1304};
1305
1306union cvmx_sli_pcie_msi_rcv {
1307 uint64_t u64;
1308 struct cvmx_sli_pcie_msi_rcv_s {
1309 uint64_t reserved_8_63:56;
1310 uint64_t intr:8;
1311 } s;
1312 struct cvmx_sli_pcie_msi_rcv_s cn61xx;
1313 struct cvmx_sli_pcie_msi_rcv_s cn63xx;
1314 struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
1315 struct cvmx_sli_pcie_msi_rcv_s cn66xx;
1316 struct cvmx_sli_pcie_msi_rcv_s cn68xx;
1317 struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
1318};
1319
1320union cvmx_sli_pcie_msi_rcv_b1 {
1321 uint64_t u64;
1322 struct cvmx_sli_pcie_msi_rcv_b1_s {
1323 uint64_t reserved_16_63:48;
1324 uint64_t intr:8;
1325 uint64_t reserved_0_7:8;
1326 } s;
1327 struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
1328 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
1329 struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
1330 struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
1331 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
1332 struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
1333};
1334
1335union cvmx_sli_pcie_msi_rcv_b2 {
1336 uint64_t u64;
1337 struct cvmx_sli_pcie_msi_rcv_b2_s {
1338 uint64_t reserved_24_63:40;
1339 uint64_t intr:8;
1340 uint64_t reserved_0_15:16;
1341 } s;
1342 struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
1343 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
1344 struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
1345 struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
1346 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
1347 struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
1348};
1349
1350union cvmx_sli_pcie_msi_rcv_b3 {
1351 uint64_t u64;
1352 struct cvmx_sli_pcie_msi_rcv_b3_s {
1353 uint64_t reserved_32_63:32;
1354 uint64_t intr:8;
1355 uint64_t reserved_0_23:24;
1356 } s;
1357 struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
1358 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
1359 struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
1360 struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
1361 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
1362 struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
1363};
1364
1365union cvmx_sli_pktx_cnts {
1366 uint64_t u64;
1367 struct cvmx_sli_pktx_cnts_s {
1368 uint64_t reserved_54_63:10;
1369 uint64_t timer:22;
1370 uint64_t cnt:32;
1371 } s;
1372 struct cvmx_sli_pktx_cnts_s cn61xx;
1373 struct cvmx_sli_pktx_cnts_s cn63xx;
1374 struct cvmx_sli_pktx_cnts_s cn63xxp1;
1375 struct cvmx_sli_pktx_cnts_s cn66xx;
1376 struct cvmx_sli_pktx_cnts_s cn68xx;
1377 struct cvmx_sli_pktx_cnts_s cn68xxp1;
1378};
1379
1380union cvmx_sli_pktx_in_bp {
1381 uint64_t u64;
1382 struct cvmx_sli_pktx_in_bp_s {
1383 uint64_t wmark:32;
1384 uint64_t cnt:32;
1385 } s;
1386 struct cvmx_sli_pktx_in_bp_s cn61xx;
1387 struct cvmx_sli_pktx_in_bp_s cn63xx;
1388 struct cvmx_sli_pktx_in_bp_s cn63xxp1;
1389 struct cvmx_sli_pktx_in_bp_s cn66xx;
1390};
1391
1392union cvmx_sli_pktx_instr_baddr {
1393 uint64_t u64;
1394 struct cvmx_sli_pktx_instr_baddr_s {
1395 uint64_t addr:61;
1396 uint64_t reserved_0_2:3;
1397 } s;
1398 struct cvmx_sli_pktx_instr_baddr_s cn61xx;
1399 struct cvmx_sli_pktx_instr_baddr_s cn63xx;
1400 struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
1401 struct cvmx_sli_pktx_instr_baddr_s cn66xx;
1402 struct cvmx_sli_pktx_instr_baddr_s cn68xx;
1403 struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
1404};
1405
1406union cvmx_sli_pktx_instr_baoff_dbell {
1407 uint64_t u64;
1408 struct cvmx_sli_pktx_instr_baoff_dbell_s {
1409 uint64_t aoff:32;
1410 uint64_t dbell:32;
1411 } s;
1412 struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
1413 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
1414 struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
1415 struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
1416 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
1417 struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
1418};
1419
1420union cvmx_sli_pktx_instr_fifo_rsize {
1421 uint64_t u64;
1422 struct cvmx_sli_pktx_instr_fifo_rsize_s {
1423 uint64_t max:9;
1424 uint64_t rrp:9;
1425 uint64_t wrp:9;
1426 uint64_t fcnt:5;
1427 uint64_t rsize:32;
1428 } s;
1429 struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
1430 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
1431 struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
1432 struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
1433 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
1434 struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
1435};
1436
1437union cvmx_sli_pktx_instr_header {
1438 uint64_t u64;
1439 struct cvmx_sli_pktx_instr_header_s {
1440 uint64_t reserved_44_63:20;
1441 uint64_t pbp:1;
1442 uint64_t reserved_38_42:5;
1443 uint64_t rparmode:2;
1444 uint64_t reserved_35_35:1;
1445 uint64_t rskp_len:7;
1446 uint64_t rngrpext:2;
1447 uint64_t rnqos:1;
1448 uint64_t rngrp:1;
1449 uint64_t rntt:1;
1450 uint64_t rntag:1;
1451 uint64_t use_ihdr:1;
1452 uint64_t reserved_16_20:5;
1453 uint64_t par_mode:2;
1454 uint64_t reserved_13_13:1;
1455 uint64_t skp_len:7;
1456 uint64_t ngrpext:2;
1457 uint64_t nqos:1;
1458 uint64_t ngrp:1;
1459 uint64_t ntt:1;
1460 uint64_t ntag:1;
1461 } s;
1462 struct cvmx_sli_pktx_instr_header_cn61xx {
1463 uint64_t reserved_44_63:20;
1464 uint64_t pbp:1;
1465 uint64_t reserved_38_42:5;
1466 uint64_t rparmode:2;
1467 uint64_t reserved_35_35:1;
1468 uint64_t rskp_len:7;
1469 uint64_t reserved_26_27:2;
1470 uint64_t rnqos:1;
1471 uint64_t rngrp:1;
1472 uint64_t rntt:1;
1473 uint64_t rntag:1;
1474 uint64_t use_ihdr:1;
1475 uint64_t reserved_16_20:5;
1476 uint64_t par_mode:2;
1477 uint64_t reserved_13_13:1;
1478 uint64_t skp_len:7;
1479 uint64_t reserved_4_5:2;
1480 uint64_t nqos:1;
1481 uint64_t ngrp:1;
1482 uint64_t ntt:1;
1483 uint64_t ntag:1;
1484 } cn61xx;
1485 struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
1486 struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
1487 struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
1488 struct cvmx_sli_pktx_instr_header_s cn68xx;
1489 struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
1490};
1491
1492union cvmx_sli_pktx_out_size {
1493 uint64_t u64;
1494 struct cvmx_sli_pktx_out_size_s {
1495 uint64_t reserved_23_63:41;
1496 uint64_t isize:7;
1497 uint64_t bsize:16;
1498 } s;
1499 struct cvmx_sli_pktx_out_size_s cn61xx;
1500 struct cvmx_sli_pktx_out_size_s cn63xx;
1501 struct cvmx_sli_pktx_out_size_s cn63xxp1;
1502 struct cvmx_sli_pktx_out_size_s cn66xx;
1503 struct cvmx_sli_pktx_out_size_s cn68xx;
1504 struct cvmx_sli_pktx_out_size_s cn68xxp1;
1505};
1506
1507union cvmx_sli_pktx_slist_baddr {
1508 uint64_t u64;
1509 struct cvmx_sli_pktx_slist_baddr_s {
1510 uint64_t addr:60;
1511 uint64_t reserved_0_3:4;
1512 } s;
1513 struct cvmx_sli_pktx_slist_baddr_s cn61xx;
1514 struct cvmx_sli_pktx_slist_baddr_s cn63xx;
1515 struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
1516 struct cvmx_sli_pktx_slist_baddr_s cn66xx;
1517 struct cvmx_sli_pktx_slist_baddr_s cn68xx;
1518 struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
1519};
1520
1521union cvmx_sli_pktx_slist_baoff_dbell {
1522 uint64_t u64;
1523 struct cvmx_sli_pktx_slist_baoff_dbell_s {
1524 uint64_t aoff:32;
1525 uint64_t dbell:32;
1526 } s;
1527 struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
1528 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
1529 struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
1530 struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
1531 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
1532 struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
1533};
1534
1535union cvmx_sli_pktx_slist_fifo_rsize {
1536 uint64_t u64;
1537 struct cvmx_sli_pktx_slist_fifo_rsize_s {
1538 uint64_t reserved_32_63:32;
1539 uint64_t rsize:32;
1540 } s;
1541 struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
1542 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
1543 struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
1544 struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
1545 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
1546 struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
1547};
1548
1549union cvmx_sli_pkt_cnt_int {
1550 uint64_t u64;
1551 struct cvmx_sli_pkt_cnt_int_s {
1552 uint64_t reserved_32_63:32;
1553 uint64_t port:32;
1554 } s;
1555 struct cvmx_sli_pkt_cnt_int_s cn61xx;
1556 struct cvmx_sli_pkt_cnt_int_s cn63xx;
1557 struct cvmx_sli_pkt_cnt_int_s cn63xxp1;
1558 struct cvmx_sli_pkt_cnt_int_s cn66xx;
1559 struct cvmx_sli_pkt_cnt_int_s cn68xx;
1560 struct cvmx_sli_pkt_cnt_int_s cn68xxp1;
1561};
1562
1563union cvmx_sli_pkt_cnt_int_enb {
1564 uint64_t u64;
1565 struct cvmx_sli_pkt_cnt_int_enb_s {
1566 uint64_t reserved_32_63:32;
1567 uint64_t port:32;
1568 } s;
1569 struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
1570 struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
1571 struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
1572 struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
1573 struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
1574 struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
1575};
1576
1577union cvmx_sli_pkt_ctl {
1578 uint64_t u64;
1579 struct cvmx_sli_pkt_ctl_s {
1580 uint64_t reserved_5_63:59;
1581 uint64_t ring_en:1;
1582 uint64_t pkt_bp:4;
1583 } s;
1584 struct cvmx_sli_pkt_ctl_s cn61xx;
1585 struct cvmx_sli_pkt_ctl_s cn63xx;
1586 struct cvmx_sli_pkt_ctl_s cn63xxp1;
1587 struct cvmx_sli_pkt_ctl_s cn66xx;
1588 struct cvmx_sli_pkt_ctl_s cn68xx;
1589 struct cvmx_sli_pkt_ctl_s cn68xxp1;
1590};
1591
1592union cvmx_sli_pkt_data_out_es {
1593 uint64_t u64;
1594 struct cvmx_sli_pkt_data_out_es_s {
1595 uint64_t es:64;
1596 } s;
1597 struct cvmx_sli_pkt_data_out_es_s cn61xx;
1598 struct cvmx_sli_pkt_data_out_es_s cn63xx;
1599 struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
1600 struct cvmx_sli_pkt_data_out_es_s cn66xx;
1601 struct cvmx_sli_pkt_data_out_es_s cn68xx;
1602 struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
1603};
1604
1605union cvmx_sli_pkt_data_out_ns {
1606 uint64_t u64;
1607 struct cvmx_sli_pkt_data_out_ns_s {
1608 uint64_t reserved_32_63:32;
1609 uint64_t nsr:32;
1610 } s;
1611 struct cvmx_sli_pkt_data_out_ns_s cn61xx;
1612 struct cvmx_sli_pkt_data_out_ns_s cn63xx;
1613 struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
1614 struct cvmx_sli_pkt_data_out_ns_s cn66xx;
1615 struct cvmx_sli_pkt_data_out_ns_s cn68xx;
1616 struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
1617};
1618
1619union cvmx_sli_pkt_data_out_ror {
1620 uint64_t u64;
1621 struct cvmx_sli_pkt_data_out_ror_s {
1622 uint64_t reserved_32_63:32;
1623 uint64_t ror:32;
1624 } s;
1625 struct cvmx_sli_pkt_data_out_ror_s cn61xx;
1626 struct cvmx_sli_pkt_data_out_ror_s cn63xx;
1627 struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
1628 struct cvmx_sli_pkt_data_out_ror_s cn66xx;
1629 struct cvmx_sli_pkt_data_out_ror_s cn68xx;
1630 struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
1631};
1632
1633union cvmx_sli_pkt_dpaddr {
1634 uint64_t u64;
1635 struct cvmx_sli_pkt_dpaddr_s {
1636 uint64_t reserved_32_63:32;
1637 uint64_t dptr:32;
1638 } s;
1639 struct cvmx_sli_pkt_dpaddr_s cn61xx;
1640 struct cvmx_sli_pkt_dpaddr_s cn63xx;
1641 struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
1642 struct cvmx_sli_pkt_dpaddr_s cn66xx;
1643 struct cvmx_sli_pkt_dpaddr_s cn68xx;
1644 struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
1645};
1646
1647union cvmx_sli_pkt_in_bp {
1648 uint64_t u64;
1649 struct cvmx_sli_pkt_in_bp_s {
1650 uint64_t reserved_32_63:32;
1651 uint64_t bp:32;
1652 } s;
1653 struct cvmx_sli_pkt_in_bp_s cn61xx;
1654 struct cvmx_sli_pkt_in_bp_s cn63xx;
1655 struct cvmx_sli_pkt_in_bp_s cn63xxp1;
1656 struct cvmx_sli_pkt_in_bp_s cn66xx;
1657};
1658
1659union cvmx_sli_pkt_in_donex_cnts {
1660 uint64_t u64;
1661 struct cvmx_sli_pkt_in_donex_cnts_s {
1662 uint64_t reserved_32_63:32;
1663 uint64_t cnt:32;
1664 } s;
1665 struct cvmx_sli_pkt_in_donex_cnts_s cn61xx;
1666 struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
1667 struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1;
1668 struct cvmx_sli_pkt_in_donex_cnts_s cn66xx;
1669 struct cvmx_sli_pkt_in_donex_cnts_s cn68xx;
1670 struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1;
1671};
1672
1673union cvmx_sli_pkt_in_instr_counts {
1674 uint64_t u64;
1675 struct cvmx_sli_pkt_in_instr_counts_s {
1676 uint64_t wr_cnt:32;
1677 uint64_t rd_cnt:32;
1678 } s;
1679 struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
1680 struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
1681 struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
1682 struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
1683 struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
1684 struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
1685};
1686
1687union cvmx_sli_pkt_in_pcie_port {
1688 uint64_t u64;
1689 struct cvmx_sli_pkt_in_pcie_port_s {
1690 uint64_t pp:64;
1691 } s;
1692 struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
1693 struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
1694 struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
1695 struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
1696 struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
1697 struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
1698};
1699
1700union cvmx_sli_pkt_input_control {
1701 uint64_t u64;
1702 struct cvmx_sli_pkt_input_control_s {
1703 uint64_t prd_erst:1;
1704 uint64_t prd_rds:7;
1705 uint64_t gii_erst:1;
1706 uint64_t gii_rds:7;
1707 uint64_t reserved_41_47:7;
1708 uint64_t prc_idle:1;
1709 uint64_t reserved_24_39:16;
1710 uint64_t pin_rst:1;
1711 uint64_t pkt_rr:1;
1712 uint64_t pbp_dhi:13;
1713 uint64_t d_nsr:1;
1714 uint64_t d_esr:2;
1715 uint64_t d_ror:1;
1716 uint64_t use_csr:1;
1717 uint64_t nsr:1;
1718 uint64_t esr:2;
1719 uint64_t ror:1;
1720 } s;
1721 struct cvmx_sli_pkt_input_control_s cn61xx;
1722 struct cvmx_sli_pkt_input_control_cn63xx {
1723 uint64_t reserved_23_63:41;
1724 uint64_t pkt_rr:1;
1725 uint64_t pbp_dhi:13;
1726 uint64_t d_nsr:1;
1727 uint64_t d_esr:2;
1728 uint64_t d_ror:1;
1729 uint64_t use_csr:1;
1730 uint64_t nsr:1;
1731 uint64_t esr:2;
1732 uint64_t ror:1;
1733 } cn63xx;
1734 struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
1735 struct cvmx_sli_pkt_input_control_s cn66xx;
1736 struct cvmx_sli_pkt_input_control_s cn68xx;
1737 struct cvmx_sli_pkt_input_control_s cn68xxp1;
1738};
1739
1740union cvmx_sli_pkt_instr_enb {
1741 uint64_t u64;
1742 struct cvmx_sli_pkt_instr_enb_s {
1743 uint64_t reserved_32_63:32;
1744 uint64_t enb:32;
1745 } s;
1746 struct cvmx_sli_pkt_instr_enb_s cn61xx;
1747 struct cvmx_sli_pkt_instr_enb_s cn63xx;
1748 struct cvmx_sli_pkt_instr_enb_s cn63xxp1;
1749 struct cvmx_sli_pkt_instr_enb_s cn66xx;
1750 struct cvmx_sli_pkt_instr_enb_s cn68xx;
1751 struct cvmx_sli_pkt_instr_enb_s cn68xxp1;
1752};
1753
1754union cvmx_sli_pkt_instr_rd_size {
1755 uint64_t u64;
1756 struct cvmx_sli_pkt_instr_rd_size_s {
1757 uint64_t rdsize:64;
1758 } s;
1759 struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
1760 struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
1761 struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
1762 struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
1763 struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
1764 struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
1765};
1766
1767union cvmx_sli_pkt_instr_size {
1768 uint64_t u64;
1769 struct cvmx_sli_pkt_instr_size_s {
1770 uint64_t reserved_32_63:32;
1771 uint64_t is_64b:32;
1772 } s;
1773 struct cvmx_sli_pkt_instr_size_s cn61xx;
1774 struct cvmx_sli_pkt_instr_size_s cn63xx;
1775 struct cvmx_sli_pkt_instr_size_s cn63xxp1;
1776 struct cvmx_sli_pkt_instr_size_s cn66xx;
1777 struct cvmx_sli_pkt_instr_size_s cn68xx;
1778 struct cvmx_sli_pkt_instr_size_s cn68xxp1;
1779};
1780
1781union cvmx_sli_pkt_int_levels {
1782 uint64_t u64;
1783 struct cvmx_sli_pkt_int_levels_s {
1784 uint64_t reserved_54_63:10;
1785 uint64_t time:22;
1786 uint64_t cnt:32;
1787 } s;
1788 struct cvmx_sli_pkt_int_levels_s cn61xx;
1789 struct cvmx_sli_pkt_int_levels_s cn63xx;
1790 struct cvmx_sli_pkt_int_levels_s cn63xxp1;
1791 struct cvmx_sli_pkt_int_levels_s cn66xx;
1792 struct cvmx_sli_pkt_int_levels_s cn68xx;
1793 struct cvmx_sli_pkt_int_levels_s cn68xxp1;
1794};
1795
1796union cvmx_sli_pkt_iptr {
1797 uint64_t u64;
1798 struct cvmx_sli_pkt_iptr_s {
1799 uint64_t reserved_32_63:32;
1800 uint64_t iptr:32;
1801 } s;
1802 struct cvmx_sli_pkt_iptr_s cn61xx;
1803 struct cvmx_sli_pkt_iptr_s cn63xx;
1804 struct cvmx_sli_pkt_iptr_s cn63xxp1;
1805 struct cvmx_sli_pkt_iptr_s cn66xx;
1806 struct cvmx_sli_pkt_iptr_s cn68xx;
1807 struct cvmx_sli_pkt_iptr_s cn68xxp1;
1808};
1809
1810union cvmx_sli_pkt_out_bmode {
1811 uint64_t u64;
1812 struct cvmx_sli_pkt_out_bmode_s {
1813 uint64_t reserved_32_63:32;
1814 uint64_t bmode:32;
1815 } s;
1816 struct cvmx_sli_pkt_out_bmode_s cn61xx;
1817 struct cvmx_sli_pkt_out_bmode_s cn63xx;
1818 struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
1819 struct cvmx_sli_pkt_out_bmode_s cn66xx;
1820 struct cvmx_sli_pkt_out_bmode_s cn68xx;
1821 struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
1822};
1823
1824union cvmx_sli_pkt_out_bp_en {
1825 uint64_t u64;
1826 struct cvmx_sli_pkt_out_bp_en_s {
1827 uint64_t reserved_32_63:32;
1828 uint64_t bp_en:32;
1829 } s;
1830 struct cvmx_sli_pkt_out_bp_en_s cn68xx;
1831 struct cvmx_sli_pkt_out_bp_en_s cn68xxp1;
1832};
1833
1834union cvmx_sli_pkt_out_enb {
1835 uint64_t u64;
1836 struct cvmx_sli_pkt_out_enb_s {
1837 uint64_t reserved_32_63:32;
1838 uint64_t enb:32;
1839 } s;
1840 struct cvmx_sli_pkt_out_enb_s cn61xx;
1841 struct cvmx_sli_pkt_out_enb_s cn63xx;
1842 struct cvmx_sli_pkt_out_enb_s cn63xxp1;
1843 struct cvmx_sli_pkt_out_enb_s cn66xx;
1844 struct cvmx_sli_pkt_out_enb_s cn68xx;
1845 struct cvmx_sli_pkt_out_enb_s cn68xxp1;
1846};
1847
1848union cvmx_sli_pkt_output_wmark {
1849 uint64_t u64;
1850 struct cvmx_sli_pkt_output_wmark_s {
1851 uint64_t reserved_32_63:32;
1852 uint64_t wmark:32;
1853 } s;
1854 struct cvmx_sli_pkt_output_wmark_s cn61xx;
1855 struct cvmx_sli_pkt_output_wmark_s cn63xx;
1856 struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
1857 struct cvmx_sli_pkt_output_wmark_s cn66xx;
1858 struct cvmx_sli_pkt_output_wmark_s cn68xx;
1859 struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
1860};
1861
1862union cvmx_sli_pkt_pcie_port {
1863 uint64_t u64;
1864 struct cvmx_sli_pkt_pcie_port_s {
1865 uint64_t pp:64;
1866 } s;
1867 struct cvmx_sli_pkt_pcie_port_s cn61xx;
1868 struct cvmx_sli_pkt_pcie_port_s cn63xx;
1869 struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
1870 struct cvmx_sli_pkt_pcie_port_s cn66xx;
1871 struct cvmx_sli_pkt_pcie_port_s cn68xx;
1872 struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
1873};
1874
1875union cvmx_sli_pkt_port_in_rst {
1876 uint64_t u64;
1877 struct cvmx_sli_pkt_port_in_rst_s {
1878 uint64_t in_rst:32;
1879 uint64_t out_rst:32;
1880 } s;
1881 struct cvmx_sli_pkt_port_in_rst_s cn61xx;
1882 struct cvmx_sli_pkt_port_in_rst_s cn63xx;
1883 struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
1884 struct cvmx_sli_pkt_port_in_rst_s cn66xx;
1885 struct cvmx_sli_pkt_port_in_rst_s cn68xx;
1886 struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
1887};
1888
1889union cvmx_sli_pkt_slist_es {
1890 uint64_t u64;
1891 struct cvmx_sli_pkt_slist_es_s {
1892 uint64_t es:64;
1893 } s;
1894 struct cvmx_sli_pkt_slist_es_s cn61xx;
1895 struct cvmx_sli_pkt_slist_es_s cn63xx;
1896 struct cvmx_sli_pkt_slist_es_s cn63xxp1;
1897 struct cvmx_sli_pkt_slist_es_s cn66xx;
1898 struct cvmx_sli_pkt_slist_es_s cn68xx;
1899 struct cvmx_sli_pkt_slist_es_s cn68xxp1;
1900};
1901
1902union cvmx_sli_pkt_slist_ns {
1903 uint64_t u64;
1904 struct cvmx_sli_pkt_slist_ns_s {
1905 uint64_t reserved_32_63:32;
1906 uint64_t nsr:32;
1907 } s;
1908 struct cvmx_sli_pkt_slist_ns_s cn61xx;
1909 struct cvmx_sli_pkt_slist_ns_s cn63xx;
1910 struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
1911 struct cvmx_sli_pkt_slist_ns_s cn66xx;
1912 struct cvmx_sli_pkt_slist_ns_s cn68xx;
1913 struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
1914};
1915
1916union cvmx_sli_pkt_slist_ror {
1917 uint64_t u64;
1918 struct cvmx_sli_pkt_slist_ror_s {
1919 uint64_t reserved_32_63:32;
1920 uint64_t ror:32;
1921 } s;
1922 struct cvmx_sli_pkt_slist_ror_s cn61xx;
1923 struct cvmx_sli_pkt_slist_ror_s cn63xx;
1924 struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
1925 struct cvmx_sli_pkt_slist_ror_s cn66xx;
1926 struct cvmx_sli_pkt_slist_ror_s cn68xx;
1927 struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
1928};
1929
1930union cvmx_sli_pkt_time_int {
1931 uint64_t u64;
1932 struct cvmx_sli_pkt_time_int_s {
1933 uint64_t reserved_32_63:32;
1934 uint64_t port:32;
1935 } s;
1936 struct cvmx_sli_pkt_time_int_s cn61xx;
1937 struct cvmx_sli_pkt_time_int_s cn63xx;
1938 struct cvmx_sli_pkt_time_int_s cn63xxp1;
1939 struct cvmx_sli_pkt_time_int_s cn66xx;
1940 struct cvmx_sli_pkt_time_int_s cn68xx;
1941 struct cvmx_sli_pkt_time_int_s cn68xxp1;
1942};
1943
1944union cvmx_sli_pkt_time_int_enb {
1945 uint64_t u64;
1946 struct cvmx_sli_pkt_time_int_enb_s {
1947 uint64_t reserved_32_63:32;
1948 uint64_t port:32;
1949 } s;
1950 struct cvmx_sli_pkt_time_int_enb_s cn61xx;
1951 struct cvmx_sli_pkt_time_int_enb_s cn63xx;
1952 struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
1953 struct cvmx_sli_pkt_time_int_enb_s cn66xx;
1954 struct cvmx_sli_pkt_time_int_enb_s cn68xx;
1955 struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
1956};
1957
1958union cvmx_sli_portx_pkind {
1959 uint64_t u64;
1960 struct cvmx_sli_portx_pkind_s {
1961 uint64_t reserved_25_63:39;
1962 uint64_t rpk_enb:1;
1963 uint64_t reserved_22_23:2;
1964 uint64_t pkindr:6;
1965 uint64_t reserved_14_15:2;
1966 uint64_t bpkind:6;
1967 uint64_t reserved_6_7:2;
1968 uint64_t pkind:6;
1969 } s;
1970 struct cvmx_sli_portx_pkind_s cn68xx;
1971 struct cvmx_sli_portx_pkind_cn68xxp1 {
1972 uint64_t reserved_14_63:50;
1973 uint64_t bpkind:6;
1974 uint64_t reserved_6_7:2;
1975 uint64_t pkind:6;
1976 } cn68xxp1;
1977};
1978
1979union cvmx_sli_s2m_portx_ctl {
1980 uint64_t u64;
1981 struct cvmx_sli_s2m_portx_ctl_s {
1982 uint64_t reserved_5_63:59;
1983 uint64_t wind_d:1;
1984 uint64_t bar0_d:1;
1985 uint64_t mrrs:3;
1986 } s;
1987 struct cvmx_sli_s2m_portx_ctl_s cn61xx;
1988 struct cvmx_sli_s2m_portx_ctl_s cn63xx;
1989 struct cvmx_sli_s2m_portx_ctl_s cn63xxp1;
1990 struct cvmx_sli_s2m_portx_ctl_s cn66xx;
1991 struct cvmx_sli_s2m_portx_ctl_s cn68xx;
1992 struct cvmx_sli_s2m_portx_ctl_s cn68xxp1;
1993};
1994
1995union cvmx_sli_scratch_1 {
1996 uint64_t u64;
1997 struct cvmx_sli_scratch_1_s {
1998 uint64_t data:64;
1999 } s;
2000 struct cvmx_sli_scratch_1_s cn61xx;
2001 struct cvmx_sli_scratch_1_s cn63xx;
2002 struct cvmx_sli_scratch_1_s cn63xxp1;
2003 struct cvmx_sli_scratch_1_s cn66xx;
2004 struct cvmx_sli_scratch_1_s cn68xx;
2005 struct cvmx_sli_scratch_1_s cn68xxp1;
2006};
2007
2008union cvmx_sli_scratch_2 {
2009 uint64_t u64;
2010 struct cvmx_sli_scratch_2_s {
2011 uint64_t data:64;
2012 } s;
2013 struct cvmx_sli_scratch_2_s cn61xx;
2014 struct cvmx_sli_scratch_2_s cn63xx;
2015 struct cvmx_sli_scratch_2_s cn63xxp1;
2016 struct cvmx_sli_scratch_2_s cn66xx;
2017 struct cvmx_sli_scratch_2_s cn68xx;
2018 struct cvmx_sli_scratch_2_s cn68xxp1;
2019};
2020
2021union cvmx_sli_state1 {
2022 uint64_t u64;
2023 struct cvmx_sli_state1_s {
2024 uint64_t cpl1:12;
2025 uint64_t cpl0:12;
2026 uint64_t arb:1;
2027 uint64_t csr:39;
2028 } s;
2029 struct cvmx_sli_state1_s cn61xx;
2030 struct cvmx_sli_state1_s cn63xx;
2031 struct cvmx_sli_state1_s cn63xxp1;
2032 struct cvmx_sli_state1_s cn66xx;
2033 struct cvmx_sli_state1_s cn68xx;
2034 struct cvmx_sli_state1_s cn68xxp1;
2035};
2036
2037union cvmx_sli_state2 {
2038 uint64_t u64;
2039 struct cvmx_sli_state2_s {
2040 uint64_t reserved_56_63:8;
2041 uint64_t nnp1:8;
2042 uint64_t reserved_47_47:1;
2043 uint64_t rac:1;
2044 uint64_t csm1:15;
2045 uint64_t csm0:15;
2046 uint64_t nnp0:8;
2047 uint64_t nnd:8;
2048 } s;
2049 struct cvmx_sli_state2_s cn61xx;
2050 struct cvmx_sli_state2_s cn63xx;
2051 struct cvmx_sli_state2_s cn63xxp1;
2052 struct cvmx_sli_state2_s cn66xx;
2053 struct cvmx_sli_state2_s cn68xx;
2054 struct cvmx_sli_state2_s cn68xxp1;
2055};
2056
2057union cvmx_sli_state3 {
2058 uint64_t u64;
2059 struct cvmx_sli_state3_s {
2060 uint64_t reserved_56_63:8;
2061 uint64_t psm1:15;
2062 uint64_t psm0:15;
2063 uint64_t nsm1:13;
2064 uint64_t nsm0:13;
2065 } s;
2066 struct cvmx_sli_state3_s cn61xx;
2067 struct cvmx_sli_state3_s cn63xx;
2068 struct cvmx_sli_state3_s cn63xxp1;
2069 struct cvmx_sli_state3_s cn66xx;
2070 struct cvmx_sli_state3_s cn68xx;
2071 struct cvmx_sli_state3_s cn68xxp1;
2072};
2073
2074union cvmx_sli_tx_pipe {
2075 uint64_t u64;
2076 struct cvmx_sli_tx_pipe_s {
2077 uint64_t reserved_24_63:40;
2078 uint64_t nump:8;
2079 uint64_t reserved_7_15:9;
2080 uint64_t base:7;
2081 } s;
2082 struct cvmx_sli_tx_pipe_s cn68xx;
2083 struct cvmx_sli_tx_pipe_s cn68xxp1;
2084};
2085
2086union cvmx_sli_win_rd_addr {
2087 uint64_t u64;
2088 struct cvmx_sli_win_rd_addr_s {
2089 uint64_t reserved_51_63:13;
2090 uint64_t ld_cmd:2;
2091 uint64_t iobit:1;
2092 uint64_t rd_addr:48;
2093 } s;
2094 struct cvmx_sli_win_rd_addr_s cn61xx;
2095 struct cvmx_sli_win_rd_addr_s cn63xx;
2096 struct cvmx_sli_win_rd_addr_s cn63xxp1;
2097 struct cvmx_sli_win_rd_addr_s cn66xx;
2098 struct cvmx_sli_win_rd_addr_s cn68xx;
2099 struct cvmx_sli_win_rd_addr_s cn68xxp1;
2100};
2101
2102union cvmx_sli_win_rd_data {
2103 uint64_t u64;
2104 struct cvmx_sli_win_rd_data_s {
2105 uint64_t rd_data:64;
2106 } s;
2107 struct cvmx_sli_win_rd_data_s cn61xx;
2108 struct cvmx_sli_win_rd_data_s cn63xx;
2109 struct cvmx_sli_win_rd_data_s cn63xxp1;
2110 struct cvmx_sli_win_rd_data_s cn66xx;
2111 struct cvmx_sli_win_rd_data_s cn68xx;
2112 struct cvmx_sli_win_rd_data_s cn68xxp1;
2113};
2114
2115union cvmx_sli_win_wr_addr {
2116 uint64_t u64;
2117 struct cvmx_sli_win_wr_addr_s {
2118 uint64_t reserved_49_63:15;
2119 uint64_t iobit:1;
2120 uint64_t wr_addr:45;
2121 uint64_t reserved_0_2:3;
2122 } s;
2123 struct cvmx_sli_win_wr_addr_s cn61xx;
2124 struct cvmx_sli_win_wr_addr_s cn63xx;
2125 struct cvmx_sli_win_wr_addr_s cn63xxp1;
2126 struct cvmx_sli_win_wr_addr_s cn66xx;
2127 struct cvmx_sli_win_wr_addr_s cn68xx;
2128 struct cvmx_sli_win_wr_addr_s cn68xxp1;
2129};
2130
2131union cvmx_sli_win_wr_data {
2132 uint64_t u64;
2133 struct cvmx_sli_win_wr_data_s {
2134 uint64_t wr_data:64;
2135 } s;
2136 struct cvmx_sli_win_wr_data_s cn61xx;
2137 struct cvmx_sli_win_wr_data_s cn63xx;
2138 struct cvmx_sli_win_wr_data_s cn63xxp1;
2139 struct cvmx_sli_win_wr_data_s cn66xx;
2140 struct cvmx_sli_win_wr_data_s cn68xx;
2141 struct cvmx_sli_win_wr_data_s cn68xxp1;
2142};
2143
2144union cvmx_sli_win_wr_mask {
2145 uint64_t u64;
2146 struct cvmx_sli_win_wr_mask_s {
2147 uint64_t reserved_8_63:56;
2148 uint64_t wr_mask:8;
2149 } s;
2150 struct cvmx_sli_win_wr_mask_s cn61xx;
2151 struct cvmx_sli_win_wr_mask_s cn63xx;
2152 struct cvmx_sli_win_wr_mask_s cn63xxp1;
2153 struct cvmx_sli_win_wr_mask_s cn66xx;
2154 struct cvmx_sli_win_wr_mask_s cn68xx;
2155 struct cvmx_sli_win_wr_mask_s cn68xxp1;
2156};
2157
2158union cvmx_sli_window_ctl {
2159 uint64_t u64;
2160 struct cvmx_sli_window_ctl_s {
2161 uint64_t reserved_32_63:32;
2162 uint64_t time:32;
2163 } s;
2164 struct cvmx_sli_window_ctl_s cn61xx;
2165 struct cvmx_sli_window_ctl_s cn63xx;
2166 struct cvmx_sli_window_ctl_s cn63xxp1;
2167 struct cvmx_sli_window_ctl_s cn66xx;
2168 struct cvmx_sli_window_ctl_s cn68xx;
2169 struct cvmx_sli_window_ctl_s cn68xxp1;
2170};
2171
2172#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h
new file mode 100644
index 000000000000..e814648953a5
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-spi.h
@@ -0,0 +1,269 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * This file contains defines for the SPI interface
31 */
32#ifndef __CVMX_SPI_H__
33#define __CVMX_SPI_H__
34
35#include "cvmx-gmxx-defs.h"
36
37/* CSR typedefs have been moved to cvmx-csr-*.h */
38
39typedef enum {
40 CVMX_SPI_MODE_UNKNOWN = 0,
41 CVMX_SPI_MODE_TX_HALFPLEX = 1,
42 CVMX_SPI_MODE_RX_HALFPLEX = 2,
43 CVMX_SPI_MODE_DUPLEX = 3
44} cvmx_spi_mode_t;
45
46/** Callbacks structure to customize SPI4 initialization sequence */
47typedef struct {
48 /** Called to reset SPI4 DLL */
49 int (*reset_cb) (int interface, cvmx_spi_mode_t mode);
50
51 /** Called to setup calendar */
52 int (*calendar_setup_cb) (int interface, cvmx_spi_mode_t mode,
53 int num_ports);
54
55 /** Called for Tx and Rx clock detection */
56 int (*clock_detect_cb) (int interface, cvmx_spi_mode_t mode,
57 int timeout);
58
59 /** Called to perform link training */
60 int (*training_cb) (int interface, cvmx_spi_mode_t mode, int timeout);
61
62 /** Called for calendar data synchronization */
63 int (*calendar_sync_cb) (int interface, cvmx_spi_mode_t mode,
64 int timeout);
65
66 /** Called when interface is up */
67 int (*interface_up_cb) (int interface, cvmx_spi_mode_t mode);
68
69} cvmx_spi_callbacks_t;
70
71/**
72 * Return true if the supplied interface is configured for SPI
73 *
74 * @interface: Interface to check
75 * Returns True if interface is SPI
76 */
77static inline int cvmx_spi_is_spi_interface(int interface)
78{
79 uint64_t gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
80 return (gmxState & 0x2) && (gmxState & 0x1);
81}
82
83/**
84 * Initialize and start the SPI interface.
85 *
86 * @interface: The identifier of the packet interface to configure and
87 * use as a SPI interface.
88 * @mode: The operating mode for the SPI interface. The interface
89 * can operate as a full duplex (both Tx and Rx data paths
90 * active) or as a halfplex (either the Tx data path is
91 * active or the Rx data path is active, but not both).
92 * @timeout: Timeout to wait for clock synchronization in seconds
93 * @num_ports: Number of SPI ports to configure
94 *
95 * Returns Zero on success, negative of failure.
96 */
97extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode,
98 int timeout, int num_ports);
99
100/**
101 * This routine restarts the SPI interface after it has lost synchronization
102 * with its corespondant system.
103 *
104 * @interface: The identifier of the packet interface to configure and
105 * use as a SPI interface.
106 * @mode: The operating mode for the SPI interface. The interface
107 * can operate as a full duplex (both Tx and Rx data paths
108 * active) or as a halfplex (either the Tx data path is
109 * active or the Rx data path is active, but not both).
110 * @timeout: Timeout to wait for clock synchronization in seconds
111 * Returns Zero on success, negative of failure.
112 */
113extern int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode,
114 int timeout);
115
116/**
117 * Return non-zero if the SPI interface has a SPI4000 attached
118 *
119 * @interface: SPI interface the SPI4000 is connected to
120 *
121 * Returns
122 */
123static inline int cvmx_spi4000_is_present(int interface)
124{
125 return 0;
126}
127
128/**
129 * Initialize the SPI4000 for use
130 *
131 * @interface: SPI interface the SPI4000 is connected to
132 */
133static inline int cvmx_spi4000_initialize(int interface)
134{
135 return 0;
136}
137
138/**
139 * Poll all the SPI4000 port and check its speed
140 *
141 * @interface: Interface the SPI4000 is on
142 * @port: Port to poll (0-9)
143 * Returns Status of the port. 0=down. All other values the port is up.
144 */
145static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
146 int interface,
147 int port)
148{
149 union cvmx_gmxx_rxx_rx_inbnd r;
150 r.u64 = 0;
151 return r;
152}
153
154/**
155 * Get current SPI4 initialization callbacks
156 *
157 * @callbacks: Pointer to the callbacks structure.to fill
158 *
159 * Returns Pointer to cvmx_spi_callbacks_t structure.
160 */
161extern void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks);
162
163/**
164 * Set new SPI4 initialization callbacks
165 *
166 * @new_callbacks: Pointer to an updated callbacks structure.
167 */
168extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks);
169
170/**
171 * Callback to perform SPI4 reset
172 *
173 * @interface: The identifier of the packet interface to configure and
174 * use as a SPI interface.
175 * @mode: The operating mode for the SPI interface. The interface
176 * can operate as a full duplex (both Tx and Rx data paths
177 * active) or as a halfplex (either the Tx data path is
178 * active or the Rx data path is active, but not both).
179 *
180 * Returns Zero on success, non-zero error code on failure (will cause
181 * SPI initialization to abort)
182 */
183extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode);
184
185/**
186 * Callback to setup calendar and miscellaneous settings before clock
187 * detection
188 *
189 * @interface: The identifier of the packet interface to configure and
190 * use as a SPI interface.
191 * @mode: The operating mode for the SPI interface. The interface
192 * can operate as a full duplex (both Tx and Rx data paths
193 * active) or as a halfplex (either the Tx data path is
194 * active or the Rx data path is active, but not both).
195 * @num_ports: Number of ports to configure on SPI
196 *
197 * Returns Zero on success, non-zero error code on failure (will cause
198 * SPI initialization to abort)
199 */
200extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
201 int num_ports);
202
203/**
204 * Callback to perform clock detection
205 *
206 * @interface: The identifier of the packet interface to configure and
207 * use as a SPI interface.
208 * @mode: The operating mode for the SPI interface. The interface
209 * can operate as a full duplex (both Tx and Rx data paths
210 * active) or as a halfplex (either the Tx data path is
211 * active or the Rx data path is active, but not both).
212 * @timeout: Timeout to wait for clock synchronization in seconds
213 *
214 * Returns Zero on success, non-zero error code on failure (will cause
215 * SPI initialization to abort)
216 */
217extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode,
218 int timeout);
219
220/**
221 * Callback to perform link training
222 *
223 * @interface: The identifier of the packet interface to configure and
224 * use as a SPI interface.
225 * @mode: The operating mode for the SPI interface. The interface
226 * can operate as a full duplex (both Tx and Rx data paths
227 * active) or as a halfplex (either the Tx data path is
228 * active or the Rx data path is active, but not both).
229 * @timeout: Timeout to wait for link to be trained (in seconds)
230 *
231 * Returns Zero on success, non-zero error code on failure (will cause
232 * SPI initialization to abort)
233 */
234extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode,
235 int timeout);
236
237/**
238 * Callback to perform calendar data synchronization
239 *
240 * @interface: The identifier of the packet interface to configure and
241 * use as a SPI interface.
242 * @mode: The operating mode for the SPI interface. The interface
243 * can operate as a full duplex (both Tx and Rx data paths
244 * active) or as a halfplex (either the Tx data path is
245 * active or the Rx data path is active, but not both).
246 * @timeout: Timeout to wait for calendar data in seconds
247 *
248 * Returns Zero on success, non-zero error code on failure (will cause
249 * SPI initialization to abort)
250 */
251extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode,
252 int timeout);
253
254/**
255 * Callback to handle interface up
256 *
257 * @interface: The identifier of the packet interface to configure and
258 * use as a SPI interface.
259 * @mode: The operating mode for the SPI interface. The interface
260 * can operate as a full duplex (both Tx and Rx data paths
261 * active) or as a halfplex (either the Tx data path is
262 * active or the Rx data path is active, but not both).
263 *
264 * Returns Zero on success, non-zero error code on failure (will cause
265 * SPI initialization to abort)
266 */
267extern int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode);
268
269#endif /* __CVMX_SPI_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-spxx-defs.h b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
new file mode 100644
index 000000000000..b16940e32c83
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-spxx-defs.h
@@ -0,0 +1,347 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SPXX_DEFS_H__
29#define __CVMX_SPXX_DEFS_H__
30
31#define CVMX_SPXX_BCKPRS_CNT(block_id) \
32 CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_SPXX_BIST_STAT(block_id) \
34 CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_SPXX_CLK_CTL(block_id) \
36 CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_SPXX_CLK_STAT(block_id) \
38 CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \
40 CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \
42 CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_SPXX_DRV_CTL(block_id) \
44 CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_SPXX_ERR_CTL(block_id) \
46 CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_SPXX_INT_DAT(block_id) \
48 CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_SPXX_INT_MSK(block_id) \
50 CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_SPXX_INT_REG(block_id) \
52 CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_SPXX_INT_SYNC(block_id) \
54 CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_SPXX_TPA_ACC(block_id) \
56 CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_SPXX_TPA_MAX(block_id) \
58 CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_SPXX_TPA_SEL(block_id) \
60 CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_SPXX_TRN4_CTL(block_id) \
62 CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull))
63
64union cvmx_spxx_bckprs_cnt {
65 uint64_t u64;
66 struct cvmx_spxx_bckprs_cnt_s {
67 uint64_t reserved_32_63:32;
68 uint64_t cnt:32;
69 } s;
70 struct cvmx_spxx_bckprs_cnt_s cn38xx;
71 struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
72 struct cvmx_spxx_bckprs_cnt_s cn58xx;
73 struct cvmx_spxx_bckprs_cnt_s cn58xxp1;
74};
75
76union cvmx_spxx_bist_stat {
77 uint64_t u64;
78 struct cvmx_spxx_bist_stat_s {
79 uint64_t reserved_3_63:61;
80 uint64_t stat2:1;
81 uint64_t stat1:1;
82 uint64_t stat0:1;
83 } s;
84 struct cvmx_spxx_bist_stat_s cn38xx;
85 struct cvmx_spxx_bist_stat_s cn38xxp2;
86 struct cvmx_spxx_bist_stat_s cn58xx;
87 struct cvmx_spxx_bist_stat_s cn58xxp1;
88};
89
90union cvmx_spxx_clk_ctl {
91 uint64_t u64;
92 struct cvmx_spxx_clk_ctl_s {
93 uint64_t reserved_17_63:47;
94 uint64_t seetrn:1;
95 uint64_t reserved_12_15:4;
96 uint64_t clkdly:5;
97 uint64_t runbist:1;
98 uint64_t statdrv:1;
99 uint64_t statrcv:1;
100 uint64_t sndtrn:1;
101 uint64_t drptrn:1;
102 uint64_t rcvtrn:1;
103 uint64_t srxdlck:1;
104 } s;
105 struct cvmx_spxx_clk_ctl_s cn38xx;
106 struct cvmx_spxx_clk_ctl_s cn38xxp2;
107 struct cvmx_spxx_clk_ctl_s cn58xx;
108 struct cvmx_spxx_clk_ctl_s cn58xxp1;
109};
110
111union cvmx_spxx_clk_stat {
112 uint64_t u64;
113 struct cvmx_spxx_clk_stat_s {
114 uint64_t reserved_11_63:53;
115 uint64_t stxcal:1;
116 uint64_t reserved_9_9:1;
117 uint64_t srxtrn:1;
118 uint64_t s4clk1:1;
119 uint64_t s4clk0:1;
120 uint64_t d4clk1:1;
121 uint64_t d4clk0:1;
122 uint64_t reserved_0_3:4;
123 } s;
124 struct cvmx_spxx_clk_stat_s cn38xx;
125 struct cvmx_spxx_clk_stat_s cn38xxp2;
126 struct cvmx_spxx_clk_stat_s cn58xx;
127 struct cvmx_spxx_clk_stat_s cn58xxp1;
128};
129
130union cvmx_spxx_dbg_deskew_ctl {
131 uint64_t u64;
132 struct cvmx_spxx_dbg_deskew_ctl_s {
133 uint64_t reserved_30_63:34;
134 uint64_t fallnop:1;
135 uint64_t fall8:1;
136 uint64_t reserved_26_27:2;
137 uint64_t sstep_go:1;
138 uint64_t sstep:1;
139 uint64_t reserved_22_23:2;
140 uint64_t clrdly:1;
141 uint64_t dec:1;
142 uint64_t inc:1;
143 uint64_t mux:1;
144 uint64_t offset:5;
145 uint64_t bitsel:5;
146 uint64_t offdly:6;
147 uint64_t dllfrc:1;
148 uint64_t dlldis:1;
149 } s;
150 struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
151 struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
152 struct cvmx_spxx_dbg_deskew_ctl_s cn58xx;
153 struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1;
154};
155
156union cvmx_spxx_dbg_deskew_state {
157 uint64_t u64;
158 struct cvmx_spxx_dbg_deskew_state_s {
159 uint64_t reserved_9_63:55;
160 uint64_t testres:1;
161 uint64_t unxterm:1;
162 uint64_t muxsel:2;
163 uint64_t offset:5;
164 } s;
165 struct cvmx_spxx_dbg_deskew_state_s cn38xx;
166 struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
167 struct cvmx_spxx_dbg_deskew_state_s cn58xx;
168 struct cvmx_spxx_dbg_deskew_state_s cn58xxp1;
169};
170
171union cvmx_spxx_drv_ctl {
172 uint64_t u64;
173 struct cvmx_spxx_drv_ctl_s {
174 uint64_t reserved_0_63:64;
175 } s;
176 struct cvmx_spxx_drv_ctl_cn38xx {
177 uint64_t reserved_16_63:48;
178 uint64_t stx4ncmp:4;
179 uint64_t stx4pcmp:4;
180 uint64_t srx4cmp:8;
181 } cn38xx;
182 struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
183 struct cvmx_spxx_drv_ctl_cn58xx {
184 uint64_t reserved_24_63:40;
185 uint64_t stx4ncmp:4;
186 uint64_t stx4pcmp:4;
187 uint64_t reserved_10_15:6;
188 uint64_t srx4cmp:10;
189 } cn58xx;
190 struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
191};
192
193union cvmx_spxx_err_ctl {
194 uint64_t u64;
195 struct cvmx_spxx_err_ctl_s {
196 uint64_t reserved_9_63:55;
197 uint64_t prtnxa:1;
198 uint64_t dipcls:1;
199 uint64_t dippay:1;
200 uint64_t reserved_4_5:2;
201 uint64_t errcnt:4;
202 } s;
203 struct cvmx_spxx_err_ctl_s cn38xx;
204 struct cvmx_spxx_err_ctl_s cn38xxp2;
205 struct cvmx_spxx_err_ctl_s cn58xx;
206 struct cvmx_spxx_err_ctl_s cn58xxp1;
207};
208
209union cvmx_spxx_int_dat {
210 uint64_t u64;
211 struct cvmx_spxx_int_dat_s {
212 uint64_t reserved_32_63:32;
213 uint64_t mul:1;
214 uint64_t reserved_14_30:17;
215 uint64_t calbnk:2;
216 uint64_t rsvop:4;
217 uint64_t prt:8;
218 } s;
219 struct cvmx_spxx_int_dat_s cn38xx;
220 struct cvmx_spxx_int_dat_s cn38xxp2;
221 struct cvmx_spxx_int_dat_s cn58xx;
222 struct cvmx_spxx_int_dat_s cn58xxp1;
223};
224
225union cvmx_spxx_int_msk {
226 uint64_t u64;
227 struct cvmx_spxx_int_msk_s {
228 uint64_t reserved_12_63:52;
229 uint64_t calerr:1;
230 uint64_t syncerr:1;
231 uint64_t diperr:1;
232 uint64_t tpaovr:1;
233 uint64_t rsverr:1;
234 uint64_t drwnng:1;
235 uint64_t clserr:1;
236 uint64_t spiovr:1;
237 uint64_t reserved_2_3:2;
238 uint64_t abnorm:1;
239 uint64_t prtnxa:1;
240 } s;
241 struct cvmx_spxx_int_msk_s cn38xx;
242 struct cvmx_spxx_int_msk_s cn38xxp2;
243 struct cvmx_spxx_int_msk_s cn58xx;
244 struct cvmx_spxx_int_msk_s cn58xxp1;
245};
246
247union cvmx_spxx_int_reg {
248 uint64_t u64;
249 struct cvmx_spxx_int_reg_s {
250 uint64_t reserved_32_63:32;
251 uint64_t spf:1;
252 uint64_t reserved_12_30:19;
253 uint64_t calerr:1;
254 uint64_t syncerr:1;
255 uint64_t diperr:1;
256 uint64_t tpaovr:1;
257 uint64_t rsverr:1;
258 uint64_t drwnng:1;
259 uint64_t clserr:1;
260 uint64_t spiovr:1;
261 uint64_t reserved_2_3:2;
262 uint64_t abnorm:1;
263 uint64_t prtnxa:1;
264 } s;
265 struct cvmx_spxx_int_reg_s cn38xx;
266 struct cvmx_spxx_int_reg_s cn38xxp2;
267 struct cvmx_spxx_int_reg_s cn58xx;
268 struct cvmx_spxx_int_reg_s cn58xxp1;
269};
270
271union cvmx_spxx_int_sync {
272 uint64_t u64;
273 struct cvmx_spxx_int_sync_s {
274 uint64_t reserved_12_63:52;
275 uint64_t calerr:1;
276 uint64_t syncerr:1;
277 uint64_t diperr:1;
278 uint64_t tpaovr:1;
279 uint64_t rsverr:1;
280 uint64_t drwnng:1;
281 uint64_t clserr:1;
282 uint64_t spiovr:1;
283 uint64_t reserved_2_3:2;
284 uint64_t abnorm:1;
285 uint64_t prtnxa:1;
286 } s;
287 struct cvmx_spxx_int_sync_s cn38xx;
288 struct cvmx_spxx_int_sync_s cn38xxp2;
289 struct cvmx_spxx_int_sync_s cn58xx;
290 struct cvmx_spxx_int_sync_s cn58xxp1;
291};
292
293union cvmx_spxx_tpa_acc {
294 uint64_t u64;
295 struct cvmx_spxx_tpa_acc_s {
296 uint64_t reserved_32_63:32;
297 uint64_t cnt:32;
298 } s;
299 struct cvmx_spxx_tpa_acc_s cn38xx;
300 struct cvmx_spxx_tpa_acc_s cn38xxp2;
301 struct cvmx_spxx_tpa_acc_s cn58xx;
302 struct cvmx_spxx_tpa_acc_s cn58xxp1;
303};
304
305union cvmx_spxx_tpa_max {
306 uint64_t u64;
307 struct cvmx_spxx_tpa_max_s {
308 uint64_t reserved_32_63:32;
309 uint64_t max:32;
310 } s;
311 struct cvmx_spxx_tpa_max_s cn38xx;
312 struct cvmx_spxx_tpa_max_s cn38xxp2;
313 struct cvmx_spxx_tpa_max_s cn58xx;
314 struct cvmx_spxx_tpa_max_s cn58xxp1;
315};
316
317union cvmx_spxx_tpa_sel {
318 uint64_t u64;
319 struct cvmx_spxx_tpa_sel_s {
320 uint64_t reserved_4_63:60;
321 uint64_t prtsel:4;
322 } s;
323 struct cvmx_spxx_tpa_sel_s cn38xx;
324 struct cvmx_spxx_tpa_sel_s cn38xxp2;
325 struct cvmx_spxx_tpa_sel_s cn58xx;
326 struct cvmx_spxx_tpa_sel_s cn58xxp1;
327};
328
329union cvmx_spxx_trn4_ctl {
330 uint64_t u64;
331 struct cvmx_spxx_trn4_ctl_s {
332 uint64_t reserved_13_63:51;
333 uint64_t trntest:1;
334 uint64_t jitter:3;
335 uint64_t clr_boot:1;
336 uint64_t set_boot:1;
337 uint64_t maxdist:5;
338 uint64_t macro_en:1;
339 uint64_t mux_en:1;
340 } s;
341 struct cvmx_spxx_trn4_ctl_s cn38xx;
342 struct cvmx_spxx_trn4_ctl_s cn38xxp2;
343 struct cvmx_spxx_trn4_ctl_s cn58xx;
344 struct cvmx_spxx_trn4_ctl_s cn58xxp1;
345};
346
347#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
new file mode 100644
index 000000000000..7be7e9ed7465
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
@@ -0,0 +1,1036 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2011 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SRIOX_DEFS_H__
29#define __CVMX_SRIOX_DEFS_H__
30
31#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
32#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
33#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
34#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
35#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
36#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
37#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
38#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
39#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
40#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
41#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
42#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
43#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
44#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
45#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
46#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
47#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
48#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
49#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
50#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
51#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
52#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
53#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
54#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
55#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
56#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
57#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
58#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
59#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
60#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
61#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
62#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
63#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
64#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
65#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
66#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
67#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
68#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
69#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
70#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
71#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
72#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
73#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
74#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
75#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
76#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
77#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
78
79union cvmx_sriox_acc_ctrl {
80 uint64_t u64;
81 struct cvmx_sriox_acc_ctrl_s {
82 uint64_t reserved_7_63:57;
83 uint64_t deny_adr2:1;
84 uint64_t deny_adr1:1;
85 uint64_t deny_adr0:1;
86 uint64_t reserved_3_3:1;
87 uint64_t deny_bar2:1;
88 uint64_t deny_bar1:1;
89 uint64_t deny_bar0:1;
90 } s;
91 struct cvmx_sriox_acc_ctrl_cn63xx {
92 uint64_t reserved_3_63:61;
93 uint64_t deny_bar2:1;
94 uint64_t deny_bar1:1;
95 uint64_t deny_bar0:1;
96 } cn63xx;
97 struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
98 struct cvmx_sriox_acc_ctrl_s cn66xx;
99};
100
101union cvmx_sriox_asmbly_id {
102 uint64_t u64;
103 struct cvmx_sriox_asmbly_id_s {
104 uint64_t reserved_32_63:32;
105 uint64_t assy_id:16;
106 uint64_t assy_ven:16;
107 } s;
108 struct cvmx_sriox_asmbly_id_s cn63xx;
109 struct cvmx_sriox_asmbly_id_s cn63xxp1;
110 struct cvmx_sriox_asmbly_id_s cn66xx;
111};
112
113union cvmx_sriox_asmbly_info {
114 uint64_t u64;
115 struct cvmx_sriox_asmbly_info_s {
116 uint64_t reserved_32_63:32;
117 uint64_t assy_rev:16;
118 uint64_t reserved_0_15:16;
119 } s;
120 struct cvmx_sriox_asmbly_info_s cn63xx;
121 struct cvmx_sriox_asmbly_info_s cn63xxp1;
122 struct cvmx_sriox_asmbly_info_s cn66xx;
123};
124
125union cvmx_sriox_bell_resp_ctrl {
126 uint64_t u64;
127 struct cvmx_sriox_bell_resp_ctrl_s {
128 uint64_t reserved_6_63:58;
129 uint64_t rp1_sid:1;
130 uint64_t rp0_sid:2;
131 uint64_t rp1_pid:1;
132 uint64_t rp0_pid:2;
133 } s;
134 struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
135 struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
136 struct cvmx_sriox_bell_resp_ctrl_s cn66xx;
137};
138
139union cvmx_sriox_bist_status {
140 uint64_t u64;
141 struct cvmx_sriox_bist_status_s {
142 uint64_t reserved_45_63:19;
143 uint64_t lram:1;
144 uint64_t mram:2;
145 uint64_t cram:2;
146 uint64_t bell:2;
147 uint64_t otag:2;
148 uint64_t itag:1;
149 uint64_t ofree:1;
150 uint64_t rtn:2;
151 uint64_t obulk:4;
152 uint64_t optrs:4;
153 uint64_t oarb2:2;
154 uint64_t rxbuf2:2;
155 uint64_t oarb:2;
156 uint64_t ispf:1;
157 uint64_t ospf:1;
158 uint64_t txbuf:2;
159 uint64_t rxbuf:2;
160 uint64_t imsg:5;
161 uint64_t omsg:7;
162 } s;
163 struct cvmx_sriox_bist_status_cn63xx {
164 uint64_t reserved_44_63:20;
165 uint64_t mram:2;
166 uint64_t cram:2;
167 uint64_t bell:2;
168 uint64_t otag:2;
169 uint64_t itag:1;
170 uint64_t ofree:1;
171 uint64_t rtn:2;
172 uint64_t obulk:4;
173 uint64_t optrs:4;
174 uint64_t oarb2:2;
175 uint64_t rxbuf2:2;
176 uint64_t oarb:2;
177 uint64_t ispf:1;
178 uint64_t ospf:1;
179 uint64_t txbuf:2;
180 uint64_t rxbuf:2;
181 uint64_t imsg:5;
182 uint64_t omsg:7;
183 } cn63xx;
184 struct cvmx_sriox_bist_status_cn63xxp1 {
185 uint64_t reserved_44_63:20;
186 uint64_t mram:2;
187 uint64_t cram:2;
188 uint64_t bell:2;
189 uint64_t otag:2;
190 uint64_t itag:1;
191 uint64_t ofree:1;
192 uint64_t rtn:2;
193 uint64_t obulk:4;
194 uint64_t optrs:4;
195 uint64_t reserved_20_23:4;
196 uint64_t oarb:2;
197 uint64_t ispf:1;
198 uint64_t ospf:1;
199 uint64_t txbuf:2;
200 uint64_t rxbuf:2;
201 uint64_t imsg:5;
202 uint64_t omsg:7;
203 } cn63xxp1;
204 struct cvmx_sriox_bist_status_s cn66xx;
205};
206
207union cvmx_sriox_imsg_ctrl {
208 uint64_t u64;
209 struct cvmx_sriox_imsg_ctrl_s {
210 uint64_t reserved_32_63:32;
211 uint64_t to_mode:1;
212 uint64_t reserved_30_30:1;
213 uint64_t rsp_thr:6;
214 uint64_t reserved_22_23:2;
215 uint64_t rp1_sid:1;
216 uint64_t rp0_sid:2;
217 uint64_t rp1_pid:1;
218 uint64_t rp0_pid:2;
219 uint64_t reserved_15_15:1;
220 uint64_t prt_sel:3;
221 uint64_t lttr:4;
222 uint64_t prio:4;
223 uint64_t mbox:4;
224 } s;
225 struct cvmx_sriox_imsg_ctrl_s cn63xx;
226 struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
227 struct cvmx_sriox_imsg_ctrl_s cn66xx;
228};
229
230union cvmx_sriox_imsg_inst_hdrx {
231 uint64_t u64;
232 struct cvmx_sriox_imsg_inst_hdrx_s {
233 uint64_t r:1;
234 uint64_t reserved_58_62:5;
235 uint64_t pm:2;
236 uint64_t reserved_55_55:1;
237 uint64_t sl:7;
238 uint64_t reserved_46_47:2;
239 uint64_t nqos:1;
240 uint64_t ngrp:1;
241 uint64_t ntt:1;
242 uint64_t ntag:1;
243 uint64_t reserved_35_41:7;
244 uint64_t rs:1;
245 uint64_t tt:2;
246 uint64_t tag:32;
247 } s;
248 struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
249 struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
250 struct cvmx_sriox_imsg_inst_hdrx_s cn66xx;
251};
252
253union cvmx_sriox_imsg_qos_grpx {
254 uint64_t u64;
255 struct cvmx_sriox_imsg_qos_grpx_s {
256 uint64_t reserved_63_63:1;
257 uint64_t qos7:3;
258 uint64_t grp7:4;
259 uint64_t reserved_55_55:1;
260 uint64_t qos6:3;
261 uint64_t grp6:4;
262 uint64_t reserved_47_47:1;
263 uint64_t qos5:3;
264 uint64_t grp5:4;
265 uint64_t reserved_39_39:1;
266 uint64_t qos4:3;
267 uint64_t grp4:4;
268 uint64_t reserved_31_31:1;
269 uint64_t qos3:3;
270 uint64_t grp3:4;
271 uint64_t reserved_23_23:1;
272 uint64_t qos2:3;
273 uint64_t grp2:4;
274 uint64_t reserved_15_15:1;
275 uint64_t qos1:3;
276 uint64_t grp1:4;
277 uint64_t reserved_7_7:1;
278 uint64_t qos0:3;
279 uint64_t grp0:4;
280 } s;
281 struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
282 struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
283 struct cvmx_sriox_imsg_qos_grpx_s cn66xx;
284};
285
286union cvmx_sriox_imsg_statusx {
287 uint64_t u64;
288 struct cvmx_sriox_imsg_statusx_s {
289 uint64_t val1:1;
290 uint64_t err1:1;
291 uint64_t toe1:1;
292 uint64_t toc1:1;
293 uint64_t prt1:1;
294 uint64_t reserved_58_58:1;
295 uint64_t tt1:1;
296 uint64_t dis1:1;
297 uint64_t seg1:4;
298 uint64_t mbox1:2;
299 uint64_t lttr1:2;
300 uint64_t sid1:16;
301 uint64_t val0:1;
302 uint64_t err0:1;
303 uint64_t toe0:1;
304 uint64_t toc0:1;
305 uint64_t prt0:1;
306 uint64_t reserved_26_26:1;
307 uint64_t tt0:1;
308 uint64_t dis0:1;
309 uint64_t seg0:4;
310 uint64_t mbox0:2;
311 uint64_t lttr0:2;
312 uint64_t sid0:16;
313 } s;
314 struct cvmx_sriox_imsg_statusx_s cn63xx;
315 struct cvmx_sriox_imsg_statusx_s cn63xxp1;
316 struct cvmx_sriox_imsg_statusx_s cn66xx;
317};
318
319union cvmx_sriox_imsg_vport_thr {
320 uint64_t u64;
321 struct cvmx_sriox_imsg_vport_thr_s {
322 uint64_t reserved_54_63:10;
323 uint64_t max_tot:6;
324 uint64_t reserved_46_47:2;
325 uint64_t max_s1:6;
326 uint64_t reserved_38_39:2;
327 uint64_t max_s0:6;
328 uint64_t sp_vport:1;
329 uint64_t reserved_20_30:11;
330 uint64_t buf_thr:4;
331 uint64_t reserved_14_15:2;
332 uint64_t max_p1:6;
333 uint64_t reserved_6_7:2;
334 uint64_t max_p0:6;
335 } s;
336 struct cvmx_sriox_imsg_vport_thr_s cn63xx;
337 struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
338 struct cvmx_sriox_imsg_vport_thr_s cn66xx;
339};
340
341union cvmx_sriox_imsg_vport_thr2 {
342 uint64_t u64;
343 struct cvmx_sriox_imsg_vport_thr2_s {
344 uint64_t reserved_46_63:18;
345 uint64_t max_s3:6;
346 uint64_t reserved_38_39:2;
347 uint64_t max_s2:6;
348 uint64_t reserved_0_31:32;
349 } s;
350 struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
351};
352
353union cvmx_sriox_int2_enable {
354 uint64_t u64;
355 struct cvmx_sriox_int2_enable_s {
356 uint64_t reserved_1_63:63;
357 uint64_t pko_rst:1;
358 } s;
359 struct cvmx_sriox_int2_enable_s cn63xx;
360 struct cvmx_sriox_int2_enable_s cn66xx;
361};
362
363union cvmx_sriox_int2_reg {
364 uint64_t u64;
365 struct cvmx_sriox_int2_reg_s {
366 uint64_t reserved_32_63:32;
367 uint64_t int_sum:1;
368 uint64_t reserved_1_30:30;
369 uint64_t pko_rst:1;
370 } s;
371 struct cvmx_sriox_int2_reg_s cn63xx;
372 struct cvmx_sriox_int2_reg_s cn66xx;
373};
374
375union cvmx_sriox_int_enable {
376 uint64_t u64;
377 struct cvmx_sriox_int_enable_s {
378 uint64_t reserved_27_63:37;
379 uint64_t zero_pkt:1;
380 uint64_t ttl_tout:1;
381 uint64_t fail:1;
382 uint64_t degrade:1;
383 uint64_t mac_buf:1;
384 uint64_t f_error:1;
385 uint64_t rtry_err:1;
386 uint64_t pko_err:1;
387 uint64_t omsg_err:1;
388 uint64_t omsg1:1;
389 uint64_t omsg0:1;
390 uint64_t link_up:1;
391 uint64_t link_dwn:1;
392 uint64_t phy_erb:1;
393 uint64_t log_erb:1;
394 uint64_t soft_rx:1;
395 uint64_t soft_tx:1;
396 uint64_t mce_rx:1;
397 uint64_t mce_tx:1;
398 uint64_t wr_done:1;
399 uint64_t sli_err:1;
400 uint64_t deny_wr:1;
401 uint64_t bar_err:1;
402 uint64_t maint_op:1;
403 uint64_t rxbell:1;
404 uint64_t bell_err:1;
405 uint64_t txbell:1;
406 } s;
407 struct cvmx_sriox_int_enable_s cn63xx;
408 struct cvmx_sriox_int_enable_cn63xxp1 {
409 uint64_t reserved_22_63:42;
410 uint64_t f_error:1;
411 uint64_t rtry_err:1;
412 uint64_t pko_err:1;
413 uint64_t omsg_err:1;
414 uint64_t omsg1:1;
415 uint64_t omsg0:1;
416 uint64_t link_up:1;
417 uint64_t link_dwn:1;
418 uint64_t phy_erb:1;
419 uint64_t log_erb:1;
420 uint64_t soft_rx:1;
421 uint64_t soft_tx:1;
422 uint64_t mce_rx:1;
423 uint64_t mce_tx:1;
424 uint64_t wr_done:1;
425 uint64_t sli_err:1;
426 uint64_t deny_wr:1;
427 uint64_t bar_err:1;
428 uint64_t maint_op:1;
429 uint64_t rxbell:1;
430 uint64_t bell_err:1;
431 uint64_t txbell:1;
432 } cn63xxp1;
433 struct cvmx_sriox_int_enable_s cn66xx;
434};
435
436union cvmx_sriox_int_info0 {
437 uint64_t u64;
438 struct cvmx_sriox_int_info0_s {
439 uint64_t cmd:4;
440 uint64_t type:4;
441 uint64_t tag:8;
442 uint64_t reserved_42_47:6;
443 uint64_t length:10;
444 uint64_t status:3;
445 uint64_t reserved_16_28:13;
446 uint64_t be0:8;
447 uint64_t be1:8;
448 } s;
449 struct cvmx_sriox_int_info0_s cn63xx;
450 struct cvmx_sriox_int_info0_s cn63xxp1;
451 struct cvmx_sriox_int_info0_s cn66xx;
452};
453
454union cvmx_sriox_int_info1 {
455 uint64_t u64;
456 struct cvmx_sriox_int_info1_s {
457 uint64_t info1:64;
458 } s;
459 struct cvmx_sriox_int_info1_s cn63xx;
460 struct cvmx_sriox_int_info1_s cn63xxp1;
461 struct cvmx_sriox_int_info1_s cn66xx;
462};
463
464union cvmx_sriox_int_info2 {
465 uint64_t u64;
466 struct cvmx_sriox_int_info2_s {
467 uint64_t prio:2;
468 uint64_t tt:1;
469 uint64_t sis:1;
470 uint64_t ssize:4;
471 uint64_t did:16;
472 uint64_t xmbox:4;
473 uint64_t mbox:2;
474 uint64_t letter:2;
475 uint64_t rsrvd:30;
476 uint64_t lns:1;
477 uint64_t intr:1;
478 } s;
479 struct cvmx_sriox_int_info2_s cn63xx;
480 struct cvmx_sriox_int_info2_s cn63xxp1;
481 struct cvmx_sriox_int_info2_s cn66xx;
482};
483
484union cvmx_sriox_int_info3 {
485 uint64_t u64;
486 struct cvmx_sriox_int_info3_s {
487 uint64_t prio:2;
488 uint64_t tt:2;
489 uint64_t type:4;
490 uint64_t other:48;
491 uint64_t reserved_0_7:8;
492 } s;
493 struct cvmx_sriox_int_info3_s cn63xx;
494 struct cvmx_sriox_int_info3_s cn63xxp1;
495 struct cvmx_sriox_int_info3_s cn66xx;
496};
497
498union cvmx_sriox_int_reg {
499 uint64_t u64;
500 struct cvmx_sriox_int_reg_s {
501 uint64_t reserved_32_63:32;
502 uint64_t int2_sum:1;
503 uint64_t reserved_27_30:4;
504 uint64_t zero_pkt:1;
505 uint64_t ttl_tout:1;
506 uint64_t fail:1;
507 uint64_t degrad:1;
508 uint64_t mac_buf:1;
509 uint64_t f_error:1;
510 uint64_t rtry_err:1;
511 uint64_t pko_err:1;
512 uint64_t omsg_err:1;
513 uint64_t omsg1:1;
514 uint64_t omsg0:1;
515 uint64_t link_up:1;
516 uint64_t link_dwn:1;
517 uint64_t phy_erb:1;
518 uint64_t log_erb:1;
519 uint64_t soft_rx:1;
520 uint64_t soft_tx:1;
521 uint64_t mce_rx:1;
522 uint64_t mce_tx:1;
523 uint64_t wr_done:1;
524 uint64_t sli_err:1;
525 uint64_t deny_wr:1;
526 uint64_t bar_err:1;
527 uint64_t maint_op:1;
528 uint64_t rxbell:1;
529 uint64_t bell_err:1;
530 uint64_t txbell:1;
531 } s;
532 struct cvmx_sriox_int_reg_s cn63xx;
533 struct cvmx_sriox_int_reg_cn63xxp1 {
534 uint64_t reserved_22_63:42;
535 uint64_t f_error:1;
536 uint64_t rtry_err:1;
537 uint64_t pko_err:1;
538 uint64_t omsg_err:1;
539 uint64_t omsg1:1;
540 uint64_t omsg0:1;
541 uint64_t link_up:1;
542 uint64_t link_dwn:1;
543 uint64_t phy_erb:1;
544 uint64_t log_erb:1;
545 uint64_t soft_rx:1;
546 uint64_t soft_tx:1;
547 uint64_t mce_rx:1;
548 uint64_t mce_tx:1;
549 uint64_t wr_done:1;
550 uint64_t sli_err:1;
551 uint64_t deny_wr:1;
552 uint64_t bar_err:1;
553 uint64_t maint_op:1;
554 uint64_t rxbell:1;
555 uint64_t bell_err:1;
556 uint64_t txbell:1;
557 } cn63xxp1;
558 struct cvmx_sriox_int_reg_s cn66xx;
559};
560
561union cvmx_sriox_ip_feature {
562 uint64_t u64;
563 struct cvmx_sriox_ip_feature_s {
564 uint64_t ops:32;
565 uint64_t reserved_15_31:17;
566 uint64_t no_vmin:1;
567 uint64_t a66:1;
568 uint64_t a50:1;
569 uint64_t reserved_11_11:1;
570 uint64_t tx_flow:1;
571 uint64_t pt_width:2;
572 uint64_t tx_pol:4;
573 uint64_t rx_pol:4;
574 } s;
575 struct cvmx_sriox_ip_feature_cn63xx {
576 uint64_t ops:32;
577 uint64_t reserved_14_31:18;
578 uint64_t a66:1;
579 uint64_t a50:1;
580 uint64_t reserved_11_11:1;
581 uint64_t tx_flow:1;
582 uint64_t pt_width:2;
583 uint64_t tx_pol:4;
584 uint64_t rx_pol:4;
585 } cn63xx;
586 struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
587 struct cvmx_sriox_ip_feature_s cn66xx;
588};
589
590union cvmx_sriox_mac_buffers {
591 uint64_t u64;
592 struct cvmx_sriox_mac_buffers_s {
593 uint64_t reserved_56_63:8;
594 uint64_t tx_enb:8;
595 uint64_t reserved_44_47:4;
596 uint64_t tx_inuse:4;
597 uint64_t tx_stat:8;
598 uint64_t reserved_24_31:8;
599 uint64_t rx_enb:8;
600 uint64_t reserved_12_15:4;
601 uint64_t rx_inuse:4;
602 uint64_t rx_stat:8;
603 } s;
604 struct cvmx_sriox_mac_buffers_s cn63xx;
605 struct cvmx_sriox_mac_buffers_s cn66xx;
606};
607
608union cvmx_sriox_maint_op {
609 uint64_t u64;
610 struct cvmx_sriox_maint_op_s {
611 uint64_t wr_data:32;
612 uint64_t reserved_27_31:5;
613 uint64_t fail:1;
614 uint64_t pending:1;
615 uint64_t op:1;
616 uint64_t addr:24;
617 } s;
618 struct cvmx_sriox_maint_op_s cn63xx;
619 struct cvmx_sriox_maint_op_s cn63xxp1;
620 struct cvmx_sriox_maint_op_s cn66xx;
621};
622
623union cvmx_sriox_maint_rd_data {
624 uint64_t u64;
625 struct cvmx_sriox_maint_rd_data_s {
626 uint64_t reserved_33_63:31;
627 uint64_t valid:1;
628 uint64_t rd_data:32;
629 } s;
630 struct cvmx_sriox_maint_rd_data_s cn63xx;
631 struct cvmx_sriox_maint_rd_data_s cn63xxp1;
632 struct cvmx_sriox_maint_rd_data_s cn66xx;
633};
634
635union cvmx_sriox_mce_tx_ctl {
636 uint64_t u64;
637 struct cvmx_sriox_mce_tx_ctl_s {
638 uint64_t reserved_1_63:63;
639 uint64_t mce:1;
640 } s;
641 struct cvmx_sriox_mce_tx_ctl_s cn63xx;
642 struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
643 struct cvmx_sriox_mce_tx_ctl_s cn66xx;
644};
645
646union cvmx_sriox_mem_op_ctrl {
647 uint64_t u64;
648 struct cvmx_sriox_mem_op_ctrl_s {
649 uint64_t reserved_10_63:54;
650 uint64_t rr_ro:1;
651 uint64_t w_ro:1;
652 uint64_t reserved_6_7:2;
653 uint64_t rp1_sid:1;
654 uint64_t rp0_sid:2;
655 uint64_t rp1_pid:1;
656 uint64_t rp0_pid:2;
657 } s;
658 struct cvmx_sriox_mem_op_ctrl_s cn63xx;
659 struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
660 struct cvmx_sriox_mem_op_ctrl_s cn66xx;
661};
662
663union cvmx_sriox_omsg_ctrlx {
664 uint64_t u64;
665 struct cvmx_sriox_omsg_ctrlx_s {
666 uint64_t testmode:1;
667 uint64_t reserved_37_62:26;
668 uint64_t silo_max:5;
669 uint64_t rtry_thr:16;
670 uint64_t rtry_en:1;
671 uint64_t reserved_11_14:4;
672 uint64_t idm_tt:1;
673 uint64_t idm_sis:1;
674 uint64_t idm_did:1;
675 uint64_t lttr_sp:4;
676 uint64_t lttr_mp:4;
677 } s;
678 struct cvmx_sriox_omsg_ctrlx_s cn63xx;
679 struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
680 uint64_t testmode:1;
681 uint64_t reserved_32_62:31;
682 uint64_t rtry_thr:16;
683 uint64_t rtry_en:1;
684 uint64_t reserved_11_14:4;
685 uint64_t idm_tt:1;
686 uint64_t idm_sis:1;
687 uint64_t idm_did:1;
688 uint64_t lttr_sp:4;
689 uint64_t lttr_mp:4;
690 } cn63xxp1;
691 struct cvmx_sriox_omsg_ctrlx_s cn66xx;
692};
693
694union cvmx_sriox_omsg_done_countsx {
695 uint64_t u64;
696 struct cvmx_sriox_omsg_done_countsx_s {
697 uint64_t reserved_32_63:32;
698 uint64_t bad:16;
699 uint64_t good:16;
700 } s;
701 struct cvmx_sriox_omsg_done_countsx_s cn63xx;
702 struct cvmx_sriox_omsg_done_countsx_s cn66xx;
703};
704
705union cvmx_sriox_omsg_fmp_mrx {
706 uint64_t u64;
707 struct cvmx_sriox_omsg_fmp_mrx_s {
708 uint64_t reserved_15_63:49;
709 uint64_t ctlr_sp:1;
710 uint64_t ctlr_fmp:1;
711 uint64_t ctlr_nmp:1;
712 uint64_t id_sp:1;
713 uint64_t id_fmp:1;
714 uint64_t id_nmp:1;
715 uint64_t id_psd:1;
716 uint64_t mbox_sp:1;
717 uint64_t mbox_fmp:1;
718 uint64_t mbox_nmp:1;
719 uint64_t mbox_psd:1;
720 uint64_t all_sp:1;
721 uint64_t all_fmp:1;
722 uint64_t all_nmp:1;
723 uint64_t all_psd:1;
724 } s;
725 struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
726 struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
727 struct cvmx_sriox_omsg_fmp_mrx_s cn66xx;
728};
729
730union cvmx_sriox_omsg_nmp_mrx {
731 uint64_t u64;
732 struct cvmx_sriox_omsg_nmp_mrx_s {
733 uint64_t reserved_15_63:49;
734 uint64_t ctlr_sp:1;
735 uint64_t ctlr_fmp:1;
736 uint64_t ctlr_nmp:1;
737 uint64_t id_sp:1;
738 uint64_t id_fmp:1;
739 uint64_t id_nmp:1;
740 uint64_t reserved_8_8:1;
741 uint64_t mbox_sp:1;
742 uint64_t mbox_fmp:1;
743 uint64_t mbox_nmp:1;
744 uint64_t reserved_4_4:1;
745 uint64_t all_sp:1;
746 uint64_t all_fmp:1;
747 uint64_t all_nmp:1;
748 uint64_t reserved_0_0:1;
749 } s;
750 struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
751 struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
752 struct cvmx_sriox_omsg_nmp_mrx_s cn66xx;
753};
754
755union cvmx_sriox_omsg_portx {
756 uint64_t u64;
757 struct cvmx_sriox_omsg_portx_s {
758 uint64_t reserved_32_63:32;
759 uint64_t enable:1;
760 uint64_t reserved_3_30:28;
761 uint64_t port:3;
762 } s;
763 struct cvmx_sriox_omsg_portx_cn63xx {
764 uint64_t reserved_32_63:32;
765 uint64_t enable:1;
766 uint64_t reserved_2_30:29;
767 uint64_t port:2;
768 } cn63xx;
769 struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
770 struct cvmx_sriox_omsg_portx_s cn66xx;
771};
772
773union cvmx_sriox_omsg_silo_thr {
774 uint64_t u64;
775 struct cvmx_sriox_omsg_silo_thr_s {
776 uint64_t reserved_5_63:59;
777 uint64_t tot_silo:5;
778 } s;
779 struct cvmx_sriox_omsg_silo_thr_s cn63xx;
780 struct cvmx_sriox_omsg_silo_thr_s cn66xx;
781};
782
783union cvmx_sriox_omsg_sp_mrx {
784 uint64_t u64;
785 struct cvmx_sriox_omsg_sp_mrx_s {
786 uint64_t reserved_16_63:48;
787 uint64_t xmbox_sp:1;
788 uint64_t ctlr_sp:1;
789 uint64_t ctlr_fmp:1;
790 uint64_t ctlr_nmp:1;
791 uint64_t id_sp:1;
792 uint64_t id_fmp:1;
793 uint64_t id_nmp:1;
794 uint64_t id_psd:1;
795 uint64_t mbox_sp:1;
796 uint64_t mbox_fmp:1;
797 uint64_t mbox_nmp:1;
798 uint64_t mbox_psd:1;
799 uint64_t all_sp:1;
800 uint64_t all_fmp:1;
801 uint64_t all_nmp:1;
802 uint64_t all_psd:1;
803 } s;
804 struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
805 struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
806 struct cvmx_sriox_omsg_sp_mrx_s cn66xx;
807};
808
809union cvmx_sriox_priox_in_use {
810 uint64_t u64;
811 struct cvmx_sriox_priox_in_use_s {
812 uint64_t reserved_32_63:32;
813 uint64_t end_cnt:16;
814 uint64_t start_cnt:16;
815 } s;
816 struct cvmx_sriox_priox_in_use_s cn63xx;
817 struct cvmx_sriox_priox_in_use_s cn66xx;
818};
819
820union cvmx_sriox_rx_bell {
821 uint64_t u64;
822 struct cvmx_sriox_rx_bell_s {
823 uint64_t reserved_48_63:16;
824 uint64_t data:16;
825 uint64_t src_id:16;
826 uint64_t count:8;
827 uint64_t reserved_5_7:3;
828 uint64_t dest_id:1;
829 uint64_t id16:1;
830 uint64_t reserved_2_2:1;
831 uint64_t priority:2;
832 } s;
833 struct cvmx_sriox_rx_bell_s cn63xx;
834 struct cvmx_sriox_rx_bell_s cn63xxp1;
835 struct cvmx_sriox_rx_bell_s cn66xx;
836};
837
838union cvmx_sriox_rx_bell_seq {
839 uint64_t u64;
840 struct cvmx_sriox_rx_bell_seq_s {
841 uint64_t reserved_40_63:24;
842 uint64_t count:8;
843 uint64_t seq:32;
844 } s;
845 struct cvmx_sriox_rx_bell_seq_s cn63xx;
846 struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
847 struct cvmx_sriox_rx_bell_seq_s cn66xx;
848};
849
850union cvmx_sriox_rx_status {
851 uint64_t u64;
852 struct cvmx_sriox_rx_status_s {
853 uint64_t rtn_pr3:8;
854 uint64_t rtn_pr2:8;
855 uint64_t rtn_pr1:8;
856 uint64_t reserved_28_39:12;
857 uint64_t mbox:4;
858 uint64_t comp:8;
859 uint64_t reserved_13_15:3;
860 uint64_t n_post:5;
861 uint64_t post:8;
862 } s;
863 struct cvmx_sriox_rx_status_s cn63xx;
864 struct cvmx_sriox_rx_status_s cn63xxp1;
865 struct cvmx_sriox_rx_status_s cn66xx;
866};
867
868union cvmx_sriox_s2m_typex {
869 uint64_t u64;
870 struct cvmx_sriox_s2m_typex_s {
871 uint64_t reserved_19_63:45;
872 uint64_t wr_op:3;
873 uint64_t reserved_15_15:1;
874 uint64_t rd_op:3;
875 uint64_t wr_prior:2;
876 uint64_t rd_prior:2;
877 uint64_t reserved_6_7:2;
878 uint64_t src_id:1;
879 uint64_t id16:1;
880 uint64_t reserved_2_3:2;
881 uint64_t iaow_sel:2;
882 } s;
883 struct cvmx_sriox_s2m_typex_s cn63xx;
884 struct cvmx_sriox_s2m_typex_s cn63xxp1;
885 struct cvmx_sriox_s2m_typex_s cn66xx;
886};
887
888union cvmx_sriox_seq {
889 uint64_t u64;
890 struct cvmx_sriox_seq_s {
891 uint64_t reserved_32_63:32;
892 uint64_t seq:32;
893 } s;
894 struct cvmx_sriox_seq_s cn63xx;
895 struct cvmx_sriox_seq_s cn63xxp1;
896 struct cvmx_sriox_seq_s cn66xx;
897};
898
899union cvmx_sriox_status_reg {
900 uint64_t u64;
901 struct cvmx_sriox_status_reg_s {
902 uint64_t reserved_2_63:62;
903 uint64_t access:1;
904 uint64_t srio:1;
905 } s;
906 struct cvmx_sriox_status_reg_s cn63xx;
907 struct cvmx_sriox_status_reg_s cn63xxp1;
908 struct cvmx_sriox_status_reg_s cn66xx;
909};
910
911union cvmx_sriox_tag_ctrl {
912 uint64_t u64;
913 struct cvmx_sriox_tag_ctrl_s {
914 uint64_t reserved_17_63:47;
915 uint64_t o_clr:1;
916 uint64_t reserved_13_15:3;
917 uint64_t otag:5;
918 uint64_t reserved_5_7:3;
919 uint64_t itag:5;
920 } s;
921 struct cvmx_sriox_tag_ctrl_s cn63xx;
922 struct cvmx_sriox_tag_ctrl_s cn63xxp1;
923 struct cvmx_sriox_tag_ctrl_s cn66xx;
924};
925
926union cvmx_sriox_tlp_credits {
927 uint64_t u64;
928 struct cvmx_sriox_tlp_credits_s {
929 uint64_t reserved_28_63:36;
930 uint64_t mbox:4;
931 uint64_t comp:8;
932 uint64_t reserved_13_15:3;
933 uint64_t n_post:5;
934 uint64_t post:8;
935 } s;
936 struct cvmx_sriox_tlp_credits_s cn63xx;
937 struct cvmx_sriox_tlp_credits_s cn63xxp1;
938 struct cvmx_sriox_tlp_credits_s cn66xx;
939};
940
941union cvmx_sriox_tx_bell {
942 uint64_t u64;
943 struct cvmx_sriox_tx_bell_s {
944 uint64_t reserved_48_63:16;
945 uint64_t data:16;
946 uint64_t dest_id:16;
947 uint64_t reserved_9_15:7;
948 uint64_t pending:1;
949 uint64_t reserved_5_7:3;
950 uint64_t src_id:1;
951 uint64_t id16:1;
952 uint64_t reserved_2_2:1;
953 uint64_t priority:2;
954 } s;
955 struct cvmx_sriox_tx_bell_s cn63xx;
956 struct cvmx_sriox_tx_bell_s cn63xxp1;
957 struct cvmx_sriox_tx_bell_s cn66xx;
958};
959
960union cvmx_sriox_tx_bell_info {
961 uint64_t u64;
962 struct cvmx_sriox_tx_bell_info_s {
963 uint64_t reserved_48_63:16;
964 uint64_t data:16;
965 uint64_t dest_id:16;
966 uint64_t reserved_8_15:8;
967 uint64_t timeout:1;
968 uint64_t error:1;
969 uint64_t retry:1;
970 uint64_t src_id:1;
971 uint64_t id16:1;
972 uint64_t reserved_2_2:1;
973 uint64_t priority:2;
974 } s;
975 struct cvmx_sriox_tx_bell_info_s cn63xx;
976 struct cvmx_sriox_tx_bell_info_s cn63xxp1;
977 struct cvmx_sriox_tx_bell_info_s cn66xx;
978};
979
980union cvmx_sriox_tx_ctrl {
981 uint64_t u64;
982 struct cvmx_sriox_tx_ctrl_s {
983 uint64_t reserved_53_63:11;
984 uint64_t tag_th2:5;
985 uint64_t reserved_45_47:3;
986 uint64_t tag_th1:5;
987 uint64_t reserved_37_39:3;
988 uint64_t tag_th0:5;
989 uint64_t reserved_20_31:12;
990 uint64_t tx_th2:4;
991 uint64_t reserved_12_15:4;
992 uint64_t tx_th1:4;
993 uint64_t reserved_4_7:4;
994 uint64_t tx_th0:4;
995 } s;
996 struct cvmx_sriox_tx_ctrl_s cn63xx;
997 struct cvmx_sriox_tx_ctrl_s cn63xxp1;
998 struct cvmx_sriox_tx_ctrl_s cn66xx;
999};
1000
1001union cvmx_sriox_tx_emphasis {
1002 uint64_t u64;
1003 struct cvmx_sriox_tx_emphasis_s {
1004 uint64_t reserved_4_63:60;
1005 uint64_t emph:4;
1006 } s;
1007 struct cvmx_sriox_tx_emphasis_s cn63xx;
1008 struct cvmx_sriox_tx_emphasis_s cn66xx;
1009};
1010
1011union cvmx_sriox_tx_status {
1012 uint64_t u64;
1013 struct cvmx_sriox_tx_status_s {
1014 uint64_t reserved_32_63:32;
1015 uint64_t s2m_pr3:8;
1016 uint64_t s2m_pr2:8;
1017 uint64_t s2m_pr1:8;
1018 uint64_t s2m_pr0:8;
1019 } s;
1020 struct cvmx_sriox_tx_status_s cn63xx;
1021 struct cvmx_sriox_tx_status_s cn63xxp1;
1022 struct cvmx_sriox_tx_status_s cn66xx;
1023};
1024
1025union cvmx_sriox_wr_done_counts {
1026 uint64_t u64;
1027 struct cvmx_sriox_wr_done_counts_s {
1028 uint64_t reserved_32_63:32;
1029 uint64_t bad:16;
1030 uint64_t good:16;
1031 } s;
1032 struct cvmx_sriox_wr_done_counts_s cn63xx;
1033 struct cvmx_sriox_wr_done_counts_s cn66xx;
1034};
1035
1036#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-srxx-defs.h b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
new file mode 100644
index 000000000000..d82b366c279f
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-srxx-defs.h
@@ -0,0 +1,126 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SRXX_DEFS_H__
29#define __CVMX_SRXX_DEFS_H__
30
31#define CVMX_SRXX_COM_CTL(block_id) \
32 CVMX_ADD_IO_SEG(0x0001180090000200ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_SRXX_IGN_RX_FULL(block_id) \
34 CVMX_ADD_IO_SEG(0x0001180090000218ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_SRXX_SPI4_CALX(offset, block_id) \
36 CVMX_ADD_IO_SEG(0x0001180090000000ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_SRXX_SPI4_STAT(block_id) \
38 CVMX_ADD_IO_SEG(0x0001180090000208ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_SRXX_SW_TICK_CTL(block_id) \
40 CVMX_ADD_IO_SEG(0x0001180090000220ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_SRXX_SW_TICK_DAT(block_id) \
42 CVMX_ADD_IO_SEG(0x0001180090000228ull + (((block_id) & 1) * 0x8000000ull))
43
44union cvmx_srxx_com_ctl {
45 uint64_t u64;
46 struct cvmx_srxx_com_ctl_s {
47 uint64_t reserved_8_63:56;
48 uint64_t prts:4;
49 uint64_t st_en:1;
50 uint64_t reserved_1_2:2;
51 uint64_t inf_en:1;
52 } s;
53 struct cvmx_srxx_com_ctl_s cn38xx;
54 struct cvmx_srxx_com_ctl_s cn38xxp2;
55 struct cvmx_srxx_com_ctl_s cn58xx;
56 struct cvmx_srxx_com_ctl_s cn58xxp1;
57};
58
59union cvmx_srxx_ign_rx_full {
60 uint64_t u64;
61 struct cvmx_srxx_ign_rx_full_s {
62 uint64_t reserved_16_63:48;
63 uint64_t ignore:16;
64 } s;
65 struct cvmx_srxx_ign_rx_full_s cn38xx;
66 struct cvmx_srxx_ign_rx_full_s cn38xxp2;
67 struct cvmx_srxx_ign_rx_full_s cn58xx;
68 struct cvmx_srxx_ign_rx_full_s cn58xxp1;
69};
70
71union cvmx_srxx_spi4_calx {
72 uint64_t u64;
73 struct cvmx_srxx_spi4_calx_s {
74 uint64_t reserved_17_63:47;
75 uint64_t oddpar:1;
76 uint64_t prt3:4;
77 uint64_t prt2:4;
78 uint64_t prt1:4;
79 uint64_t prt0:4;
80 } s;
81 struct cvmx_srxx_spi4_calx_s cn38xx;
82 struct cvmx_srxx_spi4_calx_s cn38xxp2;
83 struct cvmx_srxx_spi4_calx_s cn58xx;
84 struct cvmx_srxx_spi4_calx_s cn58xxp1;
85};
86
87union cvmx_srxx_spi4_stat {
88 uint64_t u64;
89 struct cvmx_srxx_spi4_stat_s {
90 uint64_t reserved_16_63:48;
91 uint64_t m:8;
92 uint64_t reserved_7_7:1;
93 uint64_t len:7;
94 } s;
95 struct cvmx_srxx_spi4_stat_s cn38xx;
96 struct cvmx_srxx_spi4_stat_s cn38xxp2;
97 struct cvmx_srxx_spi4_stat_s cn58xx;
98 struct cvmx_srxx_spi4_stat_s cn58xxp1;
99};
100
101union cvmx_srxx_sw_tick_ctl {
102 uint64_t u64;
103 struct cvmx_srxx_sw_tick_ctl_s {
104 uint64_t reserved_14_63:50;
105 uint64_t eop:1;
106 uint64_t sop:1;
107 uint64_t mod:4;
108 uint64_t opc:4;
109 uint64_t adr:4;
110 } s;
111 struct cvmx_srxx_sw_tick_ctl_s cn38xx;
112 struct cvmx_srxx_sw_tick_ctl_s cn58xx;
113 struct cvmx_srxx_sw_tick_ctl_s cn58xxp1;
114};
115
116union cvmx_srxx_sw_tick_dat {
117 uint64_t u64;
118 struct cvmx_srxx_sw_tick_dat_s {
119 uint64_t dat:64;
120 } s;
121 struct cvmx_srxx_sw_tick_dat_s cn38xx;
122 struct cvmx_srxx_sw_tick_dat_s cn58xx;
123 struct cvmx_srxx_sw_tick_dat_s cn58xxp1;
124};
125
126#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-stxx-defs.h b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
new file mode 100644
index 000000000000..4f209b62cae1
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-stxx-defs.h
@@ -0,0 +1,292 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_STXX_DEFS_H__
29#define __CVMX_STXX_DEFS_H__
30
31#define CVMX_STXX_ARB_CTL(block_id) \
32 CVMX_ADD_IO_SEG(0x0001180090000608ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_STXX_BCKPRS_CNT(block_id) \
34 CVMX_ADD_IO_SEG(0x0001180090000688ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_STXX_COM_CTL(block_id) \
36 CVMX_ADD_IO_SEG(0x0001180090000600ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_STXX_DIP_CNT(block_id) \
38 CVMX_ADD_IO_SEG(0x0001180090000690ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_STXX_IGN_CAL(block_id) \
40 CVMX_ADD_IO_SEG(0x0001180090000610ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_STXX_INT_MSK(block_id) \
42 CVMX_ADD_IO_SEG(0x00011800900006A0ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_STXX_INT_REG(block_id) \
44 CVMX_ADD_IO_SEG(0x0001180090000698ull + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_STXX_INT_SYNC(block_id) \
46 CVMX_ADD_IO_SEG(0x00011800900006A8ull + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_STXX_MIN_BST(block_id) \
48 CVMX_ADD_IO_SEG(0x0001180090000618ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_STXX_SPI4_CALX(offset, block_id) \
50 CVMX_ADD_IO_SEG(0x0001180090000400ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_STXX_SPI4_DAT(block_id) \
52 CVMX_ADD_IO_SEG(0x0001180090000628ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_STXX_SPI4_STAT(block_id) \
54 CVMX_ADD_IO_SEG(0x0001180090000630ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_STXX_STAT_BYTES_HI(block_id) \
56 CVMX_ADD_IO_SEG(0x0001180090000648ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_STXX_STAT_BYTES_LO(block_id) \
58 CVMX_ADD_IO_SEG(0x0001180090000680ull + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_STXX_STAT_CTL(block_id) \
60 CVMX_ADD_IO_SEG(0x0001180090000638ull + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_STXX_STAT_PKT_XMT(block_id) \
62 CVMX_ADD_IO_SEG(0x0001180090000640ull + (((block_id) & 1) * 0x8000000ull))
63
64union cvmx_stxx_arb_ctl {
65 uint64_t u64;
66 struct cvmx_stxx_arb_ctl_s {
67 uint64_t reserved_6_63:58;
68 uint64_t mintrn:1;
69 uint64_t reserved_4_4:1;
70 uint64_t igntpa:1;
71 uint64_t reserved_0_2:3;
72 } s;
73 struct cvmx_stxx_arb_ctl_s cn38xx;
74 struct cvmx_stxx_arb_ctl_s cn38xxp2;
75 struct cvmx_stxx_arb_ctl_s cn58xx;
76 struct cvmx_stxx_arb_ctl_s cn58xxp1;
77};
78
79union cvmx_stxx_bckprs_cnt {
80 uint64_t u64;
81 struct cvmx_stxx_bckprs_cnt_s {
82 uint64_t reserved_32_63:32;
83 uint64_t cnt:32;
84 } s;
85 struct cvmx_stxx_bckprs_cnt_s cn38xx;
86 struct cvmx_stxx_bckprs_cnt_s cn38xxp2;
87 struct cvmx_stxx_bckprs_cnt_s cn58xx;
88 struct cvmx_stxx_bckprs_cnt_s cn58xxp1;
89};
90
91union cvmx_stxx_com_ctl {
92 uint64_t u64;
93 struct cvmx_stxx_com_ctl_s {
94 uint64_t reserved_4_63:60;
95 uint64_t st_en:1;
96 uint64_t reserved_1_2:2;
97 uint64_t inf_en:1;
98 } s;
99 struct cvmx_stxx_com_ctl_s cn38xx;
100 struct cvmx_stxx_com_ctl_s cn38xxp2;
101 struct cvmx_stxx_com_ctl_s cn58xx;
102 struct cvmx_stxx_com_ctl_s cn58xxp1;
103};
104
105union cvmx_stxx_dip_cnt {
106 uint64_t u64;
107 struct cvmx_stxx_dip_cnt_s {
108 uint64_t reserved_8_63:56;
109 uint64_t frmmax:4;
110 uint64_t dipmax:4;
111 } s;
112 struct cvmx_stxx_dip_cnt_s cn38xx;
113 struct cvmx_stxx_dip_cnt_s cn38xxp2;
114 struct cvmx_stxx_dip_cnt_s cn58xx;
115 struct cvmx_stxx_dip_cnt_s cn58xxp1;
116};
117
118union cvmx_stxx_ign_cal {
119 uint64_t u64;
120 struct cvmx_stxx_ign_cal_s {
121 uint64_t reserved_16_63:48;
122 uint64_t igntpa:16;
123 } s;
124 struct cvmx_stxx_ign_cal_s cn38xx;
125 struct cvmx_stxx_ign_cal_s cn38xxp2;
126 struct cvmx_stxx_ign_cal_s cn58xx;
127 struct cvmx_stxx_ign_cal_s cn58xxp1;
128};
129
130union cvmx_stxx_int_msk {
131 uint64_t u64;
132 struct cvmx_stxx_int_msk_s {
133 uint64_t reserved_8_63:56;
134 uint64_t frmerr:1;
135 uint64_t unxfrm:1;
136 uint64_t nosync:1;
137 uint64_t diperr:1;
138 uint64_t datovr:1;
139 uint64_t ovrbst:1;
140 uint64_t calpar1:1;
141 uint64_t calpar0:1;
142 } s;
143 struct cvmx_stxx_int_msk_s cn38xx;
144 struct cvmx_stxx_int_msk_s cn38xxp2;
145 struct cvmx_stxx_int_msk_s cn58xx;
146 struct cvmx_stxx_int_msk_s cn58xxp1;
147};
148
149union cvmx_stxx_int_reg {
150 uint64_t u64;
151 struct cvmx_stxx_int_reg_s {
152 uint64_t reserved_9_63:55;
153 uint64_t syncerr:1;
154 uint64_t frmerr:1;
155 uint64_t unxfrm:1;
156 uint64_t nosync:1;
157 uint64_t diperr:1;
158 uint64_t datovr:1;
159 uint64_t ovrbst:1;
160 uint64_t calpar1:1;
161 uint64_t calpar0:1;
162 } s;
163 struct cvmx_stxx_int_reg_s cn38xx;
164 struct cvmx_stxx_int_reg_s cn38xxp2;
165 struct cvmx_stxx_int_reg_s cn58xx;
166 struct cvmx_stxx_int_reg_s cn58xxp1;
167};
168
169union cvmx_stxx_int_sync {
170 uint64_t u64;
171 struct cvmx_stxx_int_sync_s {
172 uint64_t reserved_8_63:56;
173 uint64_t frmerr:1;
174 uint64_t unxfrm:1;
175 uint64_t nosync:1;
176 uint64_t diperr:1;
177 uint64_t datovr:1;
178 uint64_t ovrbst:1;
179 uint64_t calpar1:1;
180 uint64_t calpar0:1;
181 } s;
182 struct cvmx_stxx_int_sync_s cn38xx;
183 struct cvmx_stxx_int_sync_s cn38xxp2;
184 struct cvmx_stxx_int_sync_s cn58xx;
185 struct cvmx_stxx_int_sync_s cn58xxp1;
186};
187
188union cvmx_stxx_min_bst {
189 uint64_t u64;
190 struct cvmx_stxx_min_bst_s {
191 uint64_t reserved_9_63:55;
192 uint64_t minb:9;
193 } s;
194 struct cvmx_stxx_min_bst_s cn38xx;
195 struct cvmx_stxx_min_bst_s cn38xxp2;
196 struct cvmx_stxx_min_bst_s cn58xx;
197 struct cvmx_stxx_min_bst_s cn58xxp1;
198};
199
200union cvmx_stxx_spi4_calx {
201 uint64_t u64;
202 struct cvmx_stxx_spi4_calx_s {
203 uint64_t reserved_17_63:47;
204 uint64_t oddpar:1;
205 uint64_t prt3:4;
206 uint64_t prt2:4;
207 uint64_t prt1:4;
208 uint64_t prt0:4;
209 } s;
210 struct cvmx_stxx_spi4_calx_s cn38xx;
211 struct cvmx_stxx_spi4_calx_s cn38xxp2;
212 struct cvmx_stxx_spi4_calx_s cn58xx;
213 struct cvmx_stxx_spi4_calx_s cn58xxp1;
214};
215
216union cvmx_stxx_spi4_dat {
217 uint64_t u64;
218 struct cvmx_stxx_spi4_dat_s {
219 uint64_t reserved_32_63:32;
220 uint64_t alpha:16;
221 uint64_t max_t:16;
222 } s;
223 struct cvmx_stxx_spi4_dat_s cn38xx;
224 struct cvmx_stxx_spi4_dat_s cn38xxp2;
225 struct cvmx_stxx_spi4_dat_s cn58xx;
226 struct cvmx_stxx_spi4_dat_s cn58xxp1;
227};
228
229union cvmx_stxx_spi4_stat {
230 uint64_t u64;
231 struct cvmx_stxx_spi4_stat_s {
232 uint64_t reserved_16_63:48;
233 uint64_t m:8;
234 uint64_t reserved_7_7:1;
235 uint64_t len:7;
236 } s;
237 struct cvmx_stxx_spi4_stat_s cn38xx;
238 struct cvmx_stxx_spi4_stat_s cn38xxp2;
239 struct cvmx_stxx_spi4_stat_s cn58xx;
240 struct cvmx_stxx_spi4_stat_s cn58xxp1;
241};
242
243union cvmx_stxx_stat_bytes_hi {
244 uint64_t u64;
245 struct cvmx_stxx_stat_bytes_hi_s {
246 uint64_t reserved_32_63:32;
247 uint64_t cnt:32;
248 } s;
249 struct cvmx_stxx_stat_bytes_hi_s cn38xx;
250 struct cvmx_stxx_stat_bytes_hi_s cn38xxp2;
251 struct cvmx_stxx_stat_bytes_hi_s cn58xx;
252 struct cvmx_stxx_stat_bytes_hi_s cn58xxp1;
253};
254
255union cvmx_stxx_stat_bytes_lo {
256 uint64_t u64;
257 struct cvmx_stxx_stat_bytes_lo_s {
258 uint64_t reserved_32_63:32;
259 uint64_t cnt:32;
260 } s;
261 struct cvmx_stxx_stat_bytes_lo_s cn38xx;
262 struct cvmx_stxx_stat_bytes_lo_s cn38xxp2;
263 struct cvmx_stxx_stat_bytes_lo_s cn58xx;
264 struct cvmx_stxx_stat_bytes_lo_s cn58xxp1;
265};
266
267union cvmx_stxx_stat_ctl {
268 uint64_t u64;
269 struct cvmx_stxx_stat_ctl_s {
270 uint64_t reserved_5_63:59;
271 uint64_t clr:1;
272 uint64_t bckprs:4;
273 } s;
274 struct cvmx_stxx_stat_ctl_s cn38xx;
275 struct cvmx_stxx_stat_ctl_s cn38xxp2;
276 struct cvmx_stxx_stat_ctl_s cn58xx;
277 struct cvmx_stxx_stat_ctl_s cn58xxp1;
278};
279
280union cvmx_stxx_stat_pkt_xmt {
281 uint64_t u64;
282 struct cvmx_stxx_stat_pkt_xmt_s {
283 uint64_t reserved_32_63:32;
284 uint64_t cnt:32;
285 } s;
286 struct cvmx_stxx_stat_pkt_xmt_s cn38xx;
287 struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2;
288 struct cvmx_stxx_stat_pkt_xmt_s cn58xx;
289 struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1;
290};
291
292#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h
new file mode 100644
index 000000000000..653610953d28
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-wqe.h
@@ -0,0 +1,397 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * This header file defines the work queue entry (wqe) data structure.
31 * Since this is a commonly used structure that depends on structures
32 * from several hardware blocks, those definitions have been placed
33 * in this file to create a single point of definition of the wqe
34 * format.
35 * Data structures are still named according to the block that they
36 * relate to.
37 *
38 */
39
40#ifndef __CVMX_WQE_H__
41#define __CVMX_WQE_H__
42
43#include "cvmx-packet.h"
44
45
46#define OCT_TAG_TYPE_STRING(x) \
47 (((x) == CVMX_POW_TAG_TYPE_ORDERED) ? "ORDERED" : \
48 (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ? "ATOMIC" : \
49 (((x) == CVMX_POW_TAG_TYPE_NULL) ? "NULL" : \
50 "NULL_NULL")))
51
52/**
53 * HW decode / err_code in work queue entry
54 */
55typedef union {
56 uint64_t u64;
57
58 /* Use this struct if the hardware determines that the packet is IP */
59 struct {
60 /* HW sets this to the number of buffers used by this packet */
61 uint64_t bufs:8;
62 /* HW sets to the number of L2 bytes prior to the IP */
63 uint64_t ip_offset:8;
64 /* set to 1 if we found DSA/VLAN in the L2 */
65 uint64_t vlan_valid:1;
66 /* Set to 1 if the DSA/VLAN tag is stacked */
67 uint64_t vlan_stacked:1;
68 uint64_t unassigned:1;
69 /* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
70 uint64_t vlan_cfi:1;
71 /* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
72 uint64_t vlan_id:12;
73 /* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
74 uint64_t pr:4;
75 uint64_t unassigned2:8;
76 /* the packet needs to be decompressed */
77 uint64_t dec_ipcomp:1;
78 /* the packet is either TCP or UDP */
79 uint64_t tcp_or_udp:1;
80 /* the packet needs to be decrypted (ESP or AH) */
81 uint64_t dec_ipsec:1;
82 /* the packet is IPv6 */
83 uint64_t is_v6:1;
84
85 /*
86 * (rcv_error, not_IP, IP_exc, is_frag, L4_error,
87 * software, etc.).
88 */
89
90 /*
91 * reserved for software use, hardware will clear on
92 * packet creation.
93 */
94 uint64_t software:1;
95 /* exceptional conditions below */
96 /* the receive interface hardware detected an L4 error
97 * (only applies if !is_frag) (only applies if
98 * !rcv_error && !not_IP && !IP_exc && !is_frag)
99 * failure indicated in err_code below, decode:
100 *
101 * - 1 = Malformed L4
102 * - 2 = L4 Checksum Error: the L4 checksum value is
103 * - 3 = UDP Length Error: The UDP length field would
104 * make the UDP data longer than what remains in
105 * the IP packet (as defined by the IP header
106 * length field).
107 * - 4 = Bad L4 Port: either the source or destination
108 * TCP/UDP port is 0.
109 * - 8 = TCP FIN Only: the packet is TCP and only the
110 * FIN flag set.
111 * - 9 = TCP No Flags: the packet is TCP and no flags
112 * are set.
113 * - 10 = TCP FIN RST: the packet is TCP and both FIN
114 * and RST are set.
115 * - 11 = TCP SYN URG: the packet is TCP and both SYN
116 * and URG are set.
117 * - 12 = TCP SYN RST: the packet is TCP and both SYN
118 * and RST are set.
119 * - 13 = TCP SYN FIN: the packet is TCP and both SYN
120 * and FIN are set.
121 */
122 uint64_t L4_error:1;
123 /* set if the packet is a fragment */
124 uint64_t is_frag:1;
125 /* the receive interface hardware detected an IP error
126 * / exception (only applies if !rcv_error && !not_IP)
127 * failure indicated in err_code below, decode:
128 *
129 * - 1 = Not IP: the IP version field is neither 4 nor
130 * 6.
131 * - 2 = IPv4 Header Checksum Error: the IPv4 header
132 * has a checksum violation.
133 * - 3 = IP Malformed Header: the packet is not long
134 * enough to contain the IP header.
135 * - 4 = IP Malformed: the packet is not long enough
136 * to contain the bytes indicated by the IP
137 * header. Pad is allowed.
138 * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
139 * Hop Count field are zero.
140 * - 6 = IP Options
141 */
142 uint64_t IP_exc:1;
143 /*
144 * Set if the hardware determined that the packet is a
145 * broadcast.
146 */
147 uint64_t is_bcast:1;
148 /*
149 * St if the hardware determined that the packet is a
150 * multi-cast.
151 */
152 uint64_t is_mcast:1;
153 /*
154 * Set if the packet may not be IP (must be zero in
155 * this case).
156 */
157 uint64_t not_IP:1;
158 /*
159 * The receive interface hardware detected a receive
160 * error (must be zero in this case).
161 */
162 uint64_t rcv_error:1;
163 /* lower err_code = first-level descriptor of the
164 * work */
165 /* zero for packet submitted by hardware that isn't on
166 * the slow path */
167 /* type is cvmx_pip_err_t */
168 uint64_t err_code:8;
169 } s;
170
171 /* use this to get at the 16 vlan bits */
172 struct {
173 uint64_t unused1:16;
174 uint64_t vlan:16;
175 uint64_t unused2:32;
176 } svlan;
177
178 /*
179 * use this struct if the hardware could not determine that
180 * the packet is ip.
181 */
182 struct {
183 /*
184 * HW sets this to the number of buffers used by this
185 * packet.
186 */
187 uint64_t bufs:8;
188 uint64_t unused:8;
189 /* set to 1 if we found DSA/VLAN in the L2 */
190 uint64_t vlan_valid:1;
191 /* Set to 1 if the DSA/VLAN tag is stacked */
192 uint64_t vlan_stacked:1;
193 uint64_t unassigned:1;
194 /*
195 * HW sets to the DSA/VLAN CFI flag (valid when
196 * vlan_valid)
197 */
198 uint64_t vlan_cfi:1;
199 /*
200 * HW sets to the DSA/VLAN_ID field (valid when
201 * vlan_valid).
202 */
203 uint64_t vlan_id:12;
204 /*
205 * Ring Identifier (if PCIe). Requires
206 * PIP_GBL_CTL[RING_EN]=1
207 */
208 uint64_t pr:4;
209 uint64_t unassigned2:12;
210 /*
211 * reserved for software use, hardware will clear on
212 * packet creation.
213 */
214 uint64_t software:1;
215 uint64_t unassigned3:1;
216 /*
217 * set if the hardware determined that the packet is
218 * rarp.
219 */
220 uint64_t is_rarp:1;
221 /*
222 * set if the hardware determined that the packet is
223 * arp
224 */
225 uint64_t is_arp:1;
226 /*
227 * set if the hardware determined that the packet is a
228 * broadcast.
229 */
230 uint64_t is_bcast:1;
231 /*
232 * set if the hardware determined that the packet is a
233 * multi-cast
234 */
235 uint64_t is_mcast:1;
236 /*
237 * set if the packet may not be IP (must be one in
238 * this case)
239 */
240 uint64_t not_IP:1;
241 /* The receive interface hardware detected a receive
242 * error. Failure indicated in err_code below,
243 * decode:
244 *
245 * - 1 = partial error: a packet was partially
246 * received, but internal buffering / bandwidth
247 * was not adequate to receive the entire
248 * packet.
249 * - 2 = jabber error: the RGMII packet was too large
250 * and is truncated.
251 * - 3 = overrun error: the RGMII packet is longer
252 * than allowed and had an FCS error.
253 * - 4 = oversize error: the RGMII packet is longer
254 * than allowed.
255 * - 5 = alignment error: the RGMII packet is not an
256 * integer number of bytes
257 * and had an FCS error (100M and 10M only).
258 * - 6 = fragment error: the RGMII packet is shorter
259 * than allowed and had an FCS error.
260 * - 7 = GMX FCS error: the RGMII packet had an FCS
261 * error.
262 * - 8 = undersize error: the RGMII packet is shorter
263 * than allowed.
264 * - 9 = extend error: the RGMII packet had an extend
265 * error.
266 * - 10 = length mismatch error: the RGMII packet had
267 * a length that did not match the length field
268 * in the L2 HDR.
269 * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
270 * packet had one or more data reception errors
271 * (RXERR) or the SPI4 packet had one or more
272 * DIP4 errors.
273 * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
274 * packet was not large enough to cover the
275 * skipped bytes or the SPI4 packet was
276 * terminated with an About EOPS.
277 * - 13 = RGMII nibble error/SPI4 Port NXA Error: the
278 * RGMII packet had a studder error (data not
279 * repeated - 10/100M only) or the SPI4 packet
280 * was sent to an NXA.
281 * - 16 = FCS error: a SPI4.2 packet had an FCS error.
282 * - 17 = Skip error: a packet was not large enough to
283 * cover the skipped bytes.
284 * - 18 = L2 header malformed: the packet is not long
285 * enough to contain the L2.
286 */
287
288 uint64_t rcv_error:1;
289 /*
290 * lower err_code = first-level descriptor of the
291 * work
292 */
293 /*
294 * zero for packet submitted by hardware that isn't on
295 * the slow path
296 */
297 /* type is cvmx_pip_err_t (union, so can't use directly */
298 uint64_t err_code:8;
299 } snoip;
300
301} cvmx_pip_wqe_word2;
302
303/**
304 * Work queue entry format
305 *
306 * must be 8-byte aligned
307 */
308typedef struct {
309
310 /*****************************************************************
311 * WORD 0
312 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
313 */
314
315 /**
316 * raw chksum result generated by the HW
317 */
318 uint16_t hw_chksum;
319 /**
320 * Field unused by hardware - available for software
321 */
322 uint8_t unused;
323 /**
324 * Next pointer used by hardware for list maintenance.
325 * May be written/read by HW before the work queue
326 * entry is scheduled to a PP
327 * (Only 36 bits used in Octeon 1)
328 */
329 uint64_t next_ptr:40;
330
331 /*****************************************************************
332 * WORD 1
333 * HW WRITE: the following 64 bits are filled by HW when a packet arrives
334 */
335
336 /**
337 * HW sets to the total number of bytes in the packet
338 */
339 uint64_t len:16;
340 /**
341 * HW sets this to input physical port
342 */
343 uint64_t ipprt:6;
344
345 /**
346 * HW sets this to what it thought the priority of the input packet was
347 */
348 uint64_t qos:3;
349
350 /**
351 * the group that the work queue entry will be scheduled to
352 */
353 uint64_t grp:4;
354 /**
355 * the type of the tag (ORDERED, ATOMIC, NULL)
356 */
357 uint64_t tag_type:3;
358 /**
359 * the synchronization/ordering tag
360 */
361 uint64_t tag:32;
362
363 /**
364 * WORD 2 HW WRITE: the following 64-bits are filled in by
365 * hardware when a packet arrives This indicates a variety of
366 * status and error conditions.
367 */
368 cvmx_pip_wqe_word2 word2;
369
370 /**
371 * Pointer to the first segment of the packet.
372 */
373 union cvmx_buf_ptr packet_ptr;
374
375 /**
376 * HW WRITE: octeon will fill in a programmable amount from the
377 * packet, up to (at most, but perhaps less) the amount
378 * needed to fill the work queue entry to 128 bytes
379 *
380 * If the packet is recognized to be IP, the hardware starts
381 * (except that the IPv4 header is padded for appropriate
382 * alignment) writing here where the IP header starts. If the
383 * packet is not recognized to be IP, the hardware starts
384 * writing the beginning of the packet here.
385 */
386 uint8_t packet_data[96];
387
388 /**
389 * If desired, SW can make the work Q entry any length. For the
390 * purposes of discussion here, Assume 128B always, as this is all that
391 * the hardware deals with.
392 *
393 */
394
395} CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
396
397#endif /* __CVMX_WQE_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 7e1286706d46..740be97a3251 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -31,6 +31,27 @@
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/string.h> 32#include <linux/string.h>
33 33
34enum cvmx_mips_space {
35 CVMX_MIPS_SPACE_XKSEG = 3LL,
36 CVMX_MIPS_SPACE_XKPHYS = 2LL,
37 CVMX_MIPS_SPACE_XSSEG = 1LL,
38 CVMX_MIPS_SPACE_XUSEG = 0LL
39};
40
41/* These macros for use when using 32 bit pointers. */
42#define CVMX_MIPS32_SPACE_KSEG0 1l
43#define CVMX_ADD_SEG32(segment, add) \
44 (((int32_t)segment << 31) | (int32_t)(add))
45
46#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
47
48/* These macros simplify the process of creating common IO addresses */
49#define CVMX_ADD_SEG(segment, add) \
50 ((((uint64_t)segment) << 62) | (add))
51#ifndef CVMX_ADD_IO_SEG
52#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
53#endif
54
34#include "cvmx-asm.h" 55#include "cvmx-asm.h"
35#include "cvmx-packet.h" 56#include "cvmx-packet.h"
36#include "cvmx-sysinfo.h" 57#include "cvmx-sysinfo.h"
@@ -129,27 +150,6 @@ static inline uint64_t cvmx_build_bits(uint64_t high_bit,
129 return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit; 150 return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
130} 151}
131 152
132enum cvmx_mips_space {
133 CVMX_MIPS_SPACE_XKSEG = 3LL,
134 CVMX_MIPS_SPACE_XKPHYS = 2LL,
135 CVMX_MIPS_SPACE_XSSEG = 1LL,
136 CVMX_MIPS_SPACE_XUSEG = 0LL
137};
138
139/* These macros for use when using 32 bit pointers. */
140#define CVMX_MIPS32_SPACE_KSEG0 1l
141#define CVMX_ADD_SEG32(segment, add) \
142 (((int32_t)segment << 31) | (int32_t)(add))
143
144#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
145
146/* These macros simplify the process of creating common IO addresses */
147#define CVMX_ADD_SEG(segment, add) \
148 ((((uint64_t)segment) << 62) | (add))
149#ifndef CVMX_ADD_IO_SEG
150#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
151#endif
152
153/** 153/**
154 * Convert a memory pointer (void*) into a hardware compatible 154 * Convert a memory pointer (void*) into a hardware compatible
155 * memory address (uint64_t). Octeon hardware widgets don't 155 * memory address (uint64_t). Octeon hardware widgets don't
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index cba6fbed9f43..8008da2f8779 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -31,8 +31,14 @@
31 31
32#ifndef __OCTEON_FEATURE_H__ 32#ifndef __OCTEON_FEATURE_H__
33#define __OCTEON_FEATURE_H__ 33#define __OCTEON_FEATURE_H__
34#include <asm/octeon/cvmx-mio-defs.h>
35#include <asm/octeon/cvmx-rnm-defs.h>
34 36
35enum octeon_feature { 37enum octeon_feature {
38 /* CN68XX uses port kinds for packet interface */
39 OCTEON_FEATURE_PKND,
40 /* CN68XX has different fields in word0 - word2 */
41 OCTEON_FEATURE_CN68XX_WQE,
36 /* 42 /*
37 * Octeon models in the CN5XXX family and higher support 43 * Octeon models in the CN5XXX family and higher support
38 * atomic add instructions to memory (saa/saad). 44 * atomic add instructions to memory (saa/saad).
@@ -42,8 +48,13 @@ enum octeon_feature {
42 OCTEON_FEATURE_ZIP, 48 OCTEON_FEATURE_ZIP,
43 /* Does this Octeon support crypto acceleration using COP2? */ 49 /* Does this Octeon support crypto acceleration using COP2? */
44 OCTEON_FEATURE_CRYPTO, 50 OCTEON_FEATURE_CRYPTO,
51 OCTEON_FEATURE_DORM_CRYPTO,
45 /* Does this Octeon support PCI express? */ 52 /* Does this Octeon support PCI express? */
46 OCTEON_FEATURE_PCIE, 53 OCTEON_FEATURE_PCIE,
54 /* Does this Octeon support SRIOs */
55 OCTEON_FEATURE_SRIO,
56 /* Does this Octeon support Interlaken */
57 OCTEON_FEATURE_ILK,
47 /* Some Octeon models support internal memory for storing 58 /* Some Octeon models support internal memory for storing
48 * cryptographic keys */ 59 * cryptographic keys */
49 OCTEON_FEATURE_KEY_MEMORY, 60 OCTEON_FEATURE_KEY_MEMORY,
@@ -64,6 +75,15 @@ enum octeon_feature {
64 /* Octeon MDIO block supports clause 45 transactions for 10 75 /* Octeon MDIO block supports clause 45 transactions for 10
65 * Gig support */ 76 * Gig support */
66 OCTEON_FEATURE_MDIO_CLAUSE_45, 77 OCTEON_FEATURE_MDIO_CLAUSE_45,
78 /*
79 * CN52XX and CN56XX used a block named NPEI for PCIe
80 * access. Newer chips replaced this with SLI+DPI.
81 */
82 OCTEON_FEATURE_NPEI,
83 OCTEON_FEATURE_HFA,
84 OCTEON_FEATURE_DFM,
85 OCTEON_FEATURE_CIU2,
86 OCTEON_MAX_FEATURE
67}; 87};
68 88
69static inline int cvmx_fuse_read(int fuse); 89static inline int cvmx_fuse_read(int fuse);
@@ -96,30 +116,78 @@ static inline int octeon_has_feature(enum octeon_feature feature)
96 return !cvmx_fuse_read(121); 116 return !cvmx_fuse_read(121);
97 117
98 case OCTEON_FEATURE_CRYPTO: 118 case OCTEON_FEATURE_CRYPTO:
99 return !cvmx_fuse_read(90); 119 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
120 union cvmx_mio_fus_dat2 fus_2;
121 fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
122 if (fus_2.s.nocrypto || fus_2.s.nomul) {
123 return 0;
124 } else if (!fus_2.s.dorm_crypto) {
125 return 1;
126 } else {
127 union cvmx_rnm_ctl_status st;
128 st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
129 return st.s.eer_val;
130 }
131 } else {
132 return !cvmx_fuse_read(90);
133 }
134
135 case OCTEON_FEATURE_DORM_CRYPTO:
136 if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
137 union cvmx_mio_fus_dat2 fus_2;
138 fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
139 return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
140 } else {
141 return 0;
142 }
100 143
101 case OCTEON_FEATURE_PCIE: 144 case OCTEON_FEATURE_PCIE:
102 case OCTEON_FEATURE_MGMT_PORT:
103 case OCTEON_FEATURE_RAID:
104 return OCTEON_IS_MODEL(OCTEON_CN56XX) 145 return OCTEON_IS_MODEL(OCTEON_CN56XX)
105 || OCTEON_IS_MODEL(OCTEON_CN52XX); 146 || OCTEON_IS_MODEL(OCTEON_CN52XX)
147 || OCTEON_IS_MODEL(OCTEON_CN6XXX);
148
149 case OCTEON_FEATURE_SRIO:
150 return OCTEON_IS_MODEL(OCTEON_CN63XX)
151 || OCTEON_IS_MODEL(OCTEON_CN66XX);
152
153 case OCTEON_FEATURE_ILK:
154 return (OCTEON_IS_MODEL(OCTEON_CN68XX));
106 155
107 case OCTEON_FEATURE_KEY_MEMORY: 156 case OCTEON_FEATURE_KEY_MEMORY:
157 return OCTEON_IS_MODEL(OCTEON_CN38XX)
158 || OCTEON_IS_MODEL(OCTEON_CN58XX)
159 || OCTEON_IS_MODEL(OCTEON_CN56XX)
160 || OCTEON_IS_MODEL(OCTEON_CN6XXX);
161
108 case OCTEON_FEATURE_LED_CONTROLLER: 162 case OCTEON_FEATURE_LED_CONTROLLER:
109 return OCTEON_IS_MODEL(OCTEON_CN38XX) 163 return OCTEON_IS_MODEL(OCTEON_CN38XX)
110 || OCTEON_IS_MODEL(OCTEON_CN58XX) 164 || OCTEON_IS_MODEL(OCTEON_CN58XX)
111 || OCTEON_IS_MODEL(OCTEON_CN56XX); 165 || OCTEON_IS_MODEL(OCTEON_CN56XX);
166
112 case OCTEON_FEATURE_TRA: 167 case OCTEON_FEATURE_TRA:
113 return !(OCTEON_IS_MODEL(OCTEON_CN30XX) 168 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
114 || OCTEON_IS_MODEL(OCTEON_CN50XX)); 169 || OCTEON_IS_MODEL(OCTEON_CN50XX));
170 case OCTEON_FEATURE_MGMT_PORT:
171 return OCTEON_IS_MODEL(OCTEON_CN56XX)
172 || OCTEON_IS_MODEL(OCTEON_CN52XX)
173 || OCTEON_IS_MODEL(OCTEON_CN6XXX);
174
175 case OCTEON_FEATURE_RAID:
176 return OCTEON_IS_MODEL(OCTEON_CN56XX)
177 || OCTEON_IS_MODEL(OCTEON_CN52XX)
178 || OCTEON_IS_MODEL(OCTEON_CN6XXX);
179
115 case OCTEON_FEATURE_USB: 180 case OCTEON_FEATURE_USB:
116 return !(OCTEON_IS_MODEL(OCTEON_CN38XX) 181 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
117 || OCTEON_IS_MODEL(OCTEON_CN58XX)); 182 || OCTEON_IS_MODEL(OCTEON_CN58XX));
183
118 case OCTEON_FEATURE_NO_WPTR: 184 case OCTEON_FEATURE_NO_WPTR:
119 return (OCTEON_IS_MODEL(OCTEON_CN56XX) 185 return (OCTEON_IS_MODEL(OCTEON_CN56XX)
120 || OCTEON_IS_MODEL(OCTEON_CN52XX)) 186 || OCTEON_IS_MODEL(OCTEON_CN52XX)
121 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) 187 || OCTEON_IS_MODEL(OCTEON_CN6XXX))
122 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X); 188 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
189 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
190
123 case OCTEON_FEATURE_DFA: 191 case OCTEON_FEATURE_DFA:
124 if (!OCTEON_IS_MODEL(OCTEON_CN38XX) 192 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
125 && !OCTEON_IS_MODEL(OCTEON_CN31XX) 193 && !OCTEON_IS_MODEL(OCTEON_CN31XX)
@@ -127,14 +195,42 @@ static inline int octeon_has_feature(enum octeon_feature feature)
127 return 0; 195 return 0;
128 else if (OCTEON_IS_MODEL(OCTEON_CN3020)) 196 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
129 return 0; 197 return 0;
130 else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
131 return 1;
132 else 198 else
133 return !cvmx_fuse_read(120); 199 return !cvmx_fuse_read(120);
200
201 case OCTEON_FEATURE_HFA:
202 if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
203 return 0;
204 else
205 return !cvmx_fuse_read(90);
206
207 case OCTEON_FEATURE_DFM:
208 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)
209 || OCTEON_IS_MODEL(OCTEON_CN66XX)))
210 return 0;
211 else
212 return !cvmx_fuse_read(90);
213
134 case OCTEON_FEATURE_MDIO_CLAUSE_45: 214 case OCTEON_FEATURE_MDIO_CLAUSE_45:
135 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX) 215 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
136 || OCTEON_IS_MODEL(OCTEON_CN58XX) 216 || OCTEON_IS_MODEL(OCTEON_CN58XX)
137 || OCTEON_IS_MODEL(OCTEON_CN50XX)); 217 || OCTEON_IS_MODEL(OCTEON_CN50XX));
218
219 case OCTEON_FEATURE_NPEI:
220 return OCTEON_IS_MODEL(OCTEON_CN56XX)
221 || OCTEON_IS_MODEL(OCTEON_CN52XX);
222
223 case OCTEON_FEATURE_PKND:
224 return OCTEON_IS_MODEL(OCTEON_CN68XX);
225
226 case OCTEON_FEATURE_CN68XX_WQE:
227 return OCTEON_IS_MODEL(OCTEON_CN68XX);
228
229 case OCTEON_FEATURE_CIU2:
230 return OCTEON_IS_MODEL(OCTEON_CN68XX);
231
232 default:
233 break;
138 } 234 }
139 return 0; 235 return 0;
140} 236}
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index 700f88e31cad..4e338a4d9424 100644
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -4,7 +4,7 @@
4 * Contact: support@caviumnetworks.com 4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK 5 * This file is part of the OCTEON SDK
6 * 6 *
7 * Copyright (c) 2003-2008 Cavium Networks 7 * Copyright (c) 2003-2010 Cavium Networks
8 * 8 *
9 * This file is free software; you can redistribute it and/or modify 9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as 10 * it under the terms of the GNU General Public License, Version 2, as
@@ -24,14 +24,6 @@
24 * This file may also be available under a different license from Cavium. 24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/ 26 ***********************license end**************************************/
27
28/*
29 *
30 * File defining different Octeon model IDs and macros to
31 * compare them.
32 *
33 */
34
35#ifndef __OCTEON_MODEL_H__ 27#ifndef __OCTEON_MODEL_H__
36#define __OCTEON_MODEL_H__ 28#define __OCTEON_MODEL_H__
37 29
@@ -52,6 +44,8 @@
52 * for internal use only, and may change without notice. 44 * for internal use only, and may change without notice.
53 */ 45 */
54 46
47#define OCTEON_FAMILY_MASK 0x00ffff00
48
55/* Flag bits in top byte */ 49/* Flag bits in top byte */
56/* Ignores revision in model checks */ 50/* Ignores revision in model checks */
57#define OM_IGNORE_REVISION 0x01000000 51#define OM_IGNORE_REVISION 0x01000000
@@ -63,21 +57,48 @@
63#define OM_IGNORE_MINOR_REVISION 0x08000000 57#define OM_IGNORE_MINOR_REVISION 0x08000000
64#define OM_FLAG_MASK 0xff000000 58#define OM_FLAG_MASK 0xff000000
65 59
66#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000 /* Match all cn5XXX Octeon models. */ 60/* Match all cn5XXX Octeon models. */
67#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000 /* Match all cn6XXX Octeon models. */ 61#define OM_MATCH_5XXX_FAMILY_MODELS 0x20000000
62/* Match all cn6XXX Octeon models. */
63#define OM_MATCH_6XXX_FAMILY_MODELS 0x40000000
68 64
69/* 65/*
70 * CN6XXX models with new revision encoding 66 * CN6XXX models with new revision encoding
71 */ 67 */
68#define OCTEON_CN68XX_PASS1_0 0x000d9100
69#define OCTEON_CN68XX_PASS1_1 0x000d9101
70#define OCTEON_CN68XX_PASS1_2 0x000d9102
71#define OCTEON_CN68XX_PASS2_0 0x000d9108
72
73#define OCTEON_CN68XX (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
74#define OCTEON_CN68XX_PASS1_X (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
75#define OCTEON_CN68XX_PASS2_X (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
76
77#define OCTEON_CN68XX_PASS1 OCTEON_CN68XX_PASS1_X
78#define OCTEON_CN68XX_PASS2 OCTEON_CN68XX_PASS2_X
79
80#define OCTEON_CN66XX_PASS1_0 0x000d9200
81#define OCTEON_CN66XX_PASS1_2 0x000d9202
82
83#define OCTEON_CN66XX (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION)
84#define OCTEON_CN66XX_PASS1_X (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
85
72#define OCTEON_CN63XX_PASS1_0 0x000d9000 86#define OCTEON_CN63XX_PASS1_0 0x000d9000
73#define OCTEON_CN63XX_PASS1_1 0x000d9001 87#define OCTEON_CN63XX_PASS1_1 0x000d9001
74#define OCTEON_CN63XX_PASS1_2 0x000d9002 88#define OCTEON_CN63XX_PASS1_2 0x000d9002
75#define OCTEON_CN63XX_PASS2_0 0x000d9008 89#define OCTEON_CN63XX_PASS2_0 0x000d9008
90#define OCTEON_CN63XX_PASS2_1 0x000d9009
91#define OCTEON_CN63XX_PASS2_2 0x000d900a
76 92
77#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION) 93#define OCTEON_CN63XX (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
78#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION) 94#define OCTEON_CN63XX_PASS1_X (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
79#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION) 95#define OCTEON_CN63XX_PASS2_X (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
80 96
97#define OCTEON_CN61XX_PASS1_0 0x000d9300
98
99#define OCTEON_CN61XX (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
100#define OCTEON_CN61XX_PASS1_X (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
101
81/* 102/*
82 * CN5XXX models with new revision encoding 103 * CN5XXX models with new revision encoding
83 */ 104 */
@@ -90,10 +111,8 @@
90#define OCTEON_CN58XX_PASS2_3 0x000d030b 111#define OCTEON_CN58XX_PASS2_3 0x000d030b
91 112
92#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION) 113#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
93#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 \ 114#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
94 | OM_IGNORE_MINOR_REVISION) 115#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
95#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 \
96 | OM_IGNORE_MINOR_REVISION)
97#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X 116#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X
98#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X 117#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X
99 118
@@ -103,10 +122,8 @@
103#define OCTEON_CN56XX_PASS2_1 0x000d0409 122#define OCTEON_CN56XX_PASS2_1 0x000d0409
104 123
105#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION) 124#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
106#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 \ 125#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
107 | OM_IGNORE_MINOR_REVISION) 126#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
108#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 \
109 | OM_IGNORE_MINOR_REVISION)
110#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X 127#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X
111#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X 128#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X
112 129
@@ -125,8 +142,7 @@
125#define OCTEON_CN50XX_PASS1_0 0x000d0600 142#define OCTEON_CN50XX_PASS1_0 0x000d0600
126 143
127#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION) 144#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
128#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 \ 145#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
129 | OM_IGNORE_MINOR_REVISION)
130#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X 146#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X
131 147
132/* 148/*
@@ -138,10 +154,8 @@
138#define OCTEON_CN52XX_PASS2_0 0x000d0708 154#define OCTEON_CN52XX_PASS2_0 0x000d0708
139 155
140#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION) 156#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
141#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 \ 157#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
142 | OM_IGNORE_MINOR_REVISION) 158#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
143#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 \
144 | OM_IGNORE_MINOR_REVISION)
145#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X 159#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X
146#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X 160#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X
147 161
@@ -174,28 +188,23 @@
174#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL) 188#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL)
175#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL) 189#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL)
176#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL) 190#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL)
177#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \ 191#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
178 | OM_CHECK_SUBMODEL)
179 192
180#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL) 193#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL)
181#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL) 194#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL)
182#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL) 195#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL)
183#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \ 196#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
184 | OM_CHECK_SUBMODEL)
185 197
186#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL) 198#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL)
187#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL) 199#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL)
188#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL) 200#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL)
189#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \ 201#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
190 | OM_CHECK_SUBMODEL)
191
192
193
194/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
195#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 \
196 | OM_MATCH_PREVIOUS_MODELS \
197 | OM_IGNORE_REVISION)
198 202
203/*
204 * This matches the complete family of CN3xxx CPUs, and not subsequent
205 * models
206 */
207#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
199#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS) 208#define OCTEON_CN5XXX (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
200#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS) 209#define OCTEON_CN6XXX (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
201 210
@@ -221,90 +230,55 @@
221#define OCTEON_38XX_FAMILY_MASK 0x00ffff00 230#define OCTEON_38XX_FAMILY_MASK 0x00ffff00
222#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f 231#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f
223#define OCTEON_38XX_MODEL_MASK 0x00ffff10 232#define OCTEON_38XX_MODEL_MASK 0x00ffff10
224#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \ 233#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK)
225 | OCTEON_38XX_MODEL_MASK)
226 234
227/* CN5XXX and later use different layout of bits in the revision ID field */ 235/* CN5XXX and later use different layout of bits in the revision ID field */
228#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK 236#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK
229#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f 237#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f
230#define OCTEON_58XX_MODEL_MASK 0x00ffffc0 238#define OCTEON_58XX_MODEL_MASK 0x00ffffc0
231#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \ 239#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
232 | OCTEON_58XX_MODEL_MASK) 240#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8)
233#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
234 & 0x00fffff8)
235#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0 241#define OCTEON_5XXX_MODEL_MASK 0x00ff0fc0
236 242
237#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
238
239/* NOTE: This is for internal (to this file) use only. */
240static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
241 uint32_t chip_model)
242{
243 uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL;
244
245 if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) {
246 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
247 __OCTEON_MATCH_MASK__(chip_model, arg_model,
248 OCTEON_38XX_MODEL_MASK))
249 return 1;
250 if (((arg_model & OM_FLAG_MASK) == 0) &&
251 __OCTEON_MATCH_MASK__(chip_model, arg_model,
252 OCTEON_38XX_FAMILY_REV_MASK))
253 return 1;
254 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
255 __OCTEON_MATCH_MASK__(chip_model, arg_model,
256 OCTEON_38XX_FAMILY_MASK))
257 return 1;
258 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
259 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
260 OCTEON_38XX_MODEL_REV_MASK))
261 return 1;
262 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
263 ((chip_model & OCTEON_38XX_MODEL_MASK) <
264 (arg_model & OCTEON_38XX_MODEL_MASK)))
265 return 1;
266 } else {
267 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
268 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
269 OCTEON_58XX_MODEL_MASK))
270 return 1;
271 if (((arg_model & OM_FLAG_MASK) == 0) &&
272 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
273 OCTEON_58XX_FAMILY_REV_MASK))
274 return 1;
275 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) &&
276 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
277 OCTEON_58XX_MODEL_MINOR_REV_MASK))
278 return 1;
279 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
280 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
281 OCTEON_58XX_FAMILY_MASK))
282 return 1;
283 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
284 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
285 OCTEON_58XX_MODEL_REV_MASK))
286 return 1;
287
288 if (((arg_model & OM_MATCH_5XXX_FAMILY_MODELS) == OM_MATCH_5XXX_FAMILY_MODELS) &&
289 ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0))
290 return 1;
291
292 if (((arg_model & OM_MATCH_6XXX_FAMILY_MODELS) == OM_MATCH_6XXX_FAMILY_MODELS) &&
293 ((chip_model) >= OCTEON_CN63XX_PASS1_0))
294 return 1;
295
296 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
297 ((chip_model & OCTEON_58XX_MODEL_MASK) <
298 (arg_model & OCTEON_58XX_MODEL_MASK)))
299 return 1;
300 }
301 return 0;
302}
303
304/* forward declarations */ 243/* forward declarations */
305static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure)); 244static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
306static inline uint64_t cvmx_read_csr(uint64_t csr_addr); 245static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
307 246
247#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
248
249/* NOTE: This for internal use only! */
250#define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model) \
251((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) && ( \
252 ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
253 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \
254 ((((arg_model) & (OM_FLAG_MASK)) == 0) \
255 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_REV_MASK)) || \
256 ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
257 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_FAMILY_MASK)) || \
258 ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
259 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_REV_MASK)) || \
260 ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
261 && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \
262 )) || \
263 (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0) && ( \
264 ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
265 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
266 ((((arg_model) & (OM_FLAG_MASK)) == 0) \
267 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_REV_MASK)) || \
268 ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_MINOR_REVISION) \
269 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MINOR_REV_MASK)) || \
270 ((((arg_model) & (OM_FLAG_MASK)) == OM_IGNORE_REVISION) \
271 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_FAMILY_MASK)) || \
272 ((((arg_model) & (OM_FLAG_MASK)) == OM_CHECK_SUBMODEL) \
273 && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_REV_MASK)) || \
274 ((((arg_model) & (OM_MATCH_5XXX_FAMILY_MODELS)) == OM_MATCH_5XXX_FAMILY_MODELS) \
275 && ((chip_model) >= OCTEON_CN58XX_PASS1_0) && ((chip_model) < OCTEON_CN63XX_PASS1_0)) || \
276 ((((arg_model) & (OM_MATCH_6XXX_FAMILY_MODELS)) == OM_MATCH_6XXX_FAMILY_MODELS) \
277 && ((chip_model) >= OCTEON_CN63XX_PASS1_0)) || \
278 ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
279 && (((chip_model) & OCTEON_58XX_MODEL_MASK) < ((arg_model) & OCTEON_58XX_MODEL_MASK))) \
280 )))
281
308/* NOTE: This for internal use only!!!!! */ 282/* NOTE: This for internal use only!!!!! */
309static inline int __octeon_is_model_runtime__(uint32_t model) 283static inline int __octeon_is_model_runtime__(uint32_t model)
310{ 284{
@@ -312,22 +286,25 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
312 286
313 /* 287 /*
314 * Check for special case of mismarked 3005 samples. We only 288 * Check for special case of mismarked 3005 samples. We only
315 * need to check if the sub model isn't being ignored. 289 * need to check if the sub model isn't being ignored
316 */ 290 */
317 if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) { 291 if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
318 if (cpuid == OCTEON_CN3010_PASS1 \ 292 if (cpuid == OCTEON_CN3010_PASS1 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
319 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
320 cpuid |= 0x10; 293 cpuid |= 0x10;
321 } 294 }
322 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid); 295 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
323} 296}
324 297
325/* 298/*
326 * The OCTEON_IS_MODEL macro should be used for all Octeon model 299 * The OCTEON_IS_MODEL macro should be used for all Octeon model checking done
327 * checking done in a program. This should be kept runtime if at all 300 * in a program.
328 * possible. Any compile time (#if OCTEON_IS_MODEL) usage must be 301 * This should be kept runtime if at all possible and must be conditionalized
329 * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking 302 * with OCTEON_IS_COMMON_BINARY() if runtime checking support is required.
330 * support is required. 303 *
304 * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) )
305 * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR()
306 * I.e.:
307 * #if OCTEON_IS_MODEL(OCTEON_CN56XX) -> #if CVMX_COMPILED_FOR(OCTEON_CN56XX)
331 */ 308 */
332#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x) 309#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
333#define OCTEON_IS_COMMON_BINARY() 1 310#define OCTEON_IS_COMMON_BINARY() 1
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index fba2ba200f58..c66734bd3382 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -56,7 +56,8 @@ enum octeon_dma_bar_type {
56 OCTEON_DMA_BAR_TYPE_INVALID, 56 OCTEON_DMA_BAR_TYPE_INVALID,
57 OCTEON_DMA_BAR_TYPE_SMALL, 57 OCTEON_DMA_BAR_TYPE_SMALL,
58 OCTEON_DMA_BAR_TYPE_BIG, 58 OCTEON_DMA_BAR_TYPE_BIG,
59 OCTEON_DMA_BAR_TYPE_PCIE 59 OCTEON_DMA_BAR_TYPE_PCIE,
60 OCTEON_DMA_BAR_TYPE_PCIE2
60}; 61};
61 62
62/* 63/*
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index 90ff2f497c50..ff74aec3561a 100644
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -24,5 +24,18 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
24extern void (*board_nmi_handler_setup)(void); 24extern void (*board_nmi_handler_setup)(void);
25extern void (*board_ejtag_handler_setup)(void); 25extern void (*board_ejtag_handler_setup)(void);
26extern void (*board_bind_eic_interrupt)(int irq, int regset); 26extern void (*board_bind_eic_interrupt)(int irq, int regset);
27extern void (*board_ebase_setup)(void);
28
29extern int register_nmi_notifier(struct notifier_block *nb);
30
31#define nmi_notifier(fn, pri) \
32({ \
33 static struct notifier_block fn##_nb = { \
34 .notifier_call = fn, \
35 .priority = pri \
36 }; \
37 \
38 register_nmi_notifier(&fn##_nb); \
39})
27 40
28#endif /* _ASM_TRAPS_H */ 41#endif /* _ASM_TRAPS_H */
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 1a966183e353..0c6877ea9004 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -55,9 +55,11 @@ obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
55obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o 55obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
56obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o 56obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
57obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o 57obj-$(CONFIG_CPU_XLR) += r4k_fpu.o r4k_switch.o
58obj-$(CONFIG_CPU_XLP) += r4k_fpu.o r4k_switch.o
58 59
59obj-$(CONFIG_SMP) += smp.o 60obj-$(CONFIG_SMP) += smp.o
60obj-$(CONFIG_SMP_UP) += smp-up.o 61obj-$(CONFIG_SMP_UP) += smp-up.o
62obj-$(CONFIG_CPU_BMIPS) += smp-bmips.o bmips_vec.o
61 63
62obj-$(CONFIG_MIPS_MT) += mips-mt.o 64obj-$(CONFIG_MIPS_MT) += mips-mt.o
63obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o 65obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
new file mode 100644
index 000000000000..e908e81330b1
--- /dev/null
+++ b/arch/mips/kernel/bmips_vec.S
@@ -0,0 +1,255 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * Reset/NMI/re-entry vectors for BMIPS processors
9 */
10
11#include <linux/init.h>
12
13#include <asm/asm.h>
14#include <asm/asmmacro.h>
15#include <asm/cacheops.h>
16#include <asm/regdef.h>
17#include <asm/mipsregs.h>
18#include <asm/stackframe.h>
19#include <asm/addrspace.h>
20#include <asm/hazards.h>
21#include <asm/bmips.h>
22
23 .macro BARRIER
24 .set mips32
25 _ssnop
26 _ssnop
27 _ssnop
28 .set mips0
29 .endm
30
31 __CPUINIT
32
33/***********************************************************************
34 * Alternate CPU1 startup vector for BMIPS4350
35 *
36 * On some systems the bootloader has already started CPU1 and configured
37 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
38 * triggered by the SW1 interrupt. If that is the case we try to move
39 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
40 ***********************************************************************/
41
42LEAF(bmips_smp_movevec)
43 la k0, 1f
44 li k1, CKSEG1
45 or k0, k1
46 jr k0
47
481:
49 /* clear IV, pending IPIs */
50 mtc0 zero, CP0_CAUSE
51
52 /* re-enable IRQs to wait for SW1 */
53 li k0, ST0_IE | ST0_BEV | STATUSF_IP1
54 mtc0 k0, CP0_STATUS
55
56 /* set up CPU1 CBR; move BASE to 0xa000_0000 */
57 li k0, 0xff400000
58 mtc0 k0, $22, 6
59 li k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_1
60 or k0, k1
61 li k1, 0xa0080000
62 sw k1, 0(k0)
63
64 /* wait here for SW1 interrupt from bmips_boot_secondary() */
65 wait
66
67 la k0, bmips_reset_nmi_vec
68 li k1, CKSEG1
69 or k0, k1
70 jr k0
71END(bmips_smp_movevec)
72
73/***********************************************************************
74 * Reset/NMI vector
75 * For BMIPS processors that can relocate their exception vectors, this
76 * entire function gets copied to 0x8000_0000.
77 ***********************************************************************/
78
79NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
80 .set push
81 .set noat
82 .align 4
83
84#ifdef CONFIG_SMP
85 /* if the NMI bit is clear, assume this is a CPU1 reset instead */
86 li k1, (1 << 19)
87 mfc0 k0, CP0_STATUS
88 and k0, k1
89 beqz k0, bmips_smp_entry
90
91#if defined(CONFIG_CPU_BMIPS5000)
92 /* if we're not on core 0, this must be the SMP boot signal */
93 li k1, (3 << 25)
94 mfc0 k0, $22
95 and k0, k1
96 bnez k0, bmips_smp_entry
97#endif
98#endif /* CONFIG_SMP */
99
100 /* nope, it's just a regular NMI */
101 SAVE_ALL
102 move a0, sp
103
104 /* clear EXL, ERL, BEV so that TLB refills still work */
105 mfc0 k0, CP0_STATUS
106 li k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE
107 or k0, k1
108 xor k0, k1
109 mtc0 k0, CP0_STATUS
110 BARRIER
111
112 /* jump to the NMI handler function */
113 la k0, nmi_handler
114 jr k0
115
116 RESTORE_ALL
117 .set mips3
118 eret
119
120/***********************************************************************
121 * CPU1 reset vector (used for the initial boot only)
122 * This is still part of bmips_reset_nmi_vec().
123 ***********************************************************************/
124
125#ifdef CONFIG_SMP
126
127bmips_smp_entry:
128
129 /* set up CP0 STATUS; enable FPU */
130 li k0, 0x30000000
131 mtc0 k0, CP0_STATUS
132 BARRIER
133
134 /* set local CP0 CONFIG to make kseg0 cacheable, write-back */
135 mfc0 k0, CP0_CONFIG
136 ori k0, 0x07
137 xori k0, 0x04
138 mtc0 k0, CP0_CONFIG
139
140#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
141 /* initialize CPU1's local I-cache */
142 li k0, 0x80000000
143 li k1, 0x80010000
144 mtc0 zero, $28
145 mtc0 zero, $28, 1
146 BARRIER
147
1481: cache Index_Store_Tag_I, 0(k0)
149 addiu k0, 16
150 bne k0, k1, 1b
151#elif defined(CONFIG_CPU_BMIPS5000)
152 /* set exception vector base */
153 la k0, ebase
154 lw k0, 0(k0)
155 mtc0 k0, $15, 1
156 BARRIER
157#endif
158
159 /* jump back to kseg0 in case we need to remap the kseg1 area */
160 la k0, 1f
161 jr k0
1621:
163 la k0, bmips_enable_xks01
164 jalr k0
165
166 /* use temporary stack to set up upper memory TLB */
167 li sp, BMIPS_WARM_RESTART_VEC
168 la k0, plat_wired_tlb_setup
169 jalr k0
170
171 /* switch to permanent stack and continue booting */
172
173 .global bmips_secondary_reentry
174bmips_secondary_reentry:
175 la k0, bmips_smp_boot_sp
176 lw sp, 0(k0)
177 la k0, bmips_smp_boot_gp
178 lw gp, 0(k0)
179 la k0, start_secondary
180 jr k0
181
182#endif /* CONFIG_SMP */
183
184 .align 4
185 .global bmips_reset_nmi_vec_end
186bmips_reset_nmi_vec_end:
187
188END(bmips_reset_nmi_vec)
189
190 .set pop
191 .previous
192
193/***********************************************************************
194 * CPU1 warm restart vector (used for second and subsequent boots).
195 * Also used for S2 standby recovery (PM).
196 * This entire function gets copied to (BMIPS_WARM_RESTART_VEC)
197 ***********************************************************************/
198
199LEAF(bmips_smp_int_vec)
200
201 .align 4
202 mfc0 k0, CP0_STATUS
203 ori k0, 0x01
204 xori k0, 0x01
205 mtc0 k0, CP0_STATUS
206 eret
207
208 .align 4
209 .global bmips_smp_int_vec_end
210bmips_smp_int_vec_end:
211
212END(bmips_smp_int_vec)
213
214/***********************************************************************
215 * XKS01 support
216 * Certain CPUs support extending kseg0 to 1024MB.
217 ***********************************************************************/
218
219 __CPUINIT
220
221LEAF(bmips_enable_xks01)
222
223#if defined(CONFIG_XKS01)
224
225#if defined(CONFIG_CPU_BMIPS4380)
226 mfc0 t0, $22, 3
227 li t1, 0x1ff0
228 li t2, (1 << 12) | (1 << 9)
229 or t0, t1
230 xor t0, t1
231 or t0, t2
232 mtc0 t0, $22, 3
233 BARRIER
234#elif defined(CONFIG_CPU_BMIPS5000)
235 mfc0 t0, $22, 5
236 li t1, 0x01ff
237 li t2, (1 << 8) | (1 << 5)
238 or t0, t1
239 xor t0, t1
240 or t0, t2
241 mtc0 t0, $22, 5
242 BARRIER
243#else
244
245#error Missing XKS01 setup
246
247#endif
248
249#endif /* defined(CONFIG_XKS01) */
250
251 jr ra
252
253END(bmips_enable_xks01)
254
255 .previous
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 32103cc2a257..4d735d0e58f5 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -9,6 +9,7 @@
9#include <linux/kernel.h> 9#include <linux/kernel.h>
10#include <linux/sched.h> 10#include <linux/sched.h>
11#include <linux/signal.h> 11#include <linux/signal.h>
12#include <linux/module.h>
12#include <asm/branch.h> 13#include <asm/branch.h>
13#include <asm/cpu.h> 14#include <asm/cpu.h>
14#include <asm/cpu-features.h> 15#include <asm/cpu-features.h>
@@ -17,28 +18,22 @@
17#include <asm/ptrace.h> 18#include <asm/ptrace.h>
18#include <asm/uaccess.h> 19#include <asm/uaccess.h>
19 20
20/* 21/**
21 * Compute the return address and do emulate branch simulation, if required. 22 * __compute_return_epc_for_insn - Computes the return address and do emulate
23 * branch simulation, if required.
24 *
25 * @regs: Pointer to pt_regs
26 * @insn: branch instruction to decode
27 * @returns: -EFAULT on error and forces SIGBUS, and on success
28 * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
29 * evaluating the branch.
22 */ 30 */
23int __compute_return_epc(struct pt_regs *regs) 31int __compute_return_epc_for_insn(struct pt_regs *regs,
32 union mips_instruction insn)
24{ 33{
25 unsigned int __user *addr;
26 unsigned int bit, fcr31, dspcontrol; 34 unsigned int bit, fcr31, dspcontrol;
27 long epc; 35 long epc = regs->cp0_epc;
28 union mips_instruction insn; 36 int ret = 0;
29
30 epc = regs->cp0_epc;
31 if (epc & 3)
32 goto unaligned;
33
34 /*
35 * Read the instruction
36 */
37 addr = (unsigned int __user *) epc;
38 if (__get_user(insn.word, addr)) {
39 force_sig(SIGSEGV, current);
40 return -EFAULT;
41 }
42 37
43 switch (insn.i_format.opcode) { 38 switch (insn.i_format.opcode) {
44 /* 39 /*
@@ -64,18 +59,22 @@ int __compute_return_epc(struct pt_regs *regs)
64 switch (insn.i_format.rt) { 59 switch (insn.i_format.rt) {
65 case bltz_op: 60 case bltz_op:
66 case bltzl_op: 61 case bltzl_op:
67 if ((long)regs->regs[insn.i_format.rs] < 0) 62 if ((long)regs->regs[insn.i_format.rs] < 0) {
68 epc = epc + 4 + (insn.i_format.simmediate << 2); 63 epc = epc + 4 + (insn.i_format.simmediate << 2);
69 else 64 if (insn.i_format.rt == bltzl_op)
65 ret = BRANCH_LIKELY_TAKEN;
66 } else
70 epc += 8; 67 epc += 8;
71 regs->cp0_epc = epc; 68 regs->cp0_epc = epc;
72 break; 69 break;
73 70
74 case bgez_op: 71 case bgez_op:
75 case bgezl_op: 72 case bgezl_op:
76 if ((long)regs->regs[insn.i_format.rs] >= 0) 73 if ((long)regs->regs[insn.i_format.rs] >= 0) {
77 epc = epc + 4 + (insn.i_format.simmediate << 2); 74 epc = epc + 4 + (insn.i_format.simmediate << 2);
78 else 75 if (insn.i_format.rt == bgezl_op)
76 ret = BRANCH_LIKELY_TAKEN;
77 } else
79 epc += 8; 78 epc += 8;
80 regs->cp0_epc = epc; 79 regs->cp0_epc = epc;
81 break; 80 break;
@@ -83,9 +82,11 @@ int __compute_return_epc(struct pt_regs *regs)
83 case bltzal_op: 82 case bltzal_op:
84 case bltzall_op: 83 case bltzall_op:
85 regs->regs[31] = epc + 8; 84 regs->regs[31] = epc + 8;
86 if ((long)regs->regs[insn.i_format.rs] < 0) 85 if ((long)regs->regs[insn.i_format.rs] < 0) {
87 epc = epc + 4 + (insn.i_format.simmediate << 2); 86 epc = epc + 4 + (insn.i_format.simmediate << 2);
88 else 87 if (insn.i_format.rt == bltzall_op)
88 ret = BRANCH_LIKELY_TAKEN;
89 } else
89 epc += 8; 90 epc += 8;
90 regs->cp0_epc = epc; 91 regs->cp0_epc = epc;
91 break; 92 break;
@@ -93,12 +94,15 @@ int __compute_return_epc(struct pt_regs *regs)
93 case bgezal_op: 94 case bgezal_op:
94 case bgezall_op: 95 case bgezall_op:
95 regs->regs[31] = epc + 8; 96 regs->regs[31] = epc + 8;
96 if ((long)regs->regs[insn.i_format.rs] >= 0) 97 if ((long)regs->regs[insn.i_format.rs] >= 0) {
97 epc = epc + 4 + (insn.i_format.simmediate << 2); 98 epc = epc + 4 + (insn.i_format.simmediate << 2);
98 else 99 if (insn.i_format.rt == bgezall_op)
100 ret = BRANCH_LIKELY_TAKEN;
101 } else
99 epc += 8; 102 epc += 8;
100 regs->cp0_epc = epc; 103 regs->cp0_epc = epc;
101 break; 104 break;
105
102 case bposge32_op: 106 case bposge32_op:
103 if (!cpu_has_dsp) 107 if (!cpu_has_dsp)
104 goto sigill; 108 goto sigill;
@@ -133,9 +137,11 @@ int __compute_return_epc(struct pt_regs *regs)
133 case beq_op: 137 case beq_op:
134 case beql_op: 138 case beql_op:
135 if (regs->regs[insn.i_format.rs] == 139 if (regs->regs[insn.i_format.rs] ==
136 regs->regs[insn.i_format.rt]) 140 regs->regs[insn.i_format.rt]) {
137 epc = epc + 4 + (insn.i_format.simmediate << 2); 141 epc = epc + 4 + (insn.i_format.simmediate << 2);
138 else 142 if (insn.i_format.rt == beql_op)
143 ret = BRANCH_LIKELY_TAKEN;
144 } else
139 epc += 8; 145 epc += 8;
140 regs->cp0_epc = epc; 146 regs->cp0_epc = epc;
141 break; 147 break;
@@ -143,9 +149,11 @@ int __compute_return_epc(struct pt_regs *regs)
143 case bne_op: 149 case bne_op:
144 case bnel_op: 150 case bnel_op:
145 if (regs->regs[insn.i_format.rs] != 151 if (regs->regs[insn.i_format.rs] !=
146 regs->regs[insn.i_format.rt]) 152 regs->regs[insn.i_format.rt]) {
147 epc = epc + 4 + (insn.i_format.simmediate << 2); 153 epc = epc + 4 + (insn.i_format.simmediate << 2);
148 else 154 if (insn.i_format.rt == bnel_op)
155 ret = BRANCH_LIKELY_TAKEN;
156 } else
149 epc += 8; 157 epc += 8;
150 regs->cp0_epc = epc; 158 regs->cp0_epc = epc;
151 break; 159 break;
@@ -153,9 +161,11 @@ int __compute_return_epc(struct pt_regs *regs)
153 case blez_op: /* not really i_format */ 161 case blez_op: /* not really i_format */
154 case blezl_op: 162 case blezl_op:
155 /* rt field assumed to be zero */ 163 /* rt field assumed to be zero */
156 if ((long)regs->regs[insn.i_format.rs] <= 0) 164 if ((long)regs->regs[insn.i_format.rs] <= 0) {
157 epc = epc + 4 + (insn.i_format.simmediate << 2); 165 epc = epc + 4 + (insn.i_format.simmediate << 2);
158 else 166 if (insn.i_format.rt == bnel_op)
167 ret = BRANCH_LIKELY_TAKEN;
168 } else
159 epc += 8; 169 epc += 8;
160 regs->cp0_epc = epc; 170 regs->cp0_epc = epc;
161 break; 171 break;
@@ -163,9 +173,11 @@ int __compute_return_epc(struct pt_regs *regs)
163 case bgtz_op: 173 case bgtz_op:
164 case bgtzl_op: 174 case bgtzl_op:
165 /* rt field assumed to be zero */ 175 /* rt field assumed to be zero */
166 if ((long)regs->regs[insn.i_format.rs] > 0) 176 if ((long)regs->regs[insn.i_format.rs] > 0) {
167 epc = epc + 4 + (insn.i_format.simmediate << 2); 177 epc = epc + 4 + (insn.i_format.simmediate << 2);
168 else 178 if (insn.i_format.rt == bnel_op)
179 ret = BRANCH_LIKELY_TAKEN;
180 } else
169 epc += 8; 181 epc += 8;
170 regs->cp0_epc = epc; 182 regs->cp0_epc = epc;
171 break; 183 break;
@@ -187,18 +199,22 @@ int __compute_return_epc(struct pt_regs *regs)
187 switch (insn.i_format.rt & 3) { 199 switch (insn.i_format.rt & 3) {
188 case 0: /* bc1f */ 200 case 0: /* bc1f */
189 case 2: /* bc1fl */ 201 case 2: /* bc1fl */
190 if (~fcr31 & (1 << bit)) 202 if (~fcr31 & (1 << bit)) {
191 epc = epc + 4 + (insn.i_format.simmediate << 2); 203 epc = epc + 4 + (insn.i_format.simmediate << 2);
192 else 204 if (insn.i_format.rt == 2)
205 ret = BRANCH_LIKELY_TAKEN;
206 } else
193 epc += 8; 207 epc += 8;
194 regs->cp0_epc = epc; 208 regs->cp0_epc = epc;
195 break; 209 break;
196 210
197 case 1: /* bc1t */ 211 case 1: /* bc1t */
198 case 3: /* bc1tl */ 212 case 3: /* bc1tl */
199 if (fcr31 & (1 << bit)) 213 if (fcr31 & (1 << bit)) {
200 epc = epc + 4 + (insn.i_format.simmediate << 2); 214 epc = epc + 4 + (insn.i_format.simmediate << 2);
201 else 215 if (insn.i_format.rt == 3)
216 ret = BRANCH_LIKELY_TAKEN;
217 } else
202 epc += 8; 218 epc += 8;
203 regs->cp0_epc = epc; 219 regs->cp0_epc = epc;
204 break; 220 break;
@@ -239,15 +255,39 @@ int __compute_return_epc(struct pt_regs *regs)
239#endif 255#endif
240 } 256 }
241 257
242 return 0; 258 return ret;
243 259
244unaligned: 260sigill:
245 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm); 261 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm);
246 force_sig(SIGBUS, current); 262 force_sig(SIGBUS, current);
247 return -EFAULT; 263 return -EFAULT;
264}
265EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
248 266
249sigill: 267int __compute_return_epc(struct pt_regs *regs)
250 printk("%s: DSP branch but not DSP ASE - sending SIGBUS.\n", current->comm); 268{
269 unsigned int __user *addr;
270 long epc;
271 union mips_instruction insn;
272
273 epc = regs->cp0_epc;
274 if (epc & 3)
275 goto unaligned;
276
277 /*
278 * Read the instruction
279 */
280 addr = (unsigned int __user *) epc;
281 if (__get_user(insn.word, addr)) {
282 force_sig(SIGSEGV, current);
283 return -EFAULT;
284 }
285
286 return __compute_return_epc_for_insn(regs, insn);
287
288unaligned:
289 printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
251 force_sig(SIGBUS, current); 290 force_sig(SIGBUS, current);
252 return -EFAULT; 291 return -EFAULT;
292
253} 293}
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 98383995e6ac..0bab464b8e33 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -191,6 +191,8 @@ void __init check_wait(void)
191 case CPU_CAVIUM_OCTEON_PLUS: 191 case CPU_CAVIUM_OCTEON_PLUS:
192 case CPU_CAVIUM_OCTEON2: 192 case CPU_CAVIUM_OCTEON2:
193 case CPU_JZRISC: 193 case CPU_JZRISC:
194 case CPU_XLR:
195 case CPU_XLP:
194 cpu_wait = r4k_wait; 196 cpu_wait = r4k_wait;
195 break; 197 break;
196 198
@@ -1030,6 +1032,12 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1030 MIPS_CPU_LLSC); 1032 MIPS_CPU_LLSC);
1031 1033
1032 switch (c->processor_id & 0xff00) { 1034 switch (c->processor_id & 0xff00) {
1035 case PRID_IMP_NETLOGIC_XLP8XX:
1036 case PRID_IMP_NETLOGIC_XLP3XX:
1037 c->cputype = CPU_XLP;
1038 __cpu_name[cpu] = "Netlogic XLP";
1039 break;
1040
1033 case PRID_IMP_NETLOGIC_XLR732: 1041 case PRID_IMP_NETLOGIC_XLR732:
1034 case PRID_IMP_NETLOGIC_XLR716: 1042 case PRID_IMP_NETLOGIC_XLR716:
1035 case PRID_IMP_NETLOGIC_XLR532: 1043 case PRID_IMP_NETLOGIC_XLR532:
@@ -1060,14 +1068,21 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1060 break; 1068 break;
1061 1069
1062 default: 1070 default:
1063 printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", 1071 pr_info("Unknown Netlogic chip id [%02x]!\n",
1064 c->processor_id); 1072 c->processor_id);
1065 c->cputype = CPU_XLR; 1073 c->cputype = CPU_XLR;
1066 break; 1074 break;
1067 } 1075 }
1068 1076
1069 c->isa_level = MIPS_CPU_ISA_M64R1; 1077 if (c->cputype == CPU_XLP) {
1070 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1078 c->isa_level = MIPS_CPU_ISA_M64R2;
1079 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1080 /* This will be updated again after all threads are woken up */
1081 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1082 } else {
1083 c->isa_level = MIPS_CPU_ISA_M64R1;
1084 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1085 }
1071} 1086}
1072 1087
1073#ifdef CONFIG_64BIT 1088#ifdef CONFIG_64BIT
diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
index ee28683fc2ac..158467da9bc1 100644
--- a/arch/mips/kernel/kprobes.c
+++ b/arch/mips/kernel/kprobes.c
@@ -25,10 +25,12 @@
25 25
26#include <linux/kprobes.h> 26#include <linux/kprobes.h>
27#include <linux/preempt.h> 27#include <linux/preempt.h>
28#include <linux/uaccess.h>
28#include <linux/kdebug.h> 29#include <linux/kdebug.h>
29#include <linux/slab.h> 30#include <linux/slab.h>
30 31
31#include <asm/ptrace.h> 32#include <asm/ptrace.h>
33#include <asm/branch.h>
32#include <asm/break.h> 34#include <asm/break.h>
33#include <asm/inst.h> 35#include <asm/inst.h>
34 36
@@ -112,17 +114,49 @@ insn_ok:
112 return 0; 114 return 0;
113} 115}
114 116
117/*
118 * insn_has_ll_or_sc function checks whether instruction is ll or sc
119 * one; putting breakpoint on top of atomic ll/sc pair is bad idea;
120 * so we need to prevent it and refuse kprobes insertion for such
121 * instructions; cannot do much about breakpoint in the middle of
122 * ll/sc pair; it is upto user to avoid those places
123 */
124static int __kprobes insn_has_ll_or_sc(union mips_instruction insn)
125{
126 int ret = 0;
127
128 switch (insn.i_format.opcode) {
129 case ll_op:
130 case lld_op:
131 case sc_op:
132 case scd_op:
133 ret = 1;
134 break;
135 default:
136 break;
137 }
138 return ret;
139}
140
115int __kprobes arch_prepare_kprobe(struct kprobe *p) 141int __kprobes arch_prepare_kprobe(struct kprobe *p)
116{ 142{
117 union mips_instruction insn; 143 union mips_instruction insn;
118 union mips_instruction prev_insn; 144 union mips_instruction prev_insn;
119 int ret = 0; 145 int ret = 0;
120 146
121 prev_insn = p->addr[-1];
122 insn = p->addr[0]; 147 insn = p->addr[0];
123 148
124 if (insn_has_delayslot(insn) || insn_has_delayslot(prev_insn)) { 149 if (insn_has_ll_or_sc(insn)) {
125 pr_notice("Kprobes for branch and jump instructions are not supported\n"); 150 pr_notice("Kprobes for ll and sc instructions are not"
151 "supported\n");
152 ret = -EINVAL;
153 goto out;
154 }
155
156 if ((probe_kernel_read(&prev_insn, p->addr - 1,
157 sizeof(mips_instruction)) == 0) &&
158 insn_has_delayslot(prev_insn)) {
159 pr_notice("Kprobes for branch delayslot are not supported\n");
126 ret = -EINVAL; 160 ret = -EINVAL;
127 goto out; 161 goto out;
128 } 162 }
@@ -138,9 +172,20 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
138 * In the kprobe->ainsn.insn[] array we store the original 172 * In the kprobe->ainsn.insn[] array we store the original
139 * instruction at index zero and a break trap instruction at 173 * instruction at index zero and a break trap instruction at
140 * index one. 174 * index one.
175 *
176 * On MIPS arch if the instruction at probed address is a
177 * branch instruction, we need to execute the instruction at
178 * Branch Delayslot (BD) at the time of probe hit. As MIPS also
179 * doesn't have single stepping support, the BD instruction can
180 * not be executed in-line and it would be executed on SSOL slot
181 * using a normal breakpoint instruction in the next slot.
182 * So, read the instruction and save it for later execution.
141 */ 183 */
184 if (insn_has_delayslot(insn))
185 memcpy(&p->ainsn.insn[0], p->addr + 1, sizeof(kprobe_opcode_t));
186 else
187 memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
142 188
143 memcpy(&p->ainsn.insn[0], p->addr, sizeof(kprobe_opcode_t));
144 p->ainsn.insn[1] = breakpoint2_insn; 189 p->ainsn.insn[1] = breakpoint2_insn;
145 p->opcode = *p->addr; 190 p->opcode = *p->addr;
146 191
@@ -191,16 +236,96 @@ static void set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
191 kcb->kprobe_saved_epc = regs->cp0_epc; 236 kcb->kprobe_saved_epc = regs->cp0_epc;
192} 237}
193 238
194static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs) 239/**
240 * evaluate_branch_instrucion -
241 *
242 * Evaluate the branch instruction at probed address during probe hit. The
243 * result of evaluation would be the updated epc. The insturction in delayslot
244 * would actually be single stepped using a normal breakpoint) on SSOL slot.
245 *
246 * The result is also saved in the kprobe control block for later use,
247 * in case we need to execute the delayslot instruction. The latter will be
248 * false for NOP instruction in dealyslot and the branch-likely instructions
249 * when the branch is taken. And for those cases we set a flag as
250 * SKIP_DELAYSLOT in the kprobe control block
251 */
252static int evaluate_branch_instruction(struct kprobe *p, struct pt_regs *regs,
253 struct kprobe_ctlblk *kcb)
195{ 254{
255 union mips_instruction insn = p->opcode;
256 long epc;
257 int ret = 0;
258
259 epc = regs->cp0_epc;
260 if (epc & 3)
261 goto unaligned;
262
263 if (p->ainsn.insn->word == 0)
264 kcb->flags |= SKIP_DELAYSLOT;
265 else
266 kcb->flags &= ~SKIP_DELAYSLOT;
267
268 ret = __compute_return_epc_for_insn(regs, insn);
269 if (ret < 0)
270 return ret;
271
272 if (ret == BRANCH_LIKELY_TAKEN)
273 kcb->flags |= SKIP_DELAYSLOT;
274
275 kcb->target_epc = regs->cp0_epc;
276
277 return 0;
278
279unaligned:
280 pr_notice("%s: unaligned epc - sending SIGBUS.\n", current->comm);
281 force_sig(SIGBUS, current);
282 return -EFAULT;
283
284}
285
286static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs,
287 struct kprobe_ctlblk *kcb)
288{
289 int ret = 0;
290
196 regs->cp0_status &= ~ST0_IE; 291 regs->cp0_status &= ~ST0_IE;
197 292
198 /* single step inline if the instruction is a break */ 293 /* single step inline if the instruction is a break */
199 if (p->opcode.word == breakpoint_insn.word || 294 if (p->opcode.word == breakpoint_insn.word ||
200 p->opcode.word == breakpoint2_insn.word) 295 p->opcode.word == breakpoint2_insn.word)
201 regs->cp0_epc = (unsigned long)p->addr; 296 regs->cp0_epc = (unsigned long)p->addr;
202 else 297 else if (insn_has_delayslot(p->opcode)) {
203 regs->cp0_epc = (unsigned long)&p->ainsn.insn[0]; 298 ret = evaluate_branch_instruction(p, regs, kcb);
299 if (ret < 0) {
300 pr_notice("Kprobes: Error in evaluating branch\n");
301 return;
302 }
303 }
304 regs->cp0_epc = (unsigned long)&p->ainsn.insn[0];
305}
306
307/*
308 * Called after single-stepping. p->addr is the address of the
309 * instruction whose first byte has been replaced by the "break 0"
310 * instruction. To avoid the SMP problems that can occur when we
311 * temporarily put back the original opcode to single-step, we
312 * single-stepped a copy of the instruction. The address of this
313 * copy is p->ainsn.insn.
314 *
315 * This function prepares to return from the post-single-step
316 * breakpoint trap. In case of branch instructions, the target
317 * epc to be restored.
318 */
319static void __kprobes resume_execution(struct kprobe *p,
320 struct pt_regs *regs,
321 struct kprobe_ctlblk *kcb)
322{
323 if (insn_has_delayslot(p->opcode))
324 regs->cp0_epc = kcb->target_epc;
325 else {
326 unsigned long orig_epc = kcb->kprobe_saved_epc;
327 regs->cp0_epc = orig_epc + 4;
328 }
204} 329}
205 330
206static int __kprobes kprobe_handler(struct pt_regs *regs) 331static int __kprobes kprobe_handler(struct pt_regs *regs)
@@ -239,8 +364,13 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
239 save_previous_kprobe(kcb); 364 save_previous_kprobe(kcb);
240 set_current_kprobe(p, regs, kcb); 365 set_current_kprobe(p, regs, kcb);
241 kprobes_inc_nmissed_count(p); 366 kprobes_inc_nmissed_count(p);
242 prepare_singlestep(p, regs); 367 prepare_singlestep(p, regs, kcb);
243 kcb->kprobe_status = KPROBE_REENTER; 368 kcb->kprobe_status = KPROBE_REENTER;
369 if (kcb->flags & SKIP_DELAYSLOT) {
370 resume_execution(p, regs, kcb);
371 restore_previous_kprobe(kcb);
372 preempt_enable_no_resched();
373 }
244 return 1; 374 return 1;
245 } else { 375 } else {
246 if (addr->word != breakpoint_insn.word) { 376 if (addr->word != breakpoint_insn.word) {
@@ -284,8 +414,16 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
284 } 414 }
285 415
286ss_probe: 416ss_probe:
287 prepare_singlestep(p, regs); 417 prepare_singlestep(p, regs, kcb);
288 kcb->kprobe_status = KPROBE_HIT_SS; 418 if (kcb->flags & SKIP_DELAYSLOT) {
419 kcb->kprobe_status = KPROBE_HIT_SSDONE;
420 if (p->post_handler)
421 p->post_handler(p, regs, 0);
422 resume_execution(p, regs, kcb);
423 preempt_enable_no_resched();
424 } else
425 kcb->kprobe_status = KPROBE_HIT_SS;
426
289 return 1; 427 return 1;
290 428
291no_kprobe: 429no_kprobe:
@@ -294,25 +432,6 @@ no_kprobe:
294 432
295} 433}
296 434
297/*
298 * Called after single-stepping. p->addr is the address of the
299 * instruction whose first byte has been replaced by the "break 0"
300 * instruction. To avoid the SMP problems that can occur when we
301 * temporarily put back the original opcode to single-step, we
302 * single-stepped a copy of the instruction. The address of this
303 * copy is p->ainsn.insn.
304 *
305 * This function prepares to return from the post-single-step
306 * breakpoint trap.
307 */
308static void __kprobes resume_execution(struct kprobe *p,
309 struct pt_regs *regs,
310 struct kprobe_ctlblk *kcb)
311{
312 unsigned long orig_epc = kcb->kprobe_saved_epc;
313 regs->cp0_epc = orig_epc + 4;
314}
315
316static inline int post_kprobe_handler(struct pt_regs *regs) 435static inline int post_kprobe_handler(struct pt_regs *regs)
317{ 436{
318 struct kprobe *cur = kprobe_running(); 437 struct kprobe *cur = kprobe_running();
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 4f2971bcf8e5..bda4bc9e6988 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -621,11 +621,6 @@ static int mipspmu_event_init(struct perf_event *event)
621 return -ENODEV; 621 return -ENODEV;
622 622
623 if (!atomic_inc_not_zero(&active_events)) { 623 if (!atomic_inc_not_zero(&active_events)) {
624 if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
625 atomic_dec(&active_events);
626 return -ENOSPC;
627 }
628
629 mutex_lock(&pmu_reserve_mutex); 624 mutex_lock(&pmu_reserve_mutex);
630 if (atomic_read(&active_events) == 0) 625 if (atomic_read(&active_events) == 0)
631 err = mipspmu_get_irq(); 626 err = mipspmu_get_irq();
@@ -638,11 +633,7 @@ static int mipspmu_event_init(struct perf_event *event)
638 if (err) 633 if (err)
639 return err; 634 return err;
640 635
641 err = __hw_perf_event_init(event); 636 return __hw_perf_event_init(event);
642 if (err)
643 hw_perf_event_destroy(event);
644
645 return err;
646} 637}
647 638
648static struct pmu pmu = { 639static struct pmu pmu = {
@@ -712,18 +703,6 @@ static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
712 703
713} 704}
714 705
715static int validate_event(struct cpu_hw_events *cpuc,
716 struct perf_event *event)
717{
718 struct hw_perf_event fake_hwc = event->hw;
719
720 /* Allow mixed event group. So return 1 to pass validation. */
721 if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
722 return 1;
723
724 return mipsxx_pmu_alloc_counter(cpuc, &fake_hwc) >= 0;
725}
726
727static int validate_group(struct perf_event *event) 706static int validate_group(struct perf_event *event)
728{ 707{
729 struct perf_event *sibling, *leader = event->group_leader; 708 struct perf_event *sibling, *leader = event->group_leader;
@@ -731,15 +710,15 @@ static int validate_group(struct perf_event *event)
731 710
732 memset(&fake_cpuc, 0, sizeof(fake_cpuc)); 711 memset(&fake_cpuc, 0, sizeof(fake_cpuc));
733 712
734 if (!validate_event(&fake_cpuc, leader)) 713 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
735 return -ENOSPC; 714 return -ENOSPC;
736 715
737 list_for_each_entry(sibling, &leader->sibling_list, group_entry) { 716 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
738 if (!validate_event(&fake_cpuc, sibling)) 717 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
739 return -ENOSPC; 718 return -ENOSPC;
740 } 719 }
741 720
742 if (!validate_event(&fake_cpuc, event)) 721 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
743 return -ENOSPC; 722 return -ENOSPC;
744 723
745 return 0; 724 return 0;
@@ -1279,13 +1258,14 @@ static int __hw_perf_event_init(struct perf_event *event)
1279 } 1258 }
1280 1259
1281 err = 0; 1260 err = 0;
1282 if (event->group_leader != event) { 1261 if (event->group_leader != event)
1283 err = validate_group(event); 1262 err = validate_group(event);
1284 if (err)
1285 return -EINVAL;
1286 }
1287 1263
1288 event->destroy = hw_perf_event_destroy; 1264 event->destroy = hw_perf_event_destroy;
1265
1266 if (err)
1267 event->destroy(event);
1268
1289 return err; 1269 return err;
1290} 1270}
1291 1271
@@ -1380,20 +1360,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1380} 1360}
1381 1361
1382/* 24K */ 1362/* 24K */
1383#define IS_UNSUPPORTED_24K_EVENT(r, b) \
1384 ((b) == 12 || (r) == 151 || (r) == 152 || (b) == 26 || \
1385 (b) == 27 || (r) == 28 || (r) == 158 || (b) == 31 || \
1386 (b) == 32 || (b) == 34 || (b) == 36 || (r) == 168 || \
1387 (r) == 172 || (b) == 47 || ((b) >= 56 && (b) <= 63) || \
1388 ((b) >= 68 && (b) <= 127))
1389#define IS_BOTH_COUNTERS_24K_EVENT(b) \ 1363#define IS_BOTH_COUNTERS_24K_EVENT(b) \
1390 ((b) == 0 || (b) == 1 || (b) == 11) 1364 ((b) == 0 || (b) == 1 || (b) == 11)
1391 1365
1392/* 34K */ 1366/* 34K */
1393#define IS_UNSUPPORTED_34K_EVENT(r, b) \
1394 ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 36 || \
1395 (b) == 38 || (r) == 175 || ((b) >= 56 && (b) <= 63) || \
1396 ((b) >= 68 && (b) <= 127))
1397#define IS_BOTH_COUNTERS_34K_EVENT(b) \ 1367#define IS_BOTH_COUNTERS_34K_EVENT(b) \
1398 ((b) == 0 || (b) == 1 || (b) == 11) 1368 ((b) == 0 || (b) == 1 || (b) == 11)
1399#ifdef CONFIG_MIPS_MT_SMP 1369#ifdef CONFIG_MIPS_MT_SMP
@@ -1406,20 +1376,10 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1406#endif 1376#endif
1407 1377
1408/* 74K */ 1378/* 74K */
1409#define IS_UNSUPPORTED_74K_EVENT(r, b) \
1410 ((r) == 5 || ((r) >= 135 && (r) <= 137) || \
1411 ((b) >= 10 && (b) <= 12) || (b) == 22 || (b) == 27 || \
1412 (b) == 33 || (b) == 34 || ((b) >= 47 && (b) <= 49) || \
1413 (r) == 178 || (b) == 55 || (b) == 57 || (b) == 60 || \
1414 (b) == 61 || (r) == 62 || (r) == 191 || \
1415 ((b) >= 64 && (b) <= 127))
1416#define IS_BOTH_COUNTERS_74K_EVENT(b) \ 1379#define IS_BOTH_COUNTERS_74K_EVENT(b) \
1417 ((b) == 0 || (b) == 1) 1380 ((b) == 0 || (b) == 1)
1418 1381
1419/* 1004K */ 1382/* 1004K */
1420#define IS_UNSUPPORTED_1004K_EVENT(r, b) \
1421 ((b) == 12 || (r) == 27 || (r) == 158 || (b) == 38 || \
1422 (r) == 175 || (b) == 63 || ((b) >= 68 && (b) <= 127))
1423#define IS_BOTH_COUNTERS_1004K_EVENT(b) \ 1383#define IS_BOTH_COUNTERS_1004K_EVENT(b) \
1424 ((b) == 0 || (b) == 1 || (b) == 11) 1384 ((b) == 0 || (b) == 1 || (b) == 11)
1425#ifdef CONFIG_MIPS_MT_SMP 1385#ifdef CONFIG_MIPS_MT_SMP
@@ -1445,11 +1405,10 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1445 unsigned int raw_id = config & 0xff; 1405 unsigned int raw_id = config & 0xff;
1446 unsigned int base_id = raw_id & 0x7f; 1406 unsigned int base_id = raw_id & 0x7f;
1447 1407
1408 raw_event.event_id = base_id;
1409
1448 switch (current_cpu_type()) { 1410 switch (current_cpu_type()) {
1449 case CPU_24K: 1411 case CPU_24K:
1450 if (IS_UNSUPPORTED_24K_EVENT(raw_id, base_id))
1451 return ERR_PTR(-EOPNOTSUPP);
1452 raw_event.event_id = base_id;
1453 if (IS_BOTH_COUNTERS_24K_EVENT(base_id)) 1412 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1454 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1413 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1455 else 1414 else
@@ -1464,9 +1423,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1464#endif 1423#endif
1465 break; 1424 break;
1466 case CPU_34K: 1425 case CPU_34K:
1467 if (IS_UNSUPPORTED_34K_EVENT(raw_id, base_id))
1468 return ERR_PTR(-EOPNOTSUPP);
1469 raw_event.event_id = base_id;
1470 if (IS_BOTH_COUNTERS_34K_EVENT(base_id)) 1426 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1471 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1427 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1472 else 1428 else
@@ -1482,9 +1438,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1482#endif 1438#endif
1483 break; 1439 break;
1484 case CPU_74K: 1440 case CPU_74K:
1485 if (IS_UNSUPPORTED_74K_EVENT(raw_id, base_id))
1486 return ERR_PTR(-EOPNOTSUPP);
1487 raw_event.event_id = base_id;
1488 if (IS_BOTH_COUNTERS_74K_EVENT(base_id)) 1441 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1489 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1442 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1490 else 1443 else
@@ -1495,9 +1448,6 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1495#endif 1448#endif
1496 break; 1449 break;
1497 case CPU_1004K: 1450 case CPU_1004K:
1498 if (IS_UNSUPPORTED_1004K_EVENT(raw_id, base_id))
1499 return ERR_PTR(-EOPNOTSUPP);
1500 raw_event.event_id = base_id;
1501 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id)) 1451 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1502 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1452 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1503 else 1453 else
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
new file mode 100644
index 000000000000..58fe71afd879
--- /dev/null
+++ b/arch/mips/kernel/smp-bmips.c
@@ -0,0 +1,458 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * SMP support for BMIPS
9 */
10
11#include <linux/version.h>
12#include <linux/init.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
15#include <linux/delay.h>
16#include <linux/smp.h>
17#include <linux/interrupt.h>
18#include <linux/spinlock.h>
19#include <linux/init.h>
20#include <linux/cpu.h>
21#include <linux/cpumask.h>
22#include <linux/reboot.h>
23#include <linux/io.h>
24#include <linux/compiler.h>
25#include <linux/linkage.h>
26#include <linux/bug.h>
27#include <linux/kernel.h>
28
29#include <asm/time.h>
30#include <asm/pgtable.h>
31#include <asm/processor.h>
32#include <asm/system.h>
33#include <asm/bootinfo.h>
34#include <asm/pmon.h>
35#include <asm/cacheflush.h>
36#include <asm/tlbflush.h>
37#include <asm/mipsregs.h>
38#include <asm/bmips.h>
39#include <asm/traps.h>
40#include <asm/barrier.h>
41
42static int __maybe_unused max_cpus = 1;
43
44/* these may be configured by the platform code */
45int bmips_smp_enabled = 1;
46int bmips_cpu_offset;
47cpumask_t bmips_booted_mask;
48
49#ifdef CONFIG_SMP
50
51/* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
52unsigned long bmips_smp_boot_sp;
53unsigned long bmips_smp_boot_gp;
54
55static void bmips_send_ipi_single(int cpu, unsigned int action);
56static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
57
58/* SW interrupts 0,1 are used for interprocessor signaling */
59#define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
60#define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
61
62#define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
63#define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
64#define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
65#define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
66
67static void __init bmips_smp_setup(void)
68{
69 int i;
70
71#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
72 /* arbitration priority */
73 clear_c0_brcm_cmt_ctrl(0x30);
74
75 /* NBK and weak order flags */
76 set_c0_brcm_config_0(0x30000);
77
78 /*
79 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
80 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
81 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
82 */
83 change_c0_brcm_cmt_intr(0xf8018000,
84 (0x02 << 27) | (0x03 << 15));
85
86 /* single core, 2 threads (2 pipelines) */
87 max_cpus = 2;
88#elif defined(CONFIG_CPU_BMIPS5000)
89 /* enable raceless SW interrupts */
90 set_c0_brcm_config(0x03 << 22);
91
92 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
93 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
94
95 /* N cores, 2 threads per core */
96 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
97
98 /* clear any pending SW interrupts */
99 for (i = 0; i < max_cpus; i++) {
100 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
101 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
102 }
103#endif
104
105 if (!bmips_smp_enabled)
106 max_cpus = 1;
107
108 /* this can be overridden by the BSP */
109 if (!board_ebase_setup)
110 board_ebase_setup = &bmips_ebase_setup;
111
112 for (i = 0; i < max_cpus; i++) {
113 __cpu_number_map[i] = 1;
114 __cpu_logical_map[i] = 1;
115 set_cpu_possible(i, 1);
116 set_cpu_present(i, 1);
117 }
118}
119
120/*
121 * IPI IRQ setup - runs on CPU0
122 */
123static void bmips_prepare_cpus(unsigned int max_cpus)
124{
125 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
126 "smp_ipi0", NULL))
127 panic("Can't request IPI0 interrupt\n");
128 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
129 "smp_ipi1", NULL))
130 panic("Can't request IPI1 interrupt\n");
131}
132
133/*
134 * Tell the hardware to boot CPUx - runs on CPU0
135 */
136static void bmips_boot_secondary(int cpu, struct task_struct *idle)
137{
138 bmips_smp_boot_sp = __KSTK_TOS(idle);
139 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
140 mb();
141
142 /*
143 * Initial boot sequence for secondary CPU:
144 * bmips_reset_nmi_vec @ a000_0000 ->
145 * bmips_smp_entry ->
146 * plat_wired_tlb_setup (cached function call; optional) ->
147 * start_secondary (cached jump)
148 *
149 * Warm restart sequence:
150 * play_dead WAIT loop ->
151 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
152 * eret to play_dead ->
153 * bmips_secondary_reentry ->
154 * start_secondary
155 */
156
157 pr_info("SMP: Booting CPU%d...\n", cpu);
158
159 if (cpumask_test_cpu(cpu, &bmips_booted_mask))
160 bmips_send_ipi_single(cpu, 0);
161 else {
162#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
163 set_c0_brcm_cmt_ctrl(0x01);
164#elif defined(CONFIG_CPU_BMIPS5000)
165 if (cpu & 0x01)
166 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
167 else {
168 /*
169 * core N thread 0 was already booted; just
170 * pulse the NMI line
171 */
172 bmips_write_zscm_reg(0x210, 0xc0000000);
173 udelay(10);
174 bmips_write_zscm_reg(0x210, 0x00);
175 }
176#endif
177 cpumask_set_cpu(cpu, &bmips_booted_mask);
178 }
179}
180
181/*
182 * Early setup - runs on secondary CPU after cache probe
183 */
184static void bmips_init_secondary(void)
185{
186 /* move NMI vector to kseg0, in case XKS01 is enabled */
187
188#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
189 void __iomem *cbr = BMIPS_GET_CBR();
190 unsigned long old_vec;
191
192 old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
193 __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
194
195 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
196#elif defined(CONFIG_CPU_BMIPS5000)
197 write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
198 (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
199
200 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
201#endif
202
203 /* make sure there won't be a timer interrupt for a little while */
204 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
205
206 irq_enable_hazard();
207 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
208 irq_enable_hazard();
209}
210
211/*
212 * Late setup - runs on secondary CPU before entering the idle loop
213 */
214static void bmips_smp_finish(void)
215{
216 pr_info("SMP: CPU%d is running\n", smp_processor_id());
217}
218
219/*
220 * Runs on CPU0 after all CPUs have been booted
221 */
222static void bmips_cpus_done(void)
223{
224}
225
226#if defined(CONFIG_CPU_BMIPS5000)
227
228/*
229 * BMIPS5000 raceless IPIs
230 *
231 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
232 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
233 * IPI1 is used for SMP_CALL_FUNCTION
234 */
235
236static void bmips_send_ipi_single(int cpu, unsigned int action)
237{
238 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
239}
240
241static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
242{
243 int action = irq - IPI0_IRQ;
244
245 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
246
247 if (action == 0)
248 scheduler_ipi();
249 else
250 smp_call_function_interrupt();
251
252 return IRQ_HANDLED;
253}
254
255#else
256
257/*
258 * BMIPS43xx racey IPIs
259 *
260 * We use one inbound SW IRQ for each CPU.
261 *
262 * A spinlock must be held in order to keep CPUx from accidentally clearing
263 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
264 * same spinlock is used to protect the action masks.
265 */
266
267static DEFINE_SPINLOCK(ipi_lock);
268static DEFINE_PER_CPU(int, ipi_action_mask);
269
270static void bmips_send_ipi_single(int cpu, unsigned int action)
271{
272 unsigned long flags;
273
274 spin_lock_irqsave(&ipi_lock, flags);
275 set_c0_cause(cpu ? C_SW1 : C_SW0);
276 per_cpu(ipi_action_mask, cpu) |= action;
277 irq_enable_hazard();
278 spin_unlock_irqrestore(&ipi_lock, flags);
279}
280
281static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
282{
283 unsigned long flags;
284 int action, cpu = irq - IPI0_IRQ;
285
286 spin_lock_irqsave(&ipi_lock, flags);
287 action = __get_cpu_var(ipi_action_mask);
288 per_cpu(ipi_action_mask, cpu) = 0;
289 clear_c0_cause(cpu ? C_SW1 : C_SW0);
290 spin_unlock_irqrestore(&ipi_lock, flags);
291
292 if (action & SMP_RESCHEDULE_YOURSELF)
293 scheduler_ipi();
294 if (action & SMP_CALL_FUNCTION)
295 smp_call_function_interrupt();
296
297 return IRQ_HANDLED;
298}
299
300#endif /* BMIPS type */
301
302static void bmips_send_ipi_mask(const struct cpumask *mask,
303 unsigned int action)
304{
305 unsigned int i;
306
307 for_each_cpu(i, mask)
308 bmips_send_ipi_single(i, action);
309}
310
311#ifdef CONFIG_HOTPLUG_CPU
312
313static int bmips_cpu_disable(void)
314{
315 unsigned int cpu = smp_processor_id();
316
317 if (cpu == 0)
318 return -EBUSY;
319
320 pr_info("SMP: CPU%d is offline\n", cpu);
321
322 cpu_clear(cpu, cpu_online_map);
323 cpu_clear(cpu, cpu_callin_map);
324
325 local_flush_tlb_all();
326 local_flush_icache_range(0, ~0);
327
328 return 0;
329}
330
331static void bmips_cpu_die(unsigned int cpu)
332{
333}
334
335void __ref play_dead(void)
336{
337 idle_task_exit();
338
339 /* flush data cache */
340 _dma_cache_wback_inv(0, ~0);
341
342 /*
343 * Wakeup is on SW0 or SW1; disable everything else
344 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
345 * IRQ handlers; this clears ST0_IE and returns immediately.
346 */
347 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
348 change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
349 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
350 irq_disable_hazard();
351
352 /*
353 * wait for SW interrupt from bmips_boot_secondary(), then jump
354 * back to start_secondary()
355 */
356 __asm__ __volatile__(
357 " wait\n"
358 " j bmips_secondary_reentry\n"
359 : : : "memory");
360}
361
362#endif /* CONFIG_HOTPLUG_CPU */
363
364struct plat_smp_ops bmips_smp_ops = {
365 .smp_setup = bmips_smp_setup,
366 .prepare_cpus = bmips_prepare_cpus,
367 .boot_secondary = bmips_boot_secondary,
368 .smp_finish = bmips_smp_finish,
369 .init_secondary = bmips_init_secondary,
370 .cpus_done = bmips_cpus_done,
371 .send_ipi_single = bmips_send_ipi_single,
372 .send_ipi_mask = bmips_send_ipi_mask,
373#ifdef CONFIG_HOTPLUG_CPU
374 .cpu_disable = bmips_cpu_disable,
375 .cpu_die = bmips_cpu_die,
376#endif
377};
378
379#endif /* CONFIG_SMP */
380
381/***********************************************************************
382 * BMIPS vector relocation
383 * This is primarily used for SMP boot, but it is applicable to some
384 * UP BMIPS systems as well.
385 ***********************************************************************/
386
387static void __cpuinit bmips_wr_vec(unsigned long dst, char *start, char *end)
388{
389 memcpy((void *)dst, start, end - start);
390 dma_cache_wback((unsigned long)start, end - start);
391 local_flush_icache_range(dst, dst + (end - start));
392 instruction_hazard();
393}
394
395static inline void __cpuinit bmips_nmi_handler_setup(void)
396{
397 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
398 &bmips_reset_nmi_vec_end);
399 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
400 &bmips_smp_int_vec_end);
401}
402
403void __cpuinit bmips_ebase_setup(void)
404{
405 unsigned long new_ebase = ebase;
406 void __iomem __maybe_unused *cbr;
407
408 BUG_ON(ebase != CKSEG0);
409
410#if defined(CONFIG_CPU_BMIPS4350)
411 /*
412 * BMIPS4350 cannot relocate the normal vectors, but it
413 * can relocate the BEV=1 vectors. So CPU1 starts up at
414 * the relocated BEV=1, IV=0 general exception vector @
415 * 0xa000_0380.
416 *
417 * set_uncached_handler() is used here because:
418 * - CPU1 will run this from uncached space
419 * - None of the cacheflush functions are set up yet
420 */
421 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
422 &bmips_smp_int_vec, 0x80);
423 __sync();
424 return;
425#elif defined(CONFIG_CPU_BMIPS4380)
426 /*
427 * 0x8000_0000: reset/NMI (initially in kseg1)
428 * 0x8000_0400: normal vectors
429 */
430 new_ebase = 0x80000400;
431 cbr = BMIPS_GET_CBR();
432 __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
433 __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
434#elif defined(CONFIG_CPU_BMIPS5000)
435 /*
436 * 0x8000_0000: reset/NMI (initially in kseg1)
437 * 0x8000_1000: normal vectors
438 */
439 new_ebase = 0x80001000;
440 write_c0_brcm_bootvec(0xa0088008);
441 write_c0_ebase(new_ebase);
442 if (max_cpus > 2)
443 bmips_write_zscm_reg(0xa0, 0xa008a008);
444#else
445 return;
446#endif
447 board_nmi_handler_setup = &bmips_nmi_handler_setup;
448 ebase = new_ebase;
449}
450
451asmlinkage void __weak plat_wired_tlb_setup(void)
452{
453 /*
454 * Called when starting/restarting a secondary CPU.
455 * Kernel stacks and other important data might only be accessible
456 * once the wired entries are present.
457 */
458}
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 363c4764b818..48240fd8c297 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -91,6 +91,7 @@ int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
91void (*board_nmi_handler_setup)(void); 91void (*board_nmi_handler_setup)(void);
92void (*board_ejtag_handler_setup)(void); 92void (*board_ejtag_handler_setup)(void);
93void (*board_bind_eic_interrupt)(int irq, int regset); 93void (*board_bind_eic_interrupt)(int irq, int regset);
94void (*board_ebase_setup)(void);
94 95
95 96
96static void show_raw_backtrace(unsigned long reg29) 97static void show_raw_backtrace(unsigned long reg29)
@@ -1339,9 +1340,18 @@ void ejtag_exception_handler(struct pt_regs *regs)
1339 1340
1340/* 1341/*
1341 * NMI exception handler. 1342 * NMI exception handler.
1343 * No lock; only written during early bootup by CPU 0.
1342 */ 1344 */
1345static RAW_NOTIFIER_HEAD(nmi_chain);
1346
1347int register_nmi_notifier(struct notifier_block *nb)
1348{
1349 return raw_notifier_chain_register(&nmi_chain, nb);
1350}
1351
1343NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) 1352NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1344{ 1353{
1354 raw_notifier_call_chain(&nmi_chain, 0, regs);
1345 bust_spinlocks(1); 1355 bust_spinlocks(1);
1346 printk("NMI taken!!!!\n"); 1356 printk("NMI taken!!!!\n");
1347 die("NMI", regs); 1357 die("NMI", regs);
@@ -1682,6 +1692,8 @@ void __init trap_init(void)
1682 ebase += (read_c0_ebase() & 0x3ffff000); 1692 ebase += (read_c0_ebase() & 0x3ffff000);
1683 } 1693 }
1684 1694
1695 if (board_ebase_setup)
1696 board_ebase_setup();
1685 per_cpu_trap_init(); 1697 per_cpu_trap_init();
1686 1698
1687 /* 1699 /*
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index b2cad4fd5fc4..2a7c74fc15fc 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o
29obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o 29obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o
30obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o 30obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o
31obj-$(CONFIG_CPU_XLR) += dump_tlb.o 31obj-$(CONFIG_CPU_XLR) += dump_tlb.o
32obj-$(CONFIG_CPU_XLP) += dump_tlb.o
32 33
33# libgcc-style stuff needed in the kernel 34# libgcc-style stuff needed in the kernel
34obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o 35obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index dbf2f93a5091..a03bf00a1a9c 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -245,7 +245,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
245 */ 245 */
246 emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */ 246 emulpc = xcp->cp0_epc + 4; /* Snapshot emulation target */
247 247
248 if (__compute_return_epc(xcp)) { 248 if (__compute_return_epc(xcp) < 0) {
249#ifdef CP1DBG 249#ifdef CP1DBG
250 printk("failed to emulate branch at %p\n", 250 printk("failed to emulate branch at %p\n",
251 (void *) (xcp->cp0_epc)); 251 (void *) (xcp->cp0_epc));
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 3ca2a065cf76..4aa20280613e 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o
31obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o 31obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o
32obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o 32obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
33obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o 33obj-$(CONFIG_CPU_XLR) += c-r4k.o tlb-r4k.o cex-gen.o
34obj-$(CONFIG_CPU_XLP) += c-r4k.o tlb-r4k.o cex-gen.o
34 35
35obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o 36obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
36obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o 37obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index a79fe9aa7721..4f9eb0b23036 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1235,6 +1235,9 @@ static void __cpuinit setup_scache(void)
1235 loongson2_sc_init(); 1235 loongson2_sc_init();
1236 return; 1236 return;
1237#endif 1237#endif
1238 case CPU_XLP:
1239 /* don't need to worry about L2, fully coherent */
1240 return;
1238 1241
1239 default: 1242 default:
1240 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1243 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
diff --git a/arch/mips/netlogic/Kconfig b/arch/mips/netlogic/Kconfig
index a5ca743613f2..75bec44b5856 100644
--- a/arch/mips/netlogic/Kconfig
+++ b/arch/mips/netlogic/Kconfig
@@ -1,5 +1,2 @@
1config NLM_COMMON 1config NLM_COMMON
2 bool 2 bool
3
4config NLM_XLR
5 bool
diff --git a/arch/mips/netlogic/Makefile b/arch/mips/netlogic/Makefile
new file mode 100644
index 000000000000..36d169b2ca6d
--- /dev/null
+++ b/arch/mips/netlogic/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_NLM_COMMON) += common/
2obj-$(CONFIG_CPU_XLR) += xlr/
3obj-$(CONFIG_CPU_XLP) += xlp/
diff --git a/arch/mips/netlogic/Platform b/arch/mips/netlogic/Platform
index b648b487fd66..cdfc9abbbb7b 100644
--- a/arch/mips/netlogic/Platform
+++ b/arch/mips/netlogic/Platform
@@ -1,16 +1,17 @@
1# 1#
2# NETLOGIC includes 2# NETLOGIC includes
3# 3#
4cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic 4cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/mach-netlogic
5cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic 5cflags-$(CONFIG_NLM_COMMON) += -I$(srctree)/arch/mips/include/asm/netlogic
6 6
7# 7#
8# use mips64 if xlr is not available 8# use mips64 if xlr is not available
9# 9#
10cflags-$(CONFIG_NLM_XLR) += $(call cc-option,-march=xlr,-march=mips64) 10cflags-$(CONFIG_CPU_XLR) += $(call cc-option,-march=xlr,-march=mips64)
11cflags-$(CONFIG_CPU_XLP) += $(call cc-option,-march=xlp,-march=mips64r2)
11 12
12# 13#
13# NETLOGIC XLR/XLS SoC, Simulator and boards 14# NETLOGIC processor support
14# 15#
15core-$(CONFIG_NLM_XLR) += arch/mips/netlogic/xlr/ 16platform-$(CONFIG_NLM_COMMON) += netlogic/
16load-$(CONFIG_NLM_XLR_BOARD) += 0xffffffff84000000 17load-$(CONFIG_NLM_COMMON) += 0xffffffff80100000
diff --git a/arch/mips/netlogic/common/Makefile b/arch/mips/netlogic/common/Makefile
new file mode 100644
index 000000000000..291372a086f5
--- /dev/null
+++ b/arch/mips/netlogic/common/Makefile
@@ -0,0 +1,3 @@
1obj-y += irq.o time.o
2obj-$(CONFIG_SMP) += smp.o smpboot.o
3obj-$(CONFIG_EARLY_PRINTK) += earlycons.o
diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c
new file mode 100644
index 000000000000..f193f7b3bd81
--- /dev/null
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -0,0 +1,60 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <linux/serial_reg.h>
37
38#include <asm/mipsregs.h>
39#include <asm/netlogic/haldefs.h>
40
41#if defined(CONFIG_CPU_XLP)
42#include <asm/netlogic/xlp-hal/iomap.h>
43#include <asm/netlogic/xlp-hal/uart.h>
44#elif defined(CONFIG_CPU_XLR)
45#include <asm/netlogic/xlr/iomap.h>
46#endif
47
48void prom_putchar(char c)
49{
50 uint64_t uartbase;
51
52#if defined(CONFIG_CPU_XLP)
53 uartbase = nlm_get_uart_regbase(0, 0);
54#elif defined(CONFIG_CPU_XLR)
55 uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
56#endif
57 while (nlm_read_reg(uartbase, UART_LSR) == 0)
58 ;
59 nlm_write_reg(uartbase, UART_TX, c);
60}
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
new file mode 100644
index 000000000000..49a4f6cf71e5
--- /dev/null
+++ b/arch/mips/netlogic/common/irq.c
@@ -0,0 +1,238 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41#include <linux/slab.h>
42#include <linux/irq.h>
43
44#include <asm/errno.h>
45#include <asm/signal.h>
46#include <asm/system.h>
47#include <asm/ptrace.h>
48#include <asm/mipsregs.h>
49#include <asm/thread_info.h>
50
51#include <asm/netlogic/mips-extns.h>
52#include <asm/netlogic/interrupt.h>
53#include <asm/netlogic/haldefs.h>
54#include <asm/netlogic/common.h>
55
56#if defined(CONFIG_CPU_XLP)
57#include <asm/netlogic/xlp-hal/iomap.h>
58#include <asm/netlogic/xlp-hal/xlp.h>
59#include <asm/netlogic/xlp-hal/pic.h>
60#elif defined(CONFIG_CPU_XLR)
61#include <asm/netlogic/xlr/iomap.h>
62#include <asm/netlogic/xlr/pic.h>
63#else
64#error "Unknown CPU"
65#endif
66/*
67 * These are the routines that handle all the low level interrupt stuff.
68 * Actions handled here are: initialization of the interrupt map, requesting of
69 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
70 * for interrupt lines
71 */
72
73/* Globals */
74static uint64_t nlm_irq_mask;
75static DEFINE_SPINLOCK(nlm_pic_lock);
76
77static void xlp_pic_enable(struct irq_data *d)
78{
79 unsigned long flags;
80 int irt;
81
82 irt = nlm_irq_to_irt(d->irq);
83 if (irt == -1)
84 return;
85 spin_lock_irqsave(&nlm_pic_lock, flags);
86 nlm_pic_enable_irt(nlm_pic_base, irt);
87 spin_unlock_irqrestore(&nlm_pic_lock, flags);
88}
89
90static void xlp_pic_disable(struct irq_data *d)
91{
92 unsigned long flags;
93 int irt;
94
95 irt = nlm_irq_to_irt(d->irq);
96 if (irt == -1)
97 return;
98 spin_lock_irqsave(&nlm_pic_lock, flags);
99 nlm_pic_disable_irt(nlm_pic_base, irt);
100 spin_unlock_irqrestore(&nlm_pic_lock, flags);
101}
102
103static void xlp_pic_mask_ack(struct irq_data *d)
104{
105 uint64_t mask = 1ull << d->irq;
106
107 write_c0_eirr(mask); /* ack by writing EIRR */
108}
109
110static void xlp_pic_unmask(struct irq_data *d)
111{
112 void *hd = irq_data_get_irq_handler_data(d);
113 int irt;
114
115 irt = nlm_irq_to_irt(d->irq);
116 if (irt == -1)
117 return;
118
119 if (hd) {
120 void (*extra_ack)(void *) = hd;
121 extra_ack(d);
122 }
123 /* Ack is a single write, no need to lock */
124 nlm_pic_ack(nlm_pic_base, irt);
125}
126
127static struct irq_chip xlp_pic = {
128 .name = "XLP-PIC",
129 .irq_enable = xlp_pic_enable,
130 .irq_disable = xlp_pic_disable,
131 .irq_mask_ack = xlp_pic_mask_ack,
132 .irq_unmask = xlp_pic_unmask,
133};
134
135static void cpuintr_disable(struct irq_data *d)
136{
137 uint64_t eimr;
138 uint64_t mask = 1ull << d->irq;
139
140 eimr = read_c0_eimr();
141 write_c0_eimr(eimr & ~mask);
142}
143
144static void cpuintr_enable(struct irq_data *d)
145{
146 uint64_t eimr;
147 uint64_t mask = 1ull << d->irq;
148
149 eimr = read_c0_eimr();
150 write_c0_eimr(eimr | mask);
151}
152
153static void cpuintr_ack(struct irq_data *d)
154{
155 uint64_t mask = 1ull << d->irq;
156
157 write_c0_eirr(mask);
158}
159
160static void cpuintr_nop(struct irq_data *d)
161{
162 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
163}
164
165/*
166 * Chip definition for CPU originated interrupts(timer, msg) and
167 * IPIs
168 */
169struct irq_chip nlm_cpu_intr = {
170 .name = "XLP-CPU-INTR",
171 .irq_enable = cpuintr_enable,
172 .irq_disable = cpuintr_disable,
173 .irq_mask = cpuintr_nop,
174 .irq_ack = cpuintr_nop,
175 .irq_eoi = cpuintr_ack,
176};
177
178void __init init_nlm_common_irqs(void)
179{
180 int i, irq, irt;
181
182 for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
183 irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
184
185 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ ; i++)
186 irq_set_chip_and_handler(i, &xlp_pic, handle_level_irq);
187
188#ifdef CONFIG_SMP
189 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
190 nlm_smp_function_ipi_handler);
191 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
192 nlm_smp_resched_ipi_handler);
193 nlm_irq_mask |=
194 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
195#endif
196
197 for (irq = PIC_IRT_FIRST_IRQ; irq <= PIC_IRT_LAST_IRQ; irq++) {
198 irt = nlm_irq_to_irt(irq);
199 if (irt == -1)
200 continue;
201 nlm_irq_mask |= (1ULL << irq);
202 nlm_pic_init_irt(nlm_pic_base, irt, irq, 0);
203 }
204
205 nlm_irq_mask |= (1ULL << IRQ_TIMER);
206}
207
208void __init arch_init_irq(void)
209{
210 /* Initialize the irq descriptors */
211 init_nlm_common_irqs();
212
213 write_c0_eimr(nlm_irq_mask);
214}
215
216void __cpuinit nlm_smp_irq_init(void)
217{
218 /* set interrupt mask for non-zero cpus */
219 write_c0_eimr(nlm_irq_mask);
220}
221
222asmlinkage void plat_irq_dispatch(void)
223{
224 uint64_t eirr;
225 int i;
226
227 eirr = read_c0_eirr() & read_c0_eimr();
228 if (eirr & (1 << IRQ_TIMER)) {
229 do_IRQ(IRQ_TIMER);
230 return;
231 }
232
233 i = __ilog2_u64(eirr);
234 if (i == -1)
235 return;
236
237 do_IRQ(i);
238}
diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/common/smp.c
index 080284ded508..db17f49886c2 100644
--- a/arch/mips/netlogic/xlr/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -42,31 +42,29 @@
42 42
43#include <asm/netlogic/interrupt.h> 43#include <asm/netlogic/interrupt.h>
44#include <asm/netlogic/mips-extns.h> 44#include <asm/netlogic/mips-extns.h>
45 45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47
48#if defined(CONFIG_CPU_XLP)
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/xlp.h>
51#include <asm/netlogic/xlp-hal/pic.h>
52#elif defined(CONFIG_CPU_XLR)
46#include <asm/netlogic/xlr/iomap.h> 53#include <asm/netlogic/xlr/iomap.h>
47#include <asm/netlogic/xlr/pic.h> 54#include <asm/netlogic/xlr/pic.h>
48#include <asm/netlogic/xlr/xlr.h> 55#include <asm/netlogic/xlr/xlr.h>
56#else
57#error "Unknown CPU"
58#endif
49 59
50void core_send_ipi(int logical_cpu, unsigned int action) 60void nlm_send_ipi_single(int logical_cpu, unsigned int action)
51{ 61{
52 int cpu = cpu_logical_map(logical_cpu); 62 int cpu = cpu_logical_map(logical_cpu);
53 u32 tid = cpu & 0x3;
54 u32 pid = (cpu >> 2) & 0x07;
55 u32 ipi = (tid << 16) | (pid << 20);
56 63
57 if (action & SMP_CALL_FUNCTION) 64 if (action & SMP_CALL_FUNCTION)
58 ipi |= IRQ_IPI_SMP_FUNCTION; 65 nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_FUNCTION, 0);
59 else if (action & SMP_RESCHEDULE_YOURSELF) 66 if (action & SMP_RESCHEDULE_YOURSELF)
60 ipi |= IRQ_IPI_SMP_RESCHEDULE; 67 nlm_pic_send_ipi(nlm_pic_base, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
61 else
62 return;
63
64 pic_send_ipi(ipi);
65}
66
67void nlm_send_ipi_single(int cpu, unsigned int action)
68{
69 core_send_ipi(cpu, action);
70} 68}
71 69
72void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action) 70void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
@@ -74,29 +72,35 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
74 int cpu; 72 int cpu;
75 73
76 for_each_cpu(cpu, mask) { 74 for_each_cpu(cpu, mask) {
77 core_send_ipi(cpu, action); 75 nlm_send_ipi_single(cpu, action);
78 } 76 }
79} 77}
80 78
81/* IRQ_IPI_SMP_FUNCTION Handler */ 79/* IRQ_IPI_SMP_FUNCTION Handler */
82void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) 80void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
83{ 81{
82 write_c0_eirr(1ull << irq);
84 smp_call_function_interrupt(); 83 smp_call_function_interrupt();
85} 84}
86 85
87/* IRQ_IPI_SMP_RESCHEDULE handler */ 86/* IRQ_IPI_SMP_RESCHEDULE handler */
88void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) 87void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
89{ 88{
89 write_c0_eirr(1ull << irq);
90 scheduler_ipi(); 90 scheduler_ipi();
91} 91}
92 92
93/* 93/*
94 * Called before going into mips code, early cpu init 94 * Called before going into mips code, early cpu init
95 */ 95 */
96void nlm_early_init_secondary(void) 96void nlm_early_init_secondary(int cpu)
97{ 97{
98 change_c0_config(CONF_CM_CMASK, 0x3);
98 write_c0_ebase((uint32_t)nlm_common_ebase); 99 write_c0_ebase((uint32_t)nlm_common_ebase);
99 /* TLB partition here later */ 100#ifdef CONFIG_CPU_XLP
101 if (hard_smp_processor_id() % 4 == 0)
102 xlp_mmu_init();
103#endif
100} 104}
101 105
102/* 106/*
@@ -104,9 +108,16 @@ void nlm_early_init_secondary(void)
104 */ 108 */
105static void __cpuinit nlm_init_secondary(void) 109static void __cpuinit nlm_init_secondary(void)
106{ 110{
111 current_cpu_data.core = hard_smp_processor_id() / 4;
107 nlm_smp_irq_init(); 112 nlm_smp_irq_init();
108} 113}
109 114
115void nlm_prepare_cpus(unsigned int max_cpus)
116{
117 /* declare we are SMT capable */
118 smp_num_siblings = nlm_threads_per_core;
119}
120
110void nlm_smp_finish(void) 121void nlm_smp_finish(void)
111{ 122{
112#ifdef notyet 123#ifdef notyet
@@ -123,10 +134,10 @@ void nlm_cpus_done(void)
123 * Boot all other cpus in the system, initialize them, and bring them into 134 * Boot all other cpus in the system, initialize them, and bring them into
124 * the boot function 135 * the boot function
125 */ 136 */
126int nlm_cpu_unblock[NR_CPUS];
127int nlm_cpu_ready[NR_CPUS]; 137int nlm_cpu_ready[NR_CPUS];
128unsigned long nlm_next_gp; 138unsigned long nlm_next_gp;
129unsigned long nlm_next_sp; 139unsigned long nlm_next_sp;
140
130cpumask_t phys_cpu_present_map; 141cpumask_t phys_cpu_present_map;
131 142
132void nlm_boot_secondary(int logical_cpu, struct task_struct *idle) 143void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
@@ -140,7 +151,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
140 151
141 /* barrier */ 152 /* barrier */
142 __sync(); 153 __sync();
143 nlm_cpu_unblock[cpu] = 1; 154 nlm_pic_send_ipi(nlm_pic_base, cpu, 1, 1);
144} 155}
145 156
146void __init nlm_smp_setup(void) 157void __init nlm_smp_setup(void)
@@ -159,8 +170,8 @@ void __init nlm_smp_setup(void)
159 num_cpus = 1; 170 num_cpus = 1;
160 for (i = 0; i < NR_CPUS; i++) { 171 for (i = 0; i < NR_CPUS; i++) {
161 /* 172 /*
162 * BSP is not set in nlm_cpu_ready array, it is only for 173 * nlm_cpu_ready array is not set for the boot_cpu,
163 * ASPs (goto see smpboot.S) 174 * it is only set for ASPs (see smpboot.S)
164 */ 175 */
165 if (nlm_cpu_ready[i]) { 176 if (nlm_cpu_ready[i]) {
166 cpu_set(i, phys_cpu_present_map); 177 cpu_set(i, phys_cpu_present_map);
@@ -176,10 +187,75 @@ void __init nlm_smp_setup(void)
176 (unsigned long)cpu_possible_map.bits[0]); 187 (unsigned long)cpu_possible_map.bits[0]);
177 188
178 pr_info("Detected %i Slave CPU(s)\n", num_cpus); 189 pr_info("Detected %i Slave CPU(s)\n", num_cpus);
190 nlm_set_nmi_handler(nlm_boot_secondary_cpus);
179} 191}
180 192
181void nlm_prepare_cpus(unsigned int max_cpus) 193static int nlm_parse_cpumask(u32 cpu_mask)
194{
195 uint32_t core0_thr_mask, core_thr_mask;
196 int threadmode, i;
197
198 core0_thr_mask = cpu_mask & 0xf;
199 switch (core0_thr_mask) {
200 case 1:
201 nlm_threads_per_core = 1;
202 threadmode = 0;
203 break;
204 case 3:
205 nlm_threads_per_core = 2;
206 threadmode = 2;
207 break;
208 case 0xf:
209 nlm_threads_per_core = 4;
210 threadmode = 3;
211 break;
212 default:
213 goto unsupp;
214 }
215
216 /* Verify other cores CPU masks */
217 nlm_coremask = 1;
218 nlm_cpumask = core0_thr_mask;
219 for (i = 1; i < 8; i++) {
220 core_thr_mask = (cpu_mask >> (i * 4)) & 0xf;
221 if (core_thr_mask) {
222 if (core_thr_mask != core0_thr_mask)
223 goto unsupp;
224 nlm_coremask |= 1 << i;
225 nlm_cpumask |= core0_thr_mask << (4 * i);
226 }
227 }
228 return threadmode;
229
230unsupp:
231 panic("Unsupported CPU mask %x\n", cpu_mask);
232 return 0;
233}
234
235int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
182{ 236{
237 unsigned long reset_vec;
238 char *reset_data;
239 int threadmode;
240
241 /* Update reset entry point with CPU init code */
242 reset_vec = CKSEG1ADDR(RESET_VEC_PHYS);
243 memcpy((void *)reset_vec, (void *)nlm_reset_entry,
244 (nlm_reset_entry_end - nlm_reset_entry));
245
246 /* verify the mask and setup core config variables */
247 threadmode = nlm_parse_cpumask(wakeup_mask);
248
249 /* Setup CPU init parameters */
250 reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
251 *(int *)(reset_data + BOOT_THREAD_MODE) = threadmode;
252
253#ifdef CONFIG_CPU_XLP
254 xlp_wakeup_secondary_cpus();
255#else
256 xlr_wakeup_secondary_cpus();
257#endif
258 return 0;
183} 259}
184 260
185struct plat_smp_ops nlm_smp_ops = { 261struct plat_smp_ops nlm_smp_ops = {
@@ -192,29 +268,3 @@ struct plat_smp_ops nlm_smp_ops = {
192 .smp_setup = nlm_smp_setup, 268 .smp_setup = nlm_smp_setup,
193 .prepare_cpus = nlm_prepare_cpus, 269 .prepare_cpus = nlm_prepare_cpus,
194}; 270};
195
196unsigned long secondary_entry_point;
197
198int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
199{
200 unsigned int tid, pid, ipi, i, boot_cpu;
201 void *reset_vec;
202
203 secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
204 reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
205 memcpy(reset_vec, nlm_boot_smp_nmi, 0x80);
206 boot_cpu = hard_smp_processor_id();
207
208 for (i = 0; i < NR_CPUS; i++) {
209 if (i == boot_cpu)
210 continue;
211 if (wakeup_mask & (1u << i)) {
212 tid = i & 0x3;
213 pid = (i >> 2) & 0x7;
214 ipi = (tid << 16) | (pid << 20) | (1 << 8);
215 pic_send_ipi(ipi);
216 }
217 }
218
219 return 0;
220}
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
new file mode 100644
index 000000000000..c138b1a6dec3
--- /dev/null
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -0,0 +1,272 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36
37#include <asm/asm.h>
38#include <asm/asm-offsets.h>
39#include <asm/regdef.h>
40#include <asm/mipsregs.h>
41#include <asm/stackframe.h>
42#include <asm/asmmacro.h>
43#include <asm/addrspace.h>
44
45#include <asm/netlogic/common.h>
46
47#include <asm/netlogic/xlp-hal/iomap.h>
48#include <asm/netlogic/xlp-hal/xlp.h>
49#include <asm/netlogic/xlp-hal/sys.h>
50#include <asm/netlogic/xlp-hal/cpucontrol.h>
51
52#define CP0_EBASE $15
53#define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4
56
57.macro __config_lsu
58 li t0, LSU_DEFEATURE
59 mfcr t1, t0
60
61 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
62 or t1, t1, t2
63 li t2, ~0xe /* S1RCM */
64 and t1, t1, t2
65 mtcr t1, t0
66
67 li t0, SCHED_DEFEATURE
68 lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */
69 mtcr t1, t0
70.endm
71
72/*
73 * The cores can come start when they are woken up. This is also the NMI
74 * entry, so check that first.
75 *
76 * The data corresponding to reset is stored at RESET_DATA_PHYS location,
77 * this will have the thread mask (used when core is woken up) and the
78 * current NMI handler in case we reached here for an NMI.
79 *
80 * When a core or thread is newly woken up, it loops in a 'wait'. When
81 * the CPU really needs waking up, we send an NMI to it, with the NMI
82 * handler set to prom_boot_secondary_cpus
83 */
84
85 .set noreorder
86 .set noat
87 .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
88
89FEXPORT(nlm_reset_entry)
90 dmtc0 k0, $22, 6
91 dmtc0 k1, $22, 7
92 mfc0 k0, CP0_STATUS
93 li k1, 0x80000
94 and k1, k0, k1
95 beqz k1, 1f /* go to real reset entry */
96 nop
97 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
98 ld k0, BOOT_NMI_HANDLER(k1)
99 jr k0
100 nop
101
1021: /* Entry point on core wakeup */
103 mfc0 t0, CP0_EBASE, 1
104 mfc0 t1, CP0_EBASE, 1
105 srl t1, 5
106 andi t1, 0x3 /* t1 <- node */
107 li t2, 0x40000
108 mul t3, t2, t1 /* t3 = node * 0x40000 */
109 srl t0, t0, 2
110 and t0, t0, 0x7 /* t0 <- core */
111 li t1, 0x1
112 sll t0, t1, t0
113 nor t0, t0, zero /* t0 <- ~(1 << core) */
114 li t2, SYS_CPU_COHERENT_BASE(0)
115 add t2, t2, t3 /* t2 <- SYS offset for node */
116 lw t1, 0(t2)
117 and t1, t1, t0
118 sw t1, 0(t2)
119
120 /* read back to ensure complete */
121 lw t1, 0(t2)
122 sync
123
124 /* Configure LSU on Non-0 Cores. */
125 __config_lsu
126
127/*
128 * Wake up sibling threads from the initial thread in
129 * a core.
130 */
131EXPORT(nlm_boot_siblings)
132 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
133 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
134 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
135 mfcr t2, t0
136 or t2, t2, t1
137 mtcr t2, t0
138
139 /*
140 * The new hardware thread starts at the next instruction
141 * For all the cases other than core 0 thread 0, we will
142 * jump to the secondary wait function.
143 */
144 mfc0 v0, CP0_EBASE, 1
145 andi v0, 0x7f /* v0 <- node/core */
146
147#if 1
148 /* A0 errata - Write MMU_SETUP after changing thread mode register. */
149 andi v1, v0, 0x3 /* v1 <- thread id */
150 bnez v1, 2f
151 nop
152
153 li t0, MMU_SETUP
154 li t1, 0
155 mtcr t1, t0
156 ehb
157#endif
158
1592: beqz v0, 4f
160 nop
161
162 /* setup status reg */
163 mfc0 t1, CP0_STATUS
164 li t0, ST0_BEV
165 or t1, t0
166 xor t1, t0
167#ifdef CONFIG_64BIT
168 ori t1, ST0_KX
169#endif
170 mtc0 t1, CP0_STATUS
171 /* mark CPU ready */
172 PTR_LA t1, nlm_cpu_ready
173 sll v1, v0, 2
174 PTR_ADDU t1, v1
175 li t2, 1
176 sw t2, 0(t1)
177 /* Wait until NMI hits */
1783: wait
179 j 3b
180 nop
181
182 /*
183 * For the boot CPU, we have to restore registers and
184 * return
185 */
1864: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
187 li t1, 0xfadebeef
188 dmtc0 t1, $4, 2 /* restore SP from UserLocal */
189 PTR_SUBU sp, t0, PT_SIZE
190 RESTORE_ALL
191 jr ra
192 nop
193EXPORT(nlm_reset_entry_end)
194
195FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
196 __config_lsu
197 dmtc0 sp, $4, 2 /* SP saved in UserLocal */
198 SAVE_ALL
199 sync
200 /* find the location to which nlm_boot_siblings was relocated */
201 li t0, CKSEG1ADDR(RESET_VEC_PHYS)
202 dla t1, nlm_reset_entry
203 dla t2, nlm_boot_siblings
204 dsubu t2, t1
205 daddu t2, t0
206 /* call it */
207 jr t2
208 nop
209 /* not reached */
210
211 __CPUINIT
212NESTED(nlm_boot_secondary_cpus, 16, sp)
213 PTR_LA t1, nlm_next_sp
214 PTR_L sp, 0(t1)
215 PTR_LA t1, nlm_next_gp
216 PTR_L gp, 0(t1)
217
218 /* a0 has the processor id */
219 PTR_LA t0, nlm_early_init_secondary
220 jalr t0
221 nop
222
223 PTR_LA t0, smp_bootstrap
224 jr t0
225 nop
226END(nlm_boot_secondary_cpus)
227 __FINIT
228
229/*
230 * In case of RMIboot bootloader which is used on XLR boards, the CPUs
231 * be already woken up and waiting in bootloader code.
232 * This will get them out of the bootloader code and into linux. Needed
233 * because the bootloader area will be taken and initialized by linux.
234 */
235 __CPUINIT
236NESTED(nlm_rmiboot_preboot, 16, sp)
237 mfc0 t0, $15, 1 # read ebase
238 andi t0, 0x1f # t0 has the processor_id()
239 andi t2, t0, 0x3 # thread no
240 sll t0, 2 # offset in cpu array
241
242 PTR_LA t1, nlm_cpu_ready # mark CPU ready
243 PTR_ADDU t1, t0
244 li t3, 1
245 sw t3, 0(t1)
246
247 bnez t2, 1f # skip thread programming
248 nop # for non zero hw threads
249
250 /*
251 * MMU setup only for first thread in core
252 */
253 li t0, 0x400
254 mfcr t1, t0
255 li t2, 6 # XLR thread mode mask
256 nor t3, t2, zero
257 and t2, t1, t2 # t2 - current thread mode
258 li v0, CKSEG1ADDR(RESET_DATA_PHYS)
259 lw v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode
260 sll v1, 1
261 beq v1, t2, 1f # same as request value
262 nop # nothing to do */
263
264 and t2, t1, t3 # mask out old thread mode
265 or t1, t2, v1 # put in new value
266 mtcr t1, t0 # update core control
267
2681: wait
269 j 1b
270 nop
271END(nlm_rmiboot_preboot)
272 __FINIT
diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/common/time.c
index 0d81b262593c..bd3e498157ff 100644
--- a/arch/mips/netlogic/xlr/time.c
+++ b/arch/mips/netlogic/common/time.c
@@ -36,7 +36,7 @@
36 36
37#include <asm/time.h> 37#include <asm/time.h>
38#include <asm/netlogic/interrupt.h> 38#include <asm/netlogic/interrupt.h>
39#include <asm/netlogic/psb-bootinfo.h> 39#include <asm/netlogic/common.h>
40 40
41unsigned int __cpuinit get_c0_compare_int(void) 41unsigned int __cpuinit get_c0_compare_int(void)
42{ 42{
@@ -45,7 +45,7 @@ unsigned int __cpuinit get_c0_compare_int(void)
45 45
46void __init plat_time_init(void) 46void __init plat_time_init(void)
47{ 47{
48 mips_hpt_frequency = nlm_prom_info.cpu_frequency; 48 mips_hpt_frequency = nlm_get_cpu_frequency();
49 pr_info("MIPS counter frequency [%ld]\n", 49 pr_info("MIPS counter frequency [%ld]\n",
50 (unsigned long)mips_hpt_frequency); 50 (unsigned long)mips_hpt_frequency);
51} 51}
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
new file mode 100644
index 000000000000..b93ed83474ec
--- /dev/null
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -0,0 +1,2 @@
1obj-y += setup.o platform.o nlm_hal.o
2obj-$(CONFIG_SMP) += wakeup.o
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
new file mode 100644
index 000000000000..9428e7125fed
--- /dev/null
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <linux/kernel.h>
37#include <linux/mm.h>
38#include <linux/delay.h>
39
40#include <asm/mipsregs.h>
41#include <asm/time.h>
42
43#include <asm/netlogic/haldefs.h>
44#include <asm/netlogic/xlp-hal/iomap.h>
45#include <asm/netlogic/xlp-hal/xlp.h>
46#include <asm/netlogic/xlp-hal/pic.h>
47#include <asm/netlogic/xlp-hal/sys.h>
48
49/* These addresses are computed by the nlm_hal_init() */
50uint64_t nlm_io_base;
51uint64_t nlm_sys_base;
52uint64_t nlm_pic_base;
53
54/* Main initialization */
55void nlm_hal_init(void)
56{
57 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE);
58 nlm_sys_base = nlm_get_sys_regbase(0); /* node 0 */
59 nlm_pic_base = nlm_get_pic_regbase(0); /* node 0 */
60}
61
62int nlm_irq_to_irt(int irq)
63{
64 if (!PIC_IRQ_IS_IRT(irq))
65 return -1;
66
67 switch (irq) {
68 case PIC_UART_0_IRQ:
69 return PIC_IRT_UART_0_INDEX;
70 case PIC_UART_1_IRQ:
71 return PIC_IRT_UART_1_INDEX;
72 default:
73 return -1;
74 }
75}
76
77int nlm_irt_to_irq(int irt)
78{
79 switch (irt) {
80 case PIC_IRT_UART_0_INDEX:
81 return PIC_UART_0_IRQ;
82 case PIC_IRT_UART_1_INDEX:
83 return PIC_UART_1_IRQ;
84 default:
85 return -1;
86 }
87}
88
89unsigned int nlm_get_core_frequency(int core)
90{
91 unsigned int pll_divf, pll_divr, dfs_div, ext_div;
92 unsigned int rstval, dfsval, denom;
93 uint64_t num;
94
95 rstval = nlm_read_sys_reg(nlm_sys_base, SYS_POWER_ON_RESET_CFG);
96 dfsval = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIV_VALUE);
97 pll_divf = ((rstval >> 10) & 0x7f) + 1;
98 pll_divr = ((rstval >> 8) & 0x3) + 1;
99 ext_div = ((rstval >> 30) & 0x3) + 1;
100 dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
101
102 num = 800000000ULL * pll_divf;
103 denom = 3 * pll_divr * ext_div * dfs_div;
104 do_div(num, denom);
105 return (unsigned int)num;
106}
107
108unsigned int nlm_get_cpu_frequency(void)
109{
110 return nlm_get_core_frequency(0);
111}
diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c
new file mode 100644
index 000000000000..1f5e4cba891d
--- /dev/null
+++ b/arch/mips/netlogic/xlp/platform.c
@@ -0,0 +1,108 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/dma-mapping.h>
36#include <linux/kernel.h>
37#include <linux/delay.h>
38#include <linux/init.h>
39#include <linux/platform_device.h>
40#include <linux/serial.h>
41#include <linux/serial_8250.h>
42#include <linux/pci.h>
43#include <linux/serial_reg.h>
44#include <linux/spinlock.h>
45
46#include <asm/time.h>
47#include <asm/addrspace.h>
48#include <asm/netlogic/haldefs.h>
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/xlp.h>
51#include <asm/netlogic/xlp-hal/pic.h>
52#include <asm/netlogic/xlp-hal/uart.h>
53
54static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset)
55{
56 return nlm_read_reg(p->iobase, offset);
57}
58
59static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value)
60{
61 nlm_write_reg(p->iobase, offset, value);
62}
63
64#define PORT(_irq) \
65 { \
66 .irq = _irq, \
67 .regshift = 2, \
68 .iotype = UPIO_MEM32, \
69 .flags = (UPF_SKIP_TEST|UPF_FIXED_TYPE|\
70 UPF_BOOT_AUTOCONF), \
71 .uartclk = XLP_IO_CLK, \
72 .type = PORT_16550A, \
73 .serial_in = nlm_xlp_uart_in, \
74 .serial_out = nlm_xlp_uart_out, \
75 }
76
77static struct plat_serial8250_port xlp_uart_data[] = {
78 PORT(PIC_UART_0_IRQ),
79 PORT(PIC_UART_1_IRQ),
80 {},
81};
82
83static struct platform_device uart_device = {
84 .name = "serial8250",
85 .id = PLAT8250_DEV_PLATFORM,
86 .dev = {
87 .platform_data = xlp_uart_data,
88 },
89};
90
91static int __init nlm_platform_uart_init(void)
92{
93 unsigned long mmio;
94
95 mmio = (unsigned long)nlm_get_uart_regbase(0, 0);
96 xlp_uart_data[0].iobase = mmio;
97 xlp_uart_data[0].membase = (void __iomem *)mmio;
98 xlp_uart_data[0].mapbase = mmio;
99
100 mmio = (unsigned long)nlm_get_uart_regbase(0, 1);
101 xlp_uart_data[1].iobase = mmio;
102 xlp_uart_data[1].membase = (void __iomem *)mmio;
103 xlp_uart_data[1].mapbase = mmio;
104
105 return platform_device_register(&uart_device);
106}
107
108arch_initcall(nlm_platform_uart_init);
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
new file mode 100644
index 000000000000..acb677a1227c
--- /dev/null
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/serial_8250.h>
37#include <linux/pm.h>
38
39#include <asm/reboot.h>
40#include <asm/time.h>
41#include <asm/bootinfo.h>
42
43#include <linux/of_fdt.h>
44
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47
48#include <asm/netlogic/xlp-hal/iomap.h>
49#include <asm/netlogic/xlp-hal/xlp.h>
50#include <asm/netlogic/xlp-hal/sys.h>
51
52unsigned long nlm_common_ebase = 0x0;
53
54/* default to uniprocessor */
55uint32_t nlm_coremask = 1, nlm_cpumask = 1;
56int nlm_threads_per_core = 1;
57
58static void nlm_linux_exit(void)
59{
60 nlm_write_sys_reg(nlm_sys_base, SYS_CHIP_RESET, 1);
61 for ( ; ; )
62 cpu_wait();
63}
64
65void __init plat_mem_setup(void)
66{
67 panic_timeout = 5;
68 _machine_restart = (void (*)(char *))nlm_linux_exit;
69 _machine_halt = nlm_linux_exit;
70 pm_power_off = nlm_linux_exit;
71}
72
73const char *get_system_type(void)
74{
75 return "Netlogic XLP Series";
76}
77
78void __init prom_free_prom_memory(void)
79{
80 /* Nothing yet */
81}
82
83void xlp_mmu_init(void)
84{
85 write_c0_config6(read_c0_config6() | 0x24);
86 current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
87 write_c0_config7(PM_DEFAULT_MASK >>
88 (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
89}
90
91void __init prom_init(void)
92{
93 void *fdtp;
94
95 fdtp = (void *)(long)fw_arg0;
96 xlp_mmu_init();
97 nlm_hal_init();
98 early_init_devtree(fdtp);
99
100 nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
101#ifdef CONFIG_SMP
102 nlm_wakeup_secondary_cpus(0xffffffff);
103 register_smp_ops(&nlm_smp_ops);
104#endif
105}
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
new file mode 100644
index 000000000000..44d923ff3846
--- /dev/null
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -0,0 +1,102 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/init.h>
36#include <linux/kernel.h>
37#include <linux/threads.h>
38
39#include <asm/asm.h>
40#include <asm/asm-offsets.h>
41#include <asm/mipsregs.h>
42#include <asm/addrspace.h>
43#include <asm/string.h>
44
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47#include <asm/netlogic/mips-extns.h>
48
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/pic.h>
51#include <asm/netlogic/xlp-hal/xlp.h>
52#include <asm/netlogic/xlp-hal/sys.h>
53
54static void xlp_enable_secondary_cores(void)
55{
56 uint32_t core, value, coremask, syscoremask;
57 int count;
58
59 /* read cores in reset from SYS block */
60 syscoremask = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
61
62 /* update user specified */
63 nlm_coremask = nlm_coremask & (syscoremask | 1);
64
65 for (core = 1; core < 8; core++) {
66 coremask = 1 << core;
67 if ((nlm_coremask & coremask) == 0)
68 continue;
69
70 /* Enable CPU clock */
71 value = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL);
72 value &= ~coremask;
73 nlm_write_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL, value);
74
75 /* Remove CPU Reset */
76 value = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
77 value &= ~coremask;
78 nlm_write_sys_reg(nlm_sys_base, SYS_CPU_RESET, value);
79
80 /* Poll for CPU to mark itself coherent */
81 count = 100000;
82 do {
83 value = nlm_read_sys_reg(nlm_sys_base,
84 SYS_CPU_NONCOHERENT_MODE);
85 } while ((value & coremask) != 0 && count-- > 0);
86
87 if (count == 0)
88 pr_err("Failed to enable core %d\n", core);
89 }
90}
91
92void xlp_wakeup_secondary_cpus(void)
93{
94 /*
95 * In case of u-boot, the secondaries are in reset
96 * first wakeup core 0 threads
97 */
98 xlp_boot_core0_siblings();
99
100 /* now get other cores out of reset */
101 xlp_enable_secondary_cores();
102}
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index 2dca585dd2f7..f01e4d7a0600 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,5 +1,2 @@
1obj-y += setup.o platform.o irq.o setup.o time.o 1obj-y += setup.o platform.o
2obj-$(CONFIG_SMP) += smp.o smpboot.o 2obj-$(CONFIG_SMP) += wakeup.o
3obj-$(CONFIG_EARLY_PRINTK) += xlr_console.o
4
5ccflags-y += -Werror
diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c
deleted file mode 100644
index 521bb7377eb0..000000000000
--- a/arch/mips/netlogic/xlr/irq.c
+++ /dev/null
@@ -1,300 +0,0 @@
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41
42#include <asm/mipsregs.h>
43
44#include <asm/netlogic/xlr/iomap.h>
45#include <asm/netlogic/xlr/pic.h>
46#include <asm/netlogic/xlr/xlr.h>
47
48#include <asm/netlogic/interrupt.h>
49#include <asm/netlogic/mips-extns.h>
50
51static u64 nlm_irq_mask;
52static DEFINE_SPINLOCK(nlm_pic_lock);
53
54static void xlr_pic_enable(struct irq_data *d)
55{
56 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
57 unsigned long flags;
58 nlm_reg_t reg;
59 int irq = d->irq;
60
61 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
62
63 spin_lock_irqsave(&nlm_pic_lock, flags);
64 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
65 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
66 reg | (1 << 6) | (1 << 30) | (1 << 31));
67 spin_unlock_irqrestore(&nlm_pic_lock, flags);
68}
69
70static void xlr_pic_mask(struct irq_data *d)
71{
72 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
73 unsigned long flags;
74 nlm_reg_t reg;
75 int irq = d->irq;
76
77 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
78
79 spin_lock_irqsave(&nlm_pic_lock, flags);
80 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
81 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
82 reg | (1 << 6) | (1 << 30) | (0 << 31));
83 spin_unlock_irqrestore(&nlm_pic_lock, flags);
84}
85
86#ifdef CONFIG_PCI
87/* Extra ACK needed for XLR on chip PCI controller */
88static void xlr_pci_ack(struct irq_data *d)
89{
90 nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
91
92 netlogic_read_reg(pci_mmio, (0x140 >> 2));
93}
94
95/* Extra ACK needed for XLS on chip PCIe controller */
96static void xls_pcie_ack(struct irq_data *d)
97{
98 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
99
100 switch (d->irq) {
101 case PIC_PCIE_LINK0_IRQ:
102 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
103 break;
104 case PIC_PCIE_LINK1_IRQ:
105 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
106 break;
107 case PIC_PCIE_LINK2_IRQ:
108 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
109 break;
110 case PIC_PCIE_LINK3_IRQ:
111 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
112 break;
113 }
114}
115
116/* For XLS B silicon, the 3,4 PCI interrupts are different */
117static void xls_pcie_ack_b(struct irq_data *d)
118{
119 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
120
121 switch (d->irq) {
122 case PIC_PCIE_LINK0_IRQ:
123 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
124 break;
125 case PIC_PCIE_LINK1_IRQ:
126 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
127 break;
128 case PIC_PCIE_XLSB0_LINK2_IRQ:
129 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
130 break;
131 case PIC_PCIE_XLSB0_LINK3_IRQ:
132 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
133 break;
134 }
135}
136#endif
137
138static void xlr_pic_ack(struct irq_data *d)
139{
140 unsigned long flags;
141 nlm_reg_t *mmio;
142 int irq = d->irq;
143 void *hd = irq_data_get_irq_handler_data(d);
144
145 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
146
147 if (hd) {
148 void (*extra_ack)(void *) = hd;
149 extra_ack(d);
150 }
151 mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
152 spin_lock_irqsave(&nlm_pic_lock, flags);
153 netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
154 spin_unlock_irqrestore(&nlm_pic_lock, flags);
155}
156
157/*
158 * This chip definition handles interrupts routed thru the XLR
159 * hardware PIC, currently IRQs 8-39 are mapped to hardware intr
160 * 0-31 wired the XLR PIC
161 */
162static struct irq_chip xlr_pic = {
163 .name = "XLR-PIC",
164 .irq_enable = xlr_pic_enable,
165 .irq_mask = xlr_pic_mask,
166 .irq_ack = xlr_pic_ack,
167};
168
169static void rsvd_irq_handler(struct irq_data *d)
170{
171 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
172}
173
174/*
175 * Chip definition for CPU originated interrupts(timer, msg) and
176 * IPIs
177 */
178struct irq_chip nlm_cpu_intr = {
179 .name = "XLR-CPU-INTR",
180 .irq_enable = rsvd_irq_handler,
181 .irq_mask = rsvd_irq_handler,
182 .irq_ack = rsvd_irq_handler,
183};
184
185void __init init_xlr_irqs(void)
186{
187 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
188 uint32_t thread_mask = 1;
189 int level, i;
190
191 pr_info("Interrupt thread mask [%x]\n", thread_mask);
192 for (i = 0; i < PIC_NUM_IRTS; i++) {
193 level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
194
195 /* Bind all PIC irqs to boot cpu */
196 netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask);
197
198 /*
199 * Use local scheduling and high polarity for all IRTs
200 * Invalidate all IRTs, by default
201 */
202 netlogic_write_reg(mmio, PIC_IRT_1_BASE + i,
203 (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
204 }
205
206 /* Make all IRQs as level triggered by default */
207 for (i = 0; i < NR_IRQS; i++) {
208 if (PIC_IRQ_IS_IRT(i))
209 irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq);
210 else
211 irq_set_chip_and_handler(i, &nlm_cpu_intr,
212 handle_percpu_irq);
213 }
214#ifdef CONFIG_SMP
215 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
216 nlm_smp_function_ipi_handler);
217 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
218 nlm_smp_resched_ipi_handler);
219 nlm_irq_mask |=
220 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
221#endif
222
223#ifdef CONFIG_PCI
224 /*
225 * For PCI interrupts, we need to ack the PIC controller too, overload
226 * irq handler data to do this
227 */
228 if (nlm_chip_is_xls()) {
229 if (nlm_chip_is_xls_b()) {
230 irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
231 xls_pcie_ack_b);
232 irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
233 xls_pcie_ack_b);
234 irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
235 xls_pcie_ack_b);
236 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
237 xls_pcie_ack_b);
238 } else {
239 irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
240 irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
241 irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
242 irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
243 }
244 } else {
245 /* XLR PCI controller ACK */
246 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
247 }
248#endif
249 /* unmask all PIC related interrupts. If no handler is installed by the
250 * drivers, it'll just ack the interrupt and return
251 */
252 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++)
253 nlm_irq_mask |= (1ULL << i);
254
255 nlm_irq_mask |= (1ULL << IRQ_TIMER);
256}
257
258void __init arch_init_irq(void)
259{
260 /* Initialize the irq descriptors */
261 init_xlr_irqs();
262 write_c0_eimr(nlm_irq_mask);
263}
264
265void __cpuinit nlm_smp_irq_init(void)
266{
267 /* set interrupt mask for non-zero cpus */
268 write_c0_eimr(nlm_irq_mask);
269}
270
271asmlinkage void plat_irq_dispatch(void)
272{
273 uint64_t eirr;
274 int i;
275
276 eirr = read_c0_eirr() & read_c0_eimr();
277 if (!eirr)
278 return;
279
280 /* no need of EIRR here, writing compare clears interrupt */
281 if (eirr & (1 << IRQ_TIMER)) {
282 do_IRQ(IRQ_TIMER);
283 return;
284 }
285
286 /* use dcltz: optimize below code */
287 for (i = 63; i != -1; i--) {
288 if (eirr & (1ULL << i))
289 break;
290 }
291 if (i == -1) {
292 pr_err("no interrupt !!\n");
293 return;
294 }
295
296 /* Ack eirr */
297 write_c0_eirr(1ULL << i);
298
299 do_IRQ(i);
300}
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 609ec2534642..eab64b45dffd 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -15,18 +15,19 @@
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/serial_reg.h> 16#include <linux/serial_reg.h>
17 17
18#include <asm/netlogic/haldefs.h>
18#include <asm/netlogic/xlr/iomap.h> 19#include <asm/netlogic/xlr/iomap.h>
19#include <asm/netlogic/xlr/pic.h> 20#include <asm/netlogic/xlr/pic.h>
20#include <asm/netlogic/xlr/xlr.h> 21#include <asm/netlogic/xlr/xlr.h>
21 22
22unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) 23unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
23{ 24{
24 nlm_reg_t *mmio; 25 uint64_t uartbase;
25 unsigned int value; 26 unsigned int value;
26 27
27 /* XLR uart does not need any mapping of regs */ 28 /* sign extend to 64 bits, if needed */
28 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); 29 uartbase = (uint64_t)(long)p->membase;
29 value = netlogic_read_reg(mmio, 0); 30 value = nlm_read_reg(uartbase, offset);
30 31
31 /* See XLR/XLS errata */ 32 /* See XLR/XLS errata */
32 if (offset == UART_MSR) 33 if (offset == UART_MSR)
@@ -39,10 +40,10 @@ unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset)
39 40
40void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) 41void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
41{ 42{
42 nlm_reg_t *mmio; 43 uint64_t uartbase;
43 44
44 /* XLR uart does not need any mapping of regs */ 45 /* sign extend to 64 bits, if needed */
45 mmio = (nlm_reg_t *)(p->membase + (offset << p->regshift)); 46 uartbase = (uint64_t)(long)p->membase;
46 47
47 /* See XLR/XLS errata */ 48 /* See XLR/XLS errata */
48 if (offset == UART_MSR) 49 if (offset == UART_MSR)
@@ -50,7 +51,7 @@ void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
50 else if (offset == UART_MCR) 51 else if (offset == UART_MCR)
51 value ^= 0x3; 52 value ^= 0x3;
52 53
53 netlogic_write_reg(mmio, 0, value); 54 nlm_write_reg(uartbase, offset, value);
54} 55}
55 56
56#define PORT(_irq) \ 57#define PORT(_irq) \
@@ -82,15 +83,15 @@ static struct platform_device uart_device = {
82 83
83static int __init nlm_uart_init(void) 84static int __init nlm_uart_init(void)
84{ 85{
85 nlm_reg_t *mmio; 86 unsigned long uartbase;
86 87
87 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 88 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
88 xlr_uart_data[0].membase = (void __iomem *)mmio; 89 xlr_uart_data[0].membase = (void __iomem *)uartbase;
89 xlr_uart_data[0].mapbase = CPHYSADDR((unsigned long)mmio); 90 xlr_uart_data[0].mapbase = CPHYSADDR(uartbase);
90 91
91 mmio = netlogic_io_mmio(NETLOGIC_IO_UART_1_OFFSET); 92 uartbase = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_1_OFFSET);
92 xlr_uart_data[1].membase = (void __iomem *)mmio; 93 xlr_uart_data[1].membase = (void __iomem *)uartbase;
93 xlr_uart_data[1].mapbase = CPHYSADDR((unsigned long)mmio); 94 xlr_uart_data[1].mapbase = CPHYSADDR(uartbase);
94 95
95 return platform_device_register(&uart_device); 96 return platform_device_register(&uart_device);
96} 97}
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index cee25ddd0887..c9d066dedc4e 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -39,26 +39,33 @@
39#include <asm/reboot.h> 39#include <asm/reboot.h>
40#include <asm/time.h> 40#include <asm/time.h>
41#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
42#include <asm/smp-ops.h>
43 42
44#include <asm/netlogic/interrupt.h> 43#include <asm/netlogic/interrupt.h>
45#include <asm/netlogic/psb-bootinfo.h> 44#include <asm/netlogic/psb-bootinfo.h>
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
46 47
47#include <asm/netlogic/xlr/xlr.h> 48#include <asm/netlogic/xlr/xlr.h>
48#include <asm/netlogic/xlr/iomap.h> 49#include <asm/netlogic/xlr/iomap.h>
49#include <asm/netlogic/xlr/pic.h> 50#include <asm/netlogic/xlr/pic.h>
50#include <asm/netlogic/xlr/gpio.h> 51#include <asm/netlogic/xlr/gpio.h>
51 52
52unsigned long netlogic_io_base = (unsigned long)(DEFAULT_NETLOGIC_IO_BASE); 53uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE;
53unsigned long nlm_common_ebase = 0x0; 54uint64_t nlm_pic_base;
54struct psb_info nlm_prom_info; 55struct psb_info nlm_prom_info;
55 56
57unsigned long nlm_common_ebase = 0x0;
58
59/* default to uniprocessor */
60uint32_t nlm_coremask = 1, nlm_cpumask = 1;
61int nlm_threads_per_core = 1;
62
56static void __init nlm_early_serial_setup(void) 63static void __init nlm_early_serial_setup(void)
57{ 64{
58 struct uart_port s; 65 struct uart_port s;
59 nlm_reg_t *uart_base; 66 unsigned long uart_base;
60 67
61 uart_base = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET); 68 uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
62 memset(&s, 0, sizeof(s)); 69 memset(&s, 0, sizeof(s));
63 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; 70 s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
64 s.iotype = UPIO_MEM32; 71 s.iotype = UPIO_MEM32;
@@ -67,18 +74,18 @@ static void __init nlm_early_serial_setup(void)
67 s.uartclk = PIC_CLKS_PER_SEC; 74 s.uartclk = PIC_CLKS_PER_SEC;
68 s.serial_in = nlm_xlr_uart_in; 75 s.serial_in = nlm_xlr_uart_in;
69 s.serial_out = nlm_xlr_uart_out; 76 s.serial_out = nlm_xlr_uart_out;
70 s.mapbase = (unsigned long)uart_base; 77 s.mapbase = uart_base;
71 s.membase = (unsigned char __iomem *)uart_base; 78 s.membase = (unsigned char __iomem *)uart_base;
72 early_serial_setup(&s); 79 early_serial_setup(&s);
73} 80}
74 81
75static void nlm_linux_exit(void) 82static void nlm_linux_exit(void)
76{ 83{
77 nlm_reg_t *mmio; 84 uint64_t gpiobase;
78 85
79 mmio = netlogic_io_mmio(NETLOGIC_IO_GPIO_OFFSET); 86 gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
80 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ 87 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
81 netlogic_write_reg(mmio, NETLOGIC_GPIO_SWRESET_REG, 1); 88 nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1);
82 for ( ; ; ) 89 for ( ; ; )
83 cpu_wait(); 90 cpu_wait();
84} 91}
@@ -96,6 +103,11 @@ const char *get_system_type(void)
96 return "Netlogic XLR/XLS Series"; 103 return "Netlogic XLR/XLS Series";
97} 104}
98 105
106unsigned int nlm_get_cpu_frequency(void)
107{
108 return (unsigned int)nlm_prom_info.cpu_frequency;
109}
110
99void __init prom_free_prom_memory(void) 111void __init prom_free_prom_memory(void)
100{ 112{
101 /* Nothing yet */ 113 /* Nothing yet */
@@ -175,6 +187,7 @@ void __init prom_init(void)
175 prom_infop = (struct psb_info *)(long)(int)fw_arg3; 187 prom_infop = (struct psb_info *)(long)(int)fw_arg3;
176 188
177 nlm_prom_info = *prom_infop; 189 nlm_prom_info = *prom_infop;
190 nlm_pic_base = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
178 191
179 nlm_early_serial_setup(); 192 nlm_early_serial_setup();
180 build_arcs_cmdline(argv); 193 build_arcs_cmdline(argv);
diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/wakeup.c
index 8cb7889ce0cc..db5d987d4881 100644
--- a/arch/mips/netlogic/xlr/smpboot.S
+++ b/arch/mips/netlogic/xlr/wakeup.c
@@ -33,68 +33,36 @@
33 */ 33 */
34 34
35#include <linux/init.h> 35#include <linux/init.h>
36#include <linux/threads.h>
36 37
37#include <asm/asm.h> 38#include <asm/asm.h>
38#include <asm/asm-offsets.h> 39#include <asm/asm-offsets.h>
39#include <asm/regdef.h>
40#include <asm/mipsregs.h> 40#include <asm/mipsregs.h>
41#include <asm/addrspace.h>
42#include <asm/string.h>
41 43
42/* 44#include <asm/netlogic/haldefs.h>
43 * Early code for secondary CPUs. This will get them out of the bootloader 45#include <asm/netlogic/common.h>
44 * code and into linux. Needed because the bootloader area will be taken 46#include <asm/netlogic/mips-extns.h>
45 * and initialized by linux.
46 */
47 __CPUINIT
48NESTED(prom_pre_boot_secondary_cpus, 16, sp)
49 .set mips64
50 mfc0 t0, $15, 1 # read ebase
51 andi t0, 0x1f # t0 has the processor_id()
52 sll t0, 2 # offset in cpu array
53
54 PTR_LA t1, nlm_cpu_ready # mark CPU ready
55 PTR_ADDU t1, t0
56 li t2, 1
57 sw t2, 0(t1)
58
59 PTR_LA t1, nlm_cpu_unblock
60 PTR_ADDU t1, t0
611: lw t2, 0(t1) # wait till unblocked
62 beqz t2, 1b
63 nop
64 47
65 PTR_LA t1, nlm_next_sp 48#include <asm/netlogic/xlr/iomap.h>
66 PTR_L sp, 0(t1) 49#include <asm/netlogic/xlr/pic.h>
67 PTR_LA t1, nlm_next_gp
68 PTR_L gp, 0(t1)
69 50
70 PTR_LA t0, nlm_early_init_secondary 51int __cpuinit xlr_wakeup_secondary_cpus(void)
71 jalr t0 52{
72 nop 53 unsigned int i, boot_cpu;
73
74 PTR_LA t0, smp_bootstrap
75 jr t0
76 nop
77END(prom_pre_boot_secondary_cpus)
78 __FINIT
79
80/*
81 * NMI code, used for CPU wakeup, copied to reset entry
82 */
83NESTED(nlm_boot_smp_nmi, 0, sp)
84 .set push
85 .set noat
86 .set mips64
87 .set noreorder
88 54
89 /* Clear the NMI and BEV bits */ 55 /*
90 MFC0 k0, CP0_STATUS 56 * In case of RMI boot, hit with NMI to get the cores
91 li k1, 0xffb7ffff 57 * from bootloader to linux code.
92 and k0, k0, k1 58 */
93 MTC0 k0, CP0_STATUS 59 boot_cpu = hard_smp_processor_id();
60 nlm_set_nmi_handler(nlm_rmiboot_preboot);
61 for (i = 0; i < NR_CPUS; i++) {
62 if (i == boot_cpu || (nlm_cpumask & (1u << i)) == 0)
63 continue;
64 nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
65 }
94 66
95 PTR_LA k1, secondary_entry_point 67 return 0;
96 PTR_L k0, 0(k1) 68}
97 jr k0
98 nop
99 .set pop
100END(nlm_boot_smp_nmi)
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index bb82cbdbc62a..c3ac4b086eb2 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
19obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ 19obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
20 ops-bcm63xx.o 20 ops-bcm63xx.o
21obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o 21obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
22obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
22 23
23# 24#
24# These are still pretty much in the old state, watch, go blind. 25# These are still pretty much in the old state, watch, go blind.
@@ -55,7 +56,7 @@ obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
55obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o 56obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
56obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o 57obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
57obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o 58obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
58obj-$(CONFIG_NLM_XLR) += pci-xlr.o 59obj-$(CONFIG_CPU_XLR) += pci-xlr.o
59 60
60ifdef CONFIG_PCI_MSI 61ifdef CONFIG_PCI_MSI
61obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o 62obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
diff --git a/arch/mips/pci/pci-ath724x.c b/arch/mips/pci/pci-ath724x.c
new file mode 100644
index 000000000000..a4dd24a4130b
--- /dev/null
+++ b/arch/mips/pci/pci-ath724x.c
@@ -0,0 +1,174 @@
1/*
2 * Atheros 724x PCI support
3 *
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11#include <linux/pci.h>
12#include <asm/mach-ath79/pci-ath724x.h>
13
14#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
15#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
16
17#define ATH724X_PCI_DEV_BASE 0x14000000
18#define ATH724X_PCI_MEM_BASE 0x10000000
19#define ATH724X_PCI_MEM_SIZE 0x08000000
20
21static DEFINE_SPINLOCK(ath724x_pci_lock);
22static struct ath724x_pci_data *pci_data;
23static int pci_data_size;
24
25static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
26 int size, uint32_t *value)
27{
28 unsigned long flags, addr, tval, mask;
29
30 if (devfn)
31 return PCIBIOS_DEVICE_NOT_FOUND;
32
33 if (where & (size - 1))
34 return PCIBIOS_BAD_REGISTER_NUMBER;
35
36 spin_lock_irqsave(&ath724x_pci_lock, flags);
37
38 switch (size) {
39 case 1:
40 addr = where & ~3;
41 mask = 0xff000000 >> ((where % 4) * 8);
42 tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
43 tval = tval & ~mask;
44 *value = (tval >> ((4 - (where % 4))*8));
45 break;
46 case 2:
47 addr = where & ~3;
48 mask = 0xffff0000 >> ((where % 4)*8);
49 tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
50 tval = tval & ~mask;
51 *value = (tval >> ((4 - (where % 4))*8));
52 break;
53 case 4:
54 *value = reg_read(ATH724X_PCI_DEV_BASE + where);
55 break;
56 default:
57 spin_unlock_irqrestore(&ath724x_pci_lock, flags);
58
59 return PCIBIOS_BAD_REGISTER_NUMBER;
60 }
61
62 spin_unlock_irqrestore(&ath724x_pci_lock, flags);
63
64 return PCIBIOS_SUCCESSFUL;
65}
66
67static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
68 int size, uint32_t value)
69{
70 unsigned long flags, tval, addr, mask;
71
72 if (devfn)
73 return PCIBIOS_DEVICE_NOT_FOUND;
74
75 if (where & (size - 1))
76 return PCIBIOS_BAD_REGISTER_NUMBER;
77
78 spin_lock_irqsave(&ath724x_pci_lock, flags);
79
80 switch (size) {
81 case 1:
82 addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
83 mask = 0xff000000 >> ((where % 4)*8);
84 tval = reg_read(addr);
85 tval = tval & ~mask;
86 tval |= (value << ((4 - (where % 4))*8)) & mask;
87 reg_write(addr, tval);
88 break;
89 case 2:
90 addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
91 mask = 0xffff0000 >> ((where % 4)*8);
92 tval = reg_read(addr);
93 tval = tval & ~mask;
94 tval |= (value << ((4 - (where % 4))*8)) & mask;
95 reg_write(addr, tval);
96 break;
97 case 4:
98 reg_write((ATH724X_PCI_DEV_BASE + where), value);
99 break;
100 default:
101 spin_unlock_irqrestore(&ath724x_pci_lock, flags);
102
103 return PCIBIOS_BAD_REGISTER_NUMBER;
104 }
105
106 spin_unlock_irqrestore(&ath724x_pci_lock, flags);
107
108 return PCIBIOS_SUCCESSFUL;
109}
110
111static struct pci_ops ath724x_pci_ops = {
112 .read = ath724x_pci_read,
113 .write = ath724x_pci_write,
114};
115
116static struct resource ath724x_io_resource = {
117 .name = "PCI IO space",
118 .start = 0,
119 .end = 0,
120 .flags = IORESOURCE_IO,
121};
122
123static struct resource ath724x_mem_resource = {
124 .name = "PCI memory space",
125 .start = ATH724X_PCI_MEM_BASE,
126 .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
127 .flags = IORESOURCE_MEM,
128};
129
130static struct pci_controller ath724x_pci_controller = {
131 .pci_ops = &ath724x_pci_ops,
132 .io_resource = &ath724x_io_resource,
133 .mem_resource = &ath724x_mem_resource,
134};
135
136void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
137{
138 pci_data = data;
139 pci_data_size = size;
140}
141
142int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
143{
144 unsigned int devfn = dev->devfn;
145 int irq = -1;
146
147 if (devfn > pci_data_size - 1)
148 return irq;
149
150 irq = pci_data[devfn].irq;
151
152 return irq;
153}
154
155int pcibios_plat_dev_init(struct pci_dev *dev)
156{
157 unsigned int devfn = dev->devfn;
158
159 if (devfn > pci_data_size - 1)
160 return PCIBIOS_DEVICE_NOT_FOUND;
161
162 dev->dev.platform_data = pci_data[devfn].pdata;
163
164 return PCIBIOS_SUCCESSFUL;
165}
166
167static int __init ath724x_pcibios_init(void)
168{
169 register_pci_controller(&ath724x_pci_controller);
170
171 return PCIBIOS_SUCCESSFUL;
172}
173
174arch_initcall(ath724x_pcibios_init);
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 82e0fde1dba0..39eb7c417e2f 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -99,7 +99,7 @@ static int __init bcm63xx_pci_init(void)
99 unsigned int mem_size; 99 unsigned int mem_size;
100 u32 val; 100 u32 val;
101 101
102 if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358()) 102 if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
103 return -ENODEV; 103 return -ENODEV;
104 104
105 if (!bcm63xx_pci_enabled) 105 if (!bcm63xx_pci_enabled)
@@ -159,7 +159,7 @@ static int __init bcm63xx_pci_init(void)
159 /* setup PCI to local bus access, used by PCI device to target 159 /* setup PCI to local bus access, used by PCI device to target
160 * local RAM while bus mastering */ 160 * local RAM while bus mastering */
161 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); 161 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
162 if (BCMCPU_IS_6358()) 162 if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
163 val = MPI_SP0_REMAP_ENABLE_MASK; 163 val = MPI_SP0_REMAP_ENABLE_MASK;
164 else 164 else
165 val = 0; 165 val = 0;
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index ed1c54284b8f..52a1ba70b3b6 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -99,7 +99,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
99 */ 99 */
100 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4); 100 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
101 /* Set latency timers for all devices */ 101 /* Set latency timers for all devices */
102 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48); 102 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
103 103
104 /* Enable reporting System errors and parity errors on all devices */ 104 /* Enable reporting System errors and parity errors on all devices */
105 /* Enable parity checking and error reporting */ 105 /* Enable parity checking and error reporting */
@@ -109,7 +109,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
109 109
110 if (dev->subordinate) { 110 if (dev->subordinate) {
111 /* Set latency timers on sub bridges */ 111 /* Set latency timers on sub bridges */
112 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48); 112 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
113 /* More bridge error detection */ 113 /* More bridge error detection */
114 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); 114 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
115 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; 115 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
@@ -121,14 +121,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
121 if (pos) { 121 if (pos) {
122 /* Update Device Control */ 122 /* Update Device Control */
123 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); 123 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
124 /* Correctable Error Reporting */ 124 config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
125 config |= PCI_EXP_DEVCTL_CERE; 125 config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
126 /* Non-Fatal Error Reporting */ 126 config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */
127 config |= PCI_EXP_DEVCTL_NFERE; 127 config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */
128 /* Fatal Error Reporting */
129 config |= PCI_EXP_DEVCTL_FERE;
130 /* Unsupported Request */
131 config |= PCI_EXP_DEVCTL_URRE;
132 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); 128 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
133 } 129 }
134 130
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 38fece16c435..3d701a962ef4 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -36,12 +36,18 @@
36#include <linux/pci.h> 36#include <linux/pci.h>
37#include <linux/kernel.h> 37#include <linux/kernel.h>
38#include <linux/init.h> 38#include <linux/init.h>
39#include <linux/msi.h>
39#include <linux/mm.h> 40#include <linux/mm.h>
41#include <linux/irq.h>
42#include <linux/irqdesc.h>
40#include <linux/console.h> 43#include <linux/console.h>
41 44
42#include <asm/io.h> 45#include <asm/io.h>
43 46
44#include <asm/netlogic/interrupt.h> 47#include <asm/netlogic/interrupt.h>
48#include <asm/netlogic/haldefs.h>
49
50#include <asm/netlogic/xlr/msidef.h>
45#include <asm/netlogic/xlr/iomap.h> 51#include <asm/netlogic/xlr/iomap.h>
46#include <asm/netlogic/xlr/pic.h> 52#include <asm/netlogic/xlr/pic.h>
47#include <asm/netlogic/xlr/xlr.h> 53#include <asm/netlogic/xlr/xlr.h>
@@ -150,7 +156,7 @@ struct pci_controller nlm_pci_controller = {
150 .io_offset = 0x00000000UL, 156 .io_offset = 0x00000000UL,
151}; 157};
152 158
153int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 159static int get_irq_vector(const struct pci_dev *dev)
154{ 160{
155 if (!nlm_chip_is_xls()) 161 if (!nlm_chip_is_xls())
156 return PIC_PCIX_IRQ; /* for XLR just one IRQ*/ 162 return PIC_PCIX_IRQ; /* for XLR just one IRQ*/
@@ -182,6 +188,101 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
182 return 0; 188 return 0;
183} 189}
184 190
191#ifdef CONFIG_PCI_MSI
192void destroy_irq(unsigned int irq)
193{
194 /* nothing to do yet */
195}
196
197void arch_teardown_msi_irq(unsigned int irq)
198{
199 destroy_irq(irq);
200}
201
202int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
203{
204 struct msi_msg msg;
205 int irq, ret;
206
207 irq = get_irq_vector(dev);
208 if (irq <= 0)
209 return 1;
210
211 msg.address_hi = MSI_ADDR_BASE_HI;
212 msg.address_lo = MSI_ADDR_BASE_LO |
213 MSI_ADDR_DEST_MODE_PHYSICAL |
214 MSI_ADDR_REDIRECTION_CPU;
215
216 msg.data = MSI_DATA_TRIGGER_EDGE |
217 MSI_DATA_LEVEL_ASSERT |
218 MSI_DATA_DELIVERY_FIXED;
219
220 ret = irq_set_msi_desc(irq, desc);
221 if (ret < 0) {
222 destroy_irq(irq);
223 return ret;
224 }
225
226 write_msi_msg(irq, &msg);
227 return 0;
228}
229#endif
230
231/* Extra ACK needed for XLR on chip PCI controller */
232static void xlr_pci_ack(struct irq_data *d)
233{
234 uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET);
235
236 nlm_read_reg(pcibase, (0x140 >> 2));
237}
238
239/* Extra ACK needed for XLS on chip PCIe controller */
240static void xls_pcie_ack(struct irq_data *d)
241{
242 uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
243
244 switch (d->irq) {
245 case PIC_PCIE_LINK0_IRQ:
246 nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
247 break;
248 case PIC_PCIE_LINK1_IRQ:
249 nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
250 break;
251 case PIC_PCIE_LINK2_IRQ:
252 nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
253 break;
254 case PIC_PCIE_LINK3_IRQ:
255 nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
256 break;
257 }
258}
259
260/* For XLS B silicon, the 3,4 PCI interrupts are different */
261static void xls_pcie_ack_b(struct irq_data *d)
262{
263 uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
264
265 switch (d->irq) {
266 case PIC_PCIE_LINK0_IRQ:
267 nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
268 break;
269 case PIC_PCIE_LINK1_IRQ:
270 nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
271 break;
272 case PIC_PCIE_XLSB0_LINK2_IRQ:
273 nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
274 break;
275 case PIC_PCIE_XLSB0_LINK3_IRQ:
276 nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
277 break;
278 }
279}
280
281int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
282{
283 return get_irq_vector(dev);
284}
285
185/* Do platform specific device initialization at pci_enable_device() time */ 286/* Do platform specific device initialization at pci_enable_device() time */
186int pcibios_plat_dev_init(struct pci_dev *dev) 287int pcibios_plat_dev_init(struct pci_dev *dev)
187{ 288{
@@ -204,6 +305,31 @@ static int __init pcibios_init(void)
204 pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n"); 305 pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n");
205 register_pci_controller(&nlm_pci_controller); 306 register_pci_controller(&nlm_pci_controller);
206 307
308 /*
309 * For PCI interrupts, we need to ack the PCI controller too, overload
310 * irq handler data to do this
311 */
312 if (nlm_chip_is_xls()) {
313 if (nlm_chip_is_xls_b()) {
314 irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
315 xls_pcie_ack_b);
316 irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
317 xls_pcie_ack_b);
318 irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
319 xls_pcie_ack_b);
320 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
321 xls_pcie_ack_b);
322 } else {
323 irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
324 irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
325 irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
326 irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
327 }
328 } else {
329 /* XLR PCI controller ACK */
330 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
331 }
332
207 return 0; 333 return 0;
208} 334}
209 335
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 0583c463e5f1..fdb4d558c0cc 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2007, 2008 Cavium Networks 6 * Copyright (C) 2007, 2008, 2009, 2010, 2011 Cavium Networks
7 */ 7 */
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/init.h> 9#include <linux/init.h>
@@ -11,15 +11,32 @@
11#include <linux/interrupt.h> 11#include <linux/interrupt.h>
12#include <linux/time.h> 12#include <linux/time.h>
13#include <linux/delay.h> 13#include <linux/delay.h>
14#include <linux/module.h>
14 15
15#include <asm/octeon/octeon.h> 16#include <asm/octeon/octeon.h>
16#include <asm/octeon/cvmx-npei-defs.h> 17#include <asm/octeon/cvmx-npei-defs.h>
17#include <asm/octeon/cvmx-pciercx-defs.h> 18#include <asm/octeon/cvmx-pciercx-defs.h>
18#include <asm/octeon/cvmx-pescx-defs.h> 19#include <asm/octeon/cvmx-pescx-defs.h>
19#include <asm/octeon/cvmx-pexp-defs.h> 20#include <asm/octeon/cvmx-pexp-defs.h>
21#include <asm/octeon/cvmx-pemx-defs.h>
22#include <asm/octeon/cvmx-dpi-defs.h>
23#include <asm/octeon/cvmx-sli-defs.h>
24#include <asm/octeon/cvmx-sriox-defs.h>
20#include <asm/octeon/cvmx-helper-errata.h> 25#include <asm/octeon/cvmx-helper-errata.h>
21#include <asm/octeon/pci-octeon.h> 26#include <asm/octeon/pci-octeon.h>
22 27
28#define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
29#define MPS_CN5XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
30#define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
31#define MPS_CN6XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
32
33/* Module parameter to disable PCI probing */
34static int pcie_disable;
35module_param(pcie_disable, int, S_IRUGO);
36
37static int enable_pcie_14459_war;
38static int enable_pcie_bus_num_war[2];
39
23union cvmx_pcie_address { 40union cvmx_pcie_address {
24 uint64_t u64; 41 uint64_t u64;
25 struct { 42 struct {
@@ -75,6 +92,8 @@ union cvmx_pcie_address {
75 } mem; 92 } mem;
76}; 93};
77 94
95static int cvmx_pcie_rc_initialize(int pcie_port);
96
78#include <dma-coherence.h> 97#include <dma-coherence.h>
79 98
80/** 99/**
@@ -154,12 +173,21 @@ static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
154 */ 173 */
155static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset) 174static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
156{ 175{
157 union cvmx_pescx_cfg_rd pescx_cfg_rd; 176 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
158 pescx_cfg_rd.u64 = 0; 177 union cvmx_pescx_cfg_rd pescx_cfg_rd;
159 pescx_cfg_rd.s.addr = cfg_offset; 178 pescx_cfg_rd.u64 = 0;
160 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64); 179 pescx_cfg_rd.s.addr = cfg_offset;
161 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port)); 180 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
162 return pescx_cfg_rd.s.data; 181 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
182 return pescx_cfg_rd.s.data;
183 } else {
184 union cvmx_pemx_cfg_rd pemx_cfg_rd;
185 pemx_cfg_rd.u64 = 0;
186 pemx_cfg_rd.s.addr = cfg_offset;
187 cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
188 pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));
189 return pemx_cfg_rd.s.data;
190 }
163} 191}
164 192
165/** 193/**
@@ -173,11 +201,19 @@ static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
173static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, 201static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
174 uint32_t val) 202 uint32_t val)
175{ 203{
176 union cvmx_pescx_cfg_wr pescx_cfg_wr; 204 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
177 pescx_cfg_wr.u64 = 0; 205 union cvmx_pescx_cfg_wr pescx_cfg_wr;
178 pescx_cfg_wr.s.addr = cfg_offset; 206 pescx_cfg_wr.u64 = 0;
179 pescx_cfg_wr.s.data = val; 207 pescx_cfg_wr.s.addr = cfg_offset;
180 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64); 208 pescx_cfg_wr.s.data = val;
209 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
210 } else {
211 union cvmx_pemx_cfg_wr pemx_cfg_wr;
212 pemx_cfg_wr.u64 = 0;
213 pemx_cfg_wr.s.addr = cfg_offset;
214 pemx_cfg_wr.s.data = val;
215 cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
216 }
181} 217}
182 218
183/** 219/**
@@ -348,7 +384,6 @@ static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
348static void __cvmx_pcie_rc_initialize_config_space(int pcie_port) 384static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
349{ 385{
350 union cvmx_pciercx_cfg030 pciercx_cfg030; 386 union cvmx_pciercx_cfg030 pciercx_cfg030;
351 union cvmx_npei_ctl_status2 npei_ctl_status2;
352 union cvmx_pciercx_cfg070 pciercx_cfg070; 387 union cvmx_pciercx_cfg070 pciercx_cfg070;
353 union cvmx_pciercx_cfg001 pciercx_cfg001; 388 union cvmx_pciercx_cfg001 pciercx_cfg001;
354 union cvmx_pciercx_cfg032 pciercx_cfg032; 389 union cvmx_pciercx_cfg032 pciercx_cfg032;
@@ -365,21 +400,21 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
365 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */ 400 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
366 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */ 401 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
367 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */ 402 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
368 pciercx_cfg030.u32 = 403
369 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port)); 404 pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
370 /* 405 if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
371 * Max payload size = 128 bytes for best Octeon DMA 406 pciercx_cfg030.s.mps = MPS_CN5XXX;
372 * performance. 407 pciercx_cfg030.s.mrrs = MRRS_CN5XXX;
373 */ 408 } else {
374 pciercx_cfg030.s.mps = 0; 409 pciercx_cfg030.s.mps = MPS_CN6XXX;
410 pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
411 }
375 /* 412 /*
376 * Max read request size = 128 bytes for best Octeon DMA 413 * Enable relaxed order processing. This will allow devices to
377 * performance. 414 * affect read response ordering.
378 */ 415 */
379 pciercx_cfg030.s.mrrs = 0;
380 /* Enable relaxed ordering. */
381 pciercx_cfg030.s.ro_en = 1; 416 pciercx_cfg030.s.ro_en = 1;
382 /* Enable no snoop. */ 417 /* Enable no snoop processing. Not used by Octeon */
383 pciercx_cfg030.s.ns_en = 1; 418 pciercx_cfg030.s.ns_en = 1;
384 /* Correctable error reporting enable. */ 419 /* Correctable error reporting enable. */
385 pciercx_cfg030.s.ce_en = 1; 420 pciercx_cfg030.s.ce_en = 1;
@@ -389,50 +424,67 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
389 pciercx_cfg030.s.fe_en = 1; 424 pciercx_cfg030.s.fe_en = 1;
390 /* Unsupported request reporting enable. */ 425 /* Unsupported request reporting enable. */
391 pciercx_cfg030.s.ur_en = 1; 426 pciercx_cfg030.s.ur_en = 1;
392 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), 427 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
393 pciercx_cfg030.u32);
394 428
395 /* 429
396 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match 430 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
397 * PCIE*_CFG030[MPS] 431 union cvmx_npei_ctl_status2 npei_ctl_status2;
398 * 432 /*
399 * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not 433 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
400 * exceed PCIE*_CFG030[MRRS]. 434 * PCIE*_CFG030[MPS]. Max Read Request Size
401 */ 435 * (NPEI_CTL_STATUS2[MRRS]) must not exceed
402 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2); 436 * PCIE*_CFG030[MRRS]
403 /* Max payload size = 128 bytes for best Octeon DMA performance */ 437 */
404 npei_ctl_status2.s.mps = 0; 438 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
405 /* Max read request size = 128 bytes for best Octeon DMA performance */ 439 /* Max payload size = 128 bytes for best Octeon DMA performance */
406 npei_ctl_status2.s.mrrs = 0; 440 npei_ctl_status2.s.mps = MPS_CN5XXX;
407 if (pcie_port) 441 /* Max read request size = 128 bytes for best Octeon DMA performance */
408 npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */ 442 npei_ctl_status2.s.mrrs = MRRS_CN5XXX;
409 else 443 if (pcie_port)
410 npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */ 444 npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
411 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64); 445 else
446 npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
447
448 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
449 } else {
450 /*
451 * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
452 * PCIE*_CFG030[MPS]. Max Read Request Size
453 * (DPI_SLI_PRTX_CFG[MRRS]) must not exceed
454 * PCIE*_CFG030[MRRS].
455 */
456 union cvmx_dpi_sli_prtx_cfg prt_cfg;
457 union cvmx_sli_s2m_portx_ctl sli_s2m_portx_ctl;
458 prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
459 prt_cfg.s.mps = MPS_CN6XXX;
460 prt_cfg.s.mrrs = MRRS_CN6XXX;
461 /* Max outstanding load request. */
462 prt_cfg.s.molr = 32;
463 cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
464
465 sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
466 sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
467 cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
468 }
412 469
413 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */ 470 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
414 pciercx_cfg070.u32 = 471 pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
415 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
416 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */ 472 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
417 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */ 473 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
418 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), 474 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
419 pciercx_cfg070.u32);
420 475
421 /* 476 /*
422 * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should 477 * Access Enables (PCIE*_CFG001[MSAE,ME])
423 * always be set. 478 * ME and MSAE should always be set.
424 * 479 * Interrupt Disable (PCIE*_CFG001[I_DIS])
425 * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error 480 * System Error Message Enable (PCIE*_CFG001[SEE])
426 * Message Enable (PCIE*_CFG001[SEE])
427 */ 481 */
428 pciercx_cfg001.u32 = 482 pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
429 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
430 pciercx_cfg001.s.msae = 1; /* Memory space enable. */ 483 pciercx_cfg001.s.msae = 1; /* Memory space enable. */
431 pciercx_cfg001.s.me = 1; /* Bus master enable. */ 484 pciercx_cfg001.s.me = 1; /* Bus master enable. */
432 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */ 485 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
433 pciercx_cfg001.s.see = 1; /* SERR# enable */ 486 pciercx_cfg001.s.see = 1; /* SERR# enable */
434 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), 487 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
435 pciercx_cfg001.u32);
436 488
437 /* Advanced Error Recovery Message Enables */ 489 /* Advanced Error Recovery Message Enables */
438 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */ 490 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
@@ -440,14 +492,11 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
440 /* Use CVMX_PCIERCX_CFG067 hardware default */ 492 /* Use CVMX_PCIERCX_CFG067 hardware default */
441 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0); 493 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
442 494
443 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
444 pciercx_cfg032.u32 =
445 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
446 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
447 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
448 pciercx_cfg032.u32);
449 495
450 /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */ 496 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
497 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
498 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
499 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
451 500
452 /* 501 /*
453 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during 502 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
@@ -462,8 +511,8 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
462 pciercx_cfg006.s.pbnum = 1; 511 pciercx_cfg006.s.pbnum = 1;
463 pciercx_cfg006.s.sbnum = 1; 512 pciercx_cfg006.s.sbnum = 1;
464 pciercx_cfg006.s.subbnum = 1; 513 pciercx_cfg006.s.subbnum = 1;
465 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), 514 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
466 pciercx_cfg006.u32); 515
467 516
468 /* 517 /*
469 * Memory-mapped I/O BAR (PCIERCn_CFG008) 518 * Memory-mapped I/O BAR (PCIERCn_CFG008)
@@ -473,8 +522,8 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
473 pciercx_cfg008.u32 = 0; 522 pciercx_cfg008.u32 = 0;
474 pciercx_cfg008.s.mb_addr = 0x100; 523 pciercx_cfg008.s.mb_addr = 0x100;
475 pciercx_cfg008.s.ml_addr = 0; 524 pciercx_cfg008.s.ml_addr = 0;
476 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), 525 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
477 pciercx_cfg008.u32); 526
478 527
479 /* 528 /*
480 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011) 529 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
@@ -482,72 +531,51 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
482 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] < 531 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
483 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE] 532 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
484 */ 533 */
485 pciercx_cfg009.u32 = 534 pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
486 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port)); 535 pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
487 pciercx_cfg010.u32 = 536 pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
488 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
489 pciercx_cfg011.u32 =
490 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
491 pciercx_cfg009.s.lmem_base = 0x100; 537 pciercx_cfg009.s.lmem_base = 0x100;
492 pciercx_cfg009.s.lmem_limit = 0; 538 pciercx_cfg009.s.lmem_limit = 0;
493 pciercx_cfg010.s.umem_base = 0x100; 539 pciercx_cfg010.s.umem_base = 0x100;
494 pciercx_cfg011.s.umem_limit = 0; 540 pciercx_cfg011.s.umem_limit = 0;
495 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), 541 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
496 pciercx_cfg009.u32); 542 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
497 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), 543 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
498 pciercx_cfg010.u32);
499 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
500 pciercx_cfg011.u32);
501 544
502 /* 545 /*
503 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE]) 546 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
504 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE]) 547 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
505 */ 548 */
506 pciercx_cfg035.u32 = 549 pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
507 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port)); 550 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
508 /* System error on correctable error enable. */ 551 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
509 pciercx_cfg035.s.secee = 1; 552 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
510 /* System error on fatal error enable. */ 553 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
511 pciercx_cfg035.s.sefee = 1; 554 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
512 /* System error on non-fatal error enable. */
513 pciercx_cfg035.s.senfee = 1;
514 /* PME interrupt enable. */
515 pciercx_cfg035.s.pmeie = 1;
516 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
517 pciercx_cfg035.u32);
518 555
519 /* 556 /*
520 * Advanced Error Recovery Interrupt Enables 557 * Advanced Error Recovery Interrupt Enables
521 * (PCIERCn_CFG075[CERE,NFERE,FERE]) 558 * (PCIERCn_CFG075[CERE,NFERE,FERE])
522 */ 559 */
523 pciercx_cfg075.u32 = 560 pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
524 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port)); 561 pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
525 /* Correctable error reporting enable. */ 562 pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
526 pciercx_cfg075.s.cere = 1; 563 pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
527 /* Non-fatal error reporting enable. */ 564 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
528 pciercx_cfg075.s.nfere = 1;
529 /* Fatal error reporting enable. */
530 pciercx_cfg075.s.fere = 1;
531 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
532 pciercx_cfg075.u32);
533 565
534 /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN], 566 /*
567 * HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
535 * PCIERCn_CFG034[DLLS_EN,CCINT_EN]) 568 * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
536 */ 569 */
537 pciercx_cfg034.u32 = 570 pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
538 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port)); 571 pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
539 /* Hot-plug interrupt enable. */ 572 pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
540 pciercx_cfg034.s.hpint_en = 1; 573 pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
541 /* Data Link Layer state changed enable */ 574 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
542 pciercx_cfg034.s.dlls_en = 1;
543 /* Command completed interrupt enable. */
544 pciercx_cfg034.s.ccint_en = 1;
545 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
546 pciercx_cfg034.u32);
547} 575}
548 576
549/** 577/**
550 * Initialize a host mode PCIe link. This function takes a PCIe 578 * Initialize a host mode PCIe gen 1 link. This function takes a PCIe
551 * port from reset to a link up state. Software can then begin 579 * port from reset to a link up state. Software can then begin
552 * configuring the rest of the link. 580 * configuring the rest of the link.
553 * 581 *
@@ -555,7 +583,7 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
555 * 583 *
556 * Returns Zero on success 584 * Returns Zero on success
557 */ 585 */
558static int __cvmx_pcie_rc_initialize_link(int pcie_port) 586static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
559{ 587{
560 uint64_t start_cycle; 588 uint64_t start_cycle;
561 union cvmx_pescx_ctl_status pescx_ctl_status; 589 union cvmx_pescx_ctl_status pescx_ctl_status;
@@ -564,18 +592,15 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
564 union cvmx_pciercx_cfg448 pciercx_cfg448; 592 union cvmx_pciercx_cfg448 pciercx_cfg448;
565 593
566 /* Set the lane width */ 594 /* Set the lane width */
567 pciercx_cfg452.u32 = 595 pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
568 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
569 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port)); 596 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
570 if (pescx_ctl_status.s.qlm_cfg == 0) { 597 if (pescx_ctl_status.s.qlm_cfg == 0)
571 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */ 598 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
572 pciercx_cfg452.s.lme = 0xf; 599 pciercx_cfg452.s.lme = 0xf;
573 } else { 600 else
574 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */ 601 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
575 pciercx_cfg452.s.lme = 0x7; 602 pciercx_cfg452.s.lme = 0x7;
576 } 603 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), pciercx_cfg452.u32);
577 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
578 pciercx_cfg452.u32);
579 604
580 /* 605 /*
581 * CN52XX pass 1.x has an errata where length mismatches on UR 606 * CN52XX pass 1.x has an errata where length mismatches on UR
@@ -584,19 +609,15 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
584 */ 609 */
585 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { 610 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
586 union cvmx_pciercx_cfg455 pciercx_cfg455; 611 union cvmx_pciercx_cfg455 pciercx_cfg455;
587 pciercx_cfg455.u32 = 612 pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG455(pcie_port));
588 cvmx_pcie_cfgx_read(pcie_port,
589 CVMX_PCIERCX_CFG455(pcie_port));
590 pciercx_cfg455.s.m_cpl_len_err = 1; 613 pciercx_cfg455.s.m_cpl_len_err = 1;
591 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), 614 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), pciercx_cfg455.u32);
592 pciercx_cfg455.u32);
593 } 615 }
594 616
595 /* Lane swap needs to be manually enabled for CN52XX */ 617 /* Lane swap needs to be manually enabled for CN52XX */
596 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) { 618 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
597 pescx_ctl_status.s.lane_swp = 1; 619 pescx_ctl_status.s.lane_swp = 1;
598 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), 620 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
599 pescx_ctl_status.u64);
600 } 621 }
601 622
602 /* Bring up the link */ 623 /* Bring up the link */
@@ -612,24 +633,18 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
612 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0); 633 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
613 634
614 /* Wait for the link to come up */ 635 /* Wait for the link to come up */
615 cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
616 start_cycle = cvmx_get_cycle(); 636 start_cycle = cvmx_get_cycle();
617 do { 637 do {
618 if (cvmx_get_cycle() - start_cycle > 638 if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) {
619 2 * cvmx_sysinfo_get()->cpu_clock_hz) { 639 cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
620 cvmx_dprintf("PCIe: Port %d link timeout\n",
621 pcie_port);
622 return -1; 640 return -1;
623 } 641 }
624 cvmx_wait(10000); 642 cvmx_wait(10000);
625 pciercx_cfg032.u32 = 643 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
626 cvmx_pcie_cfgx_read(pcie_port,
627 CVMX_PCIERCX_CFG032(pcie_port));
628 } while (pciercx_cfg032.s.dlla == 0); 644 } while (pciercx_cfg032.s.dlla == 0);
629 645
630 /* Display the link status */ 646 /* Clear all pending errors */
631 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, 647 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
632 pciercx_cfg032.s.nlw);
633 648
634 /* 649 /*
635 * Update the Replay Time Limit. Empirically, some PCIe 650 * Update the Replay Time Limit. Empirically, some PCIe
@@ -639,8 +654,7 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
639 * our actual 256 byte MPS. The numbers below are directly 654 * our actual 256 byte MPS. The numbers below are directly
640 * from the PCIe spec table 3-4. 655 * from the PCIe spec table 3-4.
641 */ 656 */
642 pciercx_cfg448.u32 = 657 pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
643 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
644 switch (pciercx_cfg032.s.nlw) { 658 switch (pciercx_cfg032.s.nlw) {
645 case 1: /* 1 lane */ 659 case 1: /* 1 lane */
646 pciercx_cfg448.s.rtl = 1677; 660 pciercx_cfg448.s.rtl = 1677;
@@ -655,21 +669,28 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
655 pciercx_cfg448.s.rtl = 258; 669 pciercx_cfg448.s.rtl = 258;
656 break; 670 break;
657 } 671 }
658 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), 672 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
659 pciercx_cfg448.u32);
660 673
661 return 0; 674 return 0;
662} 675}
663 676
677static void __cvmx_increment_ba(union cvmx_sli_mem_access_subidx *pmas)
678{
679 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
680 pmas->cn68xx.ba++;
681 else
682 pmas->cn63xx.ba++;
683}
684
664/** 685/**
665 * Initialize a PCIe port for use in host(RC) mode. It doesn't 686 * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't
666 * enumerate the bus. 687 * enumerate the bus.
667 * 688 *
668 * @pcie_port: PCIe port to initialize 689 * @pcie_port: PCIe port to initialize
669 * 690 *
670 * Returns Zero on success 691 * Returns Zero on success
671 */ 692 */
672static int cvmx_pcie_rc_initialize(int pcie_port) 693static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
673{ 694{
674 int i; 695 int i;
675 int base; 696 int base;
@@ -682,16 +703,17 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
682 union cvmx_npei_mem_access_subidx mem_access_subid; 703 union cvmx_npei_mem_access_subidx mem_access_subid;
683 union cvmx_npei_dbg_data npei_dbg_data; 704 union cvmx_npei_dbg_data npei_dbg_data;
684 union cvmx_pescx_ctl_status2 pescx_ctl_status2; 705 union cvmx_pescx_ctl_status2 pescx_ctl_status2;
706 union cvmx_pciercx_cfg032 pciercx_cfg032;
685 union cvmx_npei_bar1_indexx bar1_index; 707 union cvmx_npei_bar1_indexx bar1_index;
686 708
709retry:
687 /* 710 /*
688 * Make sure we aren't trying to setup a target mode interface 711 * Make sure we aren't trying to setup a target mode interface
689 * in host mode. 712 * in host mode.
690 */ 713 */
691 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); 714 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
692 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) { 715 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
693 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called " 716 cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port);
694 "on port0, but port0 is not in host mode\n");
695 return -1; 717 return -1;
696 } 718 }
697 719
@@ -702,9 +724,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
702 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { 724 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
703 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); 725 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
704 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) { 726 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
705 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() " 727 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n");
706 "called on port1, but port1 is "
707 "disabled\n");
708 return -1; 728 return -1;
709 } 729 }
710 } 730 }
@@ -733,7 +753,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
733 * the board. As a workaround for this bug, we bring 753 * the board. As a workaround for this bug, we bring
734 * both PCIe ports out of reset at the same time 754 * both PCIe ports out of reset at the same time
735 * instead of on separate calls. So for port 0, we 755 * instead of on separate calls. So for port 0, we
736 * bring both out of reset and do nothing on port 1. 756 * bring both out of reset and do nothing on port 1
737 */ 757 */
738 if (pcie_port == 0) { 758 if (pcie_port == 0) {
739 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST); 759 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
@@ -746,13 +766,10 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
746 if (ciu_soft_prst.s.soft_prst == 0) { 766 if (ciu_soft_prst.s.soft_prst == 0) {
747 /* Reset the ports */ 767 /* Reset the ports */
748 ciu_soft_prst.s.soft_prst = 1; 768 ciu_soft_prst.s.soft_prst = 1;
749 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 769 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
750 ciu_soft_prst.u64); 770 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
751 ciu_soft_prst.u64 =
752 cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
753 ciu_soft_prst.s.soft_prst = 1; 771 ciu_soft_prst.s.soft_prst = 1;
754 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, 772 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
755 ciu_soft_prst.u64);
756 /* Wait until pcie resets the ports. */ 773 /* Wait until pcie resets the ports. */
757 udelay(2000); 774 udelay(2000);
758 } 775 }
@@ -782,11 +799,9 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
782 /* Reset the port */ 799 /* Reset the port */
783 ciu_soft_prst.s.soft_prst = 1; 800 ciu_soft_prst.s.soft_prst = 1;
784 if (pcie_port) 801 if (pcie_port)
785 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, 802 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
786 ciu_soft_prst.u64);
787 else 803 else
788 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 804 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
789 ciu_soft_prst.u64);
790 /* Wait until pcie resets the ports. */ 805 /* Wait until pcie resets the ports. */
791 udelay(2000); 806 udelay(2000);
792 } 807 }
@@ -808,25 +823,21 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
808 */ 823 */
809 cvmx_wait(400000); 824 cvmx_wait(400000);
810 825
811 /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and 826 /*
812 CN52XX, so we only probe it on newer chips */ 827 * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
813 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) 828 * CN56XX and CN52XX, so we only probe it on newer chips
814 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { 829 */
830 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
815 /* Clear PCLK_RUN so we can check if the clock is running */ 831 /* Clear PCLK_RUN so we can check if the clock is running */
816 pescx_ctl_status2.u64 = 832 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
817 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
818 pescx_ctl_status2.s.pclk_run = 1; 833 pescx_ctl_status2.s.pclk_run = 1;
819 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), 834 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);
820 pescx_ctl_status2.u64); 835 /* Now that we cleared PCLK_RUN, wait for it to be set
821 /* 836 * again telling us the clock is running
822 * Now that we cleared PCLK_RUN, wait for it to be set
823 * again telling us the clock is running.
824 */ 837 */
825 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port), 838 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
826 union cvmx_pescx_ctl_status2, 839 union cvmx_pescx_ctl_status2, pclk_run, ==, 1, 10000)) {
827 pclk_run, ==, 1, 10000)) { 840 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port);
828 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
829 pcie_port);
830 return -1; 841 return -1;
831 } 842 }
832 } 843 }
@@ -836,30 +847,26 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
836 * the board probably hasn't wired the clocks up and the 847 * the board probably hasn't wired the clocks up and the
837 * interface should be skipped. 848 * interface should be skipped.
838 */ 849 */
839 pescx_ctl_status2.u64 = 850 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
840 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
841 if (pescx_ctl_status2.s.pcierst) { 851 if (pescx_ctl_status2.s.pcierst) {
842 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", 852 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
843 pcie_port);
844 return -1; 853 return -1;
845 } 854 }
846 855
847 /* 856 /*
848 * Check BIST2 status. If any bits are set skip this interface. This 857 * Check BIST2 status. If any bits are set skip this
849 * is an attempt to catch PCIE-813 on pass 1 parts. 858 * interface. This is an attempt to catch PCIE-813 on pass 1
859 * parts.
850 */ 860 */
851 pescx_bist_status2.u64 = 861 pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
852 cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
853 if (pescx_bist_status2.u64) { 862 if (pescx_bist_status2.u64) {
854 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this " 863 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n",
855 "port isn't hooked up, skipping.\n",
856 pcie_port); 864 pcie_port);
857 return -1; 865 return -1;
858 } 866 }
859 867
860 /* Check BIST status */ 868 /* Check BIST status */
861 pescx_bist_status.u64 = 869 pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
862 cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
863 if (pescx_bist_status.u64) 870 if (pescx_bist_status.u64)
864 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n", 871 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
865 pcie_port, CAST64(pescx_bist_status.u64)); 872 pcie_port, CAST64(pescx_bist_status.u64));
@@ -868,50 +875,37 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
868 __cvmx_pcie_rc_initialize_config_space(pcie_port); 875 __cvmx_pcie_rc_initialize_config_space(pcie_port);
869 876
870 /* Bring the link up */ 877 /* Bring the link up */
871 if (__cvmx_pcie_rc_initialize_link(pcie_port)) { 878 if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port)) {
872 cvmx_dprintf 879 cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n",
873 ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n"); 880 pcie_port);
874 return -1; 881 return -1;
875 } 882 }
876 883
877 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */ 884 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
878 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL); 885 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
879 /* Allow 16 words to combine */ 886 npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
880 npei_mem_access_ctl.s.max_word = 0; 887 npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
881 /* Wait up to 127 cycles for more data */
882 npei_mem_access_ctl.s.timer = 127;
883 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64); 888 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
884 889
885 /* Setup Mem access SubDIDs */ 890 /* Setup Mem access SubDIDs */
886 mem_access_subid.u64 = 0; 891 mem_access_subid.u64 = 0;
887 /* Port the request is sent to. */ 892 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
888 mem_access_subid.s.port = pcie_port; 893 mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */
889 /* Due to an errata on pass 1 chips, no merging is allowed. */ 894 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
890 mem_access_subid.s.nmerge = 1; 895 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
891 /* Endian-swap for Reads. */ 896 mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
892 mem_access_subid.s.esr = 1; 897 mem_access_subid.s.nsw = 0; /* Enable Snoop for Writes. */
893 /* Endian-swap for Writes. */ 898 mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */
894 mem_access_subid.s.esw = 1; 899 mem_access_subid.s.row = 0; /* Disable Relaxed Ordering for Writes. */
895 /* No Snoop for Reads. */ 900 mem_access_subid.s.ba = 0; /* PCIe Adddress Bits <63:34>. */
896 mem_access_subid.s.nsr = 1;
897 /* No Snoop for Writes. */
898 mem_access_subid.s.nsw = 1;
899 /* Disable Relaxed Ordering for Reads. */
900 mem_access_subid.s.ror = 0;
901 /* Disable Relaxed Ordering for Writes. */
902 mem_access_subid.s.row = 0;
903 /* PCIe Address Bits <63:34>. */
904 mem_access_subid.s.ba = 0;
905 901
906 /* 902 /*
907 * Setup mem access 12-15 for port 0, 16-19 for port 1, 903 * Setup mem access 12-15 for port 0, 16-19 for port 1,
908 * supplying 36 bits of address space. 904 * supplying 36 bits of address space.
909 */ 905 */
910 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) { 906 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
911 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), 907 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
912 mem_access_subid.u64); 908 mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
913 /* Set each SUBID to extend the addressable range */
914 mem_access_subid.s.ba += 1;
915 } 909 }
916 910
917 /* 911 /*
@@ -927,7 +921,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
927 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ 921 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
928 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0); 922 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
929 923
930 /* BAR1 follows BAR2 with a gap. */ 924 /* BAR1 follows BAR2 with a gap so it has the same address as for gen2. */
931 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE); 925 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
932 926
933 bar1_index.u32 = 0; 927 bar1_index.u32 = 0;
@@ -992,14 +986,474 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
992 npei_ctl_port.s.waitl_com = 0; 986 npei_ctl_port.s.waitl_com = 0;
993 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64); 987 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
994 } 988 }
989
990 /*
991 * Both pass 1 and pass 2 of CN52XX and CN56XX have an errata
992 * that causes TLP ordering to not be preserved after multiple
993 * PCIe port resets. This code detects this fault and corrects
994 * it by aligning the TLP counters properly. Another link
995 * reset is then performed. See PCIE-13340
996 */
997 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
998 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
999 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) ||
1000 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1001 union cvmx_npei_dbg_data dbg_data;
1002 int old_in_fif_p_count;
1003 int in_fif_p_count;
1004 int out_p_count;
1005 int in_p_offset = (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) ? 4 : 1;
1006 int i;
1007
1008 /*
1009 * Choose a write address of 1MB. It should be
1010 * harmless as all bars haven't been setup.
1011 */
1012 uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63);
1013
1014 /*
1015 * Make sure at least in_p_offset have been executed before we try and
1016 * read in_fif_p_count
1017 */
1018 i = in_p_offset;
1019 while (i--) {
1020 cvmx_write64_uint32(write_address, 0);
1021 cvmx_wait(10000);
1022 }
1023
1024 /*
1025 * Read the IN_FIF_P_COUNT from the debug
1026 * select. IN_FIF_P_COUNT can be unstable sometimes so
1027 * read it twice with a write between the reads. This
1028 * way we can tell the value is good as it will
1029 * increment by one due to the write
1030 */
1031 cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);
1032 cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
1033 do {
1034 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1035 old_in_fif_p_count = dbg_data.s.data & 0xff;
1036 cvmx_write64_uint32(write_address, 0);
1037 cvmx_wait(10000);
1038 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1039 in_fif_p_count = dbg_data.s.data & 0xff;
1040 } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
1041
1042 /* Update in_fif_p_count for it's offset with respect to out_p_count */
1043 in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
1044
1045 /* Read the OUT_P_COUNT from the debug select */
1046 cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);
1047 cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
1048 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1049 out_p_count = (dbg_data.s.data>>1) & 0xff;
1050
1051 /* Check that the two counters are aligned */
1052 if (out_p_count != in_fif_p_count) {
1053 cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
1054 while (in_fif_p_count != 0) {
1055 cvmx_write64_uint32(write_address, 0);
1056 cvmx_wait(10000);
1057 in_fif_p_count = (in_fif_p_count + 1) & 0xff;
1058 }
1059 /*
1060 * The EBH5200 board swapped the PCIe reset
1061 * lines on the board. This means we must
1062 * bring both links down and up, which will
1063 * cause the PCIe0 to need alignment
1064 * again. Lots of messages will be displayed,
1065 * but everything should work
1066 */
1067 if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) &&
1068 (pcie_port == 1))
1069 cvmx_pcie_rc_initialize(0);
1070 /* Rety bringing this port up */
1071 goto retry;
1072 }
1073 }
1074
1075 /* Display the link status */
1076 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1077 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
1078
995 return 0; 1079 return 0;
996} 1080}
997 1081
1082/**
1083 * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
1084 * port from reset to a link up state. Software can then begin
1085 * configuring the rest of the link.
1086 *
1087 * @pcie_port: PCIe port to initialize
1088 *
1089 * Return Zero on success.
1090 */
1091static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
1092{
1093 uint64_t start_cycle;
1094 union cvmx_pemx_ctl_status pem_ctl_status;
1095 union cvmx_pciercx_cfg032 pciercx_cfg032;
1096 union cvmx_pciercx_cfg448 pciercx_cfg448;
998 1097
999/* Above was cvmx-pcie.c, below original pcie.c */ 1098 /* Bring up the link */
1099 pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
1100 pem_ctl_status.s.lnk_enb = 1;
1101 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
1102
1103 /* Wait for the link to come up */
1104 start_cycle = cvmx_get_cycle();
1105 do {
1106 if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
1107 return -1;
1108 cvmx_wait(10000);
1109 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1110 } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
1111
1112 /*
1113 * Update the Replay Time Limit. Empirically, some PCIe
1114 * devices take a little longer to respond than expected under
1115 * load. As a workaround for this we configure the Replay Time
1116 * Limit to the value expected for a 512 byte MPS instead of
1117 * our actual 256 byte MPS. The numbers below are directly
1118 * from the PCIe spec table 3-4
1119 */
1120 pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
1121 switch (pciercx_cfg032.s.nlw) {
1122 case 1: /* 1 lane */
1123 pciercx_cfg448.s.rtl = 1677;
1124 break;
1125 case 2: /* 2 lanes */
1126 pciercx_cfg448.s.rtl = 867;
1127 break;
1128 case 4: /* 4 lanes */
1129 pciercx_cfg448.s.rtl = 462;
1130 break;
1131 case 8: /* 8 lanes */
1132 pciercx_cfg448.s.rtl = 258;
1133 break;
1134 }
1135 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
1136
1137 return 0;
1138}
1000 1139
1001 1140
1002/** 1141/**
1142 * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
1143 * the bus.
1144 *
1145 * @pcie_port: PCIe port to initialize
1146 *
1147 * Returns Zero on success.
1148 */
1149static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
1150{
1151 int i;
1152 union cvmx_ciu_soft_prst ciu_soft_prst;
1153 union cvmx_mio_rst_ctlx mio_rst_ctl;
1154 union cvmx_pemx_bar_ctl pemx_bar_ctl;
1155 union cvmx_pemx_ctl_status pemx_ctl_status;
1156 union cvmx_pemx_bist_status pemx_bist_status;
1157 union cvmx_pemx_bist_status2 pemx_bist_status2;
1158 union cvmx_pciercx_cfg032 pciercx_cfg032;
1159 union cvmx_pciercx_cfg515 pciercx_cfg515;
1160 union cvmx_sli_ctl_portx sli_ctl_portx;
1161 union cvmx_sli_mem_access_ctl sli_mem_access_ctl;
1162 union cvmx_sli_mem_access_subidx mem_access_subid;
1163 union cvmx_sriox_status_reg sriox_status_reg;
1164 union cvmx_pemx_bar1_indexx bar1_index;
1165
1166 if (octeon_has_feature(OCTEON_FEATURE_SRIO)) {
1167 /* Make sure this interface isn't SRIO */
1168 if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
1169 /*
1170 * The CN66XX requires reading the
1171 * MIO_QLMX_CFG register to figure out the
1172 * port type.
1173 */
1174 union cvmx_mio_qlmx_cfg qlmx_cfg;
1175 qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port));
1176
1177 if (qlmx_cfg.s.qlm_spd == 15) {
1178 pr_notice("PCIe: Port %d is disabled, skipping.\n", pcie_port);
1179 return -1;
1180 }
1181
1182 switch (qlmx_cfg.s.qlm_spd) {
1183 case 0x1: /* SRIO 1x4 short */
1184 case 0x3: /* SRIO 1x4 long */
1185 case 0x4: /* SRIO 2x2 short */
1186 case 0x6: /* SRIO 2x2 long */
1187 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
1188 return -1;
1189 case 0x9: /* SGMII */
1190 pr_notice("PCIe: Port %d is SGMII, skipping.\n", pcie_port);
1191 return -1;
1192 case 0xb: /* XAUI */
1193 pr_notice("PCIe: Port %d is XAUI, skipping.\n", pcie_port);
1194 return -1;
1195 case 0x0: /* PCIE gen2 */
1196 case 0x8: /* PCIE gen2 (alias) */
1197 case 0x2: /* PCIE gen1 */
1198 case 0xa: /* PCIE gen1 (alias) */
1199 break;
1200 default:
1201 pr_notice("PCIe: Port %d is unknown, skipping.\n", pcie_port);
1202 return -1;
1203 }
1204 } else {
1205 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));
1206 if (sriox_status_reg.s.srio) {
1207 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
1208 return -1;
1209 }
1210 }
1211 }
1212
1213#if 0
1214 /* This code is so that the PCIe analyzer is able to see 63XX traffic */
1215 pr_notice("PCIE : init for pcie analyzer.\n");
1216 cvmx_helper_qlm_jtag_init();
1217 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1218 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1219 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1220 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1221 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1222 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1223 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1224 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1225 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1226 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1227 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1228 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1229 cvmx_helper_qlm_jtag_update(pcie_port);
1230#endif
1231
1232 /* Make sure we aren't trying to setup a target mode interface in host mode */
1233 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
1234 if (!mio_rst_ctl.s.host_mode) {
1235 pr_notice("PCIe: Port %d in endpoint mode.\n", pcie_port);
1236 return -1;
1237 }
1238
1239 /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
1240 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
1241 if (pcie_port) {
1242 union cvmx_ciu_qlm1 ciu_qlm;
1243 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
1244 ciu_qlm.s.txbypass = 1;
1245 ciu_qlm.s.txdeemph = 5;
1246 ciu_qlm.s.txmargin = 0x17;
1247 cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
1248 } else {
1249 union cvmx_ciu_qlm0 ciu_qlm;
1250 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
1251 ciu_qlm.s.txbypass = 1;
1252 ciu_qlm.s.txdeemph = 5;
1253 ciu_qlm.s.txmargin = 0x17;
1254 cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
1255 }
1256 }
1257 /* Bring the PCIe out of reset */
1258 if (pcie_port)
1259 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1260 else
1261 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1262 /*
1263 * After a chip reset the PCIe will also be in reset. If it
1264 * isn't, most likely someone is trying to init it again
1265 * without a proper PCIe reset
1266 */
1267 if (ciu_soft_prst.s.soft_prst == 0) {
1268 /* Reset the port */
1269 ciu_soft_prst.s.soft_prst = 1;
1270 if (pcie_port)
1271 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1272 else
1273 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1274 /* Wait until pcie resets the ports. */
1275 udelay(2000);
1276 }
1277 if (pcie_port) {
1278 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1279 ciu_soft_prst.s.soft_prst = 0;
1280 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1281 } else {
1282 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1283 ciu_soft_prst.s.soft_prst = 0;
1284 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1285 }
1286
1287 /* Wait for PCIe reset to complete */
1288 udelay(1000);
1289
1290 /*
1291 * Check and make sure PCIe came out of reset. If it doesn't
1292 * the board probably hasn't wired the clocks up and the
1293 * interface should be skipped.
1294 */
1295 if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) {
1296 pr_notice("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
1297 return -1;
1298 }
1299
1300 /* Check BIST status */
1301 pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));
1302 if (pemx_bist_status.u64)
1303 pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));
1304 pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));
1305 /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */
1306 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
1307 pemx_bist_status2.u64 &= ~0x3full;
1308 if (pemx_bist_status2.u64)
1309 pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));
1310
1311 /* Initialize the config space CSRs */
1312 __cvmx_pcie_rc_initialize_config_space(pcie_port);
1313
1314 /* Enable gen2 speed selection */
1315 pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
1316 pciercx_cfg515.s.dsc = 1;
1317 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
1318
1319 /* Bring the link up */
1320 if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
1321 /*
1322 * Some gen1 devices don't handle the gen 2 training
1323 * correctly. Disable gen2 and try again with only
1324 * gen1
1325 */
1326 union cvmx_pciercx_cfg031 pciercx_cfg031;
1327 pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
1328 pciercx_cfg031.s.mls = 1;
1329 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
1330 if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
1331 pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);
1332 return -1;
1333 }
1334 }
1335
1336 /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
1337 sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
1338 sli_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
1339 sli_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
1340 cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
1341
1342 /* Setup Mem access SubDIDs */
1343 mem_access_subid.u64 = 0;
1344 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
1345 mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
1346 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
1347 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
1348 mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1349 mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1350 /* PCIe Adddress Bits <63:34>. */
1351 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1352 mem_access_subid.cn68xx.ba = 0;
1353 else
1354 mem_access_subid.cn63xx.ba = 0;
1355
1356 /*
1357 * Setup mem access 12-15 for port 0, 16-19 for port 1,
1358 * supplying 36 bits of address space.
1359 */
1360 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
1361 cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
1362 /* Set each SUBID to extend the addressable range */
1363 __cvmx_increment_ba(&mem_access_subid);
1364 }
1365
1366 /*
1367 * Disable the peer to peer forwarding register. This must be
1368 * setup by the OS after it enumerates the bus and assigns
1369 * addresses to the PCIe busses.
1370 */
1371 for (i = 0; i < 4; i++) {
1372 cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
1373 cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
1374 }
1375
1376 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
1377 cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
1378
1379 /*
1380 * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take
1381 * precedence where they overlap. It also overlaps with the
1382 * device addresses, so make sure the peer to peer forwarding
1383 * is set right.
1384 */
1385 cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
1386
1387 /*
1388 * Setup BAR2 attributes
1389 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
1390 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
1391 * - WAIT_COM=0 will likely work for all applications.
1392 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM])
1393 */
1394 pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));
1395 pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1*/
1396 pemx_bar_ctl.s.bar2_enb = 1;
1397 pemx_bar_ctl.s.bar2_esx = 1;
1398 pemx_bar_ctl.s.bar2_cax = 0;
1399 cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
1400 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
1401 sli_ctl_portx.s.ptlp_ro = 1;
1402 sli_ctl_portx.s.ctlp_ro = 1;
1403 sli_ctl_portx.s.wait_com = 0;
1404 sli_ctl_portx.s.waitl_com = 0;
1405 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
1406
1407 /* BAR1 follows BAR2 */
1408 cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
1409
1410 bar1_index.u64 = 0;
1411 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
1412 bar1_index.s.ca = 1; /* Not Cached */
1413 bar1_index.s.end_swp = 1; /* Endian Swap mode */
1414 bar1_index.s.addr_v = 1; /* Valid entry */
1415
1416 for (i = 0; i < 16; i++) {
1417 cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
1418 /* 256MB / 16 >> 22 == 4 */
1419 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
1420 }
1421
1422 /*
1423 * Allow config retries for 250ms. Count is based off the 5Ghz
1424 * SERDES clock.
1425 */
1426 pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
1427 pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000;
1428 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
1429
1430 /* Display the link status */
1431 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1432 pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
1433
1434 return 0;
1435}
1436
1437/**
1438 * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
1439 *
1440 * @pcie_port: PCIe port to initialize
1441 *
1442 * Returns Zero on success
1443 */
1444static int cvmx_pcie_rc_initialize(int pcie_port)
1445{
1446 int result;
1447 if (octeon_has_feature(OCTEON_FEATURE_NPEI))
1448 result = __cvmx_pcie_rc_initialize_gen1(pcie_port);
1449 else
1450 result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
1451 return result;
1452}
1453
1454/* Above was cvmx-pcie.c, below original pcie.c */
1455
1456/**
1003 * Map a PCI device to the appropriate interrupt line 1457 * Map a PCI device to the appropriate interrupt line
1004 * 1458 *
1005 * @dev: The Linux PCI device structure for the device to map 1459 * @dev: The Linux PCI device structure for the device to map
@@ -1027,11 +1481,12 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
1027 */ 1481 */
1028 while (dev->bus && dev->bus->parent) 1482 while (dev->bus && dev->bus->parent)
1029 dev = to_pci_dev(dev->bus->bridge); 1483 dev = to_pci_dev(dev->bus->bridge);
1030 /* If the root bus is number 0 and the PEX 8114 is the 1484 /*
1485 * If the root bus is number 0 and the PEX 8114 is the
1031 * root, assume we are behind the miswired bus. We 1486 * root, assume we are behind the miswired bus. We
1032 * need to correct the swizzle level by two. Yuck. 1487 * need to correct the swizzle level by two. Yuck.
1033 */ 1488 */
1034 if ((dev->bus->number == 0) && 1489 if ((dev->bus->number == 1) &&
1035 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) { 1490 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
1036 /* 1491 /*
1037 * The pin field is one based, not zero. We 1492 * The pin field is one based, not zero. We
@@ -1048,39 +1503,73 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
1048 return pin - 1 + OCTEON_IRQ_PCI_INT0; 1503 return pin - 1 + OCTEON_IRQ_PCI_INT0;
1049} 1504}
1050 1505
1051/** 1506static void set_cfg_read_retry(u32 retry_cnt)
1507{
1508 union cvmx_pemx_ctl_status pemx_ctl;
1509 pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
1510 pemx_ctl.s.cfg_rtry = retry_cnt;
1511 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
1512}
1513
1514
1515static u32 disable_cfg_read_retry(void)
1516{
1517 u32 retry_cnt;
1518
1519 union cvmx_pemx_ctl_status pemx_ctl;
1520 pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
1521 retry_cnt = pemx_ctl.s.cfg_rtry;
1522 pemx_ctl.s.cfg_rtry = 0;
1523 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
1524 return retry_cnt;
1525}
1526
1527static int is_cfg_retry(void)
1528{
1529 union cvmx_pemx_int_sum pemx_int_sum;
1530 pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1));
1531 if (pemx_int_sum.s.crs_dr)
1532 return 1;
1533 return 0;
1534}
1535
1536/*
1052 * Read a value from configuration space 1537 * Read a value from configuration space
1053 * 1538 *
1054 * @bus:
1055 * @devfn:
1056 * @reg:
1057 * @size:
1058 * @val:
1059 * Returns
1060 */ 1539 */
1061static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus, 1540static int octeon_pcie_read_config(unsigned int pcie_port, struct pci_bus *bus,
1062 unsigned int devfn, int reg, int size, 1541 unsigned int devfn, int reg, int size,
1063 u32 *val) 1542 u32 *val)
1064{ 1543{
1065 union octeon_cvmemctl cvmmemctl; 1544 union octeon_cvmemctl cvmmemctl;
1066 union octeon_cvmemctl cvmmemctl_save; 1545 union octeon_cvmemctl cvmmemctl_save;
1067 int bus_number = bus->number; 1546 int bus_number = bus->number;
1547 int cfg_retry = 0;
1548 int retry_cnt = 0;
1549 int max_retry_cnt = 10;
1550 u32 cfg_retry_cnt = 0;
1068 1551
1552 cvmmemctl_save.u64 = 0;
1553 BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
1069 /* 1554 /*
1070 * For the top level bus make sure our hardware bus number 1555 * For the top level bus make sure our hardware bus number
1071 * matches the software one. 1556 * matches the software one
1072 */ 1557 */
1073 if (bus->parent == NULL) { 1558 if (bus->parent == NULL) {
1074 union cvmx_pciercx_cfg006 pciercx_cfg006; 1559 if (enable_pcie_bus_num_war[pcie_port])
1075 pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port, 1560 bus_number = 0;
1076 CVMX_PCIERCX_CFG006(pcie_port)); 1561 else {
1077 if (pciercx_cfg006.s.pbnum != bus_number) { 1562 union cvmx_pciercx_cfg006 pciercx_cfg006;
1078 pciercx_cfg006.s.pbnum = bus_number; 1563 pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
1079 pciercx_cfg006.s.sbnum = bus_number; 1564 CVMX_PCIERCX_CFG006(pcie_port));
1080 pciercx_cfg006.s.subbnum = bus_number; 1565 if (pciercx_cfg006.s.pbnum != bus_number) {
1081 cvmx_pcie_cfgx_write(pcie_port, 1566 pciercx_cfg006.s.pbnum = bus_number;
1082 CVMX_PCIERCX_CFG006(pcie_port), 1567 pciercx_cfg006.s.sbnum = bus_number;
1083 pciercx_cfg006.u32); 1568 pciercx_cfg006.s.subbnum = bus_number;
1569 cvmx_pcie_cfgx_write(pcie_port,
1570 CVMX_PCIERCX_CFG006(pcie_port),
1571 pciercx_cfg006.u32);
1572 }
1084 } 1573 }
1085 } 1574 }
1086 1575
@@ -1116,29 +1605,52 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
1116 */ 1605 */
1117#if 1 1606#if 1
1118 /* Use this option if you aren't using either slot */ 1607 /* Use this option if you aren't using either slot */
1119 if (bus_number == 1) 1608 if (bus_number == 2)
1120 return PCIBIOS_FUNC_NOT_SUPPORTED; 1609 return PCIBIOS_FUNC_NOT_SUPPORTED;
1121#elif 0 1610#elif 0
1122 /* 1611 /*
1123 * Use this option if you are using the first slot but 1612 * Use this option if you are using the first slot but
1124 * not the second. 1613 * not the second.
1125 */ 1614 */
1126 if ((bus_number == 1) && (devfn >> 3 != 2)) 1615 if ((bus_number == 2) && (devfn >> 3 != 2))
1127 return PCIBIOS_FUNC_NOT_SUPPORTED; 1616 return PCIBIOS_FUNC_NOT_SUPPORTED;
1128#elif 0 1617#elif 0
1129 /* 1618 /*
1130 * Use this option if you are using the second slot 1619 * Use this option if you are using the second slot
1131 * but not the first. 1620 * but not the first.
1132 */ 1621 */
1133 if ((bus_number == 1) && (devfn >> 3 != 3)) 1622 if ((bus_number == 2) && (devfn >> 3 != 3))
1134 return PCIBIOS_FUNC_NOT_SUPPORTED; 1623 return PCIBIOS_FUNC_NOT_SUPPORTED;
1135#elif 0 1624#elif 0
1136 /* Use this opion if you are using both slots */ 1625 /* Use this opion if you are using both slots */
1137 if ((bus_number == 1) && 1626 if ((bus_number == 2) &&
1138 !((devfn == (2 << 3)) || (devfn == (3 << 3)))) 1627 !((devfn == (2 << 3)) || (devfn == (3 << 3))))
1139 return PCIBIOS_FUNC_NOT_SUPPORTED; 1628 return PCIBIOS_FUNC_NOT_SUPPORTED;
1140#endif 1629#endif
1141 1630
1631 /* The following #if gives a more complicated example. This is
1632 the required checks for running a Nitrox CN16XX-NHBX in the
1633 slot of the EBH5600. This card has a PLX PCIe bridge with
1634 four Nitrox PLX parts behind it */
1635#if 0
1636 /* PLX bridge with 4 ports */
1637 if ((bus_number == 4) &&
1638 !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
1639 return PCIBIOS_FUNC_NOT_SUPPORTED;
1640 /* Nitrox behind PLX 1 */
1641 if ((bus_number == 5) && (devfn >> 3 != 0))
1642 return PCIBIOS_FUNC_NOT_SUPPORTED;
1643 /* Nitrox behind PLX 2 */
1644 if ((bus_number == 6) && (devfn >> 3 != 0))
1645 return PCIBIOS_FUNC_NOT_SUPPORTED;
1646 /* Nitrox behind PLX 3 */
1647 if ((bus_number == 7) && (devfn >> 3 != 0))
1648 return PCIBIOS_FUNC_NOT_SUPPORTED;
1649 /* Nitrox behind PLX 4 */
1650 if ((bus_number == 8) && (devfn >> 3 != 0))
1651 return PCIBIOS_FUNC_NOT_SUPPORTED;
1652#endif
1653
1142 /* 1654 /*
1143 * Shorten the DID timeout so bus errors for PCIe 1655 * Shorten the DID timeout so bus errors for PCIe
1144 * config reads from non existent devices happen 1656 * config reads from non existent devices happen
@@ -1152,26 +1664,48 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
1152 __write_64bit_c0_register($11, 7, cvmmemctl.u64); 1664 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
1153 } 1665 }
1154 1666
1155 switch (size) { 1667 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
1156 case 4: 1668 cfg_retry_cnt = disable_cfg_read_retry();
1157 *val = cvmx_pcie_config_read32(pcie_port, bus_number, 1669
1158 devfn >> 3, devfn & 0x7, reg); 1670 pr_debug("pcie_cfg_rd port=%d b=%d devfn=0x%03x reg=0x%03x"
1671 " size=%d ", pcie_port, bus_number, devfn, reg, size);
1672 do {
1673 switch (size) {
1674 case 4:
1675 *val = cvmx_pcie_config_read32(pcie_port, bus_number,
1676 devfn >> 3, devfn & 0x7, reg);
1159 break; 1677 break;
1160 case 2: 1678 case 2:
1161 *val = cvmx_pcie_config_read16(pcie_port, bus_number, 1679 *val = cvmx_pcie_config_read16(pcie_port, bus_number,
1162 devfn >> 3, devfn & 0x7, reg); 1680 devfn >> 3, devfn & 0x7, reg);
1163 break; 1681 break;
1164 case 1: 1682 case 1:
1165 *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3, 1683 *val = cvmx_pcie_config_read8(pcie_port, bus_number,
1166 devfn & 0x7, reg); 1684 devfn >> 3, devfn & 0x7, reg);
1167 break; 1685 break;
1168 default: 1686 default:
1169 return PCIBIOS_FUNC_NOT_SUPPORTED; 1687 if (OCTEON_IS_MODEL(OCTEON_CN63XX))
1170 } 1688 set_cfg_read_retry(cfg_retry_cnt);
1689 return PCIBIOS_FUNC_NOT_SUPPORTED;
1690 }
1691 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) &&
1692 (enable_pcie_14459_war)) {
1693 cfg_retry = is_cfg_retry();
1694 retry_cnt++;
1695 if (retry_cnt > max_retry_cnt) {
1696 pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n",
1697 retry_cnt);
1698 cfg_retry = 0;
1699 }
1700 }
1701 } while (cfg_retry);
1171 1702
1703 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
1704 set_cfg_read_retry(cfg_retry_cnt);
1705 pr_debug("val=%08x : tries=%02d\n", *val, retry_cnt);
1172 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) || 1706 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1173 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) 1707 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
1174 __write_64bit_c0_register($11, 7, cvmmemctl_save.u64); 1708 write_c0_cvmmemctl(cvmmemctl_save.u64);
1175 return PCIBIOS_SUCCESSFUL; 1709 return PCIBIOS_SUCCESSFUL;
1176} 1710}
1177 1711
@@ -1187,42 +1721,56 @@ static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
1187 return octeon_pcie_read_config(1, bus, devfn, reg, size, val); 1721 return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
1188} 1722}
1189 1723
1724static int octeon_dummy_read_config(struct pci_bus *bus, unsigned int devfn,
1725 int reg, int size, u32 *val)
1726{
1727 return PCIBIOS_FUNC_NOT_SUPPORTED;
1728}
1190 1729
1191 1730/*
1192/**
1193 * Write a value to PCI configuration space 1731 * Write a value to PCI configuration space
1194 *
1195 * @bus:
1196 * @devfn:
1197 * @reg:
1198 * @size:
1199 * @val:
1200 * Returns
1201 */ 1732 */
1202static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus, 1733static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,
1203 unsigned int devfn, int reg, 1734 unsigned int devfn, int reg,
1204 int size, u32 val) 1735 int size, u32 val)
1205{ 1736{
1206 int bus_number = bus->number; 1737 int bus_number = bus->number;
1207 1738
1739 BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
1740
1741 if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port]))
1742 bus_number = 0;
1743
1744 pr_debug("pcie_cfg_wr port=%d b=%d devfn=0x%03x"
1745 " reg=0x%03x size=%d val=%08x\n", pcie_port, bus_number, devfn,
1746 reg, size, val);
1747
1748
1208 switch (size) { 1749 switch (size) {
1209 case 4: 1750 case 4:
1210 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3, 1751 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
1211 devfn & 0x7, reg, val); 1752 devfn & 0x7, reg, val);
1212 return PCIBIOS_SUCCESSFUL; 1753 break;
1213 case 2: 1754 case 2:
1214 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3, 1755 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
1215 devfn & 0x7, reg, val); 1756 devfn & 0x7, reg, val);
1216 return PCIBIOS_SUCCESSFUL; 1757 break;
1217 case 1: 1758 case 1:
1218 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3, 1759 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
1219 devfn & 0x7, reg, val); 1760 devfn & 0x7, reg, val);
1220 return PCIBIOS_SUCCESSFUL; 1761 break;
1762 default:
1763 return PCIBIOS_FUNC_NOT_SUPPORTED;
1221 } 1764 }
1222#if PCI_CONFIG_SPACE_DELAY 1765#if PCI_CONFIG_SPACE_DELAY
1766 /*
1767 * Delay on writes so that devices have time to come up. Some
1768 * bridges need this to allow time for the secondary busses to
1769 * work
1770 */
1223 udelay(PCI_CONFIG_SPACE_DELAY); 1771 udelay(PCI_CONFIG_SPACE_DELAY);
1224#endif 1772#endif
1225 return PCIBIOS_FUNC_NOT_SUPPORTED; 1773 return PCIBIOS_SUCCESSFUL;
1226} 1774}
1227 1775
1228static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn, 1776static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -1237,6 +1785,12 @@ static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
1237 return octeon_pcie_write_config(1, bus, devfn, reg, size, val); 1785 return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
1238} 1786}
1239 1787
1788static int octeon_dummy_write_config(struct pci_bus *bus, unsigned int devfn,
1789 int reg, int size, u32 val)
1790{
1791 return PCIBIOS_FUNC_NOT_SUPPORTED;
1792}
1793
1240static struct pci_ops octeon_pcie0_ops = { 1794static struct pci_ops octeon_pcie0_ops = {
1241 octeon_pcie0_read_config, 1795 octeon_pcie0_read_config,
1242 octeon_pcie0_write_config, 1796 octeon_pcie0_write_config,
@@ -1279,6 +1833,35 @@ static struct pci_controller octeon_pcie1_controller = {
1279 .io_resource = &octeon_pcie1_io_resource, 1833 .io_resource = &octeon_pcie1_io_resource,
1280}; 1834};
1281 1835
1836static struct pci_ops octeon_dummy_ops = {
1837 octeon_dummy_read_config,
1838 octeon_dummy_write_config,
1839};
1840
1841static struct resource octeon_dummy_mem_resource = {
1842 .name = "Virtual PCIe MEM",
1843 .flags = IORESOURCE_MEM,
1844};
1845
1846static struct resource octeon_dummy_io_resource = {
1847 .name = "Virtual PCIe IO",
1848 .flags = IORESOURCE_IO,
1849};
1850
1851static struct pci_controller octeon_dummy_controller = {
1852 .pci_ops = &octeon_dummy_ops,
1853 .mem_resource = &octeon_dummy_mem_resource,
1854 .io_resource = &octeon_dummy_io_resource,
1855};
1856
1857static int device_needs_bus_num_war(uint32_t deviceid)
1858{
1859#define IDT_VENDOR_ID 0x111d
1860
1861 if ((deviceid & 0xffff) == IDT_VENDOR_ID)
1862 return 1;
1863 return 0;
1864}
1282 1865
1283/** 1866/**
1284 * Initialize the Octeon PCIe controllers 1867 * Initialize the Octeon PCIe controllers
@@ -1287,19 +1870,27 @@ static struct pci_controller octeon_pcie1_controller = {
1287 */ 1870 */
1288static int __init octeon_pcie_setup(void) 1871static int __init octeon_pcie_setup(void)
1289{ 1872{
1290 union cvmx_npei_ctl_status npei_ctl_status;
1291 int result; 1873 int result;
1874 int host_mode;
1875 int srio_war15205 = 0, port;
1876 union cvmx_sli_ctl_portx sli_ctl_portx;
1877 union cvmx_sriox_status_reg sriox_status_reg;
1292 1878
1293 /* These chips don't have PCIe */ 1879 /* These chips don't have PCIe */
1294 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) 1880 if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
1295 return 0; 1881 return 0;
1296 1882
1883 /* No PCIe simulation */
1884 if (octeon_is_simulation())
1885 return 0;
1886
1887 /* Disable PCI if instructed on the command line */
1888 if (pcie_disable)
1889 return 0;
1890
1297 /* Point pcibios_map_irq() to the PCIe version of it */ 1891 /* Point pcibios_map_irq() to the PCIe version of it */
1298 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq; 1892 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
1299 1893
1300 /* Use the PCIe based DMA mappings */
1301 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1302
1303 /* 1894 /*
1304 * PCIe I/O range. It is based on port 0 but includes up until 1895 * PCIe I/O range. It is based on port 0 but includes up until
1305 * port 1's end. 1896 * port 1's end.
@@ -1310,11 +1901,43 @@ static int __init octeon_pcie_setup(void)
1310 cvmx_pcie_get_io_base_address(1) - 1901 cvmx_pcie_get_io_base_address(1) -
1311 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1; 1902 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1312 1903
1313 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS); 1904 /*
1314 if (npei_ctl_status.s.host_mode) { 1905 * Create a dummy PCIe controller to swallow up bus 0. IDT bridges
1906 * don't work if the primary bus number is zero. Here we add a fake
1907 * PCIe controller that the kernel will give bus 0. This allows
1908 * us to not change the normal kernel bus enumeration
1909 */
1910 octeon_dummy_controller.io_map_base = -1;
1911 octeon_dummy_controller.mem_resource->start = (1ull<<48);
1912 octeon_dummy_controller.mem_resource->end = (1ull<<48);
1913 register_pci_controller(&octeon_dummy_controller);
1914
1915 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
1916 union cvmx_npei_ctl_status npei_ctl_status;
1917 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1918 host_mode = npei_ctl_status.s.host_mode;
1919 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1920 } else {
1921 union cvmx_mio_rst_ctlx mio_rst_ctl;
1922 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0));
1923 host_mode = mio_rst_ctl.s.host_mode;
1924 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE2;
1925 }
1926
1927 if (host_mode) {
1315 pr_notice("PCIe: Initializing port 0\n"); 1928 pr_notice("PCIe: Initializing port 0\n");
1929 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1930 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1931 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1932 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
1933 if (sriox_status_reg.s.srio) {
1934 srio_war15205 += 1; /* Port is SRIO */
1935 port = 0;
1936 }
1937 }
1316 result = cvmx_pcie_rc_initialize(0); 1938 result = cvmx_pcie_rc_initialize(0);
1317 if (result == 0) { 1939 if (result == 0) {
1940 uint32_t device0;
1318 /* Memory offsets are physical addresses */ 1941 /* Memory offsets are physical addresses */
1319 octeon_pcie0_controller.mem_offset = 1942 octeon_pcie0_controller.mem_offset =
1320 cvmx_pcie_get_mem_base_address(0); 1943 cvmx_pcie_get_mem_base_address(0);
@@ -1343,60 +1966,134 @@ static int __init octeon_pcie_setup(void)
1343 octeon_pcie0_controller.io_resource->start = 4 << 10; 1966 octeon_pcie0_controller.io_resource->start = 4 << 10;
1344 octeon_pcie0_controller.io_resource->end = 1967 octeon_pcie0_controller.io_resource->end =
1345 cvmx_pcie_get_io_size(0) - 1; 1968 cvmx_pcie_get_io_size(0) - 1;
1969 msleep(100); /* Some devices need extra time */
1346 register_pci_controller(&octeon_pcie0_controller); 1970 register_pci_controller(&octeon_pcie0_controller);
1971 device0 = cvmx_pcie_config_read32(0, 0, 0, 0, 0);
1972 enable_pcie_bus_num_war[0] =
1973 device_needs_bus_num_war(device0);
1347 } 1974 }
1348 } else { 1975 } else {
1349 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n"); 1976 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1977 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1978 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1979 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1980 srio_war15205 += 1;
1981 port = 0;
1982 }
1350 } 1983 }
1351 1984
1352 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */ 1985 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
1353 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { 1986 host_mode = 1;
1354 union cvmx_npei_dbg_data npei_dbg_data; 1987 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1355 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA); 1988 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1356 if (npei_dbg_data.cn52xx.qlm0_link_width) 1989 union cvmx_npei_dbg_data dbg_data;
1357 return 0; 1990 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1991 if (dbg_data.cn52xx.qlm0_link_width)
1992 host_mode = 0;
1993 }
1994 } else {
1995 union cvmx_mio_rst_ctlx mio_rst_ctl;
1996 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1));
1997 host_mode = mio_rst_ctl.s.host_mode;
1358 } 1998 }
1359 1999
1360 pr_notice("PCIe: Initializing port 1\n"); 2000 if (host_mode) {
1361 result = cvmx_pcie_rc_initialize(1); 2001 pr_notice("PCIe: Initializing port 1\n");
1362 if (result == 0) { 2002 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1363 /* Memory offsets are physical addresses */ 2003 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1364 octeon_pcie1_controller.mem_offset = 2004 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1365 cvmx_pcie_get_mem_base_address(1); 2005 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
1366 /* IO offsets are Mips virtual addresses */ 2006 if (sriox_status_reg.s.srio) {
1367 octeon_pcie1_controller.io_map_base = 2007 srio_war15205 += 1; /* Port is SRIO */
1368 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1)); 2008 port = 1;
1369 octeon_pcie1_controller.io_offset = 2009 }
1370 cvmx_pcie_get_io_base_address(1) - 2010 }
1371 cvmx_pcie_get_io_base_address(0); 2011 result = cvmx_pcie_rc_initialize(1);
1372 /* 2012 if (result == 0) {
1373 * To keep things similar to PCI, we start device 2013 uint32_t device0;
1374 * addresses at the same place as PCI uisng big bar 2014 /* Memory offsets are physical addresses */
1375 * support. This normally translates to 4GB-256MB, 2015 octeon_pcie1_controller.mem_offset =
1376 * which is the same as most x86 PCs. 2016 cvmx_pcie_get_mem_base_address(1);
1377 */ 2017 /*
1378 octeon_pcie1_controller.mem_resource->start = 2018 * To calculate the address for accessing the 2nd PCIe device,
1379 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) - 2019 * either 'io_map_base' (pci_iomap()), or 'mips_io_port_base'
1380 (OCTEON_PCI_BAR1_HOLE_SIZE << 20); 2020 * (ioport_map()) value is added to
1381 octeon_pcie1_controller.mem_resource->end = 2021 * pci_resource_start(dev,bar)). The 'mips_io_port_base' is set
1382 cvmx_pcie_get_mem_base_address(1) + 2022 * only once based on first PCIe. Also changing 'io_map_base'
1383 cvmx_pcie_get_mem_size(1) - 1; 2023 * based on first slot's value so that both the routines will
1384 /* 2024 * work properly.
1385 * Ports must be above 16KB for the ISA bus filtering 2025 */
1386 * in the PCI-X to PCI bridge. 2026 octeon_pcie1_controller.io_map_base =
1387 */ 2027 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0));
1388 octeon_pcie1_controller.io_resource->start = 2028 /* IO offsets are Mips virtual addresses */
1389 cvmx_pcie_get_io_base_address(1) - 2029 octeon_pcie1_controller.io_offset =
1390 cvmx_pcie_get_io_base_address(0); 2030 cvmx_pcie_get_io_base_address(1) -
1391 octeon_pcie1_controller.io_resource->end = 2031 cvmx_pcie_get_io_base_address(0);
1392 octeon_pcie1_controller.io_resource->start + 2032 /*
1393 cvmx_pcie_get_io_size(1) - 1; 2033 * To keep things similar to PCI, we start device
1394 register_pci_controller(&octeon_pcie1_controller); 2034 * addresses at the same place as PCI uisng big bar
2035 * support. This normally translates to 4GB-256MB,
2036 * which is the same as most x86 PCs.
2037 */
2038 octeon_pcie1_controller.mem_resource->start =
2039 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
2040 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
2041 octeon_pcie1_controller.mem_resource->end =
2042 cvmx_pcie_get_mem_base_address(1) +
2043 cvmx_pcie_get_mem_size(1) - 1;
2044 /*
2045 * Ports must be above 16KB for the ISA bus filtering
2046 * in the PCI-X to PCI bridge.
2047 */
2048 octeon_pcie1_controller.io_resource->start =
2049 cvmx_pcie_get_io_base_address(1) -
2050 cvmx_pcie_get_io_base_address(0);
2051 octeon_pcie1_controller.io_resource->end =
2052 octeon_pcie1_controller.io_resource->start +
2053 cvmx_pcie_get_io_size(1) - 1;
2054 msleep(100); /* Some devices need extra time */
2055 register_pci_controller(&octeon_pcie1_controller);
2056 device0 = cvmx_pcie_config_read32(1, 0, 0, 0, 0);
2057 enable_pcie_bus_num_war[1] =
2058 device_needs_bus_num_war(device0);
2059 }
2060 } else {
2061 pr_notice("PCIe: Port 1 not in root complex mode, skipping.\n");
2062 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
2063 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
2064 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2065 srio_war15205 += 1;
2066 port = 1;
2067 }
2068 }
2069
2070 /*
2071 * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all
2072 * of SRIO MACs SLI_CTL_PORT*[INT*_MAP] to similar value and
2073 * all of PCIe Macs SLI_CTL_PORT*[INT*_MAP] to different value
2074 * from the previous set values
2075 */
2076 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
2077 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2078 if (srio_war15205 == 1) {
2079 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port));
2080 sli_ctl_portx.s.inta_map = 1;
2081 sli_ctl_portx.s.intb_map = 1;
2082 sli_ctl_portx.s.intc_map = 1;
2083 sli_ctl_portx.s.intd_map = 1;
2084 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64);
2085
2086 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port));
2087 sli_ctl_portx.s.inta_map = 0;
2088 sli_ctl_portx.s.intb_map = 0;
2089 sli_ctl_portx.s.intc_map = 0;
2090 sli_ctl_portx.s.intd_map = 0;
2091 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64);
2092 }
1395 } 2093 }
1396 2094
1397 octeon_pci_dma_init(); 2095 octeon_pci_dma_init();
1398 2096
1399 return 0; 2097 return 0;
1400} 2098}
1401
1402arch_initcall(octeon_pcie_setup); 2099arch_initcall(octeon_pcie_setup);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 19:38:09 -0500