60 files changed, 67 insertions, 67 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 83aa5fb8e8f1..8e256cc5dcd9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1135,7 +1135,7 @@ config CPU_LOONGSON2E
           The Loongson 2E processor implements the MIPS III instruction set
           with many extensions.
 
-          It has an internal FPGA northbridge, which is compatiable to
+          It has an internal FPGA northbridge, which is compatible to
           bonito64.
 
 config CPU_LOONGSON2F
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index ac1d5b611a27..53e3514ba10e 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -101,7 +101,7 @@ cflags-y += -ffreestanding
 # carefully avoid to add it redundantly because gcc 3.3/3.4 complains
 # when fed the toolchain default!
 #
-# Certain gcc versions upto gcc 4.1.1 (probably 4.2-subversion as of
+# Certain gcc versions up to gcc 4.1.1 (probably 4.2-subversion as of
 # 2006-10-10 don't properly change the predefined symbols if -EB / -EL
 # are used, so we kludge that here.  A bug has been filed at
 # http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29413.
@@ -314,5 +314,5 @@ define archhelp
         echo '  vmlinuz.bin          - Raw binary zboot image'
         echo '  vmlinuz.srec         - SREC zboot image'
         echo
-        echo '  These will be default as apropriate for a configured platform.'
+        echo '  These will be default as appropriate for a configured platform.'
 endef
diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c
index af0fe41055af..f38298a8b98c 100644
--- a/arch/mips/alchemy/common/clocks.c
+++ b/arch/mips/alchemy/common/clocks.c
@@ -75,7 +75,7 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base)
  * counter, if it exists.  If we don't have an accurate processor
  * speed, all of the peripherals that derive their clocks based on
  * this advertised speed will introduce error and sometimes not work
- * properly.  This function is futher convoluted to still allow configurations
+ * properly.  This function is further convoluted to still allow configurations
  * to do that in case they have really, really old silicon with a
  * write-only PLL register.                     -- Dan
  */
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c
index 9afc3794ed1b..c8d35684504e 100644
--- a/arch/mips/cavium-octeon/executive/octeon-model.c
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -75,7 +75,7 @@ const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
 
         num_cores = cvmx_octeon_num_cores();
 
-        /* Make sure the non existant devices look disabled */
+        /* Make sure the non existent devices look disabled */
         switch ((chip_id >> 8) & 0xff) {
         case 6:         /* CN50XX */
         case 2:         /* CN30XX */
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index cecaf62aef32..cd61d7281d91 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -75,7 +75,7 @@ static int __init octeon_cf_device_init(void)
                  * zero.
                  */
 
-                /* Asume that CS1 immediately follows. */
+                /* Assume that CS1 immediately follows. */
                 mio_boot_reg_cfg.u64 =
                         cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
                 region_base = mio_boot_reg_cfg.s.base << 16;
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 8b139bf4a1b5..0707fae3f0ee 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -662,7 +662,7 @@ void __init plat_mem_setup(void)
          * some memory vectors. When SPARSEMEM is in use, it doesn't
          * verify that the size is big enough for the final
          * vectors. Making the smallest chuck 4MB seems to be enough
-         * to consistantly work.
+         * to consistently work.
          */
         mem_alloc_size = 4 << 20;
         if (mem_alloc_size > MAX_MEMORY)
diff --git a/arch/mips/fw/arc/promlib.c b/arch/mips/fw/arc/promlib.c
index c508c00dbb64..b7f9dd3c93c6 100644
--- a/arch/mips/fw/arc/promlib.c
+++ b/arch/mips/fw/arc/promlib.c
@@ -4,7 +4,7 @@
  * for more details.
  *
  * Copyright (C) 1996 David S. Miller (dm@sgi.com)
- * Compability with board caches, Ulf Carlsson
+ * Compatibility with board caches, Ulf Carlsson
  */
 #include <linux/kernel.h>
 #include <asm/sgialib.h>
diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
index b9c8203688d5..c0ead6313845 100644
--- a/arch/mips/include/asm/dec/prom.h
+++ b/arch/mips/include/asm/dec/prom.h
@@ -108,7 +108,7 @@ extern int (*__pmax_close)(int);
 
 /*
  * On MIPS64 we have to call PROM functions via a helper
- * dispatcher to accomodate ABI incompatibilities.
+ * dispatcher to accommodate ABI incompatibilities.
  */
 #define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
                                  __asm__(#fun " = call_o32")
diff --git a/arch/mips/include/asm/floppy.h b/arch/mips/include/asm/floppy.h
index 992d232adc83..c5c7c0e6064c 100644
--- a/arch/mips/include/asm/floppy.h
+++ b/arch/mips/include/asm/floppy.h
@@ -24,7 +24,7 @@ static inline void fd_cacheflush(char * addr, long size)
  * And on Mips's the CMOS info fails also ...
  *
  * FIXME: This information should come from the ARC configuration tree
- *        or whereever a particular machine has stored this ...
+ *        or wherever a particular machine has stored this ...
  */
 #define FLOPPY0_TYPE            fd_drive_type(0)
 #define FLOPPY1_TYPE            fd_drive_type(1)
diff --git a/arch/mips/include/asm/hw_irq.h b/arch/mips/include/asm/hw_irq.h
index aca05a43a97b..77adda297ad9 100644
--- a/arch/mips/include/asm/hw_irq.h
+++ b/arch/mips/include/asm/hw_irq.h
@@ -13,7 +13,7 @@
 extern atomic_t irq_err_count;
 
 /*
- * interrupt-retrigger: NOP for now. This may not be apropriate for all
+ * interrupt-retrigger: NOP for now. This may not be appropriate for all
  * machines, we'll see ...
  */
 
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 5b017f23e243..b04e4de5dd2e 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -242,7 +242,7 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
  * This version of ioremap ensures that the memory is marked uncachable
  * on the CPU as well as honouring existing caching rules from things like
  * the PCI bus. Note that there are other caches and buffers on many
- * busses. In paticular driver authors should read up on PCI writes
+ * busses. In particular driver authors should read up on PCI writes
  *
  * It's useful if some control registers are in such an area and
  * write combining or read caching is not desirable:
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index 9ef3b0d17896..309cbcd6909c 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -174,7 +174,7 @@ __asm__(
         "mtc0   \\flags, $2, 1                                          \n"
 #elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
         /*
-         * Slow, but doesn't suffer from a relativly unlikely race
+         * Slow, but doesn't suffer from a relatively unlikely race
          * condition we're having since days 1.
          */
         "       beqz    \\flags, 1f                                     \n"
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
index 5325084d5c48..32978d32561a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
@@ -4,7 +4,7 @@
 #define TAGVER_LEN              4       /* Length of Tag Version */
 #define TAGLAYOUT_LEN           4       /* Length of FlashLayoutVer */
 #define SIG1_LEN                20      /* Company Signature 1 Length */
-#define SIG2_LEN                14      /* Company Signature 2 Lenght */
+#define SIG2_LEN                14      /* Company Signature 2 Length */
 #define BOARDID_LEN             16      /* Length of BoardId */
 #define ENDIANFLAG_LEN          2       /* Endian Flag Length */
 #define CHIPID_LEN              6       /* Chip Id Length */
diff --git a/arch/mips/include/asm/mach-ip32/mc146818rtc.h b/arch/mips/include/asm/mach-ip32/mc146818rtc.h
index c28ba8d84076..6b6bab43d5c1 100644
--- a/arch/mips/include/asm/mach-ip32/mc146818rtc.h
+++ b/arch/mips/include/asm/mach-ip32/mc146818rtc.h
@@ -26,7 +26,7 @@ static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
 }
 
 /*
- * FIXME: Do it right. For now just assume that noone lives in 20th century
+ * FIXME: Do it right. For now just assume that no one lives in 20th century
  * and no O2 user in 22th century ;-)
  */
 #define mc146818_decode_year(year) ((year) + 2000)
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
index 021f77ca59ec..2a8e2bb5d539 100644
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -1,5 +1,5 @@
 /*
- * The header file of cs5536 sourth bridge.
+ * The header file of cs5536 south bridge.
  *
  * Copyright (C) 2007 Lemote, Inc.
  * Author : jlliu <liujl@lemote.com>
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
index 6d1ff9060e44..65059255dc1e 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1000.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1000.h
@@ -1,5 +1,5 @@
 /*
- * Alchemy Semi Pb1000 Referrence Board
+ * Alchemy Semi Pb1000 Reference Board
  *
  * Copyright 2001, 2008 MontaVista Software Inc.
  * Author: MontaVista Software, Inc. <source@mvista.com>
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index 962eb55dc880..fce4332ebb7f 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -1,5 +1,5 @@
 /*
- * AMD Alchemy Pb1200 Referrence Board
+ * AMD Alchemy Pb1200 Reference Board
  * Board Registers defines.
  *
  * ########################################################################
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index fc4d766641ce..f835c88e9593 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -1,5 +1,5 @@
 /*
- * AMD Alchemy Semi PB1550 Referrence Board
+ * AMD Alchemy Semi PB1550 Reference Board
  * Board Registers defines.
  *
  * Copyright 2004 Embedded Edge LLC.
diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
index f76029c2406e..a8e72cf12142 100644
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -48,7 +48,7 @@ static inline unsigned long virt_to_phys_from_pte(void *addr)
                                 /* check for a valid page */
                                 if (pte_present(pte)) {
                                         /* get the physical address the page is
-                                         * refering to */
+                                         * referring to */
                                         phys_addr = (unsigned long)
                                                 page_to_phys(pte_page(pte));
                                         /* add the offset within the page */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 4d9870975382..6a6f8a8f542d 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -922,7 +922,7 @@ do {									\
 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
 
 /*
- * The WatchLo register.  There may be upto 8 of them.
+ * The WatchLo register.  There may be up to 8 of them.
  */
 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
@@ -942,7 +942,7 @@ do {									\
 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
 
 /*
- * The WatchHi register.  There may be upto 8 of them.
+ * The WatchHi register.  There may be up to 8 of them.
  */
 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index f3c23a43f845..4e4c3a8282d6 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -200,7 +200,7 @@ enum cvmx_chip_types_enum {
         CVMX_CHIP_TYPE_MAX,
 };
 
-/* Compatability alias for NAC38 name change, planned to be removed
+/* Compatibility alias for NAC38 name change, planned to be removed
  * from SDK 1.7 */
 #define CVMX_BOARD_TYPE_NAO38   CVMX_BOARD_TYPE_NAC38
 
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 8e708bdb43f7..877845b84b14 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -67,7 +67,7 @@ struct cvmx_bootmem_block_header {
 
 /*
  * Structure for named memory blocks.  Number of descriptors available
- * can be changed without affecting compatiblity, but name length
+ * can be changed without affecting compatibility, but name length
  * changes require a bump in the bootmem descriptor version Note: This
  * structure must be naturally 64 bit aligned, as a single memory
  * image will be used by both 32 and 64 bit programs.
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
index 0b32c5b118e2..2c8ff9e33ec3 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2c.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -157,7 +157,7 @@ enum cvmx_l2c_tad_event {
 
 /**
  * Configure one of the four L2 Cache performance counters to capture event
- * occurences.
+ * occurrences.
  *
  * @counter:        The counter to configure. Range 0..3.
  * @event:          The type of L2 Cache event occurrence to count.
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 9d9381e2e3d8..7e1286706d46 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -151,7 +151,7 @@ enum cvmx_mips_space {
 #endif
 
 /**
- * Convert a memory pointer (void*) into a hardware compatable
+ * Convert a memory pointer (void*) into a hardware compatible
  * memory address (uint64_t). Octeon hardware widgets don't
  * understand logical addresses.
  *
diff --git a/arch/mips/include/asm/paccess.h b/arch/mips/include/asm/paccess.h
index c2394f8b0fe1..9ce5a1e7e14c 100644
--- a/arch/mips/include/asm/paccess.h
+++ b/arch/mips/include/asm/paccess.h
@@ -7,7 +7,7 @@
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  *
  * Protected memory access.  Used for everything that might take revenge
- * by sending a DBE error like accessing possibly non-existant memory or
+ * by sending a DBE error like accessing possibly non-existent memory or
  * devices.
  */
 #ifndef _ASM_PACCESS_H
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index f1f508e4f971..be44fb0266da 100644
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -262,7 +262,7 @@ typedef volatile struct bridge_s {
 } bridge_t;
 
 /*
- * Field formats for Error Command Word and Auxillary Error Command Word
+ * Field formats for Error Command Word and Auxiliary Error Command Word
  * of bridge.
  */
 typedef struct bridge_err_cmdword_s {
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
index 60a5a38dd5b2..7d41474e5488 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
@@ -205,7 +205,7 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
  *   custom_read_reg32(address, tmp);   <-- Reads the address and put the value
  *                                              in the 'tmp' variable given
  *
- *      From here on out, you are (basicly) atomic, so don't do anything too
+ *      From here on out, you are (basically) atomic, so don't do anything too
  *      fancy!
  *      Also, this code may loop if the end of this block fails to write
  *      everything back safely due do the other CPU, so do NOT do anything
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index ead6928fa6b8..c104f1039a69 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -337,7 +337,7 @@ unsigned long get_wchan(struct task_struct *p);
 /*
  * Return_address is a replacement for __builtin_return_address(count)
  * which on certain architectures cannot reasonably be implemented in GCC
- * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
+ * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
  * Note that __builtin_return_address(x>=1) is forbidden because GCC
  * aborts compilation on some CPUs.  It's simply not possible to unwind
  * some CPU's stackframes.
diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h
index 57a971904cfe..380347b648e2 100644
--- a/arch/mips/include/asm/sgi/ioc.h
+++ b/arch/mips/include/asm/sgi/ioc.h
@@ -17,7 +17,7 @@
 #include <asm/sgi/pi1.h>
 
 /*
- * All registers are 8-bit wide alligned on 32-bit boundary. Bad things
+ * All registers are 8-bit wide aligned on 32-bit boundary. Bad things
  * happen if you try word access them. You have been warned.
  */
 
diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h
index 591b9061fd8e..77f787284235 100644
--- a/arch/mips/include/asm/sibyte/sb1250_mac.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mac.h
@@ -520,7 +520,7 @@
 #define G_MAC_RX_EOP_COUNTER(x)     _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER)
 
 /*
- * MAC Recieve Address Filter Exact Match Registers (Table 9-21)
+ * MAC Receive Address Filter Exact Match Registers (Table 9-21)
  * Registers: MAC_ADDR0_0 through MAC_ADDR7_0
  * Registers: MAC_ADDR0_1 through MAC_ADDR7_1
  * Registers: MAC_ADDR0_2 through MAC_ADDR7_2
@@ -538,7 +538,7 @@
 /* No bitfields */
 
 /*
- * MAC Recieve Address Filter Hash Match Registers (Table 9-22)
+ * MAC Receive Address Filter Hash Match Registers (Table 9-22)
  * Registers: MAC_HASH0_0 through MAC_HASH7_0
  * Registers: MAC_HASH0_1 through MAC_HASH7_1
  * Registers: MAC_HASH0_2 through MAC_HASH7_2
diff --git a/arch/mips/include/asm/siginfo.h b/arch/mips/include/asm/siginfo.h
index 1ca64b4d33d9..20ebeb875ee6 100644
--- a/arch/mips/include/asm/siginfo.h
+++ b/arch/mips/include/asm/siginfo.h
@@ -101,7 +101,7 @@ typedef struct siginfo {
 
 /*
  * si_code values
- * Again these have been choosen to be IRIX compatible.
+ * Again these have been chosen to be IRIX compatible.
  */
 #undef SI_ASYNCIO
 #undef SI_TIMER
diff --git a/arch/mips/include/asm/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h
index 09e590daca17..fe02900b930d 100644
--- a/arch/mips/include/asm/sn/klconfig.h
+++ b/arch/mips/include/asm/sn/klconfig.h
@@ -78,7 +78,7 @@ typedef s32 klconf_off_t;
  */
 #define MAX_SLOTS_PER_NODE      (1 + 2 + 6 + 2)
 
-/* XXX if each node is guranteed to have some memory */
+/* XXX if each node is guaranteed to have some memory */
 
 #define MAX_PCI_DEVS            8
 
@@ -539,7 +539,7 @@ typedef struct klinfo_s {                  /* Generic info */
 #define KLSTRUCT_IOC3_TTY       24
 
 /* Early Access IO proms are compatible
-   only with KLSTRUCT values upto 24. */
+   only with KLSTRUCT values up to 24. */
 
 #define KLSTRUCT_FIBERCHANNEL   25
 #define KLSTRUCT_MOD_SERIAL_NUM 26
diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h
index 31c76c021bb6..46286d8302a7 100644
--- a/arch/mips/include/asm/sn/sn0/hubio.h
+++ b/arch/mips/include/asm/sn/sn0/hubio.h
@@ -622,7 +622,7 @@ typedef union h1_icrbb_u {
  */
 #define IIO_ICRB_PROC0          0       /* Source of request is Proc 0 */
 #define IIO_ICRB_PROC1          1       /* Source of request is Proc 1 */
-#define IIO_ICRB_GB_REQ         2       /* Source is Guranteed BW request */
+#define IIO_ICRB_GB_REQ         2       /* Source is Guaranteed BW request */
 #define IIO_ICRB_IO_REQ         3       /* Source is Normal IO request  */
 
 /*
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 58730c5ce4bf..b4ba2449444b 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -346,7 +346,7 @@
                  * we can't dispatch it directly without trashing
                  * some registers, so we'll try to detect this unlikely
                  * case and program a software interrupt in the VPE,
-                 * as would be done for a cross-VPE IPI.  To accomodate
+                 * as would be done for a cross-VPE IPI.  To accommodate
                  * the handling of that case, we're doing a DVPE instead
                  * of just a DMT here to protect against other threads.
                  * This is a lot of cruft to cover a tiny window.
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 22361d5e3bf0..fa133c1bc1f9 100644
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -227,7 +227,7 @@
 #endif
 
 /*
- * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
+ * On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
  * may cause ll / sc and lld / scd sequences to execute non-atomically.
  */
 #ifndef R10000_LLSC_WAR
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index bc18daaa8f84..c3b04be3fb2b 100644
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -65,7 +65,7 @@ static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
 };
 
 /* Early prototypes of the QI LB60 had only 1GB of NAND.
- * In order to support these devices aswell the partition and ecc layout is
+ * In order to support these devices as well the partition and ecc layout is
  * initialized depending on the NAND size */
 static struct mtd_partition qi_lb60_partitions_1gb[] = {
         {
@@ -439,7 +439,7 @@ static struct platform_device *jz_platform_devices[] __initdata = {
 static void __init board_gpio_setup(void)
 {
         /* We only need to enable/disable pullup here for pins used in generic
-         * drivers. Everything else is done by the drivers themselfs. */
+         * drivers. Everything else is done by the drivers themselves. */
         jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N);
         jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD);
 }
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index b8bb8ba60869..f305ca14351b 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -73,7 +73,7 @@ static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
                 : "0" (5), "1" (8), "2" (5));
         align_mod(align, mod);
         /*
-         * The trailing nop is needed to fullfill the two-instruction
+         * The trailing nop is needed to fulfill the two-instruction
          * requirement between reading hi/lo and staring a mult/div.
          * Leaving it out may cause gas insert a nop itself breaking
          * the desired alignment of the next chunk.
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index d9a7db78ed62..75266ff4cc33 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -721,7 +721,7 @@ static void mipsxx_pmu_start(void)
 
 /*
  * MIPS performance counters can be per-TC. The control registers can
- * not be directly accessed accross CPUs. Hence if we want to do global
+ * not be directly accessed across CPUs. Hence if we want to do global
  * control, we need cross CPU calls. on_each_cpu() can help us, but we
  * can not make sure this function is called with interrupts enabled. So
  * here we pause local counters and then grab a rwlock and leave the
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index ae167df73ddd..d2112d3cf115 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -410,7 +410,7 @@ unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
         if (!kallsyms_lookup_size_offset(pc, &size, &ofs))
                 return 0;
         /*
-         * Return ra if an exception occured at the first instruction
+         * Return ra if an exception occurred at the first instruction
          */
         if (unlikely(ofs == 0)) {
                 pc = *ra;
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index c0e81418ba21..1ec56e635d04 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -120,7 +120,7 @@ static void vsmp_send_ipi_single(int cpu, unsigned int action)
 
         local_irq_save(flags);
 
-        vpflags = dvpe();       /* cant access the other CPU's registers whilst MVPE enabled */
+        vpflags = dvpe();       /* can't access the other CPU's registers whilst MVPE enabled */
 
         switch (action) {
         case SMP_CALL_FUNCTION:
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index fb7497405510..1083ad4e1017 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -102,7 +102,7 @@ static __init int cpu_has_mfc0_count_bug(void)
         case CPU_R4400SC:
         case CPU_R4400MC:
                 /*
-                 * The published errata for the R4400 upto 3.0 say the CPU
+                 * The published errata for the R4400 up to 3.0 say the CPU
                  * has the mfc0 from count bug.
                  */
                 if ((current_cpu_data.processor_id & 0xff) <= 0x30)
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index ab52b7cf3b6b..dbb6b408f001 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -19,7 +19,7 @@
  * VPE support module
  *
  * Provides support for loading a MIPS SP program on VPE1.
- * The SP enviroment is rather simple, no tlb's.  It needs to be relocatable
+ * The SP environment is rather simple, no tlb's.  It needs to be relocatable
  * (or partially linked). You should initialise your stack in the startup
  * code. This loader looks for the symbol __start and sets up
  * execution to resume from there. The MIPS SDE kit contains suitable examples.
diff --git a/arch/mips/lib/strnlen_user.S b/arch/mips/lib/strnlen_user.S
index c768e3000616..64457162f7e0 100644
--- a/arch/mips/lib/strnlen_user.S
+++ b/arch/mips/lib/strnlen_user.S
@@ -17,7 +17,7 @@
         .previous
 
 /*
- * Return the size of a string including the ending NUL character upto a
+ * Return the size of a string including the ending NUL character up to a
  * maximum of a1 or 0 in case of error.
  *
  * Note: for performance reasons we deliberately accept that a user may
diff --git a/arch/mips/math-emu/dp_fsp.c b/arch/mips/math-emu/dp_fsp.c
index 1dfbd92ba9d0..daed6834dc15 100644
--- a/arch/mips/math-emu/dp_fsp.c
+++ b/arch/mips/math-emu/dp_fsp.c
@@ -62,7 +62,7 @@ ieee754dp ieee754dp_fsp(ieee754sp x)
                 break;
         }
 
-        /* CANT possibly overflow,underflow, or need rounding
+        /* CAN'T possibly overflow,underflow, or need rounding
          */
 
         /* drop the hidden bit */
diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c
index aa566e785f5a..09175f461920 100644
--- a/arch/mips/math-emu/dp_mul.c
+++ b/arch/mips/math-emu/dp_mul.c
@@ -104,7 +104,7 @@ ieee754dp ieee754dp_mul(ieee754dp x, ieee754dp y)
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
                 break;
         }
-        /* rm = xm * ym, re = xe+ye basicly */
+        /* rm = xm * ym, re = xe+ye basically */
         assert(xm & DP_HIDDEN_BIT);
         assert(ym & DP_HIDDEN_BIT);
         {
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index 36d975ae08f8..3c4a8c5ba7f2 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -32,7 +32,7 @@
  * not change cp0_epc due to the instruction
  *
  * According to the spec:
- * 1) it shouldnt be a branch :-)
+ * 1) it shouldn't be a branch :-)
  * 2) it can be a COP instruction :-(
  * 3) if we are tring to run a protected memory space we must take
  *    special care on memory access instructions :-(
diff --git a/arch/mips/math-emu/sp_mul.c b/arch/mips/math-emu/sp_mul.c
index c06bb4022be5..2722a2570ea4 100644
--- a/arch/mips/math-emu/sp_mul.c
+++ b/arch/mips/math-emu/sp_mul.c
@@ -104,7 +104,7 @@ ieee754sp ieee754sp_mul(ieee754sp x, ieee754sp y)
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
                 break;
         }
-        /* rm = xm * ym, re = xe+ye basicly */
+        /* rm = xm * ym, re = xe+ye basically */
         assert(xm & SP_HIDDEN_BIT);
         assert(ym & SP_HIDDEN_BIT);
 
diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S
index 2d08268bb705..89c412bc4b64 100644
--- a/arch/mips/mm/cex-sb1.S
+++ b/arch/mips/mm/cex-sb1.S
@@ -79,7 +79,7 @@ LEAF(except_vec2_sb1)
 recovered_dcache:
         /*
          * Unlock CacheErr-D (which in turn unlocks CacheErr-DPA).
-         * Ought to log the occurence of this recovered dcache error.
+         * Ought to log the occurrence of this recovered dcache error.
          */
         b       recovered
          mtc0   $0,C0_CERR_D
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 04f9e17db9d0..5ef294fbb6e7 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -352,7 +352,7 @@ static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
 
 /*
  * Write random or indexed TLB entry, and care about the hazards from
- * the preceeding mtc0 and for the following eret.
+ * the preceding mtc0 and for the following eret.
  */
 enum tlb_write_entry { tlb_random, tlb_indexed };
 
diff --git a/arch/mips/mti-malta/malta-smtc.c b/arch/mips/mti-malta/malta-smtc.c
index e67891521ac1..49a38b09a488 100644
--- a/arch/mips/mti-malta/malta-smtc.c
+++ b/arch/mips/mti-malta/malta-smtc.c
@@ -130,7 +130,7 @@ int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
          * cleared in the affinity mask, there will never be any
          * interrupt forwarding.  But as soon as a program or operator
          * sets affinity for one of the related IRQs, we need to make
-         * sure that we don't ever try to forward across the VPE boundry,
+         * sure that we don't ever try to forward across the VPE boundary,
          * at least not until we engineer a system where the interrupt
          * _ack() or _end() function can somehow know that it corresponds
          * to an interrupt taken on another VPE, and perform the appropriate
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 68798f869c0f..8fbfbf2b931c 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -344,7 +344,7 @@ static irqreturn_t bpci_interrupt(int irq, void *dev_id)
  *                              PCI_ACCESS_WRITE and PCI_ACCESS_READ.
  *
  *               bus          - pointer to the bus number of the device to
- *                              be targetted for the configuration cycle.
+ *                              be targeted for the configuration cycle.
  *                              The only element of the pci_bus structure
  *                              used is bus->number. This argument determines
  *                              if the configuration access will be Type 0 or
@@ -354,7 +354,7 @@ static irqreturn_t bpci_interrupt(int irq, void *dev_id)
  *
  *               devfn        - this is an 8-bit field. The lower three bits
  *                              specify the function number of the device to
- *                              be targetted for the configuration cycle, with
+ *                              be targeted for the configuration cycle, with
  *                              all three-bit combinations being legal. The
  *                              upper five bits specify the device number,
  *                              with legal values being 10 to 31.
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index 6f5e24c6ae67..af8c31996965 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -210,7 +210,7 @@ static int __init bcm1480_pcibios_init(void)
         PCIBIOS_MIN_IO = 0x00008000UL;
         PCIBIOS_MIN_MEM = 0x01000000UL;
 
-        /* Set I/O resource limits. - unlimited for now to accomodate HT */
+        /* Set I/O resource limits. - unlimited for now to accommodate HT */
         ioport_resource.end = 0xffffffffUL;
         iomem_resource.end = 0xffffffffUL;
 
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 2d74fc9ae3ba..ed1c54284b8f 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -441,7 +441,7 @@ static void octeon_pci_initialize(void)
 
         /*
          * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
-         * in PCI-X mode to allow four oustanding splits. Otherwise,
+         * in PCI-X mode to allow four outstanding splits. Otherwise,
          * should not change from its reset value. Don't write PCI_CFG19
          * in PCI mode (0x82000001 reset value), write it to 0x82000004
          * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
@@ -515,7 +515,7 @@ static void octeon_pci_initialize(void)
 #endif  /* USE_OCTEON_INTERNAL_ARBITER */
 
         /*
-         * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE,
+         * Preferably written to 1 to set MLTD. [RDSATI,TRTAE,
          * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
          * 1..7.
          */
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 38bc28005b4a..33bba7bff258 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -125,7 +125,7 @@ void __devinit register_pci_controller(struct pci_controller *hose)
         hose_tail = &hose->next;
 
         /*
-         * Do not panic here but later - this might hapen before console init.
+         * Do not panic here but later - this might happen before console init.
          */
         if (!hose->io_map_base) {
                 printk(KERN_WARNING
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
index fb37a10e0309..2413ea67877e 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
@@ -239,7 +239,7 @@ void __init prom_init(void)
 #ifdef CONFIG_PMCTWILED
         /*
          * Setup LED states before the subsys_initcall loads other
-         * dependant drivers/modules.
+         * dependent drivers/modules.
          */
         pmctwiled_setup();
 #endif
diff --git a/arch/mips/pnx833x/common/platform.c b/arch/mips/pnx833x/common/platform.c
index ce45df17fd09..87167dcc79fa 100644
--- a/arch/mips/pnx833x/common/platform.c
+++ b/arch/mips/pnx833x/common/platform.c
@@ -165,7 +165,7 @@ static struct i2c_pnx0105_dev pnx833x_i2c_dev[] = {
         {
                 .base = PNX833X_I2C0_PORTS_START,
                 .irq = -1, /* should be PNX833X_PIC_I2C0_INT but polling is faster */
-                .clock = 6,     /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Prefered HDCP) */
+                .clock = 6,     /* 0 == 400 kHz, 4 == 100 kHz(Maximum HDMI), 6 = 50kHz(Preferred HDCP) */
                 .bus_addr = 0,  /* no slave support */
         },
         {
diff --git a/arch/mips/sgi-ip27/Kconfig b/arch/mips/sgi-ip27/Kconfig
index 5e960ae9735a..bc5e9769bb73 100644
--- a/arch/mips/sgi-ip27/Kconfig
+++ b/arch/mips/sgi-ip27/Kconfig
@@ -1,7 +1,7 @@
 #config SGI_SN0_XXL
 #       bool "IP27 XXL"
 #       depends on SGI_IP27
-#         This options adds support for userspace processes upto 16TB size.
+#         This options adds support for userspace processes up to 16TB size.
 #         Normally the limit is just .5TB.
 
 choice
diff --git a/arch/mips/sgi-ip27/TODO b/arch/mips/sgi-ip27/TODO
index 19f1512c8f2e..160857ff1483 100644
--- a/arch/mips/sgi-ip27/TODO
+++ b/arch/mips/sgi-ip27/TODO
@@ -13,7 +13,7 @@ being invoked on all nodes in ip27-memory.c.
 9. start_thread must turn off UX64 ... and define tlb_refill_debug.
 10. Need a bad pmd table, bad pte table. __bad_pmd_table/__bad_pagetable
 does not agree with pgd_bad/pmd_bad.
-11. All intrs (ip27_do_irq handlers) are targetted at cpu A on the node.
+11. All intrs (ip27_do_irq handlers) are targeted at cpu A on the node.
 This might need to change later. Only the timer intr is set up to be
 received on both Cpu A and B. (ip27_do_irq()/bridge_startup())
 13. Cache flushing (specially the SMP version) has to be investigated.
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index 51d3a4f2d7e1..923c080f77bd 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -93,7 +93,7 @@ static void __cpuinit per_hub_init(cnodeid_t cnode)
 
         /*
          * Some interrupts are reserved by hardware or by software convention.
-         * Mark these as reserved right away so they won't be used accidently
+         * Mark these as reserved right away so they won't be used accidentally
          * later.
          */
         for (i = 0; i <= BASE_PCI_IRQ; i++) {
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 11488719dd97..0a04603d577c 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -41,7 +41,7 @@
  * Linux has a controller-independent x86 interrupt architecture.
  * every controller has a 'controller-template', that is used
  * by the main code to do the right thing. Each driver-visible
- * interrupt source is transparently wired to the apropriate
+ * interrupt source is transparently wired to the appropriate
  * controller. Thus drivers need not be aware of the
  * interrupt-controller.
  *