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-rw-r--r--arch/mips/Kbuild.platforms1
-rw-r--r--arch/mips/Kconfig23
-rw-r--r--arch/mips/ath79/Kconfig20
-rw-r--r--arch/mips/ath79/Makefile1
-rw-r--r--arch/mips/ath79/clock.c78
-rw-r--r--arch/mips/ath79/common.c4
-rw-r--r--arch/mips/ath79/dev-common.c9
-rw-r--r--arch/mips/ath79/dev-usb.c126
-rw-r--r--arch/mips/ath79/dev-wmac.c30
-rw-r--r--arch/mips/ath79/early_printk.c2
-rw-r--r--arch/mips/ath79/gpio.c52
-rw-r--r--arch/mips/ath79/irq.c187
-rw-r--r--arch/mips/ath79/mach-ap136.c156
-rw-r--r--arch/mips/ath79/machtypes.h1
-rw-r--r--arch/mips/ath79/pci.c165
-rw-r--r--arch/mips/ath79/pci.h1
-rw-r--r--arch/mips/ath79/setup.c18
-rw-r--r--arch/mips/bcm47xx/nvram.c159
-rw-r--r--arch/mips/bcm47xx/setup.c6
-rw-r--r--arch/mips/bcm47xx/sprom.c22
-rw-r--r--arch/mips/bcm63xx/early_printk.c4
-rw-r--r--arch/mips/configs/ath79_defconfig1
-rw-r--r--arch/mips/configs/rt305x_defconfig167
-rw-r--r--arch/mips/include/asm/cpu-features.h7
-rw-r--r--arch/mips/include/asm/cpu.h5
-rw-r--r--arch/mips/include/asm/gic.h1
-rw-r--r--arch/mips/include/asm/hazards.h2
-rw-r--r--arch/mips/include/asm/irq_cpu.h6
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h124
-rw-r--r--arch/mips/include/asm/mach-ath79/ath79.h17
-rw-r--r--arch/mips/include/asm/mach-ath79/irq.h27
-rw-r--r--arch/mips/include/asm/mach-ath79/pci.h28
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h (renamed from arch/mips/include/asm/mach-bcm47xx/nvram.h)13
-rw-r--r--arch/mips/include/asm/mach-lantiq/lantiq.h2
-rw-r--r--arch/mips/include/asm/mach-ralink/ralink_regs.h39
-rw-r--r--arch/mips/include/asm/mach-ralink/rt305x.h139
-rw-r--r--arch/mips/include/asm/mach-ralink/war.h25
-rw-r--r--arch/mips/include/asm/mips-boards/generic.h28
-rw-r--r--arch/mips/include/asm/mipsregs.h311
-rw-r--r--arch/mips/include/asm/netlogic/mips-extns.h79
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h2
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h12
-rw-r--r--arch/mips/include/asm/netlogic/xlr/pic.h48
-rw-r--r--arch/mips/include/asm/pci.h5
-rw-r--r--arch/mips/include/asm/time.h2
-rw-r--r--arch/mips/kernel/Makefile32
-rw-r--r--arch/mips/kernel/cpu-probe.c14
-rw-r--r--arch/mips/kernel/csrc-gic.c49
-rw-r--r--arch/mips/kernel/early_printk.c5
-rw-r--r--arch/mips/kernel/irq_cpu.c42
-rw-r--r--arch/mips/kernel/proc.c2
-rw-r--r--arch/mips/kernel/setup.c91
-rw-r--r--arch/mips/kernel/smtc.c1
-rw-r--r--arch/mips/kernel/vpe.c15
-rw-r--r--arch/mips/lantiq/clk.c12
-rw-r--r--arch/mips/lantiq/clk.h7
-rw-r--r--arch/mips/lantiq/falcon/sysctrl.c4
-rw-r--r--arch/mips/lantiq/irq.c105
-rw-r--r--arch/mips/lantiq/xway/clk.c43
-rw-r--r--arch/mips/lantiq/xway/reset.c9
-rw-r--r--arch/mips/lantiq/xway/sysctrl.c15
-rw-r--r--arch/mips/loongson1/common/prom.c2
-rw-r--r--arch/mips/mm/c-r4k.c1
-rw-r--r--arch/mips/mm/tlbex.c1
-rw-r--r--arch/mips/mti-malta/malta-time.c83
-rw-r--r--arch/mips/netlogic/common/irq.c41
-rw-r--r--arch/mips/netlogic/common/smp.c8
-rw-r--r--arch/mips/netlogic/common/smpboot.S6
-rw-r--r--arch/mips/netlogic/common/time.c56
-rw-r--r--arch/mips/netlogic/xlp/wakeup.c35
-rw-r--r--arch/mips/netlogic/xlr/fmn-config.c2
-rw-r--r--arch/mips/netlogic/xlr/platform.c2
-rw-r--r--arch/mips/netlogic/xlr/setup.c2
-rw-r--r--arch/mips/oprofile/common.c1
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c4
-rw-r--r--arch/mips/pci/pci-ar71xx.c194
-rw-r--r--arch/mips/pci/pci-ar724x.c304
-rw-r--r--arch/mips/pci/pci-lantiq.c12
-rw-r--r--arch/mips/pci/pci-xlp.c124
-rw-r--r--arch/mips/pci/pci.c15
-rw-r--r--arch/mips/ralink/Kconfig32
-rw-r--r--arch/mips/ralink/Makefile15
-rw-r--r--arch/mips/ralink/Platform10
-rw-r--r--arch/mips/ralink/clk.c72
-rw-r--r--arch/mips/ralink/common.h44
-rw-r--r--arch/mips/ralink/dts/Makefile1
-rw-r--r--arch/mips/ralink/dts/rt3050.dtsi106
-rw-r--r--arch/mips/ralink/dts/rt3052_eval.dts52
-rw-r--r--arch/mips/ralink/early_printk.c44
-rw-r--r--arch/mips/ralink/irq.c180
-rw-r--r--arch/mips/ralink/of.c107
-rw-r--r--arch/mips/ralink/prom.c69
-rw-r--r--arch/mips/ralink/reset.c44
-rw-r--r--arch/mips/ralink/rt305x.c242
-rw-r--r--arch/mips/sgi-ip27/ip27-console.c2
-rw-r--r--arch/mips/txx9/generic/setup.c8
96 files changed, 3661 insertions, 861 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 5c088494e046..4b597d91a8d5 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -21,6 +21,7 @@ platforms += netlogic
21platforms += pmcs-msp71xx 21platforms += pmcs-msp71xx
22platforms += pnx833x 22platforms += pnx833x
23platforms += powertv 23platforms += powertv
24platforms += ralink
24platforms += rb532 25platforms += rb532
25platforms += sgi-ip22 26platforms += sgi-ip22
26platforms += sgi-ip27 27platforms += sgi-ip27
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index af4e04fde0b4..6fe9a188c49f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -107,12 +107,14 @@ config ATH79
107config BCM47XX 107config BCM47XX
108 bool "Broadcom BCM47XX based boards" 108 bool "Broadcom BCM47XX based boards"
109 select ARCH_WANT_OPTIONAL_GPIOLIB 109 select ARCH_WANT_OPTIONAL_GPIOLIB
110 select BOOT_RAW
110 select CEVT_R4K 111 select CEVT_R4K
111 select CSRC_R4K 112 select CSRC_R4K
112 select DMA_NONCOHERENT 113 select DMA_NONCOHERENT
113 select FW_CFE 114 select FW_CFE
114 select HW_HAS_PCI 115 select HW_HAS_PCI
115 select IRQ_CPU 116 select IRQ_CPU
117 select NO_EXCEPT_FILL
116 select SYS_SUPPORTS_32BIT_KERNEL 118 select SYS_SUPPORTS_32BIT_KERNEL
117 select SYS_SUPPORTS_LITTLE_ENDIAN 119 select SYS_SUPPORTS_LITTLE_ENDIAN
118 select SYS_HAS_EARLY_PRINTK 120 select SYS_HAS_EARLY_PRINTK
@@ -294,6 +296,7 @@ config MIPS_MALTA
294 select BOOT_RAW 296 select BOOT_RAW
295 select CEVT_R4K 297 select CEVT_R4K
296 select CSRC_R4K 298 select CSRC_R4K
299 select CSRC_GIC
297 select DMA_NONCOHERENT 300 select DMA_NONCOHERENT
298 select GENERIC_ISA_DMA 301 select GENERIC_ISA_DMA
299 select HAVE_PCSPKR_PLATFORM 302 select HAVE_PCSPKR_PLATFORM
@@ -425,6 +428,22 @@ config POWERTV
425 help 428 help
426 This enables support for the Cisco PowerTV Platform. 429 This enables support for the Cisco PowerTV Platform.
427 430
431config RALINK
432 bool "Ralink based machines"
433 select CEVT_R4K
434 select CSRC_R4K
435 select BOOT_RAW
436 select DMA_NONCOHERENT
437 select IRQ_CPU
438 select USE_OF
439 select SYS_HAS_CPU_MIPS32_R1
440 select SYS_HAS_CPU_MIPS32_R2
441 select SYS_SUPPORTS_32BIT_KERNEL
442 select SYS_SUPPORTS_LITTLE_ENDIAN
443 select SYS_HAS_EARLY_PRINTK
444 select HAVE_MACH_CLKDEV
445 select CLKDEV_LOOKUP
446
428config SGI_IP22 447config SGI_IP22
429 bool "SGI IP22 (Indy/Indigo2)" 448 bool "SGI IP22 (Indy/Indigo2)"
430 select FW_ARC 449 select FW_ARC
@@ -837,6 +856,7 @@ source "arch/mips/lantiq/Kconfig"
837source "arch/mips/lasat/Kconfig" 856source "arch/mips/lasat/Kconfig"
838source "arch/mips/pmcs-msp71xx/Kconfig" 857source "arch/mips/pmcs-msp71xx/Kconfig"
839source "arch/mips/powertv/Kconfig" 858source "arch/mips/powertv/Kconfig"
859source "arch/mips/ralink/Kconfig"
840source "arch/mips/sgi-ip27/Kconfig" 860source "arch/mips/sgi-ip27/Kconfig"
841source "arch/mips/sibyte/Kconfig" 861source "arch/mips/sibyte/Kconfig"
842source "arch/mips/txx9/Kconfig" 862source "arch/mips/txx9/Kconfig"
@@ -917,6 +937,9 @@ config CSRC_POWERTV
917config CSRC_R4K 937config CSRC_R4K
918 bool 938 bool
919 939
940config CSRC_GIC
941 bool
942
920config CSRC_SB1250 943config CSRC_SB1250
921 bool 944 bool
922 945
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index f44feee2d67f..3995e31a73e2 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -14,6 +14,18 @@ config ATH79_MACH_AP121
14 Say 'Y' here if you want your kernel to support the 14 Say 'Y' here if you want your kernel to support the
15 Atheros AP121 reference board. 15 Atheros AP121 reference board.
16 16
17config ATH79_MACH_AP136
18 bool "Atheros AP136 reference board"
19 select SOC_QCA955X
20 select ATH79_DEV_GPIO_BUTTONS
21 select ATH79_DEV_LEDS_GPIO
22 select ATH79_DEV_SPI
23 select ATH79_DEV_USB
24 select ATH79_DEV_WMAC
25 help
26 Say 'Y' here if you want your kernel to support the
27 Atheros AP136 reference board.
28
17config ATH79_MACH_AP81 29config ATH79_MACH_AP81
18 bool "Atheros AP81 reference board" 30 bool "Atheros AP81 reference board"
19 select SOC_AR913X 31 select SOC_AR913X
@@ -88,6 +100,12 @@ config SOC_AR934X
88 select PCI_AR724X if PCI 100 select PCI_AR724X if PCI
89 def_bool n 101 def_bool n
90 102
103config SOC_QCA955X
104 select USB_ARCH_HAS_EHCI
105 select HW_HAS_PCI
106 select PCI_AR724X if PCI
107 def_bool n
108
91config PCI_AR724X 109config PCI_AR724X
92 def_bool n 110 def_bool n
93 111
@@ -104,7 +122,7 @@ config ATH79_DEV_USB
104 def_bool n 122 def_bool n
105 123
106config ATH79_DEV_WMAC 124config ATH79_DEV_WMAC
107 depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X) 125 depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
108 def_bool n 126 def_bool n
109 127
110endif 128endif
diff --git a/arch/mips/ath79/Makefile b/arch/mips/ath79/Makefile
index 2b54d98263f3..5c9ff692ff3c 100644
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_ATH79_DEV_WMAC) += dev-wmac.o
27# Machines 27# Machines
28# 28#
29obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o 29obj-$(CONFIG_ATH79_MACH_AP121) += mach-ap121.o
30obj-$(CONFIG_ATH79_MACH_AP136) += mach-ap136.o
30obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o 31obj-$(CONFIG_ATH79_MACH_AP81) += mach-ap81.o
31obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o 32obj-$(CONFIG_ATH79_MACH_DB120) += mach-db120.o
32obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o 33obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 8c1b8bf9b32f..765ef30e3e1c 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(void)
295 iounmap(dpll_base); 295 iounmap(dpll_base);
296} 296}
297 297
298static void __init qca955x_clocks_init(void)
299{
300 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
301 u32 cpu_pll, ddr_pll;
302 u32 bootstrap;
303
304 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
305 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
306 ath79_ref_clk.rate = 40 * 1000 * 1000;
307 else
308 ath79_ref_clk.rate = 25 * 1000 * 1000;
309
310 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
311 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
312 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
313 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
314 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
315 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
316 QCA955X_PLL_CPU_CONFIG_NINT_MASK;
317 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
318 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
319
320 cpu_pll = nint * ath79_ref_clk.rate / ref_div;
321 cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
322 cpu_pll /= (1 << out_div);
323
324 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
325 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
326 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
327 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
328 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
329 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
330 QCA955X_PLL_DDR_CONFIG_NINT_MASK;
331 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
332 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
333
334 ddr_pll = nint * ath79_ref_clk.rate / ref_div;
335 ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
336 ddr_pll /= (1 << out_div);
337
338 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
339
340 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
341 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
342
343 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
344 ath79_cpu_clk.rate = ath79_ref_clk.rate;
345 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
346 ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
347 else
348 ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
349
350 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
351 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
352
353 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
354 ath79_ddr_clk.rate = ath79_ref_clk.rate;
355 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
356 ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
357 else
358 ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
359
360 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
361 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
362
363 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
364 ath79_ahb_clk.rate = ath79_ref_clk.rate;
365 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
366 ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
367 else
368 ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
369
370 ath79_wdt_clk.rate = ath79_ref_clk.rate;
371 ath79_uart_clk.rate = ath79_ref_clk.rate;
372}
373
298void __init ath79_clocks_init(void) 374void __init ath79_clocks_init(void)
299{ 375{
300 if (soc_is_ar71xx()) 376 if (soc_is_ar71xx())
@@ -307,6 +383,8 @@ void __init ath79_clocks_init(void)
307 ar933x_clocks_init(); 383 ar933x_clocks_init();
308 else if (soc_is_ar934x()) 384 else if (soc_is_ar934x())
309 ar934x_clocks_init(); 385 ar934x_clocks_init();
386 else if (soc_is_qca955x())
387 qca955x_clocks_init();
310 else 388 else
311 BUG(); 389 BUG();
312 390
diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
index 5a4adfc9d79d..eb3966cd8cfc 100644
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -72,6 +72,8 @@ void ath79_device_reset_set(u32 mask)
72 reg = AR933X_RESET_REG_RESET_MODULE; 72 reg = AR933X_RESET_REG_RESET_MODULE;
73 else if (soc_is_ar934x()) 73 else if (soc_is_ar934x())
74 reg = AR934X_RESET_REG_RESET_MODULE; 74 reg = AR934X_RESET_REG_RESET_MODULE;
75 else if (soc_is_qca955x())
76 reg = QCA955X_RESET_REG_RESET_MODULE;
75 else 77 else
76 BUG(); 78 BUG();
77 79
@@ -98,6 +100,8 @@ void ath79_device_reset_clear(u32 mask)
98 reg = AR933X_RESET_REG_RESET_MODULE; 100 reg = AR933X_RESET_REG_RESET_MODULE;
99 else if (soc_is_ar934x()) 101 else if (soc_is_ar934x())
100 reg = AR934X_RESET_REG_RESET_MODULE; 102 reg = AR934X_RESET_REG_RESET_MODULE;
103 else if (soc_is_qca955x())
104 reg = QCA955X_RESET_REG_RESET_MODULE;
101 else 105 else
102 BUG(); 106 BUG();
103 107
diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
index 45efc63b08b6..9516aab27139 100644
--- a/arch/mips/ath79/dev-common.c
+++ b/arch/mips/ath79/dev-common.c
@@ -36,7 +36,7 @@ static struct resource ath79_uart_resources[] = {
36static struct plat_serial8250_port ath79_uart_data[] = { 36static struct plat_serial8250_port ath79_uart_data[] = {
37 { 37 {
38 .mapbase = AR71XX_UART_BASE, 38 .mapbase = AR71XX_UART_BASE,
39 .irq = ATH79_MISC_IRQ_UART, 39 .irq = ATH79_MISC_IRQ(3),
40 .flags = AR71XX_UART_FLAGS, 40 .flags = AR71XX_UART_FLAGS,
41 .iotype = UPIO_MEM32, 41 .iotype = UPIO_MEM32,
42 .regshift = 2, 42 .regshift = 2,
@@ -62,8 +62,8 @@ static struct resource ar933x_uart_resources[] = {
62 .flags = IORESOURCE_MEM, 62 .flags = IORESOURCE_MEM,
63 }, 63 },
64 { 64 {
65 .start = ATH79_MISC_IRQ_UART, 65 .start = ATH79_MISC_IRQ(3),
66 .end = ATH79_MISC_IRQ_UART, 66 .end = ATH79_MISC_IRQ(3),
67 .flags = IORESOURCE_IRQ, 67 .flags = IORESOURCE_IRQ,
68 }, 68 },
69}; 69};
@@ -90,7 +90,8 @@ void __init ath79_register_uart(void)
90 if (soc_is_ar71xx() || 90 if (soc_is_ar71xx() ||
91 soc_is_ar724x() || 91 soc_is_ar724x() ||
92 soc_is_ar913x() || 92 soc_is_ar913x() ||
93 soc_is_ar934x()) { 93 soc_is_ar934x() ||
94 soc_is_qca955x()) {
94 ath79_uart_data[0].uartclk = clk_get_rate(clk); 95 ath79_uart_data[0].uartclk = clk_get_rate(clk);
95 platform_device_register(&ath79_uart_device); 96 platform_device_register(&ath79_uart_device);
96 } else if (soc_is_ar933x()) { 97 } else if (soc_is_ar933x()) {
diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c
index bd2bc108e1b5..8227265bcc2d 100644
--- a/arch/mips/ath79/dev-usb.c
+++ b/arch/mips/ath79/dev-usb.c
@@ -25,29 +25,11 @@
25#include "common.h" 25#include "common.h"
26#include "dev-usb.h" 26#include "dev-usb.h"
27 27
28static struct resource ath79_ohci_resources[2]; 28static u64 ath79_usb_dmamask = DMA_BIT_MASK(32);
29
30static u64 ath79_ohci_dmamask = DMA_BIT_MASK(32);
31 29
32static struct usb_ohci_pdata ath79_ohci_pdata = { 30static struct usb_ohci_pdata ath79_ohci_pdata = {
33}; 31};
34 32
35static struct platform_device ath79_ohci_device = {
36 .name = "ohci-platform",
37 .id = -1,
38 .resource = ath79_ohci_resources,
39 .num_resources = ARRAY_SIZE(ath79_ohci_resources),
40 .dev = {
41 .dma_mask = &ath79_ohci_dmamask,
42 .coherent_dma_mask = DMA_BIT_MASK(32),
43 .platform_data = &ath79_ohci_pdata,
44 },
45};
46
47static struct resource ath79_ehci_resources[2];
48
49static u64 ath79_ehci_dmamask = DMA_BIT_MASK(32);
50
51static struct usb_ehci_pdata ath79_ehci_pdata_v1 = { 33static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
52 .has_synopsys_hc_bug = 1, 34 .has_synopsys_hc_bug = 1,
53}; 35};
@@ -57,22 +39,16 @@ static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
57 .has_tt = 1, 39 .has_tt = 1,
58}; 40};
59 41
60static struct platform_device ath79_ehci_device = { 42static void __init ath79_usb_register(const char *name, int id,
61 .name = "ehci-platform", 43 unsigned long base, unsigned long size,
62 .id = -1, 44 int irq, const void *data,
63 .resource = ath79_ehci_resources, 45 size_t data_size)
64 .num_resources = ARRAY_SIZE(ath79_ehci_resources),
65 .dev = {
66 .dma_mask = &ath79_ehci_dmamask,
67 .coherent_dma_mask = DMA_BIT_MASK(32),
68 },
69};
70
71static void __init ath79_usb_init_resource(struct resource res[2],
72 unsigned long base,
73 unsigned long size,
74 int irq)
75{ 46{
47 struct resource res[2];
48 struct platform_device *pdev;
49
50 memset(res, 0, sizeof(res));
51
76 res[0].flags = IORESOURCE_MEM; 52 res[0].flags = IORESOURCE_MEM;
77 res[0].start = base; 53 res[0].start = base;
78 res[0].end = base + size - 1; 54 res[0].end = base + size - 1;
@@ -80,6 +56,19 @@ static void __init ath79_usb_init_resource(struct resource res[2],
80 res[1].flags = IORESOURCE_IRQ; 56 res[1].flags = IORESOURCE_IRQ;
81 res[1].start = irq; 57 res[1].start = irq;
82 res[1].end = irq; 58 res[1].end = irq;
59
60 pdev = platform_device_register_resndata(NULL, name, id,
61 res, ARRAY_SIZE(res),
62 data, data_size);
63
64 if (IS_ERR(pdev)) {
65 pr_err("ath79: unable to register USB at %08lx, err=%d\n",
66 base, (int) PTR_ERR(pdev));
67 return;
68 }
69
70 pdev->dev.dma_mask = &ath79_usb_dmamask;
71 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
83} 72}
84 73
85#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \ 74#define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
@@ -106,14 +95,15 @@ static void __init ath79_usb_setup(void)
106 95
107 mdelay(900); 96 mdelay(900);
108 97
109 ath79_usb_init_resource(ath79_ohci_resources, AR71XX_OHCI_BASE, 98 ath79_usb_register("ohci-platform", -1,
110 AR71XX_OHCI_SIZE, ATH79_MISC_IRQ_OHCI); 99 AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE,
111 platform_device_register(&ath79_ohci_device); 100 ATH79_MISC_IRQ(6),
101 &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
112 102
113 ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE, 103 ath79_usb_register("ehci-platform", -1,
114 AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB); 104 AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE,
115 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1; 105 ATH79_CPU_IRQ(3),
116 platform_device_register(&ath79_ehci_device); 106 &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1));
117} 107}
118 108
119static void __init ar7240_usb_setup(void) 109static void __init ar7240_usb_setup(void)
@@ -135,9 +125,10 @@ static void __init ar7240_usb_setup(void)
135 125
136 iounmap(usb_ctrl_base); 126 iounmap(usb_ctrl_base);
137 127
138 ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE, 128 ath79_usb_register("ohci-platform", -1,
139 AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB); 129 AR7240_OHCI_BASE, AR7240_OHCI_SIZE,
140 platform_device_register(&ath79_ohci_device); 130 ATH79_CPU_IRQ(3),
131 &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
141} 132}
142 133
143static void __init ar724x_usb_setup(void) 134static void __init ar724x_usb_setup(void)
@@ -151,10 +142,10 @@ static void __init ar724x_usb_setup(void)
151 ath79_device_reset_clear(AR724X_RESET_USB_PHY); 142 ath79_device_reset_clear(AR724X_RESET_USB_PHY);
152 mdelay(10); 143 mdelay(10);
153 144
154 ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE, 145 ath79_usb_register("ehci-platform", -1,
155 AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB); 146 AR724X_EHCI_BASE, AR724X_EHCI_SIZE,
156 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; 147 ATH79_CPU_IRQ(3),
157 platform_device_register(&ath79_ehci_device); 148 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
158} 149}
159 150
160static void __init ar913x_usb_setup(void) 151static void __init ar913x_usb_setup(void)
@@ -168,10 +159,10 @@ static void __init ar913x_usb_setup(void)
168 ath79_device_reset_clear(AR913X_RESET_USB_PHY); 159 ath79_device_reset_clear(AR913X_RESET_USB_PHY);
169 mdelay(10); 160 mdelay(10);
170 161
171 ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE, 162 ath79_usb_register("ehci-platform", -1,
172 AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB); 163 AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
173 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; 164 ATH79_CPU_IRQ(3),
174 platform_device_register(&ath79_ehci_device); 165 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
175} 166}
176 167
177static void __init ar933x_usb_setup(void) 168static void __init ar933x_usb_setup(void)
@@ -185,10 +176,10 @@ static void __init ar933x_usb_setup(void)
185 ath79_device_reset_clear(AR933X_RESET_USB_PHY); 176 ath79_device_reset_clear(AR933X_RESET_USB_PHY);
186 mdelay(10); 177 mdelay(10);
187 178
188 ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE, 179 ath79_usb_register("ehci-platform", -1,
189 AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB); 180 AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
190 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; 181 ATH79_CPU_IRQ(3),
191 platform_device_register(&ath79_ehci_device); 182 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
192} 183}
193 184
194static void __init ar934x_usb_setup(void) 185static void __init ar934x_usb_setup(void)
@@ -211,10 +202,23 @@ static void __init ar934x_usb_setup(void)
211 ath79_device_reset_clear(AR934X_RESET_USB_HOST); 202 ath79_device_reset_clear(AR934X_RESET_USB_HOST);
212 udelay(1000); 203 udelay(1000);
213 204
214 ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE, 205 ath79_usb_register("ehci-platform", -1,
215 AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB); 206 AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
216 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2; 207 ATH79_CPU_IRQ(3),
217 platform_device_register(&ath79_ehci_device); 208 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
209}
210
211static void __init qca955x_usb_setup(void)
212{
213 ath79_usb_register("ehci-platform", 0,
214 QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
215 ATH79_IP3_IRQ(0),
216 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
217
218 ath79_usb_register("ehci-platform", 1,
219 QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
220 ATH79_IP3_IRQ(1),
221 &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
218} 222}
219 223
220void __init ath79_register_usb(void) 224void __init ath79_register_usb(void)
@@ -231,6 +235,8 @@ void __init ath79_register_usb(void)
231 ar933x_usb_setup(); 235 ar933x_usb_setup();
232 else if (soc_is_ar934x()) 236 else if (soc_is_ar934x())
233 ar934x_usb_setup(); 237 ar934x_usb_setup();
238 else if (soc_is_qca955x())
239 qca955x_usb_setup();
234 else 240 else
235 BUG(); 241 BUG();
236} 242}
diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c
index d6d893c16ad4..da190b1b87ce 100644
--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
@@ -55,8 +55,8 @@ static void __init ar913x_wmac_setup(void)
55 55
56 ath79_wmac_resources[0].start = AR913X_WMAC_BASE; 56 ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
57 ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1; 57 ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
58 ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; 58 ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
59 ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; 59 ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
60} 60}
61 61
62 62
@@ -83,8 +83,8 @@ static void __init ar933x_wmac_setup(void)
83 83
84 ath79_wmac_resources[0].start = AR933X_WMAC_BASE; 84 ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
85 ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; 85 ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
86 ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; 86 ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
87 ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; 87 ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
88 88
89 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); 89 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
90 if (t & AR933X_BOOTSTRAP_REF_CLK_40) 90 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
@@ -107,7 +107,7 @@ static void ar934x_wmac_setup(void)
107 ath79_wmac_resources[0].start = AR934X_WMAC_BASE; 107 ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
108 ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; 108 ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
109 ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); 109 ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
110 ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1); 110 ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
111 111
112 t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); 112 t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
113 if (t & AR934X_BOOTSTRAP_REF_CLK_40) 113 if (t & AR934X_BOOTSTRAP_REF_CLK_40)
@@ -116,6 +116,24 @@ static void ar934x_wmac_setup(void)
116 ath79_wmac_data.is_clk_25mhz = true; 116 ath79_wmac_data.is_clk_25mhz = true;
117} 117}
118 118
119static void qca955x_wmac_setup(void)
120{
121 u32 t;
122
123 ath79_wmac_device.name = "qca955x_wmac";
124
125 ath79_wmac_resources[0].start = QCA955X_WMAC_BASE;
126 ath79_wmac_resources[0].end = QCA955X_WMAC_BASE + QCA955X_WMAC_SIZE - 1;
127 ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
128 ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
129
130 t = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
131 if (t & QCA955X_BOOTSTRAP_REF_CLK_40)
132 ath79_wmac_data.is_clk_25mhz = false;
133 else
134 ath79_wmac_data.is_clk_25mhz = true;
135}
136
119void __init ath79_register_wmac(u8 *cal_data) 137void __init ath79_register_wmac(u8 *cal_data)
120{ 138{
121 if (soc_is_ar913x()) 139 if (soc_is_ar913x())
@@ -124,6 +142,8 @@ void __init ath79_register_wmac(u8 *cal_data)
124 ar933x_wmac_setup(); 142 ar933x_wmac_setup();
125 else if (soc_is_ar934x()) 143 else if (soc_is_ar934x())
126 ar934x_wmac_setup(); 144 ar934x_wmac_setup();
145 else if (soc_is_qca955x())
146 qca955x_wmac_setup();
127 else 147 else
128 BUG(); 148 BUG();
129 149
diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
index dc938cb2ba58..b955fafc58ba 100644
--- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c
@@ -74,6 +74,8 @@ static void prom_putchar_init(void)
74 case REV_ID_MAJOR_AR9341: 74 case REV_ID_MAJOR_AR9341:
75 case REV_ID_MAJOR_AR9342: 75 case REV_ID_MAJOR_AR9342:
76 case REV_ID_MAJOR_AR9344: 76 case REV_ID_MAJOR_AR9344:
77 case REV_ID_MAJOR_QCA9556:
78 case REV_ID_MAJOR_QCA9558:
77 _prom_putchar = prom_putchar_ar71xx; 79 _prom_putchar = prom_putchar_ar71xx;
78 break; 80 break;
79 81
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c
index 48fe762d2526..8d025b028bb1 100644
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
@@ -137,49 +137,45 @@ static struct gpio_chip ath79_gpio_chip = {
137 .base = 0, 137 .base = 0,
138}; 138};
139 139
140void ath79_gpio_function_enable(u32 mask) 140static void __iomem *ath79_gpio_get_function_reg(void)
141{ 141{
142 void __iomem *base = ath79_gpio_base; 142 u32 reg = 0;
143 unsigned long flags;
144 143
145 spin_lock_irqsave(&ath79_gpio_lock, flags); 144 if (soc_is_ar71xx() ||
146 145 soc_is_ar724x() ||
147 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask, 146 soc_is_ar913x() ||
148 base + AR71XX_GPIO_REG_FUNC); 147 soc_is_ar933x())
149 /* flush write */ 148 reg = AR71XX_GPIO_REG_FUNC;
150 __raw_readl(base + AR71XX_GPIO_REG_FUNC); 149 else if (soc_is_ar934x())
150 reg = AR934X_GPIO_REG_FUNC;
151 else
152 BUG();
151 153
152 spin_unlock_irqrestore(&ath79_gpio_lock, flags); 154 return ath79_gpio_base + reg;
153} 155}
154 156
155void ath79_gpio_function_disable(u32 mask) 157void ath79_gpio_function_setup(u32 set, u32 clear)
156{ 158{
157 void __iomem *base = ath79_gpio_base; 159 void __iomem *reg = ath79_gpio_get_function_reg();
158 unsigned long flags; 160 unsigned long flags;
159 161
160 spin_lock_irqsave(&ath79_gpio_lock, flags); 162 spin_lock_irqsave(&ath79_gpio_lock, flags);
161 163
162 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask, 164 __raw_writel((__raw_readl(reg) & ~clear) | set, reg);
163 base + AR71XX_GPIO_REG_FUNC);
164 /* flush write */ 165 /* flush write */
165 __raw_readl(base + AR71XX_GPIO_REG_FUNC); 166 __raw_readl(reg);
166 167
167 spin_unlock_irqrestore(&ath79_gpio_lock, flags); 168 spin_unlock_irqrestore(&ath79_gpio_lock, flags);
168} 169}
169 170
170void ath79_gpio_function_setup(u32 set, u32 clear) 171void ath79_gpio_function_enable(u32 mask)
171{ 172{
172 void __iomem *base = ath79_gpio_base; 173 ath79_gpio_function_setup(mask, 0);
173 unsigned long flags; 174}
174
175 spin_lock_irqsave(&ath79_gpio_lock, flags);
176
177 __raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
178 base + AR71XX_GPIO_REG_FUNC);
179 /* flush write */
180 __raw_readl(base + AR71XX_GPIO_REG_FUNC);
181 175
182 spin_unlock_irqrestore(&ath79_gpio_lock, flags); 176void ath79_gpio_function_disable(u32 mask)
177{
178 ath79_gpio_function_setup(0, mask);
183} 179}
184 180
185void __init ath79_gpio_init(void) 181void __init ath79_gpio_init(void)
@@ -198,12 +194,14 @@ void __init ath79_gpio_init(void)
198 ath79_gpio_count = AR933X_GPIO_COUNT; 194 ath79_gpio_count = AR933X_GPIO_COUNT;
199 else if (soc_is_ar934x()) 195 else if (soc_is_ar934x())
200 ath79_gpio_count = AR934X_GPIO_COUNT; 196 ath79_gpio_count = AR934X_GPIO_COUNT;
197 else if (soc_is_qca955x())
198 ath79_gpio_count = QCA955X_GPIO_COUNT;
201 else 199 else
202 BUG(); 200 BUG();
203 201
204 ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); 202 ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
205 ath79_gpio_chip.ngpio = ath79_gpio_count; 203 ath79_gpio_chip.ngpio = ath79_gpio_count;
206 if (soc_is_ar934x()) { 204 if (soc_is_ar934x() || soc_is_qca955x()) {
207 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; 205 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
208 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; 206 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
209 } 207 }
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 90d09fc15398..9c0e1761773f 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -35,44 +35,17 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
35 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & 35 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) &
36 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); 36 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
37 37
38 if (pending & MISC_INT_UART) 38 if (!pending) {
39 generic_handle_irq(ATH79_MISC_IRQ_UART); 39 spurious_interrupt();
40 40 return;
41 else if (pending & MISC_INT_DMA) 41 }
42 generic_handle_irq(ATH79_MISC_IRQ_DMA);
43
44 else if (pending & MISC_INT_PERFC)
45 generic_handle_irq(ATH79_MISC_IRQ_PERFC);
46
47 else if (pending & MISC_INT_TIMER)
48 generic_handle_irq(ATH79_MISC_IRQ_TIMER);
49
50 else if (pending & MISC_INT_TIMER2)
51 generic_handle_irq(ATH79_MISC_IRQ_TIMER2);
52
53 else if (pending & MISC_INT_TIMER3)
54 generic_handle_irq(ATH79_MISC_IRQ_TIMER3);
55
56 else if (pending & MISC_INT_TIMER4)
57 generic_handle_irq(ATH79_MISC_IRQ_TIMER4);
58
59 else if (pending & MISC_INT_OHCI)
60 generic_handle_irq(ATH79_MISC_IRQ_OHCI);
61
62 else if (pending & MISC_INT_ERROR)
63 generic_handle_irq(ATH79_MISC_IRQ_ERROR);
64
65 else if (pending & MISC_INT_GPIO)
66 generic_handle_irq(ATH79_MISC_IRQ_GPIO);
67
68 else if (pending & MISC_INT_WDOG)
69 generic_handle_irq(ATH79_MISC_IRQ_WDOG);
70 42
71 else if (pending & MISC_INT_ETHSW) 43 while (pending) {
72 generic_handle_irq(ATH79_MISC_IRQ_ETHSW); 44 int bit = __ffs(pending);
73 45
74 else 46 generic_handle_irq(ATH79_MISC_IRQ(bit));
75 spurious_interrupt(); 47 pending &= ~BIT(bit);
48 }
76} 49}
77 50
78static void ar71xx_misc_irq_unmask(struct irq_data *d) 51static void ar71xx_misc_irq_unmask(struct irq_data *d)
@@ -130,7 +103,10 @@ static void __init ath79_misc_irq_init(void)
130 103
131 if (soc_is_ar71xx() || soc_is_ar913x()) 104 if (soc_is_ar71xx() || soc_is_ar913x())
132 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; 105 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
133 else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x()) 106 else if (soc_is_ar724x() ||
107 soc_is_ar933x() ||
108 soc_is_ar934x() ||
109 soc_is_qca955x())
134 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; 110 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
135 else 111 else
136 BUG(); 112 BUG();
@@ -141,7 +117,7 @@ static void __init ath79_misc_irq_init(void)
141 handle_level_irq); 117 handle_level_irq);
142 } 118 }
143 119
144 irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler); 120 irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
145} 121}
146 122
147static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc) 123static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
@@ -174,7 +150,89 @@ static void ar934x_ip2_irq_init(void)
174 irq_set_chip_and_handler(i, &dummy_irq_chip, 150 irq_set_chip_and_handler(i, &dummy_irq_chip,
175 handle_level_irq); 151 handle_level_irq);
176 152
177 irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch); 153 irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
154}
155
156static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
157{
158 u32 status;
159
160 disable_irq_nosync(irq);
161
162 status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
163 status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
164
165 if (status == 0) {
166 spurious_interrupt();
167 goto enable;
168 }
169
170 if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
171 /* TODO: flush DDR? */
172 generic_handle_irq(ATH79_IP2_IRQ(0));
173 }
174
175 if (status & QCA955X_EXT_INT_WMAC_ALL) {
176 /* TODO: flush DDR? */
177 generic_handle_irq(ATH79_IP2_IRQ(1));
178 }
179
180enable:
181 enable_irq(irq);
182}
183
184static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
185{
186 u32 status;
187
188 disable_irq_nosync(irq);
189
190 status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
191 status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
192 QCA955X_EXT_INT_USB1 |
193 QCA955X_EXT_INT_USB2;
194
195 if (status == 0) {
196 spurious_interrupt();
197 goto enable;
198 }
199
200 if (status & QCA955X_EXT_INT_USB1) {
201 /* TODO: flush DDR? */
202 generic_handle_irq(ATH79_IP3_IRQ(0));
203 }
204
205 if (status & QCA955X_EXT_INT_USB2) {
206 /* TODO: flush DDR? */
207 generic_handle_irq(ATH79_IP3_IRQ(1));
208 }
209
210 if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
211 /* TODO: flush DDR? */
212 generic_handle_irq(ATH79_IP3_IRQ(2));
213 }
214
215enable:
216 enable_irq(irq);
217}
218
219static void qca955x_irq_init(void)
220{
221 int i;
222
223 for (i = ATH79_IP2_IRQ_BASE;
224 i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
225 irq_set_chip_and_handler(i, &dummy_irq_chip,
226 handle_level_irq);
227
228 irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
229
230 for (i = ATH79_IP3_IRQ_BASE;
231 i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
232 irq_set_chip_and_handler(i, &dummy_irq_chip,
233 handle_level_irq);
234
235 irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
178} 236}
179 237
180asmlinkage void plat_irq_dispatch(void) 238asmlinkage void plat_irq_dispatch(void)
@@ -184,22 +242,22 @@ asmlinkage void plat_irq_dispatch(void)
184 pending = read_c0_status() & read_c0_cause() & ST0_IM; 242 pending = read_c0_status() & read_c0_cause() & ST0_IM;
185 243
186 if (pending & STATUSF_IP7) 244 if (pending & STATUSF_IP7)
187 do_IRQ(ATH79_CPU_IRQ_TIMER); 245 do_IRQ(ATH79_CPU_IRQ(7));
188 246
189 else if (pending & STATUSF_IP2) 247 else if (pending & STATUSF_IP2)
190 ath79_ip2_handler(); 248 ath79_ip2_handler();
191 249
192 else if (pending & STATUSF_IP4) 250 else if (pending & STATUSF_IP4)
193 do_IRQ(ATH79_CPU_IRQ_GE0); 251 do_IRQ(ATH79_CPU_IRQ(4));
194 252
195 else if (pending & STATUSF_IP5) 253 else if (pending & STATUSF_IP5)
196 do_IRQ(ATH79_CPU_IRQ_GE1); 254 do_IRQ(ATH79_CPU_IRQ(5));
197 255
198 else if (pending & STATUSF_IP3) 256 else if (pending & STATUSF_IP3)
199 ath79_ip3_handler(); 257 ath79_ip3_handler();
200 258
201 else if (pending & STATUSF_IP6) 259 else if (pending & STATUSF_IP6)
202 do_IRQ(ATH79_CPU_IRQ_MISC); 260 do_IRQ(ATH79_CPU_IRQ(6));
203 261
204 else 262 else
205 spurious_interrupt(); 263 spurious_interrupt();
@@ -212,63 +270,69 @@ asmlinkage void plat_irq_dispatch(void)
212 * Issue a flush in the handlers to ensure that the driver sees 270 * Issue a flush in the handlers to ensure that the driver sees
213 * the update. 271 * the update.
214 */ 272 */
273
274static void ath79_default_ip2_handler(void)
275{
276 do_IRQ(ATH79_CPU_IRQ(2));
277}
278
279static void ath79_default_ip3_handler(void)
280{
281 do_IRQ(ATH79_CPU_IRQ(3));
282}
283
215static void ar71xx_ip2_handler(void) 284static void ar71xx_ip2_handler(void)
216{ 285{
217 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI); 286 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
218 do_IRQ(ATH79_CPU_IRQ_IP2); 287 do_IRQ(ATH79_CPU_IRQ(2));
219} 288}
220 289
221static void ar724x_ip2_handler(void) 290static void ar724x_ip2_handler(void)
222{ 291{
223 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE); 292 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
224 do_IRQ(ATH79_CPU_IRQ_IP2); 293 do_IRQ(ATH79_CPU_IRQ(2));
225} 294}
226 295
227static void ar913x_ip2_handler(void) 296static void ar913x_ip2_handler(void)
228{ 297{
229 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC); 298 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
230 do_IRQ(ATH79_CPU_IRQ_IP2); 299 do_IRQ(ATH79_CPU_IRQ(2));
231} 300}
232 301
233static void ar933x_ip2_handler(void) 302static void ar933x_ip2_handler(void)
234{ 303{
235 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC); 304 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
236 do_IRQ(ATH79_CPU_IRQ_IP2); 305 do_IRQ(ATH79_CPU_IRQ(2));
237}
238
239static void ar934x_ip2_handler(void)
240{
241 do_IRQ(ATH79_CPU_IRQ_IP2);
242} 306}
243 307
244static void ar71xx_ip3_handler(void) 308static void ar71xx_ip3_handler(void)
245{ 309{
246 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB); 310 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
247 do_IRQ(ATH79_CPU_IRQ_USB); 311 do_IRQ(ATH79_CPU_IRQ(3));
248} 312}
249 313
250static void ar724x_ip3_handler(void) 314static void ar724x_ip3_handler(void)
251{ 315{
252 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB); 316 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
253 do_IRQ(ATH79_CPU_IRQ_USB); 317 do_IRQ(ATH79_CPU_IRQ(3));
254} 318}
255 319
256static void ar913x_ip3_handler(void) 320static void ar913x_ip3_handler(void)
257{ 321{
258 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB); 322 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
259 do_IRQ(ATH79_CPU_IRQ_USB); 323 do_IRQ(ATH79_CPU_IRQ(3));
260} 324}
261 325
262static void ar933x_ip3_handler(void) 326static void ar933x_ip3_handler(void)
263{ 327{
264 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB); 328 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
265 do_IRQ(ATH79_CPU_IRQ_USB); 329 do_IRQ(ATH79_CPU_IRQ(3));
266} 330}
267 331
268static void ar934x_ip3_handler(void) 332static void ar934x_ip3_handler(void)
269{ 333{
270 ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB); 334 ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
271 do_IRQ(ATH79_CPU_IRQ_USB); 335 do_IRQ(ATH79_CPU_IRQ(3));
272} 336}
273 337
274void __init arch_init_irq(void) 338void __init arch_init_irq(void)
@@ -286,16 +350,21 @@ void __init arch_init_irq(void)
286 ath79_ip2_handler = ar933x_ip2_handler; 350 ath79_ip2_handler = ar933x_ip2_handler;
287 ath79_ip3_handler = ar933x_ip3_handler; 351 ath79_ip3_handler = ar933x_ip3_handler;
288 } else if (soc_is_ar934x()) { 352 } else if (soc_is_ar934x()) {
289 ath79_ip2_handler = ar934x_ip2_handler; 353 ath79_ip2_handler = ath79_default_ip2_handler;
290 ath79_ip3_handler = ar934x_ip3_handler; 354 ath79_ip3_handler = ar934x_ip3_handler;
355 } else if (soc_is_qca955x()) {
356 ath79_ip2_handler = ath79_default_ip2_handler;
357 ath79_ip3_handler = ath79_default_ip3_handler;
291 } else { 358 } else {
292 BUG(); 359 BUG();
293 } 360 }
294 361
295 cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC; 362 cp0_perfcount_irq = ATH79_MISC_IRQ(5);
296 mips_cpu_irq_init(); 363 mips_cpu_irq_init();
297 ath79_misc_irq_init(); 364 ath79_misc_irq_init();
298 365
299 if (soc_is_ar934x()) 366 if (soc_is_ar934x())
300 ar934x_ip2_irq_init(); 367 ar934x_ip2_irq_init();
368 else if (soc_is_qca955x())
369 qca955x_irq_init();
301} 370}
diff --git a/arch/mips/ath79/mach-ap136.c b/arch/mips/ath79/mach-ap136.c
new file mode 100644
index 000000000000..479dd4b1d0d2
--- /dev/null
+++ b/arch/mips/ath79/mach-ap136.c
@@ -0,0 +1,156 @@
1/*
2 * Qualcomm Atheros AP136 reference board support
3 *
4 * Copyright (c) 2012 Qualcomm Atheros
5 * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21#include <linux/pci.h>
22#include <linux/ath9k_platform.h>
23
24#include "machtypes.h"
25#include "dev-gpio-buttons.h"
26#include "dev-leds-gpio.h"
27#include "dev-spi.h"
28#include "dev-usb.h"
29#include "dev-wmac.h"
30#include "pci.h"
31
32#define AP136_GPIO_LED_STATUS_RED 14
33#define AP136_GPIO_LED_STATUS_GREEN 19
34#define AP136_GPIO_LED_USB 4
35#define AP136_GPIO_LED_WLAN_2G 13
36#define AP136_GPIO_LED_WLAN_5G 12
37#define AP136_GPIO_LED_WPS_RED 15
38#define AP136_GPIO_LED_WPS_GREEN 20
39
40#define AP136_GPIO_BTN_WPS 16
41#define AP136_GPIO_BTN_RFKILL 21
42
43#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
44#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
45
46#define AP136_WMAC_CALDATA_OFFSET 0x1000
47#define AP136_PCIE_CALDATA_OFFSET 0x5000
48
49static struct gpio_led ap136_leds_gpio[] __initdata = {
50 {
51 .name = "qca:green:status",
52 .gpio = AP136_GPIO_LED_STATUS_GREEN,
53 .active_low = 1,
54 },
55 {
56 .name = "qca:red:status",
57 .gpio = AP136_GPIO_LED_STATUS_RED,
58 .active_low = 1,
59 },
60 {
61 .name = "qca:green:wps",
62 .gpio = AP136_GPIO_LED_WPS_GREEN,
63 .active_low = 1,
64 },
65 {
66 .name = "qca:red:wps",
67 .gpio = AP136_GPIO_LED_WPS_RED,
68 .active_low = 1,
69 },
70 {
71 .name = "qca:red:wlan-2g",
72 .gpio = AP136_GPIO_LED_WLAN_2G,
73 .active_low = 1,
74 },
75 {
76 .name = "qca:red:usb",
77 .gpio = AP136_GPIO_LED_USB,
78 .active_low = 1,
79 }
80};
81
82static struct gpio_keys_button ap136_gpio_keys[] __initdata = {
83 {
84 .desc = "WPS button",
85 .type = EV_KEY,
86 .code = KEY_WPS_BUTTON,
87 .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
88 .gpio = AP136_GPIO_BTN_WPS,
89 .active_low = 1,
90 },
91 {
92 .desc = "RFKILL button",
93 .type = EV_KEY,
94 .code = KEY_RFKILL,
95 .debounce_interval = AP136_KEYS_DEBOUNCE_INTERVAL,
96 .gpio = AP136_GPIO_BTN_RFKILL,
97 .active_low = 1,
98 },
99};
100
101static struct spi_board_info ap136_spi_info[] = {
102 {
103 .bus_num = 0,
104 .chip_select = 0,
105 .max_speed_hz = 25000000,
106 .modalias = "mx25l6405d",
107 }
108};
109
110static struct ath79_spi_platform_data ap136_spi_data = {
111 .bus_num = 0,
112 .num_chipselect = 1,
113};
114
115#ifdef CONFIG_PCI
116static struct ath9k_platform_data ap136_ath9k_data;
117
118static int ap136_pci_plat_dev_init(struct pci_dev *dev)
119{
120 if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
121 dev->dev.platform_data = &ap136_ath9k_data;
122
123 return 0;
124}
125
126static void __init ap136_pci_init(u8 *eeprom)
127{
128 memcpy(ap136_ath9k_data.eeprom_data, eeprom,
129 sizeof(ap136_ath9k_data.eeprom_data));
130
131 ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
132 ath79_register_pci();
133}
134#else
135static inline void ap136_pci_init(void) {}
136#endif /* CONFIG_PCI */
137
138static void __init ap136_setup(void)
139{
140 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
141
142 ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
143 ap136_leds_gpio);
144 ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
145 ARRAY_SIZE(ap136_gpio_keys),
146 ap136_gpio_keys);
147 ath79_register_spi(&ap136_spi_data, ap136_spi_info,
148 ARRAY_SIZE(ap136_spi_info));
149 ath79_register_usb();
150 ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
151 ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
152}
153
154MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
155 "Atheros AP136-010 reference board",
156 ap136_setup);
diff --git a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h
index af92e5c30d66..26254058c545 100644
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -17,6 +17,7 @@
17enum ath79_mach_type { 17enum ath79_mach_type {
18 ATH79_MACH_GENERIC = 0, 18 ATH79_MACH_GENERIC = 0,
19 ATH79_MACH_AP121, /* Atheros AP121 reference board */ 19 ATH79_MACH_AP121, /* Atheros AP121 reference board */
20 ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
20 ATH79_MACH_AP81, /* Atheros AP81 reference board */ 21 ATH79_MACH_AP81, /* Atheros AP81 reference board */
21 ATH79_MACH_DB120, /* Atheros DB120 reference board */ 22 ATH79_MACH_DB120, /* Atheros DB120 reference board */
22 ATH79_MACH_PB44, /* Atheros PB44 reference board */ 23 ATH79_MACH_PB44, /* Atheros PB44 reference board */
diff --git a/arch/mips/ath79/pci.c b/arch/mips/ath79/pci.c
index ca83abd9d31e..730c0b03060d 100644
--- a/arch/mips/ath79/pci.c
+++ b/arch/mips/ath79/pci.c
@@ -14,10 +14,11 @@
14 14
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/pci.h> 16#include <linux/pci.h>
17#include <linux/resource.h>
18#include <linux/platform_device.h>
17#include <asm/mach-ath79/ar71xx_regs.h> 19#include <asm/mach-ath79/ar71xx_regs.h>
18#include <asm/mach-ath79/ath79.h> 20#include <asm/mach-ath79/ath79.h>
19#include <asm/mach-ath79/irq.h> 21#include <asm/mach-ath79/irq.h>
20#include <asm/mach-ath79/pci.h>
21#include "pci.h" 22#include "pci.h"
22 23
23static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev); 24static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
@@ -48,6 +49,21 @@ static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = {
48 } 49 }
49}; 50};
50 51
52static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
53 {
54 .bus = 0,
55 .slot = 0,
56 .pin = 1,
57 .irq = ATH79_PCI_IRQ(0),
58 },
59 {
60 .bus = 1,
61 .slot = 0,
62 .pin = 1,
63 .irq = ATH79_PCI_IRQ(1),
64 },
65};
66
51int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) 67int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
52{ 68{
53 int irq = -1; 69 int irq = -1;
@@ -63,6 +79,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
63 soc_is_ar9344()) { 79 soc_is_ar9344()) {
64 ath79_pci_irq_map = ar724x_pci_irq_map; 80 ath79_pci_irq_map = ar724x_pci_irq_map;
65 ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map); 81 ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
82 } else if (soc_is_qca955x()) {
83 ath79_pci_irq_map = qca955x_pci_irq_map;
84 ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
66 } else { 85 } else {
67 pr_crit("pci %s: invalid irq map\n", 86 pr_crit("pci %s: invalid irq map\n",
68 pci_name((struct pci_dev *) dev)); 87 pci_name((struct pci_dev *) dev));
@@ -74,7 +93,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
74 const struct ath79_pci_irq *entry; 93 const struct ath79_pci_irq *entry;
75 94
76 entry = &ath79_pci_irq_map[i]; 95 entry = &ath79_pci_irq_map[i];
77 if (entry->slot == slot && entry->pin == pin) { 96 if (entry->bus == dev->bus->number &&
97 entry->slot == slot &&
98 entry->pin == pin) {
78 irq = entry->irq; 99 irq = entry->irq;
79 break; 100 break;
80 } 101 }
@@ -110,21 +131,143 @@ void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
110 ath79_pci_plat_dev_init = func; 131 ath79_pci_plat_dev_init = func;
111} 132}
112 133
113int __init ath79_register_pci(void) 134static struct platform_device *
135ath79_register_pci_ar71xx(void)
136{
137 struct platform_device *pdev;
138 struct resource res[4];
139
140 memset(res, 0, sizeof(res));
141
142 res[0].name = "cfg_base";
143 res[0].flags = IORESOURCE_MEM;
144 res[0].start = AR71XX_PCI_CFG_BASE;
145 res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
146
147 res[1].flags = IORESOURCE_IRQ;
148 res[1].start = ATH79_CPU_IRQ(2);
149 res[1].end = ATH79_CPU_IRQ(2);
150
151 res[2].name = "io_base";
152 res[2].flags = IORESOURCE_IO;
153 res[2].start = 0;
154 res[2].end = 0;
155
156 res[3].name = "mem_base";
157 res[3].flags = IORESOURCE_MEM;
158 res[3].start = AR71XX_PCI_MEM_BASE;
159 res[3].end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1;
160
161 pdev = platform_device_register_simple("ar71xx-pci", -1,
162 res, ARRAY_SIZE(res));
163 return pdev;
164}
165
166static struct platform_device *
167ath79_register_pci_ar724x(int id,
168 unsigned long cfg_base,
169 unsigned long ctrl_base,
170 unsigned long crp_base,
171 unsigned long mem_base,
172 unsigned long mem_size,
173 unsigned long io_base,
174 int irq)
114{ 175{
115 if (soc_is_ar71xx()) 176 struct platform_device *pdev;
116 return ar71xx_pcibios_init(); 177 struct resource res[6];
178
179 memset(res, 0, sizeof(res));
180
181 res[0].name = "cfg_base";
182 res[0].flags = IORESOURCE_MEM;
183 res[0].start = cfg_base;
184 res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
185
186 res[1].name = "ctrl_base";
187 res[1].flags = IORESOURCE_MEM;
188 res[1].start = ctrl_base;
189 res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
190
191 res[2].flags = IORESOURCE_IRQ;
192 res[2].start = irq;
193 res[2].end = irq;
194
195 res[3].name = "mem_base";
196 res[3].flags = IORESOURCE_MEM;
197 res[3].start = mem_base;
198 res[3].end = mem_base + mem_size - 1;
199
200 res[4].name = "io_base";
201 res[4].flags = IORESOURCE_IO;
202 res[4].start = io_base;
203 res[4].end = io_base;
117 204
118 if (soc_is_ar724x()) 205 res[5].name = "crp_base";
119 return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2); 206 res[5].flags = IORESOURCE_MEM;
207 res[5].start = crp_base;
208 res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
120 209
121 if (soc_is_ar9342() || soc_is_ar9344()) { 210 pdev = platform_device_register_simple("ar724x-pci", id,
211 res, ARRAY_SIZE(res));
212 return pdev;
213}
214
215int __init ath79_register_pci(void)
216{
217 struct platform_device *pdev = NULL;
218
219 if (soc_is_ar71xx()) {
220 pdev = ath79_register_pci_ar71xx();
221 } else if (soc_is_ar724x()) {
222 pdev = ath79_register_pci_ar724x(-1,
223 AR724X_PCI_CFG_BASE,
224 AR724X_PCI_CTRL_BASE,
225 AR724X_PCI_CRP_BASE,
226 AR724X_PCI_MEM_BASE,
227 AR724X_PCI_MEM_SIZE,
228 0,
229 ATH79_CPU_IRQ(2));
230 } else if (soc_is_ar9342() ||
231 soc_is_ar9344()) {
122 u32 bootstrap; 232 u32 bootstrap;
123 233
124 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP); 234 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
125 if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC) 235 if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
126 return ar724x_pcibios_init(ATH79_IP2_IRQ(0)); 236 return -ENODEV;
237
238 pdev = ath79_register_pci_ar724x(-1,
239 AR724X_PCI_CFG_BASE,
240 AR724X_PCI_CTRL_BASE,
241 AR724X_PCI_CRP_BASE,
242 AR724X_PCI_MEM_BASE,
243 AR724X_PCI_MEM_SIZE,
244 0,
245 ATH79_IP2_IRQ(0));
246 } else if (soc_is_qca9558()) {
247 pdev = ath79_register_pci_ar724x(0,
248 QCA955X_PCI_CFG_BASE0,
249 QCA955X_PCI_CTRL_BASE0,
250 QCA955X_PCI_CRP_BASE0,
251 QCA955X_PCI_MEM_BASE0,
252 QCA955X_PCI_MEM_SIZE,
253 0,
254 ATH79_IP2_IRQ(0));
255
256 pdev = ath79_register_pci_ar724x(1,
257 QCA955X_PCI_CFG_BASE1,
258 QCA955X_PCI_CTRL_BASE1,
259 QCA955X_PCI_CRP_BASE1,
260 QCA955X_PCI_MEM_BASE1,
261 QCA955X_PCI_MEM_SIZE,
262 1,
263 ATH79_IP3_IRQ(2));
264 } else {
265 /* No PCI support */
266 return -ENODEV;
127 } 267 }
128 268
129 return -ENODEV; 269 if (!pdev)
270 pr_err("unable to register PCI controller device\n");
271
272 return pdev ? 0 : -ENODEV;
130} 273}
diff --git a/arch/mips/ath79/pci.h b/arch/mips/ath79/pci.h
index 51c6625dcc6d..1d00a3803c37 100644
--- a/arch/mips/ath79/pci.h
+++ b/arch/mips/ath79/pci.h
@@ -14,6 +14,7 @@
14#define _ATH79_PCI_H 14#define _ATH79_PCI_H
15 15
16struct ath79_pci_irq { 16struct ath79_pci_irq {
17 int bus;
17 u8 slot; 18 u8 slot;
18 u8 pin; 19 u8 pin;
19 int irq; 20 int irq;
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 60d212ef8629..d5b3c9057018 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -164,13 +164,29 @@ static void __init ath79_detect_sys_type(void)
164 rev = id & AR934X_REV_ID_REVISION_MASK; 164 rev = id & AR934X_REV_ID_REVISION_MASK;
165 break; 165 break;
166 166
167 case REV_ID_MAJOR_QCA9556:
168 ath79_soc = ATH79_SOC_QCA9556;
169 chip = "9556";
170 rev = id & QCA955X_REV_ID_REVISION_MASK;
171 break;
172
173 case REV_ID_MAJOR_QCA9558:
174 ath79_soc = ATH79_SOC_QCA9558;
175 chip = "9558";
176 rev = id & QCA955X_REV_ID_REVISION_MASK;
177 break;
178
167 default: 179 default:
168 panic("ath79: unknown SoC, id:0x%08x", id); 180 panic("ath79: unknown SoC, id:0x%08x", id);
169 } 181 }
170 182
171 ath79_soc_rev = rev; 183 ath79_soc_rev = rev;
172 184
173 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev); 185 if (soc_is_qca955x())
186 sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
187 chip, rev);
188 else
189 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
174 pr_info("SoC: %s\n", ath79_sys_type); 190 pr_info("SoC: %s\n", ath79_sys_type);
175} 191}
176 192
diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index c37419c11c92..cc40b74940f5 100644
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2005 Broadcom Corporation 4 * Copyright (C) 2005 Broadcom Corporation
5 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> 5 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de> 6 * Copyright (C) 2010-2012 Hauke Mehrtens <hauke@hauke-m.de>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
@@ -18,83 +18,160 @@
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/string.h> 19#include <linux/string.h>
20#include <asm/addrspace.h> 20#include <asm/addrspace.h>
21#include <asm/mach-bcm47xx/nvram.h> 21#include <bcm47xx_nvram.h>
22#include <asm/mach-bcm47xx/bcm47xx.h> 22#include <asm/mach-bcm47xx/bcm47xx.h>
23 23
24static char nvram_buf[NVRAM_SPACE]; 24static char nvram_buf[NVRAM_SPACE];
25 25
26static u32 find_nvram_size(u32 end)
27{
28 struct nvram_header *header;
29 u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000};
30 int i;
31
32 for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {
33 header = (struct nvram_header *)KSEG1ADDR(end - nvram_sizes[i]);
34 if (header->magic == NVRAM_HEADER)
35 return nvram_sizes[i];
36 }
37
38 return 0;
39}
40
26/* Probe for NVRAM header */ 41/* Probe for NVRAM header */
27static void early_nvram_init(void) 42static int nvram_find_and_copy(u32 base, u32 lim)
28{ 43{
29#ifdef CONFIG_BCM47XX_SSB
30 struct ssb_mipscore *mcore_ssb;
31#endif
32#ifdef CONFIG_BCM47XX_BCMA
33 struct bcma_drv_cc *bcma_cc;
34#endif
35 struct nvram_header *header; 44 struct nvram_header *header;
36 int i; 45 int i;
37 u32 base = 0;
38 u32 lim = 0;
39 u32 off; 46 u32 off;
40 u32 *src, *dst; 47 u32 *src, *dst;
48 u32 size;
41 49
42 switch (bcm47xx_bus_type) { 50 /* TODO: when nvram is on nand flash check for bad blocks first. */
43#ifdef CONFIG_BCM47XX_SSB
44 case BCM47XX_BUS_TYPE_SSB:
45 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
46 base = mcore_ssb->pflash.window;
47 lim = mcore_ssb->pflash.window_size;
48 break;
49#endif
50#ifdef CONFIG_BCM47XX_BCMA
51 case BCM47XX_BUS_TYPE_BCMA:
52 bcma_cc = &bcm47xx_bus.bcma.bus.drv_cc;
53 base = bcma_cc->pflash.window;
54 lim = bcma_cc->pflash.window_size;
55 break;
56#endif
57 }
58
59 off = FLASH_MIN; 51 off = FLASH_MIN;
60 while (off <= lim) { 52 while (off <= lim) {
61 /* Windowed flash access */ 53 /* Windowed flash access */
62 header = (struct nvram_header *) 54 size = find_nvram_size(base + off);
63 KSEG1ADDR(base + off - NVRAM_SPACE); 55 if (size) {
64 if (header->magic == NVRAM_HEADER) 56 header = (struct nvram_header *)KSEG1ADDR(base + off -
57 size);
65 goto found; 58 goto found;
59 }
66 off <<= 1; 60 off <<= 1;
67 } 61 }
68 62
69 /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */ 63 /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
70 header = (struct nvram_header *) KSEG1ADDR(base + 4096); 64 header = (struct nvram_header *) KSEG1ADDR(base + 4096);
71 if (header->magic == NVRAM_HEADER) 65 if (header->magic == NVRAM_HEADER) {
66 size = NVRAM_SPACE;
72 goto found; 67 goto found;
68 }
73 69
74 header = (struct nvram_header *) KSEG1ADDR(base + 1024); 70 header = (struct nvram_header *) KSEG1ADDR(base + 1024);
75 if (header->magic == NVRAM_HEADER) 71 if (header->magic == NVRAM_HEADER) {
72 size = NVRAM_SPACE;
76 goto found; 73 goto found;
74 }
77 75
78 return; 76 pr_err("no nvram found\n");
77 return -ENXIO;
79 78
80found: 79found:
80
81 if (header->len > size)
82 pr_err("The nvram size accoridng to the header seems to be bigger than the partition on flash\n");
83 if (header->len > NVRAM_SPACE)
84 pr_err("nvram on flash (%i bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\n",
85 header->len, NVRAM_SPACE);
86
81 src = (u32 *) header; 87 src = (u32 *) header;
82 dst = (u32 *) nvram_buf; 88 dst = (u32 *) nvram_buf;
83 for (i = 0; i < sizeof(struct nvram_header); i += 4) 89 for (i = 0; i < sizeof(struct nvram_header); i += 4)
84 *dst++ = *src++; 90 *dst++ = *src++;
85 for (; i < header->len && i < NVRAM_SPACE; i += 4) 91 for (; i < header->len && i < NVRAM_SPACE && i < size; i += 4)
86 *dst++ = le32_to_cpu(*src++); 92 *dst++ = le32_to_cpu(*src++);
93 memset(dst, 0x0, NVRAM_SPACE - i);
94
95 return 0;
87} 96}
88 97
89int nvram_getenv(char *name, char *val, size_t val_len) 98#ifdef CONFIG_BCM47XX_SSB
99static int nvram_init_ssb(void)
100{
101 struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore;
102 u32 base;
103 u32 lim;
104
105 if (mcore->pflash.present) {
106 base = mcore->pflash.window;
107 lim = mcore->pflash.window_size;
108 } else {
109 pr_err("Couldn't find supported flash memory\n");
110 return -ENXIO;
111 }
112
113 return nvram_find_and_copy(base, lim);
114}
115#endif
116
117#ifdef CONFIG_BCM47XX_BCMA
118static int nvram_init_bcma(void)
119{
120 struct bcma_drv_cc *cc = &bcm47xx_bus.bcma.bus.drv_cc;
121 u32 base;
122 u32 lim;
123
124#ifdef CONFIG_BCMA_NFLASH
125 if (cc->nflash.boot) {
126 base = BCMA_SOC_FLASH1;
127 lim = BCMA_SOC_FLASH1_SZ;
128 } else
129#endif
130 if (cc->pflash.present) {
131 base = cc->pflash.window;
132 lim = cc->pflash.window_size;
133#ifdef CONFIG_BCMA_SFLASH
134 } else if (cc->sflash.present) {
135 base = cc->sflash.window;
136 lim = cc->sflash.size;
137#endif
138 } else {
139 pr_err("Couldn't find supported flash memory\n");
140 return -ENXIO;
141 }
142
143 return nvram_find_and_copy(base, lim);
144}
145#endif
146
147static int nvram_init(void)
148{
149 switch (bcm47xx_bus_type) {
150#ifdef CONFIG_BCM47XX_SSB
151 case BCM47XX_BUS_TYPE_SSB:
152 return nvram_init_ssb();
153#endif
154#ifdef CONFIG_BCM47XX_BCMA
155 case BCM47XX_BUS_TYPE_BCMA:
156 return nvram_init_bcma();
157#endif
158 }
159 return -ENXIO;
160}
161
162int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len)
90{ 163{
91 char *var, *value, *end, *eq; 164 char *var, *value, *end, *eq;
165 int err;
92 166
93 if (!name) 167 if (!name)
94 return NVRAM_ERR_INV_PARAM; 168 return -EINVAL;
95 169
96 if (!nvram_buf[0]) 170 if (!nvram_buf[0]) {
97 early_nvram_init(); 171 err = nvram_init();
172 if (err)
173 return err;
174 }
98 175
99 /* Look for name=value and return value */ 176 /* Look for name=value and return value */
100 var = &nvram_buf[sizeof(struct nvram_header)]; 177 var = &nvram_buf[sizeof(struct nvram_header)];
@@ -110,6 +187,6 @@ int nvram_getenv(char *name, char *val, size_t val_len)
110 return snprintf(val, val_len, "%s", value); 187 return snprintf(val, val_len, "%s", value);
111 } 188 }
112 } 189 }
113 return NVRAM_ERR_ENVNOTFOUND; 190 return -ENOENT;
114} 191}
115EXPORT_SYMBOL(nvram_getenv); 192EXPORT_SYMBOL(bcm47xx_nvram_getenv);
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 4d54b58dbd32..b2246cd9ca12 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -35,7 +35,7 @@
35#include <asm/reboot.h> 35#include <asm/reboot.h>
36#include <asm/time.h> 36#include <asm/time.h>
37#include <bcm47xx.h> 37#include <bcm47xx.h>
38#include <asm/mach-bcm47xx/nvram.h> 38#include <bcm47xx_nvram.h>
39 39
40union bcm47xx_bus bcm47xx_bus; 40union bcm47xx_bus bcm47xx_bus;
41EXPORT_SYMBOL(bcm47xx_bus); 41EXPORT_SYMBOL(bcm47xx_bus);
@@ -115,7 +115,7 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus,
115 memset(&iv->sprom, 0, sizeof(struct ssb_sprom)); 115 memset(&iv->sprom, 0, sizeof(struct ssb_sprom));
116 bcm47xx_fill_sprom(&iv->sprom, NULL, false); 116 bcm47xx_fill_sprom(&iv->sprom, NULL, false);
117 117
118 if (nvram_getenv("cardbus", buf, sizeof(buf)) >= 0) 118 if (bcm47xx_nvram_getenv("cardbus", buf, sizeof(buf)) >= 0)
119 iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10); 119 iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10);
120 120
121 return 0; 121 return 0;
@@ -138,7 +138,7 @@ static void __init bcm47xx_register_ssb(void)
138 panic("Failed to initialize SSB bus (err %d)", err); 138 panic("Failed to initialize SSB bus (err %d)", err);
139 139
140 mcore = &bcm47xx_bus.ssb.mipscore; 140 mcore = &bcm47xx_bus.ssb.mipscore;
141 if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) { 141 if (bcm47xx_nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
142 if (strstr(buf, "console=ttyS1")) { 142 if (strstr(buf, "console=ttyS1")) {
143 struct ssb_serial_port port; 143 struct ssb_serial_port port;
144 144
diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c
index b2a7c251e471..ad03c931b905 100644
--- a/arch/mips/bcm47xx/sprom.c
+++ b/arch/mips/bcm47xx/sprom.c
@@ -27,7 +27,7 @@
27 */ 27 */
28 28
29#include <bcm47xx.h> 29#include <bcm47xx.h>
30#include <nvram.h> 30#include <bcm47xx_nvram.h>
31 31
32static void create_key(const char *prefix, const char *postfix, 32static void create_key(const char *prefix, const char *postfix,
33 const char *name, char *buf, int len) 33 const char *name, char *buf, int len)
@@ -50,10 +50,10 @@ static int get_nvram_var(const char *prefix, const char *postfix,
50 50
51 create_key(prefix, postfix, name, key, sizeof(key)); 51 create_key(prefix, postfix, name, key, sizeof(key));
52 52
53 err = nvram_getenv(key, buf, len); 53 err = bcm47xx_nvram_getenv(key, buf, len);
54 if (fallback && err == NVRAM_ERR_ENVNOTFOUND && prefix) { 54 if (fallback && err == -ENOENT && prefix) {
55 create_key(NULL, postfix, name, key, sizeof(key)); 55 create_key(NULL, postfix, name, key, sizeof(key));
56 err = nvram_getenv(key, buf, len); 56 err = bcm47xx_nvram_getenv(key, buf, len);
57 } 57 }
58 return err; 58 return err;
59} 59}
@@ -71,7 +71,7 @@ static void nvram_read_ ## type (const char *prefix, \
71 fallback); \ 71 fallback); \
72 if (err < 0) \ 72 if (err < 0) \
73 return; \ 73 return; \
74 err = kstrto ## type (buf, 0, &var); \ 74 err = kstrto ## type(strim(buf), 0, &var); \
75 if (err) { \ 75 if (err) { \
76 pr_warn("can not parse nvram name %s%s%s with value %s got %i\n", \ 76 pr_warn("can not parse nvram name %s%s%s with value %s got %i\n", \
77 prefix, name, postfix, buf, err); \ 77 prefix, name, postfix, buf, err); \
@@ -99,7 +99,7 @@ static void nvram_read_u32_2(const char *prefix, const char *name,
99 err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback); 99 err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback);
100 if (err < 0) 100 if (err < 0)
101 return; 101 return;
102 err = kstrtou32(buf, 0, &val); 102 err = kstrtou32(strim(buf), 0, &val);
103 if (err) { 103 if (err) {
104 pr_warn("can not parse nvram name %s%s with value %s got %i\n", 104 pr_warn("can not parse nvram name %s%s with value %s got %i\n",
105 prefix, name, buf, err); 105 prefix, name, buf, err);
@@ -120,7 +120,7 @@ static void nvram_read_leddc(const char *prefix, const char *name,
120 err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback); 120 err = get_nvram_var(prefix, NULL, name, buf, sizeof(buf), fallback);
121 if (err < 0) 121 if (err < 0)
122 return; 122 return;
123 err = kstrtou32(buf, 0, &val); 123 err = kstrtou32(strim(buf), 0, &val);
124 if (err) { 124 if (err) {
125 pr_warn("can not parse nvram name %s%s with value %s got %i\n", 125 pr_warn("can not parse nvram name %s%s with value %s got %i\n",
126 prefix, name, buf, err); 126 prefix, name, buf, err);
@@ -144,7 +144,7 @@ static void nvram_read_macaddr(const char *prefix, const char *name,
144 if (err < 0) 144 if (err < 0)
145 return; 145 return;
146 146
147 nvram_parse_macaddr(buf, *val); 147 bcm47xx_nvram_parse_macaddr(buf, *val);
148} 148}
149 149
150static void nvram_read_alpha2(const char *prefix, const char *name, 150static void nvram_read_alpha2(const char *prefix, const char *name,
@@ -652,12 +652,10 @@ static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom,
652static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix, 652static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
653 bool fallback) 653 bool fallback)
654{ 654{
655 nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0, 655 nvram_read_u16(prefix, NULL, "boardrev", &sprom->board_rev, 0, true);
656 fallback);
657 nvram_read_u16(prefix, NULL, "boardnum", &sprom->board_num, 0, 656 nvram_read_u16(prefix, NULL, "boardnum", &sprom->board_num, 0,
658 fallback); 657 fallback);
659 nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0, 658 nvram_read_u16(prefix, NULL, "boardtype", &sprom->board_type, 0, true);
660 fallback);
661 nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo, 659 nvram_read_u32_2(prefix, "boardflags", &sprom->boardflags_lo,
662 &sprom->boardflags_hi, fallback); 660 &sprom->boardflags_hi, fallback);
663 nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo, 661 nvram_read_u32_2(prefix, "boardflags2", &sprom->boardflags2_lo,
diff --git a/arch/mips/bcm63xx/early_printk.c b/arch/mips/bcm63xx/early_printk.c
index bf353c937df2..aa8f7f9cc7a4 100644
--- a/arch/mips/bcm63xx/early_printk.c
+++ b/arch/mips/bcm63xx/early_printk.c
@@ -10,7 +10,7 @@
10#include <bcm63xx_io.h> 10#include <bcm63xx_io.h>
11#include <bcm63xx_regs.h> 11#include <bcm63xx_regs.h>
12 12
13static void __init wait_xfered(void) 13static void wait_xfered(void)
14{ 14{
15 unsigned int val; 15 unsigned int val;
16 16
@@ -22,7 +22,7 @@ static void __init wait_xfered(void)
22 } while (1); 22 } while (1);
23} 23}
24 24
25void __init prom_putchar(char c) 25void prom_putchar(char c)
26{ 26{
27 wait_xfered(); 27 wait_xfered();
28 bcm_uart0_writel(c, UART_FIFO_REG); 28 bcm_uart0_writel(c, UART_FIFO_REG);
diff --git a/arch/mips/configs/ath79_defconfig b/arch/mips/configs/ath79_defconfig
index ea87d43ba607..e3a3836508ec 100644
--- a/arch/mips/configs/ath79_defconfig
+++ b/arch/mips/configs/ath79_defconfig
@@ -1,5 +1,6 @@
1CONFIG_ATH79=y 1CONFIG_ATH79=y
2CONFIG_ATH79_MACH_AP121=y 2CONFIG_ATH79_MACH_AP121=y
3CONFIG_ATH79_MACH_AP136=y
3CONFIG_ATH79_MACH_AP81=y 4CONFIG_ATH79_MACH_AP81=y
4CONFIG_ATH79_MACH_DB120=y 5CONFIG_ATH79_MACH_DB120=y
5CONFIG_ATH79_MACH_PB44=y 6CONFIG_ATH79_MACH_PB44=y
diff --git a/arch/mips/configs/rt305x_defconfig b/arch/mips/configs/rt305x_defconfig
new file mode 100644
index 000000000000..d1741bcf8949
--- /dev/null
+++ b/arch/mips/configs/rt305x_defconfig
@@ -0,0 +1,167 @@
1CONFIG_RALINK=y
2CONFIG_DTB_RT305X_EVAL=y
3CONFIG_CPU_MIPS32_R2=y
4# CONFIG_COMPACTION is not set
5# CONFIG_CROSS_MEMORY_ATTACH is not set
6CONFIG_HZ_100=y
7# CONFIG_SECCOMP is not set
8CONFIG_EXPERIMENTAL=y
9# CONFIG_LOCALVERSION_AUTO is not set
10CONFIG_SYSVIPC=y
11CONFIG_HIGH_RES_TIMERS=y
12CONFIG_BLK_DEV_INITRD=y
13CONFIG_INITRAMFS_SOURCE=""
14CONFIG_INITRAMFS_ROOT_UID=1000
15CONFIG_INITRAMFS_ROOT_GID=1000
16# CONFIG_RD_GZIP is not set
17CONFIG_CC_OPTIMIZE_FOR_SIZE=y
18CONFIG_KALLSYMS_ALL=y
19# CONFIG_AIO is not set
20CONFIG_EMBEDDED=y
21# CONFIG_VM_EVENT_COUNTERS is not set
22# CONFIG_SLUB_DEBUG is not set
23# CONFIG_COMPAT_BRK is not set
24CONFIG_MODULES=y
25CONFIG_MODULE_UNLOAD=y
26# CONFIG_BLK_DEV_BSG is not set
27CONFIG_PARTITION_ADVANCED=y
28# CONFIG_IOSCHED_CFQ is not set
29# CONFIG_COREDUMP is not set
30# CONFIG_SUSPEND is not set
31CONFIG_NET=y
32CONFIG_PACKET=y
33CONFIG_UNIX=y
34CONFIG_INET=y
35CONFIG_IP_MULTICAST=y
36CONFIG_IP_ADVANCED_ROUTER=y
37CONFIG_IP_MULTIPLE_TABLES=y
38CONFIG_IP_ROUTE_MULTIPATH=y
39CONFIG_IP_ROUTE_VERBOSE=y
40CONFIG_IP_MROUTE=y
41CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
42CONFIG_ARPD=y
43CONFIG_SYN_COOKIES=y
44# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
45# CONFIG_INET_XFRM_MODE_TUNNEL is not set
46# CONFIG_INET_XFRM_MODE_BEET is not set
47# CONFIG_INET_LRO is not set
48# CONFIG_INET_DIAG is not set
49CONFIG_TCP_CONG_ADVANCED=y
50# CONFIG_TCP_CONG_BIC is not set
51# CONFIG_TCP_CONG_WESTWOOD is not set
52# CONFIG_TCP_CONG_HTCP is not set
53# CONFIG_IPV6 is not set
54CONFIG_NETFILTER=y
55# CONFIG_BRIDGE_NETFILTER is not set
56CONFIG_NF_CONNTRACK=m
57CONFIG_NF_CONNTRACK_FTP=m
58CONFIG_NF_CONNTRACK_IRC=m
59CONFIG_NETFILTER_XT_TARGET_CT=m
60CONFIG_NETFILTER_XT_TARGET_LOG=m
61CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
62CONFIG_NETFILTER_XT_MATCH_COMMENT=m
63CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
64CONFIG_NETFILTER_XT_MATCH_LIMIT=m
65CONFIG_NETFILTER_XT_MATCH_MAC=m
66CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
67CONFIG_NETFILTER_XT_MATCH_STATE=m
68CONFIG_NF_CONNTRACK_IPV4=m
69# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
70CONFIG_IP_NF_IPTABLES=m
71CONFIG_IP_NF_FILTER=m
72CONFIG_IP_NF_TARGET_REJECT=m
73CONFIG_IP_NF_MANGLE=m
74CONFIG_IP_NF_RAW=m
75CONFIG_BRIDGE=y
76# CONFIG_BRIDGE_IGMP_SNOOPING is not set
77CONFIG_VLAN_8021Q=y
78CONFIG_NET_SCHED=y
79CONFIG_HAMRADIO=y
80CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
81# CONFIG_FIRMWARE_IN_KERNEL is not set
82CONFIG_MTD=y
83CONFIG_MTD_CMDLINE_PARTS=y
84CONFIG_MTD_CHAR=y
85CONFIG_MTD_BLOCK=y
86CONFIG_MTD_CFI=y
87CONFIG_MTD_CFI_AMDSTD=y
88CONFIG_MTD_COMPLEX_MAPPINGS=y
89CONFIG_MTD_PHYSMAP=y
90CONFIG_MTD_PHYSMAP_OF=y
91CONFIG_MTD_M25P80=y
92CONFIG_EEPROM_93CX6=m
93CONFIG_SCSI=y
94CONFIG_BLK_DEV_SD=y
95CONFIG_NETDEVICES=y
96# CONFIG_NET_VENDOR_WIZNET is not set
97CONFIG_PHYLIB=y
98CONFIG_PPP=m
99CONFIG_PPP_FILTER=y
100CONFIG_PPP_MULTILINK=y
101CONFIG_PPPOE=m
102CONFIG_PPP_ASYNC=m
103CONFIG_ISDN=y
104CONFIG_INPUT=m
105CONFIG_INPUT_POLLDEV=m
106# CONFIG_INPUT_MOUSEDEV is not set
107# CONFIG_KEYBOARD_ATKBD is not set
108# CONFIG_INPUT_MOUSE is not set
109CONFIG_INPUT_MISC=y
110# CONFIG_SERIO is not set
111# CONFIG_VT is not set
112# CONFIG_LEGACY_PTYS is not set
113# CONFIG_DEVKMEM is not set
114CONFIG_SERIAL_8250=y
115CONFIG_SERIAL_8250_CONSOLE=y
116CONFIG_SERIAL_8250_RUNTIME_UARTS=2
117CONFIG_SERIAL_OF_PLATFORM=y
118CONFIG_SPI=y
119# CONFIG_HWMON is not set
120CONFIG_WATCHDOG=y
121# CONFIG_HID is not set
122# CONFIG_USB_HID is not set
123CONFIG_USB=y
124CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
125CONFIG_USB_STORAGE=y
126CONFIG_USB_STORAGE_DEBUG=y
127CONFIG_NEW_LEDS=y
128CONFIG_LEDS_CLASS=y
129CONFIG_LEDS_TRIGGERS=y
130CONFIG_LEDS_TRIGGER_TIMER=y
131CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
132CONFIG_STAGING=y
133# CONFIG_IOMMU_SUPPORT is not set
134# CONFIG_DNOTIFY is not set
135# CONFIG_PROC_PAGE_MONITOR is not set
136CONFIG_TMPFS=y
137CONFIG_TMPFS_XATTR=y
138CONFIG_JFFS2_FS=y
139CONFIG_JFFS2_SUMMARY=y
140CONFIG_JFFS2_FS_XATTR=y
141# CONFIG_JFFS2_FS_POSIX_ACL is not set
142# CONFIG_JFFS2_FS_SECURITY is not set
143CONFIG_JFFS2_COMPRESSION_OPTIONS=y
144# CONFIG_JFFS2_ZLIB is not set
145CONFIG_SQUASHFS=y
146# CONFIG_SQUASHFS_ZLIB is not set
147CONFIG_SQUASHFS_XZ=y
148CONFIG_PRINTK_TIME=y
149# CONFIG_ENABLE_MUST_CHECK is not set
150CONFIG_MAGIC_SYSRQ=y
151CONFIG_STRIP_ASM_SYMS=y
152CONFIG_DEBUG_FS=y
153# CONFIG_SCHED_DEBUG is not set
154# CONFIG_FTRACE is not set
155CONFIG_CMDLINE_BOOL=y
156CONFIG_CRYPTO_MANAGER=m
157CONFIG_CRYPTO_ARC4=m
158# CONFIG_CRYPTO_ANSI_CPRNG is not set
159CONFIG_CRC_ITU_T=m
160CONFIG_CRC32_SARWATE=y
161# CONFIG_XZ_DEC_X86 is not set
162# CONFIG_XZ_DEC_POWERPC is not set
163# CONFIG_XZ_DEC_IA64 is not set
164# CONFIG_XZ_DEC_ARM is not set
165# CONFIG_XZ_DEC_ARMTHUMB is not set
166# CONFIG_XZ_DEC_SPARC is not set
167CONFIG_AVERAGE=y
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 1e83b24fa461..1a57e8b4d092 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -98,6 +98,9 @@
98#ifndef cpu_has_rixi 98#ifndef cpu_has_rixi
99#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) 99#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
100#endif 100#endif
101#ifndef cpu_has_mmips
102#define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
103#endif
101#ifndef cpu_has_vtag_icache 104#ifndef cpu_has_vtag_icache
102#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 105#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
103#endif 106#endif
@@ -273,4 +276,8 @@
273#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI) 276#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
274#endif 277#endif
275 278
279#ifndef cpu_has_vz
280#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
281#endif
282
276#endif /* __ASM_CPU_FEATURES_H */ 283#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 9904697bd792..dd86ab205483 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -96,6 +96,7 @@
96#define PRID_IMP_1004K 0x9900 96#define PRID_IMP_1004K 0x9900
97#define PRID_IMP_1074K 0x9a00 97#define PRID_IMP_1074K 0x9a00
98#define PRID_IMP_M14KC 0x9c00 98#define PRID_IMP_M14KC 0x9c00
99#define PRID_IMP_M14KEC 0x9e00
99 100
100/* 101/*
101 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 102 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -264,6 +265,7 @@ enum cpu_type_enum {
264 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 265 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
265 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 266 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
266 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 267 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
268 CPU_M14KEC,
267 269
268 /* 270 /*
269 * MIPS64 class processors 271 * MIPS64 class processors
@@ -322,6 +324,7 @@ enum cpu_type_enum {
322#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */ 324#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
323#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ 325#define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */
324#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ 326#define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */
327#define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */
325 328
326/* 329/*
327 * CPU ASE encodings 330 * CPU ASE encodings
@@ -333,6 +336,6 @@ enum cpu_type_enum {
333#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 336#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
334#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 337#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
335#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ 338#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
336 339#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
337 340
338#endif /* _ASM_CPU_H */ 341#endif /* _ASM_CPU_H */
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 61b06d7e7de1..bdc9786ab5a7 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -359,6 +359,7 @@ struct gic_shared_intr_map {
359/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ 359/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
360#define GIC_PIN_TO_VEC_OFFSET (1) 360#define GIC_PIN_TO_VEC_OFFSET (1)
361 361
362extern int gic_present;
362extern unsigned long _gic_base; 363extern unsigned long _gic_base;
363extern unsigned int gic_irq_base; 364extern unsigned int gic_irq_base;
364extern unsigned int gic_irq_flags[]; 365extern unsigned int gic_irq_flags[];
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 568544b6e856..44d6a5bde4a1 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -141,7 +141,7 @@ do { \
141 141
142#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ 142#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
143 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ 143 defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
144 defined(CONFIG_CPU_R5500) 144 defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
145 145
146/* 146/*
147 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 147 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/irq_cpu.h b/arch/mips/include/asm/irq_cpu.h
index ef6a07cddb23..3f11fdb3ed8c 100644
--- a/arch/mips/include/asm/irq_cpu.h
+++ b/arch/mips/include/asm/irq_cpu.h
@@ -17,4 +17,10 @@ extern void mips_cpu_irq_init(void);
17extern void rm7k_cpu_irq_init(void); 17extern void rm7k_cpu_irq_init(void);
18extern void rm9k_cpu_irq_init(void); 18extern void rm9k_cpu_irq_init(void);
19 19
20#ifdef CONFIG_IRQ_DOMAIN
21struct device_node;
22extern int mips_cpu_intc_init(struct device_node *of_node,
23 struct device_node *parent);
24#endif
25
20#endif /* _ASM_IRQ_CPU_H */ 26#endif /* _ASM_IRQ_CPU_H */
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 8dec938af115..b86a1253a5bf 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -41,11 +41,37 @@
41#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) 41#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
42#define AR71XX_RESET_SIZE 0x100 42#define AR71XX_RESET_SIZE 0x100
43 43
44#define AR71XX_PCI_MEM_BASE 0x10000000
45#define AR71XX_PCI_MEM_SIZE 0x07000000
46
47#define AR71XX_PCI_WIN0_OFFS 0x10000000
48#define AR71XX_PCI_WIN1_OFFS 0x11000000
49#define AR71XX_PCI_WIN2_OFFS 0x12000000
50#define AR71XX_PCI_WIN3_OFFS 0x13000000
51#define AR71XX_PCI_WIN4_OFFS 0x14000000
52#define AR71XX_PCI_WIN5_OFFS 0x15000000
53#define AR71XX_PCI_WIN6_OFFS 0x16000000
54#define AR71XX_PCI_WIN7_OFFS 0x07000000
55
56#define AR71XX_PCI_CFG_BASE \
57 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
58#define AR71XX_PCI_CFG_SIZE 0x100
59
44#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) 60#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
45#define AR7240_USB_CTRL_SIZE 0x100 61#define AR7240_USB_CTRL_SIZE 0x100
46#define AR7240_OHCI_BASE 0x1b000000 62#define AR7240_OHCI_BASE 0x1b000000
47#define AR7240_OHCI_SIZE 0x1000 63#define AR7240_OHCI_SIZE 0x1000
48 64
65#define AR724X_PCI_MEM_BASE 0x10000000
66#define AR724X_PCI_MEM_SIZE 0x04000000
67
68#define AR724X_PCI_CFG_BASE 0x14000000
69#define AR724X_PCI_CFG_SIZE 0x1000
70#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
71#define AR724X_PCI_CRP_SIZE 0x1000
72#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
73#define AR724X_PCI_CTRL_SIZE 0x100
74
49#define AR724X_EHCI_BASE 0x1b000000 75#define AR724X_EHCI_BASE 0x1b000000
50#define AR724X_EHCI_SIZE 0x1000 76#define AR724X_EHCI_SIZE 0x1000
51 77
@@ -68,6 +94,25 @@
68#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) 94#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
69#define AR934X_SRIF_SIZE 0x1000 95#define AR934X_SRIF_SIZE 0x1000
70 96
97#define QCA955X_PCI_MEM_BASE0 0x10000000
98#define QCA955X_PCI_MEM_BASE1 0x12000000
99#define QCA955X_PCI_MEM_SIZE 0x02000000
100#define QCA955X_PCI_CFG_BASE0 0x14000000
101#define QCA955X_PCI_CFG_BASE1 0x16000000
102#define QCA955X_PCI_CFG_SIZE 0x1000
103#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
104#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
105#define QCA955X_PCI_CRP_SIZE 0x1000
106#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
107#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
108#define QCA955X_PCI_CTRL_SIZE 0x100
109
110#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
111#define QCA955X_WMAC_SIZE 0x20000
112#define QCA955X_EHCI0_BASE 0x1b000000
113#define QCA955X_EHCI1_BASE 0x1b400000
114#define QCA955X_EHCI_SIZE 0x1000
115
71/* 116/*
72 * DDR_CTRL block 117 * DDR_CTRL block
73 */ 118 */
@@ -199,6 +244,41 @@
199#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 244#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
200#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 245#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
201 246
247#define QCA955X_PLL_CPU_CONFIG_REG 0x00
248#define QCA955X_PLL_DDR_CONFIG_REG 0x04
249#define QCA955X_PLL_CLK_CTRL_REG 0x08
250
251#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
252#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
253#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
254#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
255#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
256#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
257#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
258#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
259
260#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
261#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
262#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
263#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
264#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
265#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
266#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
267#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
268
269#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
270#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
271#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
272#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
273#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
274#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
275#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
276#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
277#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
278#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
279#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
280#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
281
202/* 282/*
203 * USB_CONFIG block 283 * USB_CONFIG block
204 */ 284 */
@@ -238,6 +318,10 @@
238#define AR934X_RESET_REG_BOOTSTRAP 0xb0 318#define AR934X_RESET_REG_BOOTSTRAP 0xb0
239#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac 319#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
240 320
321#define QCA955X_RESET_REG_RESET_MODULE 0x1c
322#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
323#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
324
241#define MISC_INT_ETHSW BIT(12) 325#define MISC_INT_ETHSW BIT(12)
242#define MISC_INT_TIMER4 BIT(10) 326#define MISC_INT_TIMER4 BIT(10)
243#define MISC_INT_TIMER3 BIT(9) 327#define MISC_INT_TIMER3 BIT(9)
@@ -315,6 +399,8 @@
315#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) 399#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
316#define AR934X_BOOTSTRAP_DDR1 BIT(0) 400#define AR934X_BOOTSTRAP_DDR1 BIT(0)
317 401
402#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
403
318#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) 404#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
319#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) 405#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
320#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) 406#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
@@ -333,6 +419,37 @@
333 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ 419 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
334 AR934X_PCIE_WMAC_INT_PCIE_RC3) 420 AR934X_PCIE_WMAC_INT_PCIE_RC3)
335 421
422#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
423#define QCA955X_EXT_INT_WMAC_TX BIT(1)
424#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
425#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
426#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
427#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
428#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
429#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
430#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
431#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
432#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
433#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
434#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
435#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
436#define QCA955X_EXT_INT_USB1 BIT(24)
437#define QCA955X_EXT_INT_USB2 BIT(28)
438
439#define QCA955X_EXT_INT_WMAC_ALL \
440 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
441 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
442
443#define QCA955X_EXT_INT_PCIE_RC1_ALL \
444 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
445 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
446 QCA955X_EXT_INT_PCIE_RC1_INT3)
447
448#define QCA955X_EXT_INT_PCIE_RC2_ALL \
449 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
450 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
451 QCA955X_EXT_INT_PCIE_RC2_INT3)
452
336#define REV_ID_MAJOR_MASK 0xfff0 453#define REV_ID_MAJOR_MASK 0xfff0
337#define REV_ID_MAJOR_AR71XX 0x00a0 454#define REV_ID_MAJOR_AR71XX 0x00a0
338#define REV_ID_MAJOR_AR913X 0x00b0 455#define REV_ID_MAJOR_AR913X 0x00b0
@@ -344,6 +461,8 @@
344#define REV_ID_MAJOR_AR9341 0x0120 461#define REV_ID_MAJOR_AR9341 0x0120
345#define REV_ID_MAJOR_AR9342 0x1120 462#define REV_ID_MAJOR_AR9342 0x1120
346#define REV_ID_MAJOR_AR9344 0x2120 463#define REV_ID_MAJOR_AR9344 0x2120
464#define REV_ID_MAJOR_QCA9556 0x0130
465#define REV_ID_MAJOR_QCA9558 0x1130
347 466
348#define AR71XX_REV_ID_MINOR_MASK 0x3 467#define AR71XX_REV_ID_MINOR_MASK 0x3
349#define AR71XX_REV_ID_MINOR_AR7130 0x0 468#define AR71XX_REV_ID_MINOR_AR7130 0x0
@@ -364,6 +483,8 @@
364 483
365#define AR934X_REV_ID_REVISION_MASK 0xf 484#define AR934X_REV_ID_REVISION_MASK 0xf
366 485
486#define QCA955X_REV_ID_REVISION_MASK 0xf
487
367/* 488/*
368 * SPI block 489 * SPI block
369 */ 490 */
@@ -401,12 +522,15 @@
401#define AR71XX_GPIO_REG_INT_ENABLE 0x24 522#define AR71XX_GPIO_REG_INT_ENABLE 0x24
402#define AR71XX_GPIO_REG_FUNC 0x28 523#define AR71XX_GPIO_REG_FUNC 0x28
403 524
525#define AR934X_GPIO_REG_FUNC 0x6c
526
404#define AR71XX_GPIO_COUNT 16 527#define AR71XX_GPIO_COUNT 16
405#define AR7240_GPIO_COUNT 18 528#define AR7240_GPIO_COUNT 18
406#define AR7241_GPIO_COUNT 20 529#define AR7241_GPIO_COUNT 20
407#define AR913X_GPIO_COUNT 22 530#define AR913X_GPIO_COUNT 22
408#define AR933X_GPIO_COUNT 30 531#define AR933X_GPIO_COUNT 30
409#define AR934X_GPIO_COUNT 23 532#define AR934X_GPIO_COUNT 23
533#define QCA955X_GPIO_COUNT 24
410 534
411/* 535/*
412 * SRIF block 536 * SRIF block
diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
index 4f248c3d7b23..1557934aaca9 100644
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -32,6 +32,8 @@ enum ath79_soc_type {
32 ATH79_SOC_AR9341, 32 ATH79_SOC_AR9341,
33 ATH79_SOC_AR9342, 33 ATH79_SOC_AR9342,
34 ATH79_SOC_AR9344, 34 ATH79_SOC_AR9344,
35 ATH79_SOC_QCA9556,
36 ATH79_SOC_QCA9558,
35}; 37};
36 38
37extern enum ath79_soc_type ath79_soc; 39extern enum ath79_soc_type ath79_soc;
@@ -98,6 +100,21 @@ static inline int soc_is_ar934x(void)
98 return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); 100 return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
99} 101}
100 102
103static inline int soc_is_qca9556(void)
104{
105 return ath79_soc == ATH79_SOC_QCA9556;
106}
107
108static inline int soc_is_qca9558(void)
109{
110 return ath79_soc == ATH79_SOC_QCA9558;
111}
112
113static inline int soc_is_qca955x(void)
114{
115 return soc_is_qca9556() || soc_is_qca9558();
116}
117
101extern void __iomem *ath79_ddr_base; 118extern void __iomem *ath79_ddr_base;
102extern void __iomem *ath79_pll_base; 119extern void __iomem *ath79_pll_base;
103extern void __iomem *ath79_reset_base; 120extern void __iomem *ath79_reset_base;
diff --git a/arch/mips/include/asm/mach-ath79/irq.h b/arch/mips/include/asm/mach-ath79/irq.h
index 0968f69e2018..5c9ca76a7ebf 100644
--- a/arch/mips/include/asm/mach-ath79/irq.h
+++ b/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,10 +10,13 @@
10#define __ASM_MACH_ATH79_IRQ_H 10#define __ASM_MACH_ATH79_IRQ_H
11 11
12#define MIPS_CPU_IRQ_BASE 0 12#define MIPS_CPU_IRQ_BASE 0
13#define NR_IRQS 48 13#define NR_IRQS 51
14
15#define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
14 16
15#define ATH79_MISC_IRQ_BASE 8 17#define ATH79_MISC_IRQ_BASE 8
16#define ATH79_MISC_IRQ_COUNT 32 18#define ATH79_MISC_IRQ_COUNT 32
19#define ATH79_MISC_IRQ(_x) (ATH79_MISC_IRQ_BASE + (_x))
17 20
18#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT) 21#define ATH79_PCI_IRQ_BASE (ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
19#define ATH79_PCI_IRQ_COUNT 6 22#define ATH79_PCI_IRQ_COUNT 6
@@ -23,25 +26,9 @@
23#define ATH79_IP2_IRQ_COUNT 2 26#define ATH79_IP2_IRQ_COUNT 2
24#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x)) 27#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
25 28
26#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2) 29#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
27#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3) 30#define ATH79_IP3_IRQ_COUNT 3
28#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4) 31#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x))
29#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5)
30#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6)
31#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7)
32
33#define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0)
34#define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1)
35#define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2)
36#define ATH79_MISC_IRQ_UART (ATH79_MISC_IRQ_BASE + 3)
37#define ATH79_MISC_IRQ_WDOG (ATH79_MISC_IRQ_BASE + 4)
38#define ATH79_MISC_IRQ_PERFC (ATH79_MISC_IRQ_BASE + 5)
39#define ATH79_MISC_IRQ_OHCI (ATH79_MISC_IRQ_BASE + 6)
40#define ATH79_MISC_IRQ_DMA (ATH79_MISC_IRQ_BASE + 7)
41#define ATH79_MISC_IRQ_TIMER2 (ATH79_MISC_IRQ_BASE + 8)
42#define ATH79_MISC_IRQ_TIMER3 (ATH79_MISC_IRQ_BASE + 9)
43#define ATH79_MISC_IRQ_TIMER4 (ATH79_MISC_IRQ_BASE + 10)
44#define ATH79_MISC_IRQ_ETHSW (ATH79_MISC_IRQ_BASE + 12)
45 32
46#include_next <irq.h> 33#include_next <irq.h>
47 34
diff --git a/arch/mips/include/asm/mach-ath79/pci.h b/arch/mips/include/asm/mach-ath79/pci.h
deleted file mode 100644
index 7868f7fa028f..000000000000
--- a/arch/mips/include/asm/mach-ath79/pci.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Atheros AR71XX/AR724X PCI support
3 *
4 * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#ifndef __ASM_MACH_ATH79_PCI_H
14#define __ASM_MACH_ATH79_PCI_H
15
16#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
17int ar71xx_pcibios_init(void);
18#else
19static inline int ar71xx_pcibios_init(void) { return 0; }
20#endif
21
22#if defined(CONFIG_PCI_AR724X)
23int ar724x_pcibios_init(int irq);
24#else
25static inline int ar724x_pcibios_init(int irq) { return 0; }
26#endif
27
28#endif /* __ASM_MACH_ATH79_PCI_H */
diff --git a/arch/mips/include/asm/mach-bcm47xx/nvram.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
index 69ef3efe06e7..b8e7be8f34dd 100644
--- a/arch/mips/include/asm/mach-bcm47xx/nvram.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_nvram.h
@@ -8,8 +8,8 @@
8 * option) any later version. 8 * option) any later version.
9 */ 9 */
10 10
11#ifndef __NVRAM_H 11#ifndef __BCM47XX_NVRAM_H
12#define __NVRAM_H 12#define __BCM47XX_NVRAM_H
13 13
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
@@ -32,12 +32,9 @@ struct nvram_header {
32#define NVRAM_MAX_VALUE_LEN 255 32#define NVRAM_MAX_VALUE_LEN 255
33#define NVRAM_MAX_PARAM_LEN 64 33#define NVRAM_MAX_PARAM_LEN 64
34 34
35#define NVRAM_ERR_INV_PARAM -8 35extern int bcm47xx_nvram_getenv(char *name, char *val, size_t val_len);
36#define NVRAM_ERR_ENVNOTFOUND -9
37 36
38extern int nvram_getenv(char *name, char *val, size_t val_len); 37static inline void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
39
40static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6])
41{ 38{
42 if (strchr(buf, ':')) 39 if (strchr(buf, ':'))
43 sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], 40 sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
@@ -51,4 +48,4 @@ static inline void nvram_parse_macaddr(char *buf, u8 macaddr[6])
51 printk(KERN_WARNING "Can not parse mac address: %s\n", buf); 48 printk(KERN_WARNING "Can not parse mac address: %s\n", buf);
52} 49}
53 50
54#endif 51#endif /* __BCM47XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 5e8a6e965756..f196cceb7322 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -34,6 +34,7 @@ extern spinlock_t ebu_lock;
34extern void ltq_disable_irq(struct irq_data *data); 34extern void ltq_disable_irq(struct irq_data *data);
35extern void ltq_mask_and_ack_irq(struct irq_data *data); 35extern void ltq_mask_and_ack_irq(struct irq_data *data);
36extern void ltq_enable_irq(struct irq_data *data); 36extern void ltq_enable_irq(struct irq_data *data);
37extern int ltq_eiu_get_irq(int exin);
37 38
38/* clock handling */ 39/* clock handling */
39extern int clk_activate(struct clk *clk); 40extern int clk_activate(struct clk *clk);
@@ -41,6 +42,7 @@ extern void clk_deactivate(struct clk *clk);
41extern struct clk *clk_get_cpu(void); 42extern struct clk *clk_get_cpu(void);
42extern struct clk *clk_get_fpi(void); 43extern struct clk *clk_get_fpi(void);
43extern struct clk *clk_get_io(void); 44extern struct clk *clk_get_io(void);
45extern struct clk *clk_get_ppe(void);
44 46
45/* find out what bootsource we have */ 47/* find out what bootsource we have */
46extern unsigned char ltq_boot_select(void); 48extern unsigned char ltq_boot_select(void);
diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
new file mode 100644
index 000000000000..5a508f9f9432
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -0,0 +1,39 @@
1/*
2 * Ralink SoC register definitions
3 *
4 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13#ifndef _RALINK_REGS_H_
14#define _RALINK_REGS_H_
15
16extern __iomem void *rt_sysc_membase;
17extern __iomem void *rt_memc_membase;
18
19static inline void rt_sysc_w32(u32 val, unsigned reg)
20{
21 __raw_writel(val, rt_sysc_membase + reg);
22}
23
24static inline u32 rt_sysc_r32(unsigned reg)
25{
26 return __raw_readl(rt_sysc_membase + reg);
27}
28
29static inline void rt_memc_w32(u32 val, unsigned reg)
30{
31 __raw_writel(val, rt_memc_membase + reg);
32}
33
34static inline u32 rt_memc_r32(unsigned reg)
35{
36 return __raw_readl(rt_memc_membase + reg);
37}
38
39#endif /* _RALINK_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
new file mode 100644
index 000000000000..7d344f2d7d0a
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -0,0 +1,139 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
11 */
12
13#ifndef _RT305X_REGS_H_
14#define _RT305X_REGS_H_
15
16enum rt305x_soc_type {
17 RT305X_SOC_UNKNOWN = 0,
18 RT305X_SOC_RT3050,
19 RT305X_SOC_RT3052,
20 RT305X_SOC_RT3350,
21 RT305X_SOC_RT3352,
22 RT305X_SOC_RT5350,
23};
24
25extern enum rt305x_soc_type rt305x_soc;
26
27static inline int soc_is_rt3050(void)
28{
29 return rt305x_soc == RT305X_SOC_RT3050;
30}
31
32static inline int soc_is_rt3052(void)
33{
34 return rt305x_soc == RT305X_SOC_RT3052;
35}
36
37static inline int soc_is_rt305x(void)
38{
39 return soc_is_rt3050() || soc_is_rt3052();
40}
41
42static inline int soc_is_rt3350(void)
43{
44 return rt305x_soc == RT305X_SOC_RT3350;
45}
46
47static inline int soc_is_rt3352(void)
48{
49 return rt305x_soc == RT305X_SOC_RT3352;
50}
51
52static inline int soc_is_rt5350(void)
53{
54 return rt305x_soc == RT305X_SOC_RT5350;
55}
56
57#define RT305X_SYSC_BASE 0x10000000
58
59#define SYSC_REG_CHIP_NAME0 0x00
60#define SYSC_REG_CHIP_NAME1 0x04
61#define SYSC_REG_CHIP_ID 0x0c
62#define SYSC_REG_SYSTEM_CONFIG 0x10
63
64#define RT3052_CHIP_NAME0 0x30335452
65#define RT3052_CHIP_NAME1 0x20203235
66
67#define RT3350_CHIP_NAME0 0x33335452
68#define RT3350_CHIP_NAME1 0x20203035
69
70#define RT3352_CHIP_NAME0 0x33335452
71#define RT3352_CHIP_NAME1 0x20203235
72
73#define RT5350_CHIP_NAME0 0x33355452
74#define RT5350_CHIP_NAME1 0x20203035
75
76#define CHIP_ID_ID_MASK 0xff
77#define CHIP_ID_ID_SHIFT 8
78#define CHIP_ID_REV_MASK 0xff
79
80#define RT305X_SYSCFG_CPUCLK_SHIFT 18
81#define RT305X_SYSCFG_CPUCLK_MASK 0x1
82#define RT305X_SYSCFG_CPUCLK_LOW 0x0
83#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
84
85#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
86#define RT305X_SYSCFG_CPUCLK_MASK 0x1
87#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
88
89#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
90#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
91#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
92#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
93
94#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
95#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
96#define RT5350_SYSCFG0_CPUCLK_360 0x0
97#define RT5350_SYSCFG0_CPUCLK_320 0x2
98#define RT5350_SYSCFG0_CPUCLK_300 0x3
99
100/* multi function gpio pins */
101#define RT305X_GPIO_I2C_SD 1
102#define RT305X_GPIO_I2C_SCLK 2
103#define RT305X_GPIO_SPI_EN 3
104#define RT305X_GPIO_SPI_CLK 4
105/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
106#define RT305X_GPIO_7 7
107#define RT305X_GPIO_10 10
108#define RT305X_GPIO_14 14
109#define RT305X_GPIO_UART1_TXD 15
110#define RT305X_GPIO_UART1_RXD 16
111#define RT305X_GPIO_JTAG_TDO 17
112#define RT305X_GPIO_JTAG_TDI 18
113#define RT305X_GPIO_MDIO_MDC 22
114#define RT305X_GPIO_MDIO_MDIO 23
115#define RT305X_GPIO_SDRAM_MD16 24
116#define RT305X_GPIO_SDRAM_MD31 39
117#define RT305X_GPIO_GE0_TXD0 40
118#define RT305X_GPIO_GE0_RXCLK 51
119
120#define RT305X_GPIO_MODE_I2C BIT(0)
121#define RT305X_GPIO_MODE_SPI BIT(1)
122#define RT305X_GPIO_MODE_UART0_SHIFT 2
123#define RT305X_GPIO_MODE_UART0_MASK 0x7
124#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
125#define RT305X_GPIO_MODE_UARTF 0x0
126#define RT305X_GPIO_MODE_PCM_UARTF 0x1
127#define RT305X_GPIO_MODE_PCM_I2S 0x2
128#define RT305X_GPIO_MODE_I2S_UARTF 0x3
129#define RT305X_GPIO_MODE_PCM_GPIO 0x4
130#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
131#define RT305X_GPIO_MODE_GPIO_I2S 0x6
132#define RT305X_GPIO_MODE_GPIO 0x7
133#define RT305X_GPIO_MODE_UART1 BIT(5)
134#define RT305X_GPIO_MODE_JTAG BIT(6)
135#define RT305X_GPIO_MODE_MDIO BIT(7)
136#define RT305X_GPIO_MODE_SDRAM BIT(8)
137#define RT305X_GPIO_MODE_RGMII BIT(9)
138
139#endif
diff --git a/arch/mips/include/asm/mach-ralink/war.h b/arch/mips/include/asm/mach-ralink/war.h
new file mode 100644
index 000000000000..a7b712cf2d28
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MACH_RALINK_WAR_H
9#define __ASM_MACH_RALINK_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MACH_RALINK_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index 1465b1193b12..44a09a64160a 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -1,21 +1,14 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * This file is subject to the terms and conditions of the GNU General Public
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 3 * License. See the file "COPYING" in the main directory of this archive
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details. 4 * for more details.
13 * 5 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Defines of the MIPS boards specific address-MAP, registers, etc. 6 * Defines of the MIPS boards specific address-MAP, registers, etc.
7 *
8 * Copyright (C) 2000,2012 MIPS Technologies, Inc.
9 * All rights reserved.
10 * Authors: Carsten Langgaard <carstenl@mips.com>
11 * Steven J. Hill <sjhill@mips.com>
19 */ 12 */
20#ifndef __ASM_MIPS_BOARDS_GENERIC_H 13#ifndef __ASM_MIPS_BOARDS_GENERIC_H
21#define __ASM_MIPS_BOARDS_GENERIC_H 14#define __ASM_MIPS_BOARDS_GENERIC_H
@@ -30,13 +23,6 @@
30#define ASCII_DISPLAY_WORD_BASE 0x1f000410 23#define ASCII_DISPLAY_WORD_BASE 0x1f000410
31#define ASCII_DISPLAY_POS_BASE 0x1f000418 24#define ASCII_DISPLAY_POS_BASE 0x1f000418
32 25
33
34/*
35 * Yamon Prom print address.
36 */
37#define YAMON_PROM_PRINT_ADDR 0x1fc00504
38
39
40/* 26/*
41 * Reset register. 27 * Reset register.
42 */ 28 */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 2145162674b9..12b70c25906a 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -595,6 +595,8 @@
595#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 595#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 596#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 597#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
598#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
599#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
598 600
599#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 601#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
600#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 602#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
@@ -1158,36 +1160,26 @@ do { \
1158 __res; \ 1160 __res; \
1159}) 1161})
1160 1162
1163#ifdef HAVE_AS_DSP
1161#define rddsp(mask) \ 1164#define rddsp(mask) \
1162({ \ 1165({ \
1163 unsigned int __res; \ 1166 unsigned int __dspctl; \
1164 \ 1167 \
1165 __asm__ __volatile__( \ 1168 __asm__ __volatile__( \
1166 " .set push \n" \ 1169 " rddsp %0, %x1 \n" \
1167 " .set noat \n" \ 1170 : "=r" (__dspctl) \
1168 " # rddsp $1, %x1 \n" \
1169 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1170 " move %0, $1 \n" \
1171 " .set pop \n" \
1172 : "=r" (__res) \
1173 : "i" (mask)); \ 1171 : "i" (mask)); \
1174 __res; \ 1172 __dspctl; \
1175}) 1173})
1176 1174
1177#define wrdsp(val, mask) \ 1175#define wrdsp(val, mask) \
1178do { \ 1176do { \
1179 __asm__ __volatile__( \ 1177 __asm__ __volatile__( \
1180 " .set push \n" \ 1178 " wrdsp %0, %x1 \n" \
1181 " .set noat \n" \
1182 " move $1, %0 \n" \
1183 " # wrdsp $1, %x1 \n" \
1184 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1185 " .set pop \n" \
1186 : \ 1179 : \
1187 : "r" (val), "i" (mask)); \ 1180 : "r" (val), "i" (mask)); \
1188} while (0) 1181} while (0)
1189 1182
1190#if 0 /* Need DSP ASE capable assembler ... */
1191#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) 1183#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1192#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) 1184#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1193#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) 1185#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
@@ -1210,230 +1202,177 @@ do { \
1210 1202
1211#else 1203#else
1212 1204
1213#define mfhi0() \ 1205#ifdef CONFIG_CPU_MICROMIPS
1214({ \ 1206#define rddsp(mask) \
1215 unsigned long __treg; \
1216 \
1217 __asm__ __volatile__( \
1218 " .set push \n" \
1219 " .set noat \n" \
1220 " # mfhi %0, $ac0 \n" \
1221 " .word 0x00000810 \n" \
1222 " move %0, $1 \n" \
1223 " .set pop \n" \
1224 : "=r" (__treg)); \
1225 __treg; \
1226})
1227
1228#define mfhi1() \
1229({ \
1230 unsigned long __treg; \
1231 \
1232 __asm__ __volatile__( \
1233 " .set push \n" \
1234 " .set noat \n" \
1235 " # mfhi %0, $ac1 \n" \
1236 " .word 0x00200810 \n" \
1237 " move %0, $1 \n" \
1238 " .set pop \n" \
1239 : "=r" (__treg)); \
1240 __treg; \
1241})
1242
1243#define mfhi2() \
1244({ \
1245 unsigned long __treg; \
1246 \
1247 __asm__ __volatile__( \
1248 " .set push \n" \
1249 " .set noat \n" \
1250 " # mfhi %0, $ac2 \n" \
1251 " .word 0x00400810 \n" \
1252 " move %0, $1 \n" \
1253 " .set pop \n" \
1254 : "=r" (__treg)); \
1255 __treg; \
1256})
1257
1258#define mfhi3() \
1259({ \
1260 unsigned long __treg; \
1261 \
1262 __asm__ __volatile__( \
1263 " .set push \n" \
1264 " .set noat \n" \
1265 " # mfhi %0, $ac3 \n" \
1266 " .word 0x00600810 \n" \
1267 " move %0, $1 \n" \
1268 " .set pop \n" \
1269 : "=r" (__treg)); \
1270 __treg; \
1271})
1272
1273#define mflo0() \
1274({ \
1275 unsigned long __treg; \
1276 \
1277 __asm__ __volatile__( \
1278 " .set push \n" \
1279 " .set noat \n" \
1280 " # mflo %0, $ac0 \n" \
1281 " .word 0x00000812 \n" \
1282 " move %0, $1 \n" \
1283 " .set pop \n" \
1284 : "=r" (__treg)); \
1285 __treg; \
1286})
1287
1288#define mflo1() \
1289({ \
1290 unsigned long __treg; \
1291 \
1292 __asm__ __volatile__( \
1293 " .set push \n" \
1294 " .set noat \n" \
1295 " # mflo %0, $ac1 \n" \
1296 " .word 0x00200812 \n" \
1297 " move %0, $1 \n" \
1298 " .set pop \n" \
1299 : "=r" (__treg)); \
1300 __treg; \
1301})
1302
1303#define mflo2() \
1304({ \
1305 unsigned long __treg; \
1306 \
1307 __asm__ __volatile__( \
1308 " .set push \n" \
1309 " .set noat \n" \
1310 " # mflo %0, $ac2 \n" \
1311 " .word 0x00400812 \n" \
1312 " move %0, $1 \n" \
1313 " .set pop \n" \
1314 : "=r" (__treg)); \
1315 __treg; \
1316})
1317
1318#define mflo3() \
1319({ \ 1207({ \
1320 unsigned long __treg; \ 1208 unsigned int __res; \
1321 \ 1209 \
1322 __asm__ __volatile__( \ 1210 __asm__ __volatile__( \
1323 " .set push \n" \
1324 " .set noat \n" \
1325 " # mflo %0, $ac3 \n" \
1326 " .word 0x00600812 \n" \
1327 " move %0, $1 \n" \
1328 " .set pop \n" \
1329 : "=r" (__treg)); \
1330 __treg; \
1331})
1332
1333#define mthi0(x) \
1334do { \
1335 __asm__ __volatile__( \
1336 " .set push \n" \ 1211 " .set push \n" \
1337 " .set noat \n" \ 1212 " .set noat \n" \
1338 " move $1, %0 \n" \ 1213 " # rddsp $1, %x1 \n" \
1339 " # mthi $1, $ac0 \n" \ 1214 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1340 " .word 0x00200011 \n" \ 1215 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1216 " move %0, $1 \n" \
1341 " .set pop \n" \ 1217 " .set pop \n" \
1342 : \ 1218 : "=r" (__res) \
1343 : "r" (x)); \ 1219 : "i" (mask)); \
1344} while (0) 1220 __res; \
1221})
1345 1222
1346#define mthi1(x) \ 1223#define wrdsp(val, mask) \
1347do { \ 1224do { \
1348 __asm__ __volatile__( \ 1225 __asm__ __volatile__( \
1349 " .set push \n" \ 1226 " .set push \n" \
1350 " .set noat \n" \ 1227 " .set noat \n" \
1351 " move $1, %0 \n" \ 1228 " move $1, %0 \n" \
1352 " # mthi $1, $ac1 \n" \ 1229 " # wrdsp $1, %x1 \n" \
1353 " .word 0x00200811 \n" \ 1230 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1231 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1354 " .set pop \n" \ 1232 " .set pop \n" \
1355 : \ 1233 : \
1356 : "r" (x)); \ 1234 : "r" (val), "i" (mask)); \
1357} while (0) 1235} while (0)
1358 1236
1359#define mthi2(x) \ 1237#define _umips_dsp_mfxxx(ins) \
1360do { \ 1238({ \
1239 unsigned long __treg; \
1240 \
1361 __asm__ __volatile__( \ 1241 __asm__ __volatile__( \
1362 " .set push \n" \ 1242 " .set push \n" \
1363 " .set noat \n" \ 1243 " .set noat \n" \
1364 " move $1, %0 \n" \ 1244 " .hword 0x0001 \n" \
1365 " # mthi $1, $ac2 \n" \ 1245 " .hword %x1 \n" \
1366 " .word 0x00201011 \n" \ 1246 " move %0, $1 \n" \
1367 " .set pop \n" \ 1247 " .set pop \n" \
1368 : \ 1248 : "=r" (__treg) \
1369 : "r" (x)); \ 1249 : "i" (ins)); \
1370} while (0) 1250 __treg; \
1251})
1371 1252
1372#define mthi3(x) \ 1253#define _umips_dsp_mtxxx(val, ins) \
1373do { \ 1254do { \
1374 __asm__ __volatile__( \ 1255 __asm__ __volatile__( \
1375 " .set push \n" \ 1256 " .set push \n" \
1376 " .set noat \n" \ 1257 " .set noat \n" \
1377 " move $1, %0 \n" \ 1258 " move $1, %0 \n" \
1378 " # mthi $1, $ac3 \n" \ 1259 " .hword 0x0001 \n" \
1379 " .word 0x00201811 \n" \ 1260 " .hword %x1 \n" \
1380 " .set pop \n" \ 1261 " .set pop \n" \
1381 : \ 1262 : \
1382 : "r" (x)); \ 1263 : "r" (val), "i" (ins)); \
1383} while (0) 1264} while (0)
1384 1265
1385#define mtlo0(x) \ 1266#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1386do { \ 1267#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1268
1269#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1270#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1271
1272#define mflo0() _umips_dsp_mflo(0)
1273#define mflo1() _umips_dsp_mflo(1)
1274#define mflo2() _umips_dsp_mflo(2)
1275#define mflo3() _umips_dsp_mflo(3)
1276
1277#define mfhi0() _umips_dsp_mfhi(0)
1278#define mfhi1() _umips_dsp_mfhi(1)
1279#define mfhi2() _umips_dsp_mfhi(2)
1280#define mfhi3() _umips_dsp_mfhi(3)
1281
1282#define mtlo0(x) _umips_dsp_mtlo(x, 0)
1283#define mtlo1(x) _umips_dsp_mtlo(x, 1)
1284#define mtlo2(x) _umips_dsp_mtlo(x, 2)
1285#define mtlo3(x) _umips_dsp_mtlo(x, 3)
1286
1287#define mthi0(x) _umips_dsp_mthi(x, 0)
1288#define mthi1(x) _umips_dsp_mthi(x, 1)
1289#define mthi2(x) _umips_dsp_mthi(x, 2)
1290#define mthi3(x) _umips_dsp_mthi(x, 3)
1291
1292#else /* !CONFIG_CPU_MICROMIPS */
1293#define rddsp(mask) \
1294({ \
1295 unsigned int __res; \
1296 \
1387 __asm__ __volatile__( \ 1297 __asm__ __volatile__( \
1388 " .set push \n" \ 1298 " .set push \n" \
1389 " .set noat \n" \ 1299 " .set noat \n" \
1390 " move $1, %0 \n" \ 1300 " # rddsp $1, %x1 \n" \
1391 " # mtlo $1, $ac0 \n" \ 1301 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1392 " .word 0x00200013 \n" \ 1302 " move %0, $1 \n" \
1393 " .set pop \n" \ 1303 " .set pop \n" \
1394 : \ 1304 : "=r" (__res) \
1395 : "r" (x)); \ 1305 : "i" (mask)); \
1396} while (0) 1306 __res; \
1307})
1397 1308
1398#define mtlo1(x) \ 1309#define wrdsp(val, mask) \
1399do { \ 1310do { \
1400 __asm__ __volatile__( \ 1311 __asm__ __volatile__( \
1401 " .set push \n" \ 1312 " .set push \n" \
1402 " .set noat \n" \ 1313 " .set noat \n" \
1403 " move $1, %0 \n" \ 1314 " move $1, %0 \n" \
1404 " # mtlo $1, $ac1 \n" \ 1315 " # wrdsp $1, %x1 \n" \
1405 " .word 0x00200813 \n" \ 1316 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1406 " .set pop \n" \ 1317 " .set pop \n" \
1407 : \ 1318 : \
1408 : "r" (x)); \ 1319 : "r" (val), "i" (mask)); \
1409} while (0) 1320} while (0)
1410 1321
1411#define mtlo2(x) \ 1322#define _dsp_mfxxx(ins) \
1412do { \ 1323({ \
1324 unsigned long __treg; \
1325 \
1413 __asm__ __volatile__( \ 1326 __asm__ __volatile__( \
1414 " .set push \n" \ 1327 " .set push \n" \
1415 " .set noat \n" \ 1328 " .set noat \n" \
1416 " move $1, %0 \n" \ 1329 " .word (0x00000810 | %1) \n" \
1417 " # mtlo $1, $ac2 \n" \ 1330 " move %0, $1 \n" \
1418 " .word 0x00201013 \n" \
1419 " .set pop \n" \ 1331 " .set pop \n" \
1420 : \ 1332 : "=r" (__treg) \
1421 : "r" (x)); \ 1333 : "i" (ins)); \
1422} while (0) 1334 __treg; \
1335})
1423 1336
1424#define mtlo3(x) \ 1337#define _dsp_mtxxx(val, ins) \
1425do { \ 1338do { \
1426 __asm__ __volatile__( \ 1339 __asm__ __volatile__( \
1427 " .set push \n" \ 1340 " .set push \n" \
1428 " .set noat \n" \ 1341 " .set noat \n" \
1429 " move $1, %0 \n" \ 1342 " move $1, %0 \n" \
1430 " # mtlo $1, $ac3 \n" \ 1343 " .word (0x00200011 | %1) \n" \
1431 " .word 0x00201813 \n" \
1432 " .set pop \n" \ 1344 " .set pop \n" \
1433 : \ 1345 : \
1434 : "r" (x)); \ 1346 : "r" (val), "i" (ins)); \
1435} while (0) 1347} while (0)
1436 1348
1349#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1350#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1351
1352#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1353#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1354
1355#define mflo0() _dsp_mflo(0)
1356#define mflo1() _dsp_mflo(1)
1357#define mflo2() _dsp_mflo(2)
1358#define mflo3() _dsp_mflo(3)
1359
1360#define mfhi0() _dsp_mfhi(0)
1361#define mfhi1() _dsp_mfhi(1)
1362#define mfhi2() _dsp_mfhi(2)
1363#define mfhi3() _dsp_mfhi(3)
1364
1365#define mtlo0(x) _dsp_mtlo(x, 0)
1366#define mtlo1(x) _dsp_mtlo(x, 1)
1367#define mtlo2(x) _dsp_mtlo(x, 2)
1368#define mtlo3(x) _dsp_mtlo(x, 3)
1369
1370#define mthi0(x) _dsp_mthi(x, 0)
1371#define mthi1(x) _dsp_mthi(x, 1)
1372#define mthi2(x) _dsp_mthi(x, 2)
1373#define mthi3(x) _dsp_mthi(x, 3)
1374
1375#endif /* CONFIG_CPU_MICROMIPS */
1437#endif 1376#endif
1438 1377
1439/* 1378/*
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 8ffae43107e6..8ad2e0f81719 100644
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -68,6 +68,85 @@ do { \
68 __write_64bit_c0_register($9, 7, (val)); \ 68 __write_64bit_c0_register($9, 7, (val)); \
69} while (0) 69} while (0)
70 70
71/*
72 * Handling the 64 bit EIMR and EIRR registers in 32-bit mode with
73 * standard functions will be very inefficient. This provides
74 * optimized functions for the normal operations on the registers.
75 *
76 * Call with interrupts disabled.
77 */
78static inline void ack_c0_eirr(int irq)
79{
80 __asm__ __volatile__(
81 ".set push\n\t"
82 ".set mips64\n\t"
83 ".set noat\n\t"
84 "li $1, 1\n\t"
85 "dsllv $1, $1, %0\n\t"
86 "dmtc0 $1, $9, 6\n\t"
87 ".set pop"
88 : : "r" (irq));
89}
90
91static inline void set_c0_eimr(int irq)
92{
93 __asm__ __volatile__(
94 ".set push\n\t"
95 ".set mips64\n\t"
96 ".set noat\n\t"
97 "li $1, 1\n\t"
98 "dsllv %0, $1, %0\n\t"
99 "dmfc0 $1, $9, 7\n\t"
100 "or $1, %0\n\t"
101 "dmtc0 $1, $9, 7\n\t"
102 ".set pop"
103 : "+r" (irq));
104}
105
106static inline void clear_c0_eimr(int irq)
107{
108 __asm__ __volatile__(
109 ".set push\n\t"
110 ".set mips64\n\t"
111 ".set noat\n\t"
112 "li $1, 1\n\t"
113 "dsllv %0, $1, %0\n\t"
114 "dmfc0 $1, $9, 7\n\t"
115 "or $1, %0\n\t"
116 "xor $1, %0\n\t"
117 "dmtc0 $1, $9, 7\n\t"
118 ".set pop"
119 : "+r" (irq));
120}
121
122/*
123 * Read c0 eimr and c0 eirr, do AND of the two values, the result is
124 * the interrupts which are raised and are not masked.
125 */
126static inline uint64_t read_c0_eirr_and_eimr(void)
127{
128 uint64_t val;
129
130#ifdef CONFIG_64BIT
131 val = read_c0_eimr() & read_c0_eirr();
132#else
133 __asm__ __volatile__(
134 ".set push\n\t"
135 ".set mips64\n\t"
136 ".set noat\n\t"
137 "dmfc0 %M0, $9, 6\n\t"
138 "dmfc0 %L0, $9, 7\n\t"
139 "and %M0, %L0\n\t"
140 "dsll %L0, %M0, 32\n\t"
141 "dsra %M0, %M0, 32\n\t"
142 "dsra %L0, %L0, 32\n\t"
143 ".set pop"
144 : "=r" (val));
145#endif
146
147 return val;
148}
149
71static inline int hard_smp_processor_id(void) 150static inline int hard_smp_processor_id(void)
72{ 151{
73 return __read_32bit_c0_register($15, 1) & 0x3ff; 152 return __read_32bit_c0_register($15, 1) & 0x3ff;
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index 7b63a6b722a0..6d2e58a9a542 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -46,6 +46,8 @@
46#define CPU_BLOCKID_FPU 9 46#define CPU_BLOCKID_FPU 9
47#define CPU_BLOCKID_MAP 10 47#define CPU_BLOCKID_MAP 10
48 48
49#define ICU_DEFEATURE 0x100
50
49#define LSU_DEFEATURE 0x304 51#define LSU_DEFEATURE 0x304
50#define LSU_DEBUG_ADDR 0x305 52#define LSU_DEBUG_ADDR 0x305
51#define LSU_DEBUG_DATA0 0x306 53#define LSU_DEBUG_DATA0 0x306
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index 46ace0ca26d8..3df53017fe51 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -261,6 +261,8 @@
261#define PIC_LOCAL_SCHEDULING 1 261#define PIC_LOCAL_SCHEDULING 1
262#define PIC_GLOBAL_SCHEDULING 0 262#define PIC_GLOBAL_SCHEDULING 0
263 263
264#define PIC_CLK_HZ 133333333
265
264#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) 266#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
265#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) 267#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
266#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) 268#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
@@ -315,6 +317,12 @@ nlm_pic_read_timer(uint64_t base, int timer)
315 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); 317 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
316} 318}
317 319
320static inline uint32_t
321nlm_pic_read_timer32(uint64_t base, int timer)
322{
323 return (uint32_t)nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
324}
325
318static inline void 326static inline void
319nlm_pic_write_timer(uint64_t base, int timer, uint64_t value) 327nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
320{ 328{
@@ -376,9 +384,9 @@ nlm_pic_ack(uint64_t base, int irt_num)
376} 384}
377 385
378static inline void 386static inline void
379nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) 387nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
380{ 388{
381 nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, hwt); 389 nlm_pic_write_irt_direct(base, irt, en, 0, 0, irq, hwt);
382} 390}
383 391
384int nlm_irq_to_irt(int irq); 392int nlm_irq_to_irt(int irq);
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 2f549453585e..63c99176dffe 100644
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -35,10 +35,11 @@
35#ifndef _ASM_NLM_XLR_PIC_H 35#ifndef _ASM_NLM_XLR_PIC_H
36#define _ASM_NLM_XLR_PIC_H 36#define _ASM_NLM_XLR_PIC_H
37 37
38#define PIC_CLKS_PER_SEC 66666666ULL 38#define PIC_CLK_HZ 66666666
39/* PIC hardware interrupt numbers */ 39/* PIC hardware interrupt numbers */
40#define PIC_IRT_WD_INDEX 0 40#define PIC_IRT_WD_INDEX 0
41#define PIC_IRT_TIMER_0_INDEX 1 41#define PIC_IRT_TIMER_0_INDEX 1
42#define PIC_IRT_TIMER_INDEX(i) ((i) + PIC_IRT_TIMER_0_INDEX)
42#define PIC_IRT_TIMER_1_INDEX 2 43#define PIC_IRT_TIMER_1_INDEX 2
43#define PIC_IRT_TIMER_2_INDEX 3 44#define PIC_IRT_TIMER_2_INDEX 3
44#define PIC_IRT_TIMER_3_INDEX 4 45#define PIC_IRT_TIMER_3_INDEX 4
@@ -99,6 +100,7 @@
99 100
100/* PIC Registers */ 101/* PIC Registers */
101#define PIC_CTRL 0x00 102#define PIC_CTRL 0x00
103#define PIC_CTRL_STE 8 /* timer enable start bit */
102#define PIC_IPI 0x04 104#define PIC_IPI 0x04
103#define PIC_INT_ACK 0x06 105#define PIC_INT_ACK 0x06
104 106
@@ -251,12 +253,52 @@ nlm_pic_ack(uint64_t base, int irt)
251} 253}
252 254
253static inline void 255static inline void
254nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) 256nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en)
255{ 257{
256 nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt)); 258 nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt));
257 /* local scheduling, invalid, level by default */ 259 /* local scheduling, invalid, level by default */
258 nlm_write_reg(base, PIC_IRT_1(irt), 260 nlm_write_reg(base, PIC_IRT_1(irt),
259 (1 << 30) | (1 << 6) | irq); 261 (en << 30) | (1 << 6) | irq);
262}
263
264static inline uint64_t
265nlm_pic_read_timer(uint64_t base, int timer)
266{
267 uint32_t up1, up2, low;
268
269 up1 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
270 low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
271 up2 = nlm_read_reg(base, PIC_TIMER_COUNT_1(timer));
272
273 if (up1 != up2) /* wrapped, get the new low */
274 low = nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
275 return ((uint64_t)up2 << 32) | low;
276
277}
278
279static inline uint32_t
280nlm_pic_read_timer32(uint64_t base, int timer)
281{
282 return nlm_read_reg(base, PIC_TIMER_COUNT_0(timer));
283}
284
285static inline void
286nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
287{
288 uint32_t up, low;
289 uint64_t pic_ctrl = nlm_read_reg(base, PIC_CTRL);
290 int en;
291
292 en = (irq > 0);
293 up = value >> 32;
294 low = value & 0xFFFFFFFF;
295 nlm_write_reg(base, PIC_TIMER_MAXVAL_0(timer), low);
296 nlm_write_reg(base, PIC_TIMER_MAXVAL_1(timer), up);
297 nlm_pic_init_irt(base, PIC_IRT_TIMER_INDEX(timer), irq, cpu, 0);
298
299 /* enable the timer */
300 pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
301 nlm_write_reg(base, PIC_CTRL, pic_ctrl);
260} 302}
261#endif 303#endif
262#endif /* _ASM_NLM_XLR_PIC_H */ 304#endif /* _ASM_NLM_XLR_PIC_H */
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index e224876cc344..b8e24fd4cbc5 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -144,8 +144,13 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
144 144
145extern char * (*pcibios_plat_setup)(char *str); 145extern char * (*pcibios_plat_setup)(char *str);
146 146
147#ifdef CONFIG_OF
147/* this function parses memory ranges from a device node */ 148/* this function parses memory ranges from a device node */
148extern void pci_load_of_ranges(struct pci_controller *hose, 149extern void pci_load_of_ranges(struct pci_controller *hose,
149 struct device_node *node); 150 struct device_node *node);
151#else
152static inline void pci_load_of_ranges(struct pci_controller *hose,
153 struct device_node *node) {}
154#endif
150 155
151#endif /* _ASM_PCI_H */ 156#endif /* _ASM_PCI_H */
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 96353075cc60..debc8009bd58 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -75,7 +75,7 @@ extern int init_r4k_clocksource(void);
75 75
76static inline int init_mips_clocksource(void) 76static inline int init_mips_clocksource(void)
77{ 77{
78#ifdef CONFIG_CSRC_R4K 78#if defined(CONFIG_CSRC_R4K) && !defined(CONFIG_CSRC_GIC)
79 return init_r4k_clocksource(); 79 return init_r4k_clocksource();
80#else 80#else
81 return 0; 81 return 0;
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index c48ed923fd55..f81d98f6184c 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
27obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o 27obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
28obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o 28obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
29obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 29obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
30obj-$(CONFIG_CSRC_GIC) += csrc-gic.o
30obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 31obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
31 32
32obj-$(CONFIG_STACKTRACE) += stacktrace.o 33obj-$(CONFIG_STACKTRACE) += stacktrace.o
@@ -98,4 +99,35 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
98 99
99obj-$(CONFIG_JUMP_LABEL) += jump_label.o 100obj-$(CONFIG_JUMP_LABEL) += jump_label.o
100 101
102#
103# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe
104# to enable DSP assembler support here even if the MIPS Release 2 CPU we
105# are targetting does not support DSP because all code-paths making use of
106# it properly check that the running CPU *actually does* support these
107# instructions.
108#
109ifeq ($(CONFIG_CPU_MIPSR2), y)
110CFLAGS_DSP = -DHAVE_AS_DSP
111
112#
113# Check if assembler supports DSP ASE
114#
115ifeq ($(call cc-option-yn,-mdsp), y)
116CFLAGS_DSP += -mdsp
117endif
118
119#
120# Check if assembler supports DSP ASE Rev2
121#
122ifeq ($(call cc-option-yn,-mdspr2), y)
123CFLAGS_DSP += -mdspr2
124endif
125
126CFLAGS_signal.o = $(CFLAGS_DSP)
127CFLAGS_signal32.o = $(CFLAGS_DSP)
128CFLAGS_process.o = $(CFLAGS_DSP)
129CFLAGS_branch.o = $(CFLAGS_DSP)
130CFLAGS_ptrace.o = $(CFLAGS_DSP)
131endif
132
101CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) 133CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 2656c898e337..6bfccc227a95 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -201,6 +201,7 @@ void __init check_wait(void)
201 break; 201 break;
202 202
203 case CPU_M14KC: 203 case CPU_M14KC:
204 case CPU_M14KEC:
204 case CPU_24K: 205 case CPU_24K:
205 case CPU_34K: 206 case CPU_34K:
206 case CPU_1004K: 207 case CPU_1004K:
@@ -467,6 +468,10 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
467 c->ases |= MIPS_ASE_MIPSMT; 468 c->ases |= MIPS_ASE_MIPSMT;
468 if (config3 & MIPS_CONF3_ULRI) 469 if (config3 & MIPS_CONF3_ULRI)
469 c->options |= MIPS_CPU_ULRI; 470 c->options |= MIPS_CPU_ULRI;
471 if (config3 & MIPS_CONF3_ISA)
472 c->options |= MIPS_CPU_MICROMIPS;
473 if (config3 & MIPS_CONF3_VZ)
474 c->ases |= MIPS_ASE_VZ;
470 475
471 return config3 & MIPS_CONF_M; 476 return config3 & MIPS_CONF_M;
472} 477}
@@ -866,10 +871,13 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
866 __cpu_name[cpu] = "MIPS 20Kc"; 871 __cpu_name[cpu] = "MIPS 20Kc";
867 break; 872 break;
868 case PRID_IMP_24K: 873 case PRID_IMP_24K:
869 case PRID_IMP_24KE:
870 c->cputype = CPU_24K; 874 c->cputype = CPU_24K;
871 __cpu_name[cpu] = "MIPS 24Kc"; 875 __cpu_name[cpu] = "MIPS 24Kc";
872 break; 876 break;
877 case PRID_IMP_24KE:
878 c->cputype = CPU_24K;
879 __cpu_name[cpu] = "MIPS 24KEc";
880 break;
873 case PRID_IMP_25KF: 881 case PRID_IMP_25KF:
874 c->cputype = CPU_25KF; 882 c->cputype = CPU_25KF;
875 __cpu_name[cpu] = "MIPS 25Kc"; 883 __cpu_name[cpu] = "MIPS 25Kc";
@@ -886,6 +894,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
886 c->cputype = CPU_M14KC; 894 c->cputype = CPU_M14KC;
887 __cpu_name[cpu] = "MIPS M14Kc"; 895 __cpu_name[cpu] = "MIPS M14Kc";
888 break; 896 break;
897 case PRID_IMP_M14KEC:
898 c->cputype = CPU_M14KEC;
899 __cpu_name[cpu] = "MIPS M14KEc";
900 break;
889 case PRID_IMP_1004K: 901 case PRID_IMP_1004K:
890 c->cputype = CPU_1004K; 902 c->cputype = CPU_1004K;
891 __cpu_name[cpu] = "MIPS 1004Kc"; 903 __cpu_name[cpu] = "MIPS 1004Kc";
diff --git a/arch/mips/kernel/csrc-gic.c b/arch/mips/kernel/csrc-gic.c
new file mode 100644
index 000000000000..5dca24bce51b
--- /dev/null
+++ b/arch/mips/kernel/csrc-gic.c
@@ -0,0 +1,49 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/clocksource.h>
9#include <linux/init.h>
10
11#include <asm/time.h>
12#include <asm/gic.h>
13
14static cycle_t gic_hpt_read(struct clocksource *cs)
15{
16 unsigned int hi, hi2, lo;
17
18 do {
19 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
20 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
21 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
22 } while (hi2 != hi);
23
24 return (((cycle_t) hi) << 32) + lo;
25}
26
27static struct clocksource gic_clocksource = {
28 .name = "GIC",
29 .read = gic_hpt_read,
30 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
31};
32
33void __init gic_clocksource_init(unsigned int frequency)
34{
35 unsigned int config, bits;
36
37 /* Calculate the clocksource mask. */
38 GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), config);
39 bits = 32 + ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
40 (GIC_SH_CONFIG_COUNTBITS_SHF - 2));
41
42 /* Set clocksource mask. */
43 gic_clocksource.mask = CLOCKSOURCE_MASK(bits);
44
45 /* Calculate a somewhat reasonable rating value. */
46 gic_clocksource.rating = 200 + frequency / 10000000;
47
48 clocksource_register_hz(&gic_clocksource, frequency);
49}
diff --git a/arch/mips/kernel/early_printk.c b/arch/mips/kernel/early_printk.c
index 9ae813eb782e..9e6440eaa455 100644
--- a/arch/mips/kernel/early_printk.c
+++ b/arch/mips/kernel/early_printk.c
@@ -14,8 +14,7 @@
14 14
15extern void prom_putchar(char); 15extern void prom_putchar(char);
16 16
17static void __init 17static void early_console_write(struct console *con, const char *s, unsigned n)
18early_console_write(struct console *con, const char *s, unsigned n)
19{ 18{
20 while (n-- && *s) { 19 while (n-- && *s) {
21 if (*s == '\n') 20 if (*s == '\n')
@@ -25,7 +24,7 @@ early_console_write(struct console *con, const char *s, unsigned n)
25 } 24 }
26} 25}
27 26
28static struct console early_console __initdata = { 27static struct console early_console = {
29 .name = "early", 28 .name = "early",
30 .write = early_console_write, 29 .write = early_console_write,
31 .flags = CON_PRINTBUFFER | CON_BOOT, 30 .flags = CON_PRINTBUFFER | CON_BOOT,
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 0207a44917bf..72ef2d25cbf2 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -31,6 +31,7 @@
31#include <linux/interrupt.h> 31#include <linux/interrupt.h>
32#include <linux/kernel.h> 32#include <linux/kernel.h>
33#include <linux/irq.h> 33#include <linux/irq.h>
34#include <linux/irqdomain.h>
34 35
35#include <asm/irq_cpu.h> 36#include <asm/irq_cpu.h>
36#include <asm/mipsregs.h> 37#include <asm/mipsregs.h>
@@ -113,3 +114,44 @@ void __init mips_cpu_irq_init(void)
113 irq_set_chip_and_handler(i, &mips_cpu_irq_controller, 114 irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
114 handle_percpu_irq); 115 handle_percpu_irq);
115} 116}
117
118#ifdef CONFIG_IRQ_DOMAIN
119static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
120 irq_hw_number_t hw)
121{
122 static struct irq_chip *chip;
123
124 if (hw < 2 && cpu_has_mipsmt) {
125 /* Software interrupts are used for MT/CMT IPI */
126 chip = &mips_mt_cpu_irq_controller;
127 } else {
128 chip = &mips_cpu_irq_controller;
129 }
130
131 irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
132
133 return 0;
134}
135
136static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
137 .map = mips_cpu_intc_map,
138 .xlate = irq_domain_xlate_onecell,
139};
140
141int __init mips_cpu_intc_init(struct device_node *of_node,
142 struct device_node *parent)
143{
144 struct irq_domain *domain;
145
146 /* Mask interrupts. */
147 clear_c0_status(ST0_IM);
148 clear_c0_cause(CAUSEF_IP);
149
150 domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
151 &mips_cpu_intc_irq_domain_ops, NULL);
152 if (!domain)
153 panic("Failed to add irqdomain for MIPS CPU\n");
154
155 return 0;
156}
157#endif /* CONFIG_IRQ_DOMAIN */
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 79d4b8edbd76..135c4aadccbe 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -95,6 +95,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
95 if (cpu_has_dsp) seq_printf(m, "%s", " dsp"); 95 if (cpu_has_dsp) seq_printf(m, "%s", " dsp");
96 if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2"); 96 if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2");
97 if (cpu_has_mipsmt) seq_printf(m, "%s", " mt"); 97 if (cpu_has_mipsmt) seq_printf(m, "%s", " mt");
98 if (cpu_has_mmips) seq_printf(m, "%s", " micromips");
99 if (cpu_has_vz) seq_printf(m, "%s", " vz");
98 seq_printf(m, "\n"); 100 seq_printf(m, "\n");
99 101
100 seq_printf(m, "shadow register sets\t: %d\n", 102 seq_printf(m, "shadow register sets\t: %d\n",
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 653197e151d5..4c774d5d5087 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -480,34 +480,75 @@ static int __init early_parse_mem(char *p)
480} 480}
481early_param("mem", early_parse_mem); 481early_param("mem", early_parse_mem);
482 482
483static void __init arch_mem_init(char **cmdline_p) 483#ifdef CONFIG_PROC_VMCORE
484unsigned long setup_elfcorehdr, setup_elfcorehdr_size;
485static int __init early_parse_elfcorehdr(char *p)
486{
487 int i;
488
489 setup_elfcorehdr = memparse(p, &p);
490
491 for (i = 0; i < boot_mem_map.nr_map; i++) {
492 unsigned long start = boot_mem_map.map[i].addr;
493 unsigned long end = (boot_mem_map.map[i].addr +
494 boot_mem_map.map[i].size);
495 if (setup_elfcorehdr >= start && setup_elfcorehdr < end) {
496 /*
497 * Reserve from the elf core header to the end of
498 * the memory segment, that should all be kdump
499 * reserved memory.
500 */
501 setup_elfcorehdr_size = end - setup_elfcorehdr;
502 break;
503 }
504 }
505 /*
506 * If we don't find it in the memory map, then we shouldn't
507 * have to worry about it, as the new kernel won't use it.
508 */
509 return 0;
510}
511early_param("elfcorehdr", early_parse_elfcorehdr);
512#endif
513
514static void __init arch_mem_addpart(phys_t mem, phys_t end, int type)
484{ 515{
485 phys_t init_mem, init_end, init_size; 516 phys_t size;
517 int i;
486 518
519 size = end - mem;
520 if (!size)
521 return;
522
523 /* Make sure it is in the boot_mem_map */
524 for (i = 0; i < boot_mem_map.nr_map; i++) {
525 if (mem >= boot_mem_map.map[i].addr &&
526 mem < (boot_mem_map.map[i].addr +
527 boot_mem_map.map[i].size))
528 return;
529 }
530 add_memory_region(mem, size, type);
531}
532
533static void __init arch_mem_init(char **cmdline_p)
534{
487 extern void plat_mem_setup(void); 535 extern void plat_mem_setup(void);
488 536
489 /* call board setup routine */ 537 /* call board setup routine */
490 plat_mem_setup(); 538 plat_mem_setup();
491 539
492 init_mem = PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT; 540 /*
493 init_end = PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT; 541 * Make sure all kernel memory is in the maps. The "UP" and
494 init_size = init_end - init_mem; 542 * "DOWN" are opposite for initdata since if it crosses over
495 if (init_size) { 543 * into another memory section you don't want that to be
496 /* Make sure it is in the boot_mem_map */ 544 * freed when the initdata is freed.
497 int i, found; 545 */
498 found = 0; 546 arch_mem_addpart(PFN_DOWN(__pa_symbol(&_text)) << PAGE_SHIFT,
499 for (i = 0; i < boot_mem_map.nr_map; i++) { 547 PFN_UP(__pa_symbol(&_edata)) << PAGE_SHIFT,
500 if (init_mem >= boot_mem_map.map[i].addr && 548 BOOT_MEM_RAM);
501 init_mem < (boot_mem_map.map[i].addr + 549 arch_mem_addpart(PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT,
502 boot_mem_map.map[i].size)) { 550 PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT,
503 found = 1; 551 BOOT_MEM_INIT_RAM);
504 break;
505 }
506 }
507 if (!found)
508 add_memory_region(init_mem, init_size,
509 BOOT_MEM_INIT_RAM);
510 }
511 552
512 pr_info("Determined physical RAM map:\n"); 553 pr_info("Determined physical RAM map:\n");
513 print_memory_map(); 554 print_memory_map();
@@ -537,6 +578,14 @@ static void __init arch_mem_init(char **cmdline_p)
537 } 578 }
538 579
539 bootmem_init(); 580 bootmem_init();
581#ifdef CONFIG_PROC_VMCORE
582 if (setup_elfcorehdr && setup_elfcorehdr_size) {
583 printk(KERN_INFO "kdump reserved memory at %lx-%lx\n",
584 setup_elfcorehdr, setup_elfcorehdr_size);
585 reserve_bootmem(setup_elfcorehdr, setup_elfcorehdr_size,
586 BOOTMEM_DEFAULT);
587 }
588#endif
540#ifdef CONFIG_KEXEC 589#ifdef CONFIG_KEXEC
541 if (crashk_res.start != crashk_res.end) 590 if (crashk_res.start != crashk_res.end)
542 reserve_bootmem(crashk_res.start, 591 reserve_bootmem(crashk_res.start,
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 1c152a93dc7b..7186222dc5bb 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -41,6 +41,7 @@
41#include <asm/addrspace.h> 41#include <asm/addrspace.h>
42#include <asm/smtc.h> 42#include <asm/smtc.h>
43#include <asm/smtc_proc.h> 43#include <asm/smtc_proc.h>
44#include <asm/setup.h>
44 45
45/* 46/*
46 * SMTC Kernel needs to manipulate low-level CPU interrupt mask 47 * SMTC Kernel needs to manipulate low-level CPU interrupt mask
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 32fc5d4a22e5..b4c01522edde 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -697,18 +697,7 @@ static int vpe_run(struct vpe * v)
697 dmt_flag = dmt(); 697 dmt_flag = dmt();
698 vpeflags = dvpe(); 698 vpeflags = dvpe();
699 699
700 if (!list_empty(&v->tc)) { 700 if (list_empty(&v->tc)) {
701 if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) {
702 evpe(vpeflags);
703 emt(dmt_flag);
704 local_irq_restore(flags);
705
706 printk(KERN_WARNING
707 "VPE loader: TC %d is already in use.\n",
708 v->tc->index);
709 return -ENOEXEC;
710 }
711 } else {
712 evpe(vpeflags); 701 evpe(vpeflags);
713 emt(dmt_flag); 702 emt(dmt_flag);
714 local_irq_restore(flags); 703 local_irq_restore(flags);
@@ -720,6 +709,8 @@ static int vpe_run(struct vpe * v)
720 return -ENOEXEC; 709 return -ENOEXEC;
721 } 710 }
722 711
712 t = list_first_entry(&v->tc, struct tc, tc);
713
723 /* Put MVPE's into 'configuration state' */ 714 /* Put MVPE's into 'configuration state' */
724 set_c0_mvpcontrol(MVPCONTROL_VPC); 715 set_c0_mvpcontrol(MVPCONTROL_VPC);
725 716
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index 186fd3e44242..3fc2e6d70c77 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -26,13 +26,15 @@
26#include "prom.h" 26#include "prom.h"
27 27
28/* lantiq socs have 3 static clocks */ 28/* lantiq socs have 3 static clocks */
29static struct clk cpu_clk_generic[3]; 29static struct clk cpu_clk_generic[4];
30 30
31void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io) 31void clkdev_add_static(unsigned long cpu, unsigned long fpi,
32 unsigned long io, unsigned long ppe)
32{ 33{
33 cpu_clk_generic[0].rate = cpu; 34 cpu_clk_generic[0].rate = cpu;
34 cpu_clk_generic[1].rate = fpi; 35 cpu_clk_generic[1].rate = fpi;
35 cpu_clk_generic[2].rate = io; 36 cpu_clk_generic[2].rate = io;
37 cpu_clk_generic[3].rate = ppe;
36} 38}
37 39
38struct clk *clk_get_cpu(void) 40struct clk *clk_get_cpu(void)
@@ -51,6 +53,12 @@ struct clk *clk_get_io(void)
51 return &cpu_clk_generic[2]; 53 return &cpu_clk_generic[2];
52} 54}
53 55
56struct clk *clk_get_ppe(void)
57{
58 return &cpu_clk_generic[3];
59}
60EXPORT_SYMBOL_GPL(clk_get_ppe);
61
54static inline int clk_good(struct clk *clk) 62static inline int clk_good(struct clk *clk)
55{ 63{
56 return clk && !IS_ERR(clk); 64 return clk && !IS_ERR(clk);
diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h
index fa670602b91b..77e4bdb1fe8c 100644
--- a/arch/mips/lantiq/clk.h
+++ b/arch/mips/lantiq/clk.h
@@ -27,12 +27,15 @@
27#define CLOCK_167M 166666667 27#define CLOCK_167M 166666667
28#define CLOCK_196_608M 196608000 28#define CLOCK_196_608M 196608000
29#define CLOCK_200M 200000000 29#define CLOCK_200M 200000000
30#define CLOCK_222M 222000000
31#define CLOCK_240M 240000000
30#define CLOCK_250M 250000000 32#define CLOCK_250M 250000000
31#define CLOCK_266M 266666666 33#define CLOCK_266M 266666666
32#define CLOCK_300M 300000000 34#define CLOCK_300M 300000000
33#define CLOCK_333M 333333333 35#define CLOCK_333M 333333333
34#define CLOCK_393M 393215332 36#define CLOCK_393M 393215332
35#define CLOCK_400M 400000000 37#define CLOCK_400M 400000000
38#define CLOCK_450M 450000000
36#define CLOCK_500M 500000000 39#define CLOCK_500M 500000000
37#define CLOCK_600M 600000000 40#define CLOCK_600M 600000000
38 41
@@ -64,15 +67,17 @@ struct clk {
64}; 67};
65 68
66extern void clkdev_add_static(unsigned long cpu, unsigned long fpi, 69extern void clkdev_add_static(unsigned long cpu, unsigned long fpi,
67 unsigned long io); 70 unsigned long io, unsigned long ppe);
68 71
69extern unsigned long ltq_danube_cpu_hz(void); 72extern unsigned long ltq_danube_cpu_hz(void);
70extern unsigned long ltq_danube_fpi_hz(void); 73extern unsigned long ltq_danube_fpi_hz(void);
74extern unsigned long ltq_danube_pp32_hz(void);
71 75
72extern unsigned long ltq_ar9_cpu_hz(void); 76extern unsigned long ltq_ar9_cpu_hz(void);
73extern unsigned long ltq_ar9_fpi_hz(void); 77extern unsigned long ltq_ar9_fpi_hz(void);
74 78
75extern unsigned long ltq_vr9_cpu_hz(void); 79extern unsigned long ltq_vr9_cpu_hz(void);
76extern unsigned long ltq_vr9_fpi_hz(void); 80extern unsigned long ltq_vr9_fpi_hz(void);
81extern unsigned long ltq_vr9_pp32_hz(void);
77 82
78#endif 83#endif
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
index 2d4ced332b37..ff4894a833ee 100644
--- a/arch/mips/lantiq/falcon/sysctrl.c
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -241,9 +241,9 @@ void __init ltq_soc_init(void)
241 241
242 /* get our 3 static rates for cpu, fpi and io clocks */ 242 /* get our 3 static rates for cpu, fpi and io clocks */
243 if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV) 243 if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
244 clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M); 244 clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0);
245 else 245 else
246 clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M); 246 clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0);
247 247
248 /* add our clock domains */ 248 /* add our clock domains */
249 clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0); 249 clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 5323308aab3f..51194875f158 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -33,17 +33,10 @@
33/* register definitions - external irqs */ 33/* register definitions - external irqs */
34#define LTQ_EIU_EXIN_C 0x0000 34#define LTQ_EIU_EXIN_C 0x0000
35#define LTQ_EIU_EXIN_INIC 0x0004 35#define LTQ_EIU_EXIN_INIC 0x0004
36#define LTQ_EIU_EXIN_INC 0x0008
36#define LTQ_EIU_EXIN_INEN 0x000C 37#define LTQ_EIU_EXIN_INEN 0x000C
37 38
38/* irq numbers used by the external interrupt unit (EIU) */ 39/* number of external interrupts */
39#define LTQ_EIU_IR0 (INT_NUM_IM4_IRL0 + 30)
40#define LTQ_EIU_IR1 (INT_NUM_IM3_IRL0 + 31)
41#define LTQ_EIU_IR2 (INT_NUM_IM1_IRL0 + 26)
42#define LTQ_EIU_IR3 INT_NUM_IM1_IRL0
43#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
44#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
45#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
46#define XWAY_EXIN_COUNT 3
47#define MAX_EIU 6 40#define MAX_EIU 6
48 41
49/* the performance counter */ 42/* the performance counter */
@@ -72,20 +65,19 @@
72int gic_present; 65int gic_present;
73#endif 66#endif
74 67
75static unsigned short ltq_eiu_irq[MAX_EIU] = {
76 LTQ_EIU_IR0,
77 LTQ_EIU_IR1,
78 LTQ_EIU_IR2,
79 LTQ_EIU_IR3,
80 LTQ_EIU_IR4,
81 LTQ_EIU_IR5,
82};
83
84static int exin_avail; 68static int exin_avail;
69static struct resource ltq_eiu_irq[MAX_EIU];
85static void __iomem *ltq_icu_membase[MAX_IM]; 70static void __iomem *ltq_icu_membase[MAX_IM];
86static void __iomem *ltq_eiu_membase; 71static void __iomem *ltq_eiu_membase;
87static struct irq_domain *ltq_domain; 72static struct irq_domain *ltq_domain;
88 73
74int ltq_eiu_get_irq(int exin)
75{
76 if (exin < exin_avail)
77 return ltq_eiu_irq[exin].start;
78 return -1;
79}
80
89void ltq_disable_irq(struct irq_data *d) 81void ltq_disable_irq(struct irq_data *d)
90{ 82{
91 u32 ier = LTQ_ICU_IM0_IER; 83 u32 ier = LTQ_ICU_IM0_IER;
@@ -128,19 +120,65 @@ void ltq_enable_irq(struct irq_data *d)
128 ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier); 120 ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
129} 121}
130 122
123static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
124{
125 int i;
126
127 for (i = 0; i < MAX_EIU; i++) {
128 if (d->hwirq == ltq_eiu_irq[i].start) {
129 int val = 0;
130 int edge = 0;
131
132 switch (type) {
133 case IRQF_TRIGGER_NONE:
134 break;
135 case IRQF_TRIGGER_RISING:
136 val = 1;
137 edge = 1;
138 break;
139 case IRQF_TRIGGER_FALLING:
140 val = 2;
141 edge = 1;
142 break;
143 case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
144 val = 3;
145 edge = 1;
146 break;
147 case IRQF_TRIGGER_HIGH:
148 val = 5;
149 break;
150 case IRQF_TRIGGER_LOW:
151 val = 6;
152 break;
153 default:
154 pr_err("invalid type %d for irq %ld\n",
155 type, d->hwirq);
156 return -EINVAL;
157 }
158
159 if (edge)
160 irq_set_handler(d->hwirq, handle_edge_irq);
161
162 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
163 (val << (i * 4)), LTQ_EIU_EXIN_C);
164 }
165 }
166
167 return 0;
168}
169
131static unsigned int ltq_startup_eiu_irq(struct irq_data *d) 170static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
132{ 171{
133 int i; 172 int i;
134 173
135 ltq_enable_irq(d); 174 ltq_enable_irq(d);
136 for (i = 0; i < MAX_EIU; i++) { 175 for (i = 0; i < MAX_EIU; i++) {
137 if (d->hwirq == ltq_eiu_irq[i]) { 176 if (d->hwirq == ltq_eiu_irq[i].start) {
138 /* low level - we should really handle set_type */ 177 /* by default we are low level triggered */
139 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) | 178 ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
140 (0x6 << (i * 4)), LTQ_EIU_EXIN_C);
141 /* clear all pending */ 179 /* clear all pending */
142 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i), 180 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
143 LTQ_EIU_EXIN_INIC); 181 LTQ_EIU_EXIN_INC);
144 /* enable */ 182 /* enable */
145 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i), 183 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
146 LTQ_EIU_EXIN_INEN); 184 LTQ_EIU_EXIN_INEN);
@@ -157,7 +195,7 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d)
157 195
158 ltq_disable_irq(d); 196 ltq_disable_irq(d);
159 for (i = 0; i < MAX_EIU; i++) { 197 for (i = 0; i < MAX_EIU; i++) {
160 if (d->hwirq == ltq_eiu_irq[i]) { 198 if (d->hwirq == ltq_eiu_irq[i].start) {
161 /* disable */ 199 /* disable */
162 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i), 200 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
163 LTQ_EIU_EXIN_INEN); 201 LTQ_EIU_EXIN_INEN);
@@ -186,6 +224,7 @@ static struct irq_chip ltq_eiu_type = {
186 .irq_ack = ltq_ack_irq, 224 .irq_ack = ltq_ack_irq,
187 .irq_mask = ltq_disable_irq, 225 .irq_mask = ltq_disable_irq,
188 .irq_mask_ack = ltq_mask_and_ack_irq, 226 .irq_mask_ack = ltq_mask_and_ack_irq,
227 .irq_set_type = ltq_eiu_settype,
189}; 228};
190 229
191static void ltq_hw_irqdispatch(int module) 230static void ltq_hw_irqdispatch(int module)
@@ -301,7 +340,7 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
301 return 0; 340 return 0;
302 341
303 for (i = 0; i < exin_avail; i++) 342 for (i = 0; i < exin_avail; i++)
304 if (hw == ltq_eiu_irq[i]) 343 if (hw == ltq_eiu_irq[i].start)
305 chip = &ltq_eiu_type; 344 chip = &ltq_eiu_type;
306 345
307 irq_set_chip_and_handler(hw, chip, handle_level_irq); 346 irq_set_chip_and_handler(hw, chip, handle_level_irq);
@@ -323,7 +362,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
323{ 362{
324 struct device_node *eiu_node; 363 struct device_node *eiu_node;
325 struct resource res; 364 struct resource res;
326 int i; 365 int i, ret;
327 366
328 for (i = 0; i < MAX_IM; i++) { 367 for (i = 0; i < MAX_IM; i++) {
329 if (of_address_to_resource(node, i, &res)) 368 if (of_address_to_resource(node, i, &res))
@@ -340,17 +379,19 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
340 } 379 }
341 380
342 /* the external interrupts are optional and xway only */ 381 /* the external interrupts are optional and xway only */
343 eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu"); 382 eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
344 if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) { 383 if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
345 /* find out how many external irq sources we have */ 384 /* find out how many external irq sources we have */
346 const __be32 *count = of_get_property(node, 385 exin_avail = of_irq_count(eiu_node);
347 "lantiq,count", NULL);
348 386
349 if (count)
350 exin_avail = *count;
351 if (exin_avail > MAX_EIU) 387 if (exin_avail > MAX_EIU)
352 exin_avail = MAX_EIU; 388 exin_avail = MAX_EIU;
353 389
390 ret = of_irq_to_resource_table(eiu_node,
391 ltq_eiu_irq, exin_avail);
392 if (ret != exin_avail)
393 panic("failed to load external irq resources\n");
394
354 if (request_mem_region(res.start, resource_size(&res), 395 if (request_mem_region(res.start, resource_size(&res),
355 res.name) < 0) 396 res.name) < 0)
356 pr_err("Failed to request eiu memory"); 397 pr_err("Failed to request eiu memory");
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
index 9aa17f79a742..1ab576dc9bd1 100644
--- a/arch/mips/lantiq/xway/clk.c
+++ b/arch/mips/lantiq/xway/clk.c
@@ -53,6 +53,29 @@ unsigned long ltq_danube_cpu_hz(void)
53 } 53 }
54} 54}
55 55
56unsigned long ltq_danube_pp32_hz(void)
57{
58 unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
59 unsigned long clk;
60
61 switch (clksys) {
62 case 1:
63 clk = CLOCK_240M;
64 break;
65 case 2:
66 clk = CLOCK_222M;
67 break;
68 case 3:
69 clk = CLOCK_133M;
70 break;
71 default:
72 clk = CLOCK_266M;
73 break;
74 }
75
76 return clk;
77}
78
56unsigned long ltq_ar9_sys_hz(void) 79unsigned long ltq_ar9_sys_hz(void)
57{ 80{
58 if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2) 81 if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
@@ -149,3 +172,23 @@ unsigned long ltq_vr9_fpi_hz(void)
149 172
150 return clk; 173 return clk;
151} 174}
175
176unsigned long ltq_vr9_pp32_hz(void)
177{
178 unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3;
179 unsigned long clk;
180
181 switch (clksys) {
182 case 1:
183 clk = CLOCK_450M;
184 break;
185 case 2:
186 clk = CLOCK_300M;
187 break;
188 default:
189 clk = CLOCK_500M;
190 break;
191 }
192
193 return clk;
194}
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 544dbb7fb421..1fa0f175357e 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -78,10 +78,19 @@ static struct ltq_xrx200_gphy_reset {
78/* reset and boot a gphy. these phys only exist on xrx200 SoC */ 78/* reset and boot a gphy. these phys only exist on xrx200 SoC */
79int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr) 79int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
80{ 80{
81 struct clk *clk;
82
81 if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) { 83 if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
82 dev_err(dev, "this SoC has no GPHY\n"); 84 dev_err(dev, "this SoC has no GPHY\n");
83 return -EINVAL; 85 return -EINVAL;
84 } 86 }
87
88 clk = clk_get_sys("1f203000.rcu", "gphy");
89 if (IS_ERR(clk))
90 return PTR_ERR(clk);
91
92 clk_enable(clk);
93
85 if (id > 1) { 94 if (id > 1) {
86 dev_err(dev, "%u is an invalid gphy id\n", id); 95 dev_err(dev, "%u is an invalid gphy id\n", id);
87 return -EINVAL; 96 return -EINVAL;
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 3925e6609acc..c24924fe087d 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -305,7 +305,7 @@ void __init ltq_soc_init(void)
305 305
306 /* check if all the core register ranges are available */ 306 /* check if all the core register ranges are available */
307 if (!np_pmu || !np_cgu || !np_ebu) 307 if (!np_pmu || !np_cgu || !np_ebu)
308 panic("Failed to load core nodess from devicetree"); 308 panic("Failed to load core nodes from devicetree");
309 309
310 if (of_address_to_resource(np_pmu, 0, &res_pmu) || 310 if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
311 of_address_to_resource(np_cgu, 0, &res_cgu) || 311 of_address_to_resource(np_cgu, 0, &res_cgu) ||
@@ -356,14 +356,16 @@ void __init ltq_soc_init(void)
356 356
357 if (of_machine_is_compatible("lantiq,ase")) { 357 if (of_machine_is_compatible("lantiq,ase")) {
358 if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) 358 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
359 clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); 359 clkdev_add_static(CLOCK_266M, CLOCK_133M,
360 CLOCK_133M, CLOCK_266M);
360 else 361 else
361 clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); 362 clkdev_add_static(CLOCK_133M, CLOCK_133M,
363 CLOCK_133M, CLOCK_133M);
362 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY), 364 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
363 clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY); 365 clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
364 } else if (of_machine_is_compatible("lantiq,vr9")) { 366 } else if (of_machine_is_compatible("lantiq,vr9")) {
365 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), 367 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
366 ltq_vr9_fpi_hz()); 368 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
367 clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY); 369 clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
368 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK); 370 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
369 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI); 371 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
@@ -374,12 +376,13 @@ void __init ltq_soc_init(void)
374 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | 376 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
375 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | 377 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
376 PMU_PPE_QSB | PMU_PPE_TOP); 378 PMU_PPE_QSB | PMU_PPE_TOP);
379 clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);
377 } else if (of_machine_is_compatible("lantiq,ar9")) { 380 } else if (of_machine_is_compatible("lantiq,ar9")) {
378 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), 381 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
379 ltq_ar9_fpi_hz()); 382 ltq_ar9_fpi_hz(), CLOCK_250M);
380 clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH); 383 clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
381 } else { 384 } else {
382 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), 385 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
383 ltq_danube_fpi_hz()); 386 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
384 } 387 }
385} 388}
diff --git a/arch/mips/loongson1/common/prom.c b/arch/mips/loongson1/common/prom.c
index 2dd9c5648d79..2a47af5a55c3 100644
--- a/arch/mips/loongson1/common/prom.c
+++ b/arch/mips/loongson1/common/prom.c
@@ -73,7 +73,7 @@ void __init prom_free_prom_memory(void)
73 73
74#define PORT(offset) (u8 *)(KSEG1ADDR(LS1X_UART0_BASE + offset)) 74#define PORT(offset) (u8 *)(KSEG1ADDR(LS1X_UART0_BASE + offset))
75 75
76void __init prom_putchar(char c) 76void prom_putchar(char c)
77{ 77{
78 int timeout; 78 int timeout;
79 79
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index d45f8e28b470..ecca559b8d7b 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1057,6 +1057,7 @@ static void __cpuinit probe_pcache(void)
1057 break; 1057 break;
1058 1058
1059 case CPU_M14KC: 1059 case CPU_M14KC:
1060 case CPU_M14KEC:
1060 case CPU_24K: 1061 case CPU_24K:
1061 case CPU_34K: 1062 case CPU_34K:
1062 case CPU_74K: 1063 case CPU_74K:
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 36b9bd89c799..820e6612d744 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -581,6 +581,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
581 case CPU_4KC: 581 case CPU_4KC:
582 case CPU_4KEC: 582 case CPU_4KEC:
583 case CPU_M14KC: 583 case CPU_M14KC:
584 case CPU_M14KEC:
584 case CPU_SB1: 585 case CPU_SB1:
585 case CPU_SB1A: 586 case CPU_SB1A:
586 case CPU_4KSC: 587 case CPU_4KSC:
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 8607b0dd29f6..a144b89cf9ba 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -17,7 +17,6 @@
17 * 17 *
18 * Setting up the clock on the MIPS boards. 18 * Setting up the clock on the MIPS boards.
19 */ 19 */
20
21#include <linux/types.h> 20#include <linux/types.h>
22#include <linux/i8253.h> 21#include <linux/i8253.h>
23#include <linux/init.h> 22#include <linux/init.h>
@@ -25,7 +24,6 @@
25#include <linux/sched.h> 24#include <linux/sched.h>
26#include <linux/spinlock.h> 25#include <linux/spinlock.h>
27#include <linux/interrupt.h> 26#include <linux/interrupt.h>
28#include <linux/time.h>
29#include <linux/timex.h> 27#include <linux/timex.h>
30#include <linux/mc146818rtc.h> 28#include <linux/mc146818rtc.h>
31 29
@@ -34,11 +32,11 @@
34#include <asm/hardirq.h> 32#include <asm/hardirq.h>
35#include <asm/irq.h> 33#include <asm/irq.h>
36#include <asm/div64.h> 34#include <asm/div64.h>
37#include <asm/cpu.h>
38#include <asm/setup.h> 35#include <asm/setup.h>
39#include <asm/time.h> 36#include <asm/time.h>
40#include <asm/mc146818-time.h> 37#include <asm/mc146818-time.h>
41#include <asm/msc01_ic.h> 38#include <asm/msc01_ic.h>
39#include <asm/gic.h>
42 40
43#include <asm/mips-boards/generic.h> 41#include <asm/mips-boards/generic.h>
44#include <asm/mips-boards/prom.h> 42#include <asm/mips-boards/prom.h>
@@ -46,6 +44,7 @@
46#include <asm/mips-boards/maltaint.h> 44#include <asm/mips-boards/maltaint.h>
47 45
48unsigned long cpu_khz; 46unsigned long cpu_khz;
47int gic_frequency;
49 48
50static int mips_cpu_timer_irq; 49static int mips_cpu_timer_irq;
51static int mips_cpu_perf_irq; 50static int mips_cpu_perf_irq;
@@ -61,44 +60,50 @@ static void mips_perf_dispatch(void)
61 do_IRQ(mips_cpu_perf_irq); 60 do_IRQ(mips_cpu_perf_irq);
62} 61}
63 62
63static unsigned int freqround(unsigned int freq, unsigned int amount)
64{
65 freq += amount;
66 freq -= freq % (amount*2);
67 return freq;
68}
69
64/* 70/*
65 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect 71 * Estimate CPU and GIC frequencies.
66 */ 72 */
67static unsigned int __init estimate_cpu_frequency(void) 73static void __init estimate_frequencies(void)
68{ 74{
69 unsigned int prid = read_c0_prid() & 0xffff00;
70 unsigned int count;
71
72 unsigned long flags; 75 unsigned long flags;
73 unsigned int start; 76 unsigned int count, start;
77 unsigned int giccount = 0, gicstart = 0;
74 78
75 local_irq_save(flags); 79 local_irq_save(flags);
76 80
77 /* Start counter exactly on falling edge of update flag */ 81 /* Start counter exactly on falling edge of update flag. */
78 while (CMOS_READ(RTC_REG_A) & RTC_UIP); 82 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
79 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 83 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
80 84
81 /* Start r4k counter. */ 85 /* Initialize counters. */
82 start = read_c0_count(); 86 start = read_c0_count();
87 if (gic_present)
88 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), gicstart);
83 89
84 /* Read counter exactly on falling edge of update flag */ 90 /* Read counter exactly on falling edge of update flag. */
85 while (CMOS_READ(RTC_REG_A) & RTC_UIP); 91 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
86 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 92 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
87 93
88 count = read_c0_count() - start; 94 count = read_c0_count();
95 if (gic_present)
96 GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), giccount);
89 97
90 /* restore interrupts */
91 local_irq_restore(flags); 98 local_irq_restore(flags);
92 99
93 mips_hpt_frequency = count; 100 count -= start;
94 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) && 101 if (gic_present)
95 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF))) 102 giccount -= gicstart;
96 count *= 2;
97
98 count += 5000; /* round */
99 count -= count%10000;
100 103
101 return count; 104 mips_hpt_frequency = count;
105 if (gic_present)
106 gic_frequency = giccount;
102} 107}
103 108
104void read_persistent_clock(struct timespec *ts) 109void read_persistent_clock(struct timespec *ts)
@@ -144,22 +149,34 @@ unsigned int __cpuinit get_c0_compare_int(void)
144 149
145void __init plat_time_init(void) 150void __init plat_time_init(void)
146{ 151{
147 unsigned int est_freq; 152 unsigned int prid = read_c0_prid() & 0xffff00;
148 153 unsigned int freq;
149 /* Set Data mode - binary. */
150 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
151
152 est_freq = estimate_cpu_frequency();
153 154
154 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 155 estimate_frequencies();
155 (est_freq%1000000)*100/1000000);
156 156
157 cpu_khz = est_freq / 1000; 157 freq = mips_hpt_frequency;
158 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
159 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
160 freq *= 2;
161 freq = freqround(freq, 5000);
162 pr_debug("CPU frequency %d.%02d MHz\n", freq/1000000,
163 (freq%1000000)*100/1000000);
164 cpu_khz = freq / 1000;
165
166 if (gic_present) {
167 freq = freqround(gic_frequency, 5000);
168 pr_debug("GIC frequency %d.%02d MHz\n", freq/1000000,
169 (freq%1000000)*100/1000000);
170 gic_clocksource_init(gic_frequency);
171 } else
172 init_r4k_clocksource();
158 173
159 mips_scroll_message(); 174#ifdef CONFIG_I8253
160#ifdef CONFIG_I8253 /* Only Malta has a PIT */ 175 /* Only Malta has a PIT. */
161 setup_pit_timer(); 176 setup_pit_timer();
162#endif 177#endif
163 178
179 mips_scroll_message();
180
164 plat_perf_setup(); 181 plat_perf_setup();
165} 182}
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
index 780832e391ff..9f84c60bf535 100644
--- a/arch/mips/netlogic/common/irq.c
+++ b/arch/mips/netlogic/common/irq.c
@@ -105,21 +105,23 @@ static void xlp_pic_disable(struct irq_data *d)
105static void xlp_pic_mask_ack(struct irq_data *d) 105static void xlp_pic_mask_ack(struct irq_data *d)
106{ 106{
107 struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d); 107 struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
108 uint64_t mask = 1ull << pd->picirq;
109 108
110 write_c0_eirr(mask); /* ack by writing EIRR */ 109 clear_c0_eimr(pd->picirq);
110 ack_c0_eirr(pd->picirq);
111} 111}
112 112
113static void xlp_pic_unmask(struct irq_data *d) 113static void xlp_pic_unmask(struct irq_data *d)
114{ 114{
115 struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d); 115 struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
116 116
117 if (!pd) 117 BUG_ON(!pd);
118 return;
119 118
120 if (pd->extra_ack) 119 if (pd->extra_ack)
121 pd->extra_ack(d); 120 pd->extra_ack(d);
122 121
122 /* re-enable the intr on this cpu */
123 set_c0_eimr(pd->picirq);
124
123 /* Ack is a single write, no need to lock */ 125 /* Ack is a single write, no need to lock */
124 nlm_pic_ack(pd->node->picbase, pd->irt); 126 nlm_pic_ack(pd->node->picbase, pd->irt);
125} 127}
@@ -134,32 +136,17 @@ static struct irq_chip xlp_pic = {
134 136
135static void cpuintr_disable(struct irq_data *d) 137static void cpuintr_disable(struct irq_data *d)
136{ 138{
137 uint64_t eimr; 139 clear_c0_eimr(d->irq);
138 uint64_t mask = 1ull << d->irq;
139
140 eimr = read_c0_eimr();
141 write_c0_eimr(eimr & ~mask);
142} 140}
143 141
144static void cpuintr_enable(struct irq_data *d) 142static void cpuintr_enable(struct irq_data *d)
145{ 143{
146 uint64_t eimr; 144 set_c0_eimr(d->irq);
147 uint64_t mask = 1ull << d->irq;
148
149 eimr = read_c0_eimr();
150 write_c0_eimr(eimr | mask);
151} 145}
152 146
153static void cpuintr_ack(struct irq_data *d) 147static void cpuintr_ack(struct irq_data *d)
154{ 148{
155 uint64_t mask = 1ull << d->irq; 149 ack_c0_eirr(d->irq);
156
157 write_c0_eirr(mask);
158}
159
160static void cpuintr_nop(struct irq_data *d)
161{
162 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
163} 150}
164 151
165/* 152/*
@@ -170,9 +157,9 @@ struct irq_chip nlm_cpu_intr = {
170 .name = "XLP-CPU-INTR", 157 .name = "XLP-CPU-INTR",
171 .irq_enable = cpuintr_enable, 158 .irq_enable = cpuintr_enable,
172 .irq_disable = cpuintr_disable, 159 .irq_disable = cpuintr_disable,
173 .irq_mask = cpuintr_nop, 160 .irq_mask = cpuintr_disable,
174 .irq_ack = cpuintr_nop, 161 .irq_ack = cpuintr_ack,
175 .irq_eoi = cpuintr_ack, 162 .irq_eoi = cpuintr_enable,
176}; 163};
177 164
178static void __init nlm_init_percpu_irqs(void) 165static void __init nlm_init_percpu_irqs(void)
@@ -230,7 +217,7 @@ static void nlm_init_node_irqs(int node)
230 nlm_setup_pic_irq(node, i, i, irt); 217 nlm_setup_pic_irq(node, i, i, irt);
231 /* set interrupts to first cpu in node */ 218 /* set interrupts to first cpu in node */
232 nlm_pic_init_irt(nodep->picbase, irt, i, 219 nlm_pic_init_irt(nodep->picbase, irt, i,
233 node * NLM_CPUS_PER_NODE); 220 node * NLM_CPUS_PER_NODE, 0);
234 irqmask |= (1ull << i); 221 irqmask |= (1ull << i);
235 } 222 }
236 nodep->irqmask = irqmask; 223 nodep->irqmask = irqmask;
@@ -265,7 +252,7 @@ asmlinkage void plat_irq_dispatch(void)
265 int i, node; 252 int i, node;
266 253
267 node = nlm_nodeid(); 254 node = nlm_nodeid();
268 eirr = read_c0_eirr() & read_c0_eimr(); 255 eirr = read_c0_eirr_and_eimr();
269 256
270 i = __ilog2_u64(eirr); 257 i = __ilog2_u64(eirr);
271 if (i == -1) 258 if (i == -1)
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index a080d9ee3cd7..2bb95dcfe20a 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -84,15 +84,19 @@ void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
84/* IRQ_IPI_SMP_FUNCTION Handler */ 84/* IRQ_IPI_SMP_FUNCTION Handler */
85void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc) 85void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
86{ 86{
87 write_c0_eirr(1ull << irq); 87 clear_c0_eimr(irq);
88 ack_c0_eirr(irq);
88 smp_call_function_interrupt(); 89 smp_call_function_interrupt();
90 set_c0_eimr(irq);
89} 91}
90 92
91/* IRQ_IPI_SMP_RESCHEDULE handler */ 93/* IRQ_IPI_SMP_RESCHEDULE handler */
92void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc) 94void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
93{ 95{
94 write_c0_eirr(1ull << irq); 96 clear_c0_eimr(irq);
97 ack_c0_eirr(irq);
95 scheduler_ipi(); 98 scheduler_ipi();
99 set_c0_eimr(irq);
96} 100}
97 101
98/* 102/*
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index 280ff5855ef7..026517488584 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -69,6 +69,12 @@
69#endif 69#endif
70 mtcr t1, t0 70 mtcr t1, t0
71 71
72 li t0, ICU_DEFEATURE
73 mfcr t1, t0
74 ori t1, 0x1000 /* Enable Icache partitioning */
75 mtcr t1, t0
76
77
72#ifdef XLP_AX_WORKAROUND 78#ifdef XLP_AX_WORKAROUND
73 li t0, SCHED_DEFEATURE 79 li t0, SCHED_DEFEATURE
74 lui t1, 0x0100 /* Disable BRU accepting ALU ops */ 80 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
diff --git a/arch/mips/netlogic/common/time.c b/arch/mips/netlogic/common/time.c
index bd3e498157ff..5c56555380bb 100644
--- a/arch/mips/netlogic/common/time.c
+++ b/arch/mips/netlogic/common/time.c
@@ -35,17 +35,73 @@
35#include <linux/init.h> 35#include <linux/init.h>
36 36
37#include <asm/time.h> 37#include <asm/time.h>
38#include <asm/cpu-features.h>
39
38#include <asm/netlogic/interrupt.h> 40#include <asm/netlogic/interrupt.h>
39#include <asm/netlogic/common.h> 41#include <asm/netlogic/common.h>
42#include <asm/netlogic/haldefs.h>
43#include <asm/netlogic/common.h>
44
45#if defined(CONFIG_CPU_XLP)
46#include <asm/netlogic/xlp-hal/iomap.h>
47#include <asm/netlogic/xlp-hal/xlp.h>
48#include <asm/netlogic/xlp-hal/pic.h>
49#elif defined(CONFIG_CPU_XLR)
50#include <asm/netlogic/xlr/iomap.h>
51#include <asm/netlogic/xlr/pic.h>
52#include <asm/netlogic/xlr/xlr.h>
53#else
54#error "Unknown CPU"
55#endif
40 56
41unsigned int __cpuinit get_c0_compare_int(void) 57unsigned int __cpuinit get_c0_compare_int(void)
42{ 58{
43 return IRQ_TIMER; 59 return IRQ_TIMER;
44} 60}
45 61
62static cycle_t nlm_get_pic_timer(struct clocksource *cs)
63{
64 uint64_t picbase = nlm_get_node(0)->picbase;
65
66 return ~nlm_pic_read_timer(picbase, PIC_CLOCK_TIMER);
67}
68
69static cycle_t nlm_get_pic_timer32(struct clocksource *cs)
70{
71 uint64_t picbase = nlm_get_node(0)->picbase;
72
73 return ~nlm_pic_read_timer32(picbase, PIC_CLOCK_TIMER);
74}
75
76static struct clocksource csrc_pic = {
77 .name = "PIC",
78 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
79};
80
81static void nlm_init_pic_timer(void)
82{
83 uint64_t picbase = nlm_get_node(0)->picbase;
84
85 nlm_pic_set_timer(picbase, PIC_CLOCK_TIMER, ~0ULL, 0, 0);
86 if (current_cpu_data.cputype == CPU_XLR) {
87 csrc_pic.mask = CLOCKSOURCE_MASK(32);
88 csrc_pic.read = nlm_get_pic_timer32;
89 } else {
90 csrc_pic.mask = CLOCKSOURCE_MASK(64);
91 csrc_pic.read = nlm_get_pic_timer;
92 }
93 csrc_pic.rating = 1000;
94 clocksource_register_hz(&csrc_pic, PIC_CLK_HZ);
95}
96
46void __init plat_time_init(void) 97void __init plat_time_init(void)
47{ 98{
99 nlm_init_pic_timer();
48 mips_hpt_frequency = nlm_get_cpu_frequency(); 100 mips_hpt_frequency = nlm_get_cpu_frequency();
101 if (current_cpu_type() == CPU_XLR)
102 preset_lpj = mips_hpt_frequency / (3 * HZ);
103 else
104 preset_lpj = mips_hpt_frequency / (2 * HZ);
49 pr_info("MIPS counter frequency [%ld]\n", 105 pr_info("MIPS counter frequency [%ld]\n",
50 (unsigned long)mips_hpt_frequency); 106 (unsigned long)mips_hpt_frequency);
51} 107}
diff --git a/arch/mips/netlogic/xlp/wakeup.c b/arch/mips/netlogic/xlp/wakeup.c
index cb9010642ac3..abb3e08cc052 100644
--- a/arch/mips/netlogic/xlp/wakeup.c
+++ b/arch/mips/netlogic/xlp/wakeup.c
@@ -51,7 +51,7 @@
51#include <asm/netlogic/xlp-hal/xlp.h> 51#include <asm/netlogic/xlp-hal/xlp.h>
52#include <asm/netlogic/xlp-hal/sys.h> 52#include <asm/netlogic/xlp-hal/sys.h>
53 53
54static int xlp_wakeup_core(uint64_t sysbase, int core) 54static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
55{ 55{
56 uint32_t coremask, value; 56 uint32_t coremask, value;
57 int count; 57 int count;
@@ -82,36 +82,51 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
82 struct nlm_soc_info *nodep; 82 struct nlm_soc_info *nodep;
83 uint64_t syspcibase; 83 uint64_t syspcibase;
84 uint32_t syscoremask; 84 uint32_t syscoremask;
85 int core, n, cpu; 85 int core, n, cpu, count, val;
86 86
87 for (n = 0; n < NLM_NR_NODES; n++) { 87 for (n = 0; n < NLM_NR_NODES; n++) {
88 syspcibase = nlm_get_sys_pcibase(n); 88 syspcibase = nlm_get_sys_pcibase(n);
89 if (nlm_read_reg(syspcibase, 0) == 0xffffffff) 89 if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
90 break; 90 break;
91 91
92 /* read cores in reset from SYS and account for boot cpu */ 92 /* read cores in reset from SYS */
93 nlm_node_init(n); 93 if (n != 0)
94 nlm_node_init(n);
94 nodep = nlm_get_node(n); 95 nodep = nlm_get_node(n);
95 syscoremask = nlm_read_sys_reg(nodep->sysbase, SYS_CPU_RESET); 96 syscoremask = nlm_read_sys_reg(nodep->sysbase, SYS_CPU_RESET);
96 if (n == 0) 97 /* The boot cpu */
98 if (n == 0) {
97 syscoremask |= 1; 99 syscoremask |= 1;
100 nodep->coremask = 1;
101 }
98 102
99 for (core = 0; core < NLM_CORES_PER_NODE; core++) { 103 for (core = 0; core < NLM_CORES_PER_NODE; core++) {
104 /* we will be on node 0 core 0 */
105 if (n == 0 && core == 0)
106 continue;
107
100 /* see if the core exists */ 108 /* see if the core exists */
101 if ((syscoremask & (1 << core)) == 0) 109 if ((syscoremask & (1 << core)) == 0)
102 continue; 110 continue;
103 111
104 /* see if at least the first thread is enabled */ 112 /* see if at least the first hw thread is enabled */
105 cpu = (n * NLM_CORES_PER_NODE + core) 113 cpu = (n * NLM_CORES_PER_NODE + core)
106 * NLM_THREADS_PER_CORE; 114 * NLM_THREADS_PER_CORE;
107 if (!cpumask_test_cpu(cpu, wakeup_mask)) 115 if (!cpumask_test_cpu(cpu, wakeup_mask))
108 continue; 116 continue;
109 117
110 /* wake up the core */ 118 /* wake up the core */
111 if (xlp_wakeup_core(nodep->sysbase, core)) 119 if (!xlp_wakeup_core(nodep->sysbase, n, core))
112 nodep->coremask |= 1u << core; 120 continue;
113 else 121
114 pr_err("Failed to enable core %d\n", core); 122 /* core is up */
123 nodep->coremask |= 1u << core;
124
125 /* spin until the first hw thread sets its ready */
126 count = 0x20000000;
127 do {
128 val = *(volatile int *)&nlm_cpu_ready[cpu];
129 } while (val == 0 && --count > 0);
115 } 130 }
116 } 131 }
117} 132}
diff --git a/arch/mips/netlogic/xlr/fmn-config.c b/arch/mips/netlogic/xlr/fmn-config.c
index f5bddf95bf24..ed3bf0e3f309 100644
--- a/arch/mips/netlogic/xlr/fmn-config.c
+++ b/arch/mips/netlogic/xlr/fmn-config.c
@@ -216,6 +216,8 @@ void xlr_board_info_setup(void)
216 case PRID_IMP_NETLOGIC_XLS404B: 216 case PRID_IMP_NETLOGIC_XLS404B:
217 case PRID_IMP_NETLOGIC_XLS408B: 217 case PRID_IMP_NETLOGIC_XLS408B:
218 case PRID_IMP_NETLOGIC_XLS416B: 218 case PRID_IMP_NETLOGIC_XLS416B:
219 case PRID_IMP_NETLOGIC_XLS608B:
220 case PRID_IMP_NETLOGIC_XLS616B:
219 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0, 221 setup_fmn_cc(&gmac[0], FMN_STNID_GMAC0,
220 FMN_STNID_GMAC0_TX3, 8, 8, 32); 222 FMN_STNID_GMAC0_TX3, 8, 8, 32);
221 setup_fmn_cc(&gmac[1], FMN_STNID_GMAC1_FR_0, 223 setup_fmn_cc(&gmac[1], FMN_STNID_GMAC1_FR_0,
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index e287277d32b0..7b96a91f4773 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -64,7 +64,7 @@ void nlm_xlr_uart_out(struct uart_port *p, int offset, int value)
64 .iotype = UPIO_MEM32, \ 64 .iotype = UPIO_MEM32, \
65 .flags = (UPF_SKIP_TEST | \ 65 .flags = (UPF_SKIP_TEST | \
66 UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF),\ 66 UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF),\
67 .uartclk = PIC_CLKS_PER_SEC, \ 67 .uartclk = PIC_CLK_HZ, \
68 .type = PORT_16550A, \ 68 .type = PORT_16550A, \
69 .serial_in = nlm_xlr_uart_in, \ 69 .serial_in = nlm_xlr_uart_in, \
70 .serial_out = nlm_xlr_uart_out, \ 70 .serial_out = nlm_xlr_uart_out, \
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index f088efb8fe4c..e3e094100e3e 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -70,7 +70,7 @@ static void __init nlm_early_serial_setup(void)
70 s.iotype = UPIO_MEM32; 70 s.iotype = UPIO_MEM32;
71 s.regshift = 2; 71 s.regshift = 2;
72 s.irq = PIC_UART_0_IRQ; 72 s.irq = PIC_UART_0_IRQ;
73 s.uartclk = PIC_CLKS_PER_SEC; 73 s.uartclk = PIC_CLK_HZ;
74 s.serial_in = nlm_xlr_uart_in; 74 s.serial_in = nlm_xlr_uart_in;
75 s.serial_out = nlm_xlr_uart_out; 75 s.serial_out = nlm_xlr_uart_out;
76 s.mapbase = uart_base; 76 s.mapbase = uart_base;
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 56f2cf221c7d..af763e838fdd 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -78,6 +78,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
78 switch (current_cpu_type()) { 78 switch (current_cpu_type()) {
79 case CPU_5KC: 79 case CPU_5KC:
80 case CPU_M14KC: 80 case CPU_M14KC:
81 case CPU_M14KEC:
81 case CPU_20KC: 82 case CPU_20KC:
82 case CPU_24K: 83 case CPU_24K:
83 case CPU_25KF: 84 case CPU_25KF:
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 1cfab95755b9..1fd361462c03 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -351,6 +351,10 @@ static int __init mipsxx_init(void)
351 op_model_mipsxx_ops.cpu_type = "mips/M14Kc"; 351 op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
352 break; 352 break;
353 353
354 case CPU_M14KEC:
355 op_model_mipsxx_ops.cpu_type = "mips/M14KEc";
356 break;
357
354 case CPU_20KC: 358 case CPU_20KC:
355 op_model_mipsxx_ops.cpu_type = "mips/20K"; 359 op_model_mipsxx_ops.cpu_type = "mips/20K";
356 break; 360 break;
diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c
index 6eaa4f2d0e38..412ec025cf55 100644
--- a/arch/mips/pci/pci-ar71xx.c
+++ b/arch/mips/pci/pci-ar71xx.c
@@ -18,26 +18,11 @@
18#include <linux/pci.h> 18#include <linux/pci.h>
19#include <linux/pci_regs.h> 19#include <linux/pci_regs.h>
20#include <linux/interrupt.h> 20#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
21 23
22#include <asm/mach-ath79/ar71xx_regs.h> 24#include <asm/mach-ath79/ar71xx_regs.h>
23#include <asm/mach-ath79/ath79.h> 25#include <asm/mach-ath79/ath79.h>
24#include <asm/mach-ath79/pci.h>
25
26#define AR71XX_PCI_MEM_BASE 0x10000000
27#define AR71XX_PCI_MEM_SIZE 0x07000000
28
29#define AR71XX_PCI_WIN0_OFFS 0x10000000
30#define AR71XX_PCI_WIN1_OFFS 0x11000000
31#define AR71XX_PCI_WIN2_OFFS 0x12000000
32#define AR71XX_PCI_WIN3_OFFS 0x13000000
33#define AR71XX_PCI_WIN4_OFFS 0x14000000
34#define AR71XX_PCI_WIN5_OFFS 0x15000000
35#define AR71XX_PCI_WIN6_OFFS 0x16000000
36#define AR71XX_PCI_WIN7_OFFS 0x07000000
37
38#define AR71XX_PCI_CFG_BASE \
39 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
40#define AR71XX_PCI_CFG_SIZE 0x100
41 26
42#define AR71XX_PCI_REG_CRP_AD_CBE 0x00 27#define AR71XX_PCI_REG_CRP_AD_CBE 0x00
43#define AR71XX_PCI_REG_CRP_WRDATA 0x04 28#define AR71XX_PCI_REG_CRP_WRDATA 0x04
@@ -63,8 +48,15 @@
63 48
64#define AR71XX_PCI_IRQ_COUNT 5 49#define AR71XX_PCI_IRQ_COUNT 5
65 50
66static DEFINE_SPINLOCK(ar71xx_pci_lock); 51struct ar71xx_pci_controller {
67static void __iomem *ar71xx_pcicfg_base; 52 void __iomem *cfg_base;
53 spinlock_t lock;
54 int irq;
55 int irq_base;
56 struct pci_controller pci_ctrl;
57 struct resource io_res;
58 struct resource mem_res;
59};
68 60
69/* Byte lane enable bits */ 61/* Byte lane enable bits */
70static const u8 ar71xx_pci_ble_table[4][4] = { 62static const u8 ar71xx_pci_ble_table[4][4] = {
@@ -107,9 +99,18 @@ static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
107 return ret; 99 return ret;
108} 100}
109 101
110static int ar71xx_pci_check_error(int quiet) 102static inline struct ar71xx_pci_controller *
103pci_bus_to_ar71xx_controller(struct pci_bus *bus)
111{ 104{
112 void __iomem *base = ar71xx_pcicfg_base; 105 struct pci_controller *hose;
106
107 hose = (struct pci_controller *) bus->sysdata;
108 return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
109}
110
111static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
112{
113 void __iomem *base = apc->cfg_base;
113 u32 pci_err; 114 u32 pci_err;
114 u32 ahb_err; 115 u32 ahb_err;
115 116
@@ -144,9 +145,10 @@ static int ar71xx_pci_check_error(int quiet)
144 return !!(ahb_err | pci_err); 145 return !!(ahb_err | pci_err);
145} 146}
146 147
147static inline void ar71xx_pci_local_write(int where, int size, u32 value) 148static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
149 int where, int size, u32 value)
148{ 150{
149 void __iomem *base = ar71xx_pcicfg_base; 151 void __iomem *base = apc->cfg_base;
150 u32 ad_cbe; 152 u32 ad_cbe;
151 153
152 value = value << (8 * (where & 3)); 154 value = value << (8 * (where & 3));
@@ -162,7 +164,8 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
162 unsigned int devfn, 164 unsigned int devfn,
163 int where, int size, u32 cmd) 165 int where, int size, u32 cmd)
164{ 166{
165 void __iomem *base = ar71xx_pcicfg_base; 167 struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
168 void __iomem *base = apc->cfg_base;
166 u32 addr; 169 u32 addr;
167 170
168 addr = ar71xx_pci_bus_addr(bus, devfn, where); 171 addr = ar71xx_pci_bus_addr(bus, devfn, where);
@@ -171,13 +174,14 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
171 __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), 174 __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
172 base + AR71XX_PCI_REG_CFG_CBE); 175 base + AR71XX_PCI_REG_CFG_CBE);
173 176
174 return ar71xx_pci_check_error(1); 177 return ar71xx_pci_check_error(apc, 1);
175} 178}
176 179
177static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, 180static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
178 int where, int size, u32 *value) 181 int where, int size, u32 *value)
179{ 182{
180 void __iomem *base = ar71xx_pcicfg_base; 183 struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
184 void __iomem *base = apc->cfg_base;
181 unsigned long flags; 185 unsigned long flags;
182 u32 data; 186 u32 data;
183 int err; 187 int err;
@@ -186,7 +190,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
186 ret = PCIBIOS_SUCCESSFUL; 190 ret = PCIBIOS_SUCCESSFUL;
187 data = ~0; 191 data = ~0;
188 192
189 spin_lock_irqsave(&ar71xx_pci_lock, flags); 193 spin_lock_irqsave(&apc->lock, flags);
190 194
191 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, 195 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
192 AR71XX_PCI_CFG_CMD_READ); 196 AR71XX_PCI_CFG_CMD_READ);
@@ -195,7 +199,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
195 else 199 else
196 data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); 200 data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
197 201
198 spin_unlock_irqrestore(&ar71xx_pci_lock, flags); 202 spin_unlock_irqrestore(&apc->lock, flags);
199 203
200 *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7]; 204 *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
201 205
@@ -205,7 +209,8 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
205static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, 209static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
206 int where, int size, u32 value) 210 int where, int size, u32 value)
207{ 211{
208 void __iomem *base = ar71xx_pcicfg_base; 212 struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
213 void __iomem *base = apc->cfg_base;
209 unsigned long flags; 214 unsigned long flags;
210 int err; 215 int err;
211 int ret; 216 int ret;
@@ -213,7 +218,7 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
213 value = value << (8 * (where & 3)); 218 value = value << (8 * (where & 3));
214 ret = PCIBIOS_SUCCESSFUL; 219 ret = PCIBIOS_SUCCESSFUL;
215 220
216 spin_lock_irqsave(&ar71xx_pci_lock, flags); 221 spin_lock_irqsave(&apc->lock, flags);
217 222
218 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, 223 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
219 AR71XX_PCI_CFG_CMD_WRITE); 224 AR71XX_PCI_CFG_CMD_WRITE);
@@ -222,7 +227,7 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
222 else 227 else
223 __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); 228 __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
224 229
225 spin_unlock_irqrestore(&ar71xx_pci_lock, flags); 230 spin_unlock_irqrestore(&apc->lock, flags);
226 231
227 return ret; 232 return ret;
228} 233}
@@ -232,45 +237,28 @@ static struct pci_ops ar71xx_pci_ops = {
232 .write = ar71xx_pci_write_config, 237 .write = ar71xx_pci_write_config,
233}; 238};
234 239
235static struct resource ar71xx_pci_io_resource = {
236 .name = "PCI IO space",
237 .start = 0,
238 .end = 0,
239 .flags = IORESOURCE_IO,
240};
241
242static struct resource ar71xx_pci_mem_resource = {
243 .name = "PCI memory space",
244 .start = AR71XX_PCI_MEM_BASE,
245 .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
246 .flags = IORESOURCE_MEM
247};
248
249static struct pci_controller ar71xx_pci_controller = {
250 .pci_ops = &ar71xx_pci_ops,
251 .mem_resource = &ar71xx_pci_mem_resource,
252 .io_resource = &ar71xx_pci_io_resource,
253};
254
255static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) 240static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
256{ 241{
242 struct ar71xx_pci_controller *apc;
257 void __iomem *base = ath79_reset_base; 243 void __iomem *base = ath79_reset_base;
258 u32 pending; 244 u32 pending;
259 245
246 apc = irq_get_handler_data(irq);
247
260 pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & 248 pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
261 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); 249 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
262 250
263 if (pending & AR71XX_PCI_INT_DEV0) 251 if (pending & AR71XX_PCI_INT_DEV0)
264 generic_handle_irq(ATH79_PCI_IRQ(0)); 252 generic_handle_irq(apc->irq_base + 0);
265 253
266 else if (pending & AR71XX_PCI_INT_DEV1) 254 else if (pending & AR71XX_PCI_INT_DEV1)
267 generic_handle_irq(ATH79_PCI_IRQ(1)); 255 generic_handle_irq(apc->irq_base + 1);
268 256
269 else if (pending & AR71XX_PCI_INT_DEV2) 257 else if (pending & AR71XX_PCI_INT_DEV2)
270 generic_handle_irq(ATH79_PCI_IRQ(2)); 258 generic_handle_irq(apc->irq_base + 2);
271 259
272 else if (pending & AR71XX_PCI_INT_CORE) 260 else if (pending & AR71XX_PCI_INT_CORE)
273 generic_handle_irq(ATH79_PCI_IRQ(4)); 261 generic_handle_irq(apc->irq_base + 4);
274 262
275 else 263 else
276 spurious_interrupt(); 264 spurious_interrupt();
@@ -278,10 +266,14 @@ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
278 266
279static void ar71xx_pci_irq_unmask(struct irq_data *d) 267static void ar71xx_pci_irq_unmask(struct irq_data *d)
280{ 268{
281 unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; 269 struct ar71xx_pci_controller *apc;
270 unsigned int irq;
282 void __iomem *base = ath79_reset_base; 271 void __iomem *base = ath79_reset_base;
283 u32 t; 272 u32 t;
284 273
274 apc = irq_data_get_irq_chip_data(d);
275 irq = d->irq - apc->irq_base;
276
285 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); 277 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
286 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); 278 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
287 279
@@ -291,10 +283,14 @@ static void ar71xx_pci_irq_unmask(struct irq_data *d)
291 283
292static void ar71xx_pci_irq_mask(struct irq_data *d) 284static void ar71xx_pci_irq_mask(struct irq_data *d)
293{ 285{
294 unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE; 286 struct ar71xx_pci_controller *apc;
287 unsigned int irq;
295 void __iomem *base = ath79_reset_base; 288 void __iomem *base = ath79_reset_base;
296 u32 t; 289 u32 t;
297 290
291 apc = irq_data_get_irq_chip_data(d);
292 irq = d->irq - apc->irq_base;
293
298 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); 294 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
299 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); 295 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
300 296
@@ -309,7 +305,7 @@ static struct irq_chip ar71xx_pci_irq_chip = {
309 .irq_mask_ack = ar71xx_pci_irq_mask, 305 .irq_mask_ack = ar71xx_pci_irq_mask,
310}; 306};
311 307
312static __init void ar71xx_pci_irq_init(void) 308static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
313{ 309{
314 void __iomem *base = ath79_reset_base; 310 void __iomem *base = ath79_reset_base;
315 int i; 311 int i;
@@ -319,15 +315,19 @@ static __init void ar71xx_pci_irq_init(void)
319 315
320 BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT); 316 BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
321 317
322 for (i = ATH79_PCI_IRQ_BASE; 318 apc->irq_base = ATH79_PCI_IRQ_BASE;
323 i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) 319 for (i = apc->irq_base;
320 i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
324 irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, 321 irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
325 handle_level_irq); 322 handle_level_irq);
323 irq_set_chip_data(i, apc);
324 }
326 325
327 irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler); 326 irq_set_handler_data(apc->irq, apc);
327 irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
328} 328}
329 329
330static __init void ar71xx_pci_reset(void) 330static void ar71xx_pci_reset(void)
331{ 331{
332 void __iomem *ddr_base = ath79_ddr_base; 332 void __iomem *ddr_base = ath79_ddr_base;
333 333
@@ -349,27 +349,83 @@ static __init void ar71xx_pci_reset(void)
349 mdelay(100); 349 mdelay(100);
350} 350}
351 351
352__init int ar71xx_pcibios_init(void) 352static int ar71xx_pci_probe(struct platform_device *pdev)
353{ 353{
354 struct ar71xx_pci_controller *apc;
355 struct resource *res;
354 u32 t; 356 u32 t;
355 357
356 ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE); 358 apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
357 if (ar71xx_pcicfg_base == NULL) 359 GFP_KERNEL);
360 if (!apc)
361 return -ENOMEM;
362
363 spin_lock_init(&apc->lock);
364
365 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
366 if (!res)
367 return -EINVAL;
368
369 apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res);
370 if (!apc->cfg_base)
358 return -ENOMEM; 371 return -ENOMEM;
359 372
373 apc->irq = platform_get_irq(pdev, 0);
374 if (apc->irq < 0)
375 return -EINVAL;
376
377 res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
378 if (!res)
379 return -EINVAL;
380
381 apc->io_res.parent = res;
382 apc->io_res.name = "PCI IO space";
383 apc->io_res.start = res->start;
384 apc->io_res.end = res->end;
385 apc->io_res.flags = IORESOURCE_IO;
386
387 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
388 if (!res)
389 return -EINVAL;
390
391 apc->mem_res.parent = res;
392 apc->mem_res.name = "PCI memory space";
393 apc->mem_res.start = res->start;
394 apc->mem_res.end = res->end;
395 apc->mem_res.flags = IORESOURCE_MEM;
396
360 ar71xx_pci_reset(); 397 ar71xx_pci_reset();
361 398
362 /* setup COMMAND register */ 399 /* setup COMMAND register */
363 t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE 400 t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
364 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; 401 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
365 ar71xx_pci_local_write(PCI_COMMAND, 4, t); 402 ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
366 403
367 /* clear bus errors */ 404 /* clear bus errors */
368 ar71xx_pci_check_error(1); 405 ar71xx_pci_check_error(apc, 1);
406
407 ar71xx_pci_irq_init(apc);
369 408
370 ar71xx_pci_irq_init(); 409 apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
410 apc->pci_ctrl.mem_resource = &apc->mem_res;
411 apc->pci_ctrl.io_resource = &apc->io_res;
371 412
372 register_pci_controller(&ar71xx_pci_controller); 413 register_pci_controller(&apc->pci_ctrl);
373 414
374 return 0; 415 return 0;
375} 416}
417
418static struct platform_driver ar71xx_pci_driver = {
419 .probe = ar71xx_pci_probe,
420 .driver = {
421 .name = "ar71xx-pci",
422 .owner = THIS_MODULE,
423 },
424};
425
426static int __init ar71xx_pci_init(void)
427{
428 return platform_driver_register(&ar71xx_pci_driver);
429}
430
431postcore_initcall(ar71xx_pci_init);
diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c
index 279585d6eca0..8a0700d448fe 100644
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -9,19 +9,13 @@
9 * by the Free Software Foundation. 9 * by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/spinlock.h>
12#include <linux/irq.h> 13#include <linux/irq.h>
13#include <linux/pci.h> 14#include <linux/pci.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
14#include <asm/mach-ath79/ath79.h> 17#include <asm/mach-ath79/ath79.h>
15#include <asm/mach-ath79/ar71xx_regs.h> 18#include <asm/mach-ath79/ar71xx_regs.h>
16#include <asm/mach-ath79/pci.h>
17
18#define AR724X_PCI_CFG_BASE 0x14000000
19#define AR724X_PCI_CFG_SIZE 0x1000
20#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
21#define AR724X_PCI_CTRL_SIZE 0x100
22
23#define AR724X_PCI_MEM_BASE 0x10000000
24#define AR724X_PCI_MEM_SIZE 0x04000000
25 19
26#define AR724X_PCI_REG_RESET 0x18 20#define AR724X_PCI_REG_RESET 0x18
27#define AR724X_PCI_REG_INT_STATUS 0x4c 21#define AR724X_PCI_REG_INT_STATUS 0x4c
@@ -35,38 +29,112 @@
35 29
36#define AR7240_BAR0_WAR_VALUE 0xffff 30#define AR7240_BAR0_WAR_VALUE 0xffff
37 31
38static DEFINE_SPINLOCK(ar724x_pci_lock); 32#define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \
39static void __iomem *ar724x_pci_devcfg_base; 33 PCI_COMMAND_MASTER | \
40static void __iomem *ar724x_pci_ctrl_base; 34 PCI_COMMAND_INVALIDATE | \
35 PCI_COMMAND_PARITY | \
36 PCI_COMMAND_SERR | \
37 PCI_COMMAND_FAST_BACK)
38
39struct ar724x_pci_controller {
40 void __iomem *devcfg_base;
41 void __iomem *ctrl_base;
42 void __iomem *crp_base;
43
44 int irq;
45 int irq_base;
46
47 bool link_up;
48 bool bar0_is_cached;
49 u32 bar0_value;
41 50
42static u32 ar724x_pci_bar0_value; 51 spinlock_t lock;
43static bool ar724x_pci_bar0_is_cached;
44static bool ar724x_pci_link_up;
45 52
46static inline bool ar724x_pci_check_link(void) 53 struct pci_controller pci_controller;
54 struct resource io_res;
55 struct resource mem_res;
56};
57
58static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)
47{ 59{
48 u32 reset; 60 u32 reset;
49 61
50 reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET); 62 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET);
51 return reset & AR724X_PCI_RESET_LINK_UP; 63 return reset & AR724X_PCI_RESET_LINK_UP;
52} 64}
53 65
66static inline struct ar724x_pci_controller *
67pci_bus_to_ar724x_controller(struct pci_bus *bus)
68{
69 struct pci_controller *hose;
70
71 hose = (struct pci_controller *) bus->sysdata;
72 return container_of(hose, struct ar724x_pci_controller, pci_controller);
73}
74
75static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
76 int where, int size, u32 value)
77{
78 unsigned long flags;
79 void __iomem *base;
80 u32 data;
81 int s;
82
83 WARN_ON(where & (size - 1));
84
85 if (!apc->link_up)
86 return PCIBIOS_DEVICE_NOT_FOUND;
87
88 base = apc->crp_base;
89
90 spin_lock_irqsave(&apc->lock, flags);
91 data = __raw_readl(base + (where & ~3));
92
93 switch (size) {
94 case 1:
95 s = ((where & 3) * 8);
96 data &= ~(0xff << s);
97 data |= ((value & 0xff) << s);
98 break;
99 case 2:
100 s = ((where & 2) * 8);
101 data &= ~(0xffff << s);
102 data |= ((value & 0xffff) << s);
103 break;
104 case 4:
105 data = value;
106 break;
107 default:
108 spin_unlock_irqrestore(&apc->lock, flags);
109 return PCIBIOS_BAD_REGISTER_NUMBER;
110 }
111
112 __raw_writel(data, base + (where & ~3));
113 /* flush write */
114 __raw_readl(base + (where & ~3));
115 spin_unlock_irqrestore(&apc->lock, flags);
116
117 return PCIBIOS_SUCCESSFUL;
118}
119
54static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, 120static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
55 int size, uint32_t *value) 121 int size, uint32_t *value)
56{ 122{
123 struct ar724x_pci_controller *apc;
57 unsigned long flags; 124 unsigned long flags;
58 void __iomem *base; 125 void __iomem *base;
59 u32 data; 126 u32 data;
60 127
61 if (!ar724x_pci_link_up) 128 apc = pci_bus_to_ar724x_controller(bus);
129 if (!apc->link_up)
62 return PCIBIOS_DEVICE_NOT_FOUND; 130 return PCIBIOS_DEVICE_NOT_FOUND;
63 131
64 if (devfn) 132 if (devfn)
65 return PCIBIOS_DEVICE_NOT_FOUND; 133 return PCIBIOS_DEVICE_NOT_FOUND;
66 134
67 base = ar724x_pci_devcfg_base; 135 base = apc->devcfg_base;
68 136
69 spin_lock_irqsave(&ar724x_pci_lock, flags); 137 spin_lock_irqsave(&apc->lock, flags);
70 data = __raw_readl(base + (where & ~3)); 138 data = __raw_readl(base + (where & ~3));
71 139
72 switch (size) { 140 switch (size) {
@@ -85,17 +153,17 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
85 case 4: 153 case 4:
86 break; 154 break;
87 default: 155 default:
88 spin_unlock_irqrestore(&ar724x_pci_lock, flags); 156 spin_unlock_irqrestore(&apc->lock, flags);
89 157
90 return PCIBIOS_BAD_REGISTER_NUMBER; 158 return PCIBIOS_BAD_REGISTER_NUMBER;
91 } 159 }
92 160
93 spin_unlock_irqrestore(&ar724x_pci_lock, flags); 161 spin_unlock_irqrestore(&apc->lock, flags);
94 162
95 if (where == PCI_BASE_ADDRESS_0 && size == 4 && 163 if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
96 ar724x_pci_bar0_is_cached) { 164 apc->bar0_is_cached) {
97 /* use the cached value */ 165 /* use the cached value */
98 *value = ar724x_pci_bar0_value; 166 *value = apc->bar0_value;
99 } else { 167 } else {
100 *value = data; 168 *value = data;
101 } 169 }
@@ -106,12 +174,14 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
106static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, 174static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
107 int size, uint32_t value) 175 int size, uint32_t value)
108{ 176{
177 struct ar724x_pci_controller *apc;
109 unsigned long flags; 178 unsigned long flags;
110 void __iomem *base; 179 void __iomem *base;
111 u32 data; 180 u32 data;
112 int s; 181 int s;
113 182
114 if (!ar724x_pci_link_up) 183 apc = pci_bus_to_ar724x_controller(bus);
184 if (!apc->link_up)
115 return PCIBIOS_DEVICE_NOT_FOUND; 185 return PCIBIOS_DEVICE_NOT_FOUND;
116 186
117 if (devfn) 187 if (devfn)
@@ -129,18 +199,18 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
129 * BAR0 register in order to make the device memory 199 * BAR0 register in order to make the device memory
130 * accessible. 200 * accessible.
131 */ 201 */
132 ar724x_pci_bar0_is_cached = true; 202 apc->bar0_is_cached = true;
133 ar724x_pci_bar0_value = value; 203 apc->bar0_value = value;
134 204
135 value = AR7240_BAR0_WAR_VALUE; 205 value = AR7240_BAR0_WAR_VALUE;
136 } else { 206 } else {
137 ar724x_pci_bar0_is_cached = false; 207 apc->bar0_is_cached = false;
138 } 208 }
139 } 209 }
140 210
141 base = ar724x_pci_devcfg_base; 211 base = apc->devcfg_base;
142 212
143 spin_lock_irqsave(&ar724x_pci_lock, flags); 213 spin_lock_irqsave(&apc->lock, flags);
144 data = __raw_readl(base + (where & ~3)); 214 data = __raw_readl(base + (where & ~3));
145 215
146 switch (size) { 216 switch (size) {
@@ -158,7 +228,7 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
158 data = value; 228 data = value;
159 break; 229 break;
160 default: 230 default:
161 spin_unlock_irqrestore(&ar724x_pci_lock, flags); 231 spin_unlock_irqrestore(&apc->lock, flags);
162 232
163 return PCIBIOS_BAD_REGISTER_NUMBER; 233 return PCIBIOS_BAD_REGISTER_NUMBER;
164 } 234 }
@@ -166,7 +236,7 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
166 __raw_writel(data, base + (where & ~3)); 236 __raw_writel(data, base + (where & ~3));
167 /* flush write */ 237 /* flush write */
168 __raw_readl(base + (where & ~3)); 238 __raw_readl(base + (where & ~3));
169 spin_unlock_irqrestore(&ar724x_pci_lock, flags); 239 spin_unlock_irqrestore(&apc->lock, flags);
170 240
171 return PCIBIOS_SUCCESSFUL; 241 return PCIBIOS_SUCCESSFUL;
172} 242}
@@ -176,38 +246,20 @@ static struct pci_ops ar724x_pci_ops = {
176 .write = ar724x_pci_write, 246 .write = ar724x_pci_write,
177}; 247};
178 248
179static struct resource ar724x_io_resource = {
180 .name = "PCI IO space",
181 .start = 0,
182 .end = 0,
183 .flags = IORESOURCE_IO,
184};
185
186static struct resource ar724x_mem_resource = {
187 .name = "PCI memory space",
188 .start = AR724X_PCI_MEM_BASE,
189 .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
190 .flags = IORESOURCE_MEM,
191};
192
193static struct pci_controller ar724x_pci_controller = {
194 .pci_ops = &ar724x_pci_ops,
195 .io_resource = &ar724x_io_resource,
196 .mem_resource = &ar724x_mem_resource,
197};
198
199static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) 249static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
200{ 250{
251 struct ar724x_pci_controller *apc;
201 void __iomem *base; 252 void __iomem *base;
202 u32 pending; 253 u32 pending;
203 254
204 base = ar724x_pci_ctrl_base; 255 apc = irq_get_handler_data(irq);
256 base = apc->ctrl_base;
205 257
206 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & 258 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
207 __raw_readl(base + AR724X_PCI_REG_INT_MASK); 259 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
208 260
209 if (pending & AR724X_PCI_INT_DEV0) 261 if (pending & AR724X_PCI_INT_DEV0)
210 generic_handle_irq(ATH79_PCI_IRQ(0)); 262 generic_handle_irq(apc->irq_base + 0);
211 263
212 else 264 else
213 spurious_interrupt(); 265 spurious_interrupt();
@@ -215,13 +267,17 @@ static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
215 267
216static void ar724x_pci_irq_unmask(struct irq_data *d) 268static void ar724x_pci_irq_unmask(struct irq_data *d)
217{ 269{
270 struct ar724x_pci_controller *apc;
218 void __iomem *base; 271 void __iomem *base;
272 int offset;
219 u32 t; 273 u32 t;
220 274
221 base = ar724x_pci_ctrl_base; 275 apc = irq_data_get_irq_chip_data(d);
276 base = apc->ctrl_base;
277 offset = apc->irq_base - d->irq;
222 278
223 switch (d->irq) { 279 switch (offset) {
224 case ATH79_PCI_IRQ(0): 280 case 0:
225 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); 281 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
226 __raw_writel(t | AR724X_PCI_INT_DEV0, 282 __raw_writel(t | AR724X_PCI_INT_DEV0,
227 base + AR724X_PCI_REG_INT_MASK); 283 base + AR724X_PCI_REG_INT_MASK);
@@ -232,13 +288,17 @@ static void ar724x_pci_irq_unmask(struct irq_data *d)
232 288
233static void ar724x_pci_irq_mask(struct irq_data *d) 289static void ar724x_pci_irq_mask(struct irq_data *d)
234{ 290{
291 struct ar724x_pci_controller *apc;
235 void __iomem *base; 292 void __iomem *base;
293 int offset;
236 u32 t; 294 u32 t;
237 295
238 base = ar724x_pci_ctrl_base; 296 apc = irq_data_get_irq_chip_data(d);
297 base = apc->ctrl_base;
298 offset = apc->irq_base - d->irq;
239 299
240 switch (d->irq) { 300 switch (offset) {
241 case ATH79_PCI_IRQ(0): 301 case 0:
242 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); 302 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
243 __raw_writel(t & ~AR724X_PCI_INT_DEV0, 303 __raw_writel(t & ~AR724X_PCI_INT_DEV0,
244 base + AR724X_PCI_REG_INT_MASK); 304 base + AR724X_PCI_REG_INT_MASK);
@@ -262,53 +322,123 @@ static struct irq_chip ar724x_pci_irq_chip = {
262 .irq_mask_ack = ar724x_pci_irq_mask, 322 .irq_mask_ack = ar724x_pci_irq_mask,
263}; 323};
264 324
265static void __init ar724x_pci_irq_init(int irq) 325static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,
326 int id)
266{ 327{
267 void __iomem *base; 328 void __iomem *base;
268 int i; 329 int i;
269 330
270 base = ar724x_pci_ctrl_base; 331 base = apc->ctrl_base;
271 332
272 __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); 333 __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
273 __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); 334 __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
274 335
275 BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT); 336 apc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);
276 337
277 for (i = ATH79_PCI_IRQ_BASE; 338 for (i = apc->irq_base;
278 i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++) 339 i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {
279 irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, 340 irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
280 handle_level_irq); 341 handle_level_irq);
342 irq_set_chip_data(i, apc);
343 }
281 344
282 irq_set_chained_handler(irq, ar724x_pci_irq_handler); 345 irq_set_handler_data(apc->irq, apc);
346 irq_set_chained_handler(apc->irq, ar724x_pci_irq_handler);
283} 347}
284 348
285int __init ar724x_pcibios_init(int irq) 349static int ar724x_pci_probe(struct platform_device *pdev)
286{ 350{
287 int ret; 351 struct ar724x_pci_controller *apc;
352 struct resource *res;
353 int id;
288 354
289 ret = -ENOMEM; 355 id = pdev->id;
356 if (id == -1)
357 id = 0;
290 358
291 ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE, 359 apc = devm_kzalloc(&pdev->dev, sizeof(struct ar724x_pci_controller),
292 AR724X_PCI_CFG_SIZE); 360 GFP_KERNEL);
293 if (ar724x_pci_devcfg_base == NULL) 361 if (!apc)
294 goto err; 362 return -ENOMEM;
295 363
296 ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE, 364 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl_base");
297 AR724X_PCI_CTRL_SIZE); 365 if (!res)
298 if (ar724x_pci_ctrl_base == NULL) 366 return -EINVAL;
299 goto err_unmap_devcfg;
300 367
301 ar724x_pci_link_up = ar724x_pci_check_link(); 368 apc->ctrl_base = devm_request_and_ioremap(&pdev->dev, res);
302 if (!ar724x_pci_link_up) 369 if (apc->ctrl_base == NULL)
303 pr_warn("ar724x: PCIe link is down\n"); 370 return -EBUSY;
304 371
305 ar724x_pci_irq_init(irq); 372 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
306 register_pci_controller(&ar724x_pci_controller); 373 if (!res)
374 return -EINVAL;
307 375
308 return PCIBIOS_SUCCESSFUL; 376 apc->devcfg_base = devm_request_and_ioremap(&pdev->dev, res);
377 if (!apc->devcfg_base)
378 return -EBUSY;
379
380 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
381 if (!res)
382 return -EINVAL;
309 383
310err_unmap_devcfg: 384 apc->crp_base = devm_request_and_ioremap(&pdev->dev, res);
311 iounmap(ar724x_pci_devcfg_base); 385 if (apc->crp_base == NULL)
312err: 386 return -EBUSY;
313 return ret; 387
388 apc->irq = platform_get_irq(pdev, 0);
389 if (apc->irq < 0)
390 return -EINVAL;
391
392 spin_lock_init(&apc->lock);
393
394 res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
395 if (!res)
396 return -EINVAL;
397
398 apc->io_res.parent = res;
399 apc->io_res.name = "PCI IO space";
400 apc->io_res.start = res->start;
401 apc->io_res.end = res->end;
402 apc->io_res.flags = IORESOURCE_IO;
403
404 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
405 if (!res)
406 return -EINVAL;
407
408 apc->mem_res.parent = res;
409 apc->mem_res.name = "PCI memory space";
410 apc->mem_res.start = res->start;
411 apc->mem_res.end = res->end;
412 apc->mem_res.flags = IORESOURCE_MEM;
413
414 apc->pci_controller.pci_ops = &ar724x_pci_ops;
415 apc->pci_controller.io_resource = &apc->io_res;
416 apc->pci_controller.mem_resource = &apc->mem_res;
417
418 apc->link_up = ar724x_pci_check_link(apc);
419 if (!apc->link_up)
420 dev_warn(&pdev->dev, "PCIe link is down\n");
421
422 ar724x_pci_irq_init(apc, id);
423
424 ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
425
426 register_pci_controller(&apc->pci_controller);
427
428 return 0;
314} 429}
430
431static struct platform_driver ar724x_pci_driver = {
432 .probe = ar724x_pci_probe,
433 .driver = {
434 .name = "ar724x-pci",
435 .owner = THIS_MODULE,
436 },
437};
438
439static int __init ar724x_pci_init(void)
440{
441 return platform_driver_register(&ar724x_pci_driver);
442}
443
444postcore_initcall(ar724x_pci_init);
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 95681789b51e..f32664bbbe17 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -129,8 +129,16 @@ static int ltq_pci_startup(struct platform_device *pdev)
129 129
130 /* setup reset gpio used by pci */ 130 /* setup reset gpio used by pci */
131 reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); 131 reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
132 if (gpio_is_valid(reset_gpio)) 132 if (gpio_is_valid(reset_gpio)) {
133 devm_gpio_request(&pdev->dev, reset_gpio, "pci-reset"); 133 int ret = devm_gpio_request(&pdev->dev,
134 reset_gpio, "pci-reset");
135 if (ret) {
136 dev_err(&pdev->dev,
137 "failed to request gpio %d\n", reset_gpio);
138 return ret;
139 }
140 gpio_direction_output(reset_gpio, 1);
141 }
134 142
135 /* enable auto-switching between PCI and EBU */ 143 /* enable auto-switching between PCI and EBU */
136 ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); 144 ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c
index ad55f2cfeec1..653d2db9e0c5 100644
--- a/arch/mips/pci/pci-xlp.c
+++ b/arch/mips/pci/pci-xlp.c
@@ -46,6 +46,7 @@
46 46
47#include <asm/netlogic/interrupt.h> 47#include <asm/netlogic/interrupt.h>
48#include <asm/netlogic/haldefs.h> 48#include <asm/netlogic/haldefs.h>
49#include <asm/netlogic/common.h>
49 50
50#include <asm/netlogic/xlp-hal/iomap.h> 51#include <asm/netlogic/xlp-hal/iomap.h>
51#include <asm/netlogic/xlp-hal/pic.h> 52#include <asm/netlogic/xlp-hal/pic.h>
@@ -64,8 +65,12 @@ static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
64 u32 data; 65 u32 data;
65 u32 *cfgaddr; 66 u32 *cfgaddr;
66 67
68 where &= ~3;
69 if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954)
70 return 0xffffffff;
71
67 cfgaddr = (u32 *)(pci_config_base + 72 cfgaddr = (u32 *)(pci_config_base +
68 pci_cfg_addr(bus->number, devfn, where & ~3)); 73 pci_cfg_addr(bus->number, devfn, where));
69 data = *cfgaddr; 74 data = *cfgaddr;
70 return data; 75 return data;
71} 76}
@@ -157,32 +162,38 @@ struct pci_controller nlm_pci_controller = {
157 .io_offset = 0x00000000UL, 162 .io_offset = 0x00000000UL,
158}; 163};
159 164
160static int get_irq_vector(const struct pci_dev *dev) 165static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev)
161{ 166{
162 /* 167 struct pci_bus *bus, *p;
163 * For XLP PCIe, there is an IRQ per Link, find out which
164 * link the device is on to assign interrupts
165 */
166 if (dev->bus->self == NULL)
167 return 0;
168 168
169 switch (dev->bus->self->devfn) { 169 /* Find the bridge on bus 0 */
170 case 0x8: 170 bus = dev->bus;
171 return PIC_PCIE_LINK_0_IRQ; 171 for (p = bus->parent; p && p->number != 0; p = p->parent)
172 case 0x9: 172 bus = p;
173 return PIC_PCIE_LINK_1_IRQ; 173
174 case 0xa: 174 return p ? bus->self : NULL;
175 return PIC_PCIE_LINK_2_IRQ; 175}
176 case 0xb: 176
177 return PIC_PCIE_LINK_3_IRQ; 177static inline int nlm_pci_link_to_irq(int link)
178 } 178{
179 WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); 179 return PIC_PCIE_LINK_0_IRQ + link;
180 return 0;
181} 180}
182 181
183int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 182int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
184{ 183{
185 return get_irq_vector(dev); 184 struct pci_dev *lnkdev;
185 int lnkslot, lnkfunc;
186
187 /*
188 * For XLP PCIe, there is an IRQ per Link, find out which
189 * link the device is on to assign interrupts
190 */
191 lnkdev = xlp_get_pcie_link(dev);
192 if (lnkdev == NULL)
193 return 0;
194 lnkfunc = PCI_FUNC(lnkdev->devfn);
195 lnkslot = PCI_SLOT(lnkdev->devfn);
196 return nlm_irq_to_xirq(lnkslot / 8, nlm_pci_link_to_irq(lnkfunc));
186} 197}
187 198
188/* Do platform specific device initialization at pci_enable_device() time */ 199/* Do platform specific device initialization at pci_enable_device() time */
@@ -191,42 +202,48 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
191 return 0; 202 return 0;
192} 203}
193 204
194static int xlp_enable_pci_bswap(void) 205/*
206 * If big-endian, enable hardware byteswap on the PCIe bridges.
207 * This will make both the SoC and PCIe devices behave consistently with
208 * readl/writel.
209 */
210#ifdef __BIG_ENDIAN
211static void xlp_config_pci_bswap(int node, int link)
195{ 212{
196 uint64_t pciebase, sysbase; 213 uint64_t nbubase, lnkbase;
197 int node, i;
198 u32 reg; 214 u32 reg;
199 215
200 /* Chip-0 so node set to 0 */ 216 nbubase = nlm_get_bridge_regbase(node);
201 node = 0; 217 lnkbase = nlm_get_pcie_base(node, link);
202 sysbase = nlm_get_bridge_regbase(node); 218
203 /* 219 /*
204 * Enable byte swap in hardware. Program each link's PCIe SWAP regions 220 * Enable byte swap in hardware. Program each link's PCIe SWAP regions
205 * from the link's address ranges. 221 * from the link's address ranges.
206 */ 222 */
207 for (i = 0; i < 4; i++) { 223 reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link);
208 pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i)); 224 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg);
209 if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
210 continue;
211 225
212 reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i); 226 reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link);
213 nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg); 227 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff);
214 228
215 reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i); 229 reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link);
216 nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM, 230 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg);
217 reg | 0xfff);
218 231
219 reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i); 232 reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link);
220 nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg); 233 nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
221
222 reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
223 nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
224 }
225 return 0;
226} 234}
235#else
236/* Swap configuration not needed in little-endian mode */
237static inline void xlp_config_pci_bswap(int node, int link) {}
238#endif /* __BIG_ENDIAN */
227 239
228static int __init pcibios_init(void) 240static int __init pcibios_init(void)
229{ 241{
242 struct nlm_soc_info *nodep;
243 uint64_t pciebase;
244 int link, n;
245 u32 reg;
246
230 /* Firmware assigns PCI resources */ 247 /* Firmware assigns PCI resources */
231 pci_set_flags(PCI_PROBE_ONLY); 248 pci_set_flags(PCI_PROBE_ONLY);
232 pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); 249 pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
@@ -235,7 +252,26 @@ static int __init pcibios_init(void)
235 ioport_resource.start = 0; 252 ioport_resource.start = 0;
236 ioport_resource.end = ~0; 253 ioport_resource.end = ~0;
237 254
238 xlp_enable_pci_bswap(); 255 for (n = 0; n < NLM_NR_NODES; n++) {
256 nodep = nlm_get_node(n);
257 if (!nodep->coremask)
258 continue; /* node does not exist */
259
260 for (link = 0; link < 4; link++) {
261 pciebase = nlm_get_pcie_base(n, link);
262 if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
263 continue;
264 xlp_config_pci_bswap(n, link);
265
266 /* put in intpin and irq - u-boot does not */
267 reg = nlm_read_pci_reg(pciebase, 0xf);
268 reg &= ~0x1fu;
269 reg |= (1 << 8) | nlm_pci_link_to_irq(link);
270 nlm_write_pci_reg(pciebase, 0xf, reg);
271 pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link);
272 }
273 }
274
239 set_io_port_base(CKSEG1); 275 set_io_port_base(CKSEG1);
240 nlm_pci_controller.io_map_base = CKSEG1; 276 nlm_pci_controller.io_map_base = CKSEG1;
241 277
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index e8a14a6514cf..0872f12f268d 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -175,9 +175,20 @@ static DEFINE_MUTEX(pci_scan_mutex);
175 175
176void register_pci_controller(struct pci_controller *hose) 176void register_pci_controller(struct pci_controller *hose)
177{ 177{
178 if (request_resource(&iomem_resource, hose->mem_resource) < 0) 178 struct resource *parent;
179
180 parent = hose->mem_resource->parent;
181 if (!parent)
182 parent = &iomem_resource;
183
184 if (request_resource(parent, hose->mem_resource) < 0)
179 goto out; 185 goto out;
180 if (request_resource(&ioport_resource, hose->io_resource) < 0) { 186
187 parent = hose->io_resource->parent;
188 if (!parent)
189 parent = &ioport_resource;
190
191 if (request_resource(parent, hose->io_resource) < 0) {
181 release_resource(hose->mem_resource); 192 release_resource(hose->mem_resource);
182 goto out; 193 goto out;
183 } 194 }
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
new file mode 100644
index 000000000000..a0b0197cab0a
--- /dev/null
+++ b/arch/mips/ralink/Kconfig
@@ -0,0 +1,32 @@
1if RALINK
2
3choice
4 prompt "Ralink SoC selection"
5 default SOC_RT305X
6 help
7 Select Ralink MIPS SoC type.
8
9 config SOC_RT305X
10 bool "RT305x"
11 select USB_ARCH_HAS_HCD
12 select USB_ARCH_HAS_OHCI
13 select USB_ARCH_HAS_EHCI
14
15endchoice
16
17choice
18 prompt "Devicetree selection"
19 default DTB_RT_NONE
20 help
21 Select the devicetree.
22
23 config DTB_RT_NONE
24 bool "None"
25
26 config DTB_RT305X_EVAL
27 bool "RT305x eval kit"
28 depends on SOC_RT305X
29
30endchoice
31
32endif
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
new file mode 100644
index 000000000000..939757f0e71f
--- /dev/null
+++ b/arch/mips/ralink/Makefile
@@ -0,0 +1,15 @@
1# This program is free software; you can redistribute it and/or modify it
2# under the terms of the GNU General Public License version 2 as published
3# by the Free Software Foundation.#
4# Makefile for the Ralink common stuff
5#
6# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
7# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
8
9obj-y := prom.o of.o reset.o clk.o irq.o
10
11obj-$(CONFIG_SOC_RT305X) += rt305x.o
12
13obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
14
15obj-y += dts/
diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
new file mode 100644
index 000000000000..6babd65765e6
--- /dev/null
+++ b/arch/mips/ralink/Platform
@@ -0,0 +1,10 @@
1#
2# Ralink SoC common stuff
3#
4core-$(CONFIG_RALINK) += arch/mips/ralink/
5cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
6
7#
8# Ralink RT305x
9#
10load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
new file mode 100644
index 000000000000..8dfa22ff300b
--- /dev/null
+++ b/arch/mips/ralink/clk.c
@@ -0,0 +1,72 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/clkdev.h>
13#include <linux/clk.h>
14
15#include <asm/time.h>
16
17#include "common.h"
18
19struct clk {
20 struct clk_lookup cl;
21 unsigned long rate;
22};
23
24void ralink_clk_add(const char *dev, unsigned long rate)
25{
26 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
27
28 if (!clk)
29 panic("failed to add clock\n");
30
31 clk->cl.dev_id = dev;
32 clk->cl.clk = clk;
33
34 clk->rate = rate;
35
36 clkdev_add(&clk->cl);
37}
38
39/*
40 * Linux clock API
41 */
42int clk_enable(struct clk *clk)
43{
44 return 0;
45}
46EXPORT_SYMBOL_GPL(clk_enable);
47
48void clk_disable(struct clk *clk)
49{
50}
51EXPORT_SYMBOL_GPL(clk_disable);
52
53unsigned long clk_get_rate(struct clk *clk)
54{
55 return clk->rate;
56}
57EXPORT_SYMBOL_GPL(clk_get_rate);
58
59void __init plat_time_init(void)
60{
61 struct clk *clk;
62
63 ralink_of_remap();
64
65 ralink_clk_init();
66 clk = clk_get_sys("cpu", NULL);
67 if (IS_ERR(clk))
68 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
69 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
70 mips_hpt_frequency = clk_get_rate(clk) / 2;
71 clk_put(clk);
72}
diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
new file mode 100644
index 000000000000..300990313e1b
--- /dev/null
+++ b/arch/mips/ralink/common.h
@@ -0,0 +1,44 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _RALINK_COMMON_H__
10#define _RALINK_COMMON_H__
11
12#define RAMIPS_SYS_TYPE_LEN 32
13
14struct ralink_pinmux_grp {
15 const char *name;
16 u32 mask;
17 int gpio_first;
18 int gpio_last;
19};
20
21struct ralink_pinmux {
22 struct ralink_pinmux_grp *mode;
23 struct ralink_pinmux_grp *uart;
24 int uart_shift;
25 void (*wdt_reset)(void);
26};
27extern struct ralink_pinmux gpio_pinmux;
28
29struct ralink_soc_info {
30 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
31 unsigned char *compatible;
32};
33extern struct ralink_soc_info soc_info;
34
35extern void ralink_of_remap(void);
36
37extern void ralink_clk_init(void);
38extern void ralink_clk_add(const char *dev, unsigned long rate);
39
40extern void prom_soc_init(struct ralink_soc_info *soc_info);
41
42__iomem void *plat_of_remap_node(const char *node);
43
44#endif /* _RALINK_COMMON_H__ */
diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile
new file mode 100644
index 000000000000..1a69fb300955
--- /dev/null
+++ b/arch/mips/ralink/dts/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
diff --git a/arch/mips/ralink/dts/rt3050.dtsi b/arch/mips/ralink/dts/rt3050.dtsi
new file mode 100644
index 000000000000..069d0660e1dd
--- /dev/null
+++ b/arch/mips/ralink/dts/rt3050.dtsi
@@ -0,0 +1,106 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
5
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips24KEc";
9 };
10 };
11
12 chosen {
13 bootargs = "console=ttyS0,57600 init=/init";
14 };
15
16 cpuintc: cpuintc@0 {
17 #address-cells = <0>;
18 #interrupt-cells = <1>;
19 interrupt-controller;
20 compatible = "mti,cpu-interrupt-controller";
21 };
22
23 palmbus@10000000 {
24 compatible = "palmbus";
25 reg = <0x10000000 0x200000>;
26 ranges = <0x0 0x10000000 0x1FFFFF>;
27
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 sysc@0 {
32 compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc";
33 reg = <0x0 0x100>;
34 };
35
36 timer@100 {
37 compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
38 reg = <0x100 0x100>;
39 };
40
41 intc: intc@200 {
42 compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
43 reg = <0x200 0x100>;
44
45 interrupt-controller;
46 #interrupt-cells = <1>;
47
48 interrupt-parent = <&cpuintc>;
49 interrupts = <2>;
50 };
51
52 memc@300 {
53 compatible = "ralink,rt3052-memc", "ralink,rt3050-memc";
54 reg = <0x300 0x100>;
55 };
56
57 gpio0: gpio@600 {
58 compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
59 reg = <0x600 0x34>;
60
61 gpio-controller;
62 #gpio-cells = <2>;
63
64 ralink,ngpio = <24>;
65 ralink,regs = [ 00 04 08 0c
66 20 24 28 2c
67 30 34 ];
68 };
69
70 gpio1: gpio@638 {
71 compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
72 reg = <0x638 0x24>;
73
74 gpio-controller;
75 #gpio-cells = <2>;
76
77 ralink,ngpio = <16>;
78 ralink,regs = [ 00 04 08 0c
79 10 14 18 1c
80 20 24 ];
81 };
82
83 gpio2: gpio@660 {
84 compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
85 reg = <0x660 0x24>;
86
87 gpio-controller;
88 #gpio-cells = <2>;
89
90 ralink,ngpio = <12>;
91 ralink,regs = [ 00 04 08 0c
92 10 14 18 1c
93 20 24 ];
94 };
95
96 uartlite@c00 {
97 compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
98 reg = <0xc00 0x100>;
99
100 interrupt-parent = <&intc>;
101 interrupts = <12>;
102
103 reg-shift = <2>;
104 };
105 };
106};
diff --git a/arch/mips/ralink/dts/rt3052_eval.dts b/arch/mips/ralink/dts/rt3052_eval.dts
new file mode 100644
index 000000000000..148a590bc419
--- /dev/null
+++ b/arch/mips/ralink/dts/rt3052_eval.dts
@@ -0,0 +1,52 @@
1/dts-v1/;
2
3/include/ "rt3050.dtsi"
4
5/ {
6 #address-cells = <1>;
7 #size-cells = <1>;
8 compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc";
9 model = "Ralink RT3052 evaluation board";
10
11 memory@0 {
12 reg = <0x0 0x2000000>;
13 };
14
15 palmbus@10000000 {
16 sysc@0 {
17 ralink,pinmmux = "uartlite", "spi";
18 ralink,uartmux = "gpio";
19 ralink,wdtmux = <0>;
20 };
21 };
22
23 cfi@1f000000 {
24 compatible = "cfi-flash";
25 reg = <0x1f000000 0x800000>;
26
27 bank-width = <2>;
28 device-width = <2>;
29 #address-cells = <1>;
30 #size-cells = <1>;
31
32 partition@0 {
33 label = "uboot";
34 reg = <0x0 0x30000>;
35 read-only;
36 };
37 partition@30000 {
38 label = "uboot-env";
39 reg = <0x30000 0x10000>;
40 read-only;
41 };
42 partition@40000 {
43 label = "calibration";
44 reg = <0x40000 0x10000>;
45 read-only;
46 };
47 partition@50000 {
48 label = "linux";
49 reg = <0x50000 0x7b0000>;
50 };
51 };
52};
diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
new file mode 100644
index 000000000000..c4ae47eb24ab
--- /dev/null
+++ b/arch/mips/ralink/early_printk.c
@@ -0,0 +1,44 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 */
8
9#include <linux/io.h>
10#include <linux/serial_reg.h>
11
12#include <asm/addrspace.h>
13
14#define EARLY_UART_BASE 0x10000c00
15
16#define UART_REG_RX 0x00
17#define UART_REG_TX 0x04
18#define UART_REG_IER 0x08
19#define UART_REG_IIR 0x0c
20#define UART_REG_FCR 0x10
21#define UART_REG_LCR 0x14
22#define UART_REG_MCR 0x18
23#define UART_REG_LSR 0x1c
24
25static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
26
27static inline void uart_w32(u32 val, unsigned reg)
28{
29 __raw_writel(val, uart_membase + reg);
30}
31
32static inline u32 uart_r32(unsigned reg)
33{
34 return __raw_readl(uart_membase + reg);
35}
36
37void prom_putchar(unsigned char ch)
38{
39 while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
40 ;
41 uart_w32(ch, UART_REG_TX);
42 while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
43 ;
44}
diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
new file mode 100644
index 000000000000..6d054c5ec9ab
--- /dev/null
+++ b/arch/mips/ralink/irq.c
@@ -0,0 +1,180 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
8 */
9
10#include <linux/io.h>
11#include <linux/bitops.h>
12#include <linux/of_platform.h>
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
15#include <linux/irqdomain.h>
16#include <linux/interrupt.h>
17
18#include <asm/irq_cpu.h>
19#include <asm/mipsregs.h>
20
21#include "common.h"
22
23/* INTC register offsets */
24#define INTC_REG_STATUS0 0x00
25#define INTC_REG_STATUS1 0x04
26#define INTC_REG_TYPE 0x20
27#define INTC_REG_RAW_STATUS 0x30
28#define INTC_REG_ENABLE 0x34
29#define INTC_REG_DISABLE 0x38
30
31#define INTC_INT_GLOBAL BIT(31)
32
33#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
34#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
35#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
36#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
37
38/* we have a cascade of 8 irqs */
39#define RALINK_INTC_IRQ_BASE 8
40
41/* we have 32 SoC irqs */
42#define RALINK_INTC_IRQ_COUNT 32
43
44#define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
45
46static void __iomem *rt_intc_membase;
47
48static inline void rt_intc_w32(u32 val, unsigned reg)
49{
50 __raw_writel(val, rt_intc_membase + reg);
51}
52
53static inline u32 rt_intc_r32(unsigned reg)
54{
55 return __raw_readl(rt_intc_membase + reg);
56}
57
58static void ralink_intc_irq_unmask(struct irq_data *d)
59{
60 rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
61}
62
63static void ralink_intc_irq_mask(struct irq_data *d)
64{
65 rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
66}
67
68static struct irq_chip ralink_intc_irq_chip = {
69 .name = "INTC",
70 .irq_unmask = ralink_intc_irq_unmask,
71 .irq_mask = ralink_intc_irq_mask,
72 .irq_mask_ack = ralink_intc_irq_mask,
73};
74
75unsigned int __cpuinit get_c0_compare_int(void)
76{
77 return CP0_LEGACY_COMPARE_IRQ;
78}
79
80static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
81{
82 u32 pending = rt_intc_r32(INTC_REG_STATUS0);
83
84 if (pending) {
85 struct irq_domain *domain = irq_get_handler_data(irq);
86 generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
87 } else {
88 spurious_interrupt();
89 }
90}
91
92asmlinkage void plat_irq_dispatch(void)
93{
94 unsigned long pending;
95
96 pending = read_c0_status() & read_c0_cause() & ST0_IM;
97
98 if (pending & STATUSF_IP7)
99 do_IRQ(RALINK_CPU_IRQ_COUNTER);
100
101 else if (pending & STATUSF_IP5)
102 do_IRQ(RALINK_CPU_IRQ_FE);
103
104 else if (pending & STATUSF_IP6)
105 do_IRQ(RALINK_CPU_IRQ_WIFI);
106
107 else if (pending & STATUSF_IP2)
108 do_IRQ(RALINK_CPU_IRQ_INTC);
109
110 else
111 spurious_interrupt();
112}
113
114static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
115{
116 irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
117
118 return 0;
119}
120
121static const struct irq_domain_ops irq_domain_ops = {
122 .xlate = irq_domain_xlate_onecell,
123 .map = intc_map,
124};
125
126static int __init intc_of_init(struct device_node *node,
127 struct device_node *parent)
128{
129 struct resource res;
130 struct irq_domain *domain;
131 int irq;
132
133 irq = irq_of_parse_and_map(node, 0);
134 if (!irq)
135 panic("Failed to get INTC IRQ");
136
137 if (of_address_to_resource(node, 0, &res))
138 panic("Failed to get intc memory range");
139
140 if (request_mem_region(res.start, resource_size(&res),
141 res.name) < 0)
142 pr_err("Failed to request intc memory");
143
144 rt_intc_membase = ioremap_nocache(res.start,
145 resource_size(&res));
146 if (!rt_intc_membase)
147 panic("Failed to remap intc memory");
148
149 /* disable all interrupts */
150 rt_intc_w32(~0, INTC_REG_DISABLE);
151
152 /* route all INTC interrupts to MIPS HW0 interrupt */
153 rt_intc_w32(0, INTC_REG_TYPE);
154
155 domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
156 RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
157 if (!domain)
158 panic("Failed to add irqdomain");
159
160 rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
161
162 irq_set_chained_handler(irq, ralink_intc_irq_handler);
163 irq_set_handler_data(irq, domain);
164
165 cp0_perfcount_irq = irq_create_mapping(domain, 9);
166
167 return 0;
168}
169
170static struct of_device_id __initdata of_irq_ids[] = {
171 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
172 { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
173 {},
174};
175
176void __init arch_init_irq(void)
177{
178 of_irq_init(of_irq_ids);
179}
180
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
new file mode 100644
index 000000000000..4165e70775be
--- /dev/null
+++ b/arch/mips/ralink/of.c
@@ -0,0 +1,107 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
8 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
9 */
10
11#include <linux/io.h>
12#include <linux/clk.h>
13#include <linux/init.h>
14#include <linux/of_fdt.h>
15#include <linux/kernel.h>
16#include <linux/bootmem.h>
17#include <linux/of_platform.h>
18#include <linux/of_address.h>
19
20#include <asm/reboot.h>
21#include <asm/bootinfo.h>
22#include <asm/addrspace.h>
23
24#include "common.h"
25
26__iomem void *rt_sysc_membase;
27__iomem void *rt_memc_membase;
28
29extern struct boot_param_header __dtb_start;
30
31__iomem void *plat_of_remap_node(const char *node)
32{
33 struct resource res;
34 struct device_node *np;
35
36 np = of_find_compatible_node(NULL, NULL, node);
37 if (!np)
38 panic("Failed to find %s node", node);
39
40 if (of_address_to_resource(np, 0, &res))
41 panic("Failed to get resource for %s", node);
42
43 if ((request_mem_region(res.start,
44 resource_size(&res),
45 res.name) < 0))
46 panic("Failed to request resources for %s", node);
47
48 return ioremap_nocache(res.start, resource_size(&res));
49}
50
51void __init device_tree_init(void)
52{
53 unsigned long base, size;
54 void *fdt_copy;
55
56 if (!initial_boot_params)
57 return;
58
59 base = virt_to_phys((void *)initial_boot_params);
60 size = be32_to_cpu(initial_boot_params->totalsize);
61
62 /* Before we do anything, lets reserve the dt blob */
63 reserve_bootmem(base, size, BOOTMEM_DEFAULT);
64
65 /* The strings in the flattened tree are referenced directly by the
66 * device tree, so copy the flattened device tree from init memory
67 * to regular memory.
68 */
69 fdt_copy = alloc_bootmem(size);
70 memcpy(fdt_copy, initial_boot_params, size);
71 initial_boot_params = fdt_copy;
72
73 unflatten_device_tree();
74
75 /* free the space reserved for the dt blob */
76 free_bootmem(base, size);
77}
78
79void __init plat_mem_setup(void)
80{
81 set_io_port_base(KSEG1);
82
83 /*
84 * Load the builtin devicetree. This causes the chosen node to be
85 * parsed resulting in our memory appearing
86 */
87 __dt_setup_arch(&__dtb_start);
88}
89
90static int __init plat_of_setup(void)
91{
92 static struct of_device_id of_ids[3];
93 int len = sizeof(of_ids[0].compatible);
94
95 if (!of_have_populated_dt())
96 panic("device tree not present");
97
98 strncpy(of_ids[0].compatible, soc_info.compatible, len);
99 strncpy(of_ids[1].compatible, "palmbus", len);
100
101 if (of_platform_populate(NULL, of_ids, NULL, NULL))
102 panic("failed to populate DT\n");
103
104 return 0;
105}
106
107arch_initcall(plat_of_setup);
diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c
new file mode 100644
index 000000000000..9c64f029d047
--- /dev/null
+++ b/arch/mips/ralink/prom.c
@@ -0,0 +1,69 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2010 Joonas Lahtinen <joonas.lahtinen@gmail.com>
8 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
9 */
10
11#include <linux/string.h>
12#include <linux/of_fdt.h>
13#include <linux/of_platform.h>
14
15#include <asm/bootinfo.h>
16#include <asm/addrspace.h>
17
18#include "common.h"
19
20struct ralink_soc_info soc_info;
21
22const char *get_system_type(void)
23{
24 return soc_info.sys_type;
25}
26
27static __init void prom_init_cmdline(int argc, char **argv)
28{
29 int i;
30
31 pr_debug("prom: fw_arg0=%08x fw_arg1=%08x fw_arg2=%08x fw_arg3=%08x\n",
32 (unsigned int)fw_arg0, (unsigned int)fw_arg1,
33 (unsigned int)fw_arg2, (unsigned int)fw_arg3);
34
35 argc = fw_arg0;
36 argv = (char **) KSEG1ADDR(fw_arg1);
37
38 if (!argv) {
39 pr_debug("argv=%p is invalid, skipping\n",
40 argv);
41 return;
42 }
43
44 for (i = 0; i < argc; i++) {
45 char *p = (char *) KSEG1ADDR(argv[i]);
46
47 if (CPHYSADDR(p) && *p) {
48 pr_debug("argv[%d]: %s\n", i, p);
49 strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
50 strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
51 }
52 }
53}
54
55void __init prom_init(void)
56{
57 int argc;
58 char **argv;
59
60 prom_soc_init(&soc_info);
61
62 pr_info("SoC Type: %s\n", get_system_type());
63
64 prom_init_cmdline(argc, argv);
65}
66
67void __init prom_free_prom_memory(void)
68{
69}
diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
new file mode 100644
index 000000000000..22120e512e7e
--- /dev/null
+++ b/arch/mips/ralink/reset.c
@@ -0,0 +1,44 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
9 */
10
11#include <linux/pm.h>
12#include <linux/io.h>
13
14#include <asm/reboot.h>
15
16#include <asm/mach-ralink/ralink_regs.h>
17
18/* Reset Control */
19#define SYSC_REG_RESET_CTRL 0x034
20#define RSTCTL_RESET_SYSTEM BIT(0)
21
22static void ralink_restart(char *command)
23{
24 local_irq_disable();
25 rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
26 unreachable();
27}
28
29static void ralink_halt(void)
30{
31 local_irq_disable();
32 unreachable();
33}
34
35static int __init mips_reboot_setup(void)
36{
37 _machine_restart = ralink_restart;
38 _machine_halt = ralink_halt;
39 pm_power_off = ralink_halt;
40
41 return 0;
42}
43
44arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
new file mode 100644
index 000000000000..0a4bbdcf59d9
--- /dev/null
+++ b/arch/mips/ralink/rt305x.c
@@ -0,0 +1,242 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/module.h>
16
17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/rt305x.h>
20
21#include "common.h"
22
23enum rt305x_soc_type rt305x_soc;
24
25struct ralink_pinmux_grp mode_mux[] = {
26 {
27 .name = "i2c",
28 .mask = RT305X_GPIO_MODE_I2C,
29 .gpio_first = RT305X_GPIO_I2C_SD,
30 .gpio_last = RT305X_GPIO_I2C_SCLK,
31 }, {
32 .name = "spi",
33 .mask = RT305X_GPIO_MODE_SPI,
34 .gpio_first = RT305X_GPIO_SPI_EN,
35 .gpio_last = RT305X_GPIO_SPI_CLK,
36 }, {
37 .name = "uartlite",
38 .mask = RT305X_GPIO_MODE_UART1,
39 .gpio_first = RT305X_GPIO_UART1_TXD,
40 .gpio_last = RT305X_GPIO_UART1_RXD,
41 }, {
42 .name = "jtag",
43 .mask = RT305X_GPIO_MODE_JTAG,
44 .gpio_first = RT305X_GPIO_JTAG_TDO,
45 .gpio_last = RT305X_GPIO_JTAG_TDI,
46 }, {
47 .name = "mdio",
48 .mask = RT305X_GPIO_MODE_MDIO,
49 .gpio_first = RT305X_GPIO_MDIO_MDC,
50 .gpio_last = RT305X_GPIO_MDIO_MDIO,
51 }, {
52 .name = "sdram",
53 .mask = RT305X_GPIO_MODE_SDRAM,
54 .gpio_first = RT305X_GPIO_SDRAM_MD16,
55 .gpio_last = RT305X_GPIO_SDRAM_MD31,
56 }, {
57 .name = "rgmii",
58 .mask = RT305X_GPIO_MODE_RGMII,
59 .gpio_first = RT305X_GPIO_GE0_TXD0,
60 .gpio_last = RT305X_GPIO_GE0_RXCLK,
61 }, {0}
62};
63
64struct ralink_pinmux_grp uart_mux[] = {
65 {
66 .name = "uartf",
67 .mask = RT305X_GPIO_MODE_UARTF,
68 .gpio_first = RT305X_GPIO_7,
69 .gpio_last = RT305X_GPIO_14,
70 }, {
71 .name = "pcm uartf",
72 .mask = RT305X_GPIO_MODE_PCM_UARTF,
73 .gpio_first = RT305X_GPIO_7,
74 .gpio_last = RT305X_GPIO_14,
75 }, {
76 .name = "pcm i2s",
77 .mask = RT305X_GPIO_MODE_PCM_I2S,
78 .gpio_first = RT305X_GPIO_7,
79 .gpio_last = RT305X_GPIO_14,
80 }, {
81 .name = "i2s uartf",
82 .mask = RT305X_GPIO_MODE_I2S_UARTF,
83 .gpio_first = RT305X_GPIO_7,
84 .gpio_last = RT305X_GPIO_14,
85 }, {
86 .name = "pcm gpio",
87 .mask = RT305X_GPIO_MODE_PCM_GPIO,
88 .gpio_first = RT305X_GPIO_10,
89 .gpio_last = RT305X_GPIO_14,
90 }, {
91 .name = "gpio uartf",
92 .mask = RT305X_GPIO_MODE_GPIO_UARTF,
93 .gpio_first = RT305X_GPIO_7,
94 .gpio_last = RT305X_GPIO_14,
95 }, {
96 .name = "gpio i2s",
97 .mask = RT305X_GPIO_MODE_GPIO_I2S,
98 .gpio_first = RT305X_GPIO_7,
99 .gpio_last = RT305X_GPIO_14,
100 }, {
101 .name = "gpio",
102 .mask = RT305X_GPIO_MODE_GPIO,
103 }, {0}
104};
105
106void rt305x_wdt_reset(void)
107{
108 u32 t;
109
110 /* enable WDT reset output on pin SRAM_CS_N */
111 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
112 t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT <<
113 RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT;
114 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
115}
116
117struct ralink_pinmux gpio_pinmux = {
118 .mode = mode_mux,
119 .uart = uart_mux,
120 .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
121 .wdt_reset = rt305x_wdt_reset,
122};
123
124void __init ralink_clk_init(void)
125{
126 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
127 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
128
129 if (soc_is_rt305x() || soc_is_rt3350()) {
130 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
131 RT305X_SYSCFG_CPUCLK_MASK;
132 switch (t) {
133 case RT305X_SYSCFG_CPUCLK_LOW:
134 cpu_rate = 320000000;
135 break;
136 case RT305X_SYSCFG_CPUCLK_HIGH:
137 cpu_rate = 384000000;
138 break;
139 }
140 sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
141 } else if (soc_is_rt3352()) {
142 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
143 RT3352_SYSCFG0_CPUCLK_MASK;
144 switch (t) {
145 case RT3352_SYSCFG0_CPUCLK_LOW:
146 cpu_rate = 384000000;
147 break;
148 case RT3352_SYSCFG0_CPUCLK_HIGH:
149 cpu_rate = 400000000;
150 break;
151 }
152 sys_rate = wdt_rate = cpu_rate / 3;
153 uart_rate = 40000000;
154 } else if (soc_is_rt5350()) {
155 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
156 RT5350_SYSCFG0_CPUCLK_MASK;
157 switch (t) {
158 case RT5350_SYSCFG0_CPUCLK_360:
159 cpu_rate = 360000000;
160 sys_rate = cpu_rate / 3;
161 break;
162 case RT5350_SYSCFG0_CPUCLK_320:
163 cpu_rate = 320000000;
164 sys_rate = cpu_rate / 4;
165 break;
166 case RT5350_SYSCFG0_CPUCLK_300:
167 cpu_rate = 300000000;
168 sys_rate = cpu_rate / 3;
169 break;
170 default:
171 BUG();
172 }
173 uart_rate = 40000000;
174 wdt_rate = sys_rate;
175 } else {
176 BUG();
177 }
178
179 ralink_clk_add("cpu", cpu_rate);
180 ralink_clk_add("10000b00.spi", sys_rate);
181 ralink_clk_add("10000100.timer", wdt_rate);
182 ralink_clk_add("10000500.uart", uart_rate);
183 ralink_clk_add("10000c00.uartlite", uart_rate);
184}
185
186void __init ralink_of_remap(void)
187{
188 rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
189 rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
190
191 if (!rt_sysc_membase || !rt_memc_membase)
192 panic("Failed to remap core resources");
193}
194
195void prom_soc_init(struct ralink_soc_info *soc_info)
196{
197 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
198 unsigned char *name;
199 u32 n0;
200 u32 n1;
201 u32 id;
202
203 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
204 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
205
206 if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
207 unsigned long icache_sets;
208
209 icache_sets = (read_c0_config1() >> 22) & 7;
210 if (icache_sets == 1) {
211 rt305x_soc = RT305X_SOC_RT3050;
212 name = "RT3050";
213 soc_info->compatible = "ralink,rt3050-soc";
214 } else {
215 rt305x_soc = RT305X_SOC_RT3052;
216 name = "RT3052";
217 soc_info->compatible = "ralink,rt3052-soc";
218 }
219 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
220 rt305x_soc = RT305X_SOC_RT3350;
221 name = "RT3350";
222 soc_info->compatible = "ralink,rt3350-soc";
223 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
224 rt305x_soc = RT305X_SOC_RT3352;
225 name = "RT3352";
226 soc_info->compatible = "ralink,rt3352-soc";
227 } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
228 rt305x_soc = RT305X_SOC_RT5350;
229 name = "RT5350";
230 soc_info->compatible = "ralink,rt5350-soc";
231 } else {
232 panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
233 }
234
235 id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
236
237 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
238 "Ralink %s id:%u rev:%u",
239 name,
240 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
241 (id & CHIP_ID_REV_MASK));
242}
diff --git a/arch/mips/sgi-ip27/ip27-console.c b/arch/mips/sgi-ip27/ip27-console.c
index 984e561f0f7a..b952d5b1af86 100644
--- a/arch/mips/sgi-ip27/ip27-console.c
+++ b/arch/mips/sgi-ip27/ip27-console.c
@@ -31,7 +31,7 @@ static inline struct ioc3_uartregs *console_uart(void)
31 return &ioc3->sregs.uarta; 31 return &ioc3->sregs.uarta;
32} 32}
33 33
34void __init prom_putchar(char c) 34void prom_putchar(char c)
35{ 35{
36 struct ioc3_uartregs *uart = console_uart(); 36 struct ioc3_uartregs *uart = console_uart();
37 37
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 560fe8991753..5524f2c7b05c 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -513,19 +513,19 @@ void __init txx9_sio_init(unsigned long baseaddr, int irq,
513} 513}
514 514
515#ifdef CONFIG_EARLY_PRINTK 515#ifdef CONFIG_EARLY_PRINTK
516static void __init null_prom_putchar(char c) 516static void null_prom_putchar(char c)
517{ 517{
518} 518}
519void (*txx9_prom_putchar)(char c) __initdata = null_prom_putchar; 519void (*txx9_prom_putchar)(char c) = null_prom_putchar;
520 520
521void __init prom_putchar(char c) 521void prom_putchar(char c)
522{ 522{
523 txx9_prom_putchar(c); 523 txx9_prom_putchar(c);
524} 524}
525 525
526static void __iomem *early_txx9_sio_port; 526static void __iomem *early_txx9_sio_port;
527 527
528static void __init early_txx9_sio_putchar(char c) 528static void early_txx9_sio_putchar(char c)
529{ 529{
530#define TXX9_SICISR 0x0c 530#define TXX9_SICISR 0x0c
531#define TXX9_SITFIFO 0x1c 531#define TXX9_SITFIFO 0x1c
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 17:46:15 -0500