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-rw-r--r--arch/mips/Kbuild.platforms1
-rw-r--r--arch/mips/Kconfig37
-rw-r--r--arch/mips/alchemy/board-mtx1.c4
-rw-r--r--arch/mips/alchemy/common/platform.c10
-rw-r--r--arch/mips/alchemy/devboards/Makefile2
-rw-r--r--arch/mips/alchemy/devboards/bcsr.c5
-rw-r--r--arch/mips/alchemy/devboards/pb1100.c4
-rw-r--r--arch/mips/alchemy/devboards/pb1500.c4
-rw-r--r--arch/mips/alchemy/devboards/platform.c30
-rw-r--r--arch/mips/alchemy/devboards/prom.c69
-rw-r--r--arch/mips/bcm63xx/Kconfig4
-rw-r--r--arch/mips/bcm63xx/Makefile3
-rw-r--r--arch/mips/bcm63xx/boards/board_bcm963xx.c107
-rw-r--r--arch/mips/bcm63xx/clk.c26
-rw-r--r--arch/mips/bcm63xx/cpu.c63
-rw-r--r--arch/mips/bcm63xx/dev-dsp.c2
-rw-r--r--arch/mips/bcm63xx/dev-flash.c123
-rw-r--r--arch/mips/bcm63xx/dev-rng.c40
-rw-r--r--arch/mips/bcm63xx/dev-spi.c119
-rw-r--r--arch/mips/bcm63xx/dev-wdt.c2
-rw-r--r--arch/mips/bcm63xx/irq.c21
-rw-r--r--arch/mips/bcm63xx/prom.c4
-rw-r--r--arch/mips/bcm63xx/setup.c13
-rw-r--r--arch/mips/cavium-octeon/.gitignore2
-rw-r--r--arch/mips/cavium-octeon/Makefile16
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-fpa.c183
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c243
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c399
-rw-r--r--arch/mips/cavium-octeon/octeon-memcpy.S16
-rw-r--r--arch/mips/cavium-octeon/octeon-platform.c699
-rw-r--r--arch/mips/cavium-octeon/octeon_3xxx.dts571
-rw-r--r--arch/mips/cavium-octeon/octeon_68xx.dts625
-rw-r--r--arch/mips/cavium-octeon/serial.c134
-rw-r--r--arch/mips/cavium-octeon/setup.c45
-rw-r--r--arch/mips/configs/ls1b_defconfig109
-rw-r--r--arch/mips/configs/nlm_xlr_defconfig4
-rw-r--r--arch/mips/dec/prom/memory.c2
-rw-r--r--arch/mips/include/asm/cpu.h3
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h150
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h89
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h8
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h286
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h1
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h45
-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h3
-rw-r--r--arch/mips/include/asm/mach-loongson1/irq.h73
-rw-r--r--arch/mips/include/asm/mach-loongson1/loongson1.h44
-rw-r--r--arch/mips/include/asm/mach-loongson1/platform.h23
-rw-r--r--arch/mips/include/asm/mach-loongson1/prom.h24
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-clk.h33
-rw-r--r--arch/mips/include/asm/mach-loongson1/regs-wdt.h22
-rw-r--r--arch/mips/include/asm/mach-loongson1/war.h25
-rw-r--r--arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-tx49xx/mangle-port.h2
-rw-r--r--arch/mips/include/asm/mipsmtregs.h13
-rw-r--r--arch/mips/include/asm/module.h2
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h4
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/iomap.h5
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pcibus.h76
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/pic.h4
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/usb.h64
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h17
-rw-r--r--arch/mips/include/asm/netlogic/xlr/bridge.h104
-rw-r--r--arch/mips/include/asm/netlogic/xlr/flash.h55
-rw-r--r--arch/mips/include/asm/netlogic/xlr/gpio.h59
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-fpa.h64
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper.h2
-rw-r--r--arch/mips/include/asm/octeon/octeon.h5
-rw-r--r--arch/mips/include/asm/prom.h3
-rw-r--r--arch/mips/include/asm/smtc.h6
-rw-r--r--arch/mips/include/asm/uaccess.h6
-rw-r--r--arch/mips/include/asm/uasm.h100
-rw-r--r--arch/mips/kernel/cpu-probe.c299
-rw-r--r--arch/mips/kernel/perf_event_mipsxx.c5
-rw-r--r--arch/mips/kernel/prom.c29
-rw-r--r--arch/mips/kernel/smp.c4
-rw-r--r--arch/mips/kernel/smtc.c76
-rw-r--r--arch/mips/kernel/traps.c1
-rw-r--r--arch/mips/lib/Makefile2
-rw-r--r--arch/mips/lib/memcpy-inatomic.S451
-rw-r--r--arch/mips/lib/memcpy.S11
-rw-r--r--arch/mips/loongson1/Kconfig21
-rw-r--r--arch/mips/loongson1/Makefile11
-rw-r--r--arch/mips/loongson1/Platform7
-rw-r--r--arch/mips/loongson1/common/Makefile5
-rw-r--r--arch/mips/loongson1/common/clock.c165
-rw-r--r--arch/mips/loongson1/common/irq.c147
-rw-r--r--arch/mips/loongson1/common/platform.c124
-rw-r--r--arch/mips/loongson1/common/prom.c87
-rw-r--r--arch/mips/loongson1/common/reset.c45
-rw-r--r--arch/mips/loongson1/common/setup.c29
-rw-r--r--arch/mips/loongson1/ls1b/Makefile5
-rw-r--r--arch/mips/loongson1/ls1b/board.c33
-rw-r--r--arch/mips/mm/uasm.c62
-rw-r--r--arch/mips/netlogic/common/earlycons.c2
-rw-r--r--arch/mips/netlogic/common/smpboot.S157
-rw-r--r--arch/mips/netlogic/xlp/Makefile2
-rw-r--r--arch/mips/netlogic/xlp/nlm_hal.c52
-rw-r--r--arch/mips/netlogic/xlp/of.c34
-rw-r--r--arch/mips/netlogic/xlp/platform.c2
-rw-r--r--arch/mips/netlogic/xlp/setup.c16
-rw-r--r--arch/mips/netlogic/xlp/usb-init.c124
-rw-r--r--arch/mips/netlogic/xlr/Makefile2
-rw-r--r--arch/mips/netlogic/xlr/platform-flash.c220
-rw-r--r--arch/mips/netlogic/xlr/platform.c140
-rw-r--r--arch/mips/netlogic/xlr/setup.c2
-rw-r--r--arch/mips/oprofile/common.c1
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c10
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-cobalt.c8
-rw-r--r--arch/mips/pci/fixup-malta.c14
-rw-r--r--arch/mips/pci/fixup-rc32434.c2
-rw-r--r--arch/mips/pci/ops-bcm63xx.c63
-rw-r--r--arch/mips/pci/pci-bcm63xx.c133
-rw-r--r--arch/mips/pci/pci-bcm63xx.h5
-rw-r--r--arch/mips/pci/pci-xlp.c248
-rw-r--r--arch/mips/pci/pci-xlr.c4
-rw-r--r--arch/mips/pnx833x/stb22x/board.c4
-rw-r--r--arch/mips/txx9/generic/pci.c6
-rw-r--r--arch/mips/txx9/generic/setup.c12
-rw-r--r--arch/mips/txx9/generic/setup_tx4939.c2
-rw-r--r--arch/mips/txx9/rbtx4939/setup.c11
124 files changed, 6146 insertions, 1926 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 5ce8029f558b..d64786d5e2f3 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -14,6 +14,7 @@ platforms += jz4740
14platforms += lantiq 14platforms += lantiq
15platforms += lasat 15platforms += lasat
16platforms += loongson 16platforms += loongson
17platforms += loongson1
17platforms += mipssim 18platforms += mipssim
18platforms += mti-malta 19platforms += mti-malta
19platforms += netlogic 20platforms += netlogic
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index debdb6e83409..750429018534 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -265,6 +265,16 @@ config MACH_LOONGSON
265 Chinese Academy of Sciences (CAS) in the People's Republic 265 Chinese Academy of Sciences (CAS) in the People's Republic
266 of China. The chief architect is Professor Weiwu Hu. 266 of China. The chief architect is Professor Weiwu Hu.
267 267
268config MACH_LOONGSON1
269 bool "Loongson 1 family of machines"
270 select SYS_SUPPORTS_ZBOOT
271 help
272 This enables support for the Loongson 1 based machines.
273
274 Loongson 1 is a family of 32-bit MIPS-compatible SoCs developed by
275 the ICT (Institute of Computing Technology) and the Chinese Academy
276 of Sciences.
277
268config MIPS_MALTA 278config MIPS_MALTA
269 bool "MIPS Malta board" 279 bool "MIPS Malta board"
270 select ARCH_MAY_HAVE_PC_FDC 280 select ARCH_MAY_HAVE_PC_FDC
@@ -788,6 +798,8 @@ config NLM_XLR_BOARD
788 select ZONE_DMA if 64BIT 798 select ZONE_DMA if 64BIT
789 select SYNC_R4K 799 select SYNC_R4K
790 select SYS_HAS_EARLY_PRINTK 800 select SYS_HAS_EARLY_PRINTK
801 select USB_ARCH_HAS_OHCI if USB_SUPPORT
802 select USB_ARCH_HAS_EHCI if USB_SUPPORT
791 help 803 help
792 Support for systems based on Netlogic XLR and XLS processors. 804 Support for systems based on Netlogic XLR and XLS processors.
793 Say Y here if you have a XLR or XLS based board. 805 Say Y here if you have a XLR or XLS based board.
@@ -800,7 +812,6 @@ config NLM_XLP_BOARD
800 select SYS_HAS_CPU_XLP 812 select SYS_HAS_CPU_XLP
801 select SYS_SUPPORTS_SMP 813 select SYS_SUPPORTS_SMP
802 select HW_HAS_PCI 814 select HW_HAS_PCI
803 select SWAP_IO_SPACE
804 select SYS_SUPPORTS_32BIT_KERNEL 815 select SYS_SUPPORTS_32BIT_KERNEL
805 select SYS_SUPPORTS_64BIT_KERNEL 816 select SYS_SUPPORTS_64BIT_KERNEL
806 select 64BIT_PHYS_ADDR 817 select 64BIT_PHYS_ADDR
@@ -837,6 +848,7 @@ source "arch/mips/txx9/Kconfig"
837source "arch/mips/vr41xx/Kconfig" 848source "arch/mips/vr41xx/Kconfig"
838source "arch/mips/cavium-octeon/Kconfig" 849source "arch/mips/cavium-octeon/Kconfig"
839source "arch/mips/loongson/Kconfig" 850source "arch/mips/loongson/Kconfig"
851source "arch/mips/loongson1/Kconfig"
840source "arch/mips/netlogic/Kconfig" 852source "arch/mips/netlogic/Kconfig"
841 853
842endmenu 854endmenu
@@ -1218,6 +1230,14 @@ config CPU_LOONGSON2F
1218 have a similar programming interface with FPGA northbridge used in 1230 have a similar programming interface with FPGA northbridge used in
1219 Loongson2E. 1231 Loongson2E.
1220 1232
1233config CPU_LOONGSON1B
1234 bool "Loongson 1B"
1235 depends on SYS_HAS_CPU_LOONGSON1B
1236 select CPU_LOONGSON1
1237 help
1238 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1239 release 2 instruction set.
1240
1221config CPU_MIPS32_R1 1241config CPU_MIPS32_R1
1222 bool "MIPS32 Release 1" 1242 bool "MIPS32 Release 1"
1223 depends on SYS_HAS_CPU_MIPS32_R1 1243 depends on SYS_HAS_CPU_MIPS32_R1
@@ -1433,6 +1453,8 @@ config CPU_CAVIUM_OCTEON
1433 select WEAK_ORDERING 1453 select WEAK_ORDERING
1434 select CPU_SUPPORTS_HIGHMEM 1454 select CPU_SUPPORTS_HIGHMEM
1435 select CPU_SUPPORTS_HUGEPAGES 1455 select CPU_SUPPORTS_HUGEPAGES
1456 select LIBFDT
1457 select USE_OF
1436 help 1458 help
1437 The Cavium Octeon processor is a highly integrated chip containing 1459 The Cavium Octeon processor is a highly integrated chip containing
1438 many ethernet hardware widgets for networking tasks. The processor 1460 many ethernet hardware widgets for networking tasks. The processor
@@ -1545,6 +1567,14 @@ config CPU_LOONGSON2
1545 select CPU_SUPPORTS_64BIT_KERNEL 1567 select CPU_SUPPORTS_64BIT_KERNEL
1546 select CPU_SUPPORTS_HIGHMEM 1568 select CPU_SUPPORTS_HIGHMEM
1547 1569
1570config CPU_LOONGSON1
1571 bool
1572 select CPU_MIPS32
1573 select CPU_MIPSR2
1574 select CPU_HAS_PREFETCH
1575 select CPU_SUPPORTS_32BIT_KERNEL
1576 select CPU_SUPPORTS_HIGHMEM
1577
1548config CPU_BMIPS 1578config CPU_BMIPS
1549 bool 1579 bool
1550 select CPU_MIPS32 1580 select CPU_MIPS32
@@ -1563,6 +1593,9 @@ config SYS_HAS_CPU_LOONGSON2F
1563 select CPU_SUPPORTS_ADDRWINCFG if 64BIT 1593 select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1564 select CPU_SUPPORTS_UNCACHED_ACCELERATED 1594 select CPU_SUPPORTS_UNCACHED_ACCELERATED
1565 1595
1596config SYS_HAS_CPU_LOONGSON1B
1597 bool
1598
1566config SYS_HAS_CPU_MIPS32_R1 1599config SYS_HAS_CPU_MIPS32_R1
1567 bool 1600 bool
1568 1601
@@ -2367,6 +2400,8 @@ config PCI_DOMAINS
2367 2400
2368source "drivers/pci/Kconfig" 2401source "drivers/pci/Kconfig"
2369 2402
2403source "drivers/pci/pcie/Kconfig"
2404
2370# 2405#
2371# ISA support is now enabled via select. Too many systems still have the one 2406# ISA support is now enabled via select. Too many systems still have the one
2372# or other ISA chip on the board that users don't know about so don't expect 2407# or other ISA chip on the board that users don't know about so don't expect
diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c
index 295f1a95f745..99969484c475 100644
--- a/arch/mips/alchemy/board-mtx1.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -81,10 +81,10 @@ static void mtx1_power_off(void)
81 81
82void __init board_setup(void) 82void __init board_setup(void)
83{ 83{
84#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 84#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
85 /* Enable USB power switch */ 85 /* Enable USB power switch */
86 alchemy_gpio_direction_output(204, 0); 86 alchemy_gpio_direction_output(204, 0);
87#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 87#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
88 88
89 /* Initialize sys_pinfunc */ 89 /* Initialize sys_pinfunc */
90 au_writel(SYS_PF_NI2, SYS_PINFUNC); 90 au_writel(SYS_PF_NI2, SYS_PINFUNC);
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 95cb9113b12c..c0f3ce6dcb56 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -334,13 +334,12 @@ static void __init alchemy_setup_macs(int ctype)
334 if (alchemy_get_macs(ctype) < 1) 334 if (alchemy_get_macs(ctype) < 1)
335 return; 335 return;
336 336
337 macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); 337 macres = kmemdup(au1xxx_eth0_resources[ctype],
338 sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
338 if (!macres) { 339 if (!macres) {
339 printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n"); 340 printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n");
340 return; 341 return;
341 } 342 }
342 memcpy(macres, au1xxx_eth0_resources[ctype],
343 sizeof(struct resource) * MAC_RES_COUNT);
344 au1xxx_eth0_device.resource = macres; 343 au1xxx_eth0_device.resource = macres;
345 344
346 i = prom_get_ethernet_addr(ethaddr); 345 i = prom_get_ethernet_addr(ethaddr);
@@ -356,13 +355,12 @@ static void __init alchemy_setup_macs(int ctype)
356 if (alchemy_get_macs(ctype) < 2) 355 if (alchemy_get_macs(ctype) < 2)
357 return; 356 return;
358 357
359 macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL); 358 macres = kmemdup(au1xxx_eth1_resources[ctype],
359 sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
360 if (!macres) { 360 if (!macres) {
361 printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n"); 361 printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n");
362 return; 362 return;
363 } 363 }
364 memcpy(macres, au1xxx_eth1_resources[ctype],
365 sizeof(struct resource) * MAC_RES_COUNT);
366 au1xxx_eth1_device.resource = macres; 364 au1xxx_eth1_device.resource = macres;
367 365
368 ethaddr[5] += 1; /* next addr for 2nd MAC */ 366 ethaddr[5] += 1; /* next addr for 2nd MAC */
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 3c37fb303364..c9e747dd9fc2 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -2,7 +2,7 @@
2# Alchemy Develboards 2# Alchemy Develboards
3# 3#
4 4
5obj-y += prom.o bcsr.o platform.o 5obj-y += bcsr.o platform.o
6obj-$(CONFIG_PM) += pm.o 6obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_MIPS_PB1100) += pb1100.o 7obj-$(CONFIG_MIPS_PB1100) += pb1100.o
8obj-$(CONFIG_MIPS_PB1500) += pb1500.o 8obj-$(CONFIG_MIPS_PB1500) += pb1500.o
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index 1e83ce2e1147..f2039ef2c293 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -90,10 +90,7 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
90 unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT); 90 unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
91 91
92 disable_irq_nosync(irq); 92 disable_irq_nosync(irq);
93 93 generic_handle_irq(bcsr_csc_base + __ffs(bisr));
94 for ( ; bisr; bisr &= bisr - 1)
95 generic_handle_irq(bcsr_csc_base + __ffs(bisr));
96
97 enable_irq(irq); 94 enable_irq(irq);
98} 95}
99 96
diff --git a/arch/mips/alchemy/devboards/pb1100.c b/arch/mips/alchemy/devboards/pb1100.c
index cff50d05ddd4..78c77a44a317 100644
--- a/arch/mips/alchemy/devboards/pb1100.c
+++ b/arch/mips/alchemy/devboards/pb1100.c
@@ -46,7 +46,7 @@ void __init board_setup(void)
46 alchemy_gpio1_input_enable(); 46 alchemy_gpio1_input_enable();
47 udelay(100); 47 udelay(100);
48 48
49#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 49#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
50 { 50 {
51 u32 pin_func, sys_freqctrl, sys_clksrc; 51 u32 pin_func, sys_freqctrl, sys_clksrc;
52 52
@@ -93,7 +93,7 @@ void __init board_setup(void)
93 pin_func |= SYS_PF_USB; 93 pin_func |= SYS_PF_USB;
94 au_writel(pin_func, SYS_PINFUNC); 94 au_writel(pin_func, SYS_PINFUNC);
95 } 95 }
96#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 96#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
97 97
98 /* Enable sys bus clock divider when IDLE state or no bus activity. */ 98 /* Enable sys bus clock divider when IDLE state or no bus activity. */
99 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); 99 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
diff --git a/arch/mips/alchemy/devboards/pb1500.c b/arch/mips/alchemy/devboards/pb1500.c
index e7b807b3ec51..232fee942000 100644
--- a/arch/mips/alchemy/devboards/pb1500.c
+++ b/arch/mips/alchemy/devboards/pb1500.c
@@ -53,7 +53,7 @@ void __init board_setup(void)
53 alchemy_gpio_direction_input(201); 53 alchemy_gpio_direction_input(201);
54 alchemy_gpio_direction_input(203); 54 alchemy_gpio_direction_input(203);
55 55
56#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 56#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
57 57
58 /* Zero and disable FREQ2 */ 58 /* Zero and disable FREQ2 */
59 sys_freqctrl = au_readl(SYS_FREQCTRL0); 59 sys_freqctrl = au_readl(SYS_FREQCTRL0);
@@ -87,7 +87,7 @@ void __init board_setup(void)
87 /* 2nd USB port is USB host */ 87 /* 2nd USB port is USB host */
88 pin_func |= SYS_PF_USB; 88 pin_func |= SYS_PF_USB;
89 au_writel(pin_func, SYS_PINFUNC); 89 au_writel(pin_func, SYS_PINFUNC);
90#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 90#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
91 91
92#ifdef CONFIG_PCI 92#ifdef CONFIG_PCI
93 { 93 {
diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c
index 621f70afb63a..f39042e99d0d 100644
--- a/arch/mips/alchemy/devboards/platform.c
+++ b/arch/mips/alchemy/devboards/platform.c
@@ -10,9 +10,39 @@
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/pm.h> 11#include <linux/pm.h>
12 12
13#include <asm/bootinfo.h>
13#include <asm/reboot.h> 14#include <asm/reboot.h>
15#include <asm/mach-au1x00/au1000.h>
14#include <asm/mach-db1x00/bcsr.h> 16#include <asm/mach-db1x00/bcsr.h>
15 17
18#include <prom.h>
19
20void __init prom_init(void)
21{
22 unsigned char *memsize_str;
23 unsigned long memsize;
24
25 prom_argc = (int)fw_arg0;
26 prom_argv = (char **)fw_arg1;
27 prom_envp = (char **)fw_arg2;
28
29 prom_init_cmdline();
30 memsize_str = prom_getenv("memsize");
31 if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
32 memsize = 64 << 20; /* all devboards have at least 64MB RAM */
33
34 add_memory_region(0, memsize, BOOT_MEM_RAM);
35}
36
37void prom_putchar(unsigned char c)
38{
39#ifdef CONFIG_MIPS_DB1300
40 alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
41#else
42 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
43#endif
44}
45
16 46
17static struct platform_device db1x00_rtc_dev = { 47static struct platform_device db1x00_rtc_dev = {
18 .name = "rtc-au1xxx", 48 .name = "rtc-au1xxx",
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
deleted file mode 100644
index 93a22107cc41..000000000000
--- a/arch/mips/alchemy/devboards/prom.c
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * Common code used by all Alchemy develboards.
3 *
4 * Extracted from files which had this to say:
5 *
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <asm/bootinfo.h>
33#include <asm/mach-au1x00/au1000.h>
34#include <prom.h>
35
36#if defined(CONFIG_MIPS_DB1000) || \
37 defined(CONFIG_MIPS_PB1100) || \
38 defined(CONFIG_MIPS_PB1500)
39#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000
40
41#else /* Au1550/Au1200-based develboards */
42#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x08000000
43#endif
44
45void __init prom_init(void)
46{
47 unsigned char *memsize_str;
48 unsigned long memsize;
49
50 prom_argc = (int)fw_arg0;
51 prom_argv = (char **)fw_arg1;
52 prom_envp = (char **)fw_arg2;
53
54 prom_init_cmdline();
55 memsize_str = prom_getenv("memsize");
56 if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
57 memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE;
58
59 add_memory_region(0, memsize, BOOT_MEM_RAM);
60}
61
62void prom_putchar(unsigned char c)
63{
64#ifdef CONFIG_MIPS_DB1300
65 alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
66#else
67 alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
68#endif
69}
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index 6b1b9ad8d857..d03e8799d1cf 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -1,6 +1,10 @@
1menu "CPU support" 1menu "CPU support"
2 depends on BCM63XX 2 depends on BCM63XX
3 3
4config BCM63XX_CPU_6328
5 bool "support 6328 CPU"
6 select HW_HAS_PCI
7
4config BCM63XX_CPU_6338 8config BCM63XX_CPU_6338
5 bool "support 6338 CPU" 9 bool "support 6338 CPU"
6 select HW_HAS_PCI 10 select HW_HAS_PCI
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index 6dfdc69928ac..833af72c852a 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -1,5 +1,6 @@
1obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ 1obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
2 dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o 2 dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \
3 dev-spi.o dev-uart.o dev-wdt.o
3obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 4obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
4 5
5obj-y += boards/ 6obj-y += boards/
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 2f1773f3fb7a..feb05258a4d1 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -11,9 +11,6 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/string.h> 12#include <linux/string.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/mtd/mtd.h>
15#include <linux/mtd/partitions.h>
16#include <linux/mtd/physmap.h>
17#include <linux/ssb/ssb.h> 14#include <linux/ssb/ssb.h>
18#include <asm/addrspace.h> 15#include <asm/addrspace.h>
19#include <bcm63xx_board.h> 16#include <bcm63xx_board.h>
@@ -24,7 +21,9 @@
24#include <bcm63xx_dev_pci.h> 21#include <bcm63xx_dev_pci.h>
25#include <bcm63xx_dev_enet.h> 22#include <bcm63xx_dev_enet.h>
26#include <bcm63xx_dev_dsp.h> 23#include <bcm63xx_dev_dsp.h>
24#include <bcm63xx_dev_flash.h>
27#include <bcm63xx_dev_pcmcia.h> 25#include <bcm63xx_dev_pcmcia.h>
26#include <bcm63xx_dev_spi.h>
28#include <board_bcm963xx.h> 27#include <board_bcm963xx.h>
29 28
30#define PFX "board_bcm963xx: " 29#define PFX "board_bcm963xx: "
@@ -34,6 +33,48 @@ static unsigned int mac_addr_used;
34static struct board_info board; 33static struct board_info board;
35 34
36/* 35/*
36 * known 6328 boards
37 */
38#ifdef CONFIG_BCM63XX_CPU_6328
39static struct board_info __initdata board_96328avng = {
40 .name = "96328avng",
41 .expected_cpu_id = 0x6328,
42
43 .has_uart0 = 1,
44 .has_pci = 1,
45
46 .leds = {
47 {
48 .name = "96328avng::ppp-fail",
49 .gpio = 2,
50 .active_low = 1,
51 },
52 {
53 .name = "96328avng::power",
54 .gpio = 4,
55 .active_low = 1,
56 .default_trigger = "default-on",
57 },
58 {
59 .name = "96328avng::power-fail",
60 .gpio = 8,
61 .active_low = 1,
62 },
63 {
64 .name = "96328avng::wps",
65 .gpio = 9,
66 .active_low = 1,
67 },
68 {
69 .name = "96328avng::ppp",
70 .gpio = 11,
71 .active_low = 1,
72 },
73 },
74};
75#endif
76
77/*
37 * known 6338 boards 78 * known 6338 boards
38 */ 79 */
39#ifdef CONFIG_BCM63XX_CPU_6338 80#ifdef CONFIG_BCM63XX_CPU_6338
@@ -592,6 +633,9 @@ static struct board_info __initdata board_DWVS0 = {
592 * all boards 633 * all boards
593 */ 634 */
594static const struct board_info __initdata *bcm963xx_boards[] = { 635static const struct board_info __initdata *bcm963xx_boards[] = {
636#ifdef CONFIG_BCM63XX_CPU_6328
637 &board_96328avng,
638#endif
595#ifdef CONFIG_BCM63XX_CPU_6338 639#ifdef CONFIG_BCM63XX_CPU_6338
596 &board_96338gw, 640 &board_96338gw,
597 &board_96338w, 641 &board_96338w,
@@ -709,9 +753,15 @@ void __init board_prom_init(void)
709 char cfe_version[32]; 753 char cfe_version[32];
710 u32 val; 754 u32 val;
711 755
712 /* read base address of boot chip select (0) */ 756 /* read base address of boot chip select (0)
713 val = bcm_mpi_readl(MPI_CSBASE_REG(0)); 757 * 6328 does not have MPI but boots from a fixed address
714 val &= MPI_CSBASE_BASE_MASK; 758 */
759 if (BCMCPU_IS_6328())
760 val = 0x18000000;
761 else {
762 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
763 val &= MPI_CSBASE_BASE_MASK;
764 }
715 boot_addr = (u8 *)KSEG1ADDR(val); 765 boot_addr = (u8 *)KSEG1ADDR(val);
716 766
717 /* dump cfe version */ 767 /* dump cfe version */
@@ -808,40 +858,6 @@ void __init board_setup(void)
808 panic("unexpected CPU for bcm963xx board"); 858 panic("unexpected CPU for bcm963xx board");
809} 859}
810 860
811static struct mtd_partition mtd_partitions[] = {
812 {
813 .name = "cfe",
814 .offset = 0x0,
815 .size = 0x40000,
816 }
817};
818
819static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL };
820
821static struct physmap_flash_data flash_data = {
822 .width = 2,
823 .nr_parts = ARRAY_SIZE(mtd_partitions),
824 .parts = mtd_partitions,
825 .part_probe_types = bcm63xx_part_types,
826};
827
828static struct resource mtd_resources[] = {
829 {
830 .start = 0, /* filled at runtime */
831 .end = 0, /* filled at runtime */
832 .flags = IORESOURCE_MEM,
833 }
834};
835
836static struct platform_device mtd_dev = {
837 .name = "physmap-flash",
838 .resource = mtd_resources,
839 .num_resources = ARRAY_SIZE(mtd_resources),
840 .dev = {
841 .platform_data = &flash_data,
842 },
843};
844
845static struct gpio_led_platform_data bcm63xx_led_data; 861static struct gpio_led_platform_data bcm63xx_led_data;
846 862
847static struct platform_device bcm63xx_gpio_leds = { 863static struct platform_device bcm63xx_gpio_leds = {
@@ -855,8 +871,6 @@ static struct platform_device bcm63xx_gpio_leds = {
855 */ 871 */
856int __init board_register_devices(void) 872int __init board_register_devices(void)
857{ 873{
858 u32 val;
859
860 if (board.has_uart0) 874 if (board.has_uart0)
861 bcm63xx_uart_register(0); 875 bcm63xx_uart_register(0);
862 876
@@ -890,14 +904,9 @@ int __init board_register_devices(void)
890 } 904 }
891#endif 905#endif
892 906
893 /* read base address of boot chip select (0) */ 907 bcm63xx_spi_register();
894 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
895 val &= MPI_CSBASE_BASE_MASK;
896
897 mtd_resources[0].start = val;
898 mtd_resources[0].end = 0x1FFFFFFF;
899 908
900 platform_device_register(&mtd_dev); 909 bcm63xx_flash_register();
901 910
902 bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); 911 bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
903 bcm63xx_led_data.leds = board.leds; 912 bcm63xx_led_data.leds = board.leds;
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 9d57c71b7b58..1db48adb543a 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -120,7 +120,7 @@ static void enetsw_set(struct clk *clk, int enable)
120{ 120{
121 if (!BCMCPU_IS_6368()) 121 if (!BCMCPU_IS_6368())
122 return; 122 return;
123 bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN | 123 bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
124 CKCTL_6368_SWPKT_USB_EN | 124 CKCTL_6368_SWPKT_USB_EN |
125 CKCTL_6368_SWPKT_SAR_EN, enable); 125 CKCTL_6368_SWPKT_SAR_EN, enable);
126 if (enable) { 126 if (enable) {
@@ -163,7 +163,7 @@ static void usbh_set(struct clk *clk, int enable)
163 if (BCMCPU_IS_6348()) 163 if (BCMCPU_IS_6348())
164 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); 164 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
165 else if (BCMCPU_IS_6368()) 165 else if (BCMCPU_IS_6368())
166 bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable); 166 bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
167} 167}
168 168
169static struct clk clk_usbh = { 169static struct clk clk_usbh = {
@@ -181,9 +181,11 @@ static void spi_set(struct clk *clk, int enable)
181 mask = CKCTL_6338_SPI_EN; 181 mask = CKCTL_6338_SPI_EN;
182 else if (BCMCPU_IS_6348()) 182 else if (BCMCPU_IS_6348())
183 mask = CKCTL_6348_SPI_EN; 183 mask = CKCTL_6348_SPI_EN;
184 else 184 else if (BCMCPU_IS_6358())
185 /* BCMCPU_IS_6358 */
186 mask = CKCTL_6358_SPI_EN; 185 mask = CKCTL_6358_SPI_EN;
186 else
187 /* BCMCPU_IS_6368 */
188 mask = CKCTL_6368_SPI_EN;
187 bcm_hwclock_set(mask, enable); 189 bcm_hwclock_set(mask, enable);
188} 190}
189 191
@@ -199,7 +201,7 @@ static void xtm_set(struct clk *clk, int enable)
199 if (!BCMCPU_IS_6368()) 201 if (!BCMCPU_IS_6368())
200 return; 202 return;
201 203
202 bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN | 204 bcm_hwclock_set(CKCTL_6368_SAR_EN |
203 CKCTL_6368_SWPKT_SAR_EN, enable); 205 CKCTL_6368_SWPKT_SAR_EN, enable);
204 206
205 if (enable) { 207 if (enable) {
@@ -222,6 +224,18 @@ static struct clk clk_xtm = {
222}; 224};
223 225
224/* 226/*
227 * IPsec clock
228 */
229static void ipsec_set(struct clk *clk, int enable)
230{
231 bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
232}
233
234static struct clk clk_ipsec = {
235 .set = ipsec_set,
236};
237
238/*
225 * Internal peripheral clock 239 * Internal peripheral clock
226 */ 240 */
227static struct clk clk_periph = { 241static struct clk clk_periph = {
@@ -278,6 +292,8 @@ struct clk *clk_get(struct device *dev, const char *id)
278 return &clk_periph; 292 return &clk_periph;
279 if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) 293 if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
280 return &clk_pcm; 294 return &clk_pcm;
295 if (BCMCPU_IS_6368() && !strcmp(id, "ipsec"))
296 return &clk_ipsec;
281 return ERR_PTR(-ENOENT); 297 return ERR_PTR(-ENOENT);
282} 298}
283 299
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 8f0d6c7725ea..a7afb289b15a 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,6 +29,14 @@ static u16 bcm63xx_cpu_rev;
29static unsigned int bcm63xx_cpu_freq; 29static unsigned int bcm63xx_cpu_freq;
30static unsigned int bcm63xx_memory_size; 30static unsigned int bcm63xx_memory_size;
31 31
32static const unsigned long bcm6328_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(6328)
34};
35
36static const int bcm6328_irqs[] = {
37 __GEN_CPU_IRQ_TABLE(6328)
38};
39
32static const unsigned long bcm6338_regs_base[] = { 40static const unsigned long bcm6338_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(6338) 41 __GEN_CPU_REGS_TABLE(6338)
34}; 42};
@@ -99,6 +107,33 @@ unsigned int bcm63xx_get_memory_size(void)
99static unsigned int detect_cpu_clock(void) 107static unsigned int detect_cpu_clock(void)
100{ 108{
101 switch (bcm63xx_get_cpu_id()) { 109 switch (bcm63xx_get_cpu_id()) {
110 case BCM6328_CPU_ID:
111 {
112 unsigned int tmp, mips_pll_fcvo;
113
114 tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
115 mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
116 >> STRAPBUS_6328_FCVO_SHIFT;
117
118 switch (mips_pll_fcvo) {
119 case 0x12:
120 case 0x14:
121 case 0x19:
122 return 160000000;
123 case 0x1c:
124 return 192000000;
125 case 0x13:
126 case 0x15:
127 return 200000000;
128 case 0x1a:
129 return 384000000;
130 case 0x16:
131 return 400000000;
132 default:
133 return 320000000;
134 }
135
136 }
102 case BCM6338_CPU_ID: 137 case BCM6338_CPU_ID:
103 /* BCM6338 has a fixed 240 Mhz frequency */ 138 /* BCM6338 has a fixed 240 Mhz frequency */
104 return 240000000; 139 return 240000000;
@@ -170,6 +205,9 @@ static unsigned int detect_memory_size(void)
170 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; 205 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
171 u32 val; 206 u32 val;
172 207
208 if (BCMCPU_IS_6328())
209 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
210
173 if (BCMCPU_IS_6345()) { 211 if (BCMCPU_IS_6345()) {
174 val = bcm_sdram_readl(SDRAM_MBASE_REG); 212 val = bcm_sdram_readl(SDRAM_MBASE_REG);
175 return (val * 8 * 1024 * 1024); 213 return (val * 8 * 1024 * 1024);
@@ -228,17 +266,26 @@ void __init bcm63xx_cpu_init(void)
228 bcm63xx_irqs = bcm6345_irqs; 266 bcm63xx_irqs = bcm6345_irqs;
229 break; 267 break;
230 case CPU_BMIPS4350: 268 case CPU_BMIPS4350:
231 switch (read_c0_prid() & 0xf0) { 269 if ((read_c0_prid() & 0xf0) == 0x10) {
232 case 0x10:
233 expected_cpu_id = BCM6358_CPU_ID; 270 expected_cpu_id = BCM6358_CPU_ID;
234 bcm63xx_regs_base = bcm6358_regs_base; 271 bcm63xx_regs_base = bcm6358_regs_base;
235 bcm63xx_irqs = bcm6358_irqs; 272 bcm63xx_irqs = bcm6358_irqs;
236 break; 273 } else {
237 case 0x30: 274 /* all newer chips have the same chip id location */
238 expected_cpu_id = BCM6368_CPU_ID; 275 u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
239 bcm63xx_regs_base = bcm6368_regs_base; 276
240 bcm63xx_irqs = bcm6368_irqs; 277 switch (chip_id) {
241 break; 278 case BCM6328_CPU_ID:
279 expected_cpu_id = BCM6328_CPU_ID;
280 bcm63xx_regs_base = bcm6328_regs_base;
281 bcm63xx_irqs = bcm6328_irqs;
282 break;
283 case BCM6368_CPU_ID:
284 expected_cpu_id = BCM6368_CPU_ID;
285 bcm63xx_regs_base = bcm6368_regs_base;
286 bcm63xx_irqs = bcm6368_irqs;
287 break;
288 }
242 } 289 }
243 break; 290 break;
244 } 291 }
diff --git a/arch/mips/bcm63xx/dev-dsp.c b/arch/mips/bcm63xx/dev-dsp.c
index da46d1d3c77c..5bb5b154c9bd 100644
--- a/arch/mips/bcm63xx/dev-dsp.c
+++ b/arch/mips/bcm63xx/dev-dsp.c
@@ -31,7 +31,7 @@ static struct resource voip_dsp_resources[] = {
31 31
32static struct platform_device bcm63xx_voip_dsp_device = { 32static struct platform_device bcm63xx_voip_dsp_device = {
33 .name = "bcm63xx-voip-dsp", 33 .name = "bcm63xx-voip-dsp",
34 .id = 0, 34 .id = -1,
35 .num_resources = ARRAY_SIZE(voip_dsp_resources), 35 .num_resources = ARRAY_SIZE(voip_dsp_resources),
36 .resource = voip_dsp_resources, 36 .resource = voip_dsp_resources,
37}; 37};
diff --git a/arch/mips/bcm63xx/dev-flash.c b/arch/mips/bcm63xx/dev-flash.c
new file mode 100644
index 000000000000..58371c7deac2
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-flash.c
@@ -0,0 +1,123 @@
1/*
2 * Broadcom BCM63xx flash registration
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
9 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
10 * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
11 */
12
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/mtd/mtd.h>
17#include <linux/mtd/partitions.h>
18#include <linux/mtd/physmap.h>
19
20#include <bcm63xx_cpu.h>
21#include <bcm63xx_dev_flash.h>
22#include <bcm63xx_regs.h>
23#include <bcm63xx_io.h>
24
25static struct mtd_partition mtd_partitions[] = {
26 {
27 .name = "cfe",
28 .offset = 0x0,
29 .size = 0x40000,
30 }
31};
32
33static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL };
34
35static struct physmap_flash_data flash_data = {
36 .width = 2,
37 .parts = mtd_partitions,
38 .part_probe_types = bcm63xx_part_types,
39};
40
41static struct resource mtd_resources[] = {
42 {
43 .start = 0, /* filled at runtime */
44 .end = 0, /* filled at runtime */
45 .flags = IORESOURCE_MEM,
46 }
47};
48
49static struct platform_device mtd_dev = {
50 .name = "physmap-flash",
51 .resource = mtd_resources,
52 .num_resources = ARRAY_SIZE(mtd_resources),
53 .dev = {
54 .platform_data = &flash_data,
55 },
56};
57
58static int __init bcm63xx_detect_flash_type(void)
59{
60 u32 val;
61
62 switch (bcm63xx_get_cpu_id()) {
63 case BCM6328_CPU_ID:
64 val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
65 if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
66 return BCM63XX_FLASH_TYPE_SERIAL;
67 else
68 return BCM63XX_FLASH_TYPE_NAND;
69 case BCM6338_CPU_ID:
70 case BCM6345_CPU_ID:
71 case BCM6348_CPU_ID:
72 /* no way to auto detect so assume parallel */
73 return BCM63XX_FLASH_TYPE_PARALLEL;
74 case BCM6358_CPU_ID:
75 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
76 if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
77 return BCM63XX_FLASH_TYPE_PARALLEL;
78 else
79 return BCM63XX_FLASH_TYPE_SERIAL;
80 case BCM6368_CPU_ID:
81 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
82 switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
83 case STRAPBUS_6368_BOOT_SEL_NAND:
84 return BCM63XX_FLASH_TYPE_NAND;
85 case STRAPBUS_6368_BOOT_SEL_SERIAL:
86 return BCM63XX_FLASH_TYPE_SERIAL;
87 case STRAPBUS_6368_BOOT_SEL_PARALLEL:
88 return BCM63XX_FLASH_TYPE_PARALLEL;
89 }
90 default:
91 return -EINVAL;
92 }
93}
94
95int __init bcm63xx_flash_register(void)
96{
97 int flash_type;
98 u32 val;
99
100 flash_type = bcm63xx_detect_flash_type();
101
102 switch (flash_type) {
103 case BCM63XX_FLASH_TYPE_PARALLEL:
104 /* read base address of boot chip select (0) */
105 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
106 val &= MPI_CSBASE_BASE_MASK;
107
108 mtd_resources[0].start = val;
109 mtd_resources[0].end = 0x1FFFFFFF;
110
111 return platform_device_register(&mtd_dev);
112 case BCM63XX_FLASH_TYPE_SERIAL:
113 pr_warn("unsupported serial flash detected\n");
114 return -ENODEV;
115 case BCM63XX_FLASH_TYPE_NAND:
116 pr_warn("unsupported NAND flash detected\n");
117 return -ENODEV;
118 default:
119 pr_err("flash detection failed for BCM%x: %d\n",
120 bcm63xx_get_cpu_id(), flash_type);
121 return -ENODEV;
122 }
123}
diff --git a/arch/mips/bcm63xx/dev-rng.c b/arch/mips/bcm63xx/dev-rng.c
new file mode 100644
index 000000000000..d277b4dc6c68
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-rng.c
@@ -0,0 +1,40 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 Florian Fainelli <florian@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/platform_device.h>
12#include <bcm63xx_cpu.h>
13
14static struct resource rng_resources[] = {
15 {
16 .start = -1, /* filled at runtime */
17 .end = -1, /* filled at runtime */
18 .flags = IORESOURCE_MEM,
19 },
20};
21
22static struct platform_device bcm63xx_rng_device = {
23 .name = "bcm63xx-rng",
24 .id = -1,
25 .num_resources = ARRAY_SIZE(rng_resources),
26 .resource = rng_resources,
27};
28
29int __init bcm63xx_rng_register(void)
30{
31 if (!BCMCPU_IS_6368())
32 return -ENODEV;
33
34 rng_resources[0].start = bcm63xx_regset_address(RSET_RNG);
35 rng_resources[0].end = rng_resources[0].start;
36 rng_resources[0].end += RSET_RNG_SIZE - 1;
37
38 return platform_device_register(&bcm63xx_rng_device);
39}
40arch_initcall(bcm63xx_rng_register);
diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c
new file mode 100644
index 000000000000..e39f73048d4f
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-spi.c
@@ -0,0 +1,119 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
7 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
8 */
9
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/export.h>
13#include <linux/platform_device.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16
17#include <bcm63xx_cpu.h>
18#include <bcm63xx_dev_spi.h>
19#include <bcm63xx_regs.h>
20
21#ifdef BCMCPU_RUNTIME_DETECT
22/*
23 * register offsets
24 */
25static const unsigned long bcm6338_regs_spi[] = {
26 __GEN_SPI_REGS_TABLE(6338)
27};
28
29static const unsigned long bcm6348_regs_spi[] = {
30 __GEN_SPI_REGS_TABLE(6348)
31};
32
33static const unsigned long bcm6358_regs_spi[] = {
34 __GEN_SPI_REGS_TABLE(6358)
35};
36
37static const unsigned long bcm6368_regs_spi[] = {
38 __GEN_SPI_REGS_TABLE(6368)
39};
40
41const unsigned long *bcm63xx_regs_spi;
42EXPORT_SYMBOL(bcm63xx_regs_spi);
43
44static __init void bcm63xx_spi_regs_init(void)
45{
46 if (BCMCPU_IS_6338())
47 bcm63xx_regs_spi = bcm6338_regs_spi;
48 if (BCMCPU_IS_6348())
49 bcm63xx_regs_spi = bcm6348_regs_spi;
50 if (BCMCPU_IS_6358())
51 bcm63xx_regs_spi = bcm6358_regs_spi;
52 if (BCMCPU_IS_6368())
53 bcm63xx_regs_spi = bcm6368_regs_spi;
54}
55#else
56static __init void bcm63xx_spi_regs_init(void) { }
57#endif
58
59static struct resource spi_resources[] = {
60 {
61 .start = -1, /* filled at runtime */
62 .end = -1, /* filled at runtime */
63 .flags = IORESOURCE_MEM,
64 },
65 {
66 .start = -1, /* filled at runtime */
67 .flags = IORESOURCE_IRQ,
68 },
69};
70
71static struct bcm63xx_spi_pdata spi_pdata = {
72 .bus_num = 0,
73 .num_chipselect = 8,
74};
75
76static struct platform_device bcm63xx_spi_device = {
77 .name = "bcm63xx-spi",
78 .id = -1,
79 .num_resources = ARRAY_SIZE(spi_resources),
80 .resource = spi_resources,
81 .dev = {
82 .platform_data = &spi_pdata,
83 },
84};
85
86int __init bcm63xx_spi_register(void)
87{
88 struct clk *periph_clk;
89
90 if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
91 return -ENODEV;
92
93 periph_clk = clk_get(NULL, "periph");
94 if (IS_ERR(periph_clk)) {
95 pr_err("unable to get periph clock\n");
96 return -ENODEV;
97 }
98
99 /* Set bus frequency */
100 spi_pdata.speed_hz = clk_get_rate(periph_clk);
101
102 spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
103 spi_resources[0].end = spi_resources[0].start;
104 spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
105
106 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
107 spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1;
108 spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE;
109 }
110
111 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
112 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
113 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
114 }
115
116 bcm63xx_spi_regs_init();
117
118 return platform_device_register(&bcm63xx_spi_device);
119}
diff --git a/arch/mips/bcm63xx/dev-wdt.c b/arch/mips/bcm63xx/dev-wdt.c
index 3e6c716a4c11..2a2346a99bcb 100644
--- a/arch/mips/bcm63xx/dev-wdt.c
+++ b/arch/mips/bcm63xx/dev-wdt.c
@@ -21,7 +21,7 @@ static struct resource wdt_resources[] = {
21 21
22static struct platform_device bcm63xx_wdt_device = { 22static struct platform_device bcm63xx_wdt_device = {
23 .name = "bcm63xx-wdt", 23 .name = "bcm63xx-wdt",
24 .id = 0, 24 .id = -1,
25 .num_resources = ARRAY_SIZE(wdt_resources), 25 .num_resources = ARRAY_SIZE(wdt_resources),
26 .resource = wdt_resources, 26 .resource = wdt_resources,
27}; 27};
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 9a216a451d92..18e051ad18a5 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
27static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; 27static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
28 28
29#ifndef BCMCPU_RUNTIME_DETECT 29#ifndef BCMCPU_RUNTIME_DETECT
30#ifdef CONFIG_BCM63XX_CPU_6328
31#define irq_stat_reg PERF_IRQSTAT_6328_REG
32#define irq_mask_reg PERF_IRQMASK_6328_REG
33#define irq_bits 64
34#define is_ext_irq_cascaded 1
35#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
36#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
37#define ext_irq_count 4
38#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328
39#define ext_irq_cfg_reg2 0
40#endif
30#ifdef CONFIG_BCM63XX_CPU_6338 41#ifdef CONFIG_BCM63XX_CPU_6338
31#define irq_stat_reg PERF_IRQSTAT_6338_REG 42#define irq_stat_reg PERF_IRQSTAT_6338_REG
32#define irq_mask_reg PERF_IRQMASK_6338_REG 43#define irq_mask_reg PERF_IRQMASK_6338_REG
@@ -118,6 +129,16 @@ static void bcm63xx_init_irq(void)
118 irq_mask_addr = bcm63xx_regset_address(RSET_PERF); 129 irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
119 130
120 switch (bcm63xx_get_cpu_id()) { 131 switch (bcm63xx_get_cpu_id()) {
132 case BCM6328_CPU_ID:
133 irq_stat_addr += PERF_IRQSTAT_6328_REG;
134 irq_mask_addr += PERF_IRQMASK_6328_REG;
135 irq_bits = 64;
136 ext_irq_count = 4;
137 is_ext_irq_cascaded = 1;
138 ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
139 ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
140 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
141 break;
121 case BCM6338_CPU_ID: 142 case BCM6338_CPU_ID:
122 irq_stat_addr += PERF_IRQSTAT_6338_REG; 143 irq_stat_addr += PERF_IRQSTAT_6338_REG;
123 irq_mask_addr += PERF_IRQMASK_6338_REG; 144 irq_mask_addr += PERF_IRQMASK_6338_REG;
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index 99d7f405cbeb..10eaff458071 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -26,7 +26,9 @@ void __init prom_init(void)
26 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); 26 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
27 27
28 /* disable all hardware blocks clock for now */ 28 /* disable all hardware blocks clock for now */
29 if (BCMCPU_IS_6338()) 29 if (BCMCPU_IS_6328())
30 mask = CKCTL_6328_ALL_SAFE_EN;
31 else if (BCMCPU_IS_6338())
30 mask = CKCTL_6338_ALL_SAFE_EN; 32 mask = CKCTL_6338_ALL_SAFE_EN;
31 else if (BCMCPU_IS_6345()) 33 else if (BCMCPU_IS_6345())
32 mask = CKCTL_6345_ALL_SAFE_EN; 34 mask = CKCTL_6345_ALL_SAFE_EN;
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 356b05583e14..0e74a13639cd 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
68 68
69 /* mask and clear all external irq */ 69 /* mask and clear all external irq */
70 switch (bcm63xx_get_cpu_id()) { 70 switch (bcm63xx_get_cpu_id()) {
71 case BCM6328_CPU_ID:
72 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
73 break;
71 case BCM6338_CPU_ID: 74 case BCM6338_CPU_ID:
72 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338; 75 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
73 break; 76 break;
@@ -95,9 +98,13 @@ void bcm63xx_machine_reboot(void)
95 bcm6348_a1_reboot(); 98 bcm6348_a1_reboot();
96 99
97 printk(KERN_INFO "triggering watchdog soft-reset...\n"); 100 printk(KERN_INFO "triggering watchdog soft-reset...\n");
98 reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); 101 if (BCMCPU_IS_6328()) {
99 reg |= SYS_PLL_SOFT_RESET; 102 bcm_wdt_writel(1, WDT_SOFTRESET_REG);
100 bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG); 103 } else {
104 reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
105 reg |= SYS_PLL_SOFT_RESET;
106 bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
107 }
101 while (1) 108 while (1)
102 ; 109 ;
103} 110}
diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore
new file mode 100644
index 000000000000..39c968605ff6
--- /dev/null
+++ b/arch/mips/cavium-octeon/.gitignore
@@ -0,0 +1,2 @@
1*.dtb.S
2*.dtb
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 19eb0434269f..bc96e2908f14 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -9,9 +9,25 @@
9# Copyright (C) 2005-2009 Cavium Networks 9# Copyright (C) 2005-2009 Cavium Networks
10# 10#
11 11
12CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt
13CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
14
12obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o 15obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
13obj-y += dma-octeon.o flash_setup.o 16obj-y += dma-octeon.o flash_setup.o
14obj-y += octeon-memcpy.o 17obj-y += octeon-memcpy.o
15obj-y += executive/ 18obj-y += executive/
16 19
17obj-$(CONFIG_SMP) += smp.o 20obj-$(CONFIG_SMP) += smp.o
21
22DTS_FILES = octeon_3xxx.dts octeon_68xx.dts
23DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES))
24
25obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES))
26
27$(obj)/%.dtb: $(src)/%.dts FORCE
28 $(call if_changed_dep,dtc)
29
30# Let's keep the .dtb files around in case we want to look at them.
31.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES))
32
33clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES))
diff --git a/arch/mips/cavium-octeon/executive/cvmx-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-fpa.c
deleted file mode 100644
index ad44b8bd8057..000000000000
--- a/arch/mips/cavium-octeon/executive/cvmx-fpa.c
+++ /dev/null
@@ -1,183 +0,0 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Support library for the hardware Free Pool Allocator.
32 *
33 *
34 */
35
36#include "cvmx-config.h"
37#include "cvmx.h"
38#include "cvmx-fpa.h"
39#include "cvmx-ipd.h"
40
41/**
42 * Current state of all the pools. Use access functions
43 * instead of using it directly.
44 */
45CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
46
47/**
48 * Setup a FPA pool to control a new block of memory. The
49 * buffer pointer must be a physical address.
50 *
51 * @pool: Pool to initialize
52 * 0 <= pool < 8
53 * @name: Constant character string to name this pool.
54 * String is not copied.
55 * @buffer: Pointer to the block of memory to use. This must be
56 * accessible by all processors and external hardware.
57 * @block_size: Size for each block controlled by the FPA
58 * @num_blocks: Number of blocks
59 *
60 * Returns 0 on Success,
61 * -1 on failure
62 */
63int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
64 uint64_t block_size, uint64_t num_blocks)
65{
66 char *ptr;
67 if (!buffer) {
68 cvmx_dprintf
69 ("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n");
70 return -1;
71 }
72 if (pool >= CVMX_FPA_NUM_POOLS) {
73 cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n");
74 return -1;
75 }
76
77 if (block_size < CVMX_FPA_MIN_BLOCK_SIZE) {
78 cvmx_dprintf
79 ("ERROR: cvmx_fpa_setup_pool: Block size too small.\n");
80 return -1;
81 }
82
83 if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT - 1)) != 0) {
84 cvmx_dprintf
85 ("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n");
86 return -1;
87 }
88
89 cvmx_fpa_pool_info[pool].name = name;
90 cvmx_fpa_pool_info[pool].size = block_size;
91 cvmx_fpa_pool_info[pool].starting_element_count = num_blocks;
92 cvmx_fpa_pool_info[pool].base = buffer;
93
94 ptr = (char *)buffer;
95 while (num_blocks--) {
96 cvmx_fpa_free(ptr, pool, 0);
97 ptr += block_size;
98 }
99 return 0;
100}
101
102/**
103 * Shutdown a Memory pool and validate that it had all of
104 * the buffers originally placed in it.
105 *
106 * @pool: Pool to shutdown
107 * Returns Zero on success
108 * - Positive is count of missing buffers
109 * - Negative is too many buffers or corrupted pointers
110 */
111uint64_t cvmx_fpa_shutdown_pool(uint64_t pool)
112{
113 uint64_t errors = 0;
114 uint64_t count = 0;
115 uint64_t base = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base);
116 uint64_t finish =
117 base +
118 cvmx_fpa_pool_info[pool].size *
119 cvmx_fpa_pool_info[pool].starting_element_count;
120 void *ptr;
121 uint64_t address;
122
123 count = 0;
124 do {
125 ptr = cvmx_fpa_alloc(pool);
126 if (ptr)
127 address = cvmx_ptr_to_phys(ptr);
128 else
129 address = 0;
130 if (address) {
131 if ((address >= base) && (address < finish) &&
132 (((address -
133 base) % cvmx_fpa_pool_info[pool].size) == 0)) {
134 count++;
135 } else {
136 cvmx_dprintf
137 ("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n",
138 (unsigned long long)address,
139 cvmx_fpa_pool_info[pool].name, (int)pool);
140 errors++;
141 }
142 }
143 } while (address);
144
145#ifdef CVMX_ENABLE_PKO_FUNCTIONS
146 if (pool == 0)
147 cvmx_ipd_free_ptr();
148#endif
149
150 if (errors) {
151 cvmx_dprintf
152 ("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n",
153 cvmx_fpa_pool_info[pool].name, (int)pool,
154 (unsigned long long)base, (unsigned long long)finish,
155 (unsigned long long)cvmx_fpa_pool_info[pool].size);
156 return -errors;
157 } else
158 return 0;
159}
160
161uint64_t cvmx_fpa_get_block_size(uint64_t pool)
162{
163 switch (pool) {
164 case 0:
165 return CVMX_FPA_POOL_0_SIZE;
166 case 1:
167 return CVMX_FPA_POOL_1_SIZE;
168 case 2:
169 return CVMX_FPA_POOL_2_SIZE;
170 case 3:
171 return CVMX_FPA_POOL_3_SIZE;
172 case 4:
173 return CVMX_FPA_POOL_4_SIZE;
174 case 5:
175 return CVMX_FPA_POOL_5_SIZE;
176 case 6:
177 return CVMX_FPA_POOL_6_SIZE;
178 case 7:
179 return CVMX_FPA_POOL_7_SIZE;
180 default:
181 return 0;
182 }
183}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
deleted file mode 100644
index c239e5f4ab9a..000000000000
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
+++ /dev/null
@@ -1,243 +0,0 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Helper functions for FPA setup.
32 *
33 */
34#include "executive-config.h"
35#include "cvmx-config.h"
36#include "cvmx.h"
37#include "cvmx-bootmem.h"
38#include "cvmx-fpa.h"
39#include "cvmx-helper-fpa.h"
40
41/**
42 * Allocate memory for and initialize a single FPA pool.
43 *
44 * @pool: Pool to initialize
45 * @buffer_size: Size of buffers to allocate in bytes
46 * @buffers: Number of buffers to put in the pool. Zero is allowed
47 * @name: String name of the pool for debugging purposes
48 * Returns Zero on success, non-zero on failure
49 */
50static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size,
51 uint64_t buffers, const char *name)
52{
53 uint64_t current_num;
54 void *memory;
55 uint64_t align = CVMX_CACHE_LINE_SIZE;
56
57 /*
58 * Align the allocation so that power of 2 size buffers are
59 * naturally aligned.
60 */
61 while (align < buffer_size)
62 align = align << 1;
63
64 if (buffers == 0)
65 return 0;
66
67 current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool));
68 if (current_num) {
69 cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. "
70 "Skipping setup.\n",
71 pool, name, (unsigned long long)current_num);
72 return 0;
73 }
74
75 memory = cvmx_bootmem_alloc(buffer_size * buffers, align);
76 if (memory == NULL) {
77 cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n",
78 pool, name);
79 return -1;
80 }
81 cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers);
82 return 0;
83}
84
85/**
86 * Allocate memory and initialize the FPA pools using memory
87 * from cvmx-bootmem. Specifying zero for the number of
88 * buffers will cause that FPA pool to not be setup. This is
89 * useful if you aren't using some of the hardware and want
90 * to save memory. Use cvmx_helper_initialize_fpa instead of
91 * this function directly.
92 *
93 * @pip_pool: Should always be CVMX_FPA_PACKET_POOL
94 * @pip_size: Should always be CVMX_FPA_PACKET_POOL_SIZE
95 * @pip_buffers:
96 * Number of packet buffers.
97 * @wqe_pool: Should always be CVMX_FPA_WQE_POOL
98 * @wqe_size: Should always be CVMX_FPA_WQE_POOL_SIZE
99 * @wqe_entries:
100 * Number of work queue entries
101 * @pko_pool: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL
102 * @pko_size: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE
103 * @pko_buffers:
104 * PKO Command buffers. You should at minimum have two per
105 * each PKO queue.
106 * @tim_pool: Should always be CVMX_FPA_TIMER_POOL
107 * @tim_size: Should always be CVMX_FPA_TIMER_POOL_SIZE
108 * @tim_buffers:
109 * TIM ring buffer command queues. At least two per timer bucket
110 * is recommened.
111 * @dfa_pool: Should always be CVMX_FPA_DFA_POOL
112 * @dfa_size: Should always be CVMX_FPA_DFA_POOL_SIZE
113 * @dfa_buffers:
114 * DFA command buffer. A relatively small (32 for example)
115 * number should work.
116 * Returns Zero on success, non-zero if out of memory
117 */
118static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size,
119 int pip_buffers, int wqe_pool,
120 int wqe_size, int wqe_entries,
121 int pko_pool, int pko_size,
122 int pko_buffers, int tim_pool,
123 int tim_size, int tim_buffers,
124 int dfa_pool, int dfa_size,
125 int dfa_buffers)
126{
127 int status;
128
129 cvmx_fpa_enable();
130
131 if ((pip_buffers > 0) && (pip_buffers <= 64))
132 cvmx_dprintf
133 ("Warning: %d packet buffers may not be enough for hardware"
134 " prefetch. 65 or more is recommended.\n", pip_buffers);
135
136 if (pip_pool >= 0) {
137 status =
138 __cvmx_helper_initialize_fpa_pool(pip_pool, pip_size,
139 pip_buffers,
140 "Packet Buffers");
141 if (status)
142 return status;
143 }
144
145 if (wqe_pool >= 0) {
146 status =
147 __cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size,
148 wqe_entries,
149 "Work Queue Entries");
150 if (status)
151 return status;
152 }
153
154 if (pko_pool >= 0) {
155 status =
156 __cvmx_helper_initialize_fpa_pool(pko_pool, pko_size,
157 pko_buffers,
158 "PKO Command Buffers");
159 if (status)
160 return status;
161 }
162
163 if (tim_pool >= 0) {
164 status =
165 __cvmx_helper_initialize_fpa_pool(tim_pool, tim_size,
166 tim_buffers,
167 "TIM Command Buffers");
168 if (status)
169 return status;
170 }
171
172 if (dfa_pool >= 0) {
173 status =
174 __cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size,
175 dfa_buffers,
176 "DFA Command Buffers");
177 if (status)
178 return status;
179 }
180
181 return 0;
182}
183
184/**
185 * Allocate memory and initialize the FPA pools using memory
186 * from cvmx-bootmem. Sizes of each element in the pools is
187 * controlled by the cvmx-config.h header file. Specifying
188 * zero for any parameter will cause that FPA pool to not be
189 * setup. This is useful if you aren't using some of the
190 * hardware and want to save memory.
191 *
192 * @packet_buffers:
193 * Number of packet buffers to allocate
194 * @work_queue_entries:
195 * Number of work queue entries
196 * @pko_buffers:
197 * PKO Command buffers. You should at minimum have two per
198 * each PKO queue.
199 * @tim_buffers:
200 * TIM ring buffer command queues. At least two per timer bucket
201 * is recommened.
202 * @dfa_buffers:
203 * DFA command buffer. A relatively small (32 for example)
204 * number should work.
205 * Returns Zero on success, non-zero if out of memory
206 */
207int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries,
208 int pko_buffers, int tim_buffers,
209 int dfa_buffers)
210{
211#ifndef CVMX_FPA_PACKET_POOL
212#define CVMX_FPA_PACKET_POOL -1
213#define CVMX_FPA_PACKET_POOL_SIZE 0
214#endif
215#ifndef CVMX_FPA_WQE_POOL
216#define CVMX_FPA_WQE_POOL -1
217#define CVMX_FPA_WQE_POOL_SIZE 0
218#endif
219#ifndef CVMX_FPA_OUTPUT_BUFFER_POOL
220#define CVMX_FPA_OUTPUT_BUFFER_POOL -1
221#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0
222#endif
223#ifndef CVMX_FPA_TIMER_POOL
224#define CVMX_FPA_TIMER_POOL -1
225#define CVMX_FPA_TIMER_POOL_SIZE 0
226#endif
227#ifndef CVMX_FPA_DFA_POOL
228#define CVMX_FPA_DFA_POOL -1
229#define CVMX_FPA_DFA_POOL_SIZE 0
230#endif
231 return __cvmx_helper_initialize_fpa(CVMX_FPA_PACKET_POOL,
232 CVMX_FPA_PACKET_POOL_SIZE,
233 packet_buffers, CVMX_FPA_WQE_POOL,
234 CVMX_FPA_WQE_POOL_SIZE,
235 work_queue_entries,
236 CVMX_FPA_OUTPUT_BUFFER_POOL,
237 CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE,
238 pko_buffers, CVMX_FPA_TIMER_POOL,
239 CVMX_FPA_TIMER_POOL_SIZE,
240 tim_buffers, CVMX_FPA_DFA_POOL,
241 CVMX_FPA_DFA_POOL_SIZE,
242 dfa_buffers);
243}
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index ffd4ae660f79..7fb1f222b8a5 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -3,14 +3,17 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks 6 * Copyright (C) 2004-2012 Cavium, Inc.
7 */ 7 */
8 8
9#include <linux/interrupt.h> 9#include <linux/interrupt.h>
10#include <linux/irqdomain.h>
10#include <linux/bitops.h> 11#include <linux/bitops.h>
11#include <linux/percpu.h> 12#include <linux/percpu.h>
13#include <linux/slab.h>
12#include <linux/irq.h> 14#include <linux/irq.h>
13#include <linux/smp.h> 15#include <linux/smp.h>
16#include <linux/of.h>
14 17
15#include <asm/octeon/octeon.h> 18#include <asm/octeon/octeon.h>
16 19
@@ -42,9 +45,9 @@ struct octeon_core_chip_data {
42 45
43static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; 46static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
44 47
45static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, 48static void octeon_irq_set_ciu_mapping(int irq, int line, int bit,
46 struct irq_chip *chip, 49 struct irq_chip *chip,
47 irq_flow_handler_t handler) 50 irq_flow_handler_t handler)
48{ 51{
49 union octeon_ciu_chip_data cd; 52 union octeon_ciu_chip_data cd;
50 53
@@ -505,6 +508,85 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
505 } 508 }
506} 509}
507 510
511static void octeon_irq_gpio_setup(struct irq_data *data)
512{
513 union cvmx_gpio_bit_cfgx cfg;
514 union octeon_ciu_chip_data cd;
515 u32 t = irqd_get_trigger_type(data);
516
517 cd.p = irq_data_get_irq_chip_data(data);
518
519 cfg.u64 = 0;
520 cfg.s.int_en = 1;
521 cfg.s.int_type = (t & IRQ_TYPE_EDGE_BOTH) != 0;
522 cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0;
523
524 /* 140 nS glitch filter*/
525 cfg.s.fil_cnt = 7;
526 cfg.s.fil_sel = 3;
527
528 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), cfg.u64);
529}
530
531static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data)
532{
533 octeon_irq_gpio_setup(data);
534 octeon_irq_ciu_enable_v2(data);
535}
536
537static void octeon_irq_ciu_enable_gpio(struct irq_data *data)
538{
539 octeon_irq_gpio_setup(data);
540 octeon_irq_ciu_enable(data);
541}
542
543static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t)
544{
545 irqd_set_trigger_type(data, t);
546 octeon_irq_gpio_setup(data);
547
548 return IRQ_SET_MASK_OK;
549}
550
551static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data)
552{
553 union octeon_ciu_chip_data cd;
554
555 cd.p = irq_data_get_irq_chip_data(data);
556 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0);
557
558 octeon_irq_ciu_disable_all_v2(data);
559}
560
561static void octeon_irq_ciu_disable_gpio(struct irq_data *data)
562{
563 union octeon_ciu_chip_data cd;
564
565 cd.p = irq_data_get_irq_chip_data(data);
566 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0);
567
568 octeon_irq_ciu_disable_all(data);
569}
570
571static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
572{
573 union octeon_ciu_chip_data cd;
574 u64 mask;
575
576 cd.p = irq_data_get_irq_chip_data(data);
577 mask = 1ull << (cd.s.bit - 16);
578
579 cvmx_write_csr(CVMX_GPIO_INT_CLR, mask);
580}
581
582static void octeon_irq_handle_gpio(unsigned int irq, struct irq_desc *desc)
583{
584 if (irqd_get_trigger_type(irq_desc_get_irq_data(desc)) & IRQ_TYPE_EDGE_BOTH)
585 handle_edge_irq(irq, desc);
586 else
587 handle_level_irq(irq, desc);
588}
589
508#ifdef CONFIG_SMP 590#ifdef CONFIG_SMP
509 591
510static void octeon_irq_cpu_offline_ciu(struct irq_data *data) 592static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
@@ -650,18 +732,6 @@ static struct irq_chip octeon_irq_chip_ciu_v2 = {
650 .name = "CIU", 732 .name = "CIU",
651 .irq_enable = octeon_irq_ciu_enable_v2, 733 .irq_enable = octeon_irq_ciu_enable_v2,
652 .irq_disable = octeon_irq_ciu_disable_all_v2, 734 .irq_disable = octeon_irq_ciu_disable_all_v2,
653 .irq_mask = octeon_irq_ciu_disable_local_v2,
654 .irq_unmask = octeon_irq_ciu_enable_v2,
655#ifdef CONFIG_SMP
656 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
657 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
658#endif
659};
660
661static struct irq_chip octeon_irq_chip_ciu_edge_v2 = {
662 .name = "CIU-E",
663 .irq_enable = octeon_irq_ciu_enable_v2,
664 .irq_disable = octeon_irq_ciu_disable_all_v2,
665 .irq_ack = octeon_irq_ciu_ack, 735 .irq_ack = octeon_irq_ciu_ack,
666 .irq_mask = octeon_irq_ciu_disable_local_v2, 736 .irq_mask = octeon_irq_ciu_disable_local_v2,
667 .irq_unmask = octeon_irq_ciu_enable_v2, 737 .irq_unmask = octeon_irq_ciu_enable_v2,
@@ -675,19 +745,8 @@ static struct irq_chip octeon_irq_chip_ciu = {
675 .name = "CIU", 745 .name = "CIU",
676 .irq_enable = octeon_irq_ciu_enable, 746 .irq_enable = octeon_irq_ciu_enable,
677 .irq_disable = octeon_irq_ciu_disable_all, 747 .irq_disable = octeon_irq_ciu_disable_all,
678 .irq_mask = octeon_irq_dummy_mask,
679#ifdef CONFIG_SMP
680 .irq_set_affinity = octeon_irq_ciu_set_affinity,
681 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
682#endif
683};
684
685static struct irq_chip octeon_irq_chip_ciu_edge = {
686 .name = "CIU-E",
687 .irq_enable = octeon_irq_ciu_enable,
688 .irq_disable = octeon_irq_ciu_disable_all,
689 .irq_mask = octeon_irq_dummy_mask,
690 .irq_ack = octeon_irq_ciu_ack, 748 .irq_ack = octeon_irq_ciu_ack,
749 .irq_mask = octeon_irq_dummy_mask,
691#ifdef CONFIG_SMP 750#ifdef CONFIG_SMP
692 .irq_set_affinity = octeon_irq_ciu_set_affinity, 751 .irq_set_affinity = octeon_irq_ciu_set_affinity,
693 .irq_cpu_offline = octeon_irq_cpu_offline_ciu, 752 .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
@@ -717,6 +776,33 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = {
717 .flags = IRQCHIP_ONOFFLINE_ENABLED, 776 .flags = IRQCHIP_ONOFFLINE_ENABLED,
718}; 777};
719 778
779static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
780 .name = "CIU-GPIO",
781 .irq_enable = octeon_irq_ciu_enable_gpio_v2,
782 .irq_disable = octeon_irq_ciu_disable_gpio_v2,
783 .irq_ack = octeon_irq_ciu_gpio_ack,
784 .irq_mask = octeon_irq_ciu_disable_local_v2,
785 .irq_unmask = octeon_irq_ciu_enable_v2,
786 .irq_set_type = octeon_irq_ciu_gpio_set_type,
787#ifdef CONFIG_SMP
788 .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
789#endif
790 .flags = IRQCHIP_SET_TYPE_MASKED,
791};
792
793static struct irq_chip octeon_irq_chip_ciu_gpio = {
794 .name = "CIU-GPIO",
795 .irq_enable = octeon_irq_ciu_enable_gpio,
796 .irq_disable = octeon_irq_ciu_disable_gpio,
797 .irq_mask = octeon_irq_dummy_mask,
798 .irq_ack = octeon_irq_ciu_gpio_ack,
799 .irq_set_type = octeon_irq_ciu_gpio_set_type,
800#ifdef CONFIG_SMP
801 .irq_set_affinity = octeon_irq_ciu_set_affinity,
802#endif
803 .flags = IRQCHIP_SET_TYPE_MASKED,
804};
805
720/* 806/*
721 * Watchdog interrupts are special. They are associated with a single 807 * Watchdog interrupts are special. They are associated with a single
722 * core, so we hardwire the affinity to that core. 808 * core, so we hardwire the affinity to that core.
@@ -764,6 +850,178 @@ static struct irq_chip octeon_irq_chip_ciu_wd = {
764 .irq_mask = octeon_irq_dummy_mask, 850 .irq_mask = octeon_irq_dummy_mask,
765}; 851};
766 852
853static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit)
854{
855 bool edge = false;
856
857 if (line == 0)
858 switch (bit) {
859 case 48 ... 49: /* GMX DRP */
860 case 50: /* IPD_DRP */
861 case 52 ... 55: /* Timers */
862 case 58: /* MPI */
863 edge = true;
864 break;
865 default:
866 break;
867 }
868 else /* line == 1 */
869 switch (bit) {
870 case 47: /* PTP */
871 edge = true;
872 break;
873 default:
874 break;
875 }
876 return edge;
877}
878
879struct octeon_irq_gpio_domain_data {
880 unsigned int base_hwirq;
881};
882
883static int octeon_irq_gpio_xlat(struct irq_domain *d,
884 struct device_node *node,
885 const u32 *intspec,
886 unsigned int intsize,
887 unsigned long *out_hwirq,
888 unsigned int *out_type)
889{
890 unsigned int type;
891 unsigned int pin;
892 unsigned int trigger;
893 struct octeon_irq_gpio_domain_data *gpiod;
894
895 if (d->of_node != node)
896 return -EINVAL;
897
898 if (intsize < 2)
899 return -EINVAL;
900
901 pin = intspec[0];
902 if (pin >= 16)
903 return -EINVAL;
904
905 trigger = intspec[1];
906
907 switch (trigger) {
908 case 1:
909 type = IRQ_TYPE_EDGE_RISING;
910 break;
911 case 2:
912 type = IRQ_TYPE_EDGE_FALLING;
913 break;
914 case 4:
915 type = IRQ_TYPE_LEVEL_HIGH;
916 break;
917 case 8:
918 type = IRQ_TYPE_LEVEL_LOW;
919 break;
920 default:
921 pr_err("Error: (%s) Invalid irq trigger specification: %x\n",
922 node->name,
923 trigger);
924 type = IRQ_TYPE_LEVEL_LOW;
925 break;
926 }
927 *out_type = type;
928 gpiod = d->host_data;
929 *out_hwirq = gpiod->base_hwirq + pin;
930
931 return 0;
932}
933
934static int octeon_irq_ciu_xlat(struct irq_domain *d,
935 struct device_node *node,
936 const u32 *intspec,
937 unsigned int intsize,
938 unsigned long *out_hwirq,
939 unsigned int *out_type)
940{
941 unsigned int ciu, bit;
942
943 ciu = intspec[0];
944 bit = intspec[1];
945
946 if (ciu > 1 || bit > 63)
947 return -EINVAL;
948
949 /* These are the GPIO lines */
950 if (ciu == 0 && bit >= 16 && bit < 32)
951 return -EINVAL;
952
953 *out_hwirq = (ciu << 6) | bit;
954 *out_type = 0;
955
956 return 0;
957}
958
959static struct irq_chip *octeon_irq_ciu_chip;
960static struct irq_chip *octeon_irq_gpio_chip;
961
962static bool octeon_irq_virq_in_range(unsigned int virq)
963{
964 /* We cannot let it overflow the mapping array. */
965 if (virq < (1ul << 8 * sizeof(octeon_irq_ciu_to_irq[0][0])))
966 return true;
967
968 WARN_ONCE(true, "virq out of range %u.\n", virq);
969 return false;
970}
971
972static int octeon_irq_ciu_map(struct irq_domain *d,
973 unsigned int virq, irq_hw_number_t hw)
974{
975 unsigned int line = hw >> 6;
976 unsigned int bit = hw & 63;
977
978 if (!octeon_irq_virq_in_range(virq))
979 return -EINVAL;
980
981 if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
982 return -EINVAL;
983
984 if (octeon_irq_ciu_is_edge(line, bit))
985 octeon_irq_set_ciu_mapping(virq, line, bit,
986 octeon_irq_ciu_chip,
987 handle_edge_irq);
988 else
989 octeon_irq_set_ciu_mapping(virq, line, bit,
990 octeon_irq_ciu_chip,
991 handle_level_irq);
992
993 return 0;
994}
995
996static int octeon_irq_gpio_map(struct irq_domain *d,
997 unsigned int virq, irq_hw_number_t hw)
998{
999 unsigned int line = hw >> 6;
1000 unsigned int bit = hw & 63;
1001
1002 if (!octeon_irq_virq_in_range(virq))
1003 return -EINVAL;
1004
1005 if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
1006 return -EINVAL;
1007
1008 octeon_irq_set_ciu_mapping(virq, line, bit,
1009 octeon_irq_gpio_chip,
1010 octeon_irq_handle_gpio);
1011
1012 return 0;
1013}
1014
1015static struct irq_domain_ops octeon_irq_domain_ciu_ops = {
1016 .map = octeon_irq_ciu_map,
1017 .xlate = octeon_irq_ciu_xlat,
1018};
1019
1020static struct irq_domain_ops octeon_irq_domain_gpio_ops = {
1021 .map = octeon_irq_gpio_map,
1022 .xlate = octeon_irq_gpio_xlat,
1023};
1024
767static void octeon_irq_ip2_v1(void) 1025static void octeon_irq_ip2_v1(void)
768{ 1026{
769 const unsigned long core_id = cvmx_get_core_num(); 1027 const unsigned long core_id = cvmx_get_core_num();
@@ -887,9 +1145,10 @@ static void __init octeon_irq_init_ciu(void)
887{ 1145{
888 unsigned int i; 1146 unsigned int i;
889 struct irq_chip *chip; 1147 struct irq_chip *chip;
890 struct irq_chip *chip_edge;
891 struct irq_chip *chip_mbox; 1148 struct irq_chip *chip_mbox;
892 struct irq_chip *chip_wd; 1149 struct irq_chip *chip_wd;
1150 struct device_node *gpio_node;
1151 struct device_node *ciu_node;
893 1152
894 octeon_irq_init_ciu_percpu(); 1153 octeon_irq_init_ciu_percpu();
895 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; 1154 octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
@@ -901,17 +1160,18 @@ static void __init octeon_irq_init_ciu(void)
901 octeon_irq_ip2 = octeon_irq_ip2_v2; 1160 octeon_irq_ip2 = octeon_irq_ip2_v2;
902 octeon_irq_ip3 = octeon_irq_ip3_v2; 1161 octeon_irq_ip3 = octeon_irq_ip3_v2;
903 chip = &octeon_irq_chip_ciu_v2; 1162 chip = &octeon_irq_chip_ciu_v2;
904 chip_edge = &octeon_irq_chip_ciu_edge_v2;
905 chip_mbox = &octeon_irq_chip_ciu_mbox_v2; 1163 chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
906 chip_wd = &octeon_irq_chip_ciu_wd_v2; 1164 chip_wd = &octeon_irq_chip_ciu_wd_v2;
1165 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2;
907 } else { 1166 } else {
908 octeon_irq_ip2 = octeon_irq_ip2_v1; 1167 octeon_irq_ip2 = octeon_irq_ip2_v1;
909 octeon_irq_ip3 = octeon_irq_ip3_v1; 1168 octeon_irq_ip3 = octeon_irq_ip3_v1;
910 chip = &octeon_irq_chip_ciu; 1169 chip = &octeon_irq_chip_ciu;
911 chip_edge = &octeon_irq_chip_ciu_edge;
912 chip_mbox = &octeon_irq_chip_ciu_mbox; 1170 chip_mbox = &octeon_irq_chip_ciu_mbox;
913 chip_wd = &octeon_irq_chip_ciu_wd; 1171 chip_wd = &octeon_irq_chip_ciu_wd;
1172 octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio;
914 } 1173 }
1174 octeon_irq_ciu_chip = chip;
915 octeon_irq_ip4 = octeon_irq_ip4_mask; 1175 octeon_irq_ip4 = octeon_irq_ip4_mask;
916 1176
917 /* Mips internal */ 1177 /* Mips internal */
@@ -920,80 +1180,49 @@ static void __init octeon_irq_init_ciu(void)
920 /* CIU_0 */ 1180 /* CIU_0 */
921 for (i = 0; i < 16; i++) 1181 for (i = 0; i < 16; i++)
922 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); 1182 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq);
923 for (i = 0; i < 16; i++)
924 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq);
925 1183
926 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); 1184 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
927 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); 1185 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
928 1186
929 octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq);
930 octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq);
931
932 for (i = 0; i < 4; i++) 1187 for (i = 0; i < 4; i++)
933 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq); 1188 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq);
934 for (i = 0; i < 4; i++) 1189 for (i = 0; i < 4; i++)
935 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq); 1190 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq);
936 1191
937 octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq);
938 octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); 1192 octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq);
939 octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq);
940
941 for (i = 0; i < 2; i++)
942 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq);
943
944 octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq);
945 octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq);
946
947 for (i = 0; i < 4; i++) 1193 for (i = 0; i < 4; i++)
948 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq); 1194 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip, handle_edge_irq);
949 1195
950 octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); 1196 octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq);
951 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq);
952 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq);
953 octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq);
954 octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq);
955 octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq);
956 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq);
957 octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); 1197 octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq);
958 1198
959 /* CIU_1 */ 1199 /* CIU_1 */
960 for (i = 0; i < 16; i++) 1200 for (i = 0; i < 16; i++)
961 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); 1201 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq);
962 1202
963 octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq);
964 octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); 1203 octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq);
965 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq); 1204
966 octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq); 1205 gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio");
967 octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq); 1206 if (gpio_node) {
968 octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq); 1207 struct octeon_irq_gpio_domain_data *gpiod;
969 octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq); 1208
970 octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq); 1209 gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL);
971 octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq); 1210 if (gpiod) {
972 octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq); 1211 /* gpio domain host_data is the base hwirq number. */
973 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq); 1212 gpiod->base_hwirq = 16;
974 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq); 1213 irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod);
975 octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq); 1214 of_node_put(gpio_node);
976 octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq); 1215 } else
977 octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq); 1216 pr_warn("Cannot allocate memory for GPIO irq_domain.\n");
978 octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq); 1217 } else
979 octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq); 1218 pr_warn("Cannot find device node for cavium,octeon-3860-gpio.\n");
980 octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq); 1219
981 octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq); 1220 ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu");
982 octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq); 1221 if (ciu_node) {
983 1222 irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL);
984 octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq); 1223 of_node_put(ciu_node);
985 1224 } else
986 octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq); 1225 pr_warn("Cannot find device node for cavium,octeon-3860-ciu.\n");
987
988 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq);
989
990 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq);
991 octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq);
992 octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq);
993 octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq);
994 octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq);
995 octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq);
996 octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq);
997 1226
998 /* Enable the CIU lines */ 1227 /* Enable the CIU lines */
999 set_c0_status(STATUSF_IP3 | STATUSF_IP2); 1228 set_c0_status(STATUSF_IP3 | STATUSF_IP2);
diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S
index 88e0cddca205..db478dbb9c7b 100644
--- a/arch/mips/cavium-octeon/octeon-memcpy.S
+++ b/arch/mips/cavium-octeon/octeon-memcpy.S
@@ -164,6 +164,14 @@
164 .set noat 164 .set noat
165 165
166/* 166/*
167 * t7 is used as a flag to note inatomic mode.
168 */
169LEAF(__copy_user_inatomic)
170 b __copy_user_common
171 li t7, 1
172 END(__copy_user_inatomic)
173
174/*
167 * A combined memcpy/__copy_user 175 * A combined memcpy/__copy_user
168 * __copy_user sets len to 0 for success; else to an upper bound of 176 * __copy_user sets len to 0 for success; else to an upper bound of
169 * the number of uncopied bytes. 177 * the number of uncopied bytes.
@@ -174,6 +182,8 @@ LEAF(memcpy) /* a0=dst a1=src a2=len */
174 move v0, dst /* return value */ 182 move v0, dst /* return value */
175__memcpy: 183__memcpy:
176FEXPORT(__copy_user) 184FEXPORT(__copy_user)
185 li t7, 0 /* not inatomic */
186__copy_user_common:
177 /* 187 /*
178 * Note: dst & src may be unaligned, len may be 0 188 * Note: dst & src may be unaligned, len may be 0
179 * Temps 189 * Temps
@@ -412,7 +422,6 @@ l_exc_copy:
412 * Assumes src < THREAD_BUADDR($28) 422 * Assumes src < THREAD_BUADDR($28)
413 */ 423 */
414 LOAD t0, TI_TASK($28) 424 LOAD t0, TI_TASK($28)
415 nop
416 LOAD t0, THREAD_BUADDR(t0) 425 LOAD t0, THREAD_BUADDR(t0)
4171: 4261:
418EXC( lb t1, 0(src), l_exc) 427EXC( lb t1, 0(src), l_exc)
@@ -422,10 +431,9 @@ EXC( lb t1, 0(src), l_exc)
422 ADD dst, dst, 1 431 ADD dst, dst, 1
423l_exc: 432l_exc:
424 LOAD t0, TI_TASK($28) 433 LOAD t0, TI_TASK($28)
425 nop
426 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address 434 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
427 nop
428 SUB len, AT, t0 # len number of uncopied bytes 435 SUB len, AT, t0 # len number of uncopied bytes
436 bnez t7, 2f /* Skip the zeroing out part if inatomic */
429 /* 437 /*
430 * Here's where we rely on src and dst being incremented in tandem, 438 * Here's where we rely on src and dst being incremented in tandem,
431 * See (3) above. 439 * See (3) above.
@@ -443,7 +451,7 @@ l_exc:
443 ADD dst, dst, 1 451 ADD dst, dst, 1
444 bnez src, 1b 452 bnez src, 1b
445 SUB src, src, 1 453 SUB src, src, 1
446 jr ra 4542: jr ra
447 nop 455 nop
448 456
449 457
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index cd61d7281d91..0938df10a71c 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2004-2010 Cavium Networks 6 * Copyright (C) 2004-2011 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems 7 * Copyright (C) 2008 Wind River Systems
8 */ 8 */
9 9
@@ -13,10 +13,16 @@
13#include <linux/usb.h> 13#include <linux/usb.h>
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/slab.h>
16#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/of_platform.h>
19#include <linux/of_fdt.h>
20#include <linux/libfdt.h>
17 21
18#include <asm/octeon/octeon.h> 22#include <asm/octeon/octeon.h>
19#include <asm/octeon/cvmx-rnm-defs.h> 23#include <asm/octeon/cvmx-rnm-defs.h>
24#include <asm/octeon/cvmx-helper.h>
25#include <asm/octeon/cvmx-helper-board.h>
20 26
21static struct octeon_cf_data octeon_cf_data; 27static struct octeon_cf_data octeon_cf_data;
22 28
@@ -162,182 +168,6 @@ out:
162} 168}
163device_initcall(octeon_rng_device_init); 169device_initcall(octeon_rng_device_init);
164 170
165static struct i2c_board_info __initdata octeon_i2c_devices[] = {
166 {
167 I2C_BOARD_INFO("ds1337", 0x68),
168 },
169};
170
171static int __init octeon_i2c_devices_init(void)
172{
173 return i2c_register_board_info(0, octeon_i2c_devices,
174 ARRAY_SIZE(octeon_i2c_devices));
175}
176arch_initcall(octeon_i2c_devices_init);
177
178#define OCTEON_I2C_IO_BASE 0x1180000001000ull
179#define OCTEON_I2C_IO_UNIT_OFFSET 0x200
180
181static struct octeon_i2c_data octeon_i2c_data[2];
182
183static int __init octeon_i2c_device_init(void)
184{
185 struct platform_device *pd;
186 int ret = 0;
187 int port, num_ports;
188
189 struct resource i2c_resources[] = {
190 {
191 .flags = IORESOURCE_MEM,
192 }, {
193 .flags = IORESOURCE_IRQ,
194 }
195 };
196
197 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
198 num_ports = 2;
199 else
200 num_ports = 1;
201
202 for (port = 0; port < num_ports; port++) {
203 octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate();
204 /*FIXME: should be examined. At the moment is set for 100Khz */
205 octeon_i2c_data[port].i2c_freq = 100000;
206
207 pd = platform_device_alloc("i2c-octeon", port);
208 if (!pd) {
209 ret = -ENOMEM;
210 goto out;
211 }
212
213 pd->dev.platform_data = octeon_i2c_data + port;
214
215 i2c_resources[0].start =
216 OCTEON_I2C_IO_BASE + (port * OCTEON_I2C_IO_UNIT_OFFSET);
217 i2c_resources[0].end = i2c_resources[0].start + 0x1f;
218 switch (port) {
219 case 0:
220 i2c_resources[1].start = OCTEON_IRQ_TWSI;
221 i2c_resources[1].end = OCTEON_IRQ_TWSI;
222 break;
223 case 1:
224 i2c_resources[1].start = OCTEON_IRQ_TWSI2;
225 i2c_resources[1].end = OCTEON_IRQ_TWSI2;
226 break;
227 default:
228 BUG();
229 }
230
231 ret = platform_device_add_resources(pd,
232 i2c_resources,
233 ARRAY_SIZE(i2c_resources));
234 if (ret)
235 goto fail;
236
237 ret = platform_device_add(pd);
238 if (ret)
239 goto fail;
240 }
241 return ret;
242fail:
243 platform_device_put(pd);
244out:
245 return ret;
246}
247device_initcall(octeon_i2c_device_init);
248
249/* Octeon SMI/MDIO interface. */
250static int __init octeon_mdiobus_device_init(void)
251{
252 struct platform_device *pd;
253 int ret = 0;
254
255 if (octeon_is_simulation())
256 return 0; /* No mdio in the simulator. */
257
258 /* The bus number is the platform_device id. */
259 pd = platform_device_alloc("mdio-octeon", 0);
260 if (!pd) {
261 ret = -ENOMEM;
262 goto out;
263 }
264
265 ret = platform_device_add(pd);
266 if (ret)
267 goto fail;
268
269 return ret;
270fail:
271 platform_device_put(pd);
272
273out:
274 return ret;
275
276}
277device_initcall(octeon_mdiobus_device_init);
278
279/* Octeon mgmt port Ethernet interface. */
280static int __init octeon_mgmt_device_init(void)
281{
282 struct platform_device *pd;
283 int ret = 0;
284 int port, num_ports;
285
286 struct resource mgmt_port_resource = {
287 .flags = IORESOURCE_IRQ,
288 .start = -1,
289 .end = -1
290 };
291
292 if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX))
293 return 0;
294
295 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
296 num_ports = 1;
297 else
298 num_ports = 2;
299
300 for (port = 0; port < num_ports; port++) {
301 pd = platform_device_alloc("octeon_mgmt", port);
302 if (!pd) {
303 ret = -ENOMEM;
304 goto out;
305 }
306 /* No DMA restrictions */
307 pd->dev.coherent_dma_mask = DMA_BIT_MASK(64);
308 pd->dev.dma_mask = &pd->dev.coherent_dma_mask;
309
310 switch (port) {
311 case 0:
312 mgmt_port_resource.start = OCTEON_IRQ_MII0;
313 break;
314 case 1:
315 mgmt_port_resource.start = OCTEON_IRQ_MII1;
316 break;
317 default:
318 BUG();
319 }
320 mgmt_port_resource.end = mgmt_port_resource.start;
321
322 ret = platform_device_add_resources(pd, &mgmt_port_resource, 1);
323
324 if (ret)
325 goto fail;
326
327 ret = platform_device_add(pd);
328 if (ret)
329 goto fail;
330 }
331 return ret;
332fail:
333 platform_device_put(pd);
334
335out:
336 return ret;
337
338}
339device_initcall(octeon_mgmt_device_init);
340
341#ifdef CONFIG_USB 171#ifdef CONFIG_USB
342 172
343static int __init octeon_ehci_device_init(void) 173static int __init octeon_ehci_device_init(void)
@@ -440,6 +270,521 @@ device_initcall(octeon_ohci_device_init);
440 270
441#endif /* CONFIG_USB */ 271#endif /* CONFIG_USB */
442 272
273static struct of_device_id __initdata octeon_ids[] = {
274 { .compatible = "simple-bus", },
275 { .compatible = "cavium,octeon-6335-uctl", },
276 { .compatible = "cavium,octeon-3860-bootbus", },
277 { .compatible = "cavium,mdio-mux", },
278 { .compatible = "gpio-leds", },
279 {},
280};
281
282static bool __init octeon_has_88e1145(void)
283{
284 return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
285 !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
286 !OCTEON_IS_MODEL(OCTEON_CN56XX);
287}
288
289static void __init octeon_fdt_set_phy(int eth, int phy_addr)
290{
291 const __be32 *phy_handle;
292 const __be32 *alt_phy_handle;
293 const __be32 *reg;
294 u32 phandle;
295 int phy;
296 int alt_phy;
297 const char *p;
298 int current_len;
299 char new_name[20];
300
301 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
302 if (!phy_handle)
303 return;
304
305 phandle = be32_to_cpup(phy_handle);
306 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
307
308 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
309 if (alt_phy_handle) {
310 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
311 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
312 } else {
313 alt_phy = -1;
314 }
315
316 if (phy_addr < 0 || phy < 0) {
317 /* Delete the PHY things */
318 fdt_nop_property(initial_boot_params, eth, "phy-handle");
319 /* This one may fail */
320 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
321 if (phy >= 0)
322 fdt_nop_node(initial_boot_params, phy);
323 if (alt_phy >= 0)
324 fdt_nop_node(initial_boot_params, alt_phy);
325 return;
326 }
327
328 if (phy_addr >= 256 && alt_phy > 0) {
329 const struct fdt_property *phy_prop;
330 struct fdt_property *alt_prop;
331 u32 phy_handle_name;
332
333 /* Use the alt phy node instead.*/
334 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
335 phy_handle_name = phy_prop->nameoff;
336 fdt_nop_node(initial_boot_params, phy);
337 fdt_nop_property(initial_boot_params, eth, "phy-handle");
338 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
339 alt_prop->nameoff = phy_handle_name;
340 phy = alt_phy;
341 }
342
343 phy_addr &= 0xff;
344
345 if (octeon_has_88e1145()) {
346 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
347 memset(new_name, 0, sizeof(new_name));
348 strcpy(new_name, "marvell,88e1145");
349 p = fdt_getprop(initial_boot_params, phy, "compatible",
350 &current_len);
351 if (p && current_len >= strlen(new_name))
352 fdt_setprop_inplace(initial_boot_params, phy,
353 "compatible", new_name, current_len);
354 }
355
356 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
357 if (phy_addr == be32_to_cpup(reg))
358 return;
359
360 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
361
362 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
363
364 p = fdt_get_name(initial_boot_params, phy, &current_len);
365 if (p && current_len == strlen(new_name))
366 fdt_set_name(initial_boot_params, phy, new_name);
367 else
368 pr_err("Error: could not rename ethernet phy: <%s>", p);
369}
370
371static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
372{
373 u8 new_mac[6];
374 u64 mac = *pmac;
375 int r;
376
377 new_mac[0] = (mac >> 40) & 0xff;
378 new_mac[1] = (mac >> 32) & 0xff;
379 new_mac[2] = (mac >> 24) & 0xff;
380 new_mac[3] = (mac >> 16) & 0xff;
381 new_mac[4] = (mac >> 8) & 0xff;
382 new_mac[5] = mac & 0xff;
383
384 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
385 new_mac, sizeof(new_mac));
386
387 if (r) {
388 pr_err("Setting \"local-mac-address\" failed %d", r);
389 return;
390 }
391 *pmac = mac + 1;
392}
393
394static void __init octeon_fdt_rm_ethernet(int node)
395{
396 const __be32 *phy_handle;
397
398 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
399 if (phy_handle) {
400 u32 ph = be32_to_cpup(phy_handle);
401 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
402 if (p >= 0)
403 fdt_nop_node(initial_boot_params, p);
404 }
405 fdt_nop_node(initial_boot_params, node);
406}
407
408static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac)
409{
410 char name_buffer[20];
411 int eth;
412 int phy_addr;
413 int ipd_port;
414
415 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
416 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
417 if (eth < 0)
418 return;
419 if (p > max) {
420 pr_debug("Deleting port %x:%x\n", i, p);
421 octeon_fdt_rm_ethernet(eth);
422 return;
423 }
424 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
425 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
426 else
427 ipd_port = 16 * i + p;
428
429 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
430 octeon_fdt_set_phy(eth, phy_addr);
431 octeon_fdt_set_mac_addr(eth, pmac);
432}
433
434static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
435{
436 char name_buffer[20];
437 int iface;
438 int p;
439 int count;
440
441 count = cvmx_helper_interface_enumerate(idx);
442
443 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
444 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
445 if (iface < 0)
446 return;
447
448 for (p = 0; p < 16; p++)
449 octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
450}
451
452int __init octeon_prune_device_tree(void)
453{
454 int i, max_port, uart_mask;
455 const char *pip_path;
456 const char *alias_prop;
457 char name_buffer[20];
458 int aliases;
459 u64 mac_addr_base;
460
461 if (fdt_check_header(initial_boot_params))
462 panic("Corrupt Device Tree.");
463
464 aliases = fdt_path_offset(initial_boot_params, "/aliases");
465 if (aliases < 0) {
466 pr_err("Error: No /aliases node in device tree.");
467 return -EINVAL;
468 }
469
470
471 mac_addr_base =
472 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
473 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
474 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
475 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
476 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
477 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
478
479 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
480 max_port = 2;
481 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
482 max_port = 1;
483 else
484 max_port = 0;
485
486 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
487 max_port = 0;
488
489 for (i = 0; i < 2; i++) {
490 int mgmt;
491 snprintf(name_buffer, sizeof(name_buffer),
492 "mix%d", i);
493 alias_prop = fdt_getprop(initial_boot_params, aliases,
494 name_buffer, NULL);
495 if (alias_prop) {
496 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
497 if (mgmt < 0)
498 continue;
499 if (i >= max_port) {
500 pr_debug("Deleting mix%d\n", i);
501 octeon_fdt_rm_ethernet(mgmt);
502 fdt_nop_property(initial_boot_params, aliases,
503 name_buffer);
504 } else {
505 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
506 octeon_fdt_set_phy(mgmt, phy_addr);
507 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
508 }
509 }
510 }
511
512 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
513 if (pip_path) {
514 int pip = fdt_path_offset(initial_boot_params, pip_path);
515 if (pip >= 0)
516 for (i = 0; i <= 4; i++)
517 octeon_fdt_pip_iface(pip, i, &mac_addr_base);
518 }
519
520 /* I2C */
521 if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
522 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
523 OCTEON_IS_MODEL(OCTEON_CN68XX) ||
524 OCTEON_IS_MODEL(OCTEON_CN56XX))
525 max_port = 2;
526 else
527 max_port = 1;
528
529 for (i = 0; i < 2; i++) {
530 int i2c;
531 snprintf(name_buffer, sizeof(name_buffer),
532 "twsi%d", i);
533 alias_prop = fdt_getprop(initial_boot_params, aliases,
534 name_buffer, NULL);
535
536 if (alias_prop) {
537 i2c = fdt_path_offset(initial_boot_params, alias_prop);
538 if (i2c < 0)
539 continue;
540 if (i >= max_port) {
541 pr_debug("Deleting twsi%d\n", i);
542 fdt_nop_node(initial_boot_params, i2c);
543 fdt_nop_property(initial_boot_params, aliases,
544 name_buffer);
545 }
546 }
547 }
548
549 /* SMI/MDIO */
550 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
551 max_port = 4;
552 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
553 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
554 OCTEON_IS_MODEL(OCTEON_CN56XX))
555 max_port = 2;
556 else
557 max_port = 1;
558
559 for (i = 0; i < 2; i++) {
560 int i2c;
561 snprintf(name_buffer, sizeof(name_buffer),
562 "smi%d", i);
563 alias_prop = fdt_getprop(initial_boot_params, aliases,
564 name_buffer, NULL);
565
566 if (alias_prop) {
567 i2c = fdt_path_offset(initial_boot_params, alias_prop);
568 if (i2c < 0)
569 continue;
570 if (i >= max_port) {
571 pr_debug("Deleting smi%d\n", i);
572 fdt_nop_node(initial_boot_params, i2c);
573 fdt_nop_property(initial_boot_params, aliases,
574 name_buffer);
575 }
576 }
577 }
578
579 /* Serial */
580 uart_mask = 3;
581
582 /* Right now CN52XX is the only chip with a third uart */
583 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
584 uart_mask |= 4; /* uart2 */
585
586 for (i = 0; i < 3; i++) {
587 int uart;
588 snprintf(name_buffer, sizeof(name_buffer),
589 "uart%d", i);
590 alias_prop = fdt_getprop(initial_boot_params, aliases,
591 name_buffer, NULL);
592
593 if (alias_prop) {
594 uart = fdt_path_offset(initial_boot_params, alias_prop);
595 if (uart_mask & (1 << i))
596 continue;
597 pr_debug("Deleting uart%d\n", i);
598 fdt_nop_node(initial_boot_params, uart);
599 fdt_nop_property(initial_boot_params, aliases,
600 name_buffer);
601 }
602 }
603
604 /* Compact Flash */
605 alias_prop = fdt_getprop(initial_boot_params, aliases,
606 "cf0", NULL);
607 if (alias_prop) {
608 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
609 unsigned long base_ptr, region_base, region_size;
610 unsigned long region1_base = 0;
611 unsigned long region1_size = 0;
612 int cs, bootbus;
613 bool is_16bit = false;
614 bool is_true_ide = false;
615 __be32 new_reg[6];
616 __be32 *ranges;
617 int len;
618
619 int cf = fdt_path_offset(initial_boot_params, alias_prop);
620 base_ptr = 0;
621 if (octeon_bootinfo->major_version == 1
622 && octeon_bootinfo->minor_version >= 1) {
623 if (octeon_bootinfo->compact_flash_common_base_addr)
624 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
625 } else {
626 base_ptr = 0x1d000800;
627 }
628
629 if (!base_ptr)
630 goto no_cf;
631
632 /* Find CS0 region. */
633 for (cs = 0; cs < 8; cs++) {
634 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
635 region_base = mio_boot_reg_cfg.s.base << 16;
636 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
637 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
638 && base_ptr < region_base + region_size) {
639 is_16bit = mio_boot_reg_cfg.s.width;
640 break;
641 }
642 }
643 if (cs >= 7) {
644 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
645 goto no_cf;
646 }
647
648 if (!(base_ptr & 0xfffful)) {
649 /*
650 * Boot loader signals availability of DMA (true_ide
651 * mode) by setting low order bits of base_ptr to
652 * zero.
653 */
654
655 /* Asume that CS1 immediately follows. */
656 mio_boot_reg_cfg.u64 =
657 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
658 region1_base = mio_boot_reg_cfg.s.base << 16;
659 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
660 if (!mio_boot_reg_cfg.s.en)
661 goto no_cf;
662 is_true_ide = true;
663
664 } else {
665 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
666 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
667 if (!is_16bit) {
668 __be32 width = cpu_to_be32(8);
669 fdt_setprop_inplace(initial_boot_params, cf,
670 "cavium,bus-width", &width, sizeof(width));
671 }
672 }
673 new_reg[0] = cpu_to_be32(cs);
674 new_reg[1] = cpu_to_be32(0);
675 new_reg[2] = cpu_to_be32(0x10000);
676 new_reg[3] = cpu_to_be32(cs + 1);
677 new_reg[4] = cpu_to_be32(0);
678 new_reg[5] = cpu_to_be32(0x10000);
679 fdt_setprop_inplace(initial_boot_params, cf,
680 "reg", new_reg, sizeof(new_reg));
681
682 bootbus = fdt_parent_offset(initial_boot_params, cf);
683 if (bootbus < 0)
684 goto no_cf;
685 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
686 if (!ranges || len < (5 * 8 * sizeof(__be32)))
687 goto no_cf;
688
689 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
690 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
691 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
692 if (is_true_ide) {
693 cs++;
694 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
695 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
696 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
697 }
698 goto end_cf;
699no_cf:
700 fdt_nop_node(initial_boot_params, cf);
701
702end_cf:
703 ;
704 }
705
706 /* 8 char LED */
707 alias_prop = fdt_getprop(initial_boot_params, aliases,
708 "led0", NULL);
709 if (alias_prop) {
710 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
711 unsigned long base_ptr, region_base, region_size;
712 int cs, bootbus;
713 __be32 new_reg[6];
714 __be32 *ranges;
715 int len;
716 int led = fdt_path_offset(initial_boot_params, alias_prop);
717
718 base_ptr = octeon_bootinfo->led_display_base_addr;
719 if (base_ptr == 0)
720 goto no_led;
721 /* Find CS0 region. */
722 for (cs = 0; cs < 8; cs++) {
723 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
724 region_base = mio_boot_reg_cfg.s.base << 16;
725 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
726 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
727 && base_ptr < region_base + region_size)
728 break;
729 }
730
731 if (cs > 7)
732 goto no_led;
733
734 new_reg[0] = cpu_to_be32(cs);
735 new_reg[1] = cpu_to_be32(0x20);
736 new_reg[2] = cpu_to_be32(0x20);
737 new_reg[3] = cpu_to_be32(cs);
738 new_reg[4] = cpu_to_be32(0);
739 new_reg[5] = cpu_to_be32(0x20);
740 fdt_setprop_inplace(initial_boot_params, led,
741 "reg", new_reg, sizeof(new_reg));
742
743 bootbus = fdt_parent_offset(initial_boot_params, led);
744 if (bootbus < 0)
745 goto no_led;
746 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
747 if (!ranges || len < (5 * 8 * sizeof(__be32)))
748 goto no_led;
749
750 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
751 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
752 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
753 goto end_led;
754
755no_led:
756 fdt_nop_node(initial_boot_params, led);
757end_led:
758 ;
759 }
760
761 /* OHCI/UHCI USB */
762 alias_prop = fdt_getprop(initial_boot_params, aliases,
763 "uctl", NULL);
764 if (alias_prop) {
765 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
766
767 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
768 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
769 pr_debug("Deleting uctl\n");
770 fdt_nop_node(initial_boot_params, uctl);
771 fdt_nop_property(initial_boot_params, aliases, "uctl");
772 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
773 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
774 /* Missing "refclk-type" defaults to crystal. */
775 fdt_nop_property(initial_boot_params, uctl, "refclk-type");
776 }
777 }
778
779 return 0;
780}
781
782static int __init octeon_publish_devices(void)
783{
784 return of_platform_bus_probe(NULL, octeon_ids, NULL);
785}
786device_initcall(octeon_publish_devices);
787
443MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>"); 788MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
444MODULE_LICENSE("GPL"); 789MODULE_LICENSE("GPL");
445MODULE_DESCRIPTION("Platform driver for Octeon SOC"); 790MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts
new file mode 100644
index 000000000000..f28b2d0fde22
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon_3xxx.dts
@@ -0,0 +1,571 @@
1/dts-v1/;
2/*
3 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
4 *
5 * This device tree is pruned and patched by early boot code before
6 * use. Because of this, it contains a super-set of the available
7 * devices and properties.
8 */
9/ {
10 compatible = "cavium,octeon-3860";
11 #address-cells = <2>;
12 #size-cells = <2>;
13 interrupt-parent = <&ciu>;
14
15 soc@0 {
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges; /* Direct mapping */
20
21 ciu: interrupt-controller@1070000000000 {
22 compatible = "cavium,octeon-3860-ciu";
23 interrupt-controller;
24 /* Interrupts are specified by two parts:
25 * 1) Controller register (0 or 1)
26 * 2) Bit within the register (0..63)
27 */
28 #interrupt-cells = <2>;
29 reg = <0x10700 0x00000000 0x0 0x7000>;
30 };
31
32 gpio: gpio-controller@1070000000800 {
33 #gpio-cells = <2>;
34 compatible = "cavium,octeon-3860-gpio";
35 reg = <0x10700 0x00000800 0x0 0x100>;
36 gpio-controller;
37 /* Interrupts are specified by two parts:
38 * 1) GPIO pin number (0..15)
39 * 2) Triggering (1 - edge rising
40 * 2 - edge falling
41 * 4 - level active high
42 * 8 - level active low)
43 */
44 interrupt-controller;
45 #interrupt-cells = <2>;
46 /* The GPIO pin connect to 16 consecutive CUI bits */
47 interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
48 <0 20>, <0 21>, <0 22>, <0 23>,
49 <0 24>, <0 25>, <0 26>, <0 27>,
50 <0 28>, <0 29>, <0 30>, <0 31>;
51 };
52
53 smi0: mdio@1180000001800 {
54 compatible = "cavium,octeon-3860-mdio";
55 #address-cells = <1>;
56 #size-cells = <0>;
57 reg = <0x11800 0x00001800 0x0 0x40>;
58
59 phy0: ethernet-phy@0 {
60 compatible = "marvell,88e1118";
61 marvell,reg-init =
62 /* Fix rx and tx clock transition timing */
63 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
64 /* Adjust LED drive. */
65 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
66 /* irq, blink-activity, blink-link */
67 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
68 reg = <0>;
69 };
70
71 phy1: ethernet-phy@1 {
72 compatible = "marvell,88e1118";
73 marvell,reg-init =
74 /* Fix rx and tx clock transition timing */
75 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
76 /* Adjust LED drive. */
77 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
78 /* irq, blink-activity, blink-link */
79 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
80 reg = <1>;
81 };
82
83 phy2: ethernet-phy@2 {
84 reg = <2>;
85 compatible = "marvell,88e1149r";
86 marvell,reg-init = <3 0x10 0 0x5777>,
87 <3 0x11 0 0x00aa>,
88 <3 0x12 0 0x4105>,
89 <3 0x13 0 0x0a60>;
90 };
91 phy3: ethernet-phy@3 {
92 reg = <3>;
93 compatible = "marvell,88e1149r";
94 marvell,reg-init = <3 0x10 0 0x5777>,
95 <3 0x11 0 0x00aa>,
96 <3 0x12 0 0x4105>,
97 <3 0x13 0 0x0a60>;
98 };
99 phy4: ethernet-phy@4 {
100 reg = <4>;
101 compatible = "marvell,88e1149r";
102 marvell,reg-init = <3 0x10 0 0x5777>,
103 <3 0x11 0 0x00aa>,
104 <3 0x12 0 0x4105>,
105 <3 0x13 0 0x0a60>;
106 };
107 phy5: ethernet-phy@5 {
108 reg = <5>;
109 compatible = "marvell,88e1149r";
110 marvell,reg-init = <3 0x10 0 0x5777>,
111 <3 0x11 0 0x00aa>,
112 <3 0x12 0 0x4105>,
113 <3 0x13 0 0x0a60>;
114 };
115
116 phy6: ethernet-phy@6 {
117 reg = <6>;
118 compatible = "marvell,88e1149r";
119 marvell,reg-init = <3 0x10 0 0x5777>,
120 <3 0x11 0 0x00aa>,
121 <3 0x12 0 0x4105>,
122 <3 0x13 0 0x0a60>;
123 };
124 phy7: ethernet-phy@7 {
125 reg = <7>;
126 compatible = "marvell,88e1149r";
127 marvell,reg-init = <3 0x10 0 0x5777>,
128 <3 0x11 0 0x00aa>,
129 <3 0x12 0 0x4105>,
130 <3 0x13 0 0x0a60>;
131 };
132 phy8: ethernet-phy@8 {
133 reg = <8>;
134 compatible = "marvell,88e1149r";
135 marvell,reg-init = <3 0x10 0 0x5777>,
136 <3 0x11 0 0x00aa>,
137 <3 0x12 0 0x4105>,
138 <3 0x13 0 0x0a60>;
139 };
140 phy9: ethernet-phy@9 {
141 reg = <9>;
142 compatible = "marvell,88e1149r";
143 marvell,reg-init = <3 0x10 0 0x5777>,
144 <3 0x11 0 0x00aa>,
145 <3 0x12 0 0x4105>,
146 <3 0x13 0 0x0a60>;
147 };
148 };
149
150 smi1: mdio@1180000001900 {
151 compatible = "cavium,octeon-3860-mdio";
152 #address-cells = <1>;
153 #size-cells = <0>;
154 reg = <0x11800 0x00001900 0x0 0x40>;
155
156 phy100: ethernet-phy@1 {
157 reg = <1>;
158 compatible = "marvell,88e1149r";
159 marvell,reg-init = <3 0x10 0 0x5777>,
160 <3 0x11 0 0x00aa>,
161 <3 0x12 0 0x4105>,
162 <3 0x13 0 0x0a60>;
163 interrupt-parent = <&gpio>;
164 interrupts = <12 8>; /* Pin 12, active low */
165 };
166 phy101: ethernet-phy@2 {
167 reg = <2>;
168 compatible = "marvell,88e1149r";
169 marvell,reg-init = <3 0x10 0 0x5777>,
170 <3 0x11 0 0x00aa>,
171 <3 0x12 0 0x4105>,
172 <3 0x13 0 0x0a60>;
173 interrupt-parent = <&gpio>;
174 interrupts = <12 8>; /* Pin 12, active low */
175 };
176 phy102: ethernet-phy@3 {
177 reg = <3>;
178 compatible = "marvell,88e1149r";
179 marvell,reg-init = <3 0x10 0 0x5777>,
180 <3 0x11 0 0x00aa>,
181 <3 0x12 0 0x4105>,
182 <3 0x13 0 0x0a60>;
183 interrupt-parent = <&gpio>;
184 interrupts = <12 8>; /* Pin 12, active low */
185 };
186 phy103: ethernet-phy@4 {
187 reg = <4>;
188 compatible = "marvell,88e1149r";
189 marvell,reg-init = <3 0x10 0 0x5777>,
190 <3 0x11 0 0x00aa>,
191 <3 0x12 0 0x4105>,
192 <3 0x13 0 0x0a60>;
193 interrupt-parent = <&gpio>;
194 interrupts = <12 8>; /* Pin 12, active low */
195 };
196 };
197
198 mix0: ethernet@1070000100000 {
199 compatible = "cavium,octeon-5750-mix";
200 reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
201 <0x11800 0xE0000000 0x0 0x300>, /* AGL */
202 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
203 <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */
204 cell-index = <0>;
205 interrupts = <0 62>, <1 46>;
206 local-mac-address = [ 00 00 00 00 00 00 ];
207 phy-handle = <&phy0>;
208 };
209
210 mix1: ethernet@1070000100800 {
211 compatible = "cavium,octeon-5750-mix";
212 reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
213 <0x11800 0xE0000800 0x0 0x300>, /* AGL */
214 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
215 <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */
216 cell-index = <1>;
217 interrupts = <1 18>, < 1 46>;
218 local-mac-address = [ 00 00 00 00 00 00 ];
219 phy-handle = <&phy1>;
220 };
221
222 pip: pip@11800a0000000 {
223 compatible = "cavium,octeon-3860-pip";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 reg = <0x11800 0xa0000000 0x0 0x2000>;
227
228 interface@0 {
229 compatible = "cavium,octeon-3860-pip-interface";
230 #address-cells = <1>;
231 #size-cells = <0>;
232 reg = <0>; /* interface */
233
234 ethernet@0 {
235 compatible = "cavium,octeon-3860-pip-port";
236 reg = <0x0>; /* Port */
237 local-mac-address = [ 00 00 00 00 00 00 ];
238 phy-handle = <&phy2>;
239 cavium,alt-phy-handle = <&phy100>;
240 };
241 ethernet@1 {
242 compatible = "cavium,octeon-3860-pip-port";
243 reg = <0x1>; /* Port */
244 local-mac-address = [ 00 00 00 00 00 00 ];
245 phy-handle = <&phy3>;
246 cavium,alt-phy-handle = <&phy101>;
247 };
248 ethernet@2 {
249 compatible = "cavium,octeon-3860-pip-port";
250 reg = <0x2>; /* Port */
251 local-mac-address = [ 00 00 00 00 00 00 ];
252 phy-handle = <&phy4>;
253 cavium,alt-phy-handle = <&phy102>;
254 };
255 ethernet@3 {
256 compatible = "cavium,octeon-3860-pip-port";
257 reg = <0x3>; /* Port */
258 local-mac-address = [ 00 00 00 00 00 00 ];
259 phy-handle = <&phy5>;
260 cavium,alt-phy-handle = <&phy103>;
261 };
262 ethernet@4 {
263 compatible = "cavium,octeon-3860-pip-port";
264 reg = <0x4>; /* Port */
265 local-mac-address = [ 00 00 00 00 00 00 ];
266 };
267 ethernet@5 {
268 compatible = "cavium,octeon-3860-pip-port";
269 reg = <0x5>; /* Port */
270 local-mac-address = [ 00 00 00 00 00 00 ];
271 };
272 ethernet@6 {
273 compatible = "cavium,octeon-3860-pip-port";
274 reg = <0x6>; /* Port */
275 local-mac-address = [ 00 00 00 00 00 00 ];
276 };
277 ethernet@7 {
278 compatible = "cavium,octeon-3860-pip-port";
279 reg = <0x7>; /* Port */
280 local-mac-address = [ 00 00 00 00 00 00 ];
281 };
282 ethernet@8 {
283 compatible = "cavium,octeon-3860-pip-port";
284 reg = <0x8>; /* Port */
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 };
287 ethernet@9 {
288 compatible = "cavium,octeon-3860-pip-port";
289 reg = <0x9>; /* Port */
290 local-mac-address = [ 00 00 00 00 00 00 ];
291 };
292 ethernet@a {
293 compatible = "cavium,octeon-3860-pip-port";
294 reg = <0xa>; /* Port */
295 local-mac-address = [ 00 00 00 00 00 00 ];
296 };
297 ethernet@b {
298 compatible = "cavium,octeon-3860-pip-port";
299 reg = <0xb>; /* Port */
300 local-mac-address = [ 00 00 00 00 00 00 ];
301 };
302 ethernet@c {
303 compatible = "cavium,octeon-3860-pip-port";
304 reg = <0xc>; /* Port */
305 local-mac-address = [ 00 00 00 00 00 00 ];
306 };
307 ethernet@d {
308 compatible = "cavium,octeon-3860-pip-port";
309 reg = <0xd>; /* Port */
310 local-mac-address = [ 00 00 00 00 00 00 ];
311 };
312 ethernet@e {
313 compatible = "cavium,octeon-3860-pip-port";
314 reg = <0xe>; /* Port */
315 local-mac-address = [ 00 00 00 00 00 00 ];
316 };
317 ethernet@f {
318 compatible = "cavium,octeon-3860-pip-port";
319 reg = <0xf>; /* Port */
320 local-mac-address = [ 00 00 00 00 00 00 ];
321 };
322 };
323
324 interface@1 {
325 compatible = "cavium,octeon-3860-pip-interface";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 reg = <1>; /* interface */
329
330 ethernet@0 {
331 compatible = "cavium,octeon-3860-pip-port";
332 reg = <0x0>; /* Port */
333 local-mac-address = [ 00 00 00 00 00 00 ];
334 phy-handle = <&phy6>;
335 };
336 ethernet@1 {
337 compatible = "cavium,octeon-3860-pip-port";
338 reg = <0x1>; /* Port */
339 local-mac-address = [ 00 00 00 00 00 00 ];
340 phy-handle = <&phy7>;
341 };
342 ethernet@2 {
343 compatible = "cavium,octeon-3860-pip-port";
344 reg = <0x2>; /* Port */
345 local-mac-address = [ 00 00 00 00 00 00 ];
346 phy-handle = <&phy8>;
347 };
348 ethernet@3 {
349 compatible = "cavium,octeon-3860-pip-port";
350 reg = <0x3>; /* Port */
351 local-mac-address = [ 00 00 00 00 00 00 ];
352 phy-handle = <&phy9>;
353 };
354 };
355 };
356
357 twsi0: i2c@1180000001000 {
358 #address-cells = <1>;
359 #size-cells = <0>;
360 compatible = "cavium,octeon-3860-twsi";
361 reg = <0x11800 0x00001000 0x0 0x200>;
362 interrupts = <0 45>;
363 clock-frequency = <100000>;
364
365 rtc@68 {
366 compatible = "dallas,ds1337";
367 reg = <0x68>;
368 };
369 tmp@4c {
370 compatible = "ti,tmp421";
371 reg = <0x4c>;
372 };
373 };
374
375 twsi1: i2c@1180000001200 {
376 #address-cells = <1>;
377 #size-cells = <0>;
378 compatible = "cavium,octeon-3860-twsi";
379 reg = <0x11800 0x00001200 0x0 0x200>;
380 interrupts = <0 59>;
381 clock-frequency = <100000>;
382 };
383
384 uart0: serial@1180000000800 {
385 compatible = "cavium,octeon-3860-uart","ns16550";
386 reg = <0x11800 0x00000800 0x0 0x400>;
387 clock-frequency = <0>;
388 current-speed = <115200>;
389 reg-shift = <3>;
390 interrupts = <0 34>;
391 };
392
393 uart1: serial@1180000000c00 {
394 compatible = "cavium,octeon-3860-uart","ns16550";
395 reg = <0x11800 0x00000c00 0x0 0x400>;
396 clock-frequency = <0>;
397 current-speed = <115200>;
398 reg-shift = <3>;
399 interrupts = <0 35>;
400 };
401
402 uart2: serial@1180000000400 {
403 compatible = "cavium,octeon-3860-uart","ns16550";
404 reg = <0x11800 0x00000400 0x0 0x400>;
405 clock-frequency = <0>;
406 current-speed = <115200>;
407 reg-shift = <3>;
408 interrupts = <1 16>;
409 };
410
411 bootbus: bootbus@1180000000000 {
412 compatible = "cavium,octeon-3860-bootbus";
413 reg = <0x11800 0x00000000 0x0 0x200>;
414 /* The chip select number and offset */
415 #address-cells = <2>;
416 /* The size of the chip select region */
417 #size-cells = <1>;
418 ranges = <0 0 0x0 0x1f400000 0xc00000>,
419 <1 0 0x10000 0x30000000 0>,
420 <2 0 0x10000 0x40000000 0>,
421 <3 0 0x10000 0x50000000 0>,
422 <4 0 0x0 0x1d020000 0x10000>,
423 <5 0 0x0 0x1d040000 0x10000>,
424 <6 0 0x0 0x1d050000 0x10000>,
425 <7 0 0x10000 0x90000000 0>;
426
427 cavium,cs-config@0 {
428 compatible = "cavium,octeon-3860-bootbus-config";
429 cavium,cs-index = <0>;
430 cavium,t-adr = <20>;
431 cavium,t-ce = <60>;
432 cavium,t-oe = <60>;
433 cavium,t-we = <45>;
434 cavium,t-rd-hld = <35>;
435 cavium,t-wr-hld = <45>;
436 cavium,t-pause = <0>;
437 cavium,t-wait = <0>;
438 cavium,t-page = <35>;
439 cavium,t-rd-dly = <0>;
440
441 cavium,pages = <0>;
442 cavium,bus-width = <8>;
443 };
444 cavium,cs-config@4 {
445 compatible = "cavium,octeon-3860-bootbus-config";
446 cavium,cs-index = <4>;
447 cavium,t-adr = <320>;
448 cavium,t-ce = <320>;
449 cavium,t-oe = <320>;
450 cavium,t-we = <320>;
451 cavium,t-rd-hld = <320>;
452 cavium,t-wr-hld = <320>;
453 cavium,t-pause = <320>;
454 cavium,t-wait = <320>;
455 cavium,t-page = <320>;
456 cavium,t-rd-dly = <0>;
457
458 cavium,pages = <0>;
459 cavium,bus-width = <8>;
460 };
461 cavium,cs-config@5 {
462 compatible = "cavium,octeon-3860-bootbus-config";
463 cavium,cs-index = <5>;
464 cavium,t-adr = <5>;
465 cavium,t-ce = <300>;
466 cavium,t-oe = <125>;
467 cavium,t-we = <150>;
468 cavium,t-rd-hld = <100>;
469 cavium,t-wr-hld = <30>;
470 cavium,t-pause = <0>;
471 cavium,t-wait = <30>;
472 cavium,t-page = <320>;
473 cavium,t-rd-dly = <0>;
474
475 cavium,pages = <0>;
476 cavium,bus-width = <16>;
477 };
478 cavium,cs-config@6 {
479 compatible = "cavium,octeon-3860-bootbus-config";
480 cavium,cs-index = <6>;
481 cavium,t-adr = <5>;
482 cavium,t-ce = <300>;
483 cavium,t-oe = <270>;
484 cavium,t-we = <150>;
485 cavium,t-rd-hld = <100>;
486 cavium,t-wr-hld = <70>;
487 cavium,t-pause = <0>;
488 cavium,t-wait = <0>;
489 cavium,t-page = <320>;
490 cavium,t-rd-dly = <0>;
491
492 cavium,pages = <0>;
493 cavium,wait-mode;
494 cavium,bus-width = <16>;
495 };
496
497 flash0: nor@0,0 {
498 compatible = "cfi-flash";
499 reg = <0 0 0x800000>;
500 #address-cells = <1>;
501 #size-cells = <1>;
502 };
503
504 led0: led-display@4,0 {
505 compatible = "avago,hdsp-253x";
506 reg = <4 0x20 0x20>, <4 0 0x20>;
507 };
508
509 cf0: compact-flash@5,0 {
510 compatible = "cavium,ebt3000-compact-flash";
511 reg = <5 0 0x10000>, <6 0 0x10000>;
512 cavium,bus-width = <16>;
513 cavium,true-ide;
514 cavium,dma-engine-handle = <&dma0>;
515 };
516 };
517
518 dma0: dma-engine@1180000000100 {
519 compatible = "cavium,octeon-5750-bootbus-dma";
520 reg = <0x11800 0x00000100 0x0 0x8>;
521 interrupts = <0 63>;
522 };
523 dma1: dma-engine@1180000000108 {
524 compatible = "cavium,octeon-5750-bootbus-dma";
525 reg = <0x11800 0x00000108 0x0 0x8>;
526 interrupts = <0 63>;
527 };
528
529 uctl: uctl@118006f000000 {
530 compatible = "cavium,octeon-6335-uctl";
531 reg = <0x11800 0x6f000000 0x0 0x100>;
532 ranges; /* Direct mapping */
533 #address-cells = <2>;
534 #size-cells = <2>;
535 /* 12MHz, 24MHz and 48MHz allowed */
536 refclk-frequency = <12000000>;
537 /* Either "crystal" or "external" */
538 refclk-type = "crystal";
539
540 ehci@16f0000000000 {
541 compatible = "cavium,octeon-6335-ehci","usb-ehci";
542 reg = <0x16f00 0x00000000 0x0 0x100>;
543 interrupts = <0 56>;
544 big-endian-regs;
545 };
546 ohci@16f0000000400 {
547 compatible = "cavium,octeon-6335-ohci","usb-ohci";
548 reg = <0x16f00 0x00000400 0x0 0x100>;
549 interrupts = <0 56>;
550 big-endian-regs;
551 };
552 };
553 };
554
555 aliases {
556 mix0 = &mix0;
557 mix1 = &mix1;
558 pip = &pip;
559 smi0 = &smi0;
560 smi1 = &smi1;
561 twsi0 = &twsi0;
562 twsi1 = &twsi1;
563 uart0 = &uart0;
564 uart1 = &uart1;
565 uart2 = &uart2;
566 flash0 = &flash0;
567 cf0 = &cf0;
568 uctl = &uctl;
569 led0 = &led0;
570 };
571 };
diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts
new file mode 100644
index 000000000000..1839468932b6
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon_68xx.dts
@@ -0,0 +1,625 @@
1/dts-v1/;
2/*
3 * OCTEON 68XX device tree skeleton.
4 *
5 * This device tree is pruned and patched by early boot code before
6 * use. Because of this, it contains a super-set of the available
7 * devices and properties.
8 */
9/ {
10 compatible = "cavium,octeon-6880";
11 #address-cells = <2>;
12 #size-cells = <2>;
13 interrupt-parent = <&ciu2>;
14
15 soc@0 {
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges; /* Direct mapping */
20
21 ciu2: interrupt-controller@1070100000000 {
22 compatible = "cavium,octeon-6880-ciu2";
23 interrupt-controller;
24 /* Interrupts are specified by two parts:
25 * 1) Controller register (0 or 7)
26 * 2) Bit within the register (0..63)
27 */
28 #address-cells = <0>;
29 #interrupt-cells = <2>;
30 reg = <0x10701 0x00000000 0x0 0x4000000>;
31 };
32
33 gpio: gpio-controller@1070000000800 {
34 #gpio-cells = <2>;
35 compatible = "cavium,octeon-3860-gpio";
36 reg = <0x10700 0x00000800 0x0 0x100>;
37 gpio-controller;
38 /* Interrupts are specified by two parts:
39 * 1) GPIO pin number (0..15)
40 * 2) Triggering (1 - edge rising
41 * 2 - edge falling
42 * 4 - level active high
43 * 8 - level active low)
44 */
45 interrupt-controller;
46 #interrupt-cells = <2>;
47 /* The GPIO pins connect to 16 consecutive CUI bits */
48 interrupts = <7 0>, <7 1>, <7 2>, <7 3>,
49 <7 4>, <7 5>, <7 6>, <7 7>,
50 <7 8>, <7 9>, <7 10>, <7 11>,
51 <7 12>, <7 13>, <7 14>, <7 15>;
52 };
53
54 smi0: mdio@1180000003800 {
55 compatible = "cavium,octeon-3860-mdio";
56 #address-cells = <1>;
57 #size-cells = <0>;
58 reg = <0x11800 0x00003800 0x0 0x40>;
59
60 phy0: ethernet-phy@6 {
61 compatible = "marvell,88e1118";
62 marvell,reg-init =
63 /* Fix rx and tx clock transition timing */
64 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
65 /* Adjust LED drive. */
66 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
67 /* irq, blink-activity, blink-link */
68 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
69 reg = <6>;
70 };
71
72 phy1: ethernet-phy@1 {
73 cavium,qlm-trim = "4,sgmii";
74 reg = <1>;
75 compatible = "marvell,88e1149r";
76 marvell,reg-init = <3 0x10 0 0x5777>,
77 <3 0x11 0 0x00aa>,
78 <3 0x12 0 0x4105>,
79 <3 0x13 0 0x0a60>;
80 };
81 phy2: ethernet-phy@2 {
82 cavium,qlm-trim = "4,sgmii";
83 reg = <2>;
84 compatible = "marvell,88e1149r";
85 marvell,reg-init = <3 0x10 0 0x5777>,
86 <3 0x11 0 0x00aa>,
87 <3 0x12 0 0x4105>,
88 <3 0x13 0 0x0a60>;
89 };
90 phy3: ethernet-phy@3 {
91 cavium,qlm-trim = "4,sgmii";
92 reg = <3>;
93 compatible = "marvell,88e1149r";
94 marvell,reg-init = <3 0x10 0 0x5777>,
95 <3 0x11 0 0x00aa>,
96 <3 0x12 0 0x4105>,
97 <3 0x13 0 0x0a60>;
98 };
99 phy4: ethernet-phy@4 {
100 cavium,qlm-trim = "4,sgmii";
101 reg = <4>;
102 compatible = "marvell,88e1149r";
103 marvell,reg-init = <3 0x10 0 0x5777>,
104 <3 0x11 0 0x00aa>,
105 <3 0x12 0 0x4105>,
106 <3 0x13 0 0x0a60>;
107 };
108 };
109
110 smi1: mdio@1180000003880 {
111 compatible = "cavium,octeon-3860-mdio";
112 #address-cells = <1>;
113 #size-cells = <0>;
114 reg = <0x11800 0x00003880 0x0 0x40>;
115
116 phy41: ethernet-phy@1 {
117 cavium,qlm-trim = "0,sgmii";
118 reg = <1>;
119 compatible = "marvell,88e1149r";
120 marvell,reg-init = <3 0x10 0 0x5777>,
121 <3 0x11 0 0x00aa>,
122 <3 0x12 0 0x4105>,
123 <3 0x13 0 0x0a60>;
124 };
125 phy42: ethernet-phy@2 {
126 cavium,qlm-trim = "0,sgmii";
127 reg = <2>;
128 compatible = "marvell,88e1149r";
129 marvell,reg-init = <3 0x10 0 0x5777>,
130 <3 0x11 0 0x00aa>,
131 <3 0x12 0 0x4105>,
132 <3 0x13 0 0x0a60>;
133 };
134 phy43: ethernet-phy@3 {
135 cavium,qlm-trim = "0,sgmii";
136 reg = <3>;
137 compatible = "marvell,88e1149r";
138 marvell,reg-init = <3 0x10 0 0x5777>,
139 <3 0x11 0 0x00aa>,
140 <3 0x12 0 0x4105>,
141 <3 0x13 0 0x0a60>;
142 };
143 phy44: ethernet-phy@4 {
144 cavium,qlm-trim = "0,sgmii";
145 reg = <4>;
146 compatible = "marvell,88e1149r";
147 marvell,reg-init = <3 0x10 0 0x5777>,
148 <3 0x11 0 0x00aa>,
149 <3 0x12 0 0x4105>,
150 <3 0x13 0 0x0a60>;
151 };
152 };
153
154 smi2: mdio@1180000003900 {
155 compatible = "cavium,octeon-3860-mdio";
156 #address-cells = <1>;
157 #size-cells = <0>;
158 reg = <0x11800 0x00003900 0x0 0x40>;
159
160 phy21: ethernet-phy@1 {
161 cavium,qlm-trim = "2,sgmii";
162 reg = <1>;
163 compatible = "marvell,88e1149r";
164 marvell,reg-init = <3 0x10 0 0x5777>,
165 <3 0x11 0 0x00aa>,
166 <3 0x12 0 0x4105>,
167 <3 0x13 0 0x0a60>;
168 };
169 phy22: ethernet-phy@2 {
170 cavium,qlm-trim = "2,sgmii";
171 reg = <2>;
172 compatible = "marvell,88e1149r";
173 marvell,reg-init = <3 0x10 0 0x5777>,
174 <3 0x11 0 0x00aa>,
175 <3 0x12 0 0x4105>,
176 <3 0x13 0 0x0a60>;
177 };
178 phy23: ethernet-phy@3 {
179 cavium,qlm-trim = "2,sgmii";
180 reg = <3>;
181 compatible = "marvell,88e1149r";
182 marvell,reg-init = <3 0x10 0 0x5777>,
183 <3 0x11 0 0x00aa>,
184 <3 0x12 0 0x4105>,
185 <3 0x13 0 0x0a60>;
186 };
187 phy24: ethernet-phy@4 {
188 cavium,qlm-trim = "2,sgmii";
189 reg = <4>;
190 compatible = "marvell,88e1149r";
191 marvell,reg-init = <3 0x10 0 0x5777>,
192 <3 0x11 0 0x00aa>,
193 <3 0x12 0 0x4105>,
194 <3 0x13 0 0x0a60>;
195 };
196 };
197
198 smi3: mdio@1180000003980 {
199 compatible = "cavium,octeon-3860-mdio";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <0x11800 0x00003980 0x0 0x40>;
203
204 phy11: ethernet-phy@1 {
205 cavium,qlm-trim = "3,sgmii";
206 reg = <1>;
207 compatible = "marvell,88e1149r";
208 marvell,reg-init = <3 0x10 0 0x5777>,
209 <3 0x11 0 0x00aa>,
210 <3 0x12 0 0x4105>,
211 <3 0x13 0 0x0a60>;
212 };
213 phy12: ethernet-phy@2 {
214 cavium,qlm-trim = "3,sgmii";
215 reg = <2>;
216 compatible = "marvell,88e1149r";
217 marvell,reg-init = <3 0x10 0 0x5777>,
218 <3 0x11 0 0x00aa>,
219 <3 0x12 0 0x4105>,
220 <3 0x13 0 0x0a60>;
221 };
222 phy13: ethernet-phy@3 {
223 cavium,qlm-trim = "3,sgmii";
224 reg = <3>;
225 compatible = "marvell,88e1149r";
226 marvell,reg-init = <3 0x10 0 0x5777>,
227 <3 0x11 0 0x00aa>,
228 <3 0x12 0 0x4105>,
229 <3 0x13 0 0x0a60>;
230 };
231 phy14: ethernet-phy@4 {
232 cavium,qlm-trim = "3,sgmii";
233 reg = <4>;
234 compatible = "marvell,88e1149r";
235 marvell,reg-init = <3 0x10 0 0x5777>,
236 <3 0x11 0 0x00aa>,
237 <3 0x12 0 0x4105>,
238 <3 0x13 0 0x0a60>;
239 };
240 };
241
242 mix0: ethernet@1070000100000 {
243 compatible = "cavium,octeon-5750-mix";
244 reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
245 <0x11800 0xE0000000 0x0 0x300>, /* AGL */
246 <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */
247 <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */
248 cell-index = <0>;
249 interrupts = <6 40>, <6 32>;
250 local-mac-address = [ 00 00 00 00 00 00 ];
251 phy-handle = <&phy0>;
252 };
253
254 pip: pip@11800a0000000 {
255 compatible = "cavium,octeon-3860-pip";
256 #address-cells = <1>;
257 #size-cells = <0>;
258 reg = <0x11800 0xa0000000 0x0 0x2000>;
259
260 interface@4 {
261 compatible = "cavium,octeon-3860-pip-interface";
262 #address-cells = <1>;
263 #size-cells = <0>;
264 reg = <0x4>; /* interface */
265
266 ethernet@0 {
267 compatible = "cavium,octeon-3860-pip-port";
268 reg = <0x0>; /* Port */
269 local-mac-address = [ 00 00 00 00 00 00 ];
270 phy-handle = <&phy1>;
271 };
272 ethernet@1 {
273 compatible = "cavium,octeon-3860-pip-port";
274 reg = <0x1>; /* Port */
275 local-mac-address = [ 00 00 00 00 00 00 ];
276 phy-handle = <&phy2>;
277 };
278 ethernet@2 {
279 compatible = "cavium,octeon-3860-pip-port";
280 reg = <0x2>; /* Port */
281 local-mac-address = [ 00 00 00 00 00 00 ];
282 phy-handle = <&phy3>;
283 };
284 ethernet@3 {
285 compatible = "cavium,octeon-3860-pip-port";
286 reg = <0x3>; /* Port */
287 local-mac-address = [ 00 00 00 00 00 00 ];
288 phy-handle = <&phy4>;
289 };
290 };
291
292 interface@3 {
293 compatible = "cavium,octeon-3860-pip-interface";
294 #address-cells = <1>;
295 #size-cells = <0>;
296 reg = <0x3>; /* interface */
297
298 ethernet@0 {
299 compatible = "cavium,octeon-3860-pip-port";
300 reg = <0x0>; /* Port */
301 local-mac-address = [ 00 00 00 00 00 00 ];
302 phy-handle = <&phy11>;
303 };
304 ethernet@1 {
305 compatible = "cavium,octeon-3860-pip-port";
306 reg = <0x1>; /* Port */
307 local-mac-address = [ 00 00 00 00 00 00 ];
308 phy-handle = <&phy12>;
309 };
310 ethernet@2 {
311 compatible = "cavium,octeon-3860-pip-port";
312 reg = <0x2>; /* Port */
313 local-mac-address = [ 00 00 00 00 00 00 ];
314 phy-handle = <&phy13>;
315 };
316 ethernet@3 {
317 compatible = "cavium,octeon-3860-pip-port";
318 reg = <0x3>; /* Port */
319 local-mac-address = [ 00 00 00 00 00 00 ];
320 phy-handle = <&phy14>;
321 };
322 };
323
324 interface@2 {
325 compatible = "cavium,octeon-3860-pip-interface";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 reg = <0x2>; /* interface */
329
330 ethernet@0 {
331 compatible = "cavium,octeon-3860-pip-port";
332 reg = <0x0>; /* Port */
333 local-mac-address = [ 00 00 00 00 00 00 ];
334 phy-handle = <&phy21>;
335 };
336 ethernet@1 {
337 compatible = "cavium,octeon-3860-pip-port";
338 reg = <0x1>; /* Port */
339 local-mac-address = [ 00 00 00 00 00 00 ];
340 phy-handle = <&phy22>;
341 };
342 ethernet@2 {
343 compatible = "cavium,octeon-3860-pip-port";
344 reg = <0x2>; /* Port */
345 local-mac-address = [ 00 00 00 00 00 00 ];
346 phy-handle = <&phy23>;
347 };
348 ethernet@3 {
349 compatible = "cavium,octeon-3860-pip-port";
350 reg = <0x3>; /* Port */
351 local-mac-address = [ 00 00 00 00 00 00 ];
352 phy-handle = <&phy24>;
353 };
354 };
355
356 interface@1 {
357 compatible = "cavium,octeon-3860-pip-interface";
358 #address-cells = <1>;
359 #size-cells = <0>;
360 reg = <0x1>; /* interface */
361
362 ethernet@0 {
363 compatible = "cavium,octeon-3860-pip-port";
364 reg = <0x0>; /* Port */
365 local-mac-address = [ 00 00 00 00 00 00 ];
366 };
367 };
368
369 interface@0 {
370 compatible = "cavium,octeon-3860-pip-interface";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 reg = <0x0>; /* interface */
374
375 ethernet@0 {
376 compatible = "cavium,octeon-3860-pip-port";
377 reg = <0x0>; /* Port */
378 local-mac-address = [ 00 00 00 00 00 00 ];
379 phy-handle = <&phy41>;
380 };
381 ethernet@1 {
382 compatible = "cavium,octeon-3860-pip-port";
383 reg = <0x1>; /* Port */
384 local-mac-address = [ 00 00 00 00 00 00 ];
385 phy-handle = <&phy42>;
386 };
387 ethernet@2 {
388 compatible = "cavium,octeon-3860-pip-port";
389 reg = <0x2>; /* Port */
390 local-mac-address = [ 00 00 00 00 00 00 ];
391 phy-handle = <&phy43>;
392 };
393 ethernet@3 {
394 compatible = "cavium,octeon-3860-pip-port";
395 reg = <0x3>; /* Port */
396 local-mac-address = [ 00 00 00 00 00 00 ];
397 phy-handle = <&phy44>;
398 };
399 };
400 };
401
402 twsi0: i2c@1180000001000 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 compatible = "cavium,octeon-3860-twsi";
406 reg = <0x11800 0x00001000 0x0 0x200>;
407 interrupts = <3 32>;
408 clock-frequency = <100000>;
409
410 rtc@68 {
411 compatible = "dallas,ds1337";
412 reg = <0x68>;
413 };
414 tmp@4c {
415 compatible = "ti,tmp421";
416 reg = <0x4c>;
417 };
418 };
419
420 twsi1: i2c@1180000001200 {
421 #address-cells = <1>;
422 #size-cells = <0>;
423 compatible = "cavium,octeon-3860-twsi";
424 reg = <0x11800 0x00001200 0x0 0x200>;
425 interrupts = <3 33>;
426 clock-frequency = <100000>;
427 };
428
429 uart0: serial@1180000000800 {
430 compatible = "cavium,octeon-3860-uart","ns16550";
431 reg = <0x11800 0x00000800 0x0 0x400>;
432 clock-frequency = <0>;
433 current-speed = <115200>;
434 reg-shift = <3>;
435 interrupts = <3 36>;
436 };
437
438 uart1: serial@1180000000c00 {
439 compatible = "cavium,octeon-3860-uart","ns16550";
440 reg = <0x11800 0x00000c00 0x0 0x400>;
441 clock-frequency = <0>;
442 current-speed = <115200>;
443 reg-shift = <3>;
444 interrupts = <3 37>;
445 };
446
447 bootbus: bootbus@1180000000000 {
448 compatible = "cavium,octeon-3860-bootbus";
449 reg = <0x11800 0x00000000 0x0 0x200>;
450 /* The chip select number and offset */
451 #address-cells = <2>;
452 /* The size of the chip select region */
453 #size-cells = <1>;
454 ranges = <0 0 0 0x1f400000 0xc00000>,
455 <1 0 0x10000 0x30000000 0>,
456 <2 0 0x10000 0x40000000 0>,
457 <3 0 0x10000 0x50000000 0>,
458 <4 0 0 0x1d020000 0x10000>,
459 <5 0 0 0x1d040000 0x10000>,
460 <6 0 0 0x1d050000 0x10000>,
461 <7 0 0x10000 0x90000000 0>;
462
463 cavium,cs-config@0 {
464 compatible = "cavium,octeon-3860-bootbus-config";
465 cavium,cs-index = <0>;
466 cavium,t-adr = <10>;
467 cavium,t-ce = <50>;
468 cavium,t-oe = <50>;
469 cavium,t-we = <35>;
470 cavium,t-rd-hld = <25>;
471 cavium,t-wr-hld = <35>;
472 cavium,t-pause = <0>;
473 cavium,t-wait = <300>;
474 cavium,t-page = <25>;
475 cavium,t-rd-dly = <0>;
476
477 cavium,pages = <0>;
478 cavium,bus-width = <8>;
479 };
480 cavium,cs-config@4 {
481 compatible = "cavium,octeon-3860-bootbus-config";
482 cavium,cs-index = <4>;
483 cavium,t-adr = <320>;
484 cavium,t-ce = <320>;
485 cavium,t-oe = <320>;
486 cavium,t-we = <320>;
487 cavium,t-rd-hld = <320>;
488 cavium,t-wr-hld = <320>;
489 cavium,t-pause = <320>;
490 cavium,t-wait = <320>;
491 cavium,t-page = <320>;
492 cavium,t-rd-dly = <0>;
493
494 cavium,pages = <0>;
495 cavium,bus-width = <8>;
496 };
497 cavium,cs-config@5 {
498 compatible = "cavium,octeon-3860-bootbus-config";
499 cavium,cs-index = <5>;
500 cavium,t-adr = <0>;
501 cavium,t-ce = <300>;
502 cavium,t-oe = <125>;
503 cavium,t-we = <150>;
504 cavium,t-rd-hld = <100>;
505 cavium,t-wr-hld = <300>;
506 cavium,t-pause = <0>;
507 cavium,t-wait = <300>;
508 cavium,t-page = <310>;
509 cavium,t-rd-dly = <0>;
510
511 cavium,pages = <0>;
512 cavium,bus-width = <16>;
513 };
514 cavium,cs-config@6 {
515 compatible = "cavium,octeon-3860-bootbus-config";
516 cavium,cs-index = <6>;
517 cavium,t-adr = <0>;
518 cavium,t-ce = <30>;
519 cavium,t-oe = <125>;
520 cavium,t-we = <150>;
521 cavium,t-rd-hld = <100>;
522 cavium,t-wr-hld = <30>;
523 cavium,t-pause = <0>;
524 cavium,t-wait = <30>;
525 cavium,t-page = <310>;
526 cavium,t-rd-dly = <0>;
527
528 cavium,pages = <0>;
529 cavium,wait-mode;
530 cavium,bus-width = <16>;
531 };
532
533 flash0: nor@0,0 {
534 compatible = "cfi-flash";
535 reg = <0 0 0x800000>;
536 #address-cells = <1>;
537 #size-cells = <1>;
538
539 partition@0 {
540 label = "bootloader";
541 reg = <0 0x200000>;
542 read-only;
543 };
544 partition@200000 {
545 label = "kernel";
546 reg = <0x200000 0x200000>;
547 };
548 partition@400000 {
549 label = "cramfs";
550 reg = <0x400000 0x3fe000>;
551 };
552 partition@7fe000 {
553 label = "environment";
554 reg = <0x7fe000 0x2000>;
555 read-only;
556 };
557 };
558
559 led0: led-display@4,0 {
560 compatible = "avago,hdsp-253x";
561 reg = <4 0x20 0x20>, <4 0 0x20>;
562 };
563
564 compact-flash@5,0 {
565 compatible = "cavium,ebt3000-compact-flash";
566 reg = <5 0 0x10000>, <6 0 0x10000>;
567 cavium,bus-width = <16>;
568 cavium,true-ide;
569 cavium,dma-engine-handle = <&dma0>;
570 };
571 };
572
573 dma0: dma-engine@1180000000100 {
574 compatible = "cavium,octeon-5750-bootbus-dma";
575 reg = <0x11800 0x00000100 0x0 0x8>;
576 interrupts = <0 63>;
577 };
578 dma1: dma-engine@1180000000108 {
579 compatible = "cavium,octeon-5750-bootbus-dma";
580 reg = <0x11800 0x00000108 0x0 0x8>;
581 interrupts = <0 63>;
582 };
583
584 uctl: uctl@118006f000000 {
585 compatible = "cavium,octeon-6335-uctl";
586 reg = <0x11800 0x6f000000 0x0 0x100>;
587 ranges; /* Direct mapping */
588 #address-cells = <2>;
589 #size-cells = <2>;
590 /* 12MHz, 24MHz and 48MHz allowed */
591 refclk-frequency = <12000000>;
592 /* Either "crystal" or "external" */
593 refclk-type = "crystal";
594
595 ehci@16f0000000000 {
596 compatible = "cavium,octeon-6335-ehci","usb-ehci";
597 reg = <0x16f00 0x00000000 0x0 0x100>;
598 interrupts = <3 44>;
599 big-endian-regs;
600 };
601 ohci@16f0000000400 {
602 compatible = "cavium,octeon-6335-ohci","usb-ohci";
603 reg = <0x16f00 0x00000400 0x0 0x100>;
604 interrupts = <3 44>;
605 big-endian-regs;
606 };
607 };
608 };
609
610 aliases {
611 mix0 = &mix0;
612 pip = &pip;
613 smi0 = &smi0;
614 smi1 = &smi1;
615 smi2 = &smi2;
616 smi3 = &smi3;
617 twsi0 = &twsi0;
618 twsi1 = &twsi1;
619 uart0 = &uart0;
620 uart1 = &uart1;
621 uctl = &uctl;
622 led0 = &led0;
623 flash0 = &flash0;
624 };
625 };
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
index 057f0ae88c99..138b2216b4f8 100644
--- a/arch/mips/cavium-octeon/serial.c
+++ b/arch/mips/cavium-octeon/serial.c
@@ -43,95 +43,67 @@ void octeon_serial_out(struct uart_port *up, int offset, int value)
43 cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value); 43 cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
44} 44}
45 45
46/* 46static int __devinit octeon_serial_probe(struct platform_device *pdev)
47 * Allocated in .bss, so it is all zeroed.
48 */
49#define OCTEON_MAX_UARTS 3
50static struct plat_serial8250_port octeon_uart8250_data[OCTEON_MAX_UARTS + 1];
51static struct platform_device octeon_uart8250_device = {
52 .name = "serial8250",
53 .id = PLAT8250_DEV_PLATFORM,
54 .dev = {
55 .platform_data = octeon_uart8250_data,
56 },
57};
58
59static void __init octeon_uart_set_common(struct plat_serial8250_port *p)
60{ 47{
61 p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 48 int irq, res;
62 p->type = PORT_OCTEON; 49 struct resource *res_mem;
63 p->iotype = UPIO_MEM; 50 struct uart_port port;
64 p->regshift = 3; /* I/O addresses are every 8 bytes */ 51
52 /* All adaptors have an irq. */
53 irq = platform_get_irq(pdev, 0);
54 if (irq < 0)
55 return irq;
56
57 memset(&port, 0, sizeof(port));
58
59 port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
60 port.type = PORT_OCTEON;
61 port.iotype = UPIO_MEM;
62 port.regshift = 3;
63 port.dev = &pdev->dev;
64
65 if (octeon_is_simulation()) 65 if (octeon_is_simulation())
66 /* Make simulator output fast*/ 66 /* Make simulator output fast*/
67 p->uartclk = 115200 * 16; 67 port.uartclk = 115200 * 16;
68 else 68 else
69 p->uartclk = octeon_get_io_clock_rate(); 69 port.uartclk = octeon_get_io_clock_rate();
70 p->serial_in = octeon_serial_in;
71 p->serial_out = octeon_serial_out;
72}
73 70
74static int __init octeon_serial_init(void) 71 port.serial_in = octeon_serial_in;
75{ 72 port.serial_out = octeon_serial_out;
76 int enable_uart0; 73 port.irq = irq;
77 int enable_uart1;
78 int enable_uart2;
79 struct plat_serial8250_port *p;
80
81#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
82 /*
83 * If we are configured to run as the second of two kernels,
84 * disable uart0 and enable uart1. Uart0 is owned by the first
85 * kernel
86 */
87 enable_uart0 = 0;
88 enable_uart1 = 1;
89#else
90 /*
91 * We are configured for the first kernel. We'll enable uart0
92 * if the bootloader told us to use 0, otherwise will enable
93 * uart 1.
94 */
95 enable_uart0 = (octeon_get_boot_uart() == 0);
96 enable_uart1 = (octeon_get_boot_uart() == 1);
97#ifdef CONFIG_KGDB
98 enable_uart1 = 1;
99#endif
100#endif
101
102 /* Right now CN52XX is the only chip with a third uart */
103 enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX);
104
105 p = octeon_uart8250_data;
106 if (enable_uart0) {
107 /* Add a ttyS device for hardware uart 0 */
108 octeon_uart_set_common(p);
109 p->membase = (void *) CVMX_MIO_UARTX_RBR(0);
110 p->mapbase = CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1);
111 p->irq = OCTEON_IRQ_UART0;
112 p++;
113 }
114 74
115 if (enable_uart1) { 75 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
116 /* Add a ttyS device for hardware uart 1 */ 76 if (res_mem == NULL) {
117 octeon_uart_set_common(p); 77 dev_err(&pdev->dev, "found no memory resource\n");
118 p->membase = (void *) CVMX_MIO_UARTX_RBR(1); 78 return -ENXIO;
119 p->mapbase = CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1);
120 p->irq = OCTEON_IRQ_UART1;
121 p++;
122 }
123 if (enable_uart2) {
124 /* Add a ttyS device for hardware uart 2 */
125 octeon_uart_set_common(p);
126 p->membase = (void *) CVMX_MIO_UART2_RBR;
127 p->mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1);
128 p->irq = OCTEON_IRQ_UART2;
129 p++;
130 } 79 }
80 port.mapbase = res_mem->start;
81 port.membase = ioremap(res_mem->start, resource_size(res_mem));
131 82
132 BUG_ON(p > &octeon_uart8250_data[OCTEON_MAX_UARTS]); 83 res = serial8250_register_port(&port);
133 84
134 return platform_device_register(&octeon_uart8250_device); 85 return res >= 0 ? 0 : res;
135} 86}
136 87
137device_initcall(octeon_serial_init); 88static struct of_device_id octeon_serial_match[] = {
89 {
90 .compatible = "cavium,octeon-3860-uart",
91 },
92 {},
93};
94MODULE_DEVICE_TABLE(of, octeon_serial_match);
95
96static struct platform_driver octeon_serial_driver = {
97 .probe = octeon_serial_probe,
98 .driver = {
99 .owner = THIS_MODULE,
100 .name = "octeon_serial",
101 .of_match_table = octeon_serial_match,
102 },
103};
104
105static int __init octeon_serial_init(void)
106{
107 return platform_driver_register(&octeon_serial_driver);
108}
109late_initcall(octeon_serial_init);
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 260dc247c052..919b0fb7bb1a 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -21,6 +21,8 @@
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/serial_core.h> 22#include <linux/serial_core.h>
23#include <linux/serial_8250.h> 23#include <linux/serial_8250.h>
24#include <linux/of_fdt.h>
25#include <linux/libfdt.h>
24 26
25#include <asm/processor.h> 27#include <asm/processor.h>
26#include <asm/reboot.h> 28#include <asm/reboot.h>
@@ -775,3 +777,46 @@ void prom_free_prom_memory(void)
775 } 777 }
776#endif 778#endif
777} 779}
780
781int octeon_prune_device_tree(void);
782
783extern const char __dtb_octeon_3xxx_begin;
784extern const char __dtb_octeon_3xxx_end;
785extern const char __dtb_octeon_68xx_begin;
786extern const char __dtb_octeon_68xx_end;
787void __init device_tree_init(void)
788{
789 int dt_size;
790 struct boot_param_header *fdt;
791 bool do_prune;
792
793 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
794 fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
795 if (fdt_check_header(fdt))
796 panic("Corrupt Device Tree passed to kernel.");
797 dt_size = be32_to_cpu(fdt->totalsize);
798 do_prune = false;
799 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
800 fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin;
801 dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin;
802 do_prune = true;
803 } else {
804 fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin;
805 dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin;
806 do_prune = true;
807 }
808
809 /* Copy the default tree from init memory. */
810 initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8);
811 if (initial_boot_params == NULL)
812 panic("Could not allocate initial_boot_params\n");
813 memcpy(initial_boot_params, fdt, dt_size);
814
815 if (do_prune) {
816 octeon_prune_device_tree();
817 pr_info("Using internal Device Tree.\n");
818 } else {
819 pr_info("Using passed Device Tree.\n");
820 }
821 unflatten_device_tree();
822}
diff --git a/arch/mips/configs/ls1b_defconfig b/arch/mips/configs/ls1b_defconfig
new file mode 100644
index 000000000000..80cff8bea8e8
--- /dev/null
+++ b/arch/mips/configs/ls1b_defconfig
@@ -0,0 +1,109 @@
1CONFIG_MACH_LOONGSON1=y
2CONFIG_PREEMPT=y
3# CONFIG_SECCOMP is not set
4CONFIG_EXPERIMENTAL=y
5# CONFIG_LOCALVERSION_AUTO is not set
6CONFIG_SYSVIPC=y
7CONFIG_BSD_PROCESS_ACCT=y
8CONFIG_BSD_PROCESS_ACCT_V3=y
9CONFIG_HIGH_RES_TIMERS=y
10CONFIG_IKCONFIG=y
11CONFIG_IKCONFIG_PROC=y
12CONFIG_LOG_BUF_SHIFT=16
13CONFIG_NAMESPACES=y
14CONFIG_BLK_DEV_INITRD=y
15CONFIG_RD_BZIP2=y
16CONFIG_RD_LZMA=y
17CONFIG_EXPERT=y
18CONFIG_PERF_EVENTS=y
19# CONFIG_COMPAT_BRK is not set
20CONFIG_MODULES=y
21CONFIG_MODULE_UNLOAD=y
22CONFIG_MODVERSIONS=y
23# CONFIG_LBDAF is not set
24# CONFIG_BLK_DEV_BSG is not set
25# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
26# CONFIG_SUSPEND is not set
27CONFIG_NET=y
28CONFIG_PACKET=y
29CONFIG_UNIX=y
30CONFIG_INET=y
31CONFIG_IP_PNP=y
32CONFIG_IP_PNP_DHCP=y
33CONFIG_SYN_COOKIES=y
34# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
35# CONFIG_INET_XFRM_MODE_TUNNEL is not set
36# CONFIG_INET_XFRM_MODE_BEET is not set
37# CONFIG_INET_DIAG is not set
38# CONFIG_IPV6 is not set
39# CONFIG_WIRELESS is not set
40CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
41CONFIG_DEVTMPFS=y
42CONFIG_DEVTMPFS_MOUNT=y
43# CONFIG_STANDALONE is not set
44CONFIG_BLK_DEV_LOOP=y
45CONFIG_SCSI=m
46# CONFIG_SCSI_PROC_FS is not set
47CONFIG_BLK_DEV_SD=m
48# CONFIG_SCSI_LOWLEVEL is not set
49CONFIG_NETDEVICES=y
50# CONFIG_NET_VENDOR_BROADCOM is not set
51# CONFIG_NET_VENDOR_CHELSIO is not set
52# CONFIG_NET_VENDOR_INTEL is not set
53# CONFIG_NET_VENDOR_MARVELL is not set
54# CONFIG_NET_VENDOR_MICREL is not set
55# CONFIG_NET_VENDOR_NATSEMI is not set
56# CONFIG_NET_VENDOR_SEEQ is not set
57# CONFIG_NET_VENDOR_SMSC is not set
58CONFIG_STMMAC_ETH=y
59CONFIG_STMMAC_DA=y
60# CONFIG_NET_VENDOR_WIZNET is not set
61# CONFIG_WLAN is not set
62CONFIG_INPUT_EVDEV=y
63# CONFIG_INPUT_KEYBOARD is not set
64# CONFIG_INPUT_MOUSE is not set
65# CONFIG_SERIO is not set
66CONFIG_VT_HW_CONSOLE_BINDING=y
67CONFIG_LEGACY_PTY_COUNT=8
68# CONFIG_DEVKMEM is not set
69CONFIG_SERIAL_8250=y
70CONFIG_SERIAL_8250_CONSOLE=y
71# CONFIG_HW_RANDOM is not set
72# CONFIG_HWMON is not set
73# CONFIG_VGA_CONSOLE is not set
74CONFIG_USB_HID=m
75CONFIG_HID_GENERIC=m
76CONFIG_USB=y
77CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
78CONFIG_USB_EHCI_HCD=y
79# CONFIG_USB_EHCI_TT_NEWSCHED is not set
80CONFIG_USB_STORAGE=m
81CONFIG_USB_SERIAL=m
82CONFIG_USB_SERIAL_PL2303=m
83CONFIG_RTC_CLASS=y
84CONFIG_RTC_DRV_LOONGSON1=y
85# CONFIG_IOMMU_SUPPORT is not set
86CONFIG_EXT2_FS=y
87CONFIG_EXT2_FS_XATTR=y
88CONFIG_EXT2_FS_POSIX_ACL=y
89CONFIG_EXT2_FS_SECURITY=y
90CONFIG_EXT3_FS=y
91CONFIG_EXT3_FS_POSIX_ACL=y
92CONFIG_EXT3_FS_SECURITY=y
93# CONFIG_DNOTIFY is not set
94CONFIG_VFAT_FS=y
95CONFIG_PROC_KCORE=y
96CONFIG_TMPFS=y
97CONFIG_TMPFS_POSIX_ACL=y
98# CONFIG_MISC_FILESYSTEMS is not set
99CONFIG_NFS_FS=y
100CONFIG_ROOT_NFS=y
101CONFIG_NLS_CODEPAGE_437=m
102CONFIG_NLS_ISO8859_1=m
103# CONFIG_ENABLE_WARN_DEPRECATED is not set
104# CONFIG_ENABLE_MUST_CHECK is not set
105CONFIG_MAGIC_SYSRQ=y
106# CONFIG_SCHED_DEBUG is not set
107# CONFIG_DEBUG_PREEMPT is not set
108# CONFIG_FTRACE is not set
109# CONFIG_EARLY_PRINTK is not set
diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig
index d0b857d98c91..138f698d7c00 100644
--- a/arch/mips/configs/nlm_xlr_defconfig
+++ b/arch/mips/configs/nlm_xlr_defconfig
@@ -367,6 +367,10 @@ CONFIG_SERIAL_8250_RSA=y
367CONFIG_HW_RANDOM=y 367CONFIG_HW_RANDOM=y
368CONFIG_HW_RANDOM_TIMERIOMEM=m 368CONFIG_HW_RANDOM_TIMERIOMEM=m
369CONFIG_RAW_DRIVER=m 369CONFIG_RAW_DRIVER=m
370CONFIG_I2C=y
371CONFIG_I2C_XLR=y
372CONFIG_RTC_CLASS=y
373CONFIG_RTC_DRV_DS1374=y
370# CONFIG_HWMON is not set 374# CONFIG_HWMON is not set
371# CONFIG_VGA_CONSOLE is not set 375# CONFIG_VGA_CONSOLE is not set
372# CONFIG_HID_SUPPORT is not set 376# CONFIG_HID_SUPPORT is not set
diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c
index e95ff3054ff6..8c62316f22f4 100644
--- a/arch/mips/dec/prom/memory.c
+++ b/arch/mips/dec/prom/memory.c
@@ -101,7 +101,7 @@ void __init prom_free_prom_memory(void)
101 * the first page reserved for the exception handlers. 101 * the first page reserved for the exception handlers.
102 */ 102 */
103 103
104#if defined(CONFIG_DECLANCE) || defined(CONFIG_DECLANCE_MODULE) 104#if IS_ENABLED(CONFIG_DECLANCE)
105 /* 105 /*
106 * Leave 128 KB reserved for Lance memory for 106 * Leave 128 KB reserved for Lance memory for
107 * IOASIC DECstations. 107 * IOASIC DECstations.
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 95e40c1e8ed1..f21b7c04e95a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -197,6 +197,7 @@
197#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 197#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
198#define PRID_REV_VR4130 0x0080 198#define PRID_REV_VR4130 0x0080
199#define PRID_REV_34K_V1_0_2 0x0022 199#define PRID_REV_34K_V1_0_2 0x0022
200#define PRID_REV_LOONGSON1B 0x0020
200#define PRID_REV_LOONGSON2E 0x0002 201#define PRID_REV_LOONGSON2E 0x0002
201#define PRID_REV_LOONGSON2F 0x0003 202#define PRID_REV_LOONGSON2F 0x0003
202 203
@@ -261,7 +262,7 @@ enum cpu_type_enum {
261 */ 262 */
262 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 263 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
263 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 264 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
264 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_M14KC, 265 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
265 266
266 /* 267 /*
267 * MIPS64 class processors 268 * MIPS64 class processors
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 5b8d15bb5fe8..e104ddb694a8 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
9 * compile time if only one CPU support is enabled (idea stolen from 9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types) 10 * arm mach-types)
11 */ 11 */
12#define BCM6328_CPU_ID 0x6328
12#define BCM6338_CPU_ID 0x6338 13#define BCM6338_CPU_ID 0x6338
13#define BCM6345_CPU_ID 0x6345 14#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348 15#define BCM6348_CPU_ID 0x6348
@@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void);
20u16 bcm63xx_get_cpu_rev(void); 21u16 bcm63xx_get_cpu_rev(void);
21unsigned int bcm63xx_get_cpu_freq(void); 22unsigned int bcm63xx_get_cpu_freq(void);
22 23
24#ifdef CONFIG_BCM63XX_CPU_6328
25# ifdef bcm63xx_get_cpu_id
26# undef bcm63xx_get_cpu_id
27# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
28# define BCMCPU_RUNTIME_DETECT
29# else
30# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
31# endif
32# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
33#else
34# define BCMCPU_IS_6328() (0)
35#endif
36
23#ifdef CONFIG_BCM63XX_CPU_6338 37#ifdef CONFIG_BCM63XX_CPU_6338
24# ifdef bcm63xx_get_cpu_id 38# ifdef bcm63xx_get_cpu_id
25# undef bcm63xx_get_cpu_id 39# undef bcm63xx_get_cpu_id
@@ -102,13 +116,13 @@ enum bcm63xx_regs_set {
102 RSET_UART1, 116 RSET_UART1,
103 RSET_GPIO, 117 RSET_GPIO,
104 RSET_SPI, 118 RSET_SPI,
105 RSET_SPI2,
106 RSET_UDC0, 119 RSET_UDC0,
107 RSET_OHCI0, 120 RSET_OHCI0,
108 RSET_OHCI_PRIV, 121 RSET_OHCI_PRIV,
109 RSET_USBH_PRIV, 122 RSET_USBH_PRIV,
110 RSET_MPI, 123 RSET_MPI,
111 RSET_PCMCIA, 124 RSET_PCMCIA,
125 RSET_PCIE,
112 RSET_DSL, 126 RSET_DSL,
113 RSET_ENET0, 127 RSET_ENET0,
114 RSET_ENET1, 128 RSET_ENET1,
@@ -130,11 +144,17 @@ enum bcm63xx_regs_set {
130 RSET_PCMDMA, 144 RSET_PCMDMA,
131 RSET_PCMDMAC, 145 RSET_PCMDMAC,
132 RSET_PCMDMAS, 146 RSET_PCMDMAS,
147 RSET_RNG,
148 RSET_MISC
133}; 149};
134 150
135#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 151#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
136#define RSET_DSL_SIZE 4096 152#define RSET_DSL_SIZE 4096
137#define RSET_WDT_SIZE 12 153#define RSET_WDT_SIZE 12
154#define BCM_6338_RSET_SPI_SIZE 64
155#define BCM_6348_RSET_SPI_SIZE 64
156#define BCM_6358_RSET_SPI_SIZE 1804
157#define BCM_6368_RSET_SPI_SIZE 1804
138#define RSET_ENET_SIZE 2048 158#define RSET_ENET_SIZE 2048
139#define RSET_ENETDMA_SIZE 2048 159#define RSET_ENETDMA_SIZE 2048
140#define RSET_ENETSW_SIZE 65536 160#define RSET_ENETSW_SIZE 65536
@@ -149,8 +169,53 @@ enum bcm63xx_regs_set {
149#define RSET_XTMDMA_SIZE 256 169#define RSET_XTMDMA_SIZE 256
150#define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) 170#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
151#define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) 171#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
172#define RSET_RNG_SIZE 20
152 173
153/* 174/*
175 * 6328 register sets base address
176 */
177#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
178#define BCM_6328_PERF_BASE (0xb0000000)
179#define BCM_6328_TIMER_BASE (0xb0000040)
180#define BCM_6328_WDT_BASE (0xb000005c)
181#define BCM_6328_UART0_BASE (0xb0000100)
182#define BCM_6328_UART1_BASE (0xb0000120)
183#define BCM_6328_GPIO_BASE (0xb0000080)
184#define BCM_6328_SPI_BASE (0xdeadbeef)
185#define BCM_6328_UDC0_BASE (0xdeadbeef)
186#define BCM_6328_USBDMA_BASE (0xdeadbeef)
187#define BCM_6328_OHCI0_BASE (0xdeadbeef)
188#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
189#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
190#define BCM_6328_MPI_BASE (0xdeadbeef)
191#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
192#define BCM_6328_PCIE_BASE (0xb0e40000)
193#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
194#define BCM_6328_DSL_BASE (0xb0001900)
195#define BCM_6328_UBUS_BASE (0xdeadbeef)
196#define BCM_6328_ENET0_BASE (0xdeadbeef)
197#define BCM_6328_ENET1_BASE (0xdeadbeef)
198#define BCM_6328_ENETDMA_BASE (0xb000d800)
199#define BCM_6328_ENETDMAC_BASE (0xb000da00)
200#define BCM_6328_ENETDMAS_BASE (0xb000dc00)
201#define BCM_6328_ENETSW_BASE (0xb0e00000)
202#define BCM_6328_EHCI0_BASE (0x10002500)
203#define BCM_6328_SDRAM_BASE (0xdeadbeef)
204#define BCM_6328_MEMC_BASE (0xdeadbeef)
205#define BCM_6328_DDR_BASE (0xb0003000)
206#define BCM_6328_M2M_BASE (0xdeadbeef)
207#define BCM_6328_ATM_BASE (0xdeadbeef)
208#define BCM_6328_XTM_BASE (0xdeadbeef)
209#define BCM_6328_XTMDMA_BASE (0xb000b800)
210#define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
211#define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
212#define BCM_6328_PCM_BASE (0xb000a800)
213#define BCM_6328_PCMDMA_BASE (0xdeadbeef)
214#define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
215#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
216#define BCM_6328_RNG_BASE (0xdeadbeef)
217#define BCM_6328_MISC_BASE (0xb0001800)
218/*
154 * 6338 register sets base address 219 * 6338 register sets base address
155 */ 220 */
156#define BCM_6338_DSL_LMEM_BASE (0xfff00000) 221#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
@@ -162,7 +227,6 @@ enum bcm63xx_regs_set {
162#define BCM_6338_UART1_BASE (0xdeadbeef) 227#define BCM_6338_UART1_BASE (0xdeadbeef)
163#define BCM_6338_GPIO_BASE (0xfffe0400) 228#define BCM_6338_GPIO_BASE (0xfffe0400)
164#define BCM_6338_SPI_BASE (0xfffe0c00) 229#define BCM_6338_SPI_BASE (0xfffe0c00)
165#define BCM_6338_SPI2_BASE (0xdeadbeef)
166#define BCM_6338_UDC0_BASE (0xdeadbeef) 230#define BCM_6338_UDC0_BASE (0xdeadbeef)
167#define BCM_6338_USBDMA_BASE (0xfffe2400) 231#define BCM_6338_USBDMA_BASE (0xfffe2400)
168#define BCM_6338_OHCI0_BASE (0xdeadbeef) 232#define BCM_6338_OHCI0_BASE (0xdeadbeef)
@@ -170,6 +234,7 @@ enum bcm63xx_regs_set {
170#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) 234#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
171#define BCM_6338_MPI_BASE (0xfffe3160) 235#define BCM_6338_MPI_BASE (0xfffe3160)
172#define BCM_6338_PCMCIA_BASE (0xdeadbeef) 236#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
237#define BCM_6338_PCIE_BASE (0xdeadbeef)
173#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 238#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
174#define BCM_6338_DSL_BASE (0xfffe1000) 239#define BCM_6338_DSL_BASE (0xfffe1000)
175#define BCM_6338_UBUS_BASE (0xdeadbeef) 240#define BCM_6338_UBUS_BASE (0xdeadbeef)
@@ -193,6 +258,8 @@ enum bcm63xx_regs_set {
193#define BCM_6338_PCMDMA_BASE (0xdeadbeef) 258#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
194#define BCM_6338_PCMDMAC_BASE (0xdeadbeef) 259#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
195#define BCM_6338_PCMDMAS_BASE (0xdeadbeef) 260#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
261#define BCM_6338_RNG_BASE (0xdeadbeef)
262#define BCM_6338_MISC_BASE (0xdeadbeef)
196 263
197/* 264/*
198 * 6345 register sets base address 265 * 6345 register sets base address
@@ -206,7 +273,6 @@ enum bcm63xx_regs_set {
206#define BCM_6345_UART1_BASE (0xdeadbeef) 273#define BCM_6345_UART1_BASE (0xdeadbeef)
207#define BCM_6345_GPIO_BASE (0xfffe0400) 274#define BCM_6345_GPIO_BASE (0xfffe0400)
208#define BCM_6345_SPI_BASE (0xdeadbeef) 275#define BCM_6345_SPI_BASE (0xdeadbeef)
209#define BCM_6345_SPI2_BASE (0xdeadbeef)
210#define BCM_6345_UDC0_BASE (0xdeadbeef) 276#define BCM_6345_UDC0_BASE (0xdeadbeef)
211#define BCM_6345_USBDMA_BASE (0xfffe2800) 277#define BCM_6345_USBDMA_BASE (0xfffe2800)
212#define BCM_6345_ENET0_BASE (0xfffe1800) 278#define BCM_6345_ENET0_BASE (0xfffe1800)
@@ -216,6 +282,7 @@ enum bcm63xx_regs_set {
216#define BCM_6345_ENETSW_BASE (0xdeadbeef) 282#define BCM_6345_ENETSW_BASE (0xdeadbeef)
217#define BCM_6345_PCMCIA_BASE (0xfffe2028) 283#define BCM_6345_PCMCIA_BASE (0xfffe2028)
218#define BCM_6345_MPI_BASE (0xfffe2000) 284#define BCM_6345_MPI_BASE (0xfffe2000)
285#define BCM_6345_PCIE_BASE (0xdeadbeef)
219#define BCM_6345_OHCI0_BASE (0xfffe2100) 286#define BCM_6345_OHCI0_BASE (0xfffe2100)
220#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 287#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
221#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 288#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
@@ -237,6 +304,8 @@ enum bcm63xx_regs_set {
237#define BCM_6345_PCMDMA_BASE (0xdeadbeef) 304#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
238#define BCM_6345_PCMDMAC_BASE (0xdeadbeef) 305#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
239#define BCM_6345_PCMDMAS_BASE (0xdeadbeef) 306#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
307#define BCM_6345_RNG_BASE (0xdeadbeef)
308#define BCM_6345_MISC_BASE (0xdeadbeef)
240 309
241/* 310/*
242 * 6348 register sets base address 311 * 6348 register sets base address
@@ -249,13 +318,13 @@ enum bcm63xx_regs_set {
249#define BCM_6348_UART1_BASE (0xdeadbeef) 318#define BCM_6348_UART1_BASE (0xdeadbeef)
250#define BCM_6348_GPIO_BASE (0xfffe0400) 319#define BCM_6348_GPIO_BASE (0xfffe0400)
251#define BCM_6348_SPI_BASE (0xfffe0c00) 320#define BCM_6348_SPI_BASE (0xfffe0c00)
252#define BCM_6348_SPI2_BASE (0xdeadbeef)
253#define BCM_6348_UDC0_BASE (0xfffe1000) 321#define BCM_6348_UDC0_BASE (0xfffe1000)
254#define BCM_6348_OHCI0_BASE (0xfffe1b00) 322#define BCM_6348_OHCI0_BASE (0xfffe1b00)
255#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 323#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
256#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) 324#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
257#define BCM_6348_MPI_BASE (0xfffe2000) 325#define BCM_6348_MPI_BASE (0xfffe2000)
258#define BCM_6348_PCMCIA_BASE (0xfffe2054) 326#define BCM_6348_PCMCIA_BASE (0xfffe2054)
327#define BCM_6348_PCIE_BASE (0xdeadbeef)
259#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 328#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
260#define BCM_6348_M2M_BASE (0xfffe2800) 329#define BCM_6348_M2M_BASE (0xfffe2800)
261#define BCM_6348_DSL_BASE (0xfffe3000) 330#define BCM_6348_DSL_BASE (0xfffe3000)
@@ -278,6 +347,8 @@ enum bcm63xx_regs_set {
278#define BCM_6348_PCMDMA_BASE (0xdeadbeef) 347#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
279#define BCM_6348_PCMDMAC_BASE (0xdeadbeef) 348#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
280#define BCM_6348_PCMDMAS_BASE (0xdeadbeef) 349#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
350#define BCM_6348_RNG_BASE (0xdeadbeef)
351#define BCM_6348_MISC_BASE (0xdeadbeef)
281 352
282/* 353/*
283 * 6358 register sets base address 354 * 6358 register sets base address
@@ -289,14 +360,14 @@ enum bcm63xx_regs_set {
289#define BCM_6358_UART0_BASE (0xfffe0100) 360#define BCM_6358_UART0_BASE (0xfffe0100)
290#define BCM_6358_UART1_BASE (0xfffe0120) 361#define BCM_6358_UART1_BASE (0xfffe0120)
291#define BCM_6358_GPIO_BASE (0xfffe0080) 362#define BCM_6358_GPIO_BASE (0xfffe0080)
292#define BCM_6358_SPI_BASE (0xdeadbeef) 363#define BCM_6358_SPI_BASE (0xfffe0800)
293#define BCM_6358_SPI2_BASE (0xfffe0800)
294#define BCM_6358_UDC0_BASE (0xfffe0800) 364#define BCM_6358_UDC0_BASE (0xfffe0800)
295#define BCM_6358_OHCI0_BASE (0xfffe1400) 365#define BCM_6358_OHCI0_BASE (0xfffe1400)
296#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 366#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
297#define BCM_6358_USBH_PRIV_BASE (0xfffe1500) 367#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
298#define BCM_6358_MPI_BASE (0xfffe1000) 368#define BCM_6358_MPI_BASE (0xfffe1000)
299#define BCM_6358_PCMCIA_BASE (0xfffe1054) 369#define BCM_6358_PCMCIA_BASE (0xfffe1054)
370#define BCM_6358_PCIE_BASE (0xdeadbeef)
300#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 371#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
301#define BCM_6358_M2M_BASE (0xdeadbeef) 372#define BCM_6358_M2M_BASE (0xdeadbeef)
302#define BCM_6358_DSL_BASE (0xfffe3000) 373#define BCM_6358_DSL_BASE (0xfffe3000)
@@ -319,6 +390,8 @@ enum bcm63xx_regs_set {
319#define BCM_6358_PCMDMA_BASE (0xfffe1800) 390#define BCM_6358_PCMDMA_BASE (0xfffe1800)
320#define BCM_6358_PCMDMAC_BASE (0xfffe1900) 391#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
321#define BCM_6358_PCMDMAS_BASE (0xfffe1a00) 392#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
393#define BCM_6358_RNG_BASE (0xdeadbeef)
394#define BCM_6358_MISC_BASE (0xdeadbeef)
322 395
323 396
324/* 397/*
@@ -331,14 +404,14 @@ enum bcm63xx_regs_set {
331#define BCM_6368_UART0_BASE (0xb0000100) 404#define BCM_6368_UART0_BASE (0xb0000100)
332#define BCM_6368_UART1_BASE (0xb0000120) 405#define BCM_6368_UART1_BASE (0xb0000120)
333#define BCM_6368_GPIO_BASE (0xb0000080) 406#define BCM_6368_GPIO_BASE (0xb0000080)
334#define BCM_6368_SPI_BASE (0xdeadbeef) 407#define BCM_6368_SPI_BASE (0xb0000800)
335#define BCM_6368_SPI2_BASE (0xb0000800)
336#define BCM_6368_UDC0_BASE (0xdeadbeef) 408#define BCM_6368_UDC0_BASE (0xdeadbeef)
337#define BCM_6368_OHCI0_BASE (0xb0001600) 409#define BCM_6368_OHCI0_BASE (0xb0001600)
338#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) 410#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
339#define BCM_6368_USBH_PRIV_BASE (0xb0001700) 411#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
340#define BCM_6368_MPI_BASE (0xb0001000) 412#define BCM_6368_MPI_BASE (0xb0001000)
341#define BCM_6368_PCMCIA_BASE (0xb0001054) 413#define BCM_6368_PCMCIA_BASE (0xb0001054)
414#define BCM_6368_PCIE_BASE (0xdeadbeef)
342#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef) 415#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
343#define BCM_6368_M2M_BASE (0xdeadbeef) 416#define BCM_6368_M2M_BASE (0xdeadbeef)
344#define BCM_6368_DSL_BASE (0xdeadbeef) 417#define BCM_6368_DSL_BASE (0xdeadbeef)
@@ -361,6 +434,8 @@ enum bcm63xx_regs_set {
361#define BCM_6368_PCMDMA_BASE (0xb0005800) 434#define BCM_6368_PCMDMA_BASE (0xb0005800)
362#define BCM_6368_PCMDMAC_BASE (0xb0005a00) 435#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
363#define BCM_6368_PCMDMAS_BASE (0xb0005c00) 436#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
437#define BCM_6368_RNG_BASE (0xb0004180)
438#define BCM_6368_MISC_BASE (0xdeadbeef)
364 439
365 440
366extern const unsigned long *bcm63xx_regs_base; 441extern const unsigned long *bcm63xx_regs_base;
@@ -379,13 +454,13 @@ extern const unsigned long *bcm63xx_regs_base;
379 __GEN_RSET_BASE(__cpu, UART1) \ 454 __GEN_RSET_BASE(__cpu, UART1) \
380 __GEN_RSET_BASE(__cpu, GPIO) \ 455 __GEN_RSET_BASE(__cpu, GPIO) \
381 __GEN_RSET_BASE(__cpu, SPI) \ 456 __GEN_RSET_BASE(__cpu, SPI) \
382 __GEN_RSET_BASE(__cpu, SPI2) \
383 __GEN_RSET_BASE(__cpu, UDC0) \ 457 __GEN_RSET_BASE(__cpu, UDC0) \
384 __GEN_RSET_BASE(__cpu, OHCI0) \ 458 __GEN_RSET_BASE(__cpu, OHCI0) \
385 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ 459 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
386 __GEN_RSET_BASE(__cpu, USBH_PRIV) \ 460 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
387 __GEN_RSET_BASE(__cpu, MPI) \ 461 __GEN_RSET_BASE(__cpu, MPI) \
388 __GEN_RSET_BASE(__cpu, PCMCIA) \ 462 __GEN_RSET_BASE(__cpu, PCMCIA) \
463 __GEN_RSET_BASE(__cpu, PCIE) \
389 __GEN_RSET_BASE(__cpu, DSL) \ 464 __GEN_RSET_BASE(__cpu, DSL) \
390 __GEN_RSET_BASE(__cpu, ENET0) \ 465 __GEN_RSET_BASE(__cpu, ENET0) \
391 __GEN_RSET_BASE(__cpu, ENET1) \ 466 __GEN_RSET_BASE(__cpu, ENET1) \
@@ -407,6 +482,8 @@ extern const unsigned long *bcm63xx_regs_base;
407 __GEN_RSET_BASE(__cpu, PCMDMA) \ 482 __GEN_RSET_BASE(__cpu, PCMDMA) \
408 __GEN_RSET_BASE(__cpu, PCMDMAC) \ 483 __GEN_RSET_BASE(__cpu, PCMDMAC) \
409 __GEN_RSET_BASE(__cpu, PCMDMAS) \ 484 __GEN_RSET_BASE(__cpu, PCMDMAS) \
485 __GEN_RSET_BASE(__cpu, RNG) \
486 __GEN_RSET_BASE(__cpu, MISC) \
410 } 487 }
411 488
412#define __GEN_CPU_REGS_TABLE(__cpu) \ 489#define __GEN_CPU_REGS_TABLE(__cpu) \
@@ -418,13 +495,13 @@ extern const unsigned long *bcm63xx_regs_base;
418 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ 495 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
419 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ 496 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
420 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ 497 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
421 [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \
422 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ 498 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
423 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ 499 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
424 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ 500 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
425 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ 501 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
426 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ 502 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
427 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ 503 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
504 [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
428 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \ 505 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
429 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ 506 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
430 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ 507 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
@@ -446,6 +523,8 @@ extern const unsigned long *bcm63xx_regs_base;
446 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ 523 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
447 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ 524 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
448 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ 525 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
526 [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
527 [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
449 528
450 529
451static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 530static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
@@ -453,6 +532,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
453#ifdef BCMCPU_RUNTIME_DETECT 532#ifdef BCMCPU_RUNTIME_DETECT
454 return bcm63xx_regs_base[set]; 533 return bcm63xx_regs_base[set];
455#else 534#else
535#ifdef CONFIG_BCM63XX_CPU_6328
536 __GEN_RSET(6328)
537#endif
456#ifdef CONFIG_BCM63XX_CPU_6338 538#ifdef CONFIG_BCM63XX_CPU_6338
457 __GEN_RSET(6338) 539 __GEN_RSET(6338)
458#endif 540#endif
@@ -478,6 +560,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
478 */ 560 */
479enum bcm63xx_irq { 561enum bcm63xx_irq {
480 IRQ_TIMER = 0, 562 IRQ_TIMER = 0,
563 IRQ_SPI,
481 IRQ_UART0, 564 IRQ_UART0,
482 IRQ_UART1, 565 IRQ_UART1,
483 IRQ_DSL, 566 IRQ_DSL,
@@ -506,9 +589,51 @@ enum bcm63xx_irq {
506}; 589};
507 590
508/* 591/*
592 * 6328 irqs
593 */
594#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
595
596#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
597#define BCM_6328_SPI_IRQ 0
598#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
599#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
600#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
601#define BCM_6328_UDC0_IRQ 0
602#define BCM_6328_ENET0_IRQ 0
603#define BCM_6328_ENET1_IRQ 0
604#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
605#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
606#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
607#define BCM_6328_PCMCIA_IRQ 0
608#define BCM_6328_ENET0_RXDMA_IRQ 0
609#define BCM_6328_ENET0_TXDMA_IRQ 0
610#define BCM_6328_ENET1_RXDMA_IRQ 0
611#define BCM_6328_ENET1_TXDMA_IRQ 0
612#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
613#define BCM_6328_ATM_IRQ 0
614#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
615#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
616#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
617#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
618#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4)
619#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5)
620#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6)
621#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
622#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
623#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
624
625#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
626#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
627#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
628#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
629#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
630#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
631
632/*
509 * 6338 irqs 633 * 6338 irqs
510 */ 634 */
511#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 635#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
636#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
512#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 637#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
513#define BCM_6338_UART1_IRQ 0 638#define BCM_6338_UART1_IRQ 0
514#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 639#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
@@ -539,6 +664,7 @@ enum bcm63xx_irq {
539 * 6345 irqs 664 * 6345 irqs
540 */ 665 */
541#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 666#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
667#define BCM_6345_SPI_IRQ 0
542#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 668#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
543#define BCM_6345_UART1_IRQ 0 669#define BCM_6345_UART1_IRQ 0
544#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 670#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
@@ -569,6 +695,7 @@ enum bcm63xx_irq {
569 * 6348 irqs 695 * 6348 irqs
570 */ 696 */
571#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 697#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
698#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
572#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 699#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
573#define BCM_6348_UART1_IRQ 0 700#define BCM_6348_UART1_IRQ 0
574#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 701#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
@@ -599,6 +726,7 @@ enum bcm63xx_irq {
599 * 6358 irqs 726 * 6358 irqs
600 */ 727 */
601#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 728#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
729#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
602#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 730#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
603#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 731#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
604#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) 732#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
@@ -638,6 +766,7 @@ enum bcm63xx_irq {
638#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 766#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
639 767
640#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 768#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
769#define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
641#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 770#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
642#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 771#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
643#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 772#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
@@ -677,6 +806,7 @@ extern const int *bcm63xx_irqs;
677 806
678#define __GEN_CPU_IRQ_TABLE(__cpu) \ 807#define __GEN_CPU_IRQ_TABLE(__cpu) \
679 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ 808 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
809 [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \
680 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ 810 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
681 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ 811 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
682 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ 812 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
new file mode 100644
index 000000000000..354b8481ec4a
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
@@ -0,0 +1,12 @@
1#ifndef __BCM63XX_FLASH_H
2#define __BCM63XX_FLASH_H
3
4enum {
5 BCM63XX_FLASH_TYPE_PARALLEL,
6 BCM63XX_FLASH_TYPE_SERIAL,
7 BCM63XX_FLASH_TYPE_NAND,
8};
9
10int __init bcm63xx_flash_register(void);
11
12#endif /* __BCM63XX_FLASH_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
new file mode 100644
index 000000000000..7d98dbe5d4b5
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -0,0 +1,89 @@
1#ifndef BCM63XX_DEV_SPI_H
2#define BCM63XX_DEV_SPI_H
3
4#include <linux/types.h>
5#include <bcm63xx_io.h>
6#include <bcm63xx_regs.h>
7
8int __init bcm63xx_spi_register(void);
9
10struct bcm63xx_spi_pdata {
11 unsigned int fifo_size;
12 int bus_num;
13 int num_chipselect;
14 u32 speed_hz;
15};
16
17enum bcm63xx_regs_spi {
18 SPI_CMD,
19 SPI_INT_STATUS,
20 SPI_INT_MASK_ST,
21 SPI_INT_MASK,
22 SPI_ST,
23 SPI_CLK_CFG,
24 SPI_FILL_BYTE,
25 SPI_MSG_TAIL,
26 SPI_RX_TAIL,
27 SPI_MSG_CTL,
28 SPI_MSG_DATA,
29 SPI_RX_DATA,
30};
31
32#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
33 case SPI_## __rset: \
34 return SPI_## __cpu ##_## __rset;
35
36#define __GEN_SPI_RSET(__cpu) \
37 switch (reg) { \
38 __GEN_SPI_RSET_BASE(__cpu, CMD) \
39 __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
40 __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
41 __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
42 __GEN_SPI_RSET_BASE(__cpu, ST) \
43 __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
44 __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
45 __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
46 __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
47 __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
48 __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
49 __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
50 }
51
52#define __GEN_SPI_REGS_TABLE(__cpu) \
53 [SPI_CMD] = SPI_## __cpu ##_CMD, \
54 [SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \
55 [SPI_INT_MASK_ST] = SPI_## __cpu ##_INT_MASK_ST, \
56 [SPI_INT_MASK] = SPI_## __cpu ##_INT_MASK, \
57 [SPI_ST] = SPI_## __cpu ##_ST, \
58 [SPI_CLK_CFG] = SPI_## __cpu ##_CLK_CFG, \
59 [SPI_FILL_BYTE] = SPI_## __cpu ##_FILL_BYTE, \
60 [SPI_MSG_TAIL] = SPI_## __cpu ##_MSG_TAIL, \
61 [SPI_RX_TAIL] = SPI_## __cpu ##_RX_TAIL, \
62 [SPI_MSG_CTL] = SPI_## __cpu ##_MSG_CTL, \
63 [SPI_MSG_DATA] = SPI_## __cpu ##_MSG_DATA, \
64 [SPI_RX_DATA] = SPI_## __cpu ##_RX_DATA,
65
66static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
67{
68#ifdef BCMCPU_RUNTIME_DETECT
69 extern const unsigned long *bcm63xx_regs_spi;
70
71 return bcm63xx_regs_spi[reg];
72#else
73#ifdef CONFIG_BCM63XX_CPU_6338
74 __GEN_SPI_RSET(6338)
75#endif
76#ifdef CONFIG_BCM63XX_CPU_6348
77 __GEN_SPI_RSET(6348)
78#endif
79#ifdef CONFIG_BCM63XX_CPU_6358
80 __GEN_SPI_RSET(6358)
81#endif
82#ifdef CONFIG_BCM63XX_CPU_6368
83 __GEN_SPI_RSET(6368)
84#endif
85#endif
86 return 0;
87}
88
89#endif /* BCM63XX_DEV_SPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 1d7dd96aa460..0a9891f7580d 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
9static inline unsigned long bcm63xx_gpio_count(void) 9static inline unsigned long bcm63xx_gpio_count(void)
10{ 10{
11 switch (bcm63xx_get_cpu_id()) { 11 switch (bcm63xx_get_cpu_id()) {
12 case BCM6328_CPU_ID:
13 return 32;
12 case BCM6358_CPU_ID: 14 case BCM6358_CPU_ID:
13 return 40; 15 return 40;
14 case BCM6338_CPU_ID: 16 case BCM6338_CPU_ID:
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 72477a6441dd..9203d90e610c 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -40,6 +40,10 @@
40#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ 40#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
41 BCM_CB_MEM_SIZE - 1) 41 BCM_CB_MEM_SIZE - 1)
42 42
43#define BCM_PCIE_MEM_BASE_PA 0x10f00000
44#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024)
45#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \
46 BCM_PCIE_MEM_SIZE - 1)
43 47
44/* 48/*
45 * Internal registers are accessed through KSEG3 49 * Internal registers are accessed through KSEG3
@@ -85,11 +89,15 @@
85#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o)) 89#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
86#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o)) 90#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
87#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o)) 91#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
92#define bcm_pcie_readl(o) bcm_rset_readl(RSET_PCIE, (o))
93#define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o))
88#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o)) 94#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
89#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o)) 95#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
90#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o)) 96#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
91#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o)) 97#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
92#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o)) 98#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
93#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o)) 99#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
100#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
101#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
94 102
95#endif /* ! BCM63XX_IO_H_ */ 103#endif /* ! BCM63XX_IO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index fdcd78ca1b03..4ccc2a748aff 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -15,6 +15,30 @@
15/* Clock Control register */ 15/* Clock Control register */
16#define PERF_CKCTL_REG 0x4 16#define PERF_CKCTL_REG 0x4
17 17
18#define CKCTL_6328_PHYMIPS_EN (1 << 0)
19#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
20#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
21#define CKCTL_6328_ADSL_EN (1 << 3)
22#define CKCTL_6328_MIPS_EN (1 << 4)
23#define CKCTL_6328_SAR_EN (1 << 5)
24#define CKCTL_6328_PCM_EN (1 << 6)
25#define CKCTL_6328_USBD_EN (1 << 7)
26#define CKCTL_6328_USBH_EN (1 << 8)
27#define CKCTL_6328_HSSPI_EN (1 << 9)
28#define CKCTL_6328_PCIE_EN (1 << 10)
29#define CKCTL_6328_ROBOSW_EN (1 << 11)
30
31#define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
32 CKCTL_6328_ADSL_QPROC_EN | \
33 CKCTL_6328_ADSL_AFE_EN | \
34 CKCTL_6328_ADSL_EN | \
35 CKCTL_6328_SAR_EN | \
36 CKCTL_6328_PCM_EN | \
37 CKCTL_6328_USBD_EN | \
38 CKCTL_6328_USBH_EN | \
39 CKCTL_6328_ROBOSW_EN | \
40 CKCTL_6328_PCIE_EN)
41
18#define CKCTL_6338_ADSLPHY_EN (1 << 0) 42#define CKCTL_6338_ADSLPHY_EN (1 << 0)
19#define CKCTL_6338_MPI_EN (1 << 1) 43#define CKCTL_6338_MPI_EN (1 << 1)
20#define CKCTL_6338_DRAM_EN (1 << 2) 44#define CKCTL_6338_DRAM_EN (1 << 2)
@@ -90,35 +114,36 @@
90#define CKCTL_6368_PHYMIPS_EN (1 << 6) 114#define CKCTL_6368_PHYMIPS_EN (1 << 6)
91#define CKCTL_6368_SWPKT_USB_EN (1 << 7) 115#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
92#define CKCTL_6368_SWPKT_SAR_EN (1 << 8) 116#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
93#define CKCTL_6368_SPI_CLK_EN (1 << 9) 117#define CKCTL_6368_SPI_EN (1 << 9)
94#define CKCTL_6368_USBD_CLK_EN (1 << 10) 118#define CKCTL_6368_USBD_EN (1 << 10)
95#define CKCTL_6368_SAR_CLK_EN (1 << 11) 119#define CKCTL_6368_SAR_EN (1 << 11)
96#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12) 120#define CKCTL_6368_ROBOSW_EN (1 << 12)
97#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13) 121#define CKCTL_6368_UTOPIA_EN (1 << 13)
98#define CKCTL_6368_PCM_CLK_EN (1 << 14) 122#define CKCTL_6368_PCM_EN (1 << 14)
99#define CKCTL_6368_USBH_CLK_EN (1 << 15) 123#define CKCTL_6368_USBH_EN (1 << 15)
100#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) 124#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
101#define CKCTL_6368_NAND_CLK_EN (1 << 17) 125#define CKCTL_6368_NAND_EN (1 << 17)
102#define CKCTL_6368_IPSEC_CLK_EN (1 << 18) 126#define CKCTL_6368_IPSEC_EN (1 << 18)
103 127
104#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ 128#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
105 CKCTL_6368_SWPKT_SAR_EN | \ 129 CKCTL_6368_SWPKT_SAR_EN | \
106 CKCTL_6368_SPI_CLK_EN | \ 130 CKCTL_6368_SPI_EN | \
107 CKCTL_6368_USBD_CLK_EN | \ 131 CKCTL_6368_USBD_EN | \
108 CKCTL_6368_SAR_CLK_EN | \ 132 CKCTL_6368_SAR_EN | \
109 CKCTL_6368_ROBOSW_CLK_EN | \ 133 CKCTL_6368_ROBOSW_EN | \
110 CKCTL_6368_UTOPIA_CLK_EN | \ 134 CKCTL_6368_UTOPIA_EN | \
111 CKCTL_6368_PCM_CLK_EN | \ 135 CKCTL_6368_PCM_EN | \
112 CKCTL_6368_USBH_CLK_EN | \ 136 CKCTL_6368_USBH_EN | \
113 CKCTL_6368_DISABLE_GLESS_EN | \ 137 CKCTL_6368_DISABLE_GLESS_EN | \
114 CKCTL_6368_NAND_CLK_EN | \ 138 CKCTL_6368_NAND_EN | \
115 CKCTL_6368_IPSEC_CLK_EN) 139 CKCTL_6368_IPSEC_EN)
116 140
117/* System PLL Control register */ 141/* System PLL Control register */
118#define PERF_SYS_PLL_CTL_REG 0x8 142#define PERF_SYS_PLL_CTL_REG 0x8
119#define SYS_PLL_SOFT_RESET 0x1 143#define SYS_PLL_SOFT_RESET 0x1
120 144
121/* Interrupt Mask register */ 145/* Interrupt Mask register */
146#define PERF_IRQMASK_6328_REG 0x20
122#define PERF_IRQMASK_6338_REG 0xc 147#define PERF_IRQMASK_6338_REG 0xc
123#define PERF_IRQMASK_6345_REG 0xc 148#define PERF_IRQMASK_6345_REG 0xc
124#define PERF_IRQMASK_6348_REG 0xc 149#define PERF_IRQMASK_6348_REG 0xc
@@ -126,6 +151,7 @@
126#define PERF_IRQMASK_6368_REG 0x20 151#define PERF_IRQMASK_6368_REG 0x20
127 152
128/* Interrupt Status register */ 153/* Interrupt Status register */
154#define PERF_IRQSTAT_6328_REG 0x28
129#define PERF_IRQSTAT_6338_REG 0x10 155#define PERF_IRQSTAT_6338_REG 0x10
130#define PERF_IRQSTAT_6345_REG 0x10 156#define PERF_IRQSTAT_6345_REG 0x10
131#define PERF_IRQSTAT_6348_REG 0x10 157#define PERF_IRQSTAT_6348_REG 0x10
@@ -133,6 +159,7 @@
133#define PERF_IRQSTAT_6368_REG 0x28 159#define PERF_IRQSTAT_6368_REG 0x28
134 160
135/* External Interrupt Configuration register */ 161/* External Interrupt Configuration register */
162#define PERF_EXTIRQ_CFG_REG_6328 0x18
136#define PERF_EXTIRQ_CFG_REG_6338 0x14 163#define PERF_EXTIRQ_CFG_REG_6338 0x14
137#define PERF_EXTIRQ_CFG_REG_6348 0x14 164#define PERF_EXTIRQ_CFG_REG_6348 0x14
138#define PERF_EXTIRQ_CFG_REG_6358 0x14 165#define PERF_EXTIRQ_CFG_REG_6358 0x14
@@ -162,8 +189,21 @@
162 189
163/* Soft Reset register */ 190/* Soft Reset register */
164#define PERF_SOFTRESET_REG 0x28 191#define PERF_SOFTRESET_REG 0x28
192#define PERF_SOFTRESET_6328_REG 0x10
165#define PERF_SOFTRESET_6368_REG 0x10 193#define PERF_SOFTRESET_6368_REG 0x10
166 194
195#define SOFTRESET_6328_SPI_MASK (1 << 0)
196#define SOFTRESET_6328_EPHY_MASK (1 << 1)
197#define SOFTRESET_6328_SAR_MASK (1 << 2)
198#define SOFTRESET_6328_ENETSW_MASK (1 << 3)
199#define SOFTRESET_6328_USBS_MASK (1 << 4)
200#define SOFTRESET_6328_USBH_MASK (1 << 5)
201#define SOFTRESET_6328_PCM_MASK (1 << 6)
202#define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
203#define SOFTRESET_6328_PCIE_MASK (1 << 8)
204#define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
205#define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
206
167#define SOFTRESET_6338_SPI_MASK (1 << 0) 207#define SOFTRESET_6338_SPI_MASK (1 << 0)
168#define SOFTRESET_6338_ENET_MASK (1 << 2) 208#define SOFTRESET_6338_ENET_MASK (1 << 2)
169#define SOFTRESET_6338_USBH_MASK (1 << 3) 209#define SOFTRESET_6338_USBH_MASK (1 << 3)
@@ -307,6 +347,8 @@
307/* Watchdog reset length register */ 347/* Watchdog reset length register */
308#define WDT_RSTLEN_REG 0x8 348#define WDT_RSTLEN_REG 0x8
309 349
350/* Watchdog soft reset register (BCM6328 only) */
351#define WDT_SOFTRESET_REG 0xc
310 352
311/************************************************************************* 353/*************************************************************************
312 * _REG relative to RSET_UARTx 354 * _REG relative to RSET_UARTx
@@ -507,6 +549,15 @@
507#define GPIO_BASEMODE_6368_MASK 0x7 549#define GPIO_BASEMODE_6368_MASK 0x7
508/* those bits must be kept as read in gpio basemode register*/ 550/* those bits must be kept as read in gpio basemode register*/
509 551
552#define GPIO_STRAPBUS_REG 0x40
553#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
554#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
555#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
556#define STRAPBUS_6368_BOOT_SEL_NAND 0
557#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
558#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
559
560
510/************************************************************************* 561/*************************************************************************
511 * _REG relative to RSET_ENET 562 * _REG relative to RSET_ENET
512 *************************************************************************/ 563 *************************************************************************/
@@ -924,6 +975,8 @@
924 * _REG relative to RSET_DDR 975 * _REG relative to RSET_DDR
925 *************************************************************************/ 976 *************************************************************************/
926 977
978#define DDR_CSEND_REG 0x8
979
927#define DDR_DMIPSPLLCFG_REG 0x18 980#define DDR_DMIPSPLLCFG_REG 0x18
928#define DMIPSPLLCFG_M1_SHIFT 0 981#define DMIPSPLLCFG_M1_SHIFT 0
929#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) 982#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
@@ -973,4 +1026,201 @@
973#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) 1026#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
974#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) 1027#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
975 1028
1029/*************************************************************************
1030 * _REG relative to RSET_RNG
1031 *************************************************************************/
1032
1033#define RNG_CTRL 0x00
1034#define RNG_EN (1 << 0)
1035
1036#define RNG_STAT 0x04
1037#define RNG_AVAIL_MASK (0xff000000)
1038
1039#define RNG_DATA 0x08
1040#define RNG_THRES 0x0c
1041#define RNG_MASK 0x10
1042
1043/*************************************************************************
1044 * _REG relative to RSET_SPI
1045 *************************************************************************/
1046
1047/* BCM 6338 SPI core */
1048#define SPI_6338_CMD 0x00 /* 16-bits register */
1049#define SPI_6338_INT_STATUS 0x02
1050#define SPI_6338_INT_MASK_ST 0x03
1051#define SPI_6338_INT_MASK 0x04
1052#define SPI_6338_ST 0x05
1053#define SPI_6338_CLK_CFG 0x06
1054#define SPI_6338_FILL_BYTE 0x07
1055#define SPI_6338_MSG_TAIL 0x09
1056#define SPI_6338_RX_TAIL 0x0b
1057#define SPI_6338_MSG_CTL 0x40
1058#define SPI_6338_MSG_DATA 0x41
1059#define SPI_6338_MSG_DATA_SIZE 0x3f
1060#define SPI_6338_RX_DATA 0x80
1061#define SPI_6338_RX_DATA_SIZE 0x3f
1062
1063/* BCM 6348 SPI core */
1064#define SPI_6348_CMD 0x00 /* 16-bits register */
1065#define SPI_6348_INT_STATUS 0x02
1066#define SPI_6348_INT_MASK_ST 0x03
1067#define SPI_6348_INT_MASK 0x04
1068#define SPI_6348_ST 0x05
1069#define SPI_6348_CLK_CFG 0x06
1070#define SPI_6348_FILL_BYTE 0x07
1071#define SPI_6348_MSG_TAIL 0x09
1072#define SPI_6348_RX_TAIL 0x0b
1073#define SPI_6348_MSG_CTL 0x40
1074#define SPI_6348_MSG_DATA 0x41
1075#define SPI_6348_MSG_DATA_SIZE 0x3f
1076#define SPI_6348_RX_DATA 0x80
1077#define SPI_6348_RX_DATA_SIZE 0x3f
1078
1079/* BCM 6358 SPI core */
1080#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1081#define SPI_6358_MSG_DATA 0x02
1082#define SPI_6358_MSG_DATA_SIZE 0x21e
1083#define SPI_6358_RX_DATA 0x400
1084#define SPI_6358_RX_DATA_SIZE 0x220
1085#define SPI_6358_CMD 0x700 /* 16-bits register */
1086#define SPI_6358_INT_STATUS 0x702
1087#define SPI_6358_INT_MASK_ST 0x703
1088#define SPI_6358_INT_MASK 0x704
1089#define SPI_6358_ST 0x705
1090#define SPI_6358_CLK_CFG 0x706
1091#define SPI_6358_FILL_BYTE 0x707
1092#define SPI_6358_MSG_TAIL 0x709
1093#define SPI_6358_RX_TAIL 0x70B
1094
1095/* BCM 6358 SPI core */
1096#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
1097#define SPI_6368_MSG_DATA 0x02
1098#define SPI_6368_MSG_DATA_SIZE 0x21e
1099#define SPI_6368_RX_DATA 0x400
1100#define SPI_6368_RX_DATA_SIZE 0x220
1101#define SPI_6368_CMD 0x700 /* 16-bits register */
1102#define SPI_6368_INT_STATUS 0x702
1103#define SPI_6368_INT_MASK_ST 0x703
1104#define SPI_6368_INT_MASK 0x704
1105#define SPI_6368_ST 0x705
1106#define SPI_6368_CLK_CFG 0x706
1107#define SPI_6368_FILL_BYTE 0x707
1108#define SPI_6368_MSG_TAIL 0x709
1109#define SPI_6368_RX_TAIL 0x70B
1110
1111/* Shared SPI definitions */
1112
1113/* Message configuration */
1114#define SPI_FD_RW 0x00
1115#define SPI_HD_W 0x01
1116#define SPI_HD_R 0x02
1117#define SPI_BYTE_CNT_SHIFT 0
1118#define SPI_MSG_TYPE_SHIFT 14
1119
1120/* Command */
1121#define SPI_CMD_NOOP 0x00
1122#define SPI_CMD_SOFT_RESET 0x01
1123#define SPI_CMD_HARD_RESET 0x02
1124#define SPI_CMD_START_IMMEDIATE 0x03
1125#define SPI_CMD_COMMAND_SHIFT 0
1126#define SPI_CMD_COMMAND_MASK 0x000f
1127#define SPI_CMD_DEVICE_ID_SHIFT 4
1128#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
1129#define SPI_CMD_ONE_BYTE_SHIFT 11
1130#define SPI_CMD_ONE_WIRE_SHIFT 12
1131#define SPI_DEV_ID_0 0
1132#define SPI_DEV_ID_1 1
1133#define SPI_DEV_ID_2 2
1134#define SPI_DEV_ID_3 3
1135
1136/* Interrupt mask */
1137#define SPI_INTR_CMD_DONE 0x01
1138#define SPI_INTR_RX_OVERFLOW 0x02
1139#define SPI_INTR_TX_UNDERFLOW 0x04
1140#define SPI_INTR_TX_OVERFLOW 0x08
1141#define SPI_INTR_RX_UNDERFLOW 0x10
1142#define SPI_INTR_CLEAR_ALL 0x1f
1143
1144/* Status */
1145#define SPI_RX_EMPTY 0x02
1146#define SPI_CMD_BUSY 0x04
1147#define SPI_SERIAL_BUSY 0x08
1148
1149/* Clock configuration */
1150#define SPI_CLK_20MHZ 0x00
1151#define SPI_CLK_0_391MHZ 0x01
1152#define SPI_CLK_0_781MHZ 0x02 /* default */
1153#define SPI_CLK_1_563MHZ 0x03
1154#define SPI_CLK_3_125MHZ 0x04
1155#define SPI_CLK_6_250MHZ 0x05
1156#define SPI_CLK_12_50MHZ 0x06
1157#define SPI_CLK_MASK 0x07
1158#define SPI_SSOFFTIME_MASK 0x38
1159#define SPI_SSOFFTIME_SHIFT 3
1160#define SPI_BYTE_SWAP 0x80
1161
1162/*************************************************************************
1163 * _REG relative to RSET_MISC
1164 *************************************************************************/
1165#define MISC_SERDES_CTRL_REG 0x0
1166#define SERDES_PCIE_EN (1 << 0)
1167#define SERDES_PCIE_EXD_EN (1 << 15)
1168
1169#define MISC_STRAPBUS_6328_REG 0x240
1170#define STRAPBUS_6328_FCVO_SHIFT 7
1171#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
1172#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
1173#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
1174
1175/*************************************************************************
1176 * _REG relative to RSET_PCIE
1177 *************************************************************************/
1178
1179#define PCIE_CONFIG2_REG 0x408
1180#define CONFIG2_BAR1_SIZE_EN 1
1181#define CONFIG2_BAR1_SIZE_MASK 0xf
1182
1183#define PCIE_IDVAL3_REG 0x43c
1184#define IDVAL3_CLASS_CODE_MASK 0xffffff
1185#define IDVAL3_SUBCLASS_SHIFT 8
1186#define IDVAL3_CLASS_SHIFT 16
1187
1188#define PCIE_DLSTATUS_REG 0x1048
1189#define DLSTATUS_PHYLINKUP (1 << 13)
1190
1191#define PCIE_BRIDGE_OPT1_REG 0x2820
1192#define OPT1_RD_BE_OPT_EN (1 << 7)
1193#define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
1194#define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
1195#define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
1196
1197#define PCIE_BRIDGE_OPT2_REG 0x2824
1198#define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
1199#define OPT2_TX_CREDIT_CHK_EN (1 << 4)
1200#define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
1201#define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
1202#define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
1203
1204#define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
1205#define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
1206#define BASEMASK_REMAP_EN (1 << 0)
1207#define BASEMASK_SWAP_EN (1 << 1)
1208#define BASEMASK_MASK_SHIFT 4
1209#define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
1210#define BASEMASK_BASE_SHIFT 20
1211#define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
1212
1213#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
1214#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
1215#define REBASE_ADDR_BASE_SHIFT 20
1216#define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
1217
1218#define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
1219#define PCIE_RC_INT_A (1 << 0)
1220#define PCIE_RC_INT_B (1 << 1)
1221#define PCIE_RC_INT_C (1 << 2)
1222#define PCIE_RC_INT_D (1 << 3)
1223
1224#define PCIE_DEVICE_OFFSET 0x8000
1225
976#endif /* BCM63XX_REGS_H_ */ 1226#endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index ef94ba73646e..30931c42379d 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
18 if (offset >= 0xfff00000) 18 if (offset >= 0xfff00000)
19 return 1; 19 return 1;
20 break; 20 break;
21 case BCM6328_CPU_ID:
21 case BCM6368_CPU_ID: 22 case BCM6368_CPU_ID:
22 if (offset >= 0xb0000000 && offset < 0xb1000000) 23 if (offset >= 0xb0000000 && offset < 0xb1000000)
23 return 1; 24 return 1;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index 5b05f186e395..418992042f6f 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -41,61 +41,26 @@ enum octeon_irq {
41 OCTEON_IRQ_TWSI, 41 OCTEON_IRQ_TWSI,
42 OCTEON_IRQ_TWSI2, 42 OCTEON_IRQ_TWSI2,
43 OCTEON_IRQ_RML, 43 OCTEON_IRQ_RML,
44 OCTEON_IRQ_TRACE0,
45 OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
46 OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
47 OCTEON_IRQ_KEY_ZERO,
48 OCTEON_IRQ_TIMER0, 44 OCTEON_IRQ_TIMER0,
49 OCTEON_IRQ_TIMER1, 45 OCTEON_IRQ_TIMER1,
50 OCTEON_IRQ_TIMER2, 46 OCTEON_IRQ_TIMER2,
51 OCTEON_IRQ_TIMER3, 47 OCTEON_IRQ_TIMER3,
52 OCTEON_IRQ_USB0, 48 OCTEON_IRQ_USB0,
53 OCTEON_IRQ_USB1, 49 OCTEON_IRQ_USB1,
54 OCTEON_IRQ_PCM,
55 OCTEON_IRQ_MPI,
56 OCTEON_IRQ_POWIQ,
57 OCTEON_IRQ_IPDPPTHR,
58 OCTEON_IRQ_MII0, 50 OCTEON_IRQ_MII0,
59 OCTEON_IRQ_MII1, 51 OCTEON_IRQ_MII1,
60 OCTEON_IRQ_BOOTDMA, 52 OCTEON_IRQ_BOOTDMA,
61 53#ifndef CONFIG_PCI_MSI
62 OCTEON_IRQ_NAND, 54 OCTEON_IRQ_LAST = 127
63 OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */ 55#endif
64 OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */
65 OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */
66 OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */
67 OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */
68 OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */
69 OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */
70 OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */
71 OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */
72 OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */
73 OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */
74 OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */
75 OCTEON_IRQ_DFA, /* Summary of DFA */
76 OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */
77 OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */
78 OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */
79 OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */
80 OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5,
81 OCTEON_IRQ_PTP,
82 OCTEON_IRQ_PEM0,
83 OCTEON_IRQ_PEM1,
84 OCTEON_IRQ_SRIO0,
85 OCTEON_IRQ_SRIO1,
86 OCTEON_IRQ_LMC0,
87 OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */
88 OCTEON_IRQ_RST,
89}; 56};
90 57
91#ifdef CONFIG_PCI_MSI 58#ifdef CONFIG_PCI_MSI
92/* 152 - 407 represent the MSI interrupts 0-255 */ 59/* 256 - 511 represent the MSI interrupts 0-255 */
93#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1) 60#define OCTEON_IRQ_MSI_BIT0 (256)
94 61
95#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) 62#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
96#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) 63#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
97#else
98#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1)
99#endif 64#endif
100 65
101#endif 66#endif
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index 1e29b9dd1d73..06367c37e1b2 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/kconfig.h>
17 18
18/* loongson internal northbridge initialization */ 19/* loongson internal northbridge initialization */
19extern void bonito_irq_init(void); 20extern void bonito_irq_init(void);
@@ -66,7 +67,7 @@ extern int mach_i8259_irq(void);
66#include <linux/interrupt.h> 67#include <linux/interrupt.h>
67static inline void do_perfcnt_IRQ(void) 68static inline void do_perfcnt_IRQ(void)
68{ 69{
69#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE) 70#if IS_ENABLED(CONFIG_OPROFILE)
70 do_IRQ(LOONGSON2_PERFCNT_IRQ); 71 do_IRQ(LOONGSON2_PERFCNT_IRQ);
71#endif 72#endif
72} 73}
diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h
new file mode 100644
index 000000000000..da96ed42f733
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * IRQ mappings for Loongson 1
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13#ifndef __ASM_MACH_LOONGSON1_IRQ_H
14#define __ASM_MACH_LOONGSON1_IRQ_H
15
16/*
17 * CPU core Interrupt Numbers
18 */
19#define MIPS_CPU_IRQ_BASE 0
20#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
21
22#define SOFTINT0_IRQ MIPS_CPU_IRQ(0)
23#define SOFTINT1_IRQ MIPS_CPU_IRQ(1)
24#define INT0_IRQ MIPS_CPU_IRQ(2)
25#define INT1_IRQ MIPS_CPU_IRQ(3)
26#define INT2_IRQ MIPS_CPU_IRQ(4)
27#define INT3_IRQ MIPS_CPU_IRQ(5)
28#define INT4_IRQ MIPS_CPU_IRQ(6)
29#define TIMER_IRQ MIPS_CPU_IRQ(7) /* cpu timer */
30
31#define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
32
33/*
34 * INT0~3 Interrupt Numbers
35 */
36#define LS1X_IRQ_BASE MIPS_CPU_IRQS
37#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
38
39#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
40#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
41#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
42#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
43#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
44#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
45#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
46#define LS1X_SPI1_IRQ LS1X_IRQ(0, 9)
47#define LS1X_AC97_IRQ LS1X_IRQ(0, 10)
48#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
49#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
50#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
51#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
52#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
53#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
54#define LS1X_PWM3_IRQ LS1X_IRQ(0, 20)
55#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
56#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
57#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
58#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
59#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
60#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
61#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
62#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
63
64#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
65#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
66#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
67#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
68
69#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE)
70
71#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)
72
73#endif /* __ASM_MACH_LOONGSON1_IRQ_H */
diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h
new file mode 100644
index 000000000000..4e18e88cebbf
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/loongson1.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Register mappings for Loongson 1
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H
14#define __ASM_MACH_LOONGSON1_LOONGSON1_H
15
16#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
17
18/* Loongson 1 Register Bases */
19#define LS1X_INTC_BASE 0x1fd01040
20#define LS1X_EHCI_BASE 0x1fe00000
21#define LS1X_OHCI_BASE 0x1fe08000
22#define LS1X_GMAC0_BASE 0x1fe10000
23#define LS1X_GMAC1_BASE 0x1fe20000
24
25#define LS1X_UART0_BASE 0x1fe40000
26#define LS1X_UART1_BASE 0x1fe44000
27#define LS1X_UART2_BASE 0x1fe48000
28#define LS1X_UART3_BASE 0x1fe4c000
29#define LS1X_CAN0_BASE 0x1fe50000
30#define LS1X_CAN1_BASE 0x1fe54000
31#define LS1X_I2C0_BASE 0x1fe58000
32#define LS1X_I2C1_BASE 0x1fe68000
33#define LS1X_I2C2_BASE 0x1fe70000
34#define LS1X_PWM_BASE 0x1fe5c000
35#define LS1X_WDT_BASE 0x1fe5c060
36#define LS1X_RTC_BASE 0x1fe64000
37#define LS1X_AC97_BASE 0x1fe74000
38#define LS1X_NAND_BASE 0x1fe78000
39#define LS1X_CLK_BASE 0x1fe78030
40
41#include <regs-clk.h>
42#include <regs-wdt.h>
43
44#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
new file mode 100644
index 000000000000..2f171617bade
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10
11#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H
12#define __ASM_MACH_LOONGSON1_PLATFORM_H
13
14#include <linux/platform_device.h>
15
16extern struct platform_device ls1x_uart_device;
17extern struct platform_device ls1x_eth0_device;
18extern struct platform_device ls1x_ehci_device;
19extern struct platform_device ls1x_rtc_device;
20
21void ls1x_serial_setup(void);
22
23#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h
new file mode 100644
index 000000000000..b871dc41b8d9
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/prom.h
@@ -0,0 +1,24 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __ASM_MACH_LOONGSON1_PROM_H
11#define __ASM_MACH_LOONGSON1_PROM_H
12
13#include <linux/io.h>
14#include <linux/init.h>
15#include <linux/irq.h>
16
17/* environment arguments from bootloader */
18extern unsigned long memsize, highmemsize;
19
20/* loongson-specific command line, env and memory initialization */
21extern char *prom_getenv(char *name);
22extern void __init prom_init_cmdline(void);
23
24#endif /* __ASM_MACH_LOONGSON1_PROM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
new file mode 100644
index 000000000000..8efa7fb9f73a
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 Clock Register Definitions.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
13#define __ASM_MACH_LOONGSON1_REGS_CLK_H
14
15#define LS1X_CLK_REG(x) \
16 ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
17
18#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
19#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
20
21/* Clock PLL Divisor Register Bits */
22#define DIV_DC_EN (0x1 << 31)
23#define DIV_DC (0x1f << 26)
24#define DIV_CPU_EN (0x1 << 25)
25#define DIV_CPU (0x1f << 20)
26#define DIV_DDR_EN (0x1 << 19)
27#define DIV_DDR (0x1f << 14)
28
29#define DIV_DC_SHIFT 26
30#define DIV_CPU_SHIFT 20
31#define DIV_DDR_SHIFT 14
32
33#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
new file mode 100644
index 000000000000..f897de68c527
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Loongson 1 watchdog register definitions.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H
13#define __ASM_MACH_LOONGSON1_REGS_WDT_H
14
15#define LS1X_WDT_REG(x) \
16 ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x)))
17
18#define LS1X_WDT_EN LS1X_WDT_REG(0x0)
19#define LS1X_WDT_SET LS1X_WDT_REG(0x4)
20#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8)
21
22#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
new file mode 100644
index 000000000000..e3680a8fb349
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MACH_LOONGSON1_WAR_H
9#define __ASM_MACH_LOONGSON1_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MACH_LOONGSON1_WAR_H */
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index d193fb68cf27..966db4be377c 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -48,7 +48,6 @@
48#define cpu_has_userlocal 1 48#define cpu_has_userlocal 1
49#define cpu_has_mips32r2 1 49#define cpu_has_mips32r2 1
50#define cpu_has_mips64r2 1 50#define cpu_has_mips64r2 1
51#define cpu_has_dc_aliases 1
52#else 51#else
53#error "Unknown Netlogic CPU" 52#error "Unknown Netlogic CPU"
54#endif 53#endif
diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
index 5e6912fdd0ed..490867b03c8f 100644
--- a/arch/mips/include/asm/mach-tx49xx/mangle-port.h
+++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
@@ -9,7 +9,7 @@
9#define ioswabb(a, x) (x) 9#define ioswabb(a, x) (x)
10#define __mem_ioswabb(a, x) (x) 10#define __mem_ioswabb(a, x) (x)
11#if defined(CONFIG_TOSHIBA_RBTX4939) && \ 11#if defined(CONFIG_TOSHIBA_RBTX4939) && \
12 (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) && \ 12 IS_ENABLED(CONFIG_SMC91X) && \
13 defined(__BIG_ENDIAN) 13 defined(__BIG_ENDIAN)
14#define NEEDS_TXX9_IOSWABW 14#define NEEDS_TXX9_IOSWABW
15extern u16 (*ioswabw)(volatile u16 *a, u16 x); 15extern u16 (*ioswabw)(volatile u16 *a, u16 x);
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
index e71ff4c317f2..5b3cb8553e9a 100644
--- a/arch/mips/include/asm/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -28,6 +28,9 @@
28#define read_c0_vpeconf0() __read_32bit_c0_register($1, 2) 28#define read_c0_vpeconf0() __read_32bit_c0_register($1, 2)
29#define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) 29#define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val)
30 30
31#define read_c0_vpeconf1() __read_32bit_c0_register($1, 3)
32#define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val)
33
31#define read_c0_tcstatus() __read_32bit_c0_register($2, 1) 34#define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
32#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) 35#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
33 36
@@ -124,6 +127,14 @@
124#define VPECONF0_XTC_SHIFT 21 127#define VPECONF0_XTC_SHIFT 21
125#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) 128#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
126 129
130/* VPEConf1 fields (per VPE) */
131#define VPECONF1_NCP1_SHIFT 0
132#define VPECONF1_NCP1 (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
133#define VPECONF1_NCP2_SHIFT 10
134#define VPECONF1_NCP2 (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
135#define VPECONF1_NCX_SHIFT 20
136#define VPECONF1_NCX (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
137
127/* TCStatus fields (per TC) */ 138/* TCStatus fields (per TC) */
128#define TCSTATUS_TASID (_ULCAST_(0xff)) 139#define TCSTATUS_TASID (_ULCAST_(0xff))
129#define TCSTATUS_IXMT_SHIFT 10 140#define TCSTATUS_IXMT_SHIFT 10
@@ -350,6 +361,8 @@ do { \
350#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) 361#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val)
351#define read_vpe_c0_vpeconf0() mftc0(1, 2) 362#define read_vpe_c0_vpeconf0() mftc0(1, 2)
352#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) 363#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
364#define read_vpe_c0_vpeconf1() mftc0(1, 3)
365#define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val)
353#define read_vpe_c0_count() mftc0(9, 0) 366#define read_vpe_c0_count() mftc0(9, 0)
354#define write_vpe_c0_count(val) mttc0(9, 0, val) 367#define write_vpe_c0_count(val) mttc0(9, 0, val)
355#define read_vpe_c0_status() mftc0(12, 0) 368#define read_vpe_c0_status() mftc0(12, 0)
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 530008048c62..7531ecd654d6 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -117,6 +117,8 @@ search_module_dbetables(unsigned long addr)
117#define MODULE_PROC_FAMILY "RM9000 " 117#define MODULE_PROC_FAMILY "RM9000 "
118#elif defined CONFIG_CPU_SB1 118#elif defined CONFIG_CPU_SB1
119#define MODULE_PROC_FAMILY "SB1 " 119#define MODULE_PROC_FAMILY "SB1 "
120#elif defined CONFIG_CPU_LOONGSON1
121#define MODULE_PROC_FAMILY "LOONGSON1 "
120#elif defined CONFIG_CPU_LOONGSON2 122#elif defined CONFIG_CPU_LOONGSON2
121#define MODULE_PROC_FAMILY "LOONGSON2 " 123#define MODULE_PROC_FAMILY "LOONGSON2 "
122#elif defined CONFIG_CPU_CAVIUM_OCTEON 124#elif defined CONFIG_CPU_CAVIUM_OCTEON
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index bf7d41deb9be..7b63a6b722a0 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -47,7 +47,9 @@
47#define CPU_BLOCKID_MAP 10 47#define CPU_BLOCKID_MAP 10
48 48
49#define LSU_DEFEATURE 0x304 49#define LSU_DEFEATURE 0x304
50#define LSU_CERRLOG_REGID 0x09 50#define LSU_DEBUG_ADDR 0x305
51#define LSU_DEBUG_DATA0 0x306
52#define LSU_CERRLOG_REGID 0x309
51#define SCHED_DEFEATURE 0x700 53#define SCHED_DEFEATURE 0x700
52 54
53/* Offsets of interest from the 'MAP' Block */ 55/* Offsets of interest from the 'MAP' Block */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 86cc3391e50c..2c63f9754640 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -36,6 +36,9 @@
36#define __NLM_HAL_IOMAP_H__ 36#define __NLM_HAL_IOMAP_H__
37 37
38#define XLP_DEFAULT_IO_BASE 0x18000000 38#define XLP_DEFAULT_IO_BASE 0x18000000
39#define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE
40#define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000
41
39#define NMI_BASE 0xbfc00000 42#define NMI_BASE 0xbfc00000
40#define XLP_IO_CLK 133333333 43#define XLP_IO_CLK 133333333
41 44
@@ -129,7 +132,7 @@
129#define PCI_DEVICE_ID_NLM_PIC 0x1003 132#define PCI_DEVICE_ID_NLM_PIC 0x1003
130#define PCI_DEVICE_ID_NLM_PCIE 0x1004 133#define PCI_DEVICE_ID_NLM_PCIE 0x1004
131#define PCI_DEVICE_ID_NLM_EHCI 0x1007 134#define PCI_DEVICE_ID_NLM_EHCI 0x1007
132#define PCI_DEVICE_ID_NLM_ILK 0x1008 135#define PCI_DEVICE_ID_NLM_OHCI 0x1008
133#define PCI_DEVICE_ID_NLM_NAE 0x1009 136#define PCI_DEVICE_ID_NLM_NAE 0x1009
134#define PCI_DEVICE_ID_NLM_POE 0x100A 137#define PCI_DEVICE_ID_NLM_POE 0x100A
135#define PCI_DEVICE_ID_NLM_FMN 0x100B 138#define PCI_DEVICE_ID_NLM_FMN 0x100B
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
new file mode 100644
index 000000000000..66c323d1bd7d
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
@@ -0,0 +1,76 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_PCIBUS_H__
36#define __NLM_HAL_PCIBUS_H__
37
38/* PCIE Memory and IO regions */
39#define PCIE_MEM_BASE 0xd0000000ULL
40#define PCIE_MEM_LIMIT 0xdfffffffULL
41#define PCIE_IO_BASE 0x14000000ULL
42#define PCIE_IO_LIMIT 0x15ffffffULL
43
44#define PCIE_BRIDGE_CMD 0x1
45#define PCIE_BRIDGE_MSI_CAP 0x14
46#define PCIE_BRIDGE_MSI_ADDRL 0x15
47#define PCIE_BRIDGE_MSI_ADDRH 0x16
48#define PCIE_BRIDGE_MSI_DATA 0x17
49
50/* XLP Global PCIE configuration space registers */
51#define PCIE_BYTE_SWAP_MEM_BASE 0x247
52#define PCIE_BYTE_SWAP_MEM_LIM 0x248
53#define PCIE_BYTE_SWAP_IO_BASE 0x249
54#define PCIE_BYTE_SWAP_IO_LIM 0x24A
55#define PCIE_MSI_STATUS 0x25A
56#define PCIE_MSI_EN 0x25B
57#define PCIE_INT_EN0 0x261
58
59/* PCIE_MSI_EN */
60#define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
61
62/* PCIE_INT_EN0 */
63#define PCIE_MSI_INT_EN (1 << 9)
64
65#ifndef __ASSEMBLY__
66
67#define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
68#define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
69#define nlm_get_pcie_base(node, inst) \
70 nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
71#define nlm_get_pcie_regbase(node, inst) \
72 (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
73
74int xlp_pcie_link_irt(int link);
75#endif
76#endif /* __NLM_HAL_PCIBUS_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index b6628f7ccf74..ad8b80233a63 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -201,7 +201,11 @@
201#define PIC_NUM_USB_IRTS 6 201#define PIC_NUM_USB_IRTS 6
202#define PIC_IRT_USB_0_INDEX 115 202#define PIC_IRT_USB_0_INDEX 115
203#define PIC_IRT_EHCI_0_INDEX 115 203#define PIC_IRT_EHCI_0_INDEX 115
204#define PIC_IRT_OHCI_0_INDEX 116
205#define PIC_IRT_OHCI_1_INDEX 117
204#define PIC_IRT_EHCI_1_INDEX 118 206#define PIC_IRT_EHCI_1_INDEX 118
207#define PIC_IRT_OHCI_2_INDEX 119
208#define PIC_IRT_OHCI_3_INDEX 120
205#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX) 209#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX)
206/* 115 to 120 */ 210/* 115 to 120 */
207#define PIC_IRT_GDX_INDEX 121 211#define PIC_IRT_GDX_INDEX 121
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/usb.h b/arch/mips/include/asm/netlogic/xlp-hal/usb.h
new file mode 100644
index 000000000000..a9cd350dfb6c
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/usb.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef __NLM_HAL_USB_H__
36#define __NLM_HAL_USB_H__
37
38#define USB_CTL_0 0x01
39#define USB_PHY_0 0x0A
40#define USB_PHY_RESET 0x01
41#define USB_PHY_PORT_RESET_0 0x10
42#define USB_PHY_PORT_RESET_1 0x20
43#define USB_CONTROLLER_RESET 0x01
44#define USB_INT_STATUS 0x0E
45#define USB_INT_EN 0x0F
46#define USB_PHY_INTERRUPT_EN 0x01
47#define USB_OHCI_INTERRUPT_EN 0x02
48#define USB_OHCI_INTERRUPT1_EN 0x04
49#define USB_OHCI_INTERRUPT2_EN 0x08
50#define USB_CTRL_INTERRUPT_EN 0x10
51
52#ifndef __ASSEMBLY__
53
54#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r)
55#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v)
56#define nlm_get_usb_pcibase(node, inst) \
57 nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
58#define nlm_get_usb_hcd_base(node, inst) \
59 nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst))
60#define nlm_get_usb_regbase(node, inst) \
61 (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
62
63#endif
64#endif /* __NLM_HAL_USB_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 1540588e396d..7e47209327a5 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -35,8 +35,21 @@
35#ifndef _NLM_HAL_XLP_H 35#ifndef _NLM_HAL_XLP_H
36#define _NLM_HAL_XLP_H 36#define _NLM_HAL_XLP_H
37 37
38#define PIC_UART_0_IRQ 17 38#define PIC_UART_0_IRQ 17
39#define PIC_UART_1_IRQ 18 39#define PIC_UART_1_IRQ 18
40#define PIC_PCIE_LINK_0_IRQ 19
41#define PIC_PCIE_LINK_1_IRQ 20
42#define PIC_PCIE_LINK_2_IRQ 21
43#define PIC_PCIE_LINK_3_IRQ 22
44#define PIC_EHCI_0_IRQ 23
45#define PIC_EHCI_1_IRQ 24
46#define PIC_OHCI_0_IRQ 25
47#define PIC_OHCI_1_IRQ 26
48#define PIC_OHCI_2_IRQ 27
49#define PIC_OHCI_3_IRQ 28
50#define PIC_MMC_IRQ 29
51#define PIC_I2C_0_IRQ 30
52#define PIC_I2C_1_IRQ 31
40 53
41#ifndef __ASSEMBLY__ 54#ifndef __ASSEMBLY__
42 55
diff --git a/arch/mips/include/asm/netlogic/xlr/bridge.h b/arch/mips/include/asm/netlogic/xlr/bridge.h
new file mode 100644
index 000000000000..2d02428c4f1b
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/bridge.h
@@ -0,0 +1,104 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34#ifndef _ASM_NLM_BRIDGE_H_
35#define _ASM_NLM_BRIDGE_H_
36
37#define BRIDGE_DRAM_0_BAR 0
38#define BRIDGE_DRAM_1_BAR 1
39#define BRIDGE_DRAM_2_BAR 2
40#define BRIDGE_DRAM_3_BAR 3
41#define BRIDGE_DRAM_4_BAR 4
42#define BRIDGE_DRAM_5_BAR 5
43#define BRIDGE_DRAM_6_BAR 6
44#define BRIDGE_DRAM_7_BAR 7
45#define BRIDGE_DRAM_CHN_0_MTR_0_BAR 8
46#define BRIDGE_DRAM_CHN_0_MTR_1_BAR 9
47#define BRIDGE_DRAM_CHN_0_MTR_2_BAR 10
48#define BRIDGE_DRAM_CHN_0_MTR_3_BAR 11
49#define BRIDGE_DRAM_CHN_0_MTR_4_BAR 12
50#define BRIDGE_DRAM_CHN_0_MTR_5_BAR 13
51#define BRIDGE_DRAM_CHN_0_MTR_6_BAR 14
52#define BRIDGE_DRAM_CHN_0_MTR_7_BAR 15
53#define BRIDGE_DRAM_CHN_1_MTR_0_BAR 16
54#define BRIDGE_DRAM_CHN_1_MTR_1_BAR 17
55#define BRIDGE_DRAM_CHN_1_MTR_2_BAR 18
56#define BRIDGE_DRAM_CHN_1_MTR_3_BAR 19
57#define BRIDGE_DRAM_CHN_1_MTR_4_BAR 20
58#define BRIDGE_DRAM_CHN_1_MTR_5_BAR 21
59#define BRIDGE_DRAM_CHN_1_MTR_6_BAR 22
60#define BRIDGE_DRAM_CHN_1_MTR_7_BAR 23
61#define BRIDGE_CFG_BAR 24
62#define BRIDGE_PHNX_IO_BAR 25
63#define BRIDGE_FLASH_BAR 26
64#define BRIDGE_SRAM_BAR 27
65#define BRIDGE_HTMEM_BAR 28
66#define BRIDGE_HTINT_BAR 29
67#define BRIDGE_HTPIC_BAR 30
68#define BRIDGE_HTSM_BAR 31
69#define BRIDGE_HTIO_BAR 32
70#define BRIDGE_HTCFG_BAR 33
71#define BRIDGE_PCIXCFG_BAR 34
72#define BRIDGE_PCIXMEM_BAR 35
73#define BRIDGE_PCIXIO_BAR 36
74#define BRIDGE_DEVICE_MASK 37
75#define BRIDGE_AERR_INTR_LOG1 38
76#define BRIDGE_AERR_INTR_LOG2 39
77#define BRIDGE_AERR_INTR_LOG3 40
78#define BRIDGE_AERR_DEV_STAT 41
79#define BRIDGE_AERR1_LOG1 42
80#define BRIDGE_AERR1_LOG2 43
81#define BRIDGE_AERR1_LOG3 44
82#define BRIDGE_AERR1_DEV_STAT 45
83#define BRIDGE_AERR_INTR_EN 46
84#define BRIDGE_AERR_UPG 47
85#define BRIDGE_AERR_CLEAR 48
86#define BRIDGE_AERR1_CLEAR 49
87#define BRIDGE_SBE_COUNTS 50
88#define BRIDGE_DBE_COUNTS 51
89#define BRIDGE_BITERR_INT_EN 52
90
91#define BRIDGE_SYS2IO_CREDITS 53
92#define BRIDGE_EVNT_CNT_CTRL1 54
93#define BRIDGE_EVNT_COUNTER1 55
94#define BRIDGE_EVNT_CNT_CTRL2 56
95#define BRIDGE_EVNT_COUNTER2 57
96#define BRIDGE_RESERVED1 58
97
98#define BRIDGE_DEFEATURE 59
99#define BRIDGE_SCRATCH0 60
100#define BRIDGE_SCRATCH1 61
101#define BRIDGE_SCRATCH2 62
102#define BRIDGE_SCRATCH3 63
103
104#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/flash.h b/arch/mips/include/asm/netlogic/xlr/flash.h
new file mode 100644
index 000000000000..f8aca5472b6c
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/flash.h
@@ -0,0 +1,55 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34#ifndef _ASM_NLM_FLASH_H_
35#define _ASM_NLM_FLASH_H_
36
37#define FLASH_CSBASE_ADDR(cs) (cs)
38#define FLASH_CSADDR_MASK(cs) (0x10 + (cs))
39#define FLASH_CSDEV_PARM(cs) (0x20 + (cs))
40#define FLASH_CSTIME_PARMA(cs) (0x30 + (cs))
41#define FLASH_CSTIME_PARMB(cs) (0x40 + (cs))
42
43#define FLASH_INT_MASK 0x50
44#define FLASH_INT_STATUS 0x60
45#define FLASH_ERROR_STATUS 0x70
46#define FLASH_ERROR_ADDR 0x80
47
48#define FLASH_NAND_CLE(cs) (0x90 + (cs))
49#define FLASH_NAND_ALE(cs) (0xa0 + (cs))
50
51#define FLASH_NAND_CSDEV_PARAM 0x000041e6
52#define FLASH_NAND_CSTIME_PARAMA 0x4f400e22
53#define FLASH_NAND_CSTIME_PARAMB 0x000083cf
54
55#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h
index 51f6ad4aeb14..8492e835b110 100644
--- a/arch/mips/include/asm/netlogic/xlr/gpio.h
+++ b/arch/mips/include/asm/netlogic/xlr/gpio.h
@@ -35,39 +35,40 @@
35#ifndef _ASM_NLM_GPIO_H 35#ifndef _ASM_NLM_GPIO_H
36#define _ASM_NLM_GPIO_H 36#define _ASM_NLM_GPIO_H
37 37
38#define NETLOGIC_GPIO_INT_EN_REG 0 38#define GPIO_INT_EN_REG 0
39#define NETLOGIC_GPIO_INPUT_INVERSION_REG 1 39#define GPIO_INPUT_INVERSION_REG 1
40#define NETLOGIC_GPIO_IO_DIR_REG 2 40#define GPIO_IO_DIR_REG 2
41#define NETLOGIC_GPIO_IO_DATA_WR_REG 3 41#define GPIO_IO_DATA_WR_REG 3
42#define NETLOGIC_GPIO_IO_DATA_RD_REG 4 42#define GPIO_IO_DATA_RD_REG 4
43 43
44#define NETLOGIC_GPIO_SWRESET_REG 8 44#define GPIO_SWRESET_REG 8
45#define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9 45#define GPIO_DRAM1_CNTRL_REG 9
46#define NETLOGIC_GPIO_DRAM1_RATIO_REG 10 46#define GPIO_DRAM1_RATIO_REG 10
47#define NETLOGIC_GPIO_DRAM1_RESET_REG 11 47#define GPIO_DRAM1_RESET_REG 11
48#define NETLOGIC_GPIO_DRAM1_STATUS_REG 12 48#define GPIO_DRAM1_STATUS_REG 12
49#define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13 49#define GPIO_DRAM2_CNTRL_REG 13
50#define NETLOGIC_GPIO_DRAM2_RATIO_REG 14 50#define GPIO_DRAM2_RATIO_REG 14
51#define NETLOGIC_GPIO_DRAM2_RESET_REG 15 51#define GPIO_DRAM2_RESET_REG 15
52#define NETLOGIC_GPIO_DRAM2_STATUS_REG 16 52#define GPIO_DRAM2_STATUS_REG 16
53 53
54#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21 54#define GPIO_PWRON_RESET_CFG_REG 21
55#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24 55#define GPIO_BIST_ALL_GO_STATUS_REG 24
56#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25 56#define GPIO_BIST_CPU_GO_STATUS_REG 25
57#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26 57#define GPIO_BIST_DEV_GO_STATUS_REG 26
58 58
59#define NETLOGIC_GPIO_FUSE_BANK_REG 35 59#define GPIO_FUSE_BANK_REG 35
60#define NETLOGIC_GPIO_CPU_RESET_REG 40 60#define GPIO_CPU_RESET_REG 40
61#define NETLOGIC_GPIO_RNG_REG 43 61#define GPIO_RNG_REG 43
62 62
63#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17 63#define PWRON_RESET_PCMCIA_BOOT 17
64#define NETLOGIC_GPIO_LED_BITMAP 0x1700000
65#define NETLOGIC_GPIO_LED_0_SHIFT 20
66#define NETLOGIC_GPIO_LED_1_SHIFT 24
67 64
68#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01 65#define GPIO_LED_BITMAP 0x1700000
69#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 66#define GPIO_LED_0_SHIFT 20
70#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 67#define GPIO_LED_1_SHIFT 24
71#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04 68
69#define GPIO_LED_OUTPUT_CODE_RESET 0x01
70#define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
71#define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
72#define GPIO_LED_OUTPUT_CODE_MAIN 0x04
72 73
73#endif 74#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
deleted file mode 100644
index 5ff8c93198de..000000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Helper functions for FPA setup.
32 *
33 */
34#ifndef __CVMX_HELPER_H_FPA__
35#define __CVMX_HELPER_H_FPA__
36
37/**
38 * Allocate memory and initialize the FPA pools using memory
39 * from cvmx-bootmem. Sizes of each element in the pools is
40 * controlled by the cvmx-config.h header file. Specifying
41 * zero for any parameter will cause that FPA pool to not be
42 * setup. This is useful if you aren't using some of the
43 * hardware and want to save memory.
44 *
45 * @packet_buffers:
46 * Number of packet buffers to allocate
47 * @work_queue_entries:
48 * Number of work queue entries
49 * @pko_buffers:
50 * PKO Command buffers. You should at minimum have two per
51 * each PKO queue.
52 * @tim_buffers:
53 * TIM ring buffer command queues. At least two per timer bucket
54 * is recommened.
55 * @dfa_buffers:
56 * DFA command buffer. A relatively small (32 for example)
57 * number should work.
58 * Returns Zero on success, non-zero if out of memory
59 */
60extern int cvmx_helper_initialize_fpa(int packet_buffers,
61 int work_queue_entries, int pko_buffers,
62 int tim_buffers, int dfa_buffers);
63
64#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h
index 3169cd79f2ac..0ac6b9f412be 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper.h
@@ -61,8 +61,6 @@ typedef union {
61 } s; 61 } s;
62} cvmx_helper_link_info_t; 62} cvmx_helper_link_info_t;
63 63
64#include "cvmx-helper-fpa.h"
65
66#include <asm/octeon/cvmx-helper-errata.h> 64#include <asm/octeon/cvmx-helper-errata.h>
67#include "cvmx-helper-loop.h" 65#include "cvmx-helper-loop.h"
68#include "cvmx-helper-npi.h" 66#include "cvmx-helper-npi.h"
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index f72f768cd3a4..1e2486e23573 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -215,11 +215,6 @@ struct octeon_cf_data {
215 int dma_engine; /* -1 for no DMA */ 215 int dma_engine; /* -1 for no DMA */
216}; 216};
217 217
218struct octeon_i2c_data {
219 unsigned int sys_freq;
220 unsigned int i2c_freq;
221};
222
223extern void octeon_write_lcd(const char *s); 218extern void octeon_write_lcd(const char *s);
224extern void octeon_check_cpu_bist(void); 219extern void octeon_check_cpu_bist(void);
225extern int octeon_get_boot_debug_flag(void); 220extern int octeon_get_boot_debug_flag(void);
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index 7206d445bab8..8808bf548b99 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -20,9 +20,6 @@
20extern int early_init_dt_scan_memory_arch(unsigned long node, 20extern int early_init_dt_scan_memory_arch(unsigned long node,
21 const char *uname, int depth, void *data); 21 const char *uname, int depth, void *data);
22 22
23extern int reserve_mem_mach(unsigned long addr, unsigned long size);
24extern void free_mem_mach(unsigned long addr, unsigned long size);
25
26extern void device_tree_init(void); 23extern void device_tree_init(void);
27 24
28static inline unsigned long pci_address_to_pio(phys_addr_t address) 25static inline unsigned long pci_address_to_pio(phys_addr_t address)
diff --git a/arch/mips/include/asm/smtc.h b/arch/mips/include/asm/smtc.h
index c9736fc06325..8935426a56ab 100644
--- a/arch/mips/include/asm/smtc.h
+++ b/arch/mips/include/asm/smtc.h
@@ -33,6 +33,12 @@ typedef long asiduse;
33#endif 33#endif
34#endif 34#endif
35 35
36/*
37 * VPE Management information
38 */
39
40#define MAX_SMTC_VPES MAX_SMTC_TLBS /* FIXME: May not always be true. */
41
36extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; 42extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
37 43
38struct mm_struct; 44struct mm_struct;
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index 653a412c036c..3b92efef56d3 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -687,7 +687,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
687 __MODULE_JAL(__copy_user) \ 687 __MODULE_JAL(__copy_user) \
688 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 688 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
689 : \ 689 : \
690 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 690 : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31", \
691 DADDI_SCRATCH, "memory"); \ 691 DADDI_SCRATCH, "memory"); \
692 __cu_len_r; \ 692 __cu_len_r; \
693}) 693})
@@ -797,7 +797,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
797 ".set\treorder" \ 797 ".set\treorder" \
798 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 798 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
799 : \ 799 : \
800 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 800 : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31", \
801 DADDI_SCRATCH, "memory"); \ 801 DADDI_SCRATCH, "memory"); \
802 __cu_len_r; \ 802 __cu_len_r; \
803}) 803})
@@ -820,7 +820,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
820 ".set\treorder" \ 820 ".set\treorder" \
821 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ 821 : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \
822 : \ 822 : \
823 : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ 823 : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31", \
824 DADDI_SCRATCH, "memory"); \ 824 DADDI_SCRATCH, "memory"); \
825 __cu_len_r; \ 825 __cu_len_r; \
826}) 826})
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 440a21dab575..3d9f75f7ffc9 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -6,6 +6,7 @@
6 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 6 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
7 * Copyright (C) 2005 Maciej W. Rozycki 7 * Copyright (C) 2005 Maciej W. Rozycki
8 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
9 * Copyright (C) 2012 MIPS Technologies, Inc.
9 */ 10 */
10 11
11#include <linux/types.h> 12#include <linux/types.h>
@@ -62,8 +63,10 @@ void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b)
62 63
63Ip_u2u1s3(_addiu); 64Ip_u2u1s3(_addiu);
64Ip_u3u1u2(_addu); 65Ip_u3u1u2(_addu);
65Ip_u2u1u3(_andi);
66Ip_u3u1u2(_and); 66Ip_u3u1u2(_and);
67Ip_u2u1u3(_andi);
68Ip_u1u2s3(_bbit0);
69Ip_u1u2s3(_bbit1);
67Ip_u1u2s3(_beq); 70Ip_u1u2s3(_beq);
68Ip_u1u2s3(_beql); 71Ip_u1u2s3(_beql);
69Ip_u1s2(_bgez); 72Ip_u1s2(_bgez);
@@ -72,55 +75,54 @@ Ip_u1s2(_bltz);
72Ip_u1s2(_bltzl); 75Ip_u1s2(_bltzl);
73Ip_u1u2s3(_bne); 76Ip_u1u2s3(_bne);
74Ip_u2s3u1(_cache); 77Ip_u2s3u1(_cache);
75Ip_u1u2u3(_dmfc0);
76Ip_u1u2u3(_dmtc0);
77Ip_u2u1s3(_daddiu); 78Ip_u2u1s3(_daddiu);
78Ip_u3u1u2(_daddu); 79Ip_u3u1u2(_daddu);
80Ip_u2u1msbu3(_dins);
81Ip_u2u1msbu3(_dinsm);
82Ip_u1u2u3(_dmfc0);
83Ip_u1u2u3(_dmtc0);
84Ip_u2u1u3(_drotr);
85Ip_u2u1u3(_drotr32);
79Ip_u2u1u3(_dsll); 86Ip_u2u1u3(_dsll);
80Ip_u2u1u3(_dsll32); 87Ip_u2u1u3(_dsll32);
81Ip_u2u1u3(_dsra); 88Ip_u2u1u3(_dsra);
82Ip_u2u1u3(_dsrl); 89Ip_u2u1u3(_dsrl);
83Ip_u2u1u3(_dsrl32); 90Ip_u2u1u3(_dsrl32);
84Ip_u2u1u3(_drotr);
85Ip_u2u1u3(_drotr32);
86Ip_u3u1u2(_dsubu); 91Ip_u3u1u2(_dsubu);
87Ip_0(_eret); 92Ip_0(_eret);
88Ip_u1(_j); 93Ip_u1(_j);
89Ip_u1(_jal); 94Ip_u1(_jal);
90Ip_u1(_jr); 95Ip_u1(_jr);
91Ip_u2s3u1(_ld); 96Ip_u2s3u1(_ld);
97Ip_u3u1u2(_ldx);
92Ip_u2s3u1(_ll); 98Ip_u2s3u1(_ll);
93Ip_u2s3u1(_lld); 99Ip_u2s3u1(_lld);
94Ip_u1s2(_lui); 100Ip_u1s2(_lui);
95Ip_u2s3u1(_lw); 101Ip_u2s3u1(_lw);
102Ip_u3u1u2(_lwx);
96Ip_u1u2u3(_mfc0); 103Ip_u1u2u3(_mfc0);
97Ip_u1u2u3(_mtc0); 104Ip_u1u2u3(_mtc0);
98Ip_u2u1u3(_ori);
99Ip_u3u1u2(_or); 105Ip_u3u1u2(_or);
106Ip_u2u1u3(_ori);
100Ip_u2s3u1(_pref); 107Ip_u2s3u1(_pref);
101Ip_0(_rfe); 108Ip_0(_rfe);
109Ip_u2u1u3(_rotr);
102Ip_u2s3u1(_sc); 110Ip_u2s3u1(_sc);
103Ip_u2s3u1(_scd); 111Ip_u2s3u1(_scd);
104Ip_u2s3u1(_sd); 112Ip_u2s3u1(_sd);
105Ip_u2u1u3(_sll); 113Ip_u2u1u3(_sll);
106Ip_u2u1u3(_sra); 114Ip_u2u1u3(_sra);
107Ip_u2u1u3(_srl); 115Ip_u2u1u3(_srl);
108Ip_u2u1u3(_rotr);
109Ip_u3u1u2(_subu); 116Ip_u3u1u2(_subu);
110Ip_u2s3u1(_sw); 117Ip_u2s3u1(_sw);
118Ip_u1(_syscall);
111Ip_0(_tlbp); 119Ip_0(_tlbp);
112Ip_0(_tlbr); 120Ip_0(_tlbr);
113Ip_0(_tlbwi); 121Ip_0(_tlbwi);
114Ip_0(_tlbwr); 122Ip_0(_tlbwr);
115Ip_u3u1u2(_xor); 123Ip_u3u1u2(_xor);
116Ip_u2u1u3(_xori); 124Ip_u2u1u3(_xori);
117Ip_u2u1msbu3(_dins); 125
118Ip_u2u1msbu3(_dinsm);
119Ip_u1(_syscall);
120Ip_u1u2s3(_bbit0);
121Ip_u1u2s3(_bbit1);
122Ip_u3u1u2(_lwx);
123Ip_u3u1u2(_ldx);
124 126
125/* Handle labels. */ 127/* Handle labels. */
126struct uasm_label { 128struct uasm_label {
@@ -145,37 +147,37 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
145 147
146/* convenience macros for instructions */ 148/* convenience macros for instructions */
147#ifdef CONFIG_64BIT 149#ifdef CONFIG_64BIT
150# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
151# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
152# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
148# define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off) 153# define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off)
149# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off) 154# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
155# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
156# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
157# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
158# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
150# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh) 159# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh)
151# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh) 160# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh)
152# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh) 161# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh)
153# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_dsrl_safe(buf, rs, rt, sh) 162# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_dsrl_safe(buf, rs, rt, sh)
154# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
155# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
156# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
157# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
158# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
159# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd) 163# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd)
160# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off) 164# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off)
161# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
162# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
163#else 165#else
166# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
167# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
168# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
164# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off) 169# define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off)
165# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off) 170# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
171# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
172# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
173# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
174# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
166# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh) 175# define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh)
167# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh) 176# define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh)
168# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh) 177# define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
169# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh) 178# define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
170# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
171# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
172# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
173# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
174# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
175# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd) 179# define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd)
176# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off) 180# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
177# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
178# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
179#endif 181#endif
180 182
181#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off) 183#define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off)
@@ -183,19 +185,10 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
183#define uasm_i_beqzl(buf, rs, off) uasm_i_beql(buf, rs, 0, off) 185#define uasm_i_beqzl(buf, rs, off) uasm_i_beql(buf, rs, 0, off)
184#define uasm_i_bnez(buf, rs, off) uasm_i_bne(buf, rs, 0, off) 186#define uasm_i_bnez(buf, rs, off) uasm_i_bne(buf, rs, 0, off)
185#define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off) 187#define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off)
188#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
186#define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b) 189#define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b)
187#define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0) 190#define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0)
188#define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1) 191#define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1)
189#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
190
191static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
192 unsigned int a2, unsigned int a3)
193{
194 if (a3 < 32)
195 uasm_i_dsrl(p, a1, a2, a3);
196 else
197 uasm_i_dsrl32(p, a1, a2, a3 - 32);
198}
199 192
200static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1, 193static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
201 unsigned int a2, unsigned int a3) 194 unsigned int a2, unsigned int a3)
@@ -215,6 +208,15 @@ static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
215 uasm_i_dsll32(p, a1, a2, a3 - 32); 208 uasm_i_dsll32(p, a1, a2, a3 - 32);
216} 209}
217 210
211static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
212 unsigned int a2, unsigned int a3)
213{
214 if (a3 < 32)
215 uasm_i_dsrl(p, a1, a2, a3);
216 else
217 uasm_i_dsrl32(p, a1, a2, a3 - 32);
218}
219
218/* Handle relocations. */ 220/* Handle relocations. */
219struct uasm_reloc { 221struct uasm_reloc {
220 u32 *addr; 222 u32 *addr;
@@ -234,16 +236,16 @@ void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
234int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr); 236int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr);
235 237
236/* Convenience functions for labeled branches. */ 238/* Convenience functions for labeled branches. */
237void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
238void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid); 239void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid);
240void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
241 unsigned int bit, int lid);
242void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
243 unsigned int bit, int lid);
239void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); 244void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
240void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); 245void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
246void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
247void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
248void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
241void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, 249void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
242 unsigned int reg2, int lid); 250 unsigned int reg2, int lid);
243void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid); 251void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
244void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
245void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
246void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
247 unsigned int bit, int lid);
248void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
249 unsigned int bit, int lid);
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f4630e1082ab..1b51046191e8 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -190,6 +190,7 @@ void __init check_wait(void)
190 case CPU_CAVIUM_OCTEON_PLUS: 190 case CPU_CAVIUM_OCTEON_PLUS:
191 case CPU_CAVIUM_OCTEON2: 191 case CPU_CAVIUM_OCTEON2:
192 case CPU_JZRISC: 192 case CPU_JZRISC:
193 case CPU_LOONGSON1:
193 case CPU_XLR: 194 case CPU_XLR:
194 case CPU_XLP: 195 case CPU_XLP:
195 cpu_wait = r4k_wait; 196 cpu_wait = r4k_wait;
@@ -330,6 +331,154 @@ static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
330#endif 331#endif
331} 332}
332 333
334static char unknown_isa[] __cpuinitdata = KERN_ERR \
335 "Unsupported ISA type, c0.config0: %d.";
336
337static inline unsigned int decode_config0(struct cpuinfo_mips *c)
338{
339 unsigned int config0;
340 int isa;
341
342 config0 = read_c0_config();
343
344 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
345 c->options |= MIPS_CPU_TLB;
346 isa = (config0 & MIPS_CONF_AT) >> 13;
347 switch (isa) {
348 case 0:
349 switch ((config0 & MIPS_CONF_AR) >> 10) {
350 case 0:
351 c->isa_level = MIPS_CPU_ISA_M32R1;
352 break;
353 case 1:
354 c->isa_level = MIPS_CPU_ISA_M32R2;
355 break;
356 default:
357 goto unknown;
358 }
359 break;
360 case 2:
361 switch ((config0 & MIPS_CONF_AR) >> 10) {
362 case 0:
363 c->isa_level = MIPS_CPU_ISA_M64R1;
364 break;
365 case 1:
366 c->isa_level = MIPS_CPU_ISA_M64R2;
367 break;
368 default:
369 goto unknown;
370 }
371 break;
372 default:
373 goto unknown;
374 }
375
376 return config0 & MIPS_CONF_M;
377
378unknown:
379 panic(unknown_isa, config0);
380}
381
382static inline unsigned int decode_config1(struct cpuinfo_mips *c)
383{
384 unsigned int config1;
385
386 config1 = read_c0_config1();
387
388 if (config1 & MIPS_CONF1_MD)
389 c->ases |= MIPS_ASE_MDMX;
390 if (config1 & MIPS_CONF1_WR)
391 c->options |= MIPS_CPU_WATCH;
392 if (config1 & MIPS_CONF1_CA)
393 c->ases |= MIPS_ASE_MIPS16;
394 if (config1 & MIPS_CONF1_EP)
395 c->options |= MIPS_CPU_EJTAG;
396 if (config1 & MIPS_CONF1_FP) {
397 c->options |= MIPS_CPU_FPU;
398 c->options |= MIPS_CPU_32FPR;
399 }
400 if (cpu_has_tlb)
401 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
402
403 return config1 & MIPS_CONF_M;
404}
405
406static inline unsigned int decode_config2(struct cpuinfo_mips *c)
407{
408 unsigned int config2;
409
410 config2 = read_c0_config2();
411
412 if (config2 & MIPS_CONF2_SL)
413 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
414
415 return config2 & MIPS_CONF_M;
416}
417
418static inline unsigned int decode_config3(struct cpuinfo_mips *c)
419{
420 unsigned int config3;
421
422 config3 = read_c0_config3();
423
424 if (config3 & MIPS_CONF3_SM)
425 c->ases |= MIPS_ASE_SMARTMIPS;
426 if (config3 & MIPS_CONF3_DSP)
427 c->ases |= MIPS_ASE_DSP;
428 if (config3 & MIPS_CONF3_VINT)
429 c->options |= MIPS_CPU_VINT;
430 if (config3 & MIPS_CONF3_VEIC)
431 c->options |= MIPS_CPU_VEIC;
432 if (config3 & MIPS_CONF3_MT)
433 c->ases |= MIPS_ASE_MIPSMT;
434 if (config3 & MIPS_CONF3_ULRI)
435 c->options |= MIPS_CPU_ULRI;
436
437 return config3 & MIPS_CONF_M;
438}
439
440static inline unsigned int decode_config4(struct cpuinfo_mips *c)
441{
442 unsigned int config4;
443
444 config4 = read_c0_config4();
445
446 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
447 && cpu_has_tlb)
448 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
449
450 c->kscratch_mask = (config4 >> 16) & 0xff;
451
452 return config4 & MIPS_CONF_M;
453}
454
455static void __cpuinit decode_configs(struct cpuinfo_mips *c)
456{
457 int ok;
458
459 /* MIPS32 or MIPS64 compliant CPU. */
460 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
461 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
462
463 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
464
465 ok = decode_config0(c); /* Read Config registers. */
466 BUG_ON(!ok); /* Arch spec violation! */
467 if (ok)
468 ok = decode_config1(c);
469 if (ok)
470 ok = decode_config2(c);
471 if (ok)
472 ok = decode_config3(c);
473 if (ok)
474 ok = decode_config4(c);
475
476 mips_probe_watch_registers(c);
477
478 if (cpu_has_mips_r2)
479 c->core = read_c0_ebase() & 0x3ff;
480}
481
333#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 482#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
334 | MIPS_CPU_COUNTER) 483 | MIPS_CPU_COUNTER)
335 484
@@ -638,155 +787,19 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
638 MIPS_CPU_32FPR; 787 MIPS_CPU_32FPR;
639 c->tlbsize = 64; 788 c->tlbsize = 64;
640 break; 789 break;
641 } 790 case PRID_IMP_LOONGSON1:
642} 791 decode_configs(c);
643
644static char unknown_isa[] __cpuinitdata = KERN_ERR \
645 "Unsupported ISA type, c0.config0: %d.";
646 792
647static inline unsigned int decode_config0(struct cpuinfo_mips *c) 793 c->cputype = CPU_LOONGSON1;
648{
649 unsigned int config0;
650 int isa;
651 794
652 config0 = read_c0_config(); 795 switch (c->processor_id & PRID_REV_MASK) {
653 796 case PRID_REV_LOONGSON1B:
654 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 797 __cpu_name[cpu] = "Loongson 1B";
655 c->options |= MIPS_CPU_TLB;
656 isa = (config0 & MIPS_CONF_AT) >> 13;
657 switch (isa) {
658 case 0:
659 switch ((config0 & MIPS_CONF_AR) >> 10) {
660 case 0:
661 c->isa_level = MIPS_CPU_ISA_M32R1;
662 break;
663 case 1:
664 c->isa_level = MIPS_CPU_ISA_M32R2;
665 break; 798 break;
666 default:
667 goto unknown;
668 } 799 }
669 break;
670 case 2:
671 switch ((config0 & MIPS_CONF_AR) >> 10) {
672 case 0:
673 c->isa_level = MIPS_CPU_ISA_M64R1;
674 break;
675 case 1:
676 c->isa_level = MIPS_CPU_ISA_M64R2;
677 break;
678 default:
679 goto unknown;
680 }
681 break;
682 default:
683 goto unknown;
684 }
685
686 return config0 & MIPS_CONF_M;
687
688unknown:
689 panic(unknown_isa, config0);
690}
691 800
692static inline unsigned int decode_config1(struct cpuinfo_mips *c) 801 break;
693{
694 unsigned int config1;
695
696 config1 = read_c0_config1();
697
698 if (config1 & MIPS_CONF1_MD)
699 c->ases |= MIPS_ASE_MDMX;
700 if (config1 & MIPS_CONF1_WR)
701 c->options |= MIPS_CPU_WATCH;
702 if (config1 & MIPS_CONF1_CA)
703 c->ases |= MIPS_ASE_MIPS16;
704 if (config1 & MIPS_CONF1_EP)
705 c->options |= MIPS_CPU_EJTAG;
706 if (config1 & MIPS_CONF1_FP) {
707 c->options |= MIPS_CPU_FPU;
708 c->options |= MIPS_CPU_32FPR;
709 } 802 }
710 if (cpu_has_tlb)
711 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
712
713 return config1 & MIPS_CONF_M;
714}
715
716static inline unsigned int decode_config2(struct cpuinfo_mips *c)
717{
718 unsigned int config2;
719
720 config2 = read_c0_config2();
721
722 if (config2 & MIPS_CONF2_SL)
723 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
724
725 return config2 & MIPS_CONF_M;
726}
727
728static inline unsigned int decode_config3(struct cpuinfo_mips *c)
729{
730 unsigned int config3;
731
732 config3 = read_c0_config3();
733
734 if (config3 & MIPS_CONF3_SM)
735 c->ases |= MIPS_ASE_SMARTMIPS;
736 if (config3 & MIPS_CONF3_DSP)
737 c->ases |= MIPS_ASE_DSP;
738 if (config3 & MIPS_CONF3_VINT)
739 c->options |= MIPS_CPU_VINT;
740 if (config3 & MIPS_CONF3_VEIC)
741 c->options |= MIPS_CPU_VEIC;
742 if (config3 & MIPS_CONF3_MT)
743 c->ases |= MIPS_ASE_MIPSMT;
744 if (config3 & MIPS_CONF3_ULRI)
745 c->options |= MIPS_CPU_ULRI;
746
747 return config3 & MIPS_CONF_M;
748}
749
750static inline unsigned int decode_config4(struct cpuinfo_mips *c)
751{
752 unsigned int config4;
753
754 config4 = read_c0_config4();
755
756 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
757 && cpu_has_tlb)
758 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
759
760 c->kscratch_mask = (config4 >> 16) & 0xff;
761
762 return config4 & MIPS_CONF_M;
763}
764
765static void __cpuinit decode_configs(struct cpuinfo_mips *c)
766{
767 int ok;
768
769 /* MIPS32 or MIPS64 compliant CPU. */
770 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
771 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
772
773 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
774
775 ok = decode_config0(c); /* Read Config registers. */
776 BUG_ON(!ok); /* Arch spec violation! */
777 if (ok)
778 ok = decode_config1(c);
779 if (ok)
780 ok = decode_config2(c);
781 if (ok)
782 ok = decode_config3(c);
783 if (ok)
784 ok = decode_config4(c);
785
786 mips_probe_watch_registers(c);
787
788 if (cpu_has_mips_r2)
789 c->core = read_c0_ebase() & 0x3ff;
790} 803}
791 804
792static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 805static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index eb5e394a4650..2f28d3b55687 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1559,6 +1559,11 @@ init_hw_perf_events(void)
1559 mipspmu.general_event_map = &mipsxxcore_event_map; 1559 mipspmu.general_event_map = &mipsxxcore_event_map;
1560 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1560 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1561 break; 1561 break;
1562 case CPU_LOONGSON1:
1563 mipspmu.name = "mips/loongson1";
1564 mipspmu.general_event_map = &mipsxxcore_event_map;
1565 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1566 break;
1562 case CPU_CAVIUM_OCTEON: 1567 case CPU_CAVIUM_OCTEON:
1563 case CPU_CAVIUM_OCTEON_PLUS: 1568 case CPU_CAVIUM_OCTEON_PLUS:
1564 case CPU_CAVIUM_OCTEON2: 1569 case CPU_CAVIUM_OCTEON2:
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index f11b2bbb826d..028f6f837ef9 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -35,16 +35,6 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
35 return add_memory_region(base, size, BOOT_MEM_RAM); 35 return add_memory_region(base, size, BOOT_MEM_RAM);
36} 36}
37 37
38int __init reserve_mem_mach(unsigned long addr, unsigned long size)
39{
40 return reserve_bootmem(addr, size, BOOTMEM_DEFAULT);
41}
42
43void __init free_mem_mach(unsigned long addr, unsigned long size)
44{
45 return free_bootmem(addr, size);
46}
47
48void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) 38void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
49{ 39{
50 return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); 40 return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
@@ -77,25 +67,6 @@ void __init early_init_devtree(void *params)
77 of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL); 67 of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL);
78} 68}
79 69
80void __init device_tree_init(void)
81{
82 unsigned long base, size;
83
84 if (!initial_boot_params)
85 return;
86
87 base = virt_to_phys((void *)initial_boot_params);
88 size = be32_to_cpu(initial_boot_params->totalsize);
89
90 /* Before we do anything, lets reserve the dt blob */
91 reserve_mem_mach(base, size);
92
93 unflatten_device_tree();
94
95 /* free the space reserved for the dt blob */
96 free_mem_mach(base, size);
97}
98
99void __init __dt_setup_arch(struct boot_param_header *bph) 70void __init __dt_setup_arch(struct boot_param_header *bph)
100{ 71{
101 if (be32_to_cpu(bph->magic) != OF_DT_HEADER) { 72 if (be32_to_cpu(bph->magic) != OF_DT_HEADER) {
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 1268392f1d27..31637d8c8738 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -102,7 +102,9 @@ asmlinkage __cpuinit void start_secondary(void)
102 102
103#ifdef CONFIG_MIPS_MT_SMTC 103#ifdef CONFIG_MIPS_MT_SMTC
104 /* Only do cpu_probe for first TC of CPU */ 104 /* Only do cpu_probe for first TC of CPU */
105 if ((read_c0_tcbind() & TCBIND_CURTC) == 0) 105 if ((read_c0_tcbind() & TCBIND_CURTC) != 0)
106 __cpu_name[smp_processor_id()] = __cpu_name[0];
107 else
106#endif /* CONFIG_MIPS_MT_SMTC */ 108#endif /* CONFIG_MIPS_MT_SMTC */
107 cpu_probe(); 109 cpu_probe();
108 cpu_report(); 110 cpu_report();
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 15b5f3cfd20c..1d47843d3cc0 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -86,6 +86,13 @@ struct smtc_ipi_q IPIQ[NR_CPUS];
86static struct smtc_ipi_q freeIPIq; 86static struct smtc_ipi_q freeIPIq;
87 87
88 88
89/*
90 * Number of FPU contexts for each VPE
91 */
92
93static int smtc_nconf1[MAX_SMTC_VPES];
94
95
89/* Forward declarations */ 96/* Forward declarations */
90 97
91void ipi_decode(struct smtc_ipi *); 98void ipi_decode(struct smtc_ipi *);
@@ -174,9 +181,9 @@ static int __init tintq(char *str)
174 181
175__setup("tintq=", tintq); 182__setup("tintq=", tintq);
176 183
177static int imstuckcount[2][8]; 184static int imstuckcount[MAX_SMTC_VPES][8];
178/* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */ 185/* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
179static int vpemask[2][8] = { 186static int vpemask[MAX_SMTC_VPES][8] = {
180 {0, 0, 1, 0, 0, 0, 0, 1}, 187 {0, 0, 1, 0, 0, 0, 0, 1},
181 {0, 0, 0, 0, 0, 0, 0, 1} 188 {0, 0, 0, 0, 0, 0, 0, 1}
182}; 189};
@@ -331,6 +338,22 @@ int __init smtc_build_cpu_map(int start_cpu_slot)
331 338
332static void smtc_tc_setup(int vpe, int tc, int cpu) 339static void smtc_tc_setup(int vpe, int tc, int cpu)
333{ 340{
341 static int cp1contexts[MAX_SMTC_VPES];
342
343 /*
344 * Make a local copy of the available FPU contexts in order
345 * to keep track of TCs that can have one.
346 */
347 if (tc == 1)
348 {
349 /*
350 * FIXME: Multi-core SMTC hasn't been tested and the
351 * maximum number of VPEs may change.
352 */
353 cp1contexts[0] = smtc_nconf1[0] - 1;
354 cp1contexts[1] = smtc_nconf1[1];
355 }
356
334 settc(tc); 357 settc(tc);
335 write_tc_c0_tchalt(TCHALT_H); 358 write_tc_c0_tchalt(TCHALT_H);
336 mips_ihb(); 359 mips_ihb();
@@ -343,22 +366,29 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
343 * an active IPI queue. 366 * an active IPI queue.
344 */ 367 */
345 write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16); 368 write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
346 /* Bind tc to vpe */ 369
370 /* Bind TC to VPE. */
347 write_tc_c0_tcbind(vpe); 371 write_tc_c0_tcbind(vpe);
372
348 /* In general, all TCs should have the same cpu_data indications. */ 373 /* In general, all TCs should have the same cpu_data indications. */
349 memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips)); 374 memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
350 /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */ 375
351 if (cpu_data[0].cputype == CPU_34K || 376 /* Check to see if there is a FPU context available for this TC. */
352 cpu_data[0].cputype == CPU_1004K) 377 if (!cp1contexts[vpe])
353 cpu_data[cpu].options &= ~MIPS_CPU_FPU; 378 cpu_data[cpu].options &= ~MIPS_CPU_FPU;
379 else
380 cp1contexts[vpe]--;
381
382 /* Store the TC and VPE into the cpu_data structure. */
354 cpu_data[cpu].vpe_id = vpe; 383 cpu_data[cpu].vpe_id = vpe;
355 cpu_data[cpu].tc_id = tc; 384 cpu_data[cpu].tc_id = tc;
356 /* Multi-core SMTC hasn't been tested, but be prepared */ 385
386 /* FIXME: Multi-core SMTC hasn't been tested, but be prepared. */
357 cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff; 387 cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff;
358} 388}
359 389
360/* 390/*
361 * Tweak to get Count registes in as close a sync as possible. The 391 * Tweak to get Count registers synced as closely as possible. The
362 * value seems good for 34K-class cores. 392 * value seems good for 34K-class cores.
363 */ 393 */
364 394
@@ -466,6 +496,24 @@ void smtc_prepare_cpus(int cpus)
466 smtc_configure_tlb(); 496 smtc_configure_tlb();
467 497
468 for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) { 498 for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) {
499 /* Get number of CP1 contexts for each VPE. */
500 if (tc == 0)
501 {
502 /*
503 * Do not call settc() for TC0 or the FPU context
504 * value will be incorrect. Besides, we know that
505 * we are TC0 anyway.
506 */
507 smtc_nconf1[0] = ((read_vpe_c0_vpeconf1() &
508 VPECONF1_NCP1) >> VPECONF1_NCP1_SHIFT);
509 if (nvpe == 2)
510 {
511 settc(1);
512 smtc_nconf1[1] = ((read_vpe_c0_vpeconf1() &
513 VPECONF1_NCP1) >> VPECONF1_NCP1_SHIFT);
514 settc(0);
515 }
516 }
469 if (tcpervpe[vpe] == 0) 517 if (tcpervpe[vpe] == 0)
470 continue; 518 continue;
471 if (vpe != 0) 519 if (vpe != 0)
@@ -479,6 +527,18 @@ void smtc_prepare_cpus(int cpus)
479 */ 527 */
480 if (tc != 0) { 528 if (tc != 0) {
481 smtc_tc_setup(vpe, tc, cpu); 529 smtc_tc_setup(vpe, tc, cpu);
530 if (vpe != 0) {
531 /*
532 * Set MVP bit (possibly again). Do it
533 * here to catch CPUs that have no TCs
534 * bound to the VPE at reset. In that
535 * case, a TC must be bound to the VPE
536 * before we can set VPEControl[MVP]
537 */
538 write_vpe_c0_vpeconf0(
539 read_vpe_c0_vpeconf0() |
540 VPECONF0_MVP);
541 }
482 cpu++; 542 cpu++;
483 } 543 }
484 printk(" %d", tc); 544 printk(" %d", tc);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index c3c293543703..9be3df1fa8a4 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1253,6 +1253,7 @@ static inline void parity_protection_init(void)
1253 1253
1254 case CPU_5KC: 1254 case CPU_5KC:
1255 case CPU_5KE: 1255 case CPU_5KE:
1256 case CPU_LOONGSON1:
1256 write_c0_ecc(0x80000000); 1257 write_c0_ecc(0x80000000);
1257 back_to_back_c0_hazard(); 1258 back_to_back_c0_hazard();
1258 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1259 /* Set the PE bit (bit 31) in the c0_errctl register. */
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 2a7c74fc15fc..399a50a541d4 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -2,7 +2,7 @@
2# Makefile for MIPS-specific library files.. 2# Makefile for MIPS-specific library files..
3# 3#
4 4
5lib-y += csum_partial.o delay.o memcpy.o memcpy-inatomic.o memset.o \ 5lib-y += csum_partial.o delay.o memcpy.o memset.o \
6 strlen_user.o strncpy_user.o strnlen_user.o uncached.o 6 strlen_user.o strncpy_user.o strnlen_user.o uncached.o
7 7
8obj-y += iomap.o 8obj-y += iomap.o
diff --git a/arch/mips/lib/memcpy-inatomic.S b/arch/mips/lib/memcpy-inatomic.S
deleted file mode 100644
index 68853a038d3f..000000000000
--- a/arch/mips/lib/memcpy-inatomic.S
+++ /dev/null
@@ -1,451 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Unified implementation of memcpy, memmove and the __copy_user backend.
7 *
8 * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org)
9 * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
10 * Copyright (C) 2002 Broadcom, Inc.
11 * memcpy/copy_user author: Mark Vandevoorde
12 * Copyright (C) 2007 Maciej W. Rozycki
13 *
14 * Mnemonic names for arguments to memcpy/__copy_user
15 */
16
17/*
18 * Hack to resolve longstanding prefetch issue
19 *
20 * Prefetching may be fatal on some systems if we're prefetching beyond the
21 * end of memory on some systems. It's also a seriously bad idea on non
22 * dma-coherent systems.
23 */
24#ifdef CONFIG_DMA_NONCOHERENT
25#undef CONFIG_CPU_HAS_PREFETCH
26#endif
27#ifdef CONFIG_MIPS_MALTA
28#undef CONFIG_CPU_HAS_PREFETCH
29#endif
30
31#include <asm/asm.h>
32#include <asm/asm-offsets.h>
33#include <asm/regdef.h>
34
35#define dst a0
36#define src a1
37#define len a2
38
39/*
40 * Spec
41 *
42 * memcpy copies len bytes from src to dst and sets v0 to dst.
43 * It assumes that
44 * - src and dst don't overlap
45 * - src is readable
46 * - dst is writable
47 * memcpy uses the standard calling convention
48 *
49 * __copy_user copies up to len bytes from src to dst and sets a2 (len) to
50 * the number of uncopied bytes due to an exception caused by a read or write.
51 * __copy_user assumes that src and dst don't overlap, and that the call is
52 * implementing one of the following:
53 * copy_to_user
54 * - src is readable (no exceptions when reading src)
55 * copy_from_user
56 * - dst is writable (no exceptions when writing dst)
57 * __copy_user uses a non-standard calling convention; see
58 * include/asm-mips/uaccess.h
59 *
60 * When an exception happens on a load, the handler must
61 # ensure that all of the destination buffer is overwritten to prevent
62 * leaking information to user mode programs.
63 */
64
65/*
66 * Implementation
67 */
68
69/*
70 * The exception handler for loads requires that:
71 * 1- AT contain the address of the byte just past the end of the source
72 * of the copy,
73 * 2- src_entry <= src < AT, and
74 * 3- (dst - src) == (dst_entry - src_entry),
75 * The _entry suffix denotes values when __copy_user was called.
76 *
77 * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user
78 * (2) is met by incrementing src by the number of bytes copied
79 * (3) is met by not doing loads between a pair of increments of dst and src
80 *
81 * The exception handlers for stores adjust len (if necessary) and return.
82 * These handlers do not need to overwrite any data.
83 *
84 * For __rmemcpy and memmove an exception is always a kernel bug, therefore
85 * they're not protected.
86 */
87
88#define EXC(inst_reg,addr,handler) \
899: inst_reg, addr; \
90 .section __ex_table,"a"; \
91 PTR 9b, handler; \
92 .previous
93
94/*
95 * Only on the 64-bit kernel we can made use of 64-bit registers.
96 */
97#ifdef CONFIG_64BIT
98#define USE_DOUBLE
99#endif
100
101#ifdef USE_DOUBLE
102
103#define LOAD ld
104#define LOADL ldl
105#define LOADR ldr
106#define STOREL sdl
107#define STORER sdr
108#define STORE sd
109#define ADD daddu
110#define SUB dsubu
111#define SRL dsrl
112#define SRA dsra
113#define SLL dsll
114#define SLLV dsllv
115#define SRLV dsrlv
116#define NBYTES 8
117#define LOG_NBYTES 3
118
119/*
120 * As we are sharing code base with the mips32 tree (which use the o32 ABI
121 * register definitions). We need to redefine the register definitions from
122 * the n64 ABI register naming to the o32 ABI register naming.
123 */
124#undef t0
125#undef t1
126#undef t2
127#undef t3
128#define t0 $8
129#define t1 $9
130#define t2 $10
131#define t3 $11
132#define t4 $12
133#define t5 $13
134#define t6 $14
135#define t7 $15
136
137#else
138
139#define LOAD lw
140#define LOADL lwl
141#define LOADR lwr
142#define STOREL swl
143#define STORER swr
144#define STORE sw
145#define ADD addu
146#define SUB subu
147#define SRL srl
148#define SLL sll
149#define SRA sra
150#define SLLV sllv
151#define SRLV srlv
152#define NBYTES 4
153#define LOG_NBYTES 2
154
155#endif /* USE_DOUBLE */
156
157#ifdef CONFIG_CPU_LITTLE_ENDIAN
158#define LDFIRST LOADR
159#define LDREST LOADL
160#define STFIRST STORER
161#define STREST STOREL
162#define SHIFT_DISCARD SLLV
163#else
164#define LDFIRST LOADL
165#define LDREST LOADR
166#define STFIRST STOREL
167#define STREST STORER
168#define SHIFT_DISCARD SRLV
169#endif
170
171#define FIRST(unit) ((unit)*NBYTES)
172#define REST(unit) (FIRST(unit)+NBYTES-1)
173#define UNIT(unit) FIRST(unit)
174
175#define ADDRMASK (NBYTES-1)
176
177 .text
178 .set noreorder
179#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
180 .set noat
181#else
182 .set at=v1
183#endif
184
185/*
186 * A combined memcpy/__copy_user
187 * __copy_user sets len to 0 for success; else to an upper bound of
188 * the number of uncopied bytes.
189 * memcpy sets v0 to dst.
190 */
191 .align 5
192LEAF(__copy_user_inatomic)
193 /*
194 * Note: dst & src may be unaligned, len may be 0
195 * Temps
196 */
197#define rem t8
198
199 /*
200 * The "issue break"s below are very approximate.
201 * Issue delays for dcache fills will perturb the schedule, as will
202 * load queue full replay traps, etc.
203 *
204 * If len < NBYTES use byte operations.
205 */
206 PREF( 0, 0(src) )
207 PREF( 1, 0(dst) )
208 sltu t2, len, NBYTES
209 and t1, dst, ADDRMASK
210 PREF( 0, 1*32(src) )
211 PREF( 1, 1*32(dst) )
212 bnez t2, .Lcopy_bytes_checklen
213 and t0, src, ADDRMASK
214 PREF( 0, 2*32(src) )
215 PREF( 1, 2*32(dst) )
216 bnez t1, .Ldst_unaligned
217 nop
218 bnez t0, .Lsrc_unaligned_dst_aligned
219 /*
220 * use delay slot for fall-through
221 * src and dst are aligned; need to compute rem
222 */
223.Lboth_aligned:
224 SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
225 beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES
226 and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES)
227 PREF( 0, 3*32(src) )
228 PREF( 1, 3*32(dst) )
229 .align 4
2301:
231EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
232EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
233EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
234EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
235 SUB len, len, 8*NBYTES
236EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy)
237EXC( LOAD t7, UNIT(5)(src), .Ll_exc_copy)
238 STORE t0, UNIT(0)(dst)
239 STORE t1, UNIT(1)(dst)
240EXC( LOAD t0, UNIT(6)(src), .Ll_exc_copy)
241EXC( LOAD t1, UNIT(7)(src), .Ll_exc_copy)
242 ADD src, src, 8*NBYTES
243 ADD dst, dst, 8*NBYTES
244 STORE t2, UNIT(-6)(dst)
245 STORE t3, UNIT(-5)(dst)
246 STORE t4, UNIT(-4)(dst)
247 STORE t7, UNIT(-3)(dst)
248 STORE t0, UNIT(-2)(dst)
249 STORE t1, UNIT(-1)(dst)
250 PREF( 0, 8*32(src) )
251 PREF( 1, 8*32(dst) )
252 bne len, rem, 1b
253 nop
254
255 /*
256 * len == rem == the number of bytes left to copy < 8*NBYTES
257 */
258.Lcleanup_both_aligned:
259 beqz len, .Ldone
260 sltu t0, len, 4*NBYTES
261 bnez t0, .Lless_than_4units
262 and rem, len, (NBYTES-1) # rem = len % NBYTES
263 /*
264 * len >= 4*NBYTES
265 */
266EXC( LOAD t0, UNIT(0)(src), .Ll_exc)
267EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy)
268EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy)
269EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy)
270 SUB len, len, 4*NBYTES
271 ADD src, src, 4*NBYTES
272 STORE t0, UNIT(0)(dst)
273 STORE t1, UNIT(1)(dst)
274 STORE t2, UNIT(2)(dst)
275 STORE t3, UNIT(3)(dst)
276 .set reorder /* DADDI_WAR */
277 ADD dst, dst, 4*NBYTES
278 beqz len, .Ldone
279 .set noreorder
280.Lless_than_4units:
281 /*
282 * rem = len % NBYTES
283 */
284 beq rem, len, .Lcopy_bytes
285 nop
2861:
287EXC( LOAD t0, 0(src), .Ll_exc)
288 ADD src, src, NBYTES
289 SUB len, len, NBYTES
290 STORE t0, 0(dst)
291 .set reorder /* DADDI_WAR */
292 ADD dst, dst, NBYTES
293 bne rem, len, 1b
294 .set noreorder
295
296 /*
297 * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
298 * A loop would do only a byte at a time with possible branch
299 * mispredicts. Can't do an explicit LOAD dst,mask,or,STORE
300 * because can't assume read-access to dst. Instead, use
301 * STREST dst, which doesn't require read access to dst.
302 *
303 * This code should perform better than a simple loop on modern,
304 * wide-issue mips processors because the code has fewer branches and
305 * more instruction-level parallelism.
306 */
307#define bits t2
308 beqz len, .Ldone
309 ADD t1, dst, len # t1 is just past last byte of dst
310 li bits, 8*NBYTES
311 SLL rem, len, 3 # rem = number of bits to keep
312EXC( LOAD t0, 0(src), .Ll_exc)
313 SUB bits, bits, rem # bits = number of bits to discard
314 SHIFT_DISCARD t0, t0, bits
315 STREST t0, -1(t1)
316 jr ra
317 move len, zero
318.Ldst_unaligned:
319 /*
320 * dst is unaligned
321 * t0 = src & ADDRMASK
322 * t1 = dst & ADDRMASK; T1 > 0
323 * len >= NBYTES
324 *
325 * Copy enough bytes to align dst
326 * Set match = (src and dst have same alignment)
327 */
328#define match rem
329EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc)
330 ADD t2, zero, NBYTES
331EXC( LDREST t3, REST(0)(src), .Ll_exc_copy)
332 SUB t2, t2, t1 # t2 = number of bytes copied
333 xor match, t0, t1
334 STFIRST t3, FIRST(0)(dst)
335 beq len, t2, .Ldone
336 SUB len, len, t2
337 ADD dst, dst, t2
338 beqz match, .Lboth_aligned
339 ADD src, src, t2
340
341.Lsrc_unaligned_dst_aligned:
342 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
343 PREF( 0, 3*32(src) )
344 beqz t0, .Lcleanup_src_unaligned
345 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
346 PREF( 1, 3*32(dst) )
3471:
348/*
349 * Avoid consecutive LD*'s to the same register since some mips
350 * implementations can't issue them in the same cycle.
351 * It's OK to load FIRST(N+1) before REST(N) because the two addresses
352 * are to the same unit (unless src is aligned, but it's not).
353 */
354EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
355EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy)
356 SUB len, len, 4*NBYTES
357EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
358EXC( LDREST t1, REST(1)(src), .Ll_exc_copy)
359EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy)
360EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy)
361EXC( LDREST t2, REST(2)(src), .Ll_exc_copy)
362EXC( LDREST t3, REST(3)(src), .Ll_exc_copy)
363 PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed)
364 ADD src, src, 4*NBYTES
365#ifdef CONFIG_CPU_SB1
366 nop # improves slotting
367#endif
368 STORE t0, UNIT(0)(dst)
369 STORE t1, UNIT(1)(dst)
370 STORE t2, UNIT(2)(dst)
371 STORE t3, UNIT(3)(dst)
372 PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed)
373 .set reorder /* DADDI_WAR */
374 ADD dst, dst, 4*NBYTES
375 bne len, rem, 1b
376 .set noreorder
377
378.Lcleanup_src_unaligned:
379 beqz len, .Ldone
380 and rem, len, NBYTES-1 # rem = len % NBYTES
381 beq rem, len, .Lcopy_bytes
382 nop
3831:
384EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc)
385EXC( LDREST t0, REST(0)(src), .Ll_exc_copy)
386 ADD src, src, NBYTES
387 SUB len, len, NBYTES
388 STORE t0, 0(dst)
389 .set reorder /* DADDI_WAR */
390 ADD dst, dst, NBYTES
391 bne len, rem, 1b
392 .set noreorder
393
394.Lcopy_bytes_checklen:
395 beqz len, .Ldone
396 nop
397.Lcopy_bytes:
398 /* 0 < len < NBYTES */
399#define COPY_BYTE(N) \
400EXC( lb t0, N(src), .Ll_exc); \
401 SUB len, len, 1; \
402 beqz len, .Ldone; \
403 sb t0, N(dst)
404
405 COPY_BYTE(0)
406 COPY_BYTE(1)
407#ifdef USE_DOUBLE
408 COPY_BYTE(2)
409 COPY_BYTE(3)
410 COPY_BYTE(4)
411 COPY_BYTE(5)
412#endif
413EXC( lb t0, NBYTES-2(src), .Ll_exc)
414 SUB len, len, 1
415 jr ra
416 sb t0, NBYTES-2(dst)
417.Ldone:
418 jr ra
419 nop
420 END(__copy_user_inatomic)
421
422.Ll_exc_copy:
423 /*
424 * Copy bytes from src until faulting load address (or until a
425 * lb faults)
426 *
427 * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28)
428 * may be more than a byte beyond the last address.
429 * Hence, the lb below may get an exception.
430 *
431 * Assumes src < THREAD_BUADDR($28)
432 */
433 LOAD t0, TI_TASK($28)
434 nop
435 LOAD t0, THREAD_BUADDR(t0)
4361:
437EXC( lb t1, 0(src), .Ll_exc)
438 ADD src, src, 1
439 sb t1, 0(dst) # can't fault -- we're copy_from_user
440 .set reorder /* DADDI_WAR */
441 ADD dst, dst, 1
442 bne src, t0, 1b
443 .set noreorder
444.Ll_exc:
445 LOAD t0, TI_TASK($28)
446 nop
447 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
448 nop
449 SUB len, AT, t0 # len number of uncopied bytes
450 jr ra
451 nop
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index 56a1f85a1ce8..65192c06781e 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -183,6 +183,14 @@
183#endif 183#endif
184 184
185/* 185/*
186 * t6 is used as a flag to note inatomic mode.
187 */
188LEAF(__copy_user_inatomic)
189 b __copy_user_common
190 li t6, 1
191 END(__copy_user_inatomic)
192
193/*
186 * A combined memcpy/__copy_user 194 * A combined memcpy/__copy_user
187 * __copy_user sets len to 0 for success; else to an upper bound of 195 * __copy_user sets len to 0 for success; else to an upper bound of
188 * the number of uncopied bytes. 196 * the number of uncopied bytes.
@@ -193,6 +201,8 @@ LEAF(memcpy) /* a0=dst a1=src a2=len */
193 move v0, dst /* return value */ 201 move v0, dst /* return value */
194.L__memcpy: 202.L__memcpy:
195FEXPORT(__copy_user) 203FEXPORT(__copy_user)
204 li t6, 0 /* not inatomic */
205__copy_user_common:
196 /* 206 /*
197 * Note: dst & src may be unaligned, len may be 0 207 * Note: dst & src may be unaligned, len may be 0
198 * Temps 208 * Temps
@@ -458,6 +468,7 @@ EXC( lb t1, 0(src), .Ll_exc)
458 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address 468 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
459 nop 469 nop
460 SUB len, AT, t0 # len number of uncopied bytes 470 SUB len, AT, t0 # len number of uncopied bytes
471 bnez t6, .Ldone /* Skip the zeroing part if inatomic */
461 /* 472 /*
462 * Here's where we rely on src and dst being incremented in tandem, 473 * Here's where we rely on src and dst being incremented in tandem,
463 * See (3) above. 474 * See (3) above.
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
new file mode 100644
index 000000000000..237fa214de9f
--- /dev/null
+++ b/arch/mips/loongson1/Kconfig
@@ -0,0 +1,21 @@
1if MACH_LOONGSON1
2
3choice
4 prompt "Machine Type"
5
6config LOONGSON1_LS1B
7 bool "Loongson LS1B board"
8 select CEVT_R4K
9 select CSRC_R4K
10 select SYS_HAS_CPU_LOONGSON1B
11 select DMA_NONCOHERENT
12 select BOOT_ELF32
13 select IRQ_CPU
14 select SYS_SUPPORTS_32BIT_KERNEL
15 select SYS_SUPPORTS_LITTLE_ENDIAN
16 select SYS_SUPPORTS_HIGHMEM
17 select SYS_HAS_EARLY_PRINTK
18
19endchoice
20
21endif # MACH_LOONGSON1
diff --git a/arch/mips/loongson1/Makefile b/arch/mips/loongson1/Makefile
new file mode 100644
index 000000000000..9719c75886f5
--- /dev/null
+++ b/arch/mips/loongson1/Makefile
@@ -0,0 +1,11 @@
1#
2# Common code for all Loongson 1 based systems
3#
4
5obj-$(CONFIG_MACH_LOONGSON1) += common/
6
7#
8# Loongson LS1B board
9#
10
11obj-$(CONFIG_LOONGSON1_LS1B) += ls1b/
diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform
new file mode 100644
index 000000000000..99bdefe627af
--- /dev/null
+++ b/arch/mips/loongson1/Platform
@@ -0,0 +1,7 @@
1cflags-$(CONFIG_CPU_LOONGSON1) += \
2 $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
3 -Wa,-mips32r2 -Wa,--trap
4
5platform-$(CONFIG_MACH_LOONGSON1) += loongson1/
6cflags-$(CONFIG_MACH_LOONGSON1) += -I$(srctree)/arch/mips/include/asm/mach-loongson1
7load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80100000
diff --git a/arch/mips/loongson1/common/Makefile b/arch/mips/loongson1/common/Makefile
new file mode 100644
index 000000000000..b2797709ef5b
--- /dev/null
+++ b/arch/mips/loongson1/common/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for common code of loongson1 based machines.
3#
4
5obj-y += clock.o irq.o platform.o prom.o reset.o setup.o
diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/common/clock.c
new file mode 100644
index 000000000000..2d98fb030596
--- /dev/null
+++ b/arch/mips/loongson1/common/clock.c
@@ -0,0 +1,165 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <linux/module.h>
11#include <linux/list.h>
12#include <linux/mutex.h>
13#include <linux/clk.h>
14#include <linux/err.h>
15#include <asm/clock.h>
16#include <asm/time.h>
17
18#include <loongson1.h>
19
20static LIST_HEAD(clocks);
21static DEFINE_MUTEX(clocks_mutex);
22
23struct clk *clk_get(struct device *dev, const char *name)
24{
25 struct clk *c;
26 struct clk *ret = NULL;
27
28 mutex_lock(&clocks_mutex);
29 list_for_each_entry(c, &clocks, node) {
30 if (!strcmp(c->name, name)) {
31 ret = c;
32 break;
33 }
34 }
35 mutex_unlock(&clocks_mutex);
36
37 return ret;
38}
39EXPORT_SYMBOL(clk_get);
40
41unsigned long clk_get_rate(struct clk *clk)
42{
43 return clk->rate;
44}
45EXPORT_SYMBOL(clk_get_rate);
46
47static void pll_clk_init(struct clk *clk)
48{
49 u32 pll;
50
51 pll = __raw_readl(LS1X_CLK_PLL_FREQ);
52 clk->rate = (12 + (pll & 0x3f)) * 33 / 2
53 + ((pll >> 8) & 0x3ff) * 33 / 1024 / 2;
54 clk->rate *= 1000000;
55}
56
57static void cpu_clk_init(struct clk *clk)
58{
59 u32 pll, ctrl;
60
61 pll = clk_get_rate(clk->parent);
62 ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU;
63 clk->rate = pll / (ctrl >> DIV_CPU_SHIFT);
64}
65
66static void ddr_clk_init(struct clk *clk)
67{
68 u32 pll, ctrl;
69
70 pll = clk_get_rate(clk->parent);
71 ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR;
72 clk->rate = pll / (ctrl >> DIV_DDR_SHIFT);
73}
74
75static void dc_clk_init(struct clk *clk)
76{
77 u32 pll, ctrl;
78
79 pll = clk_get_rate(clk->parent);
80 ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC;
81 clk->rate = pll / (ctrl >> DIV_DC_SHIFT);
82}
83
84static struct clk_ops pll_clk_ops = {
85 .init = pll_clk_init,
86};
87
88static struct clk_ops cpu_clk_ops = {
89 .init = cpu_clk_init,
90};
91
92static struct clk_ops ddr_clk_ops = {
93 .init = ddr_clk_init,
94};
95
96static struct clk_ops dc_clk_ops = {
97 .init = dc_clk_init,
98};
99
100static struct clk pll_clk = {
101 .name = "pll",
102 .ops = &pll_clk_ops,
103};
104
105static struct clk cpu_clk = {
106 .name = "cpu",
107 .parent = &pll_clk,
108 .ops = &cpu_clk_ops,
109};
110
111static struct clk ddr_clk = {
112 .name = "ddr",
113 .parent = &pll_clk,
114 .ops = &ddr_clk_ops,
115};
116
117static struct clk dc_clk = {
118 .name = "dc",
119 .parent = &pll_clk,
120 .ops = &dc_clk_ops,
121};
122
123int clk_register(struct clk *clk)
124{
125 mutex_lock(&clocks_mutex);
126 list_add(&clk->node, &clocks);
127 if (clk->ops->init)
128 clk->ops->init(clk);
129 mutex_unlock(&clocks_mutex);
130
131 return 0;
132}
133EXPORT_SYMBOL(clk_register);
134
135static struct clk *ls1x_clks[] = {
136 &pll_clk,
137 &cpu_clk,
138 &ddr_clk,
139 &dc_clk,
140};
141
142int __init ls1x_clock_init(void)
143{
144 int i;
145
146 for (i = 0; i < ARRAY_SIZE(ls1x_clks); i++)
147 clk_register(ls1x_clks[i]);
148
149 return 0;
150}
151
152void __init plat_time_init(void)
153{
154 struct clk *clk;
155
156 /* Initialize LS1X clocks */
157 ls1x_clock_init();
158
159 /* setup mips r4k timer */
160 clk = clk_get(NULL, "cpu");
161 if (IS_ERR(clk))
162 panic("unable to get dc clock, err=%ld", PTR_ERR(clk));
163
164 mips_hpt_frequency = clk_get_rate(clk) / 2;
165}
diff --git a/arch/mips/loongson1/common/irq.c b/arch/mips/loongson1/common/irq.c
new file mode 100644
index 000000000000..41bc8ffe7bba
--- /dev/null
+++ b/arch/mips/loongson1/common/irq.c
@@ -0,0 +1,147 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <linux/interrupt.h>
11#include <linux/irq.h>
12#include <asm/irq_cpu.h>
13
14#include <loongson1.h>
15#include <irq.h>
16
17#define LS1X_INTC_REG(n, x) \
18 ((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x)))
19
20#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0)
21#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4)
22#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8)
23#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc)
24#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10)
25#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14)
26
27static void ls1x_irq_ack(struct irq_data *d)
28{
29 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
30 unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
31
32 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
33 | (1 << bit), LS1X_INTC_INTCLR(n));
34}
35
36static void ls1x_irq_mask(struct irq_data *d)
37{
38 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
39 unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
40
41 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
42 & ~(1 << bit), LS1X_INTC_INTIEN(n));
43}
44
45static void ls1x_irq_mask_ack(struct irq_data *d)
46{
47 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
48 unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
49
50 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
51 & ~(1 << bit), LS1X_INTC_INTIEN(n));
52 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
53 | (1 << bit), LS1X_INTC_INTCLR(n));
54}
55
56static void ls1x_irq_unmask(struct irq_data *d)
57{
58 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
59 unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
60
61 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
62 | (1 << bit), LS1X_INTC_INTIEN(n));
63}
64
65static struct irq_chip ls1x_irq_chip = {
66 .name = "LS1X-INTC",
67 .irq_ack = ls1x_irq_ack,
68 .irq_mask = ls1x_irq_mask,
69 .irq_mask_ack = ls1x_irq_mask_ack,
70 .irq_unmask = ls1x_irq_unmask,
71};
72
73static void ls1x_irq_dispatch(int n)
74{
75 u32 int_status, irq;
76
77 /* Get pending sources, masked by current enables */
78 int_status = __raw_readl(LS1X_INTC_INTISR(n)) &
79 __raw_readl(LS1X_INTC_INTIEN(n));
80
81 if (int_status) {
82 irq = LS1X_IRQ(n, __ffs(int_status));
83 do_IRQ(irq);
84 }
85}
86
87asmlinkage void plat_irq_dispatch(void)
88{
89 unsigned int pending;
90
91 pending = read_c0_cause() & read_c0_status() & ST0_IM;
92
93 if (pending & CAUSEF_IP7)
94 do_IRQ(TIMER_IRQ);
95 else if (pending & CAUSEF_IP2)
96 ls1x_irq_dispatch(0); /* INT0 */
97 else if (pending & CAUSEF_IP3)
98 ls1x_irq_dispatch(1); /* INT1 */
99 else if (pending & CAUSEF_IP4)
100 ls1x_irq_dispatch(2); /* INT2 */
101 else if (pending & CAUSEF_IP5)
102 ls1x_irq_dispatch(3); /* INT3 */
103 else if (pending & CAUSEF_IP6)
104 ls1x_irq_dispatch(4); /* INT4 */
105 else
106 spurious_interrupt();
107
108}
109
110struct irqaction cascade_irqaction = {
111 .handler = no_action,
112 .name = "cascade",
113 .flags = IRQF_NO_THREAD,
114};
115
116static void __init ls1x_irq_init(int base)
117{
118 int n;
119
120 /* Disable interrupts and clear pending,
121 * setup all IRQs as high level triggered
122 */
123 for (n = 0; n < 4; n++) {
124 __raw_writel(0x0, LS1X_INTC_INTIEN(n));
125 __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n));
126 __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n));
127 /* set DMA0, DMA1 and DMA2 to edge trigger */
128 __raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n));
129 }
130
131
132 for (n = base; n < LS1X_IRQS; n++) {
133 irq_set_chip_and_handler(n, &ls1x_irq_chip,
134 handle_level_irq);
135 }
136
137 setup_irq(INT0_IRQ, &cascade_irqaction);
138 setup_irq(INT1_IRQ, &cascade_irqaction);
139 setup_irq(INT2_IRQ, &cascade_irqaction);
140 setup_irq(INT3_IRQ, &cascade_irqaction);
141}
142
143void __init arch_init_irq(void)
144{
145 mips_cpu_irq_init();
146 ls1x_irq_init(LS1X_IRQ_BASE);
147}
diff --git a/arch/mips/loongson1/common/platform.c b/arch/mips/loongson1/common/platform.c
new file mode 100644
index 000000000000..e92d59c4bd78
--- /dev/null
+++ b/arch/mips/loongson1/common/platform.c
@@ -0,0 +1,124 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <linux/clk.h>
11#include <linux/dma-mapping.h>
12#include <linux/err.h>
13#include <linux/phy.h>
14#include <linux/serial_8250.h>
15#include <linux/stmmac.h>
16#include <asm-generic/sizes.h>
17
18#include <loongson1.h>
19
20#define LS1X_UART(_id) \
21 { \
22 .mapbase = LS1X_UART ## _id ## _BASE, \
23 .irq = LS1X_UART ## _id ## _IRQ, \
24 .iotype = UPIO_MEM, \
25 .flags = UPF_IOREMAP | UPF_FIXED_TYPE, \
26 .type = PORT_16550A, \
27 }
28
29static struct plat_serial8250_port ls1x_serial8250_port[] = {
30 LS1X_UART(0),
31 LS1X_UART(1),
32 LS1X_UART(2),
33 LS1X_UART(3),
34 {},
35};
36
37struct platform_device ls1x_uart_device = {
38 .name = "serial8250",
39 .id = PLAT8250_DEV_PLATFORM,
40 .dev = {
41 .platform_data = ls1x_serial8250_port,
42 },
43};
44
45void __init ls1x_serial_setup(void)
46{
47 struct clk *clk;
48 struct plat_serial8250_port *p;
49
50 clk = clk_get(NULL, "dc");
51 if (IS_ERR(clk))
52 panic("unable to get dc clock, err=%ld", PTR_ERR(clk));
53
54 for (p = ls1x_serial8250_port; p->flags != 0; ++p)
55 p->uartclk = clk_get_rate(clk);
56}
57
58/* Synopsys Ethernet GMAC */
59static struct resource ls1x_eth0_resources[] = {
60 [0] = {
61 .start = LS1X_GMAC0_BASE,
62 .end = LS1X_GMAC0_BASE + SZ_64K - 1,
63 .flags = IORESOURCE_MEM,
64 },
65 [1] = {
66 .name = "macirq",
67 .start = LS1X_GMAC0_IRQ,
68 .flags = IORESOURCE_IRQ,
69 },
70};
71
72static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = {
73 .bus_id = 0,
74 .phy_mask = 0,
75};
76
77static struct plat_stmmacenet_data ls1x_eth_data = {
78 .bus_id = 0,
79 .phy_addr = -1,
80 .mdio_bus_data = &ls1x_mdio_bus_data,
81 .has_gmac = 1,
82 .tx_coe = 1,
83};
84
85struct platform_device ls1x_eth0_device = {
86 .name = "stmmaceth",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(ls1x_eth0_resources),
89 .resource = ls1x_eth0_resources,
90 .dev = {
91 .platform_data = &ls1x_eth_data,
92 },
93};
94
95/* USB EHCI */
96static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);
97
98static struct resource ls1x_ehci_resources[] = {
99 [0] = {
100 .start = LS1X_EHCI_BASE,
101 .end = LS1X_EHCI_BASE + SZ_32K - 1,
102 .flags = IORESOURCE_MEM,
103 },
104 [1] = {
105 .start = LS1X_EHCI_IRQ,
106 .flags = IORESOURCE_IRQ,
107 },
108};
109
110struct platform_device ls1x_ehci_device = {
111 .name = "ls1x-ehci",
112 .id = -1,
113 .num_resources = ARRAY_SIZE(ls1x_ehci_resources),
114 .resource = ls1x_ehci_resources,
115 .dev = {
116 .dma_mask = &ls1x_ehci_dmamask,
117 },
118};
119
120/* Real Time Clock */
121struct platform_device ls1x_rtc_device = {
122 .name = "ls1x-rtc",
123 .id = -1,
124};
diff --git a/arch/mips/loongson1/common/prom.c b/arch/mips/loongson1/common/prom.c
new file mode 100644
index 000000000000..1f8e49f9886d
--- /dev/null
+++ b/arch/mips/loongson1/common/prom.c
@@ -0,0 +1,87 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * Modified from arch/mips/pnx833x/common/prom.c.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/serial_reg.h>
13#include <asm/bootinfo.h>
14
15#include <loongson1.h>
16#include <prom.h>
17
18int prom_argc;
19char **prom_argv, **prom_envp;
20unsigned long memsize, highmemsize;
21
22char *prom_getenv(char *envname)
23{
24 char **env = prom_envp;
25 int i;
26
27 i = strlen(envname);
28
29 while (*env) {
30 if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=')
31 return *env + i + 1;
32 env++;
33 }
34
35 return 0;
36}
37
38static inline unsigned long env_or_default(char *env, unsigned long dfl)
39{
40 char *str = prom_getenv(env);
41 return str ? simple_strtol(str, 0, 0) : dfl;
42}
43
44void __init prom_init_cmdline(void)
45{
46 char *c = &(arcs_cmdline[0]);
47 int i;
48
49 for (i = 1; i < prom_argc; i++) {
50 strcpy(c, prom_argv[i]);
51 c += strlen(prom_argv[i]);
52 if (i < prom_argc-1)
53 *c++ = ' ';
54 }
55 *c = 0;
56}
57
58void __init prom_init(void)
59{
60 prom_argc = fw_arg0;
61 prom_argv = (char **)fw_arg1;
62 prom_envp = (char **)fw_arg2;
63
64 prom_init_cmdline();
65
66 memsize = env_or_default("memsize", DEFAULT_MEMSIZE);
67 highmemsize = env_or_default("highmemsize", 0x0);
68}
69
70void __init prom_free_prom_memory(void)
71{
72}
73
74#define PORT(offset) (u8 *)(KSEG1ADDR(LS1X_UART0_BASE + offset))
75
76void __init prom_putchar(char c)
77{
78 int timeout;
79
80 timeout = 1024;
81
82 while (((readb(PORT(UART_LSR)) & UART_LSR_THRE) == 0)
83 && (timeout-- > 0))
84 ;
85
86 writeb(c, PORT(UART_TX));
87}
diff --git a/arch/mips/loongson1/common/reset.c b/arch/mips/loongson1/common/reset.c
new file mode 100644
index 000000000000..fb979a784eca
--- /dev/null
+++ b/arch/mips/loongson1/common/reset.c
@@ -0,0 +1,45 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <linux/io.h>
11#include <linux/pm.h>
12#include <asm/reboot.h>
13
14#include <loongson1.h>
15
16static void ls1x_restart(char *command)
17{
18 __raw_writel(0x1, LS1X_WDT_EN);
19 __raw_writel(0x5000000, LS1X_WDT_TIMER);
20 __raw_writel(0x1, LS1X_WDT_SET);
21}
22
23static void ls1x_halt(void)
24{
25 while (1) {
26 if (cpu_wait)
27 cpu_wait();
28 }
29}
30
31static void ls1x_power_off(void)
32{
33 ls1x_halt();
34}
35
36static int __init ls1x_reboot_setup(void)
37{
38 _machine_restart = ls1x_restart;
39 _machine_halt = ls1x_halt;
40 pm_power_off = ls1x_power_off;
41
42 return 0;
43}
44
45arch_initcall(ls1x_reboot_setup);
diff --git a/arch/mips/loongson1/common/setup.c b/arch/mips/loongson1/common/setup.c
new file mode 100644
index 000000000000..62128cc27e68
--- /dev/null
+++ b/arch/mips/loongson1/common/setup.c
@@ -0,0 +1,29 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <asm/bootinfo.h>
11
12#include <prom.h>
13
14void __init plat_mem_setup(void)
15{
16 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
17}
18
19const char *get_system_type(void)
20{
21 unsigned int processor_id = (&current_cpu_data)->processor_id;
22
23 switch (processor_id & PRID_REV_MASK) {
24 case PRID_REV_LOONGSON1B:
25 return "LOONGSON LS1B";
26 default:
27 return "LOONGSON (unknown)";
28 }
29}
diff --git a/arch/mips/loongson1/ls1b/Makefile b/arch/mips/loongson1/ls1b/Makefile
new file mode 100644
index 000000000000..891eac482b82
--- /dev/null
+++ b/arch/mips/loongson1/ls1b/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for loongson1B based machines.
3#
4
5obj-y += board.o
diff --git a/arch/mips/loongson1/ls1b/board.c b/arch/mips/loongson1/ls1b/board.c
new file mode 100644
index 000000000000..295b1be893e3
--- /dev/null
+++ b/arch/mips/loongson1/ls1b/board.c
@@ -0,0 +1,33 @@
1/*
2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <platform.h>
11
12#include <linux/serial_8250.h>
13#include <loongson1.h>
14
15static struct platform_device *ls1b_platform_devices[] __initdata = {
16 &ls1x_uart_device,
17 &ls1x_eth0_device,
18 &ls1x_ehci_device,
19 &ls1x_rtc_device,
20};
21
22static int __init ls1b_platform_init(void)
23{
24 int err;
25
26 ls1x_serial_setup();
27
28 err = platform_add_devices(ls1b_platform_devices,
29 ARRAY_SIZE(ls1b_platform_devices));
30 return err;
31}
32
33arch_initcall(ls1b_platform_init);
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 5fa185151fc8..64a28e819064 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -58,18 +58,16 @@ enum fields {
58 58
59enum opcode { 59enum opcode {
60 insn_invalid, 60 insn_invalid,
61 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq, 61 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
62 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, 62 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
63 insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, 63 insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
64 insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, 64 insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
65 insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret, 65 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
66 insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, 66 insn_j, insn_jal, insn_jr, insn_ld, insn_ldx, insn_ll, insn_lld,
67 insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori, 67 insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, insn_or, insn_ori,
68 insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, 68 insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll,
69 insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, 69 insn_sra, insn_srl, insn_subu, insn_sw, insn_syscall, insn_tlbp,
70 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, 70 insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
71 insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1,
72 insn_lwx, insn_ldx
73}; 71};
74 72
75struct insn { 73struct insn {
@@ -90,65 +88,65 @@ struct insn {
90static struct insn insn_table[] __uasminitdata = { 88static struct insn insn_table[] __uasminitdata = {
91 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 89 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
92 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, 90 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
93 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
94 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 91 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
95 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 92 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
93 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
94 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
96 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 95 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
97 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM }, 96 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
98 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM }, 97 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
99 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM }, 98 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
100 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM }, 99 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
100 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
101 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, 101 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
102 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 102 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
103 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 103 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
104 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, 104 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
105 { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
106 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
105 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, 107 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
106 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, 108 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
107 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE }, 109 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
110 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
108 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE }, 111 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
112 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
109 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, 113 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
110 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
111 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, 114 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
112 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, 115 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
113 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
114 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, 116 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
115 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, 117 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
116 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
117 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, 118 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
119 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
118 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, 120 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
119 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 121 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
120 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 122 { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
121 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 123 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
124 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
122 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM }, 125 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
123 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 126 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
127 { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
124 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, 128 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
125 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, 129 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
126 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
127 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 130 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
131 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
128 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 132 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
129 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 }, 133 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
130 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 134 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
131 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 135 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
136 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
132 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 137 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
133 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, 138 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
134 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, 139 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
135 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, 140 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
136 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
137 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, 141 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
138 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, 142 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
143 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
139 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, 144 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
140 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, 145 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
141 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, 146 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
142 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, 147 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
143 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
144 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, 148 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
145 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, 149 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
146 { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
147 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
148 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
149 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
150 { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
151 { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
152 { insn_invalid, 0, 0 } 150 { insn_invalid, 0, 0 }
153}; 151};
154 152
diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c
index f193f7b3bd81..1902fa22d277 100644
--- a/arch/mips/netlogic/common/earlycons.c
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -54,7 +54,7 @@ void prom_putchar(char c)
54#elif defined(CONFIG_CPU_XLR) 54#elif defined(CONFIG_CPU_XLR)
55 uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET); 55 uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
56#endif 56#endif
57 while (nlm_read_reg(uartbase, UART_LSR) == 0) 57 while ((nlm_read_reg(uartbase, UART_LSR) & UART_LSR_THRE) == 0)
58 ; 58 ;
59 nlm_write_reg(uartbase, UART_TX, c); 59 nlm_write_reg(uartbase, UART_TX, c);
60} 60}
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index c138b1a6dec3..a13355cc97eb 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -54,28 +54,68 @@
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ 54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4 55 SYS_CPU_NONCOHERENT_MODE * 4
56 56
57.macro __config_lsu 57#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */
58 li t0, LSU_DEFEATURE
59 mfcr t1, t0
60 58
61 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */ 59/* Enable XLP features and workarounds in the LSU */
62 or t1, t1, t2 60.macro xlp_config_lsu
63 li t2, ~0xe /* S1RCM */ 61 li t0, LSU_DEFEATURE
62 mfcr t1, t0
63
64 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
65 or t1, t1, t2
66#ifdef XLP_AX_WORKAROUND
67 li t2, ~0xe /* S1RCM */
64 and t1, t1, t2 68 and t1, t1, t2
65 mtcr t1, t0 69#endif
70 mtcr t1, t0
66 71
67 li t0, SCHED_DEFEATURE 72#ifdef XLP_AX_WORKAROUND
68 lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */ 73 li t0, SCHED_DEFEATURE
69 mtcr t1, t0 74 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
75 mtcr t1, t0
76#endif
77.endm
78
79/*
80 * This is the code that will be copied to the reset entry point for
81 * XLR and XLP. The XLP cores start here when they are woken up. This
82 * is also the NMI entry point.
83 */
84.macro xlp_flush_l1_dcache
85 li t0, LSU_DEBUG_DATA0
86 li t1, LSU_DEBUG_ADDR
87 li t2, 0 /* index */
88 li t3, 0x1000 /* loop count */
891:
90 sll v0, t2, 5
91 mtcr zero, t0
92 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
93 mtcr v1, t1
942:
95 mfcr v1, t1
96 andi v1, 0x1 /* wait for write_active == 0 */
97 bnez v1, 2b
98 nop
99 mtcr zero, t0
100 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
101 mtcr v1, t1
1023:
103 mfcr v1, t1
104 andi v1, 0x1 /* wait for write_active == 0 */
105 bnez v1, 3b
106 nop
107 addi t2, 1
108 bne t3, t2, 1b
109 nop
70.endm 110.endm
71 111
72/* 112/*
73 * The cores can come start when they are woken up. This is also the NMI 113 * The cores can come start when they are woken up. This is also the NMI
74 * entry, so check that first. 114 * entry, so check that first.
75 * 115 *
76 * The data corresponding to reset is stored at RESET_DATA_PHYS location, 116 * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
77 * this will have the thread mask (used when core is woken up) and the 117 * location, this will have the thread mask (used when core is woken up)
78 * current NMI handler in case we reached here for an NMI. 118 * and the current NMI handler in case we reached here for an NMI.
79 * 119 *
80 * When a core or thread is newly woken up, it loops in a 'wait'. When 120 * When a core or thread is newly woken up, it loops in a 'wait'. When
81 * the CPU really needs waking up, we send an NMI to it, with the NMI 121 * the CPU really needs waking up, we send an NMI to it, with the NMI
@@ -89,12 +129,12 @@
89FEXPORT(nlm_reset_entry) 129FEXPORT(nlm_reset_entry)
90 dmtc0 k0, $22, 6 130 dmtc0 k0, $22, 6
91 dmtc0 k1, $22, 7 131 dmtc0 k1, $22, 7
92 mfc0 k0, CP0_STATUS 132 mfc0 k0, CP0_STATUS
93 li k1, 0x80000 133 li k1, 0x80000
94 and k1, k0, k1 134 and k1, k0, k1
95 beqz k1, 1f /* go to real reset entry */ 135 beqz k1, 1f /* go to real reset entry */
96 nop 136 nop
97 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ 137 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
98 ld k0, BOOT_NMI_HANDLER(k1) 138 ld k0, BOOT_NMI_HANDLER(k1)
99 jr k0 139 jr k0
100 nop 140 nop
@@ -114,21 +154,25 @@ FEXPORT(nlm_reset_entry)
114 li t2, SYS_CPU_COHERENT_BASE(0) 154 li t2, SYS_CPU_COHERENT_BASE(0)
115 add t2, t2, t3 /* t2 <- SYS offset for node */ 155 add t2, t2, t3 /* t2 <- SYS offset for node */
116 lw t1, 0(t2) 156 lw t1, 0(t2)
117 and t1, t1, t0 157 and t1, t1, t0
118 sw t1, 0(t2) 158 sw t1, 0(t2)
119 159
120 /* read back to ensure complete */ 160 /* read back to ensure complete */
121 lw t1, 0(t2) 161 lw t1, 0(t2)
122 sync 162 sync
123 163
124 /* Configure LSU on Non-0 Cores. */ 164 /* Configure LSU on Non-0 Cores. */
125 __config_lsu 165 xlp_config_lsu
166 /* FALL THROUGH */
126 167
127/* 168/*
128 * Wake up sibling threads from the initial thread in 169 * Wake up sibling threads from the initial thread in
129 * a core. 170 * a core.
130 */ 171 */
131EXPORT(nlm_boot_siblings) 172EXPORT(nlm_boot_siblings)
173 /* core L1D flush before enable threads */
174 xlp_flush_l1_dcache
175 /* Enable hw threads by writing to MAP_THREADMODE of the core */
132 li t0, CKSEG1ADDR(RESET_DATA_PHYS) 176 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
133 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ 177 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
134 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) 178 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
@@ -139,31 +183,28 @@ EXPORT(nlm_boot_siblings)
139 /* 183 /*
140 * The new hardware thread starts at the next instruction 184 * The new hardware thread starts at the next instruction
141 * For all the cases other than core 0 thread 0, we will 185 * For all the cases other than core 0 thread 0, we will
142 * jump to the secondary wait function. 186 * jump to the secondary wait function.
143 */ 187 */
144 mfc0 v0, CP0_EBASE, 1 188 mfc0 v0, CP0_EBASE, 1
145 andi v0, 0x7f /* v0 <- node/core */ 189 andi v0, 0x7f /* v0 <- node/core */
146 190
147#if 1 191 /* Init MMU in the first thread after changing THREAD_MODE
148 /* A0 errata - Write MMU_SETUP after changing thread mode register. */ 192 * register (Ax Errata?)
193 */
149 andi v1, v0, 0x3 /* v1 <- thread id */ 194 andi v1, v0, 0x3 /* v1 <- thread id */
150 bnez v1, 2f 195 bnez v1, 2f
151 nop 196 nop
152 197
153 li t0, MMU_SETUP 198 li t0, MMU_SETUP
154 li t1, 0 199 li t1, 0
155 mtcr t1, t0 200 mtcr t1, t0
156 ehb 201 _ehb
157#endif
158 202
1592: beqz v0, 4f 2032: beqz v0, 4f /* boot cpu (cpuid == 0)? */
160 nop 204 nop
161 205
162 /* setup status reg */ 206 /* setup status reg */
163 mfc0 t1, CP0_STATUS 207 move t1, zero
164 li t0, ST0_BEV
165 or t1, t0
166 xor t1, t0
167#ifdef CONFIG_64BIT 208#ifdef CONFIG_64BIT
168 ori t1, ST0_KX 209 ori t1, ST0_KX
169#endif 210#endif
@@ -183,9 +224,9 @@ EXPORT(nlm_boot_siblings)
183 * For the boot CPU, we have to restore registers and 224 * For the boot CPU, we have to restore registers and
184 * return 225 * return
185 */ 226 */
1864: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ 2274: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
187 li t1, 0xfadebeef 228 li t1, 0xfadebeef
188 dmtc0 t1, $4, 2 /* restore SP from UserLocal */ 229 dmtc0 t1, $4, 2 /* restore SP from UserLocal */
189 PTR_SUBU sp, t0, PT_SIZE 230 PTR_SUBU sp, t0, PT_SIZE
190 RESTORE_ALL 231 RESTORE_ALL
191 jr ra 232 jr ra
@@ -193,7 +234,7 @@ EXPORT(nlm_boot_siblings)
193EXPORT(nlm_reset_entry_end) 234EXPORT(nlm_reset_entry_end)
194 235
195FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ 236FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
196 __config_lsu 237 xlp_config_lsu
197 dmtc0 sp, $4, 2 /* SP saved in UserLocal */ 238 dmtc0 sp, $4, 2 /* SP saved in UserLocal */
198 SAVE_ALL 239 SAVE_ALL
199 sync 240 sync
@@ -210,6 +251,12 @@ FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
210 251
211 __CPUINIT 252 __CPUINIT
212NESTED(nlm_boot_secondary_cpus, 16, sp) 253NESTED(nlm_boot_secondary_cpus, 16, sp)
254 /* Initialize CP0 Status */
255 move t1, zero
256#ifdef CONFIG_64BIT
257 ori t1, ST0_KX
258#endif
259 mtc0 t1, CP0_STATUS
213 PTR_LA t1, nlm_next_sp 260 PTR_LA t1, nlm_next_sp
214 PTR_L sp, 0(t1) 261 PTR_L sp, 0(t1)
215 PTR_LA t1, nlm_next_gp 262 PTR_LA t1, nlm_next_gp
@@ -234,36 +281,36 @@ END(nlm_boot_secondary_cpus)
234 */ 281 */
235 __CPUINIT 282 __CPUINIT
236NESTED(nlm_rmiboot_preboot, 16, sp) 283NESTED(nlm_rmiboot_preboot, 16, sp)
237 mfc0 t0, $15, 1 # read ebase 284 mfc0 t0, $15, 1 /* read ebase */
238 andi t0, 0x1f # t0 has the processor_id() 285 andi t0, 0x1f /* t0 has the processor_id() */
239 andi t2, t0, 0x3 # thread no 286 andi t2, t0, 0x3 /* thread num */
240 sll t0, 2 # offset in cpu array 287 sll t0, 2 /* offset in cpu array */
241 288
242 PTR_LA t1, nlm_cpu_ready # mark CPU ready 289 PTR_LA t1, nlm_cpu_ready /* mark CPU ready */
243 PTR_ADDU t1, t0 290 PTR_ADDU t1, t0
244 li t3, 1 291 li t3, 1
245 sw t3, 0(t1) 292 sw t3, 0(t1)
246 293
247 bnez t2, 1f # skip thread programming 294 bnez t2, 1f /* skip thread programming */
248 nop # for non zero hw threads 295 nop /* for thread id != 0 */
249 296
250 /* 297 /*
251 * MMU setup only for first thread in core 298 * XLR MMU setup only for first thread in core
252 */ 299 */
253 li t0, 0x400 300 li t0, 0x400
254 mfcr t1, t0 301 mfcr t1, t0
255 li t2, 6 # XLR thread mode mask 302 li t2, 6 /* XLR thread mode mask */
256 nor t3, t2, zero 303 nor t3, t2, zero
257 and t2, t1, t2 # t2 - current thread mode 304 and t2, t1, t2 /* t2 - current thread mode */
258 li v0, CKSEG1ADDR(RESET_DATA_PHYS) 305 li v0, CKSEG1ADDR(RESET_DATA_PHYS)
259 lw v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode 306 lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
260 sll v1, 1 307 sll v1, 1
261 beq v1, t2, 1f # same as request value 308 beq v1, t2, 1f /* same as request value */
262 nop # nothing to do */ 309 nop /* nothing to do */
263 310
264 and t2, t1, t3 # mask out old thread mode 311 and t2, t1, t3 /* mask out old thread mode */
265 or t1, t2, v1 # put in new value 312 or t1, t2, v1 /* put in new value */
266 mtcr t1, t0 # update core control 313 mtcr t1, t0 /* update core control */
267 314
2681: wait 3151: wait
269 j 1b 316 j 1b
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
index b93ed83474ec..6b4b972218f0 100644
--- a/arch/mips/netlogic/xlp/Makefile
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -1,2 +1,4 @@
1obj-y += setup.o platform.o nlm_hal.o 1obj-y += setup.o platform.o nlm_hal.o
2obj-$(CONFIG_OF) += of.o
2obj-$(CONFIG_SMP) += wakeup.o 3obj-$(CONFIG_SMP) += wakeup.o
4obj-$(CONFIG_USB) += usb-init.o
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 9428e7125fed..6c65ac701912 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -69,6 +69,32 @@ int nlm_irq_to_irt(int irq)
69 return PIC_IRT_UART_0_INDEX; 69 return PIC_IRT_UART_0_INDEX;
70 case PIC_UART_1_IRQ: 70 case PIC_UART_1_IRQ:
71 return PIC_IRT_UART_1_INDEX; 71 return PIC_IRT_UART_1_INDEX;
72 case PIC_PCIE_LINK_0_IRQ:
73 return PIC_IRT_PCIE_LINK_0_INDEX;
74 case PIC_PCIE_LINK_1_IRQ:
75 return PIC_IRT_PCIE_LINK_1_INDEX;
76 case PIC_PCIE_LINK_2_IRQ:
77 return PIC_IRT_PCIE_LINK_2_INDEX;
78 case PIC_PCIE_LINK_3_IRQ:
79 return PIC_IRT_PCIE_LINK_3_INDEX;
80 case PIC_EHCI_0_IRQ:
81 return PIC_IRT_EHCI_0_INDEX;
82 case PIC_EHCI_1_IRQ:
83 return PIC_IRT_EHCI_1_INDEX;
84 case PIC_OHCI_0_IRQ:
85 return PIC_IRT_OHCI_0_INDEX;
86 case PIC_OHCI_1_IRQ:
87 return PIC_IRT_OHCI_1_INDEX;
88 case PIC_OHCI_2_IRQ:
89 return PIC_IRT_OHCI_2_INDEX;
90 case PIC_OHCI_3_IRQ:
91 return PIC_IRT_OHCI_3_INDEX;
92 case PIC_MMC_IRQ:
93 return PIC_IRT_MMC_INDEX;
94 case PIC_I2C_0_IRQ:
95 return PIC_IRT_I2C_0_INDEX;
96 case PIC_I2C_1_IRQ:
97 return PIC_IRT_I2C_1_INDEX;
72 default: 98 default:
73 return -1; 99 return -1;
74 } 100 }
@@ -81,6 +107,32 @@ int nlm_irt_to_irq(int irt)
81 return PIC_UART_0_IRQ; 107 return PIC_UART_0_IRQ;
82 case PIC_IRT_UART_1_INDEX: 108 case PIC_IRT_UART_1_INDEX:
83 return PIC_UART_1_IRQ; 109 return PIC_UART_1_IRQ;
110 case PIC_IRT_PCIE_LINK_0_INDEX:
111 return PIC_PCIE_LINK_0_IRQ;
112 case PIC_IRT_PCIE_LINK_1_INDEX:
113 return PIC_PCIE_LINK_1_IRQ;
114 case PIC_IRT_PCIE_LINK_2_INDEX:
115 return PIC_PCIE_LINK_2_IRQ;
116 case PIC_IRT_PCIE_LINK_3_INDEX:
117 return PIC_PCIE_LINK_3_IRQ;
118 case PIC_IRT_EHCI_0_INDEX:
119 return PIC_EHCI_0_IRQ;
120 case PIC_IRT_EHCI_1_INDEX:
121 return PIC_EHCI_1_IRQ;
122 case PIC_IRT_OHCI_0_INDEX:
123 return PIC_OHCI_0_IRQ;
124 case PIC_IRT_OHCI_1_INDEX:
125 return PIC_OHCI_1_IRQ;
126 case PIC_IRT_OHCI_2_INDEX:
127 return PIC_OHCI_2_IRQ;
128 case PIC_IRT_OHCI_3_INDEX:
129 return PIC_OHCI_3_IRQ;
130 case PIC_IRT_MMC_INDEX:
131 return PIC_MMC_IRQ;
132 case PIC_IRT_I2C_0_INDEX:
133 return PIC_I2C_0_IRQ;
134 case PIC_IRT_I2C_1_INDEX:
135 return PIC_I2C_1_IRQ;
84 default: 136 default:
85 return -1; 137 return -1;
86 } 138 }
diff --git a/arch/mips/netlogic/xlp/of.c b/arch/mips/netlogic/xlp/of.c
new file mode 100644
index 000000000000..8e3921c0c201
--- /dev/null
+++ b/arch/mips/netlogic/xlp/of.c
@@ -0,0 +1,34 @@
1#include <linux/bootmem.h>
2#include <linux/init.h>
3#include <linux/io.h>
4#include <linux/of_fdt.h>
5#include <asm/byteorder.h>
6
7static int __init reserve_mem_mach(unsigned long addr, unsigned long size)
8{
9 return reserve_bootmem(addr, size, BOOTMEM_DEFAULT);
10}
11
12void __init free_mem_mach(unsigned long addr, unsigned long size)
13{
14 return free_bootmem(addr, size);
15}
16
17void __init device_tree_init(void)
18{
19 unsigned long base, size;
20
21 if (!initial_boot_params)
22 return;
23
24 base = virt_to_phys((void *)initial_boot_params);
25 size = be32_to_cpu(initial_boot_params->totalsize);
26
27 /* Before we do anything, lets reserve the dt blob */
28 reserve_mem_mach(base, size);
29
30 unflatten_device_tree();
31
32 /* free the space reserved for the dt blob */
33 free_mem_mach(base, size);
34}
diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c
index 1f5e4cba891d..2c510d585447 100644
--- a/arch/mips/netlogic/xlp/platform.c
+++ b/arch/mips/netlogic/xlp/platform.c
@@ -53,7 +53,7 @@
53 53
54static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset) 54static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset)
55{ 55{
56 return nlm_read_reg(p->iobase, offset); 56 return nlm_read_reg(p->iobase, offset);
57} 57}
58 58
59static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value) 59static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value)
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index b3df7c2aad1e..3dec9f28b65b 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -41,6 +41,8 @@
41#include <asm/bootinfo.h> 41#include <asm/bootinfo.h>
42 42
43#include <linux/of_fdt.h> 43#include <linux/of_fdt.h>
44#include <linux/of_platform.h>
45#include <linux/of_device.h>
44 46
45#include <asm/netlogic/haldefs.h> 47#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h> 48#include <asm/netlogic/common.h>
@@ -109,3 +111,17 @@ void __init prom_init(void)
109 register_smp_ops(&nlm_smp_ops); 111 register_smp_ops(&nlm_smp_ops);
110#endif 112#endif
111} 113}
114
115static struct of_device_id __initdata xlp_ids[] = {
116 { .compatible = "simple-bus", },
117 {},
118};
119
120int __init xlp8xx_ds_publish_devices(void)
121{
122 if (!of_have_populated_dt())
123 return 0;
124 return of_platform_bus_probe(NULL, xlp_ids, NULL);
125}
126
127device_initcall(xlp8xx_ds_publish_devices);
diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c
new file mode 100644
index 000000000000..dbe083a93538
--- /dev/null
+++ b/arch/mips/netlogic/xlp/usb-init.c
@@ -0,0 +1,124 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/dma-mapping.h>
36#include <linux/kernel.h>
37#include <linux/delay.h>
38#include <linux/init.h>
39#include <linux/pci.h>
40#include <linux/platform_device.h>
41
42#include <asm/netlogic/haldefs.h>
43#include <asm/netlogic/xlp-hal/iomap.h>
44#include <asm/netlogic/xlp-hal/xlp.h>
45#include <asm/netlogic/xlp-hal/usb.h>
46
47static void nlm_usb_intr_en(int node, int port)
48{
49 uint32_t val;
50 uint64_t port_addr;
51
52 port_addr = nlm_get_usb_regbase(node, port);
53 val = nlm_read_usb_reg(port_addr, USB_INT_EN);
54 val = USB_CTRL_INTERRUPT_EN | USB_OHCI_INTERRUPT_EN |
55 USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN |
56 USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
57 nlm_write_usb_reg(port_addr, USB_INT_EN, val);
58}
59
60static void nlm_usb_hw_reset(int node, int port)
61{
62 uint64_t port_addr;
63 uint32_t val;
64
65 /* reset USB phy */
66 port_addr = nlm_get_usb_regbase(node, port);
67 val = nlm_read_usb_reg(port_addr, USB_PHY_0);
68 val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1);
69 nlm_write_usb_reg(port_addr, USB_PHY_0, val);
70
71 mdelay(100);
72 val = nlm_read_usb_reg(port_addr, USB_CTL_0);
73 val &= ~(USB_CONTROLLER_RESET);
74 val |= 0x4;
75 nlm_write_usb_reg(port_addr, USB_CTL_0, val);
76}
77
78static int __init nlm_platform_usb_init(void)
79{
80 pr_info("Initializing USB Interface\n");
81 nlm_usb_hw_reset(0, 0);
82 nlm_usb_hw_reset(0, 3);
83
84 /* Enable PHY interrupts */
85 nlm_usb_intr_en(0, 0);
86 nlm_usb_intr_en(0, 3);
87
88 return 0;
89}
90
91arch_initcall(nlm_platform_usb_init);
92
93static u64 xlp_usb_dmamask = ~(u32)0;
94
95/* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */
96static void nlm_usb_fixup_final(struct pci_dev *dev)
97{
98 dev->dev.dma_mask = &xlp_usb_dmamask;
99 dev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
100 switch (dev->devfn) {
101 case 0x10:
102 dev->irq = PIC_EHCI_0_IRQ;
103 break;
104 case 0x11:
105 dev->irq = PIC_OHCI_0_IRQ;
106 break;
107 case 0x12:
108 dev->irq = PIC_OHCI_1_IRQ;
109 break;
110 case 0x13:
111 dev->irq = PIC_EHCI_1_IRQ;
112 break;
113 case 0x14:
114 dev->irq = PIC_OHCI_2_IRQ;
115 break;
116 case 0x15:
117 dev->irq = PIC_OHCI_3_IRQ;
118 break;
119 }
120}
121DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI,
122 nlm_usb_fixup_final);
123DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI,
124 nlm_usb_fixup_final);
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index f01e4d7a0600..c287dea87570 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,2 +1,2 @@
1obj-y += setup.o platform.o 1obj-y += setup.o platform.o platform-flash.o
2obj-$(CONFIG_SMP) += wakeup.o 2obj-$(CONFIG_SMP) += wakeup.o
diff --git a/arch/mips/netlogic/xlr/platform-flash.c b/arch/mips/netlogic/xlr/platform-flash.c
new file mode 100644
index 000000000000..340ab1601c42
--- /dev/null
+++ b/arch/mips/netlogic/xlr/platform-flash.c
@@ -0,0 +1,220 @@
1/*
2 * Copyright 2011, Netlogic Microsystems.
3 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/ioport.h>
17#include <linux/resource.h>
18#include <linux/spi/flash.h>
19
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/physmap.h>
22#include <linux/mtd/nand.h>
23#include <linux/mtd/partitions.h>
24
25#include <asm/netlogic/haldefs.h>
26#include <asm/netlogic/xlr/iomap.h>
27#include <asm/netlogic/xlr/flash.h>
28#include <asm/netlogic/xlr/bridge.h>
29#include <asm/netlogic/xlr/gpio.h>
30#include <asm/netlogic/xlr/xlr.h>
31
32/*
33 * Default NOR partition layout
34 */
35static struct mtd_partition xlr_nor_parts[] = {
36 {
37 .name = "User FS",
38 .offset = 0x800000,
39 .size = MTDPART_SIZ_FULL,
40 }
41};
42
43/*
44 * Default NAND partition layout
45 */
46static struct mtd_partition xlr_nand_parts[] = {
47 {
48 .name = "Root Filesystem",
49 .offset = 64 * 64 * 2048,
50 .size = 432 * 64 * 2048,
51 },
52 {
53 .name = "Home Filesystem",
54 .offset = MTDPART_OFS_APPEND,
55 .size = MTDPART_SIZ_FULL,
56 },
57};
58
59/* Use PHYSMAP flash for NOR */
60struct physmap_flash_data xlr_nor_data = {
61 .width = 2,
62 .parts = xlr_nor_parts,
63 .nr_parts = ARRAY_SIZE(xlr_nor_parts),
64};
65
66static struct resource xlr_nor_res[] = {
67 {
68 .flags = IORESOURCE_MEM,
69 },
70};
71
72static struct platform_device xlr_nor_dev = {
73 .name = "physmap-flash",
74 .dev = {
75 .platform_data = &xlr_nor_data,
76 },
77 .num_resources = ARRAY_SIZE(xlr_nor_res),
78 .resource = xlr_nor_res,
79};
80
81const char *xlr_part_probes[] = { "cmdlinepart", NULL };
82
83/*
84 * Use "gen_nand" driver for NAND flash
85 *
86 * There seems to be no way to store a private pointer containing
87 * platform specific info in gen_nand drivier. We will use a global
88 * struct for now, since we currently have only one NAND chip per board.
89 */
90struct xlr_nand_flash_priv {
91 int cs;
92 uint64_t flash_mmio;
93};
94
95static struct xlr_nand_flash_priv nand_priv;
96
97static void xlr_nand_ctrl(struct mtd_info *mtd, int cmd,
98 unsigned int ctrl)
99{
100 if (ctrl & NAND_CLE)
101 nlm_write_reg(nand_priv.flash_mmio,
102 FLASH_NAND_CLE(nand_priv.cs), cmd);
103 else if (ctrl & NAND_ALE)
104 nlm_write_reg(nand_priv.flash_mmio,
105 FLASH_NAND_ALE(nand_priv.cs), cmd);
106}
107
108struct platform_nand_data xlr_nand_data = {
109 .chip = {
110 .nr_chips = 1,
111 .nr_partitions = ARRAY_SIZE(xlr_nand_parts),
112 .chip_delay = 50,
113 .partitions = xlr_nand_parts,
114 .part_probe_types = xlr_part_probes,
115 },
116 .ctrl = {
117 .cmd_ctrl = xlr_nand_ctrl,
118 },
119};
120
121static struct resource xlr_nand_res[] = {
122 {
123 .flags = IORESOURCE_MEM,
124 },
125};
126
127static struct platform_device xlr_nand_dev = {
128 .name = "gen_nand",
129 .id = -1,
130 .num_resources = ARRAY_SIZE(xlr_nand_res),
131 .resource = xlr_nand_res,
132 .dev = {
133 .platform_data = &xlr_nand_data,
134 }
135};
136
137/*
138 * XLR/XLS supports upto 8 devices on its FLASH interface. The value in
139 * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the
140 * flash devices.
141 * Under this, each flash device has an offset and size given by the
142 * CSBASE_ADDR and CSBASE_MASK registers for the device.
143 *
144 * The CSBASE_ registers are expected to be setup by the bootloader.
145 */
146static void setup_flash_resource(uint64_t flash_mmio,
147 uint64_t flash_map_base, int cs, struct resource *res)
148{
149 u32 base, mask;
150
151 base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs));
152 mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs));
153
154 res->start = flash_map_base + ((unsigned long)base << 16);
155 res->end = res->start + (mask + 1) * 64 * 1024;
156}
157
158static int __init xlr_flash_init(void)
159{
160 uint64_t gpio_mmio, flash_mmio, flash_map_base;
161 u32 gpio_resetcfg, flash_bar;
162 int cs, boot_nand, boot_nor;
163
164 /* Flash address bits 39:24 is in bridge flash BAR */
165 flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR);
166 flash_map_base = (flash_bar & 0xffff0000) << 8;
167
168 gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
169 flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET);
170
171 /* Get the chip reset config */
172 gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG);
173
174 /* Check for boot flash type */
175 boot_nor = boot_nand = 0;
176 if (nlm_chip_is_xls()) {
177 /* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */
178 if (gpio_resetcfg & (1 << 16))
179 boot_nand = 1;
180
181 /* check boot from PCMCIA, (GPIO reset reg bit 15 */
182 if ((gpio_resetcfg & (1 << 15)) == 0)
183 boot_nor = 1; /* not set, booted from NOR */
184 } else { /* XLR */
185 /* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */
186 if ((gpio_resetcfg & (1 << 16)) == 0)
187 boot_nor = 1; /* not set, booted from NOR */
188 }
189
190 /* boot flash at chip select 0 */
191 cs = 0;
192
193 if (boot_nand) {
194 nand_priv.cs = cs;
195 nand_priv.flash_mmio = flash_mmio;
196 setup_flash_resource(flash_mmio, flash_map_base, cs,
197 xlr_nand_res);
198
199 /* Initialize NAND flash at CS 0 */
200 nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs),
201 FLASH_NAND_CSDEV_PARAM);
202 nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs),
203 FLASH_NAND_CSTIME_PARAMA);
204 nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs),
205 FLASH_NAND_CSTIME_PARAMB);
206
207 pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res);
208 return platform_device_register(&xlr_nand_dev);
209 }
210
211 if (boot_nor) {
212 setup_flash_resource(flash_mmio, flash_map_base, cs,
213 xlr_nor_res);
214 pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res);
215 return platform_device_register(&xlr_nor_dev);
216 }
217 return 0;
218}
219
220arch_initcall(xlr_flash_init);
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index eab64b45dffd..71b44d82621d 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -14,6 +14,7 @@
14#include <linux/resource.h> 14#include <linux/resource.h>
15#include <linux/serial_8250.h> 15#include <linux/serial_8250.h>
16#include <linux/serial_reg.h> 16#include <linux/serial_reg.h>
17#include <linux/i2c.h>
17 18
18#include <asm/netlogic/haldefs.h> 19#include <asm/netlogic/haldefs.h>
19#include <asm/netlogic/xlr/iomap.h> 20#include <asm/netlogic/xlr/iomap.h>
@@ -97,3 +98,142 @@ static int __init nlm_uart_init(void)
97} 98}
98 99
99arch_initcall(nlm_uart_init); 100arch_initcall(nlm_uart_init);
101
102#ifdef CONFIG_USB
103/* Platform USB devices, only on XLS chips */
104static u64 xls_usb_dmamask = ~(u32)0;
105#define USB_PLATFORM_DEV(n, i, irq) \
106 { \
107 .name = n, \
108 .id = i, \
109 .num_resources = 2, \
110 .dev = { \
111 .dma_mask = &xls_usb_dmamask, \
112 .coherent_dma_mask = 0xffffffff, \
113 }, \
114 .resource = (struct resource[]) { \
115 { \
116 .flags = IORESOURCE_MEM, \
117 }, \
118 { \
119 .start = irq, \
120 .end = irq, \
121 .flags = IORESOURCE_IRQ, \
122 }, \
123 }, \
124 }
125
126static struct platform_device xls_usb_ehci_device =
127 USB_PLATFORM_DEV("ehci-xls", 0, PIC_USB_IRQ);
128static struct platform_device xls_usb_ohci_device_0 =
129 USB_PLATFORM_DEV("ohci-xls-0", 1, PIC_USB_IRQ);
130static struct platform_device xls_usb_ohci_device_1 =
131 USB_PLATFORM_DEV("ohci-xls-1", 2, PIC_USB_IRQ);
132
133static struct platform_device *xls_platform_devices[] = {
134 &xls_usb_ehci_device,
135 &xls_usb_ohci_device_0,
136 &xls_usb_ohci_device_1,
137};
138
139int xls_platform_usb_init(void)
140{
141 uint64_t usb_mmio, gpio_mmio;
142 unsigned long memres;
143 uint32_t val;
144
145 if (!nlm_chip_is_xls())
146 return 0;
147
148 gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
149 usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_1_OFFSET);
150
151 /* Clear Rogue Phy INTs */
152 nlm_write_reg(usb_mmio, 49, 0x10000000);
153 /* Enable all interrupts */
154 nlm_write_reg(usb_mmio, 50, 0x1f000000);
155
156 /* Enable ports */
157 nlm_write_reg(usb_mmio, 1, 0x07000500);
158
159 val = nlm_read_reg(gpio_mmio, 21);
160 if (((val >> 22) & 0x01) == 0) {
161 pr_info("Detected USB Device mode - Not supported!\n");
162 nlm_write_reg(usb_mmio, 0, 0x01000000);
163 return 0;
164 }
165
166 pr_info("Detected USB Host mode - Adding XLS USB devices.\n");
167 /* Clear reset, host mode */
168 nlm_write_reg(usb_mmio, 0, 0x02000000);
169
170 /* Memory resource for various XLS usb ports */
171 usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_0_OFFSET);
172 memres = CPHYSADDR((unsigned long)usb_mmio);
173 xls_usb_ehci_device.resource[0].start = memres;
174 xls_usb_ehci_device.resource[0].end = memres + 0x400 - 1;
175
176 memres += 0x400;
177 xls_usb_ohci_device_0.resource[0].start = memres;
178 xls_usb_ohci_device_0.resource[0].end = memres + 0x400 - 1;
179
180 memres += 0x400;
181 xls_usb_ohci_device_1.resource[0].start = memres;
182 xls_usb_ohci_device_1.resource[0].end = memres + 0x400 - 1;
183
184 return platform_add_devices(xls_platform_devices,
185 ARRAY_SIZE(xls_platform_devices));
186}
187
188arch_initcall(xls_platform_usb_init);
189#endif
190
191#ifdef CONFIG_I2C
192static struct i2c_board_info nlm_i2c_board_info1[] __initdata = {
193 /* All XLR boards have this RTC and Max6657 Temp Chip */
194 [0] = {
195 .type = "ds1374",
196 .addr = 0x68
197 },
198 [1] = {
199 .type = "lm90",
200 .addr = 0x4c
201 },
202};
203
204static struct resource i2c_resources[] = {
205 [0] = {
206 .start = 0, /* filled at init */
207 .end = 0,
208 .flags = IORESOURCE_MEM,
209 },
210};
211
212static struct platform_device nlm_xlr_i2c_1 = {
213 .name = "xlr-i2cbus",
214 .id = 1,
215 .num_resources = 1,
216 .resource = i2c_resources,
217};
218
219static int __init nlm_i2c_init(void)
220{
221 int err = 0;
222 unsigned int offset;
223
224 /* I2C bus 0 does not have any useful devices, configure only bus 1 */
225 offset = NETLOGIC_IO_I2C_1_OFFSET;
226 nlm_xlr_i2c_1.resource[0].start = CPHYSADDR(nlm_mmio_base(offset));
227 nlm_xlr_i2c_1.resource[0].end = nlm_xlr_i2c_1.resource[0].start + 0xfff;
228
229 platform_device_register(&nlm_xlr_i2c_1);
230
231 err = i2c_register_board_info(1, nlm_i2c_board_info1,
232 ARRAY_SIZE(nlm_i2c_board_info1));
233 if (err < 0)
234 pr_err("nlm-i2c: cannot register board I2C devices\n");
235 return err;
236}
237
238arch_initcall(nlm_i2c_init);
239#endif
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index c9d066dedc4e..81b1d311834f 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -85,7 +85,7 @@ static void nlm_linux_exit(void)
85 85
86 gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET); 86 gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
87 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */ 87 /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
88 nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1); 88 nlm_write_reg(gpiobase, GPIO_SWRESET_REG, 1);
89 for ( ; ; ) 89 for ( ; ; )
90 cpu_wait(); 90 cpu_wait();
91} 91}
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index b6e378211a2c..f80480a5a032 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -85,6 +85,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
85 case CPU_34K: 85 case CPU_34K:
86 case CPU_1004K: 86 case CPU_1004K:
87 case CPU_74K: 87 case CPU_74K:
88 case CPU_LOONGSON1:
88 case CPU_SB1: 89 case CPU_SB1:
89 case CPU_SB1A: 90 case CPU_SB1A:
90 case CPU_R10000: 91 case CPU_R10000:
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 4d80a856048d..28ea1a4cc576 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -339,12 +339,6 @@ static int __init mipsxx_init(void)
339 break; 339 break;
340 340
341 case CPU_1004K: 341 case CPU_1004K:
342#if 0
343 /* FIXME: report as 34K for now */
344 op_model_mipsxx_ops.cpu_type = "mips/1004K";
345 break;
346#endif
347
348 case CPU_34K: 342 case CPU_34K:
349 op_model_mipsxx_ops.cpu_type = "mips/34K"; 343 op_model_mipsxx_ops.cpu_type = "mips/34K";
350 break; 344 break;
@@ -374,6 +368,10 @@ static int __init mipsxx_init(void)
374 op_model_mipsxx_ops.cpu_type = "mips/sb1"; 368 op_model_mipsxx_ops.cpu_type = "mips/sb1";
375 break; 369 break;
376 370
371 case CPU_LOONGSON1:
372 op_model_mipsxx_ops.cpu_type = "mips/loongson1";
373 break;
374
377 default: 375 default:
378 printk(KERN_ERR "Profiling unsupported for this CPU\n"); 376 printk(KERN_ERR "Profiling unsupported for this CPU\n");
379 377
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c703f43a9914..e13a71cbc3c7 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
59obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o 59obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
60obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o 60obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
61obj-$(CONFIG_CPU_XLR) += pci-xlr.o 61obj-$(CONFIG_CPU_XLR) += pci-xlr.o
62obj-$(CONFIG_CPU_XLP) += pci-xlp.o
62 63
63ifdef CONFIG_PCI_MSI 64ifdef CONFIG_PCI_MSI
64obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o 65obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 9553b14002dd..3e7ce65d776c 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -37,7 +37,7 @@
37#define VIA_COBALT_BRD_ID_REG 0x94 37#define VIA_COBALT_BRD_ID_REG 0x94
38#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4) 38#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4)
39 39
40static void qube_raq_galileo_early_fixup(struct pci_dev *dev) 40static void __devinit qube_raq_galileo_early_fixup(struct pci_dev *dev)
41{ 41{
42 if (dev->devfn == PCI_DEVFN(0, 0) && 42 if (dev->devfn == PCI_DEVFN(0, 0) &&
43 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) { 43 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
@@ -51,7 +51,7 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
51DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111, 51DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
52 qube_raq_galileo_early_fixup); 52 qube_raq_galileo_early_fixup);
53 53
54static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev) 54static void __devinit qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
55{ 55{
56 unsigned short cfgword; 56 unsigned short cfgword;
57 unsigned char lt; 57 unsigned char lt;
@@ -74,7 +74,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
74DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 74DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
75 qube_raq_via_bmIDE_fixup); 75 qube_raq_via_bmIDE_fixup);
76 76
77static void qube_raq_galileo_fixup(struct pci_dev *dev) 77static void __devinit qube_raq_galileo_fixup(struct pci_dev *dev)
78{ 78{
79 if (dev->devfn != PCI_DEVFN(0, 0)) 79 if (dev->devfn != PCI_DEVFN(0, 0))
80 return; 80 return;
@@ -129,7 +129,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
129 129
130int cobalt_board_id; 130int cobalt_board_id;
131 131
132static void qube_raq_via_board_id_fixup(struct pci_dev *dev) 132static void __devinit qube_raq_via_board_id_fixup(struct pci_dev *dev)
133{ 133{
134 u8 id; 134 u8 id;
135 int retval; 135 int retval;
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index 70073c98ed32..819622f93e9c 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -101,3 +101,17 @@ static void __devinit malta_piix_func1_fixup(struct pci_dev *pdev)
101 101
102DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, 102DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
103 malta_piix_func1_fixup); 103 malta_piix_func1_fixup);
104
105/* Enable PCI 2.1 compatibility in PIIX4 */
106static void __devinit quirk_dlcsetup(struct pci_dev *dev)
107{
108 u8 odlc, ndlc;
109
110 (void) pci_read_config_byte(dev, 0x82, &odlc);
111 /* Enable passive releases and delayed transaction */
112 ndlc = odlc | 7;
113 (void) pci_write_config_byte(dev, 0x82, ndlc);
114}
115
116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
117 quirk_dlcsetup);
diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c
index 3d86823d03a0..76bb1be99d43 100644
--- a/arch/mips/pci/fixup-rc32434.c
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -47,7 +47,7 @@ int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
47 return irq + GROUP4_IRQ_BASE + 4; 47 return irq + GROUP4_IRQ_BASE + 4;
48} 48}
49 49
50static void rc32434_pci_early_fixup(struct pci_dev *dev) 50static void __devinit rc32434_pci_early_fixup(struct pci_dev *dev)
51{ 51{
52 if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) { 52 if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
53 /* disable prefetched memory range */ 53 /* disable prefetched memory range */
diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
index 822ae179bc56..65c7bd100486 100644
--- a/arch/mips/pci/ops-bcm63xx.c
+++ b/arch/mips/pci/ops-bcm63xx.c
@@ -411,7 +411,7 @@ struct pci_ops bcm63xx_cb_ops = {
411 * only one IO window, so it cannot be shared by PCI and cardbus, use 411 * only one IO window, so it cannot be shared by PCI and cardbus, use
412 * fixup to choose and detect unhandled configuration 412 * fixup to choose and detect unhandled configuration
413 */ 413 */
414static void bcm63xx_fixup(struct pci_dev *dev) 414static void __devinit bcm63xx_fixup(struct pci_dev *dev)
415{ 415{
416 static int io_window = -1; 416 static int io_window = -1;
417 int i, found, new_io_window; 417 int i, found, new_io_window;
@@ -465,3 +465,64 @@ static void bcm63xx_fixup(struct pci_dev *dev)
465 465
466DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup); 466DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
467#endif 467#endif
468
469static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
470{
471 switch (bus->number) {
472 case PCIE_BUS_BRIDGE:
473 return (PCI_SLOT(devfn) == 0);
474 case PCIE_BUS_DEVICE:
475 if (PCI_SLOT(devfn) == 0)
476 return bcm_pcie_readl(PCIE_DLSTATUS_REG)
477 & DLSTATUS_PHYLINKUP;
478 default:
479 return false;
480 }
481}
482
483static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
484 int where, int size, u32 *val)
485{
486 u32 data;
487 u32 reg = where & ~3;
488
489 if (!bcm63xx_pcie_can_access(bus, devfn))
490 return PCIBIOS_DEVICE_NOT_FOUND;
491
492 if (bus->number == PCIE_BUS_DEVICE)
493 reg += PCIE_DEVICE_OFFSET;
494
495 data = bcm_pcie_readl(reg);
496
497 *val = postprocess_read(data, where, size);
498
499 return PCIBIOS_SUCCESSFUL;
500
501}
502
503static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
504 int where, int size, u32 val)
505{
506 u32 data;
507 u32 reg = where & ~3;
508
509 if (!bcm63xx_pcie_can_access(bus, devfn))
510 return PCIBIOS_DEVICE_NOT_FOUND;
511
512 if (bus->number == PCIE_BUS_DEVICE)
513 reg += PCIE_DEVICE_OFFSET;
514
515
516 data = bcm_pcie_readl(reg);
517
518 data = preprocess_write(data, val, where, size);
519 bcm_pcie_writel(data, reg);
520
521 return PCIBIOS_SUCCESSFUL;
522}
523
524
525struct pci_ops bcm63xx_pcie_ops = {
526 .read = bcm63xx_pcie_read,
527 .write = bcm63xx_pcie_write
528};
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 39eb7c417e2f..8a48139d219c 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -10,6 +10,7 @@
10#include <linux/pci.h> 10#include <linux/pci.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/delay.h>
13#include <asm/bootinfo.h> 14#include <asm/bootinfo.h>
14 15
15#include "pci-bcm63xx.h" 16#include "pci-bcm63xx.h"
@@ -71,6 +72,26 @@ struct pci_controller bcm63xx_cb_controller = {
71}; 72};
72#endif 73#endif
73 74
75static struct resource bcm_pcie_mem_resource = {
76 .name = "bcm63xx PCIe memory space",
77 .start = BCM_PCIE_MEM_BASE_PA,
78 .end = BCM_PCIE_MEM_END_PA,
79 .flags = IORESOURCE_MEM,
80};
81
82static struct resource bcm_pcie_io_resource = {
83 .name = "bcm63xx PCIe IO space",
84 .start = 0,
85 .end = 0,
86 .flags = 0,
87};
88
89struct pci_controller bcm63xx_pcie_controller = {
90 .pci_ops = &bcm63xx_pcie_ops,
91 .io_resource = &bcm_pcie_io_resource,
92 .mem_resource = &bcm_pcie_mem_resource,
93};
94
74static u32 bcm63xx_int_cfg_readl(u32 reg) 95static u32 bcm63xx_int_cfg_readl(u32 reg)
75{ 96{
76 u32 tmp; 97 u32 tmp;
@@ -94,17 +115,99 @@ static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
94 115
95void __iomem *pci_iospace_start; 116void __iomem *pci_iospace_start;
96 117
97static int __init bcm63xx_pci_init(void) 118static void __init bcm63xx_reset_pcie(void)
98{ 119{
99 unsigned int mem_size;
100 u32 val; 120 u32 val;
101 121
102 if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368()) 122 /* enable clock */
103 return -ENODEV; 123 val = bcm_perf_readl(PERF_CKCTL_REG);
124 val |= CKCTL_6328_PCIE_EN;
125 bcm_perf_writel(val, PERF_CKCTL_REG);
126
127 /* enable SERDES */
128 val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
129 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
130 bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
131
132 /* reset the PCIe core */
133 val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
134
135 val &= ~SOFTRESET_6328_PCIE_MASK;
136 val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
137 val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
138 val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
139 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
140 mdelay(10);
141
142 val |= SOFTRESET_6328_PCIE_MASK;
143 val |= SOFTRESET_6328_PCIE_CORE_MASK;
144 val |= SOFTRESET_6328_PCIE_HARD_MASK;
145 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
146 mdelay(10);
147
148 val |= SOFTRESET_6328_PCIE_EXT_MASK;
149 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
150 mdelay(200);
151}
104 152
105 if (!bcm63xx_pci_enabled) 153static int __init bcm63xx_register_pcie(void)
106 return -ENODEV; 154{
155 u32 val;
107 156
157 bcm63xx_reset_pcie();
158
159 /* configure the PCIe bridge */
160 val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
161 val |= OPT1_RD_BE_OPT_EN;
162 val |= OPT1_RD_REPLY_BE_FIX_EN;
163 val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
164 val |= OPT1_L1_INT_STATUS_MASK_POL;
165 bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
166
167 /* setup the interrupts */
168 val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
169 val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
170 bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
171
172 val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
173 /* enable credit checking and error checking */
174 val |= OPT2_TX_CREDIT_CHK_EN;
175 val |= OPT2_UBUS_UR_DECODE_DIS;
176
177 /* set device bus/func for the pcie device */
178 val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
179 val |= OPT2_CFG_TYPE1_BD_SEL;
180 bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
181
182 /* setup class code as bridge */
183 val = bcm_pcie_readl(PCIE_IDVAL3_REG);
184 val &= ~IDVAL3_CLASS_CODE_MASK;
185 val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
186 bcm_pcie_writel(val, PCIE_IDVAL3_REG);
187
188 /* disable bar1 size */
189 val = bcm_pcie_readl(PCIE_CONFIG2_REG);
190 val &= ~CONFIG2_BAR1_SIZE_MASK;
191 bcm_pcie_writel(val, PCIE_CONFIG2_REG);
192
193 /* set bar0 to little endian */
194 val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
195 val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
196 val |= BASEMASK_REMAP_EN;
197 bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
198
199 val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
200 bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
201
202 register_pci_controller(&bcm63xx_pcie_controller);
203
204 return 0;
205}
206
207static int __init bcm63xx_register_pci(void)
208{
209 unsigned int mem_size;
210 u32 val;
108 /* 211 /*
109 * configuration access are done through IO space, remap 4 212 * configuration access are done through IO space, remap 4
110 * first bytes to access it from CPU. 213 * first bytes to access it from CPU.
@@ -221,4 +324,22 @@ static int __init bcm63xx_pci_init(void)
221 return 0; 324 return 0;
222} 325}
223 326
327
328static int __init bcm63xx_pci_init(void)
329{
330 if (!bcm63xx_pci_enabled)
331 return -ENODEV;
332
333 switch (bcm63xx_get_cpu_id()) {
334 case BCM6328_CPU_ID:
335 return bcm63xx_register_pcie();
336 case BCM6348_CPU_ID:
337 case BCM6358_CPU_ID:
338 case BCM6368_CPU_ID:
339 return bcm63xx_register_pci();
340 default:
341 return -ENODEV;
342 }
343}
344
224arch_initcall(bcm63xx_pci_init); 345arch_initcall(bcm63xx_pci_init);
diff --git a/arch/mips/pci/pci-bcm63xx.h b/arch/mips/pci/pci-bcm63xx.h
index a6e594ef3d6a..e6736d558ac7 100644
--- a/arch/mips/pci/pci-bcm63xx.h
+++ b/arch/mips/pci/pci-bcm63xx.h
@@ -13,11 +13,16 @@
13 */ 13 */
14#define CARDBUS_PCI_IDSEL 0x8 14#define CARDBUS_PCI_IDSEL 0x8
15 15
16
17#define PCIE_BUS_BRIDGE 0
18#define PCIE_BUS_DEVICE 1
19
16/* 20/*
17 * defined in ops-bcm63xx.c 21 * defined in ops-bcm63xx.c
18 */ 22 */
19extern struct pci_ops bcm63xx_pci_ops; 23extern struct pci_ops bcm63xx_pci_ops;
20extern struct pci_ops bcm63xx_cb_ops; 24extern struct pci_ops bcm63xx_cb_ops;
25extern struct pci_ops bcm63xx_pcie_ops;
21 26
22/* 27/*
23 * defined in pci-bcm63xx.c 28 * defined in pci-bcm63xx.c
diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c
new file mode 100644
index 000000000000..140557a20488
--- /dev/null
+++ b/arch/mips/pci/pci-xlp.c
@@ -0,0 +1,248 @@
1/*
2 * Copyright (c) 2003-2012 Broadcom Corporation
3 * All Rights Reserved
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <linux/pci.h>
37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/msi.h>
40#include <linux/mm.h>
41#include <linux/irq.h>
42#include <linux/irqdesc.h>
43#include <linux/console.h>
44
45#include <asm/io.h>
46
47#include <asm/netlogic/interrupt.h>
48#include <asm/netlogic/haldefs.h>
49
50#include <asm/netlogic/xlp-hal/iomap.h>
51#include <asm/netlogic/xlp-hal/pic.h>
52#include <asm/netlogic/xlp-hal/xlp.h>
53#include <asm/netlogic/xlp-hal/pcibus.h>
54#include <asm/netlogic/xlp-hal/bridge.h>
55
56static void *pci_config_base;
57
58#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
59
60/* PCI ops */
61static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
62 int where)
63{
64 u32 data;
65 u32 *cfgaddr;
66
67 cfgaddr = (u32 *)(pci_config_base +
68 pci_cfg_addr(bus->number, devfn, where & ~3));
69 data = *cfgaddr;
70 return data;
71}
72
73static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
74 int where, u32 data)
75{
76 u32 *cfgaddr;
77
78 cfgaddr = (u32 *)(pci_config_base +
79 pci_cfg_addr(bus->number, devfn, where & ~3));
80 *cfgaddr = data;
81}
82
83static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
84 int where, int size, u32 *val)
85{
86 u32 data;
87
88 if ((size == 2) && (where & 1))
89 return PCIBIOS_BAD_REGISTER_NUMBER;
90 else if ((size == 4) && (where & 3))
91 return PCIBIOS_BAD_REGISTER_NUMBER;
92
93 data = pci_cfg_read_32bit(bus, devfn, where);
94
95 if (size == 1)
96 *val = (data >> ((where & 3) << 3)) & 0xff;
97 else if (size == 2)
98 *val = (data >> ((where & 3) << 3)) & 0xffff;
99 else
100 *val = data;
101
102 return PCIBIOS_SUCCESSFUL;
103}
104
105
106static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
107 int where, int size, u32 val)
108{
109 u32 data;
110
111 if ((size == 2) && (where & 1))
112 return PCIBIOS_BAD_REGISTER_NUMBER;
113 else if ((size == 4) && (where & 3))
114 return PCIBIOS_BAD_REGISTER_NUMBER;
115
116 data = pci_cfg_read_32bit(bus, devfn, where);
117
118 if (size == 1)
119 data = (data & ~(0xff << ((where & 3) << 3))) |
120 (val << ((where & 3) << 3));
121 else if (size == 2)
122 data = (data & ~(0xffff << ((where & 3) << 3))) |
123 (val << ((where & 3) << 3));
124 else
125 data = val;
126
127 pci_cfg_write_32bit(bus, devfn, where, data);
128
129 return PCIBIOS_SUCCESSFUL;
130}
131
132struct pci_ops nlm_pci_ops = {
133 .read = nlm_pcibios_read,
134 .write = nlm_pcibios_write
135};
136
137static struct resource nlm_pci_mem_resource = {
138 .name = "XLP PCI MEM",
139 .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
140 .end = 0xdfffffffUL,
141 .flags = IORESOURCE_MEM,
142};
143
144static struct resource nlm_pci_io_resource = {
145 .name = "XLP IO MEM",
146 .start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
147 .end = 0x17ffffffUL,
148 .flags = IORESOURCE_IO,
149};
150
151struct pci_controller nlm_pci_controller = {
152 .index = 0,
153 .pci_ops = &nlm_pci_ops,
154 .mem_resource = &nlm_pci_mem_resource,
155 .mem_offset = 0x00000000UL,
156 .io_resource = &nlm_pci_io_resource,
157 .io_offset = 0x00000000UL,
158};
159
160static int get_irq_vector(const struct pci_dev *dev)
161{
162 /*
163 * For XLP PCIe, there is an IRQ per Link, find out which
164 * link the device is on to assign interrupts
165 */
166 if (dev->bus->self == NULL)
167 return 0;
168
169 switch (dev->bus->self->devfn) {
170 case 0x8:
171 return PIC_PCIE_LINK_0_IRQ;
172 case 0x9:
173 return PIC_PCIE_LINK_1_IRQ;
174 case 0xa:
175 return PIC_PCIE_LINK_2_IRQ;
176 case 0xb:
177 return PIC_PCIE_LINK_3_IRQ;
178 }
179 WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
180 return 0;
181}
182
183int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
184{
185 return get_irq_vector(dev);
186}
187
188/* Do platform specific device initialization at pci_enable_device() time */
189int pcibios_plat_dev_init(struct pci_dev *dev)
190{
191 return 0;
192}
193
194static int xlp_enable_pci_bswap(void)
195{
196 uint64_t pciebase, sysbase;
197 int node, i;
198 u32 reg;
199
200 /* Chip-0 so node set to 0 */
201 node = 0;
202 sysbase = nlm_get_bridge_regbase(node);
203 /*
204 * Enable byte swap in hardware. Program each link's PCIe SWAP regions
205 * from the link's address ranges.
206 */
207 for (i = 0; i < 4; i++) {
208 pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i));
209 if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
210 continue;
211
212 reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i);
213 nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg);
214
215 reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i);
216 nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM,
217 reg | 0xfff);
218
219 reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i);
220 nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg);
221
222 reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
223 nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
224 }
225 return 0;
226}
227
228static int __init pcibios_init(void)
229{
230 /* Firmware assigns PCI resources */
231 pci_set_flags(PCI_PROBE_ONLY);
232 pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
233
234 /* Extend IO port for memory mapped io */
235 ioport_resource.start = 0;
236 ioport_resource.end = ~0;
237
238 xlp_enable_pci_bswap();
239 set_io_port_base(CKSEG1);
240 nlm_pci_controller.io_map_base = CKSEG1;
241
242 register_pci_controller(&nlm_pci_controller);
243 pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
244 &nlm_pci_mem_resource);
245
246 return 0;
247}
248arch_initcall(pcibios_init);
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 172af1cd5867..18af021d289a 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -375,7 +375,3 @@ static int __init pcibios_init(void)
375} 375}
376 376
377arch_initcall(pcibios_init); 377arch_initcall(pcibios_init);
378
379struct pci_fixup pcibios_fixups[] = {
380 {0}
381};
diff --git a/arch/mips/pnx833x/stb22x/board.c b/arch/mips/pnx833x/stb22x/board.c
index 644eb7c3210f..4b328ac43050 100644
--- a/arch/mips/pnx833x/stb22x/board.c
+++ b/arch/mips/pnx833x/stb22x/board.c
@@ -91,7 +91,7 @@ void __init pnx833x_board_setup(void)
91 pnx833x_gpio_select_function_alt(32); 91 pnx833x_gpio_select_function_alt(32);
92 pnx833x_gpio_select_function_alt(33); 92 pnx833x_gpio_select_function_alt(33);
93 93
94#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) 94#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
95 /* Setup MIU for NAND access on CS0... 95 /* Setup MIU for NAND access on CS0...
96 * 96 *
97 * (it seems that we must also configure CS1 for reliable operation, 97 * (it seems that we must also configure CS1 for reliable operation,
@@ -117,7 +117,7 @@ void __init pnx833x_board_setup(void)
117 pnx833x_gpio_select_output(5); 117 pnx833x_gpio_select_output(5);
118 pnx833x_gpio_write(1, 5); 118 pnx833x_gpio_write(1, 5);
119 119
120#elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE) 120#elif IS_ENABLED(CONFIG_MTD_CFI)
121 121
122 /* Set up MIU for 16-bit NOR access on CS0 and CS1... */ 122 /* Set up MIU for 16-bit NOR access on CS0 and CS1... */
123 123
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index 64eb71b15280..bab4953c292c 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -304,7 +304,7 @@ static void __devinit quirk_slc90e66_bridge(struct pci_dev *dev)
304 smsc_fdc37m81x_config_end(); 304 smsc_fdc37m81x_config_end();
305} 305}
306 306
307static void quirk_slc90e66_ide(struct pci_dev *dev) 307static void __devinit quirk_slc90e66_ide(struct pci_dev *dev)
308{ 308{
309 unsigned char dat; 309 unsigned char dat;
310 int regs[2] = {0x41, 0x43}; 310 int regs[2] = {0x41, 0x43};
@@ -339,7 +339,7 @@ static void quirk_slc90e66_ide(struct pci_dev *dev)
339} 339}
340#endif /* CONFIG_TOSHIBA_FPCIB0 */ 340#endif /* CONFIG_TOSHIBA_FPCIB0 */
341 341
342static void tc35815_fixup(struct pci_dev *dev) 342static void __devinit tc35815_fixup(struct pci_dev *dev)
343{ 343{
344 /* This device may have PM registers but not they are not suported. */ 344 /* This device may have PM registers but not they are not suported. */
345 if (dev->pm_cap) { 345 if (dev->pm_cap) {
@@ -348,7 +348,7 @@ static void tc35815_fixup(struct pci_dev *dev)
348 } 348 }
349} 349}
350 350
351static void final_fixup(struct pci_dev *dev) 351static void __devinit final_fixup(struct pci_dev *dev)
352{ 352{
353 unsigned char bist; 353 unsigned char bist;
354 354
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index ae77a7916c03..560fe8991753 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -632,7 +632,7 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr,
632 unsigned long size, 632 unsigned long size,
633 const struct physmap_flash_data *pdata) 633 const struct physmap_flash_data *pdata)
634{ 634{
635#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) 635#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
636 struct resource res = { 636 struct resource res = {
637 .start = addr, 637 .start = addr,
638 .end = addr + size - 1, 638 .end = addr + size - 1,
@@ -670,8 +670,7 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr,
670void __init txx9_ndfmc_init(unsigned long baseaddr, 670void __init txx9_ndfmc_init(unsigned long baseaddr,
671 const struct txx9ndfmc_platform_data *pdata) 671 const struct txx9ndfmc_platform_data *pdata)
672{ 672{
673#if defined(CONFIG_MTD_NAND_TXX9NDFMC) || \ 673#if IS_ENABLED(CONFIG_MTD_NAND_TXX9NDFMC)
674 defined(CONFIG_MTD_NAND_TXX9NDFMC_MODULE)
675 struct resource res = { 674 struct resource res = {
676 .start = baseaddr, 675 .start = baseaddr,
677 .end = baseaddr + 0x1000 - 1, 676 .end = baseaddr + 0x1000 - 1,
@@ -687,7 +686,7 @@ void __init txx9_ndfmc_init(unsigned long baseaddr,
687#endif 686#endif
688} 687}
689 688
690#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) 689#if IS_ENABLED(CONFIG_LEDS_GPIO)
691static DEFINE_SPINLOCK(txx9_iocled_lock); 690static DEFINE_SPINLOCK(txx9_iocled_lock);
692 691
693#define TXX9_IOCLED_MAXLEDS 8 692#define TXX9_IOCLED_MAXLEDS 8
@@ -810,7 +809,7 @@ void __init txx9_iocled_init(unsigned long baseaddr,
810void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq, 809void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq,
811 const struct txx9dmac_platform_data *pdata) 810 const struct txx9dmac_platform_data *pdata)
812{ 811{
813#if defined(CONFIG_TXX9_DMAC) || defined(CONFIG_TXX9_DMAC_MODULE) 812#if IS_ENABLED(CONFIG_TXX9_DMAC)
814 struct resource res[] = { 813 struct resource res[] = {
815 { 814 {
816 .start = baseaddr, 815 .start = baseaddr,
@@ -866,8 +865,7 @@ void __init txx9_aclc_init(unsigned long baseaddr, int irq,
866 unsigned int dma_chan_out, 865 unsigned int dma_chan_out,
867 unsigned int dma_chan_in) 866 unsigned int dma_chan_in)
868{ 867{
869#if defined(CONFIG_SND_SOC_TXX9ACLC) || \ 868#if IS_ENABLED(CONFIG_SND_SOC_TXX9ACLC)
870 defined(CONFIG_SND_SOC_TXX9ACLC_MODULE)
871 unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS; 869 unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS;
872 struct resource res[] = { 870 struct resource res[] = {
873 { 871 {
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
index 6567895d1f59..5ff7a9584daf 100644
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -317,7 +317,7 @@ void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
317 } 317 }
318} 318}
319 319
320#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE) 320#if IS_ENABLED(CONFIG_TC35815)
321static u32 tx4939_get_eth_speed(struct net_device *dev) 321static u32 tx4939_get_eth_speed(struct net_device *dev)
322{ 322{
323 struct ethtool_cmd cmd; 323 struct ethtool_cmd cmd;
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 2ad8973ba13d..e15641d93092 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -40,8 +40,7 @@ static void __init rbtx4939_time_init(void)
40 tx4939_time_init(0); 40 tx4939_time_init(0);
41} 41}
42 42
43#if defined(__BIG_ENDIAN) && \ 43#if defined(__BIG_ENDIAN) && IS_ENABLED(CONFIG_SMC91X)
44 (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE))
45#define HAVE_RBTX4939_IOSWAB 44#define HAVE_RBTX4939_IOSWAB
46#define IS_CE1_ADDR(addr) \ 45#define IS_CE1_ADDR(addr) \
47 ((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1)) 46 ((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1))
@@ -187,7 +186,7 @@ static void __init rbtx4939_update_ioc_pen(void)
187 186
188#define RBTX4939_MAX_7SEGLEDS 8 187#define RBTX4939_MAX_7SEGLEDS 8
189 188
190#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) 189#if IS_ENABLED(CONFIG_LEDS_CLASS)
191static u8 led_val[RBTX4939_MAX_7SEGLEDS]; 190static u8 led_val[RBTX4939_MAX_7SEGLEDS];
192struct rbtx4939_led_data { 191struct rbtx4939_led_data {
193 struct led_classdev cdev; 192 struct led_classdev cdev;
@@ -263,7 +262,7 @@ static inline void rbtx4939_led_setup(void)
263 262
264static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val) 263static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
265{ 264{
266#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE) 265#if IS_ENABLED(CONFIG_LEDS_CLASS)
267 unsigned long flags; 266 unsigned long flags;
268 local_irq_save(flags); 267 local_irq_save(flags);
269 /* bit7: reserved for LED class */ 268 /* bit7: reserved for LED class */
@@ -287,7 +286,7 @@ static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
287 __rbtx4939_7segled_putc(pos, val); 286 __rbtx4939_7segled_putc(pos, val);
288} 287}
289 288
290#if defined(CONFIG_MTD_RBTX4939) || defined(CONFIG_MTD_RBTX4939_MODULE) 289#if IS_ENABLED(CONFIG_MTD_RBTX4939)
291/* special mapping for boot rom */ 290/* special mapping for boot rom */
292static unsigned long rbtx4939_flash_fixup_ofs(unsigned long ofs) 291static unsigned long rbtx4939_flash_fixup_ofs(unsigned long ofs)
293{ 292{
@@ -463,7 +462,7 @@ static void __init rbtx4939_device_init(void)
463 .flags = SMC91X_USE_16BIT, 462 .flags = SMC91X_USE_16BIT,
464 }; 463 };
465 struct platform_device *pdev; 464 struct platform_device *pdev;
466#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE) 465#if IS_ENABLED(CONFIG_TC35815)
467 int i, j; 466 int i, j;
468 unsigned char ethaddr[2][6]; 467 unsigned char ethaddr[2][6];
469 u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; 468 u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 01:39:16 -0500