1 files changed, 6 insertions, 10 deletions

diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index ed1c54284b8f..52a1ba70b3b6 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -99,7 +99,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
          */
         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
         /* Set latency timers for all devices */
-        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
+        pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 
         /* Enable reporting System errors and parity errors on all devices */
         /* Enable parity checking and error reporting */
@@ -109,7 +109,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 
         if (dev->subordinate) {
                 /* Set latency timers on sub bridges */
-                pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
+                pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
                 /* More bridge error detection */
                 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
                 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
@@ -121,14 +121,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
         if (pos) {
                 /* Update Device Control */
                 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
-                /* Correctable Error Reporting */
-                config |= PCI_EXP_DEVCTL_CERE;
-                /* Non-Fatal Error Reporting */
-                config |= PCI_EXP_DEVCTL_NFERE;
-                /* Fatal Error Reporting */
-                config |= PCI_EXP_DEVCTL_FERE;
-                /* Unsupported Request */
-                config |= PCI_EXP_DEVCTL_URRE;
+                config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
+                config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
+                config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
+                config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
                 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
         }