diff options
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/sibyte/sb1250/irq.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 0f6e54db4888..f853c32f60a0 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c | |||
@@ -435,13 +435,17 @@ static inline int dclz(unsigned long long x) | |||
435 | return lz; | 435 | return lz; |
436 | } | 436 | } |
437 | 437 | ||
438 | extern void sb1250_timer_interrupt(struct pt_regs *regs); | ||
439 | extern void sb1250_mailbox_interrupt(struct pt_regs *regs); | ||
440 | extern void sb1250_kgdb_interrupt(struct pt_regs *regs); | ||
441 | |||
438 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) | 442 | asmlinkage void plat_irq_dispatch(struct pt_regs *regs) |
439 | { | 443 | { |
440 | unsigned int pending; | 444 | unsigned int pending; |
441 | 445 | ||
442 | #ifdef CONFIG_SIBYTE_SB1250_PROF | 446 | #ifdef CONFIG_SIBYTE_SB1250_PROF |
443 | /* Set compare to count to silence count/compare timer interrupts */ | 447 | /* Set compare to count to silence count/compare timer interrupts */ |
444 | write_c0_count(read_c0_count()); | 448 | write_c0_compare(read_c0_count()); |
445 | #endif | 449 | #endif |
446 | 450 | ||
447 | /* | 451 | /* |
@@ -482,7 +486,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs) | |||
482 | * Default...we've hit an IP[2] interrupt, which means we've | 486 | * Default...we've hit an IP[2] interrupt, which means we've |
483 | * got to check the 1250 interrupt registers to figure out what | 487 | * got to check the 1250 interrupt registers to figure out what |
484 | * to do. Need to detect which CPU we're on, now that | 488 | * to do. Need to detect which CPU we're on, now that |
485 | ~ smp_affinity is supported. | 489 | * smp_affinity is supported. |
486 | */ | 490 | */ |
487 | mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(), | 491 | mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(), |
488 | R_IMR_INTERRUPT_STATUS_BASE))); | 492 | R_IMR_INTERRUPT_STATUS_BASE))); |