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-rw-r--r--arch/mips/Makefile6
-rw-r--r--arch/mips/sibyte/Kconfig2
-rw-r--r--arch/mips/sibyte/common/Makefile5
-rw-r--r--arch/mips/sibyte/common/sb_tbprof.c (renamed from arch/mips/sibyte/sb1250/bcm1250_tbprof.c)158
-rw-r--r--arch/mips/sibyte/sb1250/Makefile1
5 files changed, 106 insertions, 66 deletions
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 92bca6ad6ab1..f2f742df32c7 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -530,25 +530,29 @@ cflags-$(CONFIG_SGI_IP32) += -Iinclude/asm-mips/mach-ip32
530load-$(CONFIG_SGI_IP32) += 0xffffffff80004000 530load-$(CONFIG_SGI_IP32) += 0xffffffff80004000
531 531
532# 532#
533# Sibyte SB1250 SOC 533# Sibyte SB1250/BCM1480 SOC
534# 534#
535# This is a LIB so that it links at the end, and initcalls are later 535# This is a LIB so that it links at the end, and initcalls are later
536# the sequence; but it is built as an object so that modules don't get 536# the sequence; but it is built as an object so that modules don't get
537# removed (as happens, even if they have __initcall/module_init) 537# removed (as happens, even if they have __initcall/module_init)
538# 538#
539core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/ 539core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/sb1250/
540core-$(CONFIG_SIBYTE_BCM112X) += arch/mips/sibyte/common/
540cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte \ 541cflags-$(CONFIG_SIBYTE_BCM112X) += -Iinclude/asm-mips/mach-sibyte \
541 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL 542 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
542 543
543core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/ 544core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/sb1250/
545core-$(CONFIG_SIBYTE_SB1250) += arch/mips/sibyte/common/
544cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte \ 546cflags-$(CONFIG_SIBYTE_SB1250) += -Iinclude/asm-mips/mach-sibyte \
545 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL 547 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
546 548
547core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/bcm1480/ 549core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/bcm1480/
550core-$(CONFIG_SIBYTE_BCM1x55) += arch/mips/sibyte/common/
548cflags-$(CONFIG_SIBYTE_BCM1x55) += -Iinclude/asm-mips/mach-sibyte \ 551cflags-$(CONFIG_SIBYTE_BCM1x55) += -Iinclude/asm-mips/mach-sibyte \
549 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL 552 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
550 553
551core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/bcm1480/ 554core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/bcm1480/
555core-$(CONFIG_SIBYTE_BCM1x80) += arch/mips/sibyte/common/
552cflags-$(CONFIG_SIBYTE_BCM1x80) += -Iinclude/asm-mips/mach-sibyte \ 556cflags-$(CONFIG_SIBYTE_BCM1x80) += -Iinclude/asm-mips/mach-sibyte \
553 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL 557 -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
554 558
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index bdf24a7b5494..e6b003ec6716 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -2,6 +2,7 @@ config SIBYTE_SB1250
2 bool 2 bool
3 select HW_HAS_PCI 3 select HW_HAS_PCI
4 select SIBYTE_ENABLE_LDT_IF_PCI 4 select SIBYTE_ENABLE_LDT_IF_PCI
5 select SIBYTE_HAS_ZBUS_PROFILING
5 select SIBYTE_SB1xxx_SOC 6 select SIBYTE_SB1xxx_SOC
6 select SYS_SUPPORTS_SMP 7 select SYS_SUPPORTS_SMP
7 8
@@ -34,6 +35,7 @@ config SIBYTE_BCM112X
34config SIBYTE_BCM1x80 35config SIBYTE_BCM1x80
35 bool 36 bool
36 select HW_HAS_PCI 37 select HW_HAS_PCI
38 select SIBYTE_HAS_ZBUS_PROFILING
37 select SIBYTE_SB1xxx_SOC 39 select SIBYTE_SB1xxx_SOC
38 select SYS_SUPPORTS_SMP 40 select SYS_SUPPORTS_SMP
39 41
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile
new file mode 100644
index 000000000000..8a06a4fb5212
--- /dev/null
+++ b/arch/mips/sibyte/common/Makefile
@@ -0,0 +1,5 @@
1obj-y :=
2
3obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o
4
5EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c
index ea0ca131a3cf..4fcdaa8ba514 100644
--- a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
+++ b/arch/mips/sibyte/common/sb_tbprof.c
@@ -31,14 +31,29 @@
31#include <linux/vmalloc.h> 31#include <linux/vmalloc.h>
32#include <linux/fs.h> 32#include <linux/fs.h>
33#include <linux/errno.h> 33#include <linux/errno.h>
34#include <linux/types.h>
35#include <linux/wait.h> 34#include <linux/wait.h>
36
37#include <asm/io.h> 35#include <asm/io.h>
38#include <asm/sibyte/sb1250.h> 36#include <asm/sibyte/sb1250.h>
37
38#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
39#include <asm/sibyte/bcm1480_regs.h>
40#include <asm/sibyte/bcm1480_scd.h>
41#include <asm/sibyte/bcm1480_int.h>
42#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
39#include <asm/sibyte/sb1250_regs.h> 43#include <asm/sibyte/sb1250_regs.h>
40#include <asm/sibyte/sb1250_scd.h> 44#include <asm/sibyte/sb1250_scd.h>
41#include <asm/sibyte/sb1250_int.h> 45#include <asm/sibyte/sb1250_int.h>
46#else
47#error invalid SiByte UART configuation
48#endif
49
50#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
51#undef K_INT_TRACE_FREEZE
52#define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE
53#undef K_INT_PERF_CNT
54#define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT
55#endif
56
42#include <asm/system.h> 57#include <asm/system.h>
43#include <asm/uaccess.h> 58#include <asm/uaccess.h>
44 59
@@ -118,7 +133,7 @@ static struct sbprof_tb sbp;
118 : /* inputs */ \ 133 : /* inputs */ \
119 : /* modifies */ "$8" ) 134 : /* modifies */ "$8" )
120 135
121#define DEVNAME "bcm1250_tbprof" 136#define DEVNAME "sb_tbprof"
122 137
123#define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES) 138#define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
124 139
@@ -132,6 +147,7 @@ static struct sbprof_tb sbp;
132 * overflow. 147 * overflow.
133 * 148 *
134 * We map the interrupt for trace_buffer_freeze to handle it on CPU 0. 149 * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
150 *
135 */ 151 */
136 152
137static u64 tb_period; 153static u64 tb_period;
@@ -143,25 +159,36 @@ static void arm_tb(void)
143 u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL; 159 u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
144 160
145 /* 161 /*
146 * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to trigger 162 * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
147 *start of trace. XXX vary sampling period 163 * trigger start of trace. XXX vary sampling period
148 */ 164 */
149 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1)); 165 __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
150 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG)); 166 scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
151 167
152 /* 168 /*
153 * Unfortunately, in Pass 2 we must clear all counters to knock down a 169 * Unfortunately, in Pass 2 we must clear all counters to knock down
154 * previous interrupt request. This means that bus profiling requires 170 * a previous interrupt request. This means that bus profiling
155 * ALL of the SCD perf counters. 171 * requires ALL of the SCD perf counters.
156 */ 172 */
173#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
174 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
175 /* keep counters 0,2,3,4,5,6,7 as is */
176 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
177 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0));
178 __raw_writeq(
179 M_SPC_CFG_ENABLE | /* enable counting */
180 M_SPC_CFG_CLEAR | /* clear all counters */
181 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
182 IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1));
183#else
157 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | 184 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
158 /* keep counters 0,2,3 as is */ 185 /* keep counters 0,2,3 as is */
159 M_SPC_CFG_ENABLE | /* enable counting */ 186 M_SPC_CFG_ENABLE | /* enable counting */
160 M_SPC_CFG_CLEAR | /* clear all counters */ 187 M_SPC_CFG_CLEAR | /* clear all counters */
161 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */ 188 V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */
162 IOADDR(A_SCD_PERF_CNT_CFG)); 189 IOADDR(A_SCD_PERF_CNT_CFG));
190#endif
163 __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1)); 191 __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
164
165 /* Reset the trace buffer */ 192 /* Reset the trace buffer */
166 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); 193 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
167#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT) 194#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
@@ -190,38 +217,37 @@ static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
190 /* Subscripts decrease to put bundle in the order */ 217 /* Subscripts decrease to put bundle in the order */
191 /* t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */ 218 /* t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
192 p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 219 p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
193 /* read t2 hi */ 220 /* read t2 hi */
194 p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 221 p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
195 /* read t2 lo */ 222 /* read t2 lo */
196 p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 223 p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
197 /* read t1 hi */ 224 /* read t1 hi */
198 p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 225 p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
199 /* read t1 lo */ 226 /* read t1 lo */
200 p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 227 p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
201 /* read t0 hi */ 228 /* read t0 hi */
202 p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ)); 229 p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
203 /* read t0 lo */ 230 /* read t0 lo */
204 } 231 }
205 if (!sbp.tb_enable) { 232 if (!sbp.tb_enable) {
206 pr_debug(DEVNAME ": tb_intr shutdown\n"); 233 pr_debug(DEVNAME ": tb_intr shutdown\n");
207 __raw_writeq(M_SCD_TRACE_CFG_RESET, 234 __raw_writeq(M_SCD_TRACE_CFG_RESET,
208 IOADDR(A_SCD_TRACE_CFG)); 235 IOADDR(A_SCD_TRACE_CFG));
209 sbp.tb_armed = 0; 236 sbp.tb_armed = 0;
210 wake_up(&sbp.tb_sync); 237 wake_up_interruptible(&sbp.tb_sync);
211 } else { 238 } else {
212 arm_tb(); /* knock down current interrupt and get another one later */ 239 /* knock down current interrupt and get another one later */
240 arm_tb();
213 } 241 }
214 } else { 242 } else {
215 /* No more trace buffer samples */ 243 /* No more trace buffer samples */
216 pr_debug(DEVNAME ": tb_intr full\n"); 244 pr_debug(DEVNAME ": tb_intr full\n");
217 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); 245 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
218 sbp.tb_armed = 0; 246 sbp.tb_armed = 0;
219 if (!sbp.tb_enable) { 247 if (!sbp.tb_enable)
220 wake_up(&sbp.tb_sync); 248 wake_up_interruptible(&sbp.tb_sync);
221 } 249 wake_up_interruptible(&sbp.tb_read);
222 wake_up(&sbp.tb_read);
223 } 250 }
224
225 return IRQ_HANDLED; 251 return IRQ_HANDLED;
226} 252}
227 253
@@ -250,8 +276,8 @@ static int sbprof_zbprof_start(struct file *filp)
250 sbp.next_tb_sample = 0; 276 sbp.next_tb_sample = 0;
251 filp->f_pos = 0; 277 filp->f_pos = 0;
252 278
253 err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, 279 err = request_irq (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
254 DEVNAME " trace freeze", &sbp); 280 DEVNAME " trace freeze", &sbp);
255 if (err) 281 if (err)
256 return -EBUSY; 282 return -EBUSY;
257 283
@@ -263,23 +289,29 @@ static int sbprof_zbprof_start(struct file *filp)
263 IOADDR(A_SCD_PERF_CNT_CFG)); 289 IOADDR(A_SCD_PERF_CNT_CFG));
264 290
265 /* 291 /*
266 * We grab this interrupt to prevent others from trying to use it, even 292 * We grab this interrupt to prevent others from trying to use
267 * though we don't want to service the interrupts (they only feed into 293 * it, even though we don't want to service the interrupts
268 * the trace-on-interrupt mechanism) 294 * (they only feed into the trace-on-interrupt mechanism)
269 */ 295 */
270 err = request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, 296 if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
271 DEVNAME " scd perfcnt", &sbp); 297 free_irq(K_INT_TRACE_FREEZE, &sbp);
272 if (err) 298 return -EBUSY;
273 goto out_free_irq; 299 }
274 300
275 /* 301 /*
276 * I need the core to mask these, but the interrupt mapper to pass them 302 * I need the core to mask these, but the interrupt mapper to
277 * through. I am exploiting my knowledge that cp0_status masks out 303 * pass them through. I am exploiting my knowledge that
278 * IP[5]. krw 304 * cp0_status masks out IP[5]. krw
279 */ 305 */
306#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
307 __raw_writeq(K_BCM1480_INT_MAP_I3,
308 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) +
309 ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3)));
310#else
280 __raw_writeq(K_INT_MAP_I3, 311 __raw_writeq(K_INT_MAP_I3,
281 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 312 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
282 (K_INT_PERF_CNT << 3))); 313 (K_INT_PERF_CNT << 3)));
314#endif
283 315
284 /* Initialize address traps */ 316 /* Initialize address traps */
285 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0)); 317 __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
@@ -298,7 +330,7 @@ static int sbprof_zbprof_start(struct file *filp)
298 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3)); 330 __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
299 331
300 /* Initialize Trace Event 0-7 */ 332 /* Initialize Trace Event 0-7 */
301 /* when interrupt */ 333 /* when interrupt */
302 __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0)); 334 __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
303 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1)); 335 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
304 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2)); 336 __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
@@ -324,24 +356,23 @@ static int sbprof_zbprof_start(struct file *filp)
324 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); 356 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
325 357
326 /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ 358 /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
359#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
360 __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f),
361 IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L)));
362#else
327 __raw_writeq(1ULL << K_INT_PERF_CNT, 363 __raw_writeq(1ULL << K_INT_PERF_CNT,
328 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE))); 364 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
329 365#endif
330 arm_tb(); 366 arm_tb();
331 367
332 pr_debug(DEVNAME ": done starting\n"); 368 pr_debug(DEVNAME ": done starting\n");
333 369
334 return 0; 370 return 0;
335
336out_free_irq:
337 free_irq(K_INT_TRACE_FREEZE, &sbp);
338
339 return err;
340} 371}
341 372
342static int sbprof_zbprof_stop(void) 373static int sbprof_zbprof_stop(void)
343{ 374{
344 int err; 375 int err = 0;
345 376
346 pr_debug(DEVNAME ": stopping\n"); 377 pr_debug(DEVNAME ": stopping\n");
347 378
@@ -365,7 +396,7 @@ static int sbprof_zbprof_stop(void)
365 396
366 pr_debug(DEVNAME ": done stopping\n"); 397 pr_debug(DEVNAME ": done stopping\n");
367 398
368 return 0; 399 return err;
369} 400}
370 401
371static int sbprof_tb_open(struct inode *inode, struct file *filp) 402static int sbprof_tb_open(struct inode *inode, struct file *filp)
@@ -380,11 +411,9 @@ static int sbprof_tb_open(struct inode *inode, struct file *filp)
380 return -EBUSY; 411 return -EBUSY;
381 412
382 memset(&sbp, 0, sizeof(struct sbprof_tb)); 413 memset(&sbp, 0, sizeof(struct sbprof_tb));
383
384 sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES); 414 sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
385 if (!sbp.sbprof_tbbuf) 415 if (!sbp.sbprof_tbbuf)
386 return -ENOMEM; 416 return -ENOMEM;
387
388 memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES); 417 memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
389 init_waitqueue_head(&sbp.tb_sync); 418 init_waitqueue_head(&sbp.tb_sync);
390 init_waitqueue_head(&sbp.tb_read); 419 init_waitqueue_head(&sbp.tb_read);
@@ -397,8 +426,9 @@ static int sbprof_tb_open(struct inode *inode, struct file *filp)
397 426
398static int sbprof_tb_release(struct inode *inode, struct file *filp) 427static int sbprof_tb_release(struct inode *inode, struct file *filp)
399{ 428{
400 int minor = iminor(inode); 429 int minor;
401 430
431 minor = iminor(inode);
402 if (minor != 0 || !sbp.open) 432 if (minor != 0 || !sbp.open)
403 return -ENODEV; 433 return -ENODEV;
404 434
@@ -419,10 +449,10 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
419 size_t size, loff_t *offp) 449 size_t size, loff_t *offp)
420{ 450{
421 int cur_sample, sample_off, cur_count, sample_left; 451 int cur_sample, sample_off, cur_count, sample_left;
422 long cur_off = *offp;
423 char *dest = buf;
424 int count = 0;
425 char *src; 452 char *src;
453 int count = 0;
454 char *dest = buf;
455 long cur_off = *offp;
426 456
427 if (!access_ok(VERIFY_WRITE, buf, size)) 457 if (!access_ok(VERIFY_WRITE, buf, size))
428 return -EFAULT; 458 return -EFAULT;
@@ -445,7 +475,6 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
445 mutex_unlock(&sbp.lock); 475 mutex_unlock(&sbp.lock);
446 return err; 476 return err;
447 } 477 }
448
449 pr_debug(DEVNAME ": read from sample %d, %d bytes\n", 478 pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
450 cur_sample, cur_count); 479 cur_sample, cur_count);
451 size -= cur_count; 480 size -= cur_count;
@@ -461,45 +490,46 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
461 dest += cur_count; 490 dest += cur_count;
462 count += cur_count; 491 count += cur_count;
463 } 492 }
464
465 *offp = cur_off; 493 *offp = cur_off;
466 mutex_unlock(&sbp.lock); 494 mutex_unlock(&sbp.lock);
467 495
468 return count; 496 return count;
469} 497}
470 498
471static long sbprof_tb_ioctl(struct file *filp, unsigned int command, 499static long sbprof_tb_ioctl(struct file *filp,
472 unsigned long arg) 500 unsigned int command,
501 unsigned long arg)
473{ 502{
474 int error = 0; 503 int err = 0;
475 504
476 switch (command) { 505 switch (command) {
477 case SBPROF_ZBSTART: 506 case SBPROF_ZBSTART:
478 mutex_lock(&sbp.lock); 507 mutex_lock(&sbp.lock);
479 error = sbprof_zbprof_start(filp); 508 err = sbprof_zbprof_start(filp);
480 mutex_unlock(&sbp.lock); 509 mutex_unlock(&sbp.lock);
481 break; 510 break;
482 511
483 case SBPROF_ZBSTOP: 512 case SBPROF_ZBSTOP:
484 mutex_lock(&sbp.lock); 513 mutex_lock(&sbp.lock);
485 error = sbprof_zbprof_stop(); 514 err = sbprof_zbprof_stop();
486 mutex_unlock(&sbp.lock); 515 mutex_unlock(&sbp.lock);
487 break; 516 break;
488 517
489 case SBPROF_ZBWAITFULL: 518 case SBPROF_ZBWAITFULL: {
490 error = wait_event_interruptible(sbp.tb_read, TB_FULL); 519 err = wait_event_interruptible(sbp.tb_read, TB_FULL);
491 if (error) 520 if (err)
492 break; 521 break;
493 522
494 error = put_user(TB_FULL, (int *) arg); 523 err = put_user(TB_FULL, (int *) arg);
495 break; 524 break;
525 }
496 526
497 default: 527 default:
498 error = -EINVAL; 528 err = -EINVAL;
499 break; 529 break;
500 } 530 }
501 531
502 return error; 532 return err;
503} 533}
504 534
505static const struct file_operations sbprof_tb_fops = { 535static const struct file_operations sbprof_tb_fops = {
@@ -544,8 +574,8 @@ static int __init sbprof_tb_init(void)
544 574
545 sbp.open = 0; 575 sbp.open = 0;
546 tb_period = zbbus_mhz * 10000LL; 576 tb_period = zbbus_mhz * 10000LL;
547 pr_info(DEVNAME ": initialized - tb_period = %lld\n", tb_period); 577 pr_info(DEVNAME ": initialized - tb_period = %lld\n",
548 578 (long long) tb_period);
549 return 0; 579 return 0;
550 580
551out_class: 581out_class:
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
index 04c0f1a7f616..df662c61473a 100644
--- a/arch/mips/sibyte/sb1250/Makefile
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -1,6 +1,5 @@
1obj-y := setup.o irq.o time.o 1obj-y := setup.o irq.o time.o
2 2
3obj-$(CONFIG_SMP) += smp.o 3obj-$(CONFIG_SMP) += smp.o
4obj-$(CONFIG_SIBYTE_TBPROF) += bcm1250_tbprof.o
5obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o 4obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o
6obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o 5obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o