diff options
Diffstat (limited to 'arch/mips')
24 files changed, 55 insertions, 78 deletions
diff --git a/arch/mips/basler/excite/excite_irq.c b/arch/mips/basler/excite/excite_irq.c index 2e2061a286c5..1ecab6350421 100644 --- a/arch/mips/basler/excite/excite_irq.c +++ b/arch/mips/basler/excite/excite_irq.c | |||
@@ -47,9 +47,9 @@ extern asmlinkage void excite_handle_int(void); | |||
47 | */ | 47 | */ |
48 | void __init arch_init_irq(void) | 48 | void __init arch_init_irq(void) |
49 | { | 49 | { |
50 | mips_cpu_irq_init(0); | 50 | mips_cpu_irq_init(); |
51 | rm7k_cpu_irq_init(8); | 51 | rm7k_cpu_irq_init(); |
52 | rm9k_cpu_irq_init(12); | 52 | rm9k_cpu_irq_init(); |
53 | 53 | ||
54 | #ifdef CONFIG_KGDB | 54 | #ifdef CONFIG_KGDB |
55 | excite_kgdb_init(); | 55 | excite_kgdb_init(); |
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c index 4c46f0e73783..fe93b846923b 100644 --- a/arch/mips/cobalt/irq.c +++ b/arch/mips/cobalt/irq.c | |||
@@ -104,7 +104,7 @@ void __init arch_init_irq(void) | |||
104 | GT_WRITE(GT_INTRMASK_OFS, 0); | 104 | GT_WRITE(GT_INTRMASK_OFS, 0); |
105 | 105 | ||
106 | init_i8259_irqs(); /* 0 ... 15 */ | 106 | init_i8259_irqs(); /* 0 ... 15 */ |
107 | mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ | 107 | mips_cpu_irq_init(); /* 16 ... 23 */ |
108 | 108 | ||
109 | /* | 109 | /* |
110 | * Mask all cpu interrupts | 110 | * Mask all cpu interrupts |
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c index a8bd2e66705c..bd7cd7c5f485 100644 --- a/arch/mips/ddb5xxx/ddb5477/irq.c +++ b/arch/mips/ddb5xxx/ddb5477/irq.c | |||
@@ -17,6 +17,7 @@ | |||
17 | #include <linux/ptrace.h> | 17 | #include <linux/ptrace.h> |
18 | 18 | ||
19 | #include <asm/i8259.h> | 19 | #include <asm/i8259.h> |
20 | #include <asm/irq_cpu.h> | ||
20 | #include <asm/system.h> | 21 | #include <asm/system.h> |
21 | #include <asm/mipsregs.h> | 22 | #include <asm/mipsregs.h> |
22 | #include <asm/debug.h> | 23 | #include <asm/debug.h> |
@@ -73,7 +74,6 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) | |||
73 | } | 74 | } |
74 | 75 | ||
75 | extern void vrc5477_irq_init(u32 base); | 76 | extern void vrc5477_irq_init(u32 base); |
76 | extern void mips_cpu_irq_init(u32 base); | ||
77 | static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; | 77 | static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; |
78 | 78 | ||
79 | void __init arch_init_irq(void) | 79 | void __init arch_init_irq(void) |
@@ -125,7 +125,7 @@ void __init arch_init_irq(void) | |||
125 | 125 | ||
126 | /* init all controllers */ | 126 | /* init all controllers */ |
127 | init_i8259_irqs(); | 127 | init_i8259_irqs(); |
128 | mips_cpu_irq_init(CPU_IRQ_BASE); | 128 | mips_cpu_irq_init(); |
129 | vrc5477_irq_init(VRC5477_IRQ_BASE); | 129 | vrc5477_irq_init(VRC5477_IRQ_BASE); |
130 | 130 | ||
131 | 131 | ||
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index d34032ac492a..1058e2f409bb 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c | |||
@@ -234,7 +234,7 @@ static void __init dec_init_kn01(void) | |||
234 | memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, | 234 | memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl, |
235 | sizeof(kn01_cpu_mask_nr_tbl)); | 235 | sizeof(kn01_cpu_mask_nr_tbl)); |
236 | 236 | ||
237 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 237 | mips_cpu_irq_init(); |
238 | 238 | ||
239 | } /* dec_init_kn01 */ | 239 | } /* dec_init_kn01 */ |
240 | 240 | ||
@@ -309,7 +309,7 @@ static void __init dec_init_kn230(void) | |||
309 | memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, | 309 | memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl, |
310 | sizeof(kn230_cpu_mask_nr_tbl)); | 310 | sizeof(kn230_cpu_mask_nr_tbl)); |
311 | 311 | ||
312 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 312 | mips_cpu_irq_init(); |
313 | 313 | ||
314 | } /* dec_init_kn230 */ | 314 | } /* dec_init_kn230 */ |
315 | 315 | ||
@@ -403,7 +403,7 @@ static void __init dec_init_kn02(void) | |||
403 | memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, | 403 | memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl, |
404 | sizeof(kn02_asic_mask_nr_tbl)); | 404 | sizeof(kn02_asic_mask_nr_tbl)); |
405 | 405 | ||
406 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 406 | mips_cpu_irq_init(); |
407 | init_kn02_irqs(KN02_IRQ_BASE); | 407 | init_kn02_irqs(KN02_IRQ_BASE); |
408 | 408 | ||
409 | } /* dec_init_kn02 */ | 409 | } /* dec_init_kn02 */ |
@@ -504,7 +504,7 @@ static void __init dec_init_kn02ba(void) | |||
504 | memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, | 504 | memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl, |
505 | sizeof(kn02ba_asic_mask_nr_tbl)); | 505 | sizeof(kn02ba_asic_mask_nr_tbl)); |
506 | 506 | ||
507 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 507 | mips_cpu_irq_init(); |
508 | init_ioasic_irqs(IO_IRQ_BASE); | 508 | init_ioasic_irqs(IO_IRQ_BASE); |
509 | 509 | ||
510 | } /* dec_init_kn02ba */ | 510 | } /* dec_init_kn02ba */ |
@@ -601,7 +601,7 @@ static void __init dec_init_kn02ca(void) | |||
601 | memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, | 601 | memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl, |
602 | sizeof(kn02ca_asic_mask_nr_tbl)); | 602 | sizeof(kn02ca_asic_mask_nr_tbl)); |
603 | 603 | ||
604 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 604 | mips_cpu_irq_init(); |
605 | init_ioasic_irqs(IO_IRQ_BASE); | 605 | init_ioasic_irqs(IO_IRQ_BASE); |
606 | 606 | ||
607 | } /* dec_init_kn02ca */ | 607 | } /* dec_init_kn02ca */ |
@@ -702,7 +702,7 @@ static void __init dec_init_kn03(void) | |||
702 | memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, | 702 | memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl, |
703 | sizeof(kn03_asic_mask_nr_tbl)); | 703 | sizeof(kn03_asic_mask_nr_tbl)); |
704 | 704 | ||
705 | mips_cpu_irq_init(DEC_CPU_IRQ_BASE); | 705 | mips_cpu_irq_init(); |
706 | init_ioasic_irqs(IO_IRQ_BASE); | 706 | init_ioasic_irqs(IO_IRQ_BASE); |
707 | 707 | ||
708 | } /* dec_init_kn03 */ | 708 | } /* dec_init_kn03 */ |
diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c index c93369cb4115..3299b6dfe764 100644 --- a/arch/mips/emma2rh/markeins/irq.c +++ b/arch/mips/emma2rh/markeins/irq.c | |||
@@ -106,7 +106,7 @@ void __init arch_init_irq(void) | |||
106 | emma2rh_irq_init(EMMA2RH_IRQ_BASE); | 106 | emma2rh_irq_init(EMMA2RH_IRQ_BASE); |
107 | emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE); | 107 | emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE); |
108 | emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE); | 108 | emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE); |
109 | mips_cpu_irq_init(CPU_IRQ_BASE); | 109 | mips_cpu_irq_init(); |
110 | 110 | ||
111 | /* setup cascade interrupts */ | 111 | /* setup cascade interrupts */ |
112 | setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade); | 112 | setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade); |
diff --git a/arch/mips/gt64120/momenco_ocelot/irq.c b/arch/mips/gt64120/momenco_ocelot/irq.c index d9294401ccb0..2585d9dbda33 100644 --- a/arch/mips/gt64120/momenco_ocelot/irq.c +++ b/arch/mips/gt64120/momenco_ocelot/irq.c | |||
@@ -90,6 +90,6 @@ void __init arch_init_irq(void) | |||
90 | clear_c0_status(ST0_IM); | 90 | clear_c0_status(ST0_IM); |
91 | local_irq_disable(); | 91 | local_irq_disable(); |
92 | 92 | ||
93 | mips_cpu_irq_init(0); | 93 | mips_cpu_irq_init(); |
94 | rm7k_cpu_irq_init(8); | 94 | rm7k_cpu_irq_init(); |
95 | } | 95 | } |
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c index eedfc24e1eae..d3d96591780e 100644 --- a/arch/mips/gt64120/wrppmc/irq.c +++ b/arch/mips/gt64120/wrppmc/irq.c | |||
@@ -63,7 +63,7 @@ void gt64120_init_pic(void) | |||
63 | void __init arch_init_irq(void) | 63 | void __init arch_init_irq(void) |
64 | { | 64 | { |
65 | /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ | 65 | /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ |
66 | mips_cpu_irq_init(0); | 66 | mips_cpu_irq_init(); |
67 | 67 | ||
68 | gt64120_init_pic(); | 68 | gt64120_init_pic(); |
69 | } | 69 | } |
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index 123324ba8c14..a60cfe5f4d18 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c | |||
@@ -17,16 +17,14 @@ | |||
17 | #include <asm/mipsregs.h> | 17 | #include <asm/mipsregs.h> |
18 | #include <asm/system.h> | 18 | #include <asm/system.h> |
19 | 19 | ||
20 | static int irq_base; | ||
21 | |||
22 | static inline void unmask_rm7k_irq(unsigned int irq) | 20 | static inline void unmask_rm7k_irq(unsigned int irq) |
23 | { | 21 | { |
24 | set_c0_intcontrol(0x100 << (irq - irq_base)); | 22 | set_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE)); |
25 | } | 23 | } |
26 | 24 | ||
27 | static inline void mask_rm7k_irq(unsigned int irq) | 25 | static inline void mask_rm7k_irq(unsigned int irq) |
28 | { | 26 | { |
29 | clear_c0_intcontrol(0x100 << (irq - irq_base)); | 27 | clear_c0_intcontrol(0x100 << (irq - RM7K_CPU_IRQ_BASE)); |
30 | } | 28 | } |
31 | 29 | ||
32 | static struct irq_chip rm7k_irq_controller = { | 30 | static struct irq_chip rm7k_irq_controller = { |
@@ -37,8 +35,9 @@ static struct irq_chip rm7k_irq_controller = { | |||
37 | .unmask = unmask_rm7k_irq, | 35 | .unmask = unmask_rm7k_irq, |
38 | }; | 36 | }; |
39 | 37 | ||
40 | void __init rm7k_cpu_irq_init(int base) | 38 | void __init rm7k_cpu_irq_init(void) |
41 | { | 39 | { |
40 | int base = RM7K_CPU_IRQ_BASE; | ||
42 | int i; | 41 | int i; |
43 | 42 | ||
44 | clear_c0_intcontrol(0x00000f00); /* Mask all */ | 43 | clear_c0_intcontrol(0x00000f00); /* Mask all */ |
@@ -46,6 +45,4 @@ void __init rm7k_cpu_irq_init(int base) | |||
46 | for (i = base; i < base + 4; i++) | 45 | for (i = base; i < base + 4; i++) |
47 | set_irq_chip_and_handler(i, &rm7k_irq_controller, | 46 | set_irq_chip_and_handler(i, &rm7k_irq_controller, |
48 | handle_level_irq); | 47 | handle_level_irq); |
49 | |||
50 | irq_base = base; | ||
51 | } | 48 | } |
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index 2e68e4b639f7..27886db89a65 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c | |||
@@ -18,16 +18,14 @@ | |||
18 | #include <asm/mipsregs.h> | 18 | #include <asm/mipsregs.h> |
19 | #include <asm/system.h> | 19 | #include <asm/system.h> |
20 | 20 | ||
21 | static int irq_base; | ||
22 | |||
23 | static inline void unmask_rm9k_irq(unsigned int irq) | 21 | static inline void unmask_rm9k_irq(unsigned int irq) |
24 | { | 22 | { |
25 | set_c0_intcontrol(0x1000 << (irq - irq_base)); | 23 | set_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE)); |
26 | } | 24 | } |
27 | 25 | ||
28 | static inline void mask_rm9k_irq(unsigned int irq) | 26 | static inline void mask_rm9k_irq(unsigned int irq) |
29 | { | 27 | { |
30 | clear_c0_intcontrol(0x1000 << (irq - irq_base)); | 28 | clear_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE)); |
31 | } | 29 | } |
32 | 30 | ||
33 | static inline void rm9k_cpu_irq_enable(unsigned int irq) | 31 | static inline void rm9k_cpu_irq_enable(unsigned int irq) |
@@ -93,8 +91,9 @@ unsigned int rm9000_perfcount_irq; | |||
93 | 91 | ||
94 | EXPORT_SYMBOL(rm9000_perfcount_irq); | 92 | EXPORT_SYMBOL(rm9000_perfcount_irq); |
95 | 93 | ||
96 | void __init rm9k_cpu_irq_init(int base) | 94 | void __init rm9k_cpu_irq_init(void) |
97 | { | 95 | { |
96 | int base = RM9K_CPU_IRQ_BASE; | ||
98 | int i; | 97 | int i; |
99 | 98 | ||
100 | clear_c0_intcontrol(0x0000f000); /* Mask all */ | 99 | clear_c0_intcontrol(0x0000f000); /* Mask all */ |
@@ -106,6 +105,4 @@ void __init rm9k_cpu_irq_init(int base) | |||
106 | rm9000_perfcount_irq = base + 1; | 105 | rm9000_perfcount_irq = base + 1; |
107 | set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, | 106 | set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, |
108 | handle_level_irq); | 107 | handle_level_irq); |
109 | |||
110 | irq_base = base; | ||
111 | } | 108 | } |
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index fcc86b96ccf6..6e73ddaeae74 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c | |||
@@ -25,7 +25,7 @@ | |||
25 | * Don't even think about using this on SMP. You have been warned. | 25 | * Don't even think about using this on SMP. You have been warned. |
26 | * | 26 | * |
27 | * This file exports one global function: | 27 | * This file exports one global function: |
28 | * void mips_cpu_irq_init(int irq_base); | 28 | * void mips_cpu_irq_init(void); |
29 | */ | 29 | */ |
30 | #include <linux/init.h> | 30 | #include <linux/init.h> |
31 | #include <linux/interrupt.h> | 31 | #include <linux/interrupt.h> |
@@ -36,17 +36,15 @@ | |||
36 | #include <asm/mipsmtregs.h> | 36 | #include <asm/mipsmtregs.h> |
37 | #include <asm/system.h> | 37 | #include <asm/system.h> |
38 | 38 | ||
39 | static int mips_cpu_irq_base; | ||
40 | |||
41 | static inline void unmask_mips_irq(unsigned int irq) | 39 | static inline void unmask_mips_irq(unsigned int irq) |
42 | { | 40 | { |
43 | set_c0_status(0x100 << (irq - mips_cpu_irq_base)); | 41 | set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); |
44 | irq_enable_hazard(); | 42 | irq_enable_hazard(); |
45 | } | 43 | } |
46 | 44 | ||
47 | static inline void mask_mips_irq(unsigned int irq) | 45 | static inline void mask_mips_irq(unsigned int irq) |
48 | { | 46 | { |
49 | clear_c0_status(0x100 << (irq - mips_cpu_irq_base)); | 47 | clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE)); |
50 | irq_disable_hazard(); | 48 | irq_disable_hazard(); |
51 | } | 49 | } |
52 | 50 | ||
@@ -70,7 +68,7 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) | |||
70 | { | 68 | { |
71 | unsigned int vpflags = dvpe(); | 69 | unsigned int vpflags = dvpe(); |
72 | 70 | ||
73 | clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); | 71 | clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); |
74 | evpe(vpflags); | 72 | evpe(vpflags); |
75 | unmask_mips_mt_irq(irq); | 73 | unmask_mips_mt_irq(irq); |
76 | 74 | ||
@@ -84,7 +82,7 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) | |||
84 | static void mips_mt_cpu_irq_ack(unsigned int irq) | 82 | static void mips_mt_cpu_irq_ack(unsigned int irq) |
85 | { | 83 | { |
86 | unsigned int vpflags = dvpe(); | 84 | unsigned int vpflags = dvpe(); |
87 | clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); | 85 | clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE)); |
88 | evpe(vpflags); | 86 | evpe(vpflags); |
89 | mask_mips_mt_irq(irq); | 87 | mask_mips_mt_irq(irq); |
90 | } | 88 | } |
@@ -99,8 +97,9 @@ static struct irq_chip mips_mt_cpu_irq_controller = { | |||
99 | .eoi = unmask_mips_mt_irq, | 97 | .eoi = unmask_mips_mt_irq, |
100 | }; | 98 | }; |
101 | 99 | ||
102 | void __init mips_cpu_irq_init(int irq_base) | 100 | void __init mips_cpu_irq_init(void) |
103 | { | 101 | { |
102 | int irq_base = MIPS_CPU_IRQ_BASE; | ||
104 | int i; | 103 | int i; |
105 | 104 | ||
106 | /* Mask interrupts. */ | 105 | /* Mask interrupts. */ |
@@ -118,6 +117,4 @@ void __init mips_cpu_irq_init(int irq_base) | |||
118 | for (i = irq_base + 2; i < irq_base + 8; i++) | 117 | for (i = irq_base + 2; i < irq_base + 8; i++) |
119 | set_irq_chip_and_handler(i, &mips_cpu_irq_controller, | 118 | set_irq_chip_and_handler(i, &mips_cpu_irq_controller, |
120 | handle_level_irq); | 119 | handle_level_irq); |
121 | |||
122 | mips_cpu_irq_base = irq_base; | ||
123 | } | 120 | } |
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c index 5a99e3e0c96d..8610f4a925e9 100644 --- a/arch/mips/kernel/rtlx.c +++ b/arch/mips/kernel/rtlx.c | |||
@@ -63,7 +63,7 @@ extern void *vpe_get_shared(int index); | |||
63 | 63 | ||
64 | static void rtlx_dispatch(void) | 64 | static void rtlx_dispatch(void) |
65 | { | 65 | { |
66 | do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ); | 66 | do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); |
67 | } | 67 | } |
68 | 68 | ||
69 | 69 | ||
@@ -491,7 +491,7 @@ static struct irqaction rtlx_irq = { | |||
491 | .name = "RTLX", | 491 | .name = "RTLX", |
492 | }; | 492 | }; |
493 | 493 | ||
494 | static int rtlx_irq_num = MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ; | 494 | static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; |
495 | 495 | ||
496 | static char register_chrdev_failed[] __initdata = | 496 | static char register_chrdev_failed[] __initdata = |
497 | KERN_ERR "rtlx_module_init: unable to register device\n"; | 497 | KERN_ERR "rtlx_module_init: unable to register device\n"; |
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 1ee689c0e0c9..64b62bdfb4f6 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c | |||
@@ -35,7 +35,6 @@ | |||
35 | #include <asm/mipsregs.h> | 35 | #include <asm/mipsregs.h> |
36 | #include <asm/mipsmtregs.h> | 36 | #include <asm/mipsmtregs.h> |
37 | #include <asm/mips_mt.h> | 37 | #include <asm/mips_mt.h> |
38 | #include <asm/mips-boards/maltaint.h> /* This is f*cking wrong */ | ||
39 | 38 | ||
40 | #define MIPS_CPU_IPI_RESCHED_IRQ 0 | 39 | #define MIPS_CPU_IPI_RESCHED_IRQ 0 |
41 | #define MIPS_CPU_IPI_CALL_IRQ 1 | 40 | #define MIPS_CPU_IPI_CALL_IRQ 1 |
@@ -108,12 +107,12 @@ void __init sanitize_tlb_entries(void) | |||
108 | 107 | ||
109 | static void ipi_resched_dispatch(void) | 108 | static void ipi_resched_dispatch(void) |
110 | { | 109 | { |
111 | do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ); | 110 | do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); |
112 | } | 111 | } |
113 | 112 | ||
114 | static void ipi_call_dispatch(void) | 113 | static void ipi_call_dispatch(void) |
115 | { | 114 | { |
116 | do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ); | 115 | do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); |
117 | } | 116 | } |
118 | 117 | ||
119 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) | 118 | static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) |
@@ -270,8 +269,8 @@ void __init plat_prepare_cpus(unsigned int max_cpus) | |||
270 | set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); | 269 | set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); |
271 | } | 270 | } |
272 | 271 | ||
273 | cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ; | 272 | cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; |
274 | cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ; | 273 | cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; |
275 | 274 | ||
276 | setup_irq(cpu_ipi_resched_irq, &irq_resched); | 275 | setup_irq(cpu_ipi_resched_irq, &irq_resched); |
277 | setup_irq(cpu_ipi_call_irq, &irq_call); | 276 | setup_irq(cpu_ipi_call_irq, &irq_call); |
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 6a857bf030b0..6a2763143771 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c | |||
@@ -26,16 +26,6 @@ | |||
26 | * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set. | 26 | * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set. |
27 | */ | 27 | */ |
28 | 28 | ||
29 | /* | ||
30 | * MIPSCPU_INT_BASE is identically defined in both | ||
31 | * asm-mips/mips-boards/maltaint.h and asm-mips/mips-boards/simint.h, | ||
32 | * but as yet there's no properly organized include structure that | ||
33 | * will ensure that the right *int.h file will be included for a | ||
34 | * given platform build. | ||
35 | */ | ||
36 | |||
37 | #define MIPSCPU_INT_BASE 16 | ||
38 | |||
39 | #define MIPS_CPU_IPI_IRQ 1 | 29 | #define MIPS_CPU_IPI_IRQ 1 |
40 | 30 | ||
41 | #define LOCK_MT_PRA() \ | 31 | #define LOCK_MT_PRA() \ |
@@ -921,7 +911,7 @@ void smtc_timer_broadcast(int vpe) | |||
921 | * interrupts. | 911 | * interrupts. |
922 | */ | 912 | */ |
923 | 913 | ||
924 | static int cpu_ipi_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_IRQ; | 914 | static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ; |
925 | 915 | ||
926 | static irqreturn_t ipi_interrupt(int irq, void *dev_idm) | 916 | static irqreturn_t ipi_interrupt(int irq, void *dev_idm) |
927 | { | 917 | { |
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c index 43dba6ce6603..85482a631e8c 100644 --- a/arch/mips/mips-boards/atlas/atlas_int.c +++ b/arch/mips/mips-boards/atlas/atlas_int.c | |||
@@ -238,7 +238,7 @@ void __init arch_init_irq(void) | |||
238 | init_atlas_irqs(ATLAS_INT_BASE); | 238 | init_atlas_irqs(ATLAS_INT_BASE); |
239 | 239 | ||
240 | if (!cpu_has_veic) | 240 | if (!cpu_has_veic) |
241 | mips_cpu_irq_init(MIPSCPU_INT_BASE); | 241 | mips_cpu_irq_init(); |
242 | 242 | ||
243 | switch(mips_revision_corid) { | 243 | switch(mips_revision_corid) { |
244 | case MIPS_REVISION_CORID_CORE_MSC: | 244 | case MIPS_REVISION_CORID_CORE_MSC: |
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index 90ad5bf3e2f1..d9ddb170e595 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c | |||
@@ -310,7 +310,7 @@ void __init arch_init_irq(void) | |||
310 | init_i8259_irqs(); | 310 | init_i8259_irqs(); |
311 | 311 | ||
312 | if (!cpu_has_veic) | 312 | if (!cpu_has_veic) |
313 | mips_cpu_irq_init (MIPSCPU_INT_BASE); | 313 | mips_cpu_irq_init(); |
314 | 314 | ||
315 | switch(mips_revision_corid) { | 315 | switch(mips_revision_corid) { |
316 | case MIPS_REVISION_CORID_CORE_MSC: | 316 | case MIPS_REVISION_CORID_CORE_MSC: |
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c index 874ccb0066b8..c4b9de3a7f27 100644 --- a/arch/mips/mips-boards/sead/sead_int.c +++ b/arch/mips/mips-boards/sead/sead_int.c | |||
@@ -113,5 +113,5 @@ asmlinkage void plat_irq_dispatch(void) | |||
113 | 113 | ||
114 | void __init arch_init_irq(void) | 114 | void __init arch_init_irq(void) |
115 | { | 115 | { |
116 | mips_cpu_irq_init(MIPSCPU_INT_BASE); | 116 | mips_cpu_irq_init(); |
117 | } | 117 | } |
diff --git a/arch/mips/mips-boards/sim/sim_int.c b/arch/mips/mips-boards/sim/sim_int.c index 2ce449dce6f2..15ac0655c1ff 100644 --- a/arch/mips/mips-boards/sim/sim_int.c +++ b/arch/mips/mips-boards/sim/sim_int.c | |||
@@ -21,9 +21,7 @@ | |||
21 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
22 | #include <linux/kernel_stat.h> | 22 | #include <linux/kernel_stat.h> |
23 | #include <asm/mips-boards/simint.h> | 23 | #include <asm/mips-boards/simint.h> |
24 | 24 | #include <asm/irq_cpu.h> | |
25 | |||
26 | extern void mips_cpu_irq_init(int); | ||
27 | 25 | ||
28 | static inline int clz(unsigned long x) | 26 | static inline int clz(unsigned long x) |
29 | { | 27 | { |
@@ -86,5 +84,5 @@ asmlinkage void plat_irq_dispatch(void) | |||
86 | 84 | ||
87 | void __init arch_init_irq(void) | 85 | void __init arch_init_irq(void) |
88 | { | 86 | { |
89 | mips_cpu_irq_init(MIPSCPU_INT_BASE); | 87 | mips_cpu_irq_init(); |
90 | } | 88 | } |
diff --git a/arch/mips/momentum/jaguar_atx/irq.c b/arch/mips/momentum/jaguar_atx/irq.c index 2efb25aa1aed..f2b432585df2 100644 --- a/arch/mips/momentum/jaguar_atx/irq.c +++ b/arch/mips/momentum/jaguar_atx/irq.c | |||
@@ -82,8 +82,8 @@ void __init arch_init_irq(void) | |||
82 | */ | 82 | */ |
83 | clear_c0_status(ST0_IM); | 83 | clear_c0_status(ST0_IM); |
84 | 84 | ||
85 | mips_cpu_irq_init(0); | 85 | mips_cpu_irq_init(); |
86 | rm7k_cpu_irq_init(8); | 86 | rm7k_cpu_irq_init(); |
87 | 87 | ||
88 | /* set up the cascading interrupts */ | 88 | /* set up the cascading interrupts */ |
89 | setup_irq(8, &cascade_mv64340); | 89 | setup_irq(8, &cascade_mv64340); |
diff --git a/arch/mips/momentum/ocelot_3/irq.c b/arch/mips/momentum/ocelot_3/irq.c index cea0e5deb80e..3862d1d1add4 100644 --- a/arch/mips/momentum/ocelot_3/irq.c +++ b/arch/mips/momentum/ocelot_3/irq.c | |||
@@ -65,7 +65,7 @@ void __init arch_init_irq(void) | |||
65 | */ | 65 | */ |
66 | clear_c0_status(ST0_IM | ST0_BEV); | 66 | clear_c0_status(ST0_IM | ST0_BEV); |
67 | 67 | ||
68 | rm7k_cpu_irq_init(8); | 68 | rm7k_cpu_irq_init(); |
69 | 69 | ||
70 | /* set up the cascading interrupts */ | 70 | /* set up the cascading interrupts */ |
71 | setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */ | 71 | setup_irq(8, &cascade_mv64340); /* unmask intControl IM8, IRQ 9 */ |
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c index ea65223a6d2c..40472f7944d7 100644 --- a/arch/mips/momentum/ocelot_c/irq.c +++ b/arch/mips/momentum/ocelot_c/irq.c | |||
@@ -94,7 +94,7 @@ void __init arch_init_irq(void) | |||
94 | */ | 94 | */ |
95 | clear_c0_status(ST0_IM); | 95 | clear_c0_status(ST0_IM); |
96 | 96 | ||
97 | mips_cpu_irq_init(0); | 97 | mips_cpu_irq_init(); |
98 | 98 | ||
99 | /* set up the cascading interrupts */ | 99 | /* set up the cascading interrupts */ |
100 | setup_irq(3, &cascade_fpga); | 100 | setup_irq(3, &cascade_fpga); |
diff --git a/arch/mips/momentum/ocelot_g/irq.c b/arch/mips/momentum/ocelot_g/irq.c index da46524e87cb..273541fe7087 100644 --- a/arch/mips/momentum/ocelot_g/irq.c +++ b/arch/mips/momentum/ocelot_g/irq.c | |||
@@ -94,8 +94,8 @@ void __init arch_init_irq(void) | |||
94 | clear_c0_status(ST0_IM); | 94 | clear_c0_status(ST0_IM); |
95 | local_irq_disable(); | 95 | local_irq_disable(); |
96 | 96 | ||
97 | mips_cpu_irq_init(0); | 97 | mips_cpu_irq_init(); |
98 | rm7k_cpu_irq_init(8); | 98 | rm7k_cpu_irq_init(); |
99 | 99 | ||
100 | gt64240_irq_init(); | 100 | gt64240_irq_init(); |
101 | } | 101 | } |
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c index adb048527e76..428d1f45a287 100644 --- a/arch/mips/pmc-sierra/yosemite/irq.c +++ b/arch/mips/pmc-sierra/yosemite/irq.c | |||
@@ -148,9 +148,9 @@ void __init arch_init_irq(void) | |||
148 | { | 148 | { |
149 | clear_c0_status(ST0_IM); | 149 | clear_c0_status(ST0_IM); |
150 | 150 | ||
151 | mips_cpu_irq_init(0); | 151 | mips_cpu_irq_init(); |
152 | rm7k_cpu_irq_init(8); | 152 | rm7k_cpu_irq_init(); |
153 | rm9k_cpu_irq_init(12); | 153 | rm9k_cpu_irq_init(); |
154 | 154 | ||
155 | #ifdef CONFIG_KGDB | 155 | #ifdef CONFIG_KGDB |
156 | /* At this point, initialize the second serial port */ | 156 | /* At this point, initialize the second serial port */ |
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c index c44f8be0644f..f3d2ae374c72 100644 --- a/arch/mips/sgi-ip22/ip22-int.c +++ b/arch/mips/sgi-ip22/ip22-int.c | |||
@@ -19,6 +19,7 @@ | |||
19 | 19 | ||
20 | #include <asm/mipsregs.h> | 20 | #include <asm/mipsregs.h> |
21 | #include <asm/addrspace.h> | 21 | #include <asm/addrspace.h> |
22 | #include <asm/irq_cpu.h> | ||
22 | 23 | ||
23 | #include <asm/sgi/ioc.h> | 24 | #include <asm/sgi/ioc.h> |
24 | #include <asm/sgi/hpc3.h> | 25 | #include <asm/sgi/hpc3.h> |
@@ -253,8 +254,6 @@ asmlinkage void plat_irq_dispatch(void) | |||
253 | indy_8254timer_irq(); | 254 | indy_8254timer_irq(); |
254 | } | 255 | } |
255 | 256 | ||
256 | extern void mips_cpu_irq_init(unsigned int irq_base); | ||
257 | |||
258 | void __init arch_init_irq(void) | 257 | void __init arch_init_irq(void) |
259 | { | 258 | { |
260 | int i; | 259 | int i; |
@@ -316,7 +315,7 @@ void __init arch_init_irq(void) | |||
316 | sgint->cmeimask1 = 0; | 315 | sgint->cmeimask1 = 0; |
317 | 316 | ||
318 | /* init CPU irqs */ | 317 | /* init CPU irqs */ |
319 | mips_cpu_irq_init(SGINT_CPU); | 318 | mips_cpu_irq_init(); |
320 | 319 | ||
321 | for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) { | 320 | for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) { |
322 | struct irq_chip *handler; | 321 | struct irq_chip *handler; |
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c index 16decf4ac2f4..697fcc260141 100644 --- a/arch/mips/vr41xx/common/irq.c +++ b/arch/mips/vr41xx/common/irq.c | |||
@@ -117,5 +117,5 @@ asmlinkage void plat_irq_dispatch(void) | |||
117 | 117 | ||
118 | void __init arch_init_irq(void) | 118 | void __init arch_init_irq(void) |
119 | { | 119 | { |
120 | mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); | 120 | mips_cpu_irq_init(); |
121 | } | 121 | } |