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-rw-r--r--arch/mips/txx9/generic/Makefile2
-rw-r--r--arch/mips/txx9/generic/mem_tx4927.c94
-rw-r--r--arch/mips/txx9/generic/mem_tx4938.c124
-rw-r--r--arch/mips/txx9/rbtx4927/prom.c6
-rw-r--r--arch/mips/txx9/rbtx4938/prom.c6
-rw-r--r--arch/mips/txx9/rbtx4938/setup.c11
6 files changed, 24 insertions, 219 deletions
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 668fdaad6448..ab274ede9a70 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -5,7 +5,7 @@
5obj-y += setup.o 5obj-y += setup.o
6obj-$(CONFIG_PCI) += pci.o 6obj-$(CONFIG_PCI) += pci.o
7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o 7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o
8obj-$(CONFIG_SOC_TX4938) += mem_tx4938.o irq_tx4938.o 8obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o irq_tx4938.o
9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
10obj-$(CONFIG_KGDB) += dbgio.o 10obj-$(CONFIG_KGDB) += dbgio.o
11 11
diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c
index 12dfc377bf2f..ef6ea6e97873 100644
--- a/arch/mips/txx9/generic/mem_tx4927.c
+++ b/arch/mips/txx9/generic/mem_tx4927.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/mips/tx4927/common/tx4927_prom.c 2 * linux/arch/mips/txx9/generic/mem_tx4927.c
3 * 3 *
4 * common tx4927 memory interface 4 * common tx4927 memory interface
5 * 5 *
@@ -32,8 +32,9 @@
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/types.h> 33#include <linux/types.h>
34#include <linux/io.h> 34#include <linux/io.h>
35#include <asm/txx9/tx4927.h>
35 36
36static unsigned int __init tx4927_process_sdccr(unsigned long addr) 37static unsigned int __init tx4927_process_sdccr(u64 __iomem *addr)
37{ 38{
38 u64 val; 39 u64 val;
39 unsigned int sdccr_ce; 40 unsigned int sdccr_ce;
@@ -45,97 +46,32 @@ static unsigned int __init tx4927_process_sdccr(unsigned long addr)
45 unsigned int rs = 0; 46 unsigned int rs = 0;
46 unsigned int cs = 0; 47 unsigned int cs = 0;
47 unsigned int mw = 0; 48 unsigned int mw = 0;
48 unsigned int msize = 0;
49 49
50 val = __raw_readq((void __iomem *)addr); 50 val = __raw_readq(addr);
51 51
52 /* MVMCP -- need #defs for these bits masks */ 52 /* MVMCP -- need #defs for these bits masks */
53 sdccr_ce = ((val & (1 << 10)) >> 10); 53 sdccr_ce = ((val & (1 << 10)) >> 10);
54 sdccr_bs = ((val & (1 << 8)) >> 8); 54 sdccr_bs = ((val & (1 << 8)) >> 8);
55 sdccr_rs = ((val & (3 << 5)) >> 5); 55 sdccr_rs = ((val & (3 << 5)) >> 5);
56 sdccr_cs = ((val & (3 << 2)) >> 2); 56 sdccr_cs = ((val & (7 << 2)) >> 2);
57 sdccr_mw = ((val & (1 << 0)) >> 0); 57 sdccr_mw = ((val & (1 << 0)) >> 0);
58 58
59 if (sdccr_ce) { 59 if (sdccr_ce) {
60 switch (sdccr_bs) { 60 bs = 2 << sdccr_bs;
61 case 0:{ 61 rs = 2048 << sdccr_rs;
62 bs = 2; 62 cs = 256 << sdccr_cs;
63 break; 63 mw = 8 >> sdccr_mw;
64 }
65 case 1:{
66 bs = 4;
67 break;
68 }
69 }
70 switch (sdccr_rs) {
71 case 0:{
72 rs = 2048;
73 break;
74 }
75 case 1:{
76 rs = 4096;
77 break;
78 }
79 case 2:{
80 rs = 8192;
81 break;
82 }
83 case 3:{
84 rs = 0;
85 break;
86 }
87 }
88 switch (sdccr_cs) {
89 case 0:{
90 cs = 256;
91 break;
92 }
93 case 1:{
94 cs = 512;
95 break;
96 }
97 case 2:{
98 cs = 1024;
99 break;
100 }
101 case 3:{
102 cs = 2048;
103 break;
104 }
105 }
106 switch (sdccr_mw) {
107 case 0:{
108 mw = 8;
109 break;
110 } /* 8 bytes = 64 bits */
111 case 1:{
112 mw = 4;
113 break;
114 } /* 4 bytes = 32 bits */
115 }
116 } 64 }
117 65
118 /* bytes per chip MB per chip num chips */ 66 return rs * cs * mw * bs;
119 msize = (((rs * cs * mw) / (1024 * 1024)) * bs);
120
121 return (msize);
122} 67}
123 68
124
125unsigned int __init tx4927_get_mem_size(void) 69unsigned int __init tx4927_get_mem_size(void)
126{ 70{
127 unsigned int c0; 71 unsigned int total = 0;
128 unsigned int c1; 72 int i;
129 unsigned int c2;
130 unsigned int c3;
131 unsigned int total;
132
133 /* MVMCP -- need #defs for these registers */
134 c0 = tx4927_process_sdccr(0xff1f8000);
135 c1 = tx4927_process_sdccr(0xff1f8008);
136 c2 = tx4927_process_sdccr(0xff1f8010);
137 c3 = tx4927_process_sdccr(0xff1f8018);
138 total = c0 + c1 + c2 + c3;
139 73
140 return (total); 74 for (i = 0; i < ARRAY_SIZE(tx4927_sdramcptr->cr); i++)
75 total += tx4927_process_sdccr(&tx4927_sdramcptr->cr[i]);
76 return total;
141} 77}
diff --git a/arch/mips/txx9/generic/mem_tx4938.c b/arch/mips/txx9/generic/mem_tx4938.c
deleted file mode 100644
index 20baeaeba4cd..000000000000
--- a/arch/mips/txx9/generic/mem_tx4938.c
+++ /dev/null
@@ -1,124 +0,0 @@
1/*
2 * linux/arch/mips/tx4938/common/prom.c
3 *
4 * common tx4938 memory interface
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14
15#include <linux/init.h>
16#include <linux/types.h>
17#include <linux/io.h>
18
19static unsigned int __init
20tx4938_process_sdccr(u64 * addr)
21{
22 u64 val;
23 unsigned int sdccr_ce;
24 unsigned int sdccr_rs;
25 unsigned int sdccr_cs;
26 unsigned int sdccr_mw;
27 unsigned int rs = 0;
28 unsigned int cs = 0;
29 unsigned int mw = 0;
30 unsigned int bc = 4;
31 unsigned int msize = 0;
32
33 val = ____raw_readq((void __iomem *)addr);
34
35 /* MVMCP -- need #defs for these bits masks */
36 sdccr_ce = ((val & (1 << 10)) >> 10);
37 sdccr_rs = ((val & (3 << 5)) >> 5);
38 sdccr_cs = ((val & (7 << 2)) >> 2);
39 sdccr_mw = ((val & (1 << 0)) >> 0);
40
41 if (sdccr_ce) {
42 switch (sdccr_rs) {
43 case 0:{
44 rs = 2048;
45 break;
46 }
47 case 1:{
48 rs = 4096;
49 break;
50 }
51 case 2:{
52 rs = 8192;
53 break;
54 }
55 default:{
56 rs = 0;
57 break;
58 }
59 }
60 switch (sdccr_cs) {
61 case 0:{
62 cs = 256;
63 break;
64 }
65 case 1:{
66 cs = 512;
67 break;
68 }
69 case 2:{
70 cs = 1024;
71 break;
72 }
73 case 3:{
74 cs = 2048;
75 break;
76 }
77 case 4:{
78 cs = 4096;
79 break;
80 }
81 default:{
82 cs = 0;
83 break;
84 }
85 }
86 switch (sdccr_mw) {
87 case 0:{
88 mw = 8;
89 break;
90 } /* 8 bytes = 64 bits */
91 case 1:{
92 mw = 4;
93 break;
94 } /* 4 bytes = 32 bits */
95 }
96 }
97
98 /* bytes per chip MB per chip bank count */
99 msize = (((rs * cs * mw) / (1024 * 1024)) * (bc));
100
101 /* MVMCP -- bc hard coded to 4 from table 9.3.1 */
102 /* boad supports bc=2 but no way to detect */
103
104 return (msize);
105}
106
107unsigned int __init
108tx4938_get_mem_size(void)
109{
110 unsigned int c0;
111 unsigned int c1;
112 unsigned int c2;
113 unsigned int c3;
114 unsigned int total;
115
116 /* MVMCP -- need #defs for these registers */
117 c0 = tx4938_process_sdccr((u64 *) 0xff1f8000);
118 c1 = tx4938_process_sdccr((u64 *) 0xff1f8008);
119 c2 = tx4938_process_sdccr((u64 *) 0xff1f8010);
120 c3 = tx4938_process_sdccr((u64 *) 0xff1f8018);
121 total = c0 + c1 + c2 + c3;
122
123 return (total);
124}
diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c
index 942e627d2dc1..5c0de54ebdd2 100644
--- a/arch/mips/txx9/rbtx4927/prom.c
+++ b/arch/mips/txx9/rbtx4927/prom.c
@@ -36,10 +36,6 @@
36 36
37void __init rbtx4927_prom_init(void) 37void __init rbtx4927_prom_init(void)
38{ 38{
39 extern int tx4927_get_mem_size(void);
40 int msize;
41
42 prom_init_cmdline(); 39 prom_init_cmdline();
43 msize = tx4927_get_mem_size(); 40 add_memory_region(0, tx4927_get_mem_size(), BOOT_MEM_RAM);
44 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
45} 41}
diff --git a/arch/mips/txx9/rbtx4938/prom.c b/arch/mips/txx9/rbtx4938/prom.c
index fbb37458ddb2..ee189519ce5a 100644
--- a/arch/mips/txx9/rbtx4938/prom.c
+++ b/arch/mips/txx9/rbtx4938/prom.c
@@ -18,12 +18,8 @@
18 18
19void __init rbtx4938_prom_init(void) 19void __init rbtx4938_prom_init(void)
20{ 20{
21 extern int tx4938_get_mem_size(void);
22 int msize;
23#ifndef CONFIG_TX4938_NAND_BOOT 21#ifndef CONFIG_TX4938_NAND_BOOT
24 prom_init_cmdline(); 22 prom_init_cmdline();
25#endif 23#endif
26 24 add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM);
27 msize = tx4938_get_mem_size();
28 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
29} 25}
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index c2da92396b7a..c1e076c7b2d2 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -310,7 +310,7 @@ void __init tx4938_board_setup(void)
310 310
311 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str); 311 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
312 for (i = 0; i < 4; i++) { 312 for (i = 0; i < 4; i++) {
313 unsigned long long cr = tx4938_sdramcptr->cr[i]; 313 u64 cr = TX4938_SDRAMC_CR(i);
314 unsigned long ram_base, ram_size; 314 unsigned long ram_base, ram_size;
315 if (!((unsigned long)cr & 0x00000400)) 315 if (!((unsigned long)cr & 0x00000400))
316 continue; /* disabled */ 316 continue; /* disabled */
@@ -318,20 +318,21 @@ void __init tx4938_board_setup(void)
318 ram_size = ((unsigned long)(cr >> 33) + 1) << 21; 318 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
319 if (ram_base >= 0x20000000) 319 if (ram_base >= 0x20000000)
320 continue; /* high memory (ignore) */ 320 continue; /* high memory (ignore) */
321 printk(" CR%d:%016Lx", i, cr); 321 printk(KERN_CONT " CR%d:%016llx", i, cr);
322 tx4938_sdram_resource[i].name = "SDRAM"; 322 tx4938_sdram_resource[i].name = "SDRAM";
323 tx4938_sdram_resource[i].start = ram_base; 323 tx4938_sdram_resource[i].start = ram_base;
324 tx4938_sdram_resource[i].end = ram_base + ram_size - 1; 324 tx4938_sdram_resource[i].end = ram_base + ram_size - 1;
325 tx4938_sdram_resource[i].flags = IORESOURCE_MEM; 325 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
326 request_resource(&iomem_resource, &tx4938_sdram_resource[i]); 326 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
327 } 327 }
328 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); 328 printk(KERN_CONT " TR:%09llx\n", ____raw_readq(&tx4938_sdramcptr->tr));
329 329
330 /* SRAM */ 330 /* SRAM */
331 if (tx4938_sramcptr->cr & 1) { 331 if (____raw_readq(&tx4938_sramcptr->cr) & 1) {
332 unsigned int size = 0x800; 332 unsigned int size = 0x800;
333 unsigned long base = 333 unsigned long base =
334 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); 334 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
335 & ~(size - 1);
335 tx4938_sram_resource.name = "SRAM"; 336 tx4938_sram_resource.name = "SRAM";
336 tx4938_sram_resource.start = base; 337 tx4938_sram_resource.start = base;
337 tx4938_sram_resource.end = base + size - 1; 338 tx4938_sram_resource.end = base + size - 1;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 21:13:23 -0500