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-rw-r--r--arch/mips/vr41xx/Kconfig13
-rw-r--r--arch/mips/vr41xx/common/Makefile2
-rw-r--r--arch/mips/vr41xx/common/int-handler.S114
-rw-r--r--arch/mips/vr41xx/common/irq.c29
4 files changed, 39 insertions, 119 deletions
diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig
index a7add16c9aa4..055a2cdfc841 100644
--- a/arch/mips/vr41xx/Kconfig
+++ b/arch/mips/vr41xx/Kconfig
@@ -4,6 +4,8 @@ config CASIO_E55
4 select DMA_NONCOHERENT 4 select DMA_NONCOHERENT
5 select IRQ_CPU 5 select IRQ_CPU
6 select ISA 6 select ISA
7 select SYS_HAS_CPU_VR41XX
8 select SYS_SUPPORTS_32BIT_KERNEL
7 select SYS_SUPPORTS_LITTLE_ENDIAN 9 select SYS_SUPPORTS_LITTLE_ENDIAN
8 10
9config IBM_WORKPAD 11config IBM_WORKPAD
@@ -12,6 +14,8 @@ config IBM_WORKPAD
12 select DMA_NONCOHERENT 14 select DMA_NONCOHERENT
13 select IRQ_CPU 15 select IRQ_CPU
14 select ISA 16 select ISA
17 select SYS_HAS_CPU_VR41XX
18 select SYS_SUPPORTS_32BIT_KERNEL
15 select SYS_SUPPORTS_LITTLE_ENDIAN 19 select SYS_SUPPORTS_LITTLE_ENDIAN
16 20
17config NEC_CMBVR4133 21config NEC_CMBVR4133
@@ -21,6 +25,9 @@ config NEC_CMBVR4133
21 select DMA_NONCOHERENT 25 select DMA_NONCOHERENT
22 select IRQ_CPU 26 select IRQ_CPU
23 select HW_HAS_PCI 27 select HW_HAS_PCI
28 select SYS_HAS_CPU_VR41XX
29 select SYS_SUPPORTS_32BIT_KERNEL
30 select SYS_SUPPORTS_LITTLE_ENDIAN
24 31
25config ROCKHOPPER 32config ROCKHOPPER
26 bool "Support for Rockhopper baseboard" 33 bool "Support for Rockhopper baseboard"
@@ -34,6 +41,8 @@ config TANBAC_TB022X
34 select DMA_NONCOHERENT 41 select DMA_NONCOHERENT
35 select HW_HAS_PCI 42 select HW_HAS_PCI
36 select IRQ_CPU 43 select IRQ_CPU
44 select SYS_HAS_CPU_VR41XX
45 select SYS_SUPPORTS_32BIT_KERNEL
37 select SYS_SUPPORTS_LITTLE_ENDIAN 46 select SYS_SUPPORTS_LITTLE_ENDIAN
38 help 47 help
39 The TANBAC VR4131 multichip module(TB0225) and 48 The TANBAC VR4131 multichip module(TB0225) and
@@ -65,6 +74,8 @@ config VICTOR_MPC30X
65 select DMA_NONCOHERENT 74 select DMA_NONCOHERENT
66 select HW_HAS_PCI 75 select HW_HAS_PCI
67 select IRQ_CPU 76 select IRQ_CPU
77 select SYS_HAS_CPU_VR41XX
78 select SYS_SUPPORTS_32BIT_KERNEL
68 select SYS_SUPPORTS_LITTLE_ENDIAN 79 select SYS_SUPPORTS_LITTLE_ENDIAN
69 80
70config ZAO_CAPCELLA 81config ZAO_CAPCELLA
@@ -73,6 +84,8 @@ config ZAO_CAPCELLA
73 select DMA_NONCOHERENT 84 select DMA_NONCOHERENT
74 select HW_HAS_PCI 85 select HW_HAS_PCI
75 select IRQ_CPU 86 select IRQ_CPU
87 select SYS_HAS_CPU_VR41XX
88 select SYS_SUPPORTS_32BIT_KERNEL
76 select SYS_SUPPORTS_LITTLE_ENDIAN 89 select SYS_SUPPORTS_LITTLE_ENDIAN
77 90
78config PCI_VR41XX 91config PCI_VR41XX
diff --git a/arch/mips/vr41xx/common/Makefile b/arch/mips/vr41xx/common/Makefile
index 9096302a7ecc..aa373974c80f 100644
--- a/arch/mips/vr41xx/common/Makefile
+++ b/arch/mips/vr41xx/common/Makefile
@@ -2,7 +2,7 @@
2# Makefile for common code of the NEC VR4100 series. 2# Makefile for common code of the NEC VR4100 series.
3# 3#
4 4
5obj-y += bcu.o cmu.o icu.o init.o int-handler.o irq.o pmu.o type.o 5obj-y += bcu.o cmu.o icu.o init.o irq.o pmu.o type.o
6obj-$(CONFIG_VRC4173) += vrc4173.o 6obj-$(CONFIG_VRC4173) += vrc4173.o
7 7
8EXTRA_AFLAGS := $(CFLAGS) 8EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/vr41xx/common/int-handler.S b/arch/mips/vr41xx/common/int-handler.S
deleted file mode 100644
index 2b6043f16d09..000000000000
--- a/arch/mips/vr41xx/common/int-handler.S
+++ /dev/null
@@ -1,114 +0,0 @@
1/*
2 * FILE NAME
3 * arch/mips/vr41xx/common/int-handler.S
4 *
5 * BRIEF MODULE DESCRIPTION
6 * Interrupt dispatcher for the NEC VR4100 series.
7 *
8 * Author: Yoichi Yuasa
9 * yyuasa@mvista.com or source@mvista.com
10 *
11 * Copyright 2001 MontaVista Software Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
24 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
26 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
27 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33/*
34 * Changes:
35 * MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
36 * - New creation, NEC VR4100 series are supported.
37 *
38 * Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
39 * - Coped with INTASSIGN of NEC VR4133.
40 */
41#include <asm/asm.h>
42#include <asm/regdef.h>
43#include <asm/mipsregs.h>
44#include <asm/stackframe.h>
45
46 .text
47 .set noreorder
48
49 .align 5
50 NESTED(vr41xx_handle_interrupt, PT_SIZE, ra)
51 .set noat
52 SAVE_ALL
53 CLI
54 .set at
55 .set noreorder
56
57 /*
58 * Get the pending interrupts
59 */
60 mfc0 t0, CP0_CAUSE
61 mfc0 t1, CP0_STATUS
62 andi t0, 0xff00
63 and t0, t0, t1
64
65 andi t1, t0, CAUSEF_IP7 # MIPS timer interrupt
66 bnez t1, handle_irq
67 li a0, 7
68
69 andi t1, t0, 0x7800 # check for Int1-4
70 beqz t1, 1f
71
72 andi t1, t0, CAUSEF_IP3 # check for Int1
73 bnez t1, handle_int
74 li a0, 3
75
76 andi t1, t0, CAUSEF_IP4 # check for Int2
77 bnez t1, handle_int
78 li a0, 4
79
80 andi t1, t0, CAUSEF_IP5 # check for Int3
81 bnez t1, handle_int
82 li a0, 5
83
84 andi t1, t0, CAUSEF_IP6 # check for Int4
85 bnez t1, handle_int
86 li a0, 6
87
881:
89 andi t1, t0, CAUSEF_IP2 # check for Int0
90 bnez t1, handle_int
91 li a0, 2
92
93 andi t1, t0, CAUSEF_IP0 # check for IP0
94 bnez t1, handle_irq
95 li a0, 0
96
97 andi t1, t0, CAUSEF_IP1 # check for IP1
98 bnez t1, handle_irq
99 li a0, 1
100
101 j spurious_interrupt
102 nop
103
104handle_int:
105 jal irq_dispatch
106 move a1, sp
107 j ret_from_irq
108 nop
109
110handle_irq:
111 jal do_IRQ
112 move a1, sp
113 j ret_from_irq
114 END(vr41xx_handle_interrupt)
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index 61aa264275ff..86796bb63c3c 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -59,7 +59,7 @@ int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)
59 59
60EXPORT_SYMBOL_GPL(cascade_irq); 60EXPORT_SYMBOL_GPL(cascade_irq);
61 61
62asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs) 62static void irq_dispatch(unsigned int irq, struct pt_regs *regs)
63{ 63{
64 irq_cascade_t *cascade; 64 irq_cascade_t *cascade;
65 irq_desc_t *desc; 65 irq_desc_t *desc;
@@ -84,11 +84,32 @@ asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs)
84 do_IRQ(irq, regs); 84 do_IRQ(irq, regs);
85} 85}
86 86
87extern asmlinkage void vr41xx_handle_interrupt(void); 87asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
88{
89 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
90
91 if (pending & CAUSEF_IP7)
92 do_IRQ(7, regs);
93 else if (pending & 0x7800) {
94 if (pending & CAUSEF_IP3)
95 irq_dispatch(3, regs);
96 else if (pending & CAUSEF_IP4)
97 irq_dispatch(4, regs);
98 else if (pending & CAUSEF_IP5)
99 irq_dispatch(5, regs);
100 else if (pending & CAUSEF_IP6)
101 irq_dispatch(6, regs);
102 } else if (pending & CAUSEF_IP2)
103 irq_dispatch(2, regs);
104 else if (pending & CAUSEF_IP0)
105 do_IRQ(0, regs);
106 else if (pending & CAUSEF_IP1)
107 do_IRQ(1, regs);
108 else
109 spurious_interrupt(regs);
110}
88 111
89void __init arch_init_irq(void) 112void __init arch_init_irq(void)
90{ 113{
91 mips_cpu_irq_init(MIPS_CPU_IRQ_BASE); 114 mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
92
93 set_except_vector(0, vr41xx_handle_interrupt);
94} 115}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 01:16:34 -0500