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-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/Makefile8
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/init.c65
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/irq.c46
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c249
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/setup.c89
5 files changed, 0 insertions, 457 deletions
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/Makefile b/arch/mips/vr41xx/nec-cmbvr4133/Makefile
deleted file mode 100644
index 5835cae54aca..000000000000
--- a/arch/mips/vr41xx/nec-cmbvr4133/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
1#
2# Makefile for the NEC-CMBVR4133
3#
4
5obj-y := init.o setup.o
6
7obj-$(CONFIG_PCI) += m1535plus.o
8obj-$(CONFIG_ROCKHOPPER) += irq.o
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/init.c b/arch/mips/vr41xx/nec-cmbvr4133/init.c
deleted file mode 100644
index 7c5e18ee2231..000000000000
--- a/arch/mips/vr41xx/nec-cmbvr4133/init.c
+++ /dev/null
@@ -1,65 +0,0 @@
1/*
2 * arch/mips/vr41xx/nec-cmbvr4133/init.c
3 *
4 * PROM library initialisation code for NEC CMB-VR4133 board.
5 *
6 * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
7 * Jun Sun <jsun@mvista.com, or source@mvista.com> and
8 * Alex Sapkov <asapkov@ru.mvista.com>
9 *
10 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 *
15 * Support for NEC-CMBVR4133 in 2.6
16 * Manish Lachwani (mlachwani@mvista.com)
17 */
18
19#ifdef CONFIG_ROCKHOPPER
20#include <asm/io.h>
21#include <linux/pci.h>
22
23#define PCICONFDREG 0xaf000c14
24#define PCICONFAREG 0xaf000c18
25
26void disable_pcnet(void)
27{
28 u32 data;
29
30 /*
31 * Workaround for the bug in PMON on VR4133. PMON leaves
32 * AMD PCNet controller (on Rockhopper) initialized and running in
33 * bus master mode. We have do disable it before doing any
34 * further initialization. Or we get problems with PCI bus 2
35 * and random lockups and crashes.
36 */
37
38 writel((2 << 16) |
39 (PCI_DEVFN(1, 0) << 8) |
40 (0 & 0xfc) |
41 1UL,
42 PCICONFAREG);
43
44 data = readl(PCICONFDREG);
45
46 writel((2 << 16) |
47 (PCI_DEVFN(1, 0) << 8) |
48 (4 & 0xfc) |
49 1UL,
50 PCICONFAREG);
51
52 data = readl(PCICONFDREG);
53
54 writel((2 << 16) |
55 (PCI_DEVFN(1, 0) << 8) |
56 (4 & 0xfc) |
57 1UL,
58 PCICONFAREG);
59
60 data &= ~4;
61
62 writel(data, PCICONFDREG);
63}
64#endif
65
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
deleted file mode 100644
index 7d2d076b0f54..000000000000
--- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * arch/mips/vr41xx/nec-cmbvr4133/irq.c
3 *
4 * Interrupt routines for the NEC CMB-VR4133 board.
5 *
6 * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
7 * Alex Sapkov <asapkov@ru.mvista.com>
8 *
9 * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * Support for NEC-CMBVR4133 in 2.6
15 * Manish Lachwani (mlachwani@mvista.com)
16 */
17#include <linux/bitops.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/ioport.h>
21#include <linux/interrupt.h>
22
23#include <asm/io.h>
24#include <asm/i8259.h>
25#include <asm/vr41xx/cmbvr4133.h>
26
27extern int vr4133_rockhopper;
28
29static int i8259_get_irq_number(int irq)
30{
31 return i8259_irq();
32}
33
34void __init rockhopper_init_irq(void)
35{
36 int i;
37
38 if(!vr4133_rockhopper) {
39 printk(KERN_ERR "Not a Rockhopper Board \n");
40 return;
41 }
42
43 vr41xx_set_irq_trigger(CMBVR41XX_INTC_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH);
44 vr41xx_set_irq_level(CMBVR41XX_INTC_PIN, LEVEL_HIGH);
45 vr41xx_cascade_irq(CMBVR41XX_INTC_IRQ, i8259_get_irq_number);
46}
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
deleted file mode 100644
index 1341f3287d04..000000000000
--- a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
+++ /dev/null
@@ -1,249 +0,0 @@
1/*
2 * arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
3 *
4 * Initialize for ALi M1535+(included M5229 and M5237).
5 *
6 * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
7 * Alex Sapkov <asapkov@ru.mvista.com>
8 *
9 * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * Support for NEC-CMBVR4133 in 2.6
15 * Author: Manish Lachwani (mlachwani@mvista.com)
16 */
17#include <linux/init.h>
18#include <linux/types.h>
19#include <linux/serial.h>
20
21#include <asm/vr41xx/cmbvr4133.h>
22#include <linux/pci.h>
23#include <asm/io.h>
24
25#define CONFIG_PORT(port) ((port) ? 0x3f0 : 0x370)
26#define DATA_PORT(port) ((port) ? 0x3f1 : 0x371)
27#define INDEX_PORT(port) CONFIG_PORT(port)
28
29#define ENTER_CONFIG_MODE(port) \
30 do { \
31 outb_p(0x51, CONFIG_PORT(port)); \
32 outb_p(0x23, CONFIG_PORT(port)); \
33 } while(0)
34
35#define SELECT_LOGICAL_DEVICE(port, dev_no) \
36 do { \
37 outb_p(0x07, INDEX_PORT(port)); \
38 outb_p((dev_no), DATA_PORT(port)); \
39 } while(0)
40
41#define WRITE_CONFIG_DATA(port, index, data) \
42 do { \
43 outb_p((index), INDEX_PORT(port)); \
44 outb_p((data), DATA_PORT(port)); \
45 } while(0)
46
47#define EXIT_CONFIG_MODE(port) outb(0xbb, CONFIG_PORT(port))
48
49#define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18)
50#define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14)
51
52#ifdef CONFIG_BLK_DEV_FD
53
54void __devinit ali_m1535plus_fdc_init(int port)
55{
56 ENTER_CONFIG_MODE(port);
57 SELECT_LOGICAL_DEVICE(port, 0); /* FDC */
58 WRITE_CONFIG_DATA(port, 0x30, 0x01); /* FDC: enable */
59 WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x3f0 */
60 WRITE_CONFIG_DATA(port, 0x61, 0xf0);
61 WRITE_CONFIG_DATA(port, 0x70, 0x06); /* IRQ: 6 */
62 WRITE_CONFIG_DATA(port, 0x74, 0x02); /* DMA: channel 2 */
63 WRITE_CONFIG_DATA(port, 0xf0, 0x08);
64 WRITE_CONFIG_DATA(port, 0xf1, 0x00);
65 WRITE_CONFIG_DATA(port, 0xf2, 0xff);
66 WRITE_CONFIG_DATA(port, 0xf4, 0x00);
67 EXIT_CONFIG_MODE(port);
68}
69
70#endif
71
72void __devinit ali_m1535plus_parport_init(int port)
73{
74 ENTER_CONFIG_MODE(port);
75 SELECT_LOGICAL_DEVICE(port, 3); /* Parallel Port */
76 WRITE_CONFIG_DATA(port, 0x30, 0x01);
77 WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x378 */
78 WRITE_CONFIG_DATA(port, 0x61, 0x78);
79 WRITE_CONFIG_DATA(port, 0x70, 0x07); /* IRQ: 7 */
80 WRITE_CONFIG_DATA(port, 0x74, 0x04); /* DMA: None */
81 WRITE_CONFIG_DATA(port, 0xf0, 0x8c); /* IRQ polarity: Active Low */
82 WRITE_CONFIG_DATA(port, 0xf1, 0xc5);
83 EXIT_CONFIG_MODE(port);
84}
85
86void __devinit ali_m1535plus_keyboard_init(int port)
87{
88 ENTER_CONFIG_MODE(port);
89 SELECT_LOGICAL_DEVICE(port, 7); /* KEYBOARD */
90 WRITE_CONFIG_DATA(port, 0x30, 0x01); /* KEYBOARD: eable */
91 WRITE_CONFIG_DATA(port, 0x70, 0x01); /* IRQ: 1 */
92 WRITE_CONFIG_DATA(port, 0x72, 0x0c); /* PS/2 Mouse IRQ: 12 */
93 WRITE_CONFIG_DATA(port, 0xf0, 0x00);
94 EXIT_CONFIG_MODE(port);
95}
96
97void __devinit ali_m1535plus_hotkey_init(int port)
98{
99 ENTER_CONFIG_MODE(port);
100 SELECT_LOGICAL_DEVICE(port, 0xc); /* HOTKEY */
101 WRITE_CONFIG_DATA(port, 0x30, 0x00);
102 WRITE_CONFIG_DATA(port, 0xf0, 0x35);
103 WRITE_CONFIG_DATA(port, 0xf1, 0x14);
104 WRITE_CONFIG_DATA(port, 0xf2, 0x11);
105 WRITE_CONFIG_DATA(port, 0xf3, 0x71);
106 WRITE_CONFIG_DATA(port, 0xf5, 0x05);
107 EXIT_CONFIG_MODE(port);
108}
109
110void ali_m1535plus_init(struct pci_dev *dev)
111{
112 pci_write_config_byte(dev, 0x40, 0x18); /* PCI Interface Control */
113 pci_write_config_byte(dev, 0x41, 0xc0); /* PS2 keyb & mouse enable */
114 pci_write_config_byte(dev, 0x42, 0x41); /* ISA bus cycle control */
115 pci_write_config_byte(dev, 0x43, 0x00); /* ISA bus cycle control 2 */
116 pci_write_config_byte(dev, 0x44, 0x5d); /* IDE enable & IRQ 14 */
117 pci_write_config_byte(dev, 0x45, 0x0b); /* PCI int polling mode */
118 pci_write_config_byte(dev, 0x47, 0x00); /* BIOS chip select control */
119
120 /* IRQ routing */
121 pci_write_config_byte(dev, 0x48, 0x03); /* INTA IRQ10, INTB disable */
122 pci_write_config_byte(dev, 0x49, 0x00); /* INTC and INTD disable */
123 pci_write_config_byte(dev, 0x4a, 0x00); /* INTE and INTF disable */
124 pci_write_config_byte(dev, 0x4b, 0x90); /* Audio IRQ11, Modem disable */
125
126 pci_write_config_word(dev, 0x50, 0x4000); /* Parity check IDE enable */
127 pci_write_config_word(dev, 0x52, 0x0000); /* USB & RTC disable */
128 pci_write_config_word(dev, 0x54, 0x0002); /* ??? no info */
129 pci_write_config_word(dev, 0x56, 0x0002); /* PCS1J signal disable */
130
131 pci_write_config_byte(dev, 0x59, 0x00); /* PCSDS */
132 pci_write_config_byte(dev, 0x5a, 0x00);
133 pci_write_config_byte(dev, 0x5b, 0x00);
134 pci_write_config_word(dev, 0x5c, 0x0000);
135 pci_write_config_byte(dev, 0x5e, 0x00);
136 pci_write_config_byte(dev, 0x5f, 0x00);
137 pci_write_config_word(dev, 0x60, 0x0000);
138
139 pci_write_config_byte(dev, 0x6c, 0x00);
140 pci_write_config_byte(dev, 0x6d, 0x48); /* ROM address mapping */
141 pci_write_config_byte(dev, 0x6e, 0x00); /* ??? what for? */
142
143 pci_write_config_byte(dev, 0x70, 0x12); /* Serial IRQ control */
144 pci_write_config_byte(dev, 0x71, 0xEF); /* DMA channel select */
145 pci_write_config_byte(dev, 0x72, 0x03); /* USB IDSEL */
146 pci_write_config_byte(dev, 0x73, 0x00); /* ??? no info */
147
148 /*
149 * IRQ setup ALi M5237 USB Host Controller
150 * IRQ: 9
151 */
152 pci_write_config_byte(dev, 0x74, 0x01); /* USB IRQ9 */
153
154 pci_write_config_byte(dev, 0x75, 0x1f); /* IDE2 IRQ 15 */
155 pci_write_config_byte(dev, 0x76, 0x80); /* ACPI disable */
156 pci_write_config_byte(dev, 0x77, 0x40); /* Modem disable */
157 pci_write_config_dword(dev, 0x78, 0x20000000); /* Pin select 2 */
158 pci_write_config_byte(dev, 0x7c, 0x00); /* Pin select 3 */
159 pci_write_config_byte(dev, 0x81, 0x00); /* ID read/write control */
160 pci_write_config_byte(dev, 0x90, 0x00); /* PCI PM block control */
161 pci_write_config_word(dev, 0xa4, 0x0000); /* PMSCR */
162
163#ifdef CONFIG_BLK_DEV_FD
164 ali_m1535plus_fdc_init(1);
165#endif
166
167 ali_m1535plus_keyboard_init(1);
168 ali_m1535plus_hotkey_init(1);
169}
170
171static inline void ali_config_writeb(u8 reg, u8 val, int devfn)
172{
173 u32 data;
174 int shift;
175
176 writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
177 data = readl(PCI_CONFIG_DATA);
178
179 shift = (reg & 3) << 3;
180 data &= ~(0xff << shift);
181 data |= (((u32)val) << shift);
182
183 writel(data, PCI_CONFIG_DATA);
184}
185
186static inline u8 ali_config_readb(u8 reg, int devfn)
187{
188 u32 data;
189
190 writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
191 data = readl(PCI_CONFIG_DATA);
192
193 return (u8)(data >> ((reg & 3) << 3));
194}
195
196static inline u16 ali_config_readw(u8 reg, int devfn)
197{
198 u32 data;
199
200 writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
201 data = readl(PCI_CONFIG_DATA);
202
203 return (u16)(data >> ((reg & 2) << 3));
204}
205
206int vr4133_rockhopper = 0;
207void __init ali_m5229_preinit(void)
208{
209 if (ali_config_readw(PCI_VENDOR_ID, 16) == PCI_VENDOR_ID_AL &&
210 ali_config_readw(PCI_DEVICE_ID, 16) == PCI_DEVICE_ID_AL_M1533) {
211 printk(KERN_INFO "Found an NEC Rockhopper \n");
212 vr4133_rockhopper = 1;
213 /*
214 * Enable ALi M5229 IDE Controller (both channels)
215 * IDSEL: A27
216 */
217 ali_config_writeb(0x58, 0x4c, 16);
218 }
219}
220
221void __init ali_m5229_init(struct pci_dev *dev)
222{
223 /*
224 * Enable Primary/Secondary Channel Cable Detect 40-Pin
225 */
226 pci_write_config_word(dev, 0x4a, 0xc023);
227
228 /*
229 * Set only the 3rd byteis for the master IDE's cycle and
230 * enable Internal IDE Function
231 */
232 pci_write_config_byte(dev, 0x50, 0x23); /* Class code attr register */
233
234 pci_write_config_byte(dev, 0x09, 0xff); /* Set native mode & stuff */
235 pci_write_config_byte(dev, 0x52, 0x00); /* use timing registers */
236 pci_write_config_byte(dev, 0x58, 0x02); /* Primary addr setup timing */
237 pci_write_config_byte(dev, 0x59, 0x22); /* Primary cmd block timing */
238 pci_write_config_byte(dev, 0x5a, 0x22); /* Pr drv 0 R/W timing */
239 pci_write_config_byte(dev, 0x5b, 0x22); /* Pr drv 1 R/W timing */
240 pci_write_config_byte(dev, 0x5c, 0x02); /* Sec addr setup timing */
241 pci_write_config_byte(dev, 0x5d, 0x22); /* Sec cmd block timing */
242 pci_write_config_byte(dev, 0x5e, 0x22); /* Sec drv 0 R/W timing */
243 pci_write_config_byte(dev, 0x5f, 0x22); /* Sec drv 1 R/W timing */
244 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
245 pci_write_config_word(dev, PCI_COMMAND,
246 PCI_COMMAND_PARITY | PCI_COMMAND_MASTER |
247 PCI_COMMAND_IO);
248}
249
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/setup.c b/arch/mips/vr41xx/nec-cmbvr4133/setup.c
deleted file mode 100644
index 7723d2011b08..000000000000
--- a/arch/mips/vr41xx/nec-cmbvr4133/setup.c
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * arch/mips/vr41xx/nec-cmbvr4133/setup.c
3 *
4 * Setup for the NEC CMB-VR4133.
5 *
6 * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
7 * Alex Sapkov <asapkov@ru.mvista.com>
8 *
9 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * Support for CMBVR4133 board in 2.6
15 * Author: Manish Lachwani (mlachwani@mvista.com)
16 */
17#include <linux/init.h>
18#include <linux/ide.h>
19#include <linux/ioport.h>
20
21#include <asm/reboot.h>
22#include <asm/time.h>
23#include <asm/vr41xx/cmbvr4133.h>
24#include <asm/bootinfo.h>
25
26#ifdef CONFIG_MTD
27#include <linux/mtd/physmap.h>
28#include <linux/mtd/partitions.h>
29#include <linux/mtd/mtd.h>
30#include <linux/mtd/map.h>
31
32static struct mtd_partition cmbvr4133_mtd_parts[] = {
33 {
34 .name = "User FS",
35 .size = 0x1be0000,
36 .offset = 0,
37 .mask_flags = 0,
38 },
39 {
40 .name = "PMON",
41 .size = 0x140000,
42 .offset = MTDPART_OFS_APPEND,
43 .mask_flags = MTD_WRITEABLE, /* force read-only */
44 },
45 {
46 .name = "User FS2",
47 .size = MTDPART_SIZ_FULL,
48 .offset = MTDPART_OFS_APPEND,
49 .mask_flags = 0,
50 }
51};
52
53#define number_partitions ARRAY_SIZE(cmbvr4133_mtd_parts)
54#endif
55
56extern void i8259_init(void);
57
58static void __init nec_cmbvr4133_setup(void)
59{
60#ifdef CONFIG_ROCKHOPPER
61 extern void disable_pcnet(void);
62
63 disable_pcnet();
64#endif
65 set_io_port_base(KSEG1ADDR(0x16000000));
66
67#ifdef CONFIG_PCI
68#ifdef CONFIG_ROCKHOPPER
69 ali_m5229_preinit();
70#endif
71#endif
72
73#ifdef CONFIG_ROCKHOPPER
74 rockhopper_init_irq();
75#endif
76
77#ifdef CONFIG_MTD
78 /* we use generic physmap mapping driver and we use partitions */
79 physmap_configure(0x1C000000, 0x02000000, 4, NULL);
80 physmap_set_partitions(cmbvr4133_mtd_parts, number_partitions);
81#endif
82
83 /* 128 MB memory support */
84 add_memory_region(0, 0x08000000, BOOT_MEM_RAM);
85
86#ifdef CONFIG_ROCKHOPPER
87 i8259_init();
88#endif
89}
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