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Diffstat (limited to 'arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c')
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diff --git a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
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1/*
2 * arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
3 *
4 * Initialize for ALi M1535+(included M5229 and M5237).
5 *
6 * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
7 * Alex Sapkov <asapkov@ru.mvista.com>
8 *
9 * 2003-2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * Support for NEC-CMBVR4133 in 2.6
15 * Author: Manish Lachwani (mlachwani@mvista.com)
16 */
17#include <linux/config.h>
18#include <linux/init.h>
19#include <linux/types.h>
20#include <linux/serial.h>
21
22#include <asm/vr41xx/cmbvr4133.h>
23#include <linux/pci.h>
24#include <asm/io.h>
25
26#define CONFIG_PORT(port) ((port) ? 0x3f0 : 0x370)
27#define DATA_PORT(port) ((port) ? 0x3f1 : 0x371)
28#define INDEX_PORT(port) CONFIG_PORT(port)
29
30#define ENTER_CONFIG_MODE(port) \
31 do { \
32 outb_p(0x51, CONFIG_PORT(port)); \
33 outb_p(0x23, CONFIG_PORT(port)); \
34 } while(0)
35
36#define SELECT_LOGICAL_DEVICE(port, dev_no) \
37 do { \
38 outb_p(0x07, INDEX_PORT(port)); \
39 outb_p((dev_no), DATA_PORT(port)); \
40 } while(0)
41
42#define WRITE_CONFIG_DATA(port,index,data) \
43 do { \
44 outb_p((index), INDEX_PORT(port)); \
45 outb_p((data), DATA_PORT(port)); \
46 } while(0)
47
48#define EXIT_CONFIG_MODE(port) outb(0xbb, CONFIG_PORT(port))
49
50#define PCI_CONFIG_ADDR KSEG1ADDR(0x0f000c18)
51#define PCI_CONFIG_DATA KSEG1ADDR(0x0f000c14)
52
53#ifdef CONFIG_BLK_DEV_FD
54
55void __devinit ali_m1535plus_fdc_init(int port)
56{
57 ENTER_CONFIG_MODE(port);
58 SELECT_LOGICAL_DEVICE(port, 0); /* FDC */
59 WRITE_CONFIG_DATA(port, 0x30, 0x01); /* FDC: enable */
60 WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x3f0 */
61 WRITE_CONFIG_DATA(port, 0x61, 0xf0);
62 WRITE_CONFIG_DATA(port, 0x70, 0x06); /* IRQ: 6 */
63 WRITE_CONFIG_DATA(port, 0x74, 0x02); /* DMA: channel 2 */
64 WRITE_CONFIG_DATA(port, 0xf0, 0x08);
65 WRITE_CONFIG_DATA(port, 0xf1, 0x00);
66 WRITE_CONFIG_DATA(port, 0xf2, 0xff);
67 WRITE_CONFIG_DATA(port, 0xf4, 0x00);
68 EXIT_CONFIG_MODE(port);
69}
70
71#endif
72
73void __devinit ali_m1535plus_parport_init(int port)
74{
75 ENTER_CONFIG_MODE(port);
76 SELECT_LOGICAL_DEVICE(port, 3); /* Parallel Port */
77 WRITE_CONFIG_DATA(port, 0x30, 0x01);
78 WRITE_CONFIG_DATA(port, 0x60, 0x03); /* I/O port base: 0x378 */
79 WRITE_CONFIG_DATA(port, 0x61, 0x78);
80 WRITE_CONFIG_DATA(port, 0x70, 0x07); /* IRQ: 7 */
81 WRITE_CONFIG_DATA(port, 0x74, 0x04); /* DMA: None */
82 WRITE_CONFIG_DATA(port, 0xf0, 0x8c); /* IRQ polarity: Active Low */
83 WRITE_CONFIG_DATA(port, 0xf1, 0xc5);
84 EXIT_CONFIG_MODE(port);
85}
86
87void __devinit ali_m1535plus_keyboard_init(int port)
88{
89 ENTER_CONFIG_MODE(port);
90 SELECT_LOGICAL_DEVICE(port, 7); /* KEYBOARD */
91 WRITE_CONFIG_DATA(port, 0x30, 0x01); /* KEYBOARD: eable */
92 WRITE_CONFIG_DATA(port, 0x70, 0x01); /* IRQ: 1 */
93 WRITE_CONFIG_DATA(port, 0x72, 0x0c); /* PS/2 Mouse IRQ: 12 */
94 WRITE_CONFIG_DATA(port, 0xf0, 0x00);
95 EXIT_CONFIG_MODE(port);
96}
97
98void __devinit ali_m1535plus_hotkey_init(int port)
99{
100 ENTER_CONFIG_MODE(port);
101 SELECT_LOGICAL_DEVICE(port, 0xc); /* HOTKEY */
102 WRITE_CONFIG_DATA(port, 0x30, 0x00);
103 WRITE_CONFIG_DATA(port, 0xf0, 0x35);
104 WRITE_CONFIG_DATA(port, 0xf1, 0x14);
105 WRITE_CONFIG_DATA(port, 0xf2, 0x11);
106 WRITE_CONFIG_DATA(port, 0xf3, 0x71);
107 WRITE_CONFIG_DATA(port, 0xf5, 0x05);
108 EXIT_CONFIG_MODE(port);
109}
110
111void ali_m1535plus_init(struct pci_dev *dev)
112{
113 pci_write_config_byte(dev, 0x40, 0x18); /* PCI Interface Control */
114 pci_write_config_byte(dev, 0x41, 0xc0); /* PS2 keyb & mouse enable */
115 pci_write_config_byte(dev, 0x42, 0x41); /* ISA bus cycle control */
116 pci_write_config_byte(dev, 0x43, 0x00); /* ISA bus cycle control 2 */
117 pci_write_config_byte(dev, 0x44, 0x5d); /* IDE enable & IRQ 14 */
118 pci_write_config_byte(dev, 0x45, 0x0b); /* PCI int polling mode */
119 pci_write_config_byte(dev, 0x47, 0x00); /* BIOS chip select control */
120
121 /* IRQ routing */
122 pci_write_config_byte(dev, 0x48, 0x03); /* INTA IRQ10, INTB disable */
123 pci_write_config_byte(dev, 0x49, 0x00); /* INTC and INTD disable */
124 pci_write_config_byte(dev, 0x4a, 0x00); /* INTE and INTF disable */
125 pci_write_config_byte(dev, 0x4b, 0x90); /* Audio IRQ11, Modem disable */
126
127 pci_write_config_word(dev, 0x50, 0x4000); /* Parity check IDE enable */
128 pci_write_config_word(dev, 0x52, 0x0000); /* USB & RTC disable */
129 pci_write_config_word(dev, 0x54, 0x0002); /* ??? no info */
130 pci_write_config_word(dev, 0x56, 0x0002); /* PCS1J signal disable */
131
132 pci_write_config_byte(dev, 0x59, 0x00); /* PCSDS */
133 pci_write_config_byte(dev, 0x5a, 0x00);
134 pci_write_config_byte(dev, 0x5b, 0x00);
135 pci_write_config_word(dev, 0x5c, 0x0000);
136 pci_write_config_byte(dev, 0x5e, 0x00);
137 pci_write_config_byte(dev, 0x5f, 0x00);
138 pci_write_config_word(dev, 0x60, 0x0000);
139
140 pci_write_config_byte(dev, 0x6c, 0x00);
141 pci_write_config_byte(dev, 0x6d, 0x48); /* ROM address mapping */
142 pci_write_config_byte(dev, 0x6e, 0x00); /* ??? what for? */
143
144 pci_write_config_byte(dev, 0x70, 0x12); /* Serial IRQ control */
145 pci_write_config_byte(dev, 0x71, 0xEF); /* DMA channel select */
146 pci_write_config_byte(dev, 0x72, 0x03); /* USB IDSEL */
147 pci_write_config_byte(dev, 0x73, 0x00); /* ??? no info */
148
149 /*
150 * IRQ setup ALi M5237 USB Host Controller
151 * IRQ: 9
152 */
153 pci_write_config_byte(dev, 0x74, 0x01); /* USB IRQ9 */
154
155 pci_write_config_byte(dev, 0x75, 0x1f); /* IDE2 IRQ 15 */
156 pci_write_config_byte(dev, 0x76, 0x80); /* ACPI disable */
157 pci_write_config_byte(dev, 0x77, 0x40); /* Modem disable */
158 pci_write_config_dword(dev, 0x78, 0x20000000); /* Pin select 2 */
159 pci_write_config_byte(dev, 0x7c, 0x00); /* Pin select 3 */
160 pci_write_config_byte(dev, 0x81, 0x00); /* ID read/write control */
161 pci_write_config_byte(dev, 0x90, 0x00); /* PCI PM block control */
162 pci_write_config_word(dev, 0xa4, 0x0000); /* PMSCR */
163
164#ifdef CONFIG_BLK_DEV_FD
165 ali_m1535plus_fdc_init(1);
166#endif
167
168 ali_m1535plus_keyboard_init(1);
169 ali_m1535plus_hotkey_init(1);
170}
171
172static inline void ali_config_writeb(u8 reg, u8 val, int devfn)
173{
174 u32 data;
175 int shift;
176
177 writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
178 data = readl(PCI_CONFIG_DATA);
179
180 shift = (reg & 3) << 3;
181 data &= ~(0xff << shift);
182 data |= (((u32)val) << shift);
183
184 writel(data, PCI_CONFIG_DATA);
185}
186
187static inline u8 ali_config_readb(u8 reg, int devfn)
188{
189 u32 data;
190
191 writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
192 data = readl(PCI_CONFIG_DATA);
193
194 return (u8)(data >> ((reg & 3) << 3));
195}
196
197static inline u16 ali_config_readw(u8 reg, int devfn)
198{
199 u32 data;
200
201 writel((1 << 16) | (devfn << 8) | (reg & 0xfc) | 1UL, PCI_CONFIG_ADDR);
202 data = readl(PCI_CONFIG_DATA);
203
204 return (u16)(data >> ((reg & 2) << 3));
205}
206
207int vr4133_rockhopper = 0;
208void __init ali_m5229_preinit(void)
209{
210 if (ali_config_readw(PCI_VENDOR_ID,16) == PCI_VENDOR_ID_AL &&
211 ali_config_readw(PCI_DEVICE_ID,16) == PCI_DEVICE_ID_AL_M1533) {
212 printk(KERN_INFO "Found an NEC Rockhopper \n");
213 vr4133_rockhopper = 1;
214 /*
215 * Enable ALi M5229 IDE Controller (both channels)
216 * IDSEL: A27
217 */
218 ali_config_writeb(0x58, 0x4c, 16);
219 }
220}
221
222void __init ali_m5229_init(struct pci_dev *dev)
223{
224 /*
225 * Enable Primary/Secondary Channel Cable Detect 40-Pin
226 */
227 pci_write_config_word(dev, 0x4a, 0xc023);
228
229 /*
230 * Set only the 3rd byteis for the master IDE's cycle and
231 * enable Internal IDE Function
232 */
233 pci_write_config_byte(dev, 0x50, 0x23); /* Class code attr register */
234
235 pci_write_config_byte(dev, 0x09, 0xff); /* Set native mode & stuff */
236 pci_write_config_byte(dev, 0x52, 0x00); /* use timing registers */
237 pci_write_config_byte(dev, 0x58, 0x02); /* Primary addr setup timing */
238 pci_write_config_byte(dev, 0x59, 0x22); /* Primary cmd block timing */
239 pci_write_config_byte(dev, 0x5a, 0x22); /* Pr drv 0 R/W timing */
240 pci_write_config_byte(dev, 0x5b, 0x22); /* Pr drv 1 R/W timing */
241 pci_write_config_byte(dev, 0x5c, 0x02); /* Sec addr setup timing */
242 pci_write_config_byte(dev, 0x5d, 0x22); /* Sec cmd block timing */
243 pci_write_config_byte(dev, 0x5e, 0x22); /* Sec drv 0 R/W timing */
244 pci_write_config_byte(dev, 0x5f, 0x22); /* Sec drv 1 R/W timing */
245 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
246 pci_write_config_word(dev, PCI_COMMAND,
247 PCI_COMMAND_PARITY | PCI_COMMAND_MASTER |
248 PCI_COMMAND_IO);
249}
250
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