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-rw-r--r--arch/mips/txx9/rbtx4938/setup.c667
1 files changed, 98 insertions, 569 deletions
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index bbd572c9675b..144d2cada820 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -15,7 +15,6 @@
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/console.h> 17#include <linux/console.h>
18#include <linux/pci.h>
19#include <linux/pm.h> 18#include <linux/pm.h>
20#include <linux/platform_device.h> 19#include <linux/platform_device.h>
21#include <linux/clk.h> 20#include <linux/clk.h>
@@ -26,6 +25,8 @@
26#include <asm/txx9tmr.h> 25#include <asm/txx9tmr.h>
27#include <asm/io.h> 26#include <asm/io.h>
28#include <asm/bootinfo.h> 27#include <asm/bootinfo.h>
28#include <asm/txx9/generic.h>
29#include <asm/txx9/pci.h>
29#include <asm/txx9/rbtx4938.h> 30#include <asm/txx9/rbtx4938.h>
30#ifdef CONFIG_SERIAL_TXX9 31#ifdef CONFIG_SERIAL_TXX9
31#include <linux/serial_core.h> 32#include <linux/serial_core.h>
@@ -35,37 +36,13 @@
35#include <asm/txx9pio.h> 36#include <asm/txx9pio.h>
36 37
37extern char * __init prom_getcmdline(void); 38extern char * __init prom_getcmdline(void);
38static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
39
40/* These functions are used for rebooting or halting the machine*/ 39/* These functions are used for rebooting or halting the machine*/
41extern void rbtx4938_machine_restart(char *command); 40extern void rbtx4938_machine_restart(char *command);
42extern void rbtx4938_machine_halt(void); 41extern void rbtx4938_machine_halt(void);
43extern void rbtx4938_machine_power_off(void); 42extern void rbtx4938_machine_power_off(void);
44 43
45/* clocks */
46unsigned int txx9_master_clock;
47unsigned int txx9_cpu_clock;
48unsigned int txx9_gbus_clock;
49
50unsigned long rbtx4938_ce_base[8];
51unsigned long rbtx4938_ce_size[8];
52int txboard_pci66_mode;
53static int tx4938_pcic_trdyto; /* default: disabled */
54static int tx4938_pcic_retryto; /* default: disabled */
55static int tx4938_ccfg_toeon = 1; 44static int tx4938_ccfg_toeon = 1;
56 45
57struct tx4938_pcic_reg *pcicptrs[4] = {
58 tx4938_pcicptr /* default setting for TX4938 */
59};
60
61static struct {
62 unsigned long base;
63 unsigned long size;
64} phys_regions[16] __initdata;
65static int num_phys_regions __initdata;
66
67#define PHYS_REGION_MINSIZE 0x10000
68
69void rbtx4938_machine_halt(void) 46void rbtx4938_machine_halt(void)
70{ 47{
71 printk(KERN_NOTICE "System Halted\n"); 48 printk(KERN_NOTICE "System Halted\n");
@@ -95,473 +72,72 @@ void rbtx4938_machine_restart(char *command)
95 ; 72 ;
96} 73}
97 74
98void __init 75static void __init rbtx4938_pci_setup(void)
99txboard_add_phys_region(unsigned long base, unsigned long size)
100{
101 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
102 printk("phys_region overflow\n");
103 return;
104 }
105 phys_regions[num_phys_regions].base = base;
106 phys_regions[num_phys_regions].size = size;
107 num_phys_regions++;
108}
109unsigned long __init
110txboard_find_free_phys_region(unsigned long begin, unsigned long end,
111 unsigned long size)
112{
113 unsigned long base;
114 int i;
115
116 for (base = begin / size * size; base < end; base += size) {
117 for (i = 0; i < num_phys_regions; i++) {
118 if (phys_regions[i].size &&
119 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
120 base + (size - 1) >= phys_regions[i].base)
121 break;
122 }
123 if (i == num_phys_regions)
124 return base;
125 }
126 return 0;
127}
128unsigned long __init
129txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
130 unsigned long *size)
131{
132 unsigned long sz, base;
133 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
134 base = txboard_find_free_phys_region(begin, end, sz);
135 if (base) {
136 *size = sz;
137 return base;
138 }
139 }
140 return 0;
141}
142unsigned long __init
143txboard_request_phys_region_range(unsigned long begin, unsigned long end,
144 unsigned long size)
145{
146 unsigned long base;
147 base = txboard_find_free_phys_region(begin, end, size);
148 if (base)
149 txboard_add_phys_region(base, size);
150 return base;
151}
152unsigned long __init
153txboard_request_phys_region(unsigned long size)
154{ 76{
155 unsigned long base;
156 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
157 base = txboard_find_free_phys_region(begin, end, size);
158 if (base)
159 txboard_add_phys_region(base, size);
160 return base;
161}
162unsigned long __init
163txboard_request_phys_region_shrink(unsigned long *size)
164{
165 unsigned long base;
166 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
167 base = txboard_find_free_phys_region_shrink(begin, end, size);
168 if (base)
169 txboard_add_phys_region(base, *size);
170 return base;
171}
172
173#ifdef CONFIG_PCI 77#ifdef CONFIG_PCI
174void __init 78 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
175tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, 79 struct pci_controller *c = &txx9_primary_pcic;
176 struct pci_controller *channel,
177 unsigned long pci_io_base,
178 int extarb)
179{
180 int i;
181 80
182 /* Disable All Initiator Space */ 81 register_pci_controller(c);
183 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
184 TX4938_PCIC_PCICCFG_G2PMEN(1)|
185 TX4938_PCIC_PCICCFG_G2PMEN(2)|
186 TX4938_PCIC_PCICCFG_G2PIOEN);
187
188 /* GB->PCI mappings */
189 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
190 pcicptr->g2piogbase = pci_io_base |
191#ifdef __BIG_ENDIAN
192 TX4938_PCIC_G2PIOGBASE_ECHG
193#else
194 TX4938_PCIC_G2PIOGBASE_BSDIS
195#endif
196 ;
197 pcicptr->g2piopbase = 0;
198 for (i = 0; i < 3; i++) {
199 pcicptr->g2pmmask[i] = 0;
200 pcicptr->g2pmgbase[i] = 0;
201 pcicptr->g2pmpbase[i] = 0;
202 }
203 if (channel->mem_resource->end) {
204 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
205 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
206#ifdef __BIG_ENDIAN
207 TX4938_PCIC_G2PMnGBASE_ECHG
208#else
209 TX4938_PCIC_G2PMnGBASE_BSDIS
210#endif
211 ;
212 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
213 }
214 /* PCI->GB mappings (I/O 256B) */
215 pcicptr->p2giopbase = 0; /* 256B */
216 pcicptr->p2giogbase = 0;
217 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
218 pcicptr->p2gm0plbase = 0;
219 pcicptr->p2gm0pubase = 0;
220 pcicptr->p2gmgbase[0] = 0 |
221 TX4938_PCIC_P2GMnGBASE_TMEMEN |
222#ifdef __BIG_ENDIAN
223 TX4938_PCIC_P2GMnGBASE_TECHG
224#else
225 TX4938_PCIC_P2GMnGBASE_TBSDIS
226#endif
227 ;
228 /* PCI->GB mappings (MEM 16MB) */
229 pcicptr->p2gm1plbase = 0xffffffff;
230 pcicptr->p2gm1pubase = 0xffffffff;
231 pcicptr->p2gmgbase[1] = 0;
232 /* PCI->GB mappings (MEM 1MB) */
233 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
234 pcicptr->p2gmgbase[2] = 0;
235
236 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
237 /* Enable Initiator Memory Space */
238 if (channel->mem_resource->end)
239 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
240 /* Enable Initiator I/O Space */
241 if (channel->io_resource->end)
242 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
243 /* Enable Initiator Config */
244 pcicptr->pciccfg |=
245 TX4938_PCIC_PCICCFG_ICAEN |
246 TX4938_PCIC_PCICCFG_TCAR;
247
248 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
249 pcicptr->pcicfg1 = 0;
250
251 pcicptr->g2ptocnt &= ~0xffff;
252
253 if (tx4938_pcic_trdyto >= 0) {
254 pcicptr->g2ptocnt &= ~0xff;
255 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
256 }
257
258 if (tx4938_pcic_retryto >= 0) {
259 pcicptr->g2ptocnt &= ~0xff00;
260 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
261 }
262
263 /* Clear All Local Bus Status */
264 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
265 /* Enable All Local Bus Interrupts */
266 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
267 /* Clear All Initiator Status */
268 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
269 /* Enable All Initiator Interrupts */
270 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
271 /* Clear All PCI Status Error */
272 pcicptr->pcistatus =
273 (pcicptr->pcistatus & 0x0000ffff) |
274 (TX4938_PCIC_PCISTATUS_ALL << 16);
275 /* Enable All PCI Status Error Interrupts */
276 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
277
278 if (!extarb) {
279 /* Reset Bus Arbiter */
280 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
281 pcicptr->pbabm = 0;
282 /* Enable Bus Arbiter */
283 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
284 }
285
286 /* PCIC Int => IRC IRQ16 */
287 pcicptr->pcicfg2 =
288 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
289
290 pcicptr->pcistatus = PCI_COMMAND_MASTER |
291 PCI_COMMAND_MEMORY |
292 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
293}
294
295int __init
296tx4938_report_pciclk(void)
297{
298 unsigned long pcode = TX4938_REV_PCODE();
299 int pciclk = 0;
300 printk("TX%lx PCIC --%s PCICLK:",
301 pcode,
302 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
303 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
304
305 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
306 case TX4938_CCFG_PCIDIVMODE_4:
307 pciclk = txx9_cpu_clock / 4; break;
308 case TX4938_CCFG_PCIDIVMODE_4_5:
309 pciclk = txx9_cpu_clock * 2 / 9; break;
310 case TX4938_CCFG_PCIDIVMODE_5:
311 pciclk = txx9_cpu_clock / 5; break;
312 case TX4938_CCFG_PCIDIVMODE_5_5:
313 pciclk = txx9_cpu_clock * 2 / 11; break;
314 case TX4938_CCFG_PCIDIVMODE_8:
315 pciclk = txx9_cpu_clock / 8; break;
316 case TX4938_CCFG_PCIDIVMODE_9:
317 pciclk = txx9_cpu_clock / 9; break;
318 case TX4938_CCFG_PCIDIVMODE_10:
319 pciclk = txx9_cpu_clock / 10; break;
320 case TX4938_CCFG_PCIDIVMODE_11:
321 pciclk = txx9_cpu_clock / 11; break;
322 }
323 printk("Internal(%dMHz)", pciclk / 1000000);
324 } else {
325 printk("External");
326 pciclk = -1;
327 }
328 printk("\n");
329 return pciclk;
330}
331
332void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
333{
334 pcicptrs[ch] = pcicptr;
335}
336
337struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
338{
339 return pcicptrs[ch];
340}
341
342static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
343 int top_bus, int busnr, int devfn)
344{
345 static struct pci_dev dev;
346 static struct pci_bus bus;
347 82
348 dev.sysdata = bus.sysdata = hose; 83 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
349 dev.devfn = devfn; 84 txx9_pci_option =
350 bus.number = busnr; 85 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
351 bus.ops = hose->pci_ops; 86 TXX9_PCI_OPT_CLK_66; /* already configured */
352 bus.parent = NULL;
353 dev.bus = &bus;
354
355 return &dev;
356}
357
358#define EARLY_PCI_OP(rw, size, type) \
359static int early_##rw##_config_##size(struct pci_controller *hose, \
360 int top_bus, int bus, int devfn, int offset, type value) \
361{ \
362 return pci_##rw##_config_##size( \
363 fake_pci_dev(hose, top_bus, bus, devfn), \
364 offset, value); \
365}
366
367EARLY_PCI_OP(read, word, u16 *)
368
369int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
370{
371 u32 pci_devfn;
372 unsigned short vid;
373 int devfn_start = 0;
374 int devfn_stop = 0xff;
375 int cap66 = -1;
376 u16 stat;
377
378 printk("PCI: Checking 66MHz capabilities...\n");
379
380 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
381 if (early_read_config_word(hose, top_bus, current_bus,
382 pci_devfn, PCI_VENDOR_ID,
383 &vid) != PCIBIOS_SUCCESSFUL)
384 continue;
385
386 if (vid == 0xffff) continue;
387
388 /* check 66MHz capability */
389 if (cap66 < 0)
390 cap66 = 1;
391 if (cap66) {
392 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
393 PCI_STATUS, &stat);
394 if (!(stat & PCI_STATUS_66MHZ)) {
395 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
396 current_bus, pci_devfn);
397 cap66 = 0;
398 break;
399 }
400 }
401 }
402 return cap66 > 0;
403}
404
405int __init
406tx4938_pciclk66_setup(void)
407{
408 int pciclk;
409
410 /* Assert M66EN */
411 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
412 /* Double PCICLK (if possible) */
413 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
414 unsigned int pcidivmode =
415 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
416 switch (pcidivmode) {
417 case TX4938_CCFG_PCIDIVMODE_8:
418 case TX4938_CCFG_PCIDIVMODE_4:
419 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
420 pciclk = txx9_cpu_clock / 4;
421 break;
422 case TX4938_CCFG_PCIDIVMODE_9:
423 case TX4938_CCFG_PCIDIVMODE_4_5:
424 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
425 pciclk = txx9_cpu_clock * 2 / 9;
426 break;
427 case TX4938_CCFG_PCIDIVMODE_10:
428 case TX4938_CCFG_PCIDIVMODE_5:
429 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
430 pciclk = txx9_cpu_clock / 5;
431 break;
432 case TX4938_CCFG_PCIDIVMODE_11:
433 case TX4938_CCFG_PCIDIVMODE_5_5:
434 default:
435 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
436 pciclk = txx9_cpu_clock * 2 / 11;
437 break;
438 }
439 tx4938_ccfgptr->ccfg =
440 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
441 | pcidivmode;
442 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
443 (unsigned long)tx4938_ccfgptr->ccfg);
444 } else {
445 pciclk = -1;
446 }
447 return pciclk;
448}
449
450extern struct pci_controller tx4938_pci_controller[];
451static int __init tx4938_pcibios_init(void)
452{
453 unsigned long mem_base[2];
454 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
455 unsigned long io_base[2];
456 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
457 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
458 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
459
460 PCIBIOS_MIN_IO = 0x00001000UL;
461
462 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
463 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
464
465 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
466 (unsigned short)(tx4938_pcicptr->pciid >> 16),
467 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
468 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
469 extarb ? "External" : "Internal");
470
471 /* setup PCI area */
472 tx4938_pci_controller[0].io_resource->start = io_base[0];
473 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
474 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
475 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
476
477 set_tx4938_pcicptr(0, tx4938_pcicptr);
478
479 register_pci_controller(&tx4938_pci_controller[0]);
480
481 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
482 printk("TX4938_CCFG_PCI66 already configured\n");
483 txboard_pci66_mode = -1; /* already configured */
484 }
485 87
486 /* Reset PCI Bus */ 88 /* Reset PCI Bus */
487 writeb(0, rbtx4938_pcireset_addr); 89 writeb(0, rbtx4938_pcireset_addr);
488 /* Reset PCIC */ 90 /* Reset PCIC */
489 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; 91 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
490 if (txboard_pci66_mode > 0) 92 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
93 TXX9_PCI_OPT_CLK_66)
491 tx4938_pciclk66_setup(); 94 tx4938_pciclk66_setup();
492 mdelay(10); 95 mdelay(10);
493 /* clear PCIC reset */ 96 /* clear PCIC reset */
494 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; 97 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
495 writeb(1, rbtx4938_pcireset_addr); 98 writeb(1, rbtx4938_pcireset_addr);
496 mmiowb(); 99 iob();
497 tx4938_report_pcic_status1(tx4938_pcicptr);
498 100
499 tx4938_report_pciclk(); 101 tx4938_report_pciclk();
500 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); 102 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
501 if (txboard_pci66_mode == 0 && 103 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
502 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { 104 TXX9_PCI_OPT_CLK_AUTO &&
105 txx9_pci66_check(c, 0, 0)) {
503 /* Reset PCI Bus */ 106 /* Reset PCI Bus */
504 writeb(0, rbtx4938_pcireset_addr); 107 writeb(0, rbtx4938_pcireset_addr);
505 /* Reset PCIC */ 108 /* Reset PCIC */
506 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; 109 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
507 tx4938_pciclk66_setup(); 110 tx4938_pciclk66_setup();
508 mdelay(10); 111 mdelay(10);
509 /* clear PCIC reset */ 112 /* clear PCIC reset */
510 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; 113 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
511 writeb(1, rbtx4938_pcireset_addr); 114 writeb(1, rbtx4938_pcireset_addr);
512 mmiowb(); 115 iob();
513 /* Reinitialize PCIC */ 116 /* Reinitialize PCIC */
514 tx4938_report_pciclk(); 117 tx4938_report_pciclk();
515 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); 118 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
516 } 119 }
517 120
518 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); 121 if (__raw_readq(&tx4938_ccfgptr->pcfg) &
519 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); 122 (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
520 /* Reset PCIC1 */ 123 /* Reset PCIC1 */
521 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; 124 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
522 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ 125 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
523 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) 126 if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
524 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; 127 & TX4938_CCFG_PCI1DMD))
525 else 128 tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
526 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; 129 mdelay(10);
527 mdelay(10); 130 /* clear PCIC1 reset */
528 /* clear PCIC1 reset */ 131 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
529 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; 132 tx4938_report_pci1clk();
530 tx4938_report_pcic_status1(tx4938_pcic1ptr); 133
531 134 /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
532 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", 135 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
533 (unsigned short)(tx4938_pcic1ptr->pciid >> 16), 136 register_pci_controller(c);
534 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), 137 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
535 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); 138 }
536 printk("%s PCICLK:%dMHz\n",
537 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
538 txx9_gbus_clock /
539 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
540 1000000);
541
542 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
543 tx4938_pci_controller[1].io_resource->start =
544 io_base[1] - io_base[0];
545 tx4938_pci_controller[1].io_resource->end =
546 io_base[1] - io_base[0] + io_size[1] - 1;
547 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
548 tx4938_pci_controller[1].mem_resource->end =
549 mem_base[1] + mem_size[1] - 1;
550 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
551
552 register_pci_controller(&tx4938_pci_controller[1]);
553
554 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
555
556 /* map ioport 0 to PCI I/O space address 0 */
557 set_io_port_base(KSEG1 + io_base[0]);
558
559 return 0;
560}
561
562arch_initcall(tx4938_pcibios_init);
563
564#endif /* CONFIG_PCI */ 139#endif /* CONFIG_PCI */
140}
565 141
566/* SPI support */ 142/* SPI support */
567 143
@@ -594,7 +170,7 @@ static int __init rbtx4938_ethaddr_init(void)
594 unsigned int id = 170 unsigned int id =
595 TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); 171 TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0);
596 struct platform_device *pdev; 172 struct platform_device *pdev;
597 if (!(tx4938_ccfgptr->pcfg & 173 if (!(__raw_readq(&tx4938_ccfgptr->pcfg) &
598 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) 174 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
599 continue; 175 continue;
600 pdev = platform_device_alloc("tc35815-mac", id); 176 pdev = platform_device_alloc("tc35815-mac", id);
@@ -611,18 +187,12 @@ device_initcall(rbtx4938_ethaddr_init);
611static void __init rbtx4938_spi_setup(void) 187static void __init rbtx4938_spi_setup(void)
612{ 188{
613 /* set SPI_SEL */ 189 /* set SPI_SEL */
614 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; 190 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
615} 191}
616 192
617static struct resource rbtx4938_fpga_resource; 193static struct resource rbtx4938_fpga_resource;
618 194static struct resource tx4938_sdram_resource[4];
619static char pcode_str[8]; 195static struct resource tx4938_sram_resource;
620static struct resource tx4938_reg_resource = {
621 .start = TX4938_REG_BASE,
622 .end = TX4938_REG_BASE + TX4938_REG_SIZE,
623 .name = pcode_str,
624 .flags = IORESOURCE_MEM
625};
626 196
627void __init tx4938_board_setup(void) 197void __init tx4938_board_setup(void)
628{ 198{
@@ -631,24 +201,28 @@ void __init tx4938_board_setup(void)
631 int cpuclk = 0; 201 int cpuclk = 0;
632 unsigned long pcode = TX4938_REV_PCODE(); 202 unsigned long pcode = TX4938_REV_PCODE();
633 203
634 ioport_resource.start = 0x1000; 204 ioport_resource.start = 0;
635 ioport_resource.end = 0xffffffff; 205 ioport_resource.end = 0xffffffff;
636 iomem_resource.start = 0x1000; 206 iomem_resource.start = 0;
637 iomem_resource.end = 0xffffffff; /* expand to 4GB */ 207 iomem_resource.end = 0xffffffff; /* expand to 4GB */
638 208
639 sprintf(pcode_str, "TX%lx", pcode); 209 txx9_reg_res_init(pcode, TX4938_REG_BASE,
210 TX4938_REG_SIZE);
640 /* SDRAMC,EBUSC are configured by PROM */ 211 /* SDRAMC,EBUSC are configured by PROM */
641 for (i = 0; i < 8; i++) { 212 for (i = 0; i < 8; i++) {
642 if (!(tx4938_ebuscptr->cr[i] & 0x8)) 213 if (!(TX4938_EBUSC_CR(i) & 0x8))
643 continue; /* disabled */ 214 continue; /* disabled */
644 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); 215 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
645 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); 216 txx9_ce_res[i].end =
217 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
218 request_resource(&iomem_resource, &txx9_ce_res[i]);
646 } 219 }
647 220
648 /* clocks */ 221 /* clocks */
649 if (txx9_master_clock) { 222 if (txx9_master_clock) {
223 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
650 /* calculate gbus_clock and cpu_clock_freq from master_clock */ 224 /* calculate gbus_clock and cpu_clock_freq from master_clock */
651 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; 225 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
652 switch (divmode) { 226 switch (divmode) {
653 case TX4938_CCFG_DIVMODE_8: 227 case TX4938_CCFG_DIVMODE_8:
654 case TX4938_CCFG_DIVMODE_10: 228 case TX4938_CCFG_DIVMODE_10:
@@ -678,12 +252,13 @@ void __init tx4938_board_setup(void)
678 } 252 }
679 txx9_cpu_clock = cpuclk; 253 txx9_cpu_clock = cpuclk;
680 } else { 254 } else {
255 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
681 if (txx9_cpu_clock == 0) { 256 if (txx9_cpu_clock == 0) {
682 txx9_cpu_clock = 300000000; /* 300MHz */ 257 txx9_cpu_clock = 300000000; /* 300MHz */
683 } 258 }
684 /* calculate gbus_clock and master_clock from cpu_clock_freq */ 259 /* calculate gbus_clock and master_clock from cpu_clock_freq */
685 cpuclk = txx9_cpu_clock; 260 cpuclk = txx9_cpu_clock;
686 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; 261 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
687 switch (divmode) { 262 switch (divmode) {
688 case TX4938_CCFG_DIVMODE_2: 263 case TX4938_CCFG_DIVMODE_2:
689 case TX4938_CCFG_DIVMODE_8: 264 case TX4938_CCFG_DIVMODE_8:
@@ -717,32 +292,32 @@ void __init tx4938_board_setup(void)
717 292
718 /* CCFG */ 293 /* CCFG */
719 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ 294 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
720 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; 295 tx4938_ccfg_set(TX4938_CCFG_WDRST | TX4938_CCFG_BEOW);
721 /* do reset on watchdog */ 296 /* do reset on watchdog */
722 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR; 297 tx4938_ccfg_set(TX4938_CCFG_WR);
723 /* clear PCIC1 reset */ 298 /* clear PCIC1 reset */
724 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) 299 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
725 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
726 300
727 /* enable Timeout BusError */ 301 /* enable Timeout BusError */
728 if (tx4938_ccfg_toeon) 302 if (tx4938_ccfg_toeon)
729 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; 303 tx4938_ccfg_set(TX4938_CCFG_TOE);
730 304
731 /* DMA selection */ 305 /* DMA selection */
732 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; 306 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
733 307
734 /* Use external clock for external arbiter */ 308 /* Use external clock for external arbiter */
735 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) 309 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
736 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; 310 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
737 311
738 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", 312 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
739 pcode_str, 313 txx9_pcode_str,
740 cpuclk / 1000000, txx9_master_clock / 1000000, 314 (cpuclk + 500000) / 1000000,
741 (unsigned long)tx4938_ccfgptr->crir, 315 (txx9_master_clock + 500000) / 1000000,
742 tx4938_ccfgptr->ccfg, 316 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
743 tx4938_ccfgptr->pcfg); 317 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
744 318 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
745 printk("%s SDRAMC --", pcode_str); 319
320 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
746 for (i = 0; i < 4; i++) { 321 for (i = 0; i < 4; i++) {
747 unsigned long long cr = tx4938_sdramcptr->cr[i]; 322 unsigned long long cr = tx4938_sdramcptr->cr[i];
748 unsigned long ram_base, ram_size; 323 unsigned long ram_base, ram_size;
@@ -753,16 +328,24 @@ void __init tx4938_board_setup(void)
753 if (ram_base >= 0x20000000) 328 if (ram_base >= 0x20000000)
754 continue; /* high memory (ignore) */ 329 continue; /* high memory (ignore) */
755 printk(" CR%d:%016Lx", i, cr); 330 printk(" CR%d:%016Lx", i, cr);
756 txboard_add_phys_region(ram_base, ram_size); 331 tx4938_sdram_resource[i].name = "SDRAM";
332 tx4938_sdram_resource[i].start = ram_base;
333 tx4938_sdram_resource[i].end = ram_base + ram_size - 1;
334 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
335 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
757 } 336 }
758 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); 337 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
759 338
760 /* SRAM */ 339 /* SRAM */
761 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { 340 if (tx4938_sramcptr->cr & 1) {
762 unsigned int size = 0x800; 341 unsigned int size = 0x800;
763 unsigned long base = 342 unsigned long base =
764 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); 343 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
765 txboard_add_phys_region(base, size); 344 tx4938_sram_resource.name = "SRAM";
345 tx4938_sram_resource.start = base;
346 tx4938_sram_resource.end = base + size - 1;
347 tx4938_sram_resource.flags = IORESOURCE_MEM;
348 request_resource(&iomem_resource, &tx4938_sram_resource);
766 } 349 }
767 350
768 /* TMR */ 351 /* TMR */
@@ -778,71 +361,15 @@ void __init tx4938_board_setup(void)
778 __raw_writel(0, &tx4938_pioptr->maskcpu); 361 __raw_writel(0, &tx4938_pioptr->maskcpu);
779 __raw_writel(0, &tx4938_pioptr->maskext); 362 __raw_writel(0, &tx4938_pioptr->maskext);
780 363
781 /* TX4938 internal registers */
782 if (request_resource(&iomem_resource, &tx4938_reg_resource))
783 printk("request resource for internal registers failed\n");
784}
785
786#ifdef CONFIG_PCI 364#ifdef CONFIG_PCI
787static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) 365 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
788{ 366#endif
789 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
790 unsigned long g2pstatus = pcicptr->g2pstatus;
791 unsigned long pcicstatus = pcicptr->pcicstatus;
792 static struct {
793 unsigned long flag;
794 const char *str;
795 } pcistat_tbl[] = {
796 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
797 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
798 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
799 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
800 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
801 { PCI_STATUS_PARITY, "MasterParityError" },
802 }, g2pstat_tbl[] = {
803 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
804 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
805 }, pcicstat_tbl[] = {
806 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
807 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
808 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
809 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
810 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
811 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
812 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
813 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
814 };
815 int i;
816
817 printk("pcistat:%04x(", pcistatus);
818 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
819 if (pcistatus & pcistat_tbl[i].flag)
820 printk("%s ", pcistat_tbl[i].str);
821 printk("), g2pstatus:%08lx(", g2pstatus);
822 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
823 if (g2pstatus & g2pstat_tbl[i].flag)
824 printk("%s ", g2pstat_tbl[i].str);
825 printk("), pcicstatus:%08lx(", pcicstatus);
826 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
827 if (pcicstatus & pcicstat_tbl[i].flag)
828 printk("%s ", pcicstat_tbl[i].str);
829 printk(")\n");
830}
831
832void tx4938_report_pcic_status(void)
833{
834 int i;
835 struct tx4938_pcic_reg *pcicptr;
836 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
837 tx4938_report_pcic_status1(pcicptr);
838} 367}
839 368
840#endif /* CONFIG_PCI */
841
842void __init plat_time_init(void) 369void __init plat_time_init(void)
843{ 370{
844 mips_hpt_frequency = txx9_cpu_clock / 2; 371 mips_hpt_frequency = txx9_cpu_clock / 2;
845 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS) 372 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
846 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL, 373 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
847 TXX9_IRQ_BASE + TX4938_IR_TMR(0), 374 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
848 txx9_gbus_clock / 2); 375 txx9_gbus_clock / 2);
@@ -890,19 +417,20 @@ void __init plat_mem_setup(void)
890#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 417#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
891 printk("PIOSEL: disabling both ata and nand selection\n"); 418 printk("PIOSEL: disabling both ata and nand selection\n");
892 local_irq_disable(); 419 local_irq_disable();
893 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); 420 txx9_clear64(&tx4938_ccfgptr->pcfg,
421 TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
894#endif 422#endif
895 423
896#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND 424#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
897 printk("PIOSEL: enabling nand selection\n"); 425 printk("PIOSEL: enabling nand selection\n");
898 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; 426 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
899 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; 427 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
900#endif 428#endif
901 429
902#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA 430#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
903 printk("PIOSEL: enabling ata selection\n"); 431 printk("PIOSEL: enabling ata selection\n");
904 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; 432 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
905 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; 433 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
906#endif 434#endif
907 435
908#ifdef CONFIG_IP_PNP 436#ifdef CONFIG_IP_PNP
@@ -920,7 +448,7 @@ void __init plat_mem_setup(void)
920#endif 448#endif
921 449
922 rbtx4938_spi_setup(); 450 rbtx4938_spi_setup();
923 pcfg = tx4938_ccfgptr->pcfg; /* updated */ 451 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
924 /* fixup piosel */ 452 /* fixup piosel */
925 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == 453 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
926 TX4938_PCFG_ATA_SEL) 454 TX4938_PCFG_ATA_SEL)
@@ -1063,6 +591,7 @@ static int __init rbtx4938_arch_init(void)
1063{ 591{
1064 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); 592 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16);
1065 gpiochip_add(&rbtx4938_spi_gpio_chip); 593 gpiochip_add(&rbtx4938_spi_gpio_chip);
594 rbtx4938_pci_setup();
1066 return rbtx4938_spi_init(); 595 return rbtx4938_spi_init();
1067} 596}
1068arch_initcall(rbtx4938_arch_init); 597arch_initcall(rbtx4938_arch_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 03:40:49 -0500