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diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
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1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Copyright 2001 MontaVista Software Inc.
23 * Author: MontaVista Software, Inc.
24 * ahennessy@mvista.com
25 *
26 * Copyright (C) 2000-2001 Toshiba Corporation
27 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
28 */
29
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/types.h>
33#include <linux/ioport.h>
34#include <linux/delay.h>
35#include <linux/pm.h>
36#include <linux/platform_device.h>
37#include <linux/gpio.h>
38#ifdef CONFIG_SERIAL_TXX9
39#include <linux/serial_core.h>
40#endif
41#include <asm/txx9tmr.h>
42#include <asm/txx9pio.h>
43#include <asm/reboot.h>
44#include <asm/txx9/generic.h>
45#include <asm/txx9/pci.h>
46#include <asm/txx9/jmr3927.h>
47#include <asm/mipsregs.h>
48
49extern void puts(const char *cp);
50
51/* don't enable - see errata */
52static int jmr3927_ccfg_toeon;
53
54static inline void do_reset(void)
55{
56#if 1 /* Resetting PCI bus */
57 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
58 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
59 (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
60 mdelay(1);
61 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
62#endif
63 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
64}
65
66static void jmr3927_machine_restart(char *command)
67{
68 local_irq_disable();
69 puts("Rebooting...");
70 do_reset();
71}
72
73static void jmr3927_machine_halt(void)
74{
75 puts("JMR-TX3927 halted.\n");
76 while (1);
77}
78
79static void jmr3927_machine_power_off(void)
80{
81 puts("JMR-TX3927 halted. Please turn off the power.\n");
82 while (1);
83}
84
85static void __init jmr3927_time_init(void)
86{
87 txx9_clockevent_init(TX3927_TMR_REG(0),
88 TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0),
89 JMR3927_IMCLK);
90 txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
91}
92
93#define DO_WRITE_THROUGH
94#define DO_ENABLE_CACHE
95
96static void jmr3927_board_init(void);
97
98static void __init jmr3927_mem_setup(void)
99{
100 char *argptr;
101
102 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
103
104 _machine_restart = jmr3927_machine_restart;
105 _machine_halt = jmr3927_machine_halt;
106 pm_power_off = jmr3927_machine_power_off;
107
108 /*
109 * IO/MEM resources.
110 */
111 ioport_resource.start = 0;
112 ioport_resource.end = 0xffffffff;
113 iomem_resource.start = 0;
114 iomem_resource.end = 0xffffffff;
115
116 /* Reboot on panic */
117 panic_timeout = 180;
118
119 /* cache setup */
120 {
121 unsigned int conf;
122#ifdef DO_ENABLE_CACHE
123 int mips_ic_disable = 0, mips_dc_disable = 0;
124#else
125 int mips_ic_disable = 1, mips_dc_disable = 1;
126#endif
127#ifdef DO_WRITE_THROUGH
128 int mips_config_cwfon = 0;
129 int mips_config_wbon = 0;
130#else
131 int mips_config_cwfon = 1;
132 int mips_config_wbon = 1;
133#endif
134
135 conf = read_c0_conf();
136 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
137 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
138 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
139 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
140 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
141
142 write_c0_conf(conf);
143 write_c0_cache(0);
144 }
145
146 /* initialize board */
147 jmr3927_board_init();
148
149 argptr = prom_getcmdline();
150
151 if ((argptr = strstr(argptr, "toeon")) != NULL)
152 jmr3927_ccfg_toeon = 1;
153 argptr = prom_getcmdline();
154 if ((argptr = strstr(argptr, "ip=")) == NULL) {
155 argptr = prom_getcmdline();
156 strcat(argptr, " ip=bootp");
157 }
158
159#ifdef CONFIG_SERIAL_TXX9
160 {
161 extern int early_serial_txx9_setup(struct uart_port *port);
162 int i;
163 struct uart_port req;
164 for(i = 0; i < 2; i++) {
165 memset(&req, 0, sizeof(req));
166 req.line = i;
167 req.iotype = UPIO_MEM;
168 req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
169 req.mapbase = TX3927_SIO_REG(i);
170 req.irq = i == 0 ?
171 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
172 if (i == 0)
173 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
174 req.uartclk = JMR3927_IMCLK;
175 early_serial_txx9_setup(&req);
176 }
177 }
178#ifdef CONFIG_SERIAL_TXX9_CONSOLE
179 argptr = prom_getcmdline();
180 if ((argptr = strstr(argptr, "console=")) == NULL) {
181 argptr = prom_getcmdline();
182 strcat(argptr, " console=ttyS1,115200");
183 }
184#endif
185#endif
186}
187
188static void tx3927_setup(void);
189
190static void __init jmr3927_pci_setup(void)
191{
192#ifdef CONFIG_PCI
193 int extarb = !(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB);
194 struct pci_controller *c;
195
196 c = txx9_alloc_pci_controller(&txx9_primary_pcic,
197 JMR3927_PCIMEM, JMR3927_PCIMEM_SIZE,
198 JMR3927_PCIIO, JMR3927_PCIIO_SIZE);
199 register_pci_controller(c);
200 if (!extarb) {
201 /* Reset PCI Bus */
202 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
203 udelay(100);
204 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
205 JMR3927_IOC_RESET_ADDR);
206 udelay(100);
207 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
208 }
209 tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb);
210#endif /* CONFIG_PCI */
211}
212
213static void __init jmr3927_board_init(void)
214{
215 tx3927_setup();
216 jmr3927_pci_setup();
217
218 /* SIO0 DTR on */
219 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
220
221 jmr3927_led_set(0);
222
223 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
224 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
225 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
226 jmr3927_dipsw1(), jmr3927_dipsw2(),
227 jmr3927_dipsw3(), jmr3927_dipsw4());
228}
229
230static void __init tx3927_setup(void)
231{
232 int i;
233
234 txx9_cpu_clock = JMR3927_CORECLK;
235 txx9_gbus_clock = JMR3927_GBUSCLK;
236 /* SDRAMC are configured by PROM */
237
238 /* ROMC */
239 tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
240 tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
241 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
242 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
243
244 /* CCFG */
245 /* enable Timeout BusError */
246 if (jmr3927_ccfg_toeon)
247 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
248
249 /* clear BusErrorOnWrite flag */
250 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
251 /* Disable PCI snoop */
252 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
253 /* do reset on watchdog */
254 tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
255
256#ifdef DO_WRITE_THROUGH
257 /* Enable PCI SNOOP - with write through only */
258 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
259#endif
260
261 /* Pin selection */
262 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
263 tx3927_ccfgptr->pcfg |=
264 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
265 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
266
267 printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
268 tx3927_ccfgptr->crir,
269 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
270
271 /* TMR */
272 for (i = 0; i < TX3927_NR_TMR; i++)
273 txx9_tmr_init(TX3927_TMR_REG(i));
274
275 /* DMA */
276 tx3927_dmaptr->mcr = 0;
277 for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
278 /* reset channel */
279 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
280 tx3927_dmaptr->ch[i].ccr = 0;
281 }
282 /* enable DMA */
283#ifdef __BIG_ENDIAN
284 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
285#else
286 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
287#endif
288
289 /* PIO */
290 /* PIO[15:12] connected to LEDs */
291 __raw_writel(0x0000f000, &tx3927_pioptr->dir);
292 __raw_writel(0, &tx3927_pioptr->maskcpu);
293 __raw_writel(0, &tx3927_pioptr->maskext);
294 txx9_gpio_init(TX3927_PIO_REG, 0, 16);
295 gpio_request(11, "dipsw1");
296 gpio_request(10, "dipsw2");
297 {
298 unsigned int conf;
299
300 conf = read_c0_conf();
301 if (!(conf & TX39_CONF_ICE))
302 printk("TX3927 I-Cache disabled.\n");
303 if (!(conf & TX39_CONF_DCE))
304 printk("TX3927 D-Cache disabled.\n");
305 else if (!(conf & TX39_CONF_WBON))
306 printk("TX3927 D-Cache WriteThrough.\n");
307 else if (!(conf & TX39_CONF_CWFON))
308 printk("TX3927 D-Cache WriteBack.\n");
309 else
310 printk("TX3927 D-Cache WriteBack (CWF) .\n");
311 }
312}
313
314/* This trick makes rtc-ds1742 driver usable as is. */
315static unsigned long jmr3927_swizzle_addr_b(unsigned long port)
316{
317 if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR)
318 return port;
319 port = (port & 0xffff0000) | (port & 0x7fff << 1);
320#ifdef __BIG_ENDIAN
321 return port;
322#else
323 return port | 1;
324#endif
325}
326
327static int __init jmr3927_rtc_init(void)
328{
329 static struct resource __initdata res = {
330 .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
331 .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
332 .flags = IORESOURCE_MEM,
333 };
334 struct platform_device *dev;
335 dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1);
336 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
337}
338
339/* Watchdog support */
340
341static int __init txx9_wdt_init(unsigned long base)
342{
343 struct resource res = {
344 .start = base,
345 .end = base + 0x100 - 1,
346 .flags = IORESOURCE_MEM,
347 };
348 struct platform_device *dev =
349 platform_device_register_simple("txx9wdt", -1, &res, 1);
350 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
351}
352
353static int __init jmr3927_wdt_init(void)
354{
355 return txx9_wdt_init(TX3927_TMR_REG(2));
356}
357
358static void __init jmr3927_device_init(void)
359{
360 __swizzle_addr_b = jmr3927_swizzle_addr_b;
361 jmr3927_rtc_init();
362 jmr3927_wdt_init();
363}
364
365struct txx9_board_vec jmr3927_vec __initdata = {
366 .system = "Toshiba JMR_TX3927",
367 .prom_init = jmr3927_prom_init,
368 .mem_setup = jmr3927_mem_setup,
369 .irq_setup = jmr3927_irq_setup,
370 .time_init = jmr3927_time_init,
371 .device_init = jmr3927_device_init,
372#ifdef CONFIG_PCI
373 .pci_map_irq = jmr3927_pci_map_irq,
374#endif
375};
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