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-rw-r--r--arch/mips/txx9/jmr3927/irq.c171
1 files changed, 171 insertions, 0 deletions
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c
new file mode 100644
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1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2000-2001 Toshiba Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32#include <linux/init.h>
33#include <linux/sched.h>
34#include <linux/types.h>
35#include <linux/interrupt.h>
36
37#include <asm/io.h>
38#include <asm/mipsregs.h>
39#include <asm/system.h>
40
41#include <asm/processor.h>
42#include <asm/txx9/generic.h>
43#include <asm/txx9/jmr3927.h>
44
45#if JMR3927_IRQ_END > NR_IRQS
46#error JMR3927_IRQ_END > NR_IRQS
47#endif
48
49static unsigned char irc_level[TX3927_NUM_IR] = {
50 5, 5, 5, 5, 5, 5, /* INT[5:0] */
51 7, 7, /* SIO */
52 5, 5, 5, 0, 0, /* DMA, PIO, PCI */
53 6, 6, 6 /* TMR */
54};
55
56/*
57 * CP0_STATUS is a thread's resource (saved/restored on context switch).
58 * So disable_irq/enable_irq MUST handle IOC/IRC registers.
59 */
60static void mask_irq_ioc(unsigned int irq)
61{
62 /* 0: mask */
63 unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
64 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
65 unsigned int bit = 1 << irq_nr;
66 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
67 /* flush write buffer */
68 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
69}
70static void unmask_irq_ioc(unsigned int irq)
71{
72 /* 0: mask */
73 unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
74 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
75 unsigned int bit = 1 << irq_nr;
76 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
77 /* flush write buffer */
78 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
79}
80
81static int jmr3927_ioc_irqroute(void)
82{
83 unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
84 int i;
85
86 for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
87 if (istat & (1 << i))
88 return JMR3927_IRQ_IOC + i;
89 }
90 return -1;
91}
92
93static int jmr3927_irq_dispatch(int pending)
94{
95 int irq;
96
97 if ((pending & CAUSEF_IP7) == 0)
98 return -1;
99 irq = (pending >> CAUSEB_IP2) & 0x0f;
100 irq += JMR3927_IRQ_IRC;
101 if (irq == JMR3927_IRQ_IOCINT)
102 irq = jmr3927_ioc_irqroute();
103 return irq;
104}
105
106#ifdef CONFIG_PCI
107static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
108{
109 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
110 printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
111 tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
112
113 return IRQ_HANDLED;
114}
115static struct irqaction pcierr_action = {
116 .handler = jmr3927_pcierr_interrupt,
117 .mask = CPU_MASK_NONE,
118 .name = "PCI error",
119};
120#endif
121
122static void __init jmr3927_irq_init(void);
123
124void __init jmr3927_irq_setup(void)
125{
126 txx9_irq_dispatch = jmr3927_irq_dispatch;
127 /* Now, interrupt control disabled, */
128 /* all IRC interrupts are masked, */
129 /* all IRC interrupt mode are Low Active. */
130
131 /* mask all IOC interrupts */
132 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
133 /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
134 jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
135
136 /* clear PCI Soft interrupts */
137 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
138 /* clear PCI Reset interrupts */
139 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
140
141 jmr3927_irq_init();
142
143 /* setup IOC interrupt 1 (PCI, MODEM) */
144 set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
145
146#ifdef CONFIG_PCI
147 setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
148#endif
149
150 /* enable all CPU interrupt bits. */
151 set_c0_status(ST0_IM); /* IE bit is still 0. */
152}
153
154static struct irq_chip jmr3927_irq_ioc = {
155 .name = "jmr3927_ioc",
156 .ack = mask_irq_ioc,
157 .mask = mask_irq_ioc,
158 .mask_ack = mask_irq_ioc,
159 .unmask = unmask_irq_ioc,
160};
161
162static void __init jmr3927_irq_init(void)
163{
164 u32 i;
165
166 txx9_irq_init(TX3927_IRC_REG);
167 for (i = 0; i < TXx9_MAX_IR; i++)
168 txx9_irq_set_pri(i, irc_level[i]);
169 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
170 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
171}
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