diff options
Diffstat (limited to 'arch/mips/txx9/jmr3927/irq.c')
-rw-r--r-- | arch/mips/txx9/jmr3927/irq.c | 43 |
1 files changed, 12 insertions, 31 deletions
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c index f3b60233e99d..68f74368ddec 100644 --- a/arch/mips/txx9/jmr3927/irq.c +++ b/arch/mips/txx9/jmr3927/irq.c | |||
@@ -46,13 +46,6 @@ | |||
46 | #error JMR3927_IRQ_END > NR_IRQS | 46 | #error JMR3927_IRQ_END > NR_IRQS |
47 | #endif | 47 | #endif |
48 | 48 | ||
49 | static unsigned char irc_level[TX3927_NUM_IR] = { | ||
50 | 5, 5, 5, 5, 5, 5, /* INT[5:0] */ | ||
51 | 7, 7, /* SIO */ | ||
52 | 5, 5, 5, 0, 0, /* DMA, PIO, PCI */ | ||
53 | 6, 6, 6 /* TMR */ | ||
54 | }; | ||
55 | |||
56 | /* | 49 | /* |
57 | * CP0_STATUS is a thread's resource (saved/restored on context switch). | 50 | * CP0_STATUS is a thread's resource (saved/restored on context switch). |
58 | * So disable_irq/enable_irq MUST handle IOC/IRC registers. | 51 | * So disable_irq/enable_irq MUST handle IOC/IRC registers. |
@@ -103,10 +96,18 @@ static int jmr3927_irq_dispatch(int pending) | |||
103 | return irq; | 96 | return irq; |
104 | } | 97 | } |
105 | 98 | ||
106 | static void __init jmr3927_irq_init(void); | 99 | static struct irq_chip jmr3927_irq_ioc = { |
100 | .name = "jmr3927_ioc", | ||
101 | .ack = mask_irq_ioc, | ||
102 | .mask = mask_irq_ioc, | ||
103 | .mask_ack = mask_irq_ioc, | ||
104 | .unmask = unmask_irq_ioc, | ||
105 | }; | ||
107 | 106 | ||
108 | void __init jmr3927_irq_setup(void) | 107 | void __init jmr3927_irq_setup(void) |
109 | { | 108 | { |
109 | int i; | ||
110 | |||
110 | txx9_irq_dispatch = jmr3927_irq_dispatch; | 111 | txx9_irq_dispatch = jmr3927_irq_dispatch; |
111 | /* Now, interrupt control disabled, */ | 112 | /* Now, interrupt control disabled, */ |
112 | /* all IRC interrupts are masked, */ | 113 | /* all IRC interrupts are masked, */ |
@@ -122,30 +123,10 @@ void __init jmr3927_irq_setup(void) | |||
122 | /* clear PCI Reset interrupts */ | 123 | /* clear PCI Reset interrupts */ |
123 | jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); | 124 | jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR); |
124 | 125 | ||
125 | jmr3927_irq_init(); | 126 | tx3927_irq_init(); |
127 | for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) | ||
128 | set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); | ||
126 | 129 | ||
127 | /* setup IOC interrupt 1 (PCI, MODEM) */ | 130 | /* setup IOC interrupt 1 (PCI, MODEM) */ |
128 | set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); | 131 | set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq); |
129 | |||
130 | /* enable all CPU interrupt bits. */ | ||
131 | set_c0_status(ST0_IM); /* IE bit is still 0. */ | ||
132 | } | ||
133 | |||
134 | static struct irq_chip jmr3927_irq_ioc = { | ||
135 | .name = "jmr3927_ioc", | ||
136 | .ack = mask_irq_ioc, | ||
137 | .mask = mask_irq_ioc, | ||
138 | .mask_ack = mask_irq_ioc, | ||
139 | .unmask = unmask_irq_ioc, | ||
140 | }; | ||
141 | |||
142 | static void __init jmr3927_irq_init(void) | ||
143 | { | ||
144 | u32 i; | ||
145 | |||
146 | txx9_irq_init(TX3927_IRC_REG); | ||
147 | for (i = 0; i < TXx9_MAX_IR; i++) | ||
148 | txx9_irq_set_pri(i, irc_level[i]); | ||
149 | for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++) | ||
150 | set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq); | ||
151 | } | 132 | } |