aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/txx9/generic
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/txx9/generic')
-rw-r--r--arch/mips/txx9/generic/Makefile4
-rw-r--r--arch/mips/txx9/generic/irq_tx4927.c2
-rw-r--r--arch/mips/txx9/generic/irq_tx4938.c2
-rw-r--r--arch/mips/txx9/generic/setup.c16
-rw-r--r--arch/mips/txx9/generic/setup_tx4927.c194
-rw-r--r--arch/mips/txx9/generic/setup_tx4938.c259
6 files changed, 471 insertions, 6 deletions
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index ab274ede9a70..9c120771e65f 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -4,8 +4,8 @@
4 4
5obj-y += setup.o 5obj-y += setup.o
6obj-$(CONFIG_PCI) += pci.o 6obj-$(CONFIG_PCI) += pci.o
7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o irq_tx4927.o 7obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
8obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o irq_tx4938.o 8obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
10obj-$(CONFIG_KGDB) += dbgio.o 10obj-$(CONFIG_KGDB) += dbgio.o
11 11
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
index 6377bd8a9050..cbea1fdde82b 100644
--- a/arch/mips/txx9/generic/irq_tx4927.c
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -31,7 +31,7 @@
31void __init tx4927_irq_init(void) 31void __init tx4927_irq_init(void)
32{ 32{
33 mips_cpu_irq_init(); 33 mips_cpu_irq_init();
34 txx9_irq_init(TX4927_IRC_REG); 34 txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
35 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT, 35 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
36 handle_simple_irq); 36 handle_simple_irq);
37} 37}
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c
index 5fc86c9c9d2f..6eac684bf190 100644
--- a/arch/mips/txx9/generic/irq_tx4938.c
+++ b/arch/mips/txx9/generic/irq_tx4938.c
@@ -19,7 +19,7 @@
19void __init tx4938_irq_init(void) 19void __init tx4938_irq_init(void)
20{ 20{
21 mips_cpu_irq_init(); 21 mips_cpu_irq_init();
22 txx9_irq_init(TX4938_IRC_REG); 22 txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
23 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT, 23 set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
24 handle_simple_irq); 24 handle_simple_irq);
25} 25}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 8caef07701bb..3715a8f5ea44 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -30,6 +30,7 @@ struct resource txx9_ce_res[8];
30static char txx9_ce_res_name[8][4]; /* "CEn" */ 30static char txx9_ce_res_name[8][4]; /* "CEn" */
31 31
32/* pcode, internal register */ 32/* pcode, internal register */
33unsigned int txx9_pcode;
33char txx9_pcode_str[8]; 34char txx9_pcode_str[8];
34static struct resource txx9_reg_res = { 35static struct resource txx9_reg_res = {
35 .name = txx9_pcode_str, 36 .name = txx9_pcode_str,
@@ -59,15 +60,16 @@ unsigned int txx9_master_clock;
59unsigned int txx9_cpu_clock; 60unsigned int txx9_cpu_clock;
60unsigned int txx9_gbus_clock; 61unsigned int txx9_gbus_clock;
61 62
63int txx9_ccfg_toeon __initdata = 1;
62 64
63/* Minimum CLK support */ 65/* Minimum CLK support */
64 66
65struct clk *clk_get(struct device *dev, const char *id) 67struct clk *clk_get(struct device *dev, const char *id)
66{ 68{
67 if (!strcmp(id, "spi-baseclk")) 69 if (!strcmp(id, "spi-baseclk"))
68 return (struct clk *)(txx9_gbus_clock / 2 / 4); 70 return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4);
69 if (!strcmp(id, "imbus_clk")) 71 if (!strcmp(id, "imbus_clk"))
70 return (struct clk *)(txx9_gbus_clock / 2); 72 return (struct clk *)((unsigned long)txx9_gbus_clock / 2);
71 return ERR_PTR(-ENOENT); 73 return ERR_PTR(-ENOENT);
72} 74}
73EXPORT_SYMBOL(clk_get); 75EXPORT_SYMBOL(clk_get);
@@ -123,6 +125,12 @@ void __init prom_init_cmdline(void)
123 int argc = (int)fw_arg0; 125 int argc = (int)fw_arg0;
124 char **argv = (char **)fw_arg1; 126 char **argv = (char **)fw_arg1;
125 int i; /* Always ignore the "-c" at argv[0] */ 127 int i; /* Always ignore the "-c" at argv[0] */
128#ifdef CONFIG_64BIT
129 char *fixed_argv[32];
130 for (i = 0; i < argc; i++)
131 fixed_argv[i] = (char *)(long)(*((__s32 *)argv + i));
132 argv = fixed_argv;
133#endif
126 134
127 /* ignore all built-in args if any f/w args given */ 135 /* ignore all built-in args if any f/w args given */
128 if (argc > 1) 136 if (argc > 1)
@@ -180,6 +188,10 @@ char * __init prom_getcmdline(void)
180/* wrappers */ 188/* wrappers */
181void __init plat_mem_setup(void) 189void __init plat_mem_setup(void)
182{ 190{
191 ioport_resource.start = 0;
192 ioport_resource.end = ~0UL; /* no limit */
193 iomem_resource.start = 0;
194 iomem_resource.end = ~0UL; /* no limit */
183 txx9_board_vec->mem_setup(); 195 txx9_board_vec->mem_setup();
184} 196}
185 197
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
new file mode 100644
index 000000000000..89d6e28add93
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -0,0 +1,194 @@
1/*
2 * TX4927 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h>
18#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h>
20#include <asm/txx9pio.h>
21#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4927.h>
23
24void __init tx4927_wdr_init(void)
25{
26 /* clear WatchDogReset (W1C) */
27 tx4927_ccfg_set(TX4927_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4927_ccfg_set(TX4927_CCFG_WR);
30}
31
32static struct resource tx4927_sdram_resource[4];
33
34void __init tx4927_setup(void)
35{
36 int i;
37 __u32 divmode;
38 int cpuclk = 0;
39 u64 ccfg;
40
41 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
42 TX4927_REG_SIZE);
43
44 /* SDRAMC,EBUSC are configured by PROM */
45 for (i = 0; i < 8; i++) {
46 if (!(TX4927_EBUSC_CR(i) & 0x8))
47 continue; /* disabled */
48 txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
49 txx9_ce_res[i].end =
50 txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
51 request_resource(&iomem_resource, &txx9_ce_res[i]);
52 }
53
54 /* clocks */
55 ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
56 if (txx9_master_clock) {
57 /* calculate gbus_clock and cpu_clock from master_clock */
58 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
59 switch (divmode) {
60 case TX4927_CCFG_DIVMODE_8:
61 case TX4927_CCFG_DIVMODE_10:
62 case TX4927_CCFG_DIVMODE_12:
63 case TX4927_CCFG_DIVMODE_16:
64 txx9_gbus_clock = txx9_master_clock * 4; break;
65 default:
66 txx9_gbus_clock = txx9_master_clock;
67 }
68 switch (divmode) {
69 case TX4927_CCFG_DIVMODE_2:
70 case TX4927_CCFG_DIVMODE_8:
71 cpuclk = txx9_gbus_clock * 2; break;
72 case TX4927_CCFG_DIVMODE_2_5:
73 case TX4927_CCFG_DIVMODE_10:
74 cpuclk = txx9_gbus_clock * 5 / 2; break;
75 case TX4927_CCFG_DIVMODE_3:
76 case TX4927_CCFG_DIVMODE_12:
77 cpuclk = txx9_gbus_clock * 3; break;
78 case TX4927_CCFG_DIVMODE_4:
79 case TX4927_CCFG_DIVMODE_16:
80 cpuclk = txx9_gbus_clock * 4; break;
81 }
82 txx9_cpu_clock = cpuclk;
83 } else {
84 if (txx9_cpu_clock == 0)
85 txx9_cpu_clock = 200000000; /* 200MHz */
86 /* calculate gbus_clock and master_clock from cpu_clock */
87 cpuclk = txx9_cpu_clock;
88 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
89 switch (divmode) {
90 case TX4927_CCFG_DIVMODE_2:
91 case TX4927_CCFG_DIVMODE_8:
92 txx9_gbus_clock = cpuclk / 2; break;
93 case TX4927_CCFG_DIVMODE_2_5:
94 case TX4927_CCFG_DIVMODE_10:
95 txx9_gbus_clock = cpuclk * 2 / 5; break;
96 case TX4927_CCFG_DIVMODE_3:
97 case TX4927_CCFG_DIVMODE_12:
98 txx9_gbus_clock = cpuclk / 3; break;
99 case TX4927_CCFG_DIVMODE_4:
100 case TX4927_CCFG_DIVMODE_16:
101 txx9_gbus_clock = cpuclk / 4; break;
102 }
103 switch (divmode) {
104 case TX4927_CCFG_DIVMODE_8:
105 case TX4927_CCFG_DIVMODE_10:
106 case TX4927_CCFG_DIVMODE_12:
107 case TX4927_CCFG_DIVMODE_16:
108 txx9_master_clock = txx9_gbus_clock / 4; break;
109 default:
110 txx9_master_clock = txx9_gbus_clock;
111 }
112 }
113 /* change default value to udelay/mdelay take reasonable time */
114 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
115
116 /* CCFG */
117 tx4927_wdr_init();
118 /* clear BusErrorOnWrite flag (W1C) */
119 tx4927_ccfg_set(TX4927_CCFG_BEOW);
120 /* enable Timeout BusError */
121 if (txx9_ccfg_toeon)
122 tx4927_ccfg_set(TX4927_CCFG_TOE);
123
124 /* DMA selection */
125 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
126
127 /* Use external clock for external arbiter */
128 if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
129 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
130
131 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
132 txx9_pcode_str,
133 (cpuclk + 500000) / 1000000,
134 (txx9_master_clock + 500000) / 1000000,
135 (__u32)____raw_readq(&tx4927_ccfgptr->crir),
136 (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
137 (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
138
139 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
140 for (i = 0; i < 4; i++) {
141 __u64 cr = TX4927_SDRAMC_CR(i);
142 unsigned long base, size;
143 if (!((__u32)cr & 0x00000400))
144 continue; /* disabled */
145 base = (unsigned long)(cr >> 49) << 21;
146 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
147 printk(" CR%d:%016llx", i, (unsigned long long)cr);
148 tx4927_sdram_resource[i].name = "SDRAM";
149 tx4927_sdram_resource[i].start = base;
150 tx4927_sdram_resource[i].end = base + size - 1;
151 tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
152 request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
153 }
154 printk(" TR:%09llx\n",
155 (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
156
157 /* TMR */
158 /* disable all timers */
159 for (i = 0; i < TX4927_NR_TMR; i++)
160 txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
161
162 /* PIO */
163 txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
164 __raw_writel(0, &tx4927_pioptr->maskcpu);
165 __raw_writel(0, &tx4927_pioptr->maskext);
166}
167
168void __init tx4927_time_init(unsigned int tmrnr)
169{
170 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
171 txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
172 TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
173 TXX9_IMCLK);
174}
175
176void __init tx4927_setup_serial(void)
177{
178#ifdef CONFIG_SERIAL_TXX9
179 int i;
180 struct uart_port req;
181
182 for (i = 0; i < 2; i++) {
183 memset(&req, 0, sizeof(req));
184 req.line = i;
185 req.iotype = UPIO_MEM;
186 req.membase = (unsigned char __iomem *)TX4927_SIO_REG(i);
187 req.mapbase = TX4927_SIO_REG(i) & 0xfffffffffULL;
188 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
189 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
190 req.uartclk = TXX9_IMCLK;
191 early_serial_txx9_setup(&req);
192 }
193#endif /* CONFIG_SERIAL_TXX9 */
194}
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
new file mode 100644
index 000000000000..317378d8579d
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -0,0 +1,259 @@
1/*
2 * TX4938/4937 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h>
18#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h>
20#include <asm/txx9pio.h>
21#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4938.h>
23
24void __init tx4938_wdr_init(void)
25{
26 /* clear WatchDogReset (W1C) */
27 tx4938_ccfg_set(TX4938_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4938_ccfg_set(TX4938_CCFG_WR);
30}
31
32static struct resource tx4938_sdram_resource[4];
33static struct resource tx4938_sram_resource;
34
35#define TX4938_SRAM_SIZE 0x800
36
37void __init tx4938_setup(void)
38{
39 int i;
40 __u32 divmode;
41 int cpuclk = 0;
42 u64 ccfg;
43
44 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
45 TX4938_REG_SIZE);
46
47 /* SDRAMC,EBUSC are configured by PROM */
48 for (i = 0; i < 8; i++) {
49 if (!(TX4938_EBUSC_CR(i) & 0x8))
50 continue; /* disabled */
51 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
52 txx9_ce_res[i].end =
53 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
54 request_resource(&iomem_resource, &txx9_ce_res[i]);
55 }
56
57 /* clocks */
58 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
59 if (txx9_master_clock) {
60 /* calculate gbus_clock and cpu_clock from master_clock */
61 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
62 switch (divmode) {
63 case TX4938_CCFG_DIVMODE_8:
64 case TX4938_CCFG_DIVMODE_10:
65 case TX4938_CCFG_DIVMODE_12:
66 case TX4938_CCFG_DIVMODE_16:
67 case TX4938_CCFG_DIVMODE_18:
68 txx9_gbus_clock = txx9_master_clock * 4; break;
69 default:
70 txx9_gbus_clock = txx9_master_clock;
71 }
72 switch (divmode) {
73 case TX4938_CCFG_DIVMODE_2:
74 case TX4938_CCFG_DIVMODE_8:
75 cpuclk = txx9_gbus_clock * 2; break;
76 case TX4938_CCFG_DIVMODE_2_5:
77 case TX4938_CCFG_DIVMODE_10:
78 cpuclk = txx9_gbus_clock * 5 / 2; break;
79 case TX4938_CCFG_DIVMODE_3:
80 case TX4938_CCFG_DIVMODE_12:
81 cpuclk = txx9_gbus_clock * 3; break;
82 case TX4938_CCFG_DIVMODE_4:
83 case TX4938_CCFG_DIVMODE_16:
84 cpuclk = txx9_gbus_clock * 4; break;
85 case TX4938_CCFG_DIVMODE_4_5:
86 case TX4938_CCFG_DIVMODE_18:
87 cpuclk = txx9_gbus_clock * 9 / 2; break;
88 }
89 txx9_cpu_clock = cpuclk;
90 } else {
91 if (txx9_cpu_clock == 0)
92 txx9_cpu_clock = 300000000; /* 300MHz */
93 /* calculate gbus_clock and master_clock from cpu_clock */
94 cpuclk = txx9_cpu_clock;
95 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
96 switch (divmode) {
97 case TX4938_CCFG_DIVMODE_2:
98 case TX4938_CCFG_DIVMODE_8:
99 txx9_gbus_clock = cpuclk / 2; break;
100 case TX4938_CCFG_DIVMODE_2_5:
101 case TX4938_CCFG_DIVMODE_10:
102 txx9_gbus_clock = cpuclk * 2 / 5; break;
103 case TX4938_CCFG_DIVMODE_3:
104 case TX4938_CCFG_DIVMODE_12:
105 txx9_gbus_clock = cpuclk / 3; break;
106 case TX4938_CCFG_DIVMODE_4:
107 case TX4938_CCFG_DIVMODE_16:
108 txx9_gbus_clock = cpuclk / 4; break;
109 case TX4938_CCFG_DIVMODE_4_5:
110 case TX4938_CCFG_DIVMODE_18:
111 txx9_gbus_clock = cpuclk * 2 / 9; break;
112 }
113 switch (divmode) {
114 case TX4938_CCFG_DIVMODE_8:
115 case TX4938_CCFG_DIVMODE_10:
116 case TX4938_CCFG_DIVMODE_12:
117 case TX4938_CCFG_DIVMODE_16:
118 case TX4938_CCFG_DIVMODE_18:
119 txx9_master_clock = txx9_gbus_clock / 4; break;
120 default:
121 txx9_master_clock = txx9_gbus_clock;
122 }
123 }
124 /* change default value to udelay/mdelay take reasonable time */
125 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
126
127 /* CCFG */
128 tx4938_wdr_init();
129 /* clear BusErrorOnWrite flag (W1C) */
130 tx4938_ccfg_set(TX4938_CCFG_BEOW);
131 /* enable Timeout BusError */
132 if (txx9_ccfg_toeon)
133 tx4938_ccfg_set(TX4938_CCFG_TOE);
134
135 /* DMA selection */
136 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
137
138 /* Use external clock for external arbiter */
139 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
140 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
141
142 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
143 txx9_pcode_str,
144 (cpuclk + 500000) / 1000000,
145 (txx9_master_clock + 500000) / 1000000,
146 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
147 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
148 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
149
150 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
151 for (i = 0; i < 4; i++) {
152 __u64 cr = TX4938_SDRAMC_CR(i);
153 unsigned long base, size;
154 if (!((__u32)cr & 0x00000400))
155 continue; /* disabled */
156 base = (unsigned long)(cr >> 49) << 21;
157 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
158 printk(" CR%d:%016llx", i, (unsigned long long)cr);
159 tx4938_sdram_resource[i].name = "SDRAM";
160 tx4938_sdram_resource[i].start = base;
161 tx4938_sdram_resource[i].end = base + size - 1;
162 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
163 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
164 }
165 printk(" TR:%09llx\n",
166 (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
167
168 /* SRAM */
169 if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
170 unsigned int size = TX4938_SRAM_SIZE;
171 tx4938_sram_resource.name = "SRAM";
172 tx4938_sram_resource.start =
173 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
174 & ~(size - 1);
175 tx4938_sram_resource.end =
176 tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1;
177 tx4938_sram_resource.flags = IORESOURCE_MEM;
178 request_resource(&iomem_resource, &tx4938_sram_resource);
179 }
180
181 /* TMR */
182 /* disable all timers */
183 for (i = 0; i < TX4938_NR_TMR; i++)
184 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
185
186 /* DMA */
187 for (i = 0; i < 2; i++)
188 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
189 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
190
191 /* PIO */
192 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
193 __raw_writel(0, &tx4938_pioptr->maskcpu);
194 __raw_writel(0, &tx4938_pioptr->maskext);
195
196 if (txx9_pcode == 0x4938) {
197 __u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
198 /* set PCIC1 reset */
199 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
200 if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) {
201 mdelay(1); /* at least 128 cpu clock */
202 /* clear PCIC1 reset */
203 txx9_clear64(&tx4938_ccfgptr->clkctr,
204 TX4938_CLKCTR_PCIC1RST);
205 } else {
206 printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
207 /* stop PCIC1 */
208 txx9_set64(&tx4938_ccfgptr->clkctr,
209 TX4938_CLKCTR_PCIC1CKD);
210 }
211 if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
212 printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
213 txx9_set64(&tx4938_ccfgptr->clkctr,
214 TX4938_CLKCTR_ETH0RST);
215 txx9_set64(&tx4938_ccfgptr->clkctr,
216 TX4938_CLKCTR_ETH0CKD);
217 }
218 if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
219 printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
220 txx9_set64(&tx4938_ccfgptr->clkctr,
221 TX4938_CLKCTR_ETH1RST);
222 txx9_set64(&tx4938_ccfgptr->clkctr,
223 TX4938_CLKCTR_ETH1CKD);
224 }
225 }
226}
227
228void __init tx4938_time_init(unsigned int tmrnr)
229{
230 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
231 txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL,
232 TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr),
233 TXX9_IMCLK);
234}
235
236void __init tx4938_setup_serial(void)
237{
238#ifdef CONFIG_SERIAL_TXX9
239 int i;
240 struct uart_port req;
241 unsigned int ch_mask = 0;
242
243 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
244 ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */
245 for (i = 0; i < 2; i++) {
246 if ((1 << i) & ch_mask)
247 continue;
248 memset(&req, 0, sizeof(req));
249 req.line = i;
250 req.iotype = UPIO_MEM;
251 req.membase = (unsigned char __iomem *)TX4938_SIO_REG(i);
252 req.mapbase = TX4938_SIO_REG(i) & 0xfffffffffULL;
253 req.irq = TXX9_IRQ_BASE + TX4938_IR_SIO(i);
254 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
255 req.uartclk = TXX9_IMCLK;
256 early_serial_txx9_setup(&req);
257 }
258#endif /* CONFIG_SERIAL_TXX9 */
259}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 04:25:15 -0500