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Diffstat (limited to 'arch/mips/txx9/generic/setup_tx4927.c')
-rw-r--r--arch/mips/txx9/generic/setup_tx4927.c194
1 files changed, 194 insertions, 0 deletions
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
new file mode 100644
index 000000000000..89d6e28add93
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -0,0 +1,194 @@
1/*
2 * TX4927 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
5 *
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/serial_core.h>
17#include <linux/param.h>
18#include <asm/txx9irq.h>
19#include <asm/txx9tmr.h>
20#include <asm/txx9pio.h>
21#include <asm/txx9/generic.h>
22#include <asm/txx9/tx4927.h>
23
24void __init tx4927_wdr_init(void)
25{
26 /* clear WatchDogReset (W1C) */
27 tx4927_ccfg_set(TX4927_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4927_ccfg_set(TX4927_CCFG_WR);
30}
31
32static struct resource tx4927_sdram_resource[4];
33
34void __init tx4927_setup(void)
35{
36 int i;
37 __u32 divmode;
38 int cpuclk = 0;
39 u64 ccfg;
40
41 txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,
42 TX4927_REG_SIZE);
43
44 /* SDRAMC,EBUSC are configured by PROM */
45 for (i = 0; i < 8; i++) {
46 if (!(TX4927_EBUSC_CR(i) & 0x8))
47 continue; /* disabled */
48 txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);
49 txx9_ce_res[i].end =
50 txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;
51 request_resource(&iomem_resource, &txx9_ce_res[i]);
52 }
53
54 /* clocks */
55 ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);
56 if (txx9_master_clock) {
57 /* calculate gbus_clock and cpu_clock from master_clock */
58 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
59 switch (divmode) {
60 case TX4927_CCFG_DIVMODE_8:
61 case TX4927_CCFG_DIVMODE_10:
62 case TX4927_CCFG_DIVMODE_12:
63 case TX4927_CCFG_DIVMODE_16:
64 txx9_gbus_clock = txx9_master_clock * 4; break;
65 default:
66 txx9_gbus_clock = txx9_master_clock;
67 }
68 switch (divmode) {
69 case TX4927_CCFG_DIVMODE_2:
70 case TX4927_CCFG_DIVMODE_8:
71 cpuclk = txx9_gbus_clock * 2; break;
72 case TX4927_CCFG_DIVMODE_2_5:
73 case TX4927_CCFG_DIVMODE_10:
74 cpuclk = txx9_gbus_clock * 5 / 2; break;
75 case TX4927_CCFG_DIVMODE_3:
76 case TX4927_CCFG_DIVMODE_12:
77 cpuclk = txx9_gbus_clock * 3; break;
78 case TX4927_CCFG_DIVMODE_4:
79 case TX4927_CCFG_DIVMODE_16:
80 cpuclk = txx9_gbus_clock * 4; break;
81 }
82 txx9_cpu_clock = cpuclk;
83 } else {
84 if (txx9_cpu_clock == 0)
85 txx9_cpu_clock = 200000000; /* 200MHz */
86 /* calculate gbus_clock and master_clock from cpu_clock */
87 cpuclk = txx9_cpu_clock;
88 divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;
89 switch (divmode) {
90 case TX4927_CCFG_DIVMODE_2:
91 case TX4927_CCFG_DIVMODE_8:
92 txx9_gbus_clock = cpuclk / 2; break;
93 case TX4927_CCFG_DIVMODE_2_5:
94 case TX4927_CCFG_DIVMODE_10:
95 txx9_gbus_clock = cpuclk * 2 / 5; break;
96 case TX4927_CCFG_DIVMODE_3:
97 case TX4927_CCFG_DIVMODE_12:
98 txx9_gbus_clock = cpuclk / 3; break;
99 case TX4927_CCFG_DIVMODE_4:
100 case TX4927_CCFG_DIVMODE_16:
101 txx9_gbus_clock = cpuclk / 4; break;
102 }
103 switch (divmode) {
104 case TX4927_CCFG_DIVMODE_8:
105 case TX4927_CCFG_DIVMODE_10:
106 case TX4927_CCFG_DIVMODE_12:
107 case TX4927_CCFG_DIVMODE_16:
108 txx9_master_clock = txx9_gbus_clock / 4; break;
109 default:
110 txx9_master_clock = txx9_gbus_clock;
111 }
112 }
113 /* change default value to udelay/mdelay take reasonable time */
114 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
115
116 /* CCFG */
117 tx4927_wdr_init();
118 /* clear BusErrorOnWrite flag (W1C) */
119 tx4927_ccfg_set(TX4927_CCFG_BEOW);
120 /* enable Timeout BusError */
121 if (txx9_ccfg_toeon)
122 tx4927_ccfg_set(TX4927_CCFG_TOE);
123
124 /* DMA selection */
125 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);
126
127 /* Use external clock for external arbiter */
128 if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
129 txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
130
131 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
132 txx9_pcode_str,
133 (cpuclk + 500000) / 1000000,
134 (txx9_master_clock + 500000) / 1000000,
135 (__u32)____raw_readq(&tx4927_ccfgptr->crir),
136 (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
137 (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
138
139 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
140 for (i = 0; i < 4; i++) {
141 __u64 cr = TX4927_SDRAMC_CR(i);
142 unsigned long base, size;
143 if (!((__u32)cr & 0x00000400))
144 continue; /* disabled */
145 base = (unsigned long)(cr >> 49) << 21;
146 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
147 printk(" CR%d:%016llx", i, (unsigned long long)cr);
148 tx4927_sdram_resource[i].name = "SDRAM";
149 tx4927_sdram_resource[i].start = base;
150 tx4927_sdram_resource[i].end = base + size - 1;
151 tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
152 request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
153 }
154 printk(" TR:%09llx\n",
155 (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
156
157 /* TMR */
158 /* disable all timers */
159 for (i = 0; i < TX4927_NR_TMR; i++)
160 txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);
161
162 /* PIO */
163 txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);
164 __raw_writel(0, &tx4927_pioptr->maskcpu);
165 __raw_writel(0, &tx4927_pioptr->maskext);
166}
167
168void __init tx4927_time_init(unsigned int tmrnr)
169{
170 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
171 txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,
172 TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),
173 TXX9_IMCLK);
174}
175
176void __init tx4927_setup_serial(void)
177{
178#ifdef CONFIG_SERIAL_TXX9
179 int i;
180 struct uart_port req;
181
182 for (i = 0; i < 2; i++) {
183 memset(&req, 0, sizeof(req));
184 req.line = i;
185 req.iotype = UPIO_MEM;
186 req.membase = (unsigned char __iomem *)TX4927_SIO_REG(i);
187 req.mapbase = TX4927_SIO_REG(i) & 0xfffffffffULL;
188 req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);
189 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
190 req.uartclk = TXX9_IMCLK;
191 early_serial_txx9_setup(&req);
192 }
193#endif /* CONFIG_SERIAL_TXX9 */
194}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 04:33:39 -0500