1 files changed, 15 insertions, 79 deletions
diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c
index 12dfc377bf2f..ef6ea6e97873 100644
--- a/arch/mips/txx9/generic/mem_tx4927.c
+++ b/arch/mips/txx9/generic/mem_tx4927.c
@@ -1,5 +1,5 @@
 /*
- * linux/arch/mips/tx4927/common/tx4927_prom.c
+ * linux/arch/mips/txx9/generic/mem_tx4927.c
 *
 * common tx4927 memory interface
 *
@@ -32,8 +32,9 @@
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/io.h>
+#include <asm/txx9/tx4927.h>
-static unsigned int __init tx4927_process_sdccr(unsigned long addr)
+static unsigned int __init tx4927_process_sdccr(u64 __iomem *addr)
 {
        u64 val;
        unsigned int sdccr_ce;
@@ -45,97 +46,32 @@ static unsigned int __init tx4927_process_sdccr(unsigned long addr)
        unsigned int rs = 0;
        unsigned int cs = 0;
        unsigned int mw = 0;
-        unsigned int msize = 0;
-        val = __raw_readq((void __iomem *)addr);
+        val = __raw_readq(addr);
        /* MVMCP -- need #defs for these bits masks */
        sdccr_ce = ((val & (1 << 10)) >> 10);
        sdccr_bs = ((val & (1 << 8)) >> 8);
        sdccr_rs = ((val & (3 << 5)) >> 5);
-        sdccr_cs = ((val & (3 << 2)) >> 2);
+        sdccr_cs = ((val & (7 << 2)) >> 2);
        sdccr_mw = ((val & (1 << 0)) >> 0);
        if (sdccr_ce) {
-                switch (sdccr_bs) {
+                bs = 2 << sdccr_bs;
-                case 0:{
+                rs = 2048 << sdccr_rs;
-                                bs = 2;
+                cs = 256 << sdccr_cs;
-                                break;
+                mw = 8 >> sdccr_mw;
-                        }
-                case 1:{
-                                bs = 4;
-                                break;
-                        }
-                }
-                switch (sdccr_rs) {
-                case 0:{
-                                rs = 2048;
-                                break;
-                        }
-                case 1:{
-                                rs = 4096;
-                                break;
-                        }
-                case 2:{
-                                rs = 8192;
-                                break;
-                        }
-                case 3:{
-                                rs = 0;
-                                break;
-                        }
-                }
-                switch (sdccr_cs) {
-                case 0:{
-                                cs = 256;
-                                break;
-                        }
-                case 1:{
-                                cs = 512;
-                                break;
-                        }
-                case 2:{
-                                cs = 1024;
-                                break;
-                        }
-                case 3:{
-                                cs = 2048;
-                                break;
-                        }
-                }
-                switch (sdccr_mw) {
-                case 0:{
-                                mw = 8;
-                                break;
-                        }       /* 8 bytes = 64 bits */
-                case 1:{
-                                mw = 4;
-                                break;
-                        }       /* 4 bytes = 32 bits */
-                }
        }
-        /*            bytes per chip     MB per chip      num chips */
+        return rs * cs * mw * bs;
-        msize = (((rs * cs * mw) / (1024 * 1024)) * bs);
-        return (msize);
 }
 unsigned int __init tx4927_get_mem_size(void)
 {
-        unsigned int c0;
+        unsigned int total = 0;
-        unsigned int c1;
+        int i;
-        unsigned int c2;
-        unsigned int c3;
-        unsigned int total;
-        /* MVMCP -- need #defs for these registers */
-        c0 = tx4927_process_sdccr(0xff1f8000);
-        c1 = tx4927_process_sdccr(0xff1f8008);
-        c2 = tx4927_process_sdccr(0xff1f8010);
-        c3 = tx4927_process_sdccr(0xff1f8018);
-        total = c0 + c1 + c2 + c3;
-        return (total);
+        for (i = 0; i < ARRAY_SIZE(tx4927_sdramcptr->cr); i++)
+                total += tx4927_process_sdccr(&tx4927_sdramcptr->cr[i]);
+        return total;
 }

diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c index 12dfc377bf2f..ef6ea6e97873 100644 --- a/arch/mips/txx9/generic/mem_tx4927.c +++ b/arch/mips/txx9/generic/mem_tx4927.c
@@ -1,5 +1,5 @@
1	/*	1	/*
2	* linux/arch/mips/tx4927/common/tx4927_prom.c	2	* linux/arch/mips/txx9/generic/mem_tx4927.c
3	*	3	*
4	* common tx4927 memory interface	4	* common tx4927 memory interface
5	*	5	*
@@ -32,8 +32,9 @@
32	#include <linux/init.h>	32	#include <linux/init.h>
33	#include <linux/types.h>	33	#include <linux/types.h>
34	#include <linux/io.h>	34	#include <linux/io.h>
		35	#include <asm/txx9/tx4927.h>
35		36
36	static unsigned int __init tx4927_process_sdccr(unsigned long addr)	37	static unsigned int __init tx4927_process_sdccr(u64 __iomem *addr)
37	{	38	{
38	u64 val;	39	u64 val;
39	unsigned int sdccr_ce;	40	unsigned int sdccr_ce;
@@ -45,97 +46,32 @@ static unsigned int __init tx4927_process_sdccr(unsigned long addr)
45	unsigned int rs = 0;	46	unsigned int rs = 0;
46	unsigned int cs = 0;	47	unsigned int cs = 0;
47	unsigned int mw = 0;	48	unsigned int mw = 0;
48	unsigned int msize = 0;
49		49
50	val = __raw_readq((void __iomem *)addr);	50	val = __raw_readq(addr);
51		51
52	/* MVMCP -- need #defs for these bits masks */	52	/* MVMCP -- need #defs for these bits masks */
53	sdccr_ce = ((val & (1 << 10)) >> 10);	53	sdccr_ce = ((val & (1 << 10)) >> 10);
54	sdccr_bs = ((val & (1 << 8)) >> 8);	54	sdccr_bs = ((val & (1 << 8)) >> 8);
55	sdccr_rs = ((val & (3 << 5)) >> 5);	55	sdccr_rs = ((val & (3 << 5)) >> 5);
56	sdccr_cs = ((val & (3 << 2)) >> 2);	56	sdccr_cs = ((val & (7 << 2)) >> 2);
57	sdccr_mw = ((val & (1 << 0)) >> 0);	57	sdccr_mw = ((val & (1 << 0)) >> 0);
58		58
59	if (sdccr_ce) {	59	if (sdccr_ce) {
60	switch (sdccr_bs) {	60	bs = 2 << sdccr_bs;
61	case 0:{	61	rs = 2048 << sdccr_rs;
62	bs = 2;	62	cs = 256 << sdccr_cs;
63	break;	63	mw = 8 >> sdccr_mw;
64	}
65	case 1:{
66	bs = 4;
67	break;
68	}
69	}
70	switch (sdccr_rs) {
71	case 0:{
72	rs = 2048;
73	break;
74	}
75	case 1:{
76	rs = 4096;
77	break;
78	}
79	case 2:{
80	rs = 8192;
81	break;
82	}
83	case 3:{
84	rs = 0;
85	break;
86	}
87	}
88	switch (sdccr_cs) {
89	case 0:{
90	cs = 256;
91	break;
92	}
93	case 1:{
94	cs = 512;
95	break;
96	}
97	case 2:{
98	cs = 1024;
99	break;
100	}
101	case 3:{
102	cs = 2048;
103	break;
104	}
105	}
106	switch (sdccr_mw) {
107	case 0:{
108	mw = 8;
109	break;
110	} /* 8 bytes = 64 bits */
111	case 1:{
112	mw = 4;
113	break;
114	} /* 4 bytes = 32 bits */
115	}
116	}	64	}
117		65
118	/* bytes per chip MB per chip num chips */	66	return rs * cs * mw * bs;
119	msize = (((rs * cs * mw) / (1024 * 1024)) * bs);
120
121	return (msize);
122	}	67	}
123		68
124
125	unsigned int __init tx4927_get_mem_size(void)	69	unsigned int __init tx4927_get_mem_size(void)
126	{	70	{
127	unsigned int c0;	71	unsigned int total = 0;
128	unsigned int c1;	72	int i;
129	unsigned int c2;
130	unsigned int c3;
131	unsigned int total;
132
133	/* MVMCP -- need #defs for these registers */
134	c0 = tx4927_process_sdccr(0xff1f8000);
135	c1 = tx4927_process_sdccr(0xff1f8008);
136	c2 = tx4927_process_sdccr(0xff1f8010);
137	c3 = tx4927_process_sdccr(0xff1f8018);
138	total = c0 + c1 + c2 + c3;
139		73
140	return (total);	74	for (i = 0; i < ARRAY_SIZE(tx4927_sdramcptr->cr); i++)
		75	total += tx4927_process_sdccr(&tx4927_sdramcptr->cr[i]);
		76	return total;
141	}	77	}