aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/tx4938/common/prom.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/tx4938/common/prom.c')
-rw-r--r--arch/mips/tx4938/common/prom.c129
1 files changed, 129 insertions, 0 deletions
diff --git a/arch/mips/tx4938/common/prom.c b/arch/mips/tx4938/common/prom.c
new file mode 100644
index 000000000000..3189a65f7d7e
--- /dev/null
+++ b/arch/mips/tx4938/common/prom.c
@@ -0,0 +1,129 @@
1/*
2 * linux/arch/mips/tx4938/common/prom.c
3 *
4 * common tx4938 memory interface
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/bootmem.h>
19
20#include <asm/addrspace.h>
21#include <asm/bootinfo.h>
22#include <asm/tx4938/tx4938.h>
23
24static unsigned int __init
25tx4938_process_sdccr(u64 * addr)
26{
27 u64 val;
28 unsigned int sdccr_ce;
29 unsigned int sdccr_rs;
30 unsigned int sdccr_cs;
31 unsigned int sdccr_mw;
32 unsigned int rs = 0;
33 unsigned int cs = 0;
34 unsigned int mw = 0;
35 unsigned int bc = 4;
36 unsigned int msize = 0;
37
38 val = (*((vu64 *) (addr)));
39
40 /* MVMCP -- need #defs for these bits masks */
41 sdccr_ce = ((val & (1 << 10)) >> 10);
42 sdccr_rs = ((val & (3 << 5)) >> 5);
43 sdccr_cs = ((val & (7 << 2)) >> 2);
44 sdccr_mw = ((val & (1 << 0)) >> 0);
45
46 if (sdccr_ce) {
47 switch (sdccr_rs) {
48 case 0:{
49 rs = 2048;
50 break;
51 }
52 case 1:{
53 rs = 4096;
54 break;
55 }
56 case 2:{
57 rs = 8192;
58 break;
59 }
60 default:{
61 rs = 0;
62 break;
63 }
64 }
65 switch (sdccr_cs) {
66 case 0:{
67 cs = 256;
68 break;
69 }
70 case 1:{
71 cs = 512;
72 break;
73 }
74 case 2:{
75 cs = 1024;
76 break;
77 }
78 case 3:{
79 cs = 2048;
80 break;
81 }
82 case 4:{
83 cs = 4096;
84 break;
85 }
86 default:{
87 cs = 0;
88 break;
89 }
90 }
91 switch (sdccr_mw) {
92 case 0:{
93 mw = 8;
94 break;
95 } /* 8 bytes = 64 bits */
96 case 1:{
97 mw = 4;
98 break;
99 } /* 4 bytes = 32 bits */
100 }
101 }
102
103 /* bytes per chip MB per chip bank count */
104 msize = (((rs * cs * mw) / (1024 * 1024)) * (bc));
105
106 /* MVMCP -- bc hard coded to 4 from table 9.3.1 */
107 /* boad supports bc=2 but no way to detect */
108
109 return (msize);
110}
111
112unsigned int __init
113tx4938_get_mem_size(void)
114{
115 unsigned int c0;
116 unsigned int c1;
117 unsigned int c2;
118 unsigned int c3;
119 unsigned int total;
120
121 /* MVMCP -- need #defs for these registers */
122 c0 = tx4938_process_sdccr((u64 *) 0xff1f8000);
123 c1 = tx4938_process_sdccr((u64 *) 0xff1f8008);
124 c2 = tx4938_process_sdccr((u64 *) 0xff1f8010);
125 c3 = tx4938_process_sdccr((u64 *) 0xff1f8018);
126 total = c0 + c1 + c2 + c3;
127
128 return (total);
129}