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-rw-r--r--arch/mips/sni/Makefile2
-rw-r--r--arch/mips/sni/int-handler.S106
-rw-r--r--arch/mips/sni/irq.c37
3 files changed, 28 insertions, 117 deletions
diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile
index 1e5676e4be86..9c7eaa5fb210 100644
--- a/arch/mips/sni/Makefile
+++ b/arch/mips/sni/Makefile
@@ -2,6 +2,6 @@
2# Makefile for the SNI specific part of the kernel 2# Makefile for the SNI specific part of the kernel
3# 3#
4 4
5obj-y += int-handler.o irq.o pcimt_scache.o reset.o setup.o 5obj-y += irq.o pcimt_scache.o reset.o setup.o
6 6
7EXTRA_AFLAGS := $(CFLAGS) 7EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/sni/int-handler.S b/arch/mips/sni/int-handler.S
deleted file mode 100644
index 2cdc09f55f18..000000000000
--- a/arch/mips/sni/int-handler.S
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * SNI RM200 PCI specific interrupt handler code.
3 *
4 * Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000, 01 by Ralf Baechle
5 */
6#include <asm/asm.h>
7#include <asm/mipsregs.h>
8#include <asm/regdef.h>
9#include <asm/sni.h>
10#include <asm/stackframe.h>
11
12/*
13 * The PCI ASIC has the nasty property that it may delay writes if it is busy.
14 * As a consequence from writes that have not graduated when we exit from the
15 * interrupt handler we might catch a spurious interrupt. To avoid this we
16 * force the PCI ASIC to graduate all writes by executing a read from the
17 * PCI bus.
18 */
19 .set noreorder
20 .set noat
21 .align 5
22 NESTED(sni_rm200_pci_handle_int, PT_SIZE, sp)
23 SAVE_ALL
24 CLI
25 .set at
26
27 /* Blinken light ... */
28 lb t0, led_cache
29 addiu t0, 1
30 sb t0, led_cache
31 sb t0, PCIMT_CSLED # write only register
32 .data
33led_cache: .byte 0
34 .text
35
36 mfc0 t0, CP0_STATUS
37 mfc0 t1, CP0_CAUSE
38 and t0, t1
39
40 andi t1, t0, 0x0800 # hardware interrupt 1
41 bnez t1, _hwint1
42 andi t1, t0, 0x4000 # hardware interrupt 4
43 bnez t1, _hwint4
44 andi t1, t0, 0x2000 # hardware interrupt 3
45 bnez t1, _hwint3
46 andi t1, t0, 0x1000 # hardware interrupt 2
47 bnez t1, _hwint2
48 andi t1, t0, 0x8000 # hardware interrupt 5
49 bnez t1, _hwint5
50 andi t1, t0, 0x0400 # hardware interrupt 0
51 bnez t1, _hwint0
52 nop
53
54 j restore_all # spurious interrupt
55 nop
56
57 ##############################################################################
58
59/* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
60 button interrupts. */
61_hwint0: jal pciasic_hwint0
62 move a0, sp
63 j ret_from_irq
64 nop
65
66/*
67 * hwint 1 deals with EISA and SCSI interrupts
68 */
69_hwint1: jal pciasic_hwint1
70 move a0, sp
71 j ret_from_irq
72 nop
73
74
75/*
76 * This interrupt was used for the com1 console on the first prototypes;
77 * it's unsed otherwise
78 */
79_hwint2: jal pciasic_hwint2
80 move a0, sp
81 j ret_from_irq
82 nop
83
84/*
85 * hwint 3 are the PCI interrupts A - D
86 */
87_hwint3: jal pciasic_hwint3
88 move a0, sp
89 j ret_from_irq
90 nop
91
92/*
93 * hwint 4 is used for only the onboard PCnet 32.
94 */
95_hwint4: jal pciasic_hwint4
96 move a0, sp
97 j ret_from_irq
98 nop
99
100/* hwint5 is the r4k count / compare interrupt */
101_hwint5: jal pciasic_hwint5
102 move a0, sp
103 j ret_from_irq
104 nop
105
106 END(sni_rm200_pci_handle_int)
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 952038aa4b90..7365b4853ddb 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -19,8 +19,6 @@
19 19
20DEFINE_SPINLOCK(pciasic_lock); 20DEFINE_SPINLOCK(pciasic_lock);
21 21
22extern asmlinkage void sni_rm200_pci_handle_int(void);
23
24static void enable_pciasic_irq(unsigned int irq) 22static void enable_pciasic_irq(unsigned int irq)
25{ 23{
26 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); 24 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
@@ -71,20 +69,20 @@ static struct hw_interrupt_type pciasic_irq_type = {
71 * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug 69 * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
72 * button interrupts. Later ... 70 * button interrupts. Later ...
73 */ 71 */
74void pciasic_hwint0(struct pt_regs *regs) 72static void pciasic_hwint0(struct pt_regs *regs)
75{ 73{
76 panic("Received int0 but no handler yet ..."); 74 panic("Received int0 but no handler yet ...");
77} 75}
78 76
79/* This interrupt was used for the com1 console on the first prototypes. */ 77/* This interrupt was used for the com1 console on the first prototypes. */
80void pciasic_hwint2(struct pt_regs *regs) 78static void pciasic_hwint2(struct pt_regs *regs)
81{ 79{
82 /* I think this shouldn't happen on production machines. */ 80 /* I think this shouldn't happen on production machines. */
83 panic("hwint2 and no handler yet"); 81 panic("hwint2 and no handler yet");
84} 82}
85 83
86/* hwint5 is the r4k count / compare interrupt */ 84/* hwint5 is the r4k count / compare interrupt */
87void pciasic_hwint5(struct pt_regs *regs) 85static void pciasic_hwint5(struct pt_regs *regs)
88{ 86{
89 panic("hwint5 and no handler yet"); 87 panic("hwint5 and no handler yet");
90} 88}
@@ -105,7 +103,7 @@ static unsigned int ls1bit8(unsigned int x)
105 * 103 *
106 * The EISA_INT bit in CSITPEND is high active, all others are low active. 104 * The EISA_INT bit in CSITPEND is high active, all others are low active.
107 */ 105 */
108void pciasic_hwint1(struct pt_regs *regs) 106static void pciasic_hwint1(struct pt_regs *regs)
109{ 107{
110 u8 pend = *(volatile char *)PCIMT_CSITPEND; 108 u8 pend = *(volatile char *)PCIMT_CSITPEND;
111 unsigned long flags; 109 unsigned long flags;
@@ -135,7 +133,7 @@ void pciasic_hwint1(struct pt_regs *regs)
135/* 133/*
136 * hwint 3 should deal with the PCI A - D interrupts, 134 * hwint 3 should deal with the PCI A - D interrupts,
137 */ 135 */
138void pciasic_hwint3(struct pt_regs *regs) 136static void pciasic_hwint3(struct pt_regs *regs)
139{ 137{
140 u8 pend = *(volatile char *)PCIMT_CSITPEND; 138 u8 pend = *(volatile char *)PCIMT_CSITPEND;
141 int irq; 139 int irq;
@@ -150,13 +148,34 @@ void pciasic_hwint3(struct pt_regs *regs)
150/* 148/*
151 * hwint 4 is used for only the onboard PCnet 32. 149 * hwint 4 is used for only the onboard PCnet 32.
152 */ 150 */
153void pciasic_hwint4(struct pt_regs *regs) 151static void pciasic_hwint4(struct pt_regs *regs)
154{ 152{
155 clear_c0_status(IE_IRQ4); 153 clear_c0_status(IE_IRQ4);
156 do_IRQ(PCIMT_IRQ_ETHERNET, regs); 154 do_IRQ(PCIMT_IRQ_ETHERNET, regs);
157 set_c0_status(IE_IRQ4); 155 set_c0_status(IE_IRQ4);
158} 156}
159 157
158asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
159{
160 unsigned int pending = read_c0_status() & read_c0_cause();
161 static unsigned char led_cache;
162
163 *(volatile unsigned char *) PCIMT_CSLED = ++led_cache;
164
165 if (pending & 0x0800)
166 pciasic_hwint1(regs);
167 else if (pending & 0x4000)
168 pciasic_hwint4(regs);
169 else if (pending & 0x2000)
170 pciasic_hwint3(regs);
171 else if (pending & 0x1000)
172 pciasic_hwint2(regs);
173 else if (pending & 0x8000)
174 pciasic_hwint5(regs);
175 else if (pending & 0x0400)
176 pciasic_hwint0(regs);
177}
178
160void __init init_pciasic(void) 179void __init init_pciasic(void)
161{ 180{
162 unsigned long flags; 181 unsigned long flags;
@@ -176,8 +195,6 @@ void __init arch_init_irq(void)
176{ 195{
177 int i; 196 int i;
178 197
179 set_except_vector(0, sni_rm200_pci_handle_int);
180
181 init_i8259_irqs(); /* Integrated i8259 */ 198 init_i8259_irqs(); /* Integrated i8259 */
182 init_pciasic(); 199 init_pciasic();
183 200
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 16:53:10 -0500